1 /******************************************************************************
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
8 * Copyright(c) 2007 - 2012 Intel Corporation. All rights reserved.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
24 * The full GNU General Public License is included in this distribution
25 * in the file called LICENSE.GPL.
27 * Contact Information:
28 * Intel Linux Wireless <ilw@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
33 * Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved.
34 * All rights reserved.
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37 * modification, are permitted provided that the following conditions
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
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43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
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48 * from this software without specific prior written permission.
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
62 *****************************************************************************/
63 #include <linux/pci.h>
64 #include <linux/pci-aspm.h>
65 #include <linux/interrupt.h>
66 #include <linux/debugfs.h>
67 #include <linux/sched.h>
68 #include <linux/bitops.h>
69 #include <linux/gfp.h>
71 #include "iwl-trans.h"
72 #include "iwl-trans-pcie-int.h"
75 #include "iwl-shared.h"
76 #include "iwl-eeprom.h"
77 #include "iwl-agn-hw.h"
79 #define IWL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo))))
81 #define SCD_QUEUECHAIN_SEL_ALL(trans, trans_pcie) \
82 (((1<<cfg(trans)->base_params->num_of_queues) - 1) &\
83 (~(1<<(trans_pcie)->cmd_queue)))
85 static int iwl_trans_rx_alloc(struct iwl_trans *trans)
87 struct iwl_trans_pcie *trans_pcie =
88 IWL_TRANS_GET_PCIE_TRANS(trans);
89 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
90 struct device *dev = trans->dev;
92 memset(&trans_pcie->rxq, 0, sizeof(trans_pcie->rxq));
94 spin_lock_init(&rxq->lock);
96 if (WARN_ON(rxq->bd || rxq->rb_stts))
99 /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */
100 rxq->bd = dma_zalloc_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
101 &rxq->bd_dma, GFP_KERNEL);
105 /*Allocate the driver's pointer to receive buffer status */
106 rxq->rb_stts = dma_zalloc_coherent(dev, sizeof(*rxq->rb_stts),
107 &rxq->rb_stts_dma, GFP_KERNEL);
114 dma_free_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
115 rxq->bd, rxq->bd_dma);
116 memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
122 static void iwl_trans_rxq_free_rx_bufs(struct iwl_trans *trans)
124 struct iwl_trans_pcie *trans_pcie =
125 IWL_TRANS_GET_PCIE_TRANS(trans);
126 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
129 /* Fill the rx_used queue with _all_ of the Rx buffers */
130 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
131 /* In the reset function, these buffers may have been allocated
132 * to an SKB, so we need to unmap and free potential storage */
133 if (rxq->pool[i].page != NULL) {
134 dma_unmap_page(trans->dev, rxq->pool[i].page_dma,
135 PAGE_SIZE << hw_params(trans).rx_page_order,
137 __free_pages(rxq->pool[i].page,
138 hw_params(trans).rx_page_order);
139 rxq->pool[i].page = NULL;
141 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
145 static void iwl_trans_rx_hw_init(struct iwl_trans *trans,
146 struct iwl_rx_queue *rxq)
149 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
150 u32 rb_timeout = RX_RB_TIMEOUT; /* FIXME: RX_RB_TIMEOUT for all devices? */
152 if (iwlagn_mod_params.amsdu_size_8K)
153 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
155 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
158 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
160 /* Reset driver's Rx queue write index */
161 iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
163 /* Tell device where to find RBD circular buffer in DRAM */
164 iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
165 (u32)(rxq->bd_dma >> 8));
167 /* Tell device where in DRAM to update its Rx status */
168 iwl_write_direct32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG,
169 rxq->rb_stts_dma >> 4);
172 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
173 * the credit mechanism in 5000 HW RX FIFO
174 * Direct rx interrupts to hosts
175 * Rx buffer size 4 or 8k
179 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG,
180 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
181 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
182 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
183 FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
185 (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
186 (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
188 /* Set interrupt coalescing timer to default (2048 usecs) */
189 iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
192 static int iwl_rx_init(struct iwl_trans *trans)
194 struct iwl_trans_pcie *trans_pcie =
195 IWL_TRANS_GET_PCIE_TRANS(trans);
196 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
202 err = iwl_trans_rx_alloc(trans);
207 spin_lock_irqsave(&rxq->lock, flags);
208 INIT_LIST_HEAD(&rxq->rx_free);
209 INIT_LIST_HEAD(&rxq->rx_used);
211 iwl_trans_rxq_free_rx_bufs(trans);
213 for (i = 0; i < RX_QUEUE_SIZE; i++)
214 rxq->queue[i] = NULL;
216 /* Set us so that we have processed and used all buffers, but have
217 * not restocked the Rx queue with fresh buffers */
218 rxq->read = rxq->write = 0;
219 rxq->write_actual = 0;
221 spin_unlock_irqrestore(&rxq->lock, flags);
223 iwlagn_rx_replenish(trans);
225 iwl_trans_rx_hw_init(trans, rxq);
227 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
228 rxq->need_update = 1;
229 iwl_rx_queue_update_write_ptr(trans, rxq);
230 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
235 static void iwl_trans_pcie_rx_free(struct iwl_trans *trans)
237 struct iwl_trans_pcie *trans_pcie =
238 IWL_TRANS_GET_PCIE_TRANS(trans);
239 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
243 /*if rxq->bd is NULL, it means that nothing has been allocated,
246 IWL_DEBUG_INFO(trans, "Free NULL rx context\n");
250 spin_lock_irqsave(&rxq->lock, flags);
251 iwl_trans_rxq_free_rx_bufs(trans);
252 spin_unlock_irqrestore(&rxq->lock, flags);
254 dma_free_coherent(trans->dev, sizeof(__le32) * RX_QUEUE_SIZE,
255 rxq->bd, rxq->bd_dma);
256 memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
260 dma_free_coherent(trans->dev,
261 sizeof(struct iwl_rb_status),
262 rxq->rb_stts, rxq->rb_stts_dma);
264 IWL_DEBUG_INFO(trans, "Free rxq->rb_stts which is NULL\n");
265 memset(&rxq->rb_stts_dma, 0, sizeof(rxq->rb_stts_dma));
269 static int iwl_trans_rx_stop(struct iwl_trans *trans)
273 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
274 return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG,
275 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
278 static inline int iwlagn_alloc_dma_ptr(struct iwl_trans *trans,
279 struct iwl_dma_ptr *ptr, size_t size)
281 if (WARN_ON(ptr->addr))
284 ptr->addr = dma_alloc_coherent(trans->dev, size,
285 &ptr->dma, GFP_KERNEL);
292 static inline void iwlagn_free_dma_ptr(struct iwl_trans *trans,
293 struct iwl_dma_ptr *ptr)
295 if (unlikely(!ptr->addr))
298 dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma);
299 memset(ptr, 0, sizeof(*ptr));
302 static int iwl_trans_txq_alloc(struct iwl_trans *trans,
303 struct iwl_tx_queue *txq, int slots_num,
306 size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX;
308 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
310 if (WARN_ON(txq->meta || txq->cmd || txq->skbs || txq->tfds))
313 txq->q.n_window = slots_num;
315 txq->meta = kcalloc(slots_num, sizeof(txq->meta[0]), GFP_KERNEL);
316 txq->cmd = kcalloc(slots_num, sizeof(txq->cmd[0]), GFP_KERNEL);
318 if (!txq->meta || !txq->cmd)
321 if (txq_id == trans_pcie->cmd_queue)
322 for (i = 0; i < slots_num; i++) {
323 txq->cmd[i] = kmalloc(sizeof(struct iwl_device_cmd),
329 /* Alloc driver data array and TFD circular buffer */
330 /* Driver private data, only for Tx (not command) queues,
331 * not shared with device. */
332 if (txq_id != trans_pcie->cmd_queue) {
333 txq->skbs = kcalloc(TFD_QUEUE_SIZE_MAX, sizeof(txq->skbs[0]),
336 IWL_ERR(trans, "kmalloc for auxiliary BD "
337 "structures failed\n");
344 /* Circular buffer of transmit frame descriptors (TFDs),
345 * shared with device */
346 txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz,
347 &txq->q.dma_addr, GFP_KERNEL);
349 IWL_ERR(trans, "dma_alloc_coherent(%zd) failed\n", tfd_sz);
358 /* since txq->cmd has been zeroed,
359 * all non allocated cmd[i] will be NULL */
360 if (txq->cmd && txq_id == trans_pcie->cmd_queue)
361 for (i = 0; i < slots_num; i++)
372 static int iwl_trans_txq_init(struct iwl_trans *trans, struct iwl_tx_queue *txq,
373 int slots_num, u32 txq_id)
377 txq->need_update = 0;
378 memset(txq->meta, 0, sizeof(txq->meta[0]) * slots_num);
381 * For the default queues 0-3, set up the swq_id
382 * already -- all others need to get one later
383 * (if they need one at all).
386 iwl_set_swq_id(txq, txq_id, txq_id);
388 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
389 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
390 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
392 /* Initialize queue's high/low-water marks, and head/tail indexes */
393 ret = iwl_queue_init(&txq->q, TFD_QUEUE_SIZE_MAX, slots_num,
398 spin_lock_init(&txq->lock);
401 * Tell nic where to find circular buffer of Tx Frame Descriptors for
402 * given Tx queue, and enable the DMA channel used for that queue.
403 * Circular buffer (TFD queue in DRAM) physical base address */
404 iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id),
405 txq->q.dma_addr >> 8);
411 * iwl_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's
413 static void iwl_tx_queue_unmap(struct iwl_trans *trans, int txq_id)
415 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
416 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
417 struct iwl_queue *q = &txq->q;
418 enum dma_data_direction dma_dir;
423 /* In the command queue, all the TBs are mapped as BIDI
424 * so unmap them as such.
426 if (txq_id == trans_pcie->cmd_queue)
427 dma_dir = DMA_BIDIRECTIONAL;
429 dma_dir = DMA_TO_DEVICE;
431 spin_lock_bh(&txq->lock);
432 while (q->write_ptr != q->read_ptr) {
433 /* The read_ptr needs to bound by q->n_window */
434 iwlagn_txq_free_tfd(trans, txq, get_cmd_index(q, q->read_ptr),
436 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
438 spin_unlock_bh(&txq->lock);
442 * iwl_tx_queue_free - Deallocate DMA queue.
443 * @txq: Transmit queue to deallocate.
445 * Empty queue by removing and destroying all BD's.
447 * 0-fill, but do not free "txq" descriptor structure.
449 static void iwl_tx_queue_free(struct iwl_trans *trans, int txq_id)
451 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
452 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
453 struct device *dev = trans->dev;
458 iwl_tx_queue_unmap(trans, txq_id);
460 /* De-alloc array of command/tx buffers */
462 if (txq_id == trans_pcie->cmd_queue)
463 for (i = 0; i < txq->q.n_window; i++)
466 /* De-alloc circular buffer of TFDs */
468 dma_free_coherent(dev, sizeof(struct iwl_tfd) *
469 txq->q.n_bd, txq->tfds, txq->q.dma_addr);
470 memset(&txq->q.dma_addr, 0, sizeof(txq->q.dma_addr));
473 /* De-alloc array of per-TFD driver data */
477 /* deallocate arrays */
483 /* 0-fill queue descriptor structure */
484 memset(txq, 0, sizeof(*txq));
488 * iwl_trans_tx_free - Free TXQ Context
490 * Destroy all TX DMA queues and structures
492 static void iwl_trans_pcie_tx_free(struct iwl_trans *trans)
495 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
498 if (trans_pcie->txq) {
500 txq_id < cfg(trans)->base_params->num_of_queues; txq_id++)
501 iwl_tx_queue_free(trans, txq_id);
504 kfree(trans_pcie->txq);
505 trans_pcie->txq = NULL;
507 iwlagn_free_dma_ptr(trans, &trans_pcie->kw);
509 iwlagn_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
513 * iwl_trans_tx_alloc - allocate TX context
514 * Allocate all Tx DMA structures and initialize them
519 static int iwl_trans_tx_alloc(struct iwl_trans *trans)
522 int txq_id, slots_num;
523 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
525 u16 scd_bc_tbls_size = cfg(trans)->base_params->num_of_queues *
526 sizeof(struct iwlagn_scd_bc_tbl);
528 /*It is not allowed to alloc twice, so warn when this happens.
529 * We cannot rely on the previous allocation, so free and fail */
530 if (WARN_ON(trans_pcie->txq)) {
535 ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
538 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
542 /* Alloc keep-warm buffer */
543 ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
545 IWL_ERR(trans, "Keep Warm allocation failed\n");
549 trans_pcie->txq = kcalloc(cfg(trans)->base_params->num_of_queues,
550 sizeof(struct iwl_tx_queue), GFP_KERNEL);
551 if (!trans_pcie->txq) {
552 IWL_ERR(trans, "Not enough memory for txq\n");
557 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
558 for (txq_id = 0; txq_id < cfg(trans)->base_params->num_of_queues;
560 slots_num = (txq_id == trans_pcie->cmd_queue) ?
561 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
562 ret = iwl_trans_txq_alloc(trans, &trans_pcie->txq[txq_id],
565 IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
573 iwl_trans_pcie_tx_free(trans);
577 static int iwl_tx_init(struct iwl_trans *trans)
580 int txq_id, slots_num;
583 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
585 if (!trans_pcie->txq) {
586 ret = iwl_trans_tx_alloc(trans);
592 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
594 /* Turn off all Tx DMA fifos */
595 iwl_write_prph(trans, SCD_TXFACT, 0);
597 /* Tell NIC where to find the "keep warm" buffer */
598 iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
599 trans_pcie->kw.dma >> 4);
601 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
603 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
604 for (txq_id = 0; txq_id < cfg(trans)->base_params->num_of_queues;
606 slots_num = (txq_id == trans_pcie->cmd_queue) ?
607 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
608 ret = iwl_trans_txq_init(trans, &trans_pcie->txq[txq_id],
611 IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
618 /*Upon error, free only if we allocated something */
620 iwl_trans_pcie_tx_free(trans);
624 static void iwl_set_pwr_vmain(struct iwl_trans *trans)
627 * (for documentation purposes)
628 * to set power to V_AUX, do:
630 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
631 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
632 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
633 ~APMG_PS_CTRL_MSK_PWR_SRC);
636 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
637 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
638 ~APMG_PS_CTRL_MSK_PWR_SRC);
642 #define PCI_CFG_RETRY_TIMEOUT 0x041
643 #define PCI_CFG_LINK_CTRL_VAL_L0S_EN 0x01
644 #define PCI_CFG_LINK_CTRL_VAL_L1_EN 0x02
646 static u16 iwl_pciexp_link_ctrl(struct iwl_trans *trans)
650 struct iwl_trans_pcie *trans_pcie =
651 IWL_TRANS_GET_PCIE_TRANS(trans);
653 struct pci_dev *pci_dev = trans_pcie->pci_dev;
655 pos = pci_pcie_cap(pci_dev);
656 pci_read_config_word(pci_dev, pos + PCI_EXP_LNKCTL, &pci_lnk_ctl);
660 static void iwl_apm_config(struct iwl_trans *trans)
663 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
664 * Check if BIOS (or OS) enabled L1-ASPM on this device.
665 * If so (likely), disable L0S, so device moves directly L0->L1;
666 * costs negligible amount of power savings.
667 * If not (unlikely), enable L0S, so there is at least some
668 * power savings, even without L1.
670 u16 lctl = iwl_pciexp_link_ctrl(trans);
672 if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
673 PCI_CFG_LINK_CTRL_VAL_L1_EN) {
674 /* L1-ASPM enabled; disable(!) L0S */
675 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
676 dev_printk(KERN_INFO, trans->dev,
677 "L1 Enabled; Disabling L0S\n");
679 /* L1-ASPM disabled; enable(!) L0S */
680 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
681 dev_printk(KERN_INFO, trans->dev,
682 "L1 Disabled; Enabling L0S\n");
684 trans->pm_support = !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN);
688 * Start up NIC's basic functionality after it has been reset
689 * (e.g. after platform boot, or shutdown via iwl_apm_stop())
690 * NOTE: This does not load uCode nor start the embedded processor
692 static int iwl_apm_init(struct iwl_trans *trans)
694 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
696 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
699 * Use "set_bit" below rather than "write", to preserve any hardware
700 * bits already set by default after reset.
703 /* Disable L0S exit timer (platform NMI Work/Around) */
704 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
705 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
708 * Disable L0s without affecting L1;
709 * don't wait for ICH L0s (ICH bug W/A)
711 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
712 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
714 /* Set FH wait threshold to maximum (HW error during stress W/A) */
715 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
718 * Enable HAP INTA (interrupt from management bus) to
719 * wake device's PCI Express link L1a -> L0s
721 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
722 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
724 iwl_apm_config(trans);
726 /* Configure analog phase-lock-loop before activating to D0A */
727 if (cfg(trans)->base_params->pll_cfg_val)
728 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
729 cfg(trans)->base_params->pll_cfg_val);
732 * Set "initialization complete" bit to move adapter from
733 * D0U* --> D0A* (powered-up active) state.
735 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
738 * Wait for clock stabilization; once stabilized, access to
739 * device-internal resources is supported, e.g. iwl_write_prph()
740 * and accesses to uCode SRAM.
742 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
743 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
744 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
746 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
751 * Enable DMA clock and wait for it to stabilize.
753 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
754 * do not disable clocks. This preserves any hardware bits already
755 * set by default in "CLK_CTRL_REG" after reset.
757 iwl_write_prph(trans, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
760 /* Disable L1-Active */
761 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
762 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
764 set_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
770 static int iwl_apm_stop_master(struct iwl_trans *trans)
774 /* stop device's busmaster DMA activity */
775 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
777 ret = iwl_poll_bit(trans, CSR_RESET,
778 CSR_RESET_REG_FLAG_MASTER_DISABLED,
779 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
781 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
783 IWL_DEBUG_INFO(trans, "stop master\n");
788 static void iwl_apm_stop(struct iwl_trans *trans)
790 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
791 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
793 clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
795 /* Stop device's DMA activity */
796 iwl_apm_stop_master(trans);
798 /* Reset the entire device */
799 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
804 * Clear "initialization complete" bit to move adapter from
805 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
807 iwl_clear_bit(trans, CSR_GP_CNTRL,
808 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
811 static int iwl_nic_init(struct iwl_trans *trans)
813 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
817 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
820 /* Set interrupt coalescing calibration timer to default (512 usecs) */
821 iwl_write8(trans, CSR_INT_COALESCING,
822 IWL_HOST_INT_CALIB_TIMEOUT_DEF);
824 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
826 iwl_set_pwr_vmain(trans);
828 iwl_op_mode_nic_config(trans->op_mode);
830 #ifndef CONFIG_IWLWIFI_IDI
831 /* Allocate the RX queue, or reset if it is already allocated */
835 /* Allocate or reset and init all Tx and Command queues */
836 if (iwl_tx_init(trans))
839 if (cfg(trans)->base_params->shadow_reg_enable) {
840 /* enable shadow regs in HW */
841 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL,
848 #define HW_READY_TIMEOUT (50)
850 /* Note: returns poll_bit return value, which is >= 0 if success */
851 static int iwl_set_hw_ready(struct iwl_trans *trans)
855 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
856 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
858 /* See if we got it */
859 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
860 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
861 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
864 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
868 /* Note: returns standard 0/-ERROR code */
869 static int iwl_prepare_card_hw(struct iwl_trans *trans)
873 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
875 ret = iwl_set_hw_ready(trans);
876 /* If the card is ready, exit 0 */
880 /* If HW is not ready, prepare the conditions to check again */
881 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
882 CSR_HW_IF_CONFIG_REG_PREPARE);
884 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
885 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
886 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
891 /* HW should be ready by now, check again. */
892 ret = iwl_set_hw_ready(trans);
898 #define IWL_AC_UNSET -1
900 struct queue_to_fifo_ac {
904 static const struct queue_to_fifo_ac iwlagn_default_queue_to_tx_fifo[] = {
905 { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
906 { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
907 { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
908 { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
909 { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
910 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
911 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
912 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
913 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
914 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
915 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
918 static const struct queue_to_fifo_ac iwlagn_ipan_queue_to_tx_fifo[] = {
919 { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
920 { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
921 { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
922 { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
923 { IWL_TX_FIFO_BK_IPAN, IEEE80211_AC_BK, },
924 { IWL_TX_FIFO_BE_IPAN, IEEE80211_AC_BE, },
925 { IWL_TX_FIFO_VI_IPAN, IEEE80211_AC_VI, },
926 { IWL_TX_FIFO_VO_IPAN, IEEE80211_AC_VO, },
927 { IWL_TX_FIFO_BE_IPAN, 2, },
928 { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
929 { IWL_TX_FIFO_AUX, IWL_AC_UNSET, },
932 static const u8 iwlagn_bss_ac_to_fifo[] = {
938 static const u8 iwlagn_bss_ac_to_queue[] = {
941 static const u8 iwlagn_pan_ac_to_fifo[] = {
947 static const u8 iwlagn_pan_ac_to_queue[] = {
954 static int iwl_load_section(struct iwl_trans *trans, u8 section_num,
955 const struct fw_desc *section)
957 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
958 dma_addr_t phy_addr = section->p_addr;
959 u32 byte_cnt = section->len;
960 u32 dst_addr = section->offset;
963 trans_pcie->ucode_write_complete = false;
965 iwl_write_direct32(trans,
966 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
967 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
969 iwl_write_direct32(trans,
970 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
972 iwl_write_direct32(trans,
973 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
974 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
976 iwl_write_direct32(trans,
977 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
978 (iwl_get_dma_hi_addr(phy_addr)
979 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
981 iwl_write_direct32(trans,
982 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
983 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
984 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
985 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
987 iwl_write_direct32(trans,
988 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
989 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
990 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
991 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
993 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
995 ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
996 trans_pcie->ucode_write_complete, 5 * HZ);
998 IWL_ERR(trans, "Could not load the [%d] uCode section\n",
1006 static int iwl_load_given_ucode(struct iwl_trans *trans,
1007 const struct fw_img *image)
1012 for (i = 0; i < IWL_UCODE_SECTION_MAX; i++) {
1013 if (!image->sec[i].p_addr)
1016 ret = iwl_load_section(trans, i, &image->sec[i]);
1021 /* Remove all resets to allow NIC to operate */
1022 iwl_write32(trans, CSR_RESET, 0);
1027 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
1028 const struct fw_img *fw)
1031 struct iwl_trans_pcie *trans_pcie =
1032 IWL_TRANS_GET_PCIE_TRANS(trans);
1035 trans_pcie->ac_to_queue[IWL_RXON_CTX_BSS] = iwlagn_bss_ac_to_queue;
1036 trans_pcie->ac_to_queue[IWL_RXON_CTX_PAN] = iwlagn_pan_ac_to_queue;
1038 trans_pcie->ac_to_fifo[IWL_RXON_CTX_BSS] = iwlagn_bss_ac_to_fifo;
1039 trans_pcie->ac_to_fifo[IWL_RXON_CTX_PAN] = iwlagn_pan_ac_to_fifo;
1041 trans_pcie->mcast_queue[IWL_RXON_CTX_BSS] = 0;
1042 trans_pcie->mcast_queue[IWL_RXON_CTX_PAN] = IWL_IPAN_MCAST_QUEUE;
1044 /* This may fail if AMT took ownership of the device */
1045 if (iwl_prepare_card_hw(trans)) {
1046 IWL_WARN(trans, "Exit HW not ready\n");
1050 /* If platform's RF_KILL switch is NOT set to KILL */
1051 hw_rfkill = !(iwl_read32(trans, CSR_GP_CNTRL) &
1052 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
1053 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1056 iwl_enable_rfkill_int(trans);
1060 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1062 ret = iwl_nic_init(trans);
1064 IWL_ERR(trans, "Unable to init nic\n");
1068 /* make sure rfkill handshake bits are cleared */
1069 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1070 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1071 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1073 /* clear (again), then enable host interrupts */
1074 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1075 iwl_enable_interrupts(trans);
1077 /* really make sure rfkill handshake bits are cleared */
1078 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1079 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1081 /* Load the given image to the HW */
1082 return iwl_load_given_ucode(trans, fw);
1086 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
1087 * must be called under the irq lock and with MAC access
1089 static void iwl_trans_txq_set_sched(struct iwl_trans *trans, u32 mask)
1091 struct iwl_trans_pcie __maybe_unused *trans_pcie =
1092 IWL_TRANS_GET_PCIE_TRANS(trans);
1094 lockdep_assert_held(&trans_pcie->irq_lock);
1096 iwl_write_prph(trans, SCD_TXFACT, mask);
1099 static void iwl_tx_start(struct iwl_trans *trans)
1101 const struct queue_to_fifo_ac *queue_to_fifo;
1102 struct iwl_trans_pcie *trans_pcie =
1103 IWL_TRANS_GET_PCIE_TRANS(trans);
1105 unsigned long flags;
1109 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1111 trans_pcie->scd_base_addr =
1112 iwl_read_prph(trans, SCD_SRAM_BASE_ADDR);
1113 a = trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_LOWER_BOUND;
1114 /* reset conext data memory */
1115 for (; a < trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_UPPER_BOUND;
1117 iwl_write_targ_mem(trans, a, 0);
1118 /* reset tx status memory */
1119 for (; a < trans_pcie->scd_base_addr + SCD_TX_STTS_MEM_UPPER_BOUND;
1121 iwl_write_targ_mem(trans, a, 0);
1122 for (; a < trans_pcie->scd_base_addr +
1123 SCD_TRANS_TBL_OFFSET_QUEUE(
1124 cfg(trans)->base_params->num_of_queues);
1126 iwl_write_targ_mem(trans, a, 0);
1128 iwl_write_prph(trans, SCD_DRAM_BASE_ADDR,
1129 trans_pcie->scd_bc_tbls.dma >> 10);
1131 /* Enable DMA channel */
1132 for (chan = 0; chan < FH_TCSR_CHNL_NUM ; chan++)
1133 iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
1134 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
1135 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
1137 /* Update FH chicken bits */
1138 reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG);
1139 iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG,
1140 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
1142 iwl_write_prph(trans, SCD_QUEUECHAIN_SEL,
1143 SCD_QUEUECHAIN_SEL_ALL(trans, trans_pcie));
1144 iwl_write_prph(trans, SCD_AGGR_SEL, 0);
1146 /* initiate the queues */
1147 for (i = 0; i < cfg(trans)->base_params->num_of_queues; i++) {
1148 iwl_write_prph(trans, SCD_QUEUE_RDPTR(i), 0);
1149 iwl_write_direct32(trans, HBUS_TARG_WRPTR, 0 | (i << 8));
1150 iwl_write_targ_mem(trans, trans_pcie->scd_base_addr +
1151 SCD_CONTEXT_QUEUE_OFFSET(i), 0);
1152 iwl_write_targ_mem(trans, trans_pcie->scd_base_addr +
1153 SCD_CONTEXT_QUEUE_OFFSET(i) +
1156 SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1157 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1158 ((SCD_FRAME_LIMIT <<
1159 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1160 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1163 iwl_write_prph(trans, SCD_INTERRUPT_MASK,
1164 IWL_MASK(0, cfg(trans)->base_params->num_of_queues));
1166 /* Activate all Tx DMA/FIFO channels */
1167 iwl_trans_txq_set_sched(trans, IWL_MASK(0, 7));
1169 /* map queues to FIFOs */
1170 if (trans->shrd->valid_contexts != BIT(IWL_RXON_CTX_BSS))
1171 queue_to_fifo = iwlagn_ipan_queue_to_tx_fifo;
1173 queue_to_fifo = iwlagn_default_queue_to_tx_fifo;
1175 iwl_trans_set_wr_ptrs(trans, trans_pcie->cmd_queue, 0);
1177 /* make sure all queue are not stopped */
1178 memset(&trans_pcie->queue_stopped[0], 0,
1179 sizeof(trans_pcie->queue_stopped));
1180 for (i = 0; i < 4; i++)
1181 atomic_set(&trans_pcie->queue_stop_count[i], 0);
1183 /* reset to 0 to enable all the queue first */
1184 trans_pcie->txq_ctx_active_msk = 0;
1186 BUILD_BUG_ON(ARRAY_SIZE(iwlagn_default_queue_to_tx_fifo) <
1187 IWLAGN_FIRST_AMPDU_QUEUE);
1188 BUILD_BUG_ON(ARRAY_SIZE(iwlagn_ipan_queue_to_tx_fifo) <
1189 IWLAGN_FIRST_AMPDU_QUEUE);
1191 for (i = 0; i < IWLAGN_FIRST_AMPDU_QUEUE; i++) {
1192 int fifo = queue_to_fifo[i].fifo;
1193 int ac = queue_to_fifo[i].ac;
1195 iwl_txq_ctx_activate(trans_pcie, i);
1197 if (fifo == IWL_TX_FIFO_UNUSED)
1200 if (ac != IWL_AC_UNSET)
1201 iwl_set_swq_id(&trans_pcie->txq[i], ac, i);
1202 iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[i],
1206 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1208 /* Enable L1-Active */
1209 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
1210 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1213 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans)
1215 iwl_reset_ict(trans);
1216 iwl_tx_start(trans);
1220 * iwlagn_txq_ctx_stop - Stop all Tx DMA channels
1222 static int iwl_trans_tx_stop(struct iwl_trans *trans)
1224 int ch, txq_id, ret;
1225 unsigned long flags;
1226 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1228 /* Turn off all Tx DMA fifos */
1229 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1231 iwl_trans_txq_set_sched(trans, 0);
1233 /* Stop each Tx DMA channel, and wait for it to be idle */
1234 for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
1235 iwl_write_direct32(trans,
1236 FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
1237 ret = iwl_poll_direct_bit(trans, FH_TSSR_TX_STATUS_REG,
1238 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
1241 IWL_ERR(trans, "Failing on timeout while stopping"
1242 " DMA channel %d [0x%08x]", ch,
1243 iwl_read_direct32(trans,
1244 FH_TSSR_TX_STATUS_REG));
1246 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1248 if (!trans_pcie->txq) {
1249 IWL_WARN(trans, "Stopping tx queues that aren't allocated...");
1253 /* Unmap DMA from host system and free skb's */
1254 for (txq_id = 0; txq_id < cfg(trans)->base_params->num_of_queues;
1256 iwl_tx_queue_unmap(trans, txq_id);
1261 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
1263 unsigned long flags;
1264 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1266 /* tell the device to stop sending interrupts */
1267 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1268 iwl_disable_interrupts(trans);
1269 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1271 /* device going down, Stop using ICT table */
1272 iwl_disable_ict(trans);
1275 * If a HW restart happens during firmware loading,
1276 * then the firmware loading might call this function
1277 * and later it might be called again due to the
1278 * restart. So don't process again if the device is
1281 if (test_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status)) {
1282 iwl_trans_tx_stop(trans);
1283 #ifndef CONFIG_IWLWIFI_IDI
1284 iwl_trans_rx_stop(trans);
1286 /* Power-down device's busmaster DMA clocks */
1287 iwl_write_prph(trans, APMG_CLK_DIS_REG,
1288 APMG_CLK_VAL_DMA_CLK_RQT);
1292 /* Make sure (redundant) we've released our request to stay awake */
1293 iwl_clear_bit(trans, CSR_GP_CNTRL,
1294 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1296 /* Stop the device, and put it in low power state */
1297 iwl_apm_stop(trans);
1299 /* Upon stop, the APM issues an interrupt if HW RF kill is set.
1300 * Clean again the interrupt here
1302 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1303 iwl_disable_interrupts(trans);
1304 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1306 /* wait to make sure we flush pending tasklet*/
1307 synchronize_irq(trans_pcie->irq);
1308 tasklet_kill(&trans_pcie->irq_tasklet);
1310 cancel_work_sync(&trans_pcie->rx_replenish);
1312 /* stop and reset the on-board processor */
1313 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
1316 static void iwl_trans_pcie_wowlan_suspend(struct iwl_trans *trans)
1318 /* let the ucode operate on its own */
1319 iwl_write32(trans, CSR_UCODE_DRV_GP1_SET,
1320 CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE);
1322 iwl_disable_interrupts(trans);
1323 iwl_clear_bit(trans, CSR_GP_CNTRL,
1324 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1327 static int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
1328 struct iwl_device_cmd *dev_cmd, enum iwl_rxon_context_id ctx,
1331 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1332 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1333 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1334 struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *) dev_cmd->payload;
1335 struct iwl_cmd_meta *out_meta;
1336 struct iwl_tx_queue *txq;
1337 struct iwl_queue *q;
1339 dma_addr_t phys_addr = 0;
1340 dma_addr_t txcmd_phys;
1341 dma_addr_t scratch_phys;
1342 u16 len, firstlen, secondlen;
1343 u8 wait_write_ptr = 0;
1345 bool is_agg = false;
1346 __le16 fc = hdr->frame_control;
1347 u8 hdr_len = ieee80211_hdrlen(fc);
1348 u16 __maybe_unused wifi_seq;
1351 * Send this frame after DTIM -- there's a special queue
1352 * reserved for this for contexts that support AP mode.
1354 if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
1355 txq_id = trans_pcie->mcast_queue[ctx];
1358 * The microcode will clear the more data
1359 * bit in the last frame it transmits.
1361 hdr->frame_control |=
1362 cpu_to_le16(IEEE80211_FCTL_MOREDATA);
1363 } else if (info->flags & IEEE80211_TX_CTL_TX_OFFCHAN)
1364 txq_id = IWL_AUX_QUEUE;
1367 trans_pcie->ac_to_queue[ctx][skb_get_queue_mapping(skb)];
1369 /* aggregation is on for this <sta,tid> */
1370 if (info->flags & IEEE80211_TX_CTL_AMPDU) {
1371 WARN_ON(tid >= IWL_MAX_TID_COUNT);
1372 txq_id = trans_pcie->agg_txq[sta_id][tid];
1376 txq = &trans_pcie->txq[txq_id];
1379 spin_lock(&txq->lock);
1381 /* In AGG mode, the index in the ring must correspond to the WiFi
1382 * sequence number. This is a HW requirements to help the SCD to parse
1384 * Check here that the packets are in the right place on the ring.
1386 #ifdef CONFIG_IWLWIFI_DEBUG
1387 wifi_seq = SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
1388 WARN_ONCE(is_agg && ((wifi_seq & 0xff) != q->write_ptr),
1389 "Q: %d WiFi Seq %d tfdNum %d",
1390 txq_id, wifi_seq, q->write_ptr);
1393 /* Set up driver data for this TFD */
1394 txq->skbs[q->write_ptr] = skb;
1395 txq->cmd[q->write_ptr] = dev_cmd;
1397 dev_cmd->hdr.cmd = REPLY_TX;
1398 dev_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
1399 INDEX_TO_SEQ(q->write_ptr)));
1401 /* Set up first empty entry in queue's array of Tx/cmd buffers */
1402 out_meta = &txq->meta[q->write_ptr];
1405 * Use the first empty entry in this queue's command buffer array
1406 * to contain the Tx command and MAC header concatenated together
1407 * (payload data will be in another buffer).
1408 * Size of this varies, due to varying MAC header length.
1409 * If end is not dword aligned, we'll have 2 extra bytes at the end
1410 * of the MAC header (device reads on dword boundaries).
1411 * We'll tell device about this padding later.
1413 len = sizeof(struct iwl_tx_cmd) +
1414 sizeof(struct iwl_cmd_header) + hdr_len;
1415 firstlen = (len + 3) & ~3;
1417 /* Tell NIC about any 2-byte padding after MAC header */
1418 if (firstlen != len)
1419 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1421 /* Physical address of this Tx command's header (not MAC header!),
1422 * within command buffer array. */
1423 txcmd_phys = dma_map_single(trans->dev,
1424 &dev_cmd->hdr, firstlen,
1426 if (unlikely(dma_mapping_error(trans->dev, txcmd_phys)))
1428 dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
1429 dma_unmap_len_set(out_meta, len, firstlen);
1431 if (!ieee80211_has_morefrags(fc)) {
1432 txq->need_update = 1;
1435 txq->need_update = 0;
1438 /* Set up TFD's 2nd entry to point directly to remainder of skb,
1439 * if any (802.11 null frames have no payload). */
1440 secondlen = skb->len - hdr_len;
1441 if (secondlen > 0) {
1442 phys_addr = dma_map_single(trans->dev, skb->data + hdr_len,
1443 secondlen, DMA_TO_DEVICE);
1444 if (unlikely(dma_mapping_error(trans->dev, phys_addr))) {
1445 dma_unmap_single(trans->dev,
1446 dma_unmap_addr(out_meta, mapping),
1447 dma_unmap_len(out_meta, len),
1453 /* Attach buffers to TFD */
1454 iwlagn_txq_attach_buf_to_tfd(trans, txq, txcmd_phys, firstlen, 1);
1456 iwlagn_txq_attach_buf_to_tfd(trans, txq, phys_addr,
1459 scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
1460 offsetof(struct iwl_tx_cmd, scratch);
1462 /* take back ownership of DMA buffer to enable update */
1463 dma_sync_single_for_cpu(trans->dev, txcmd_phys, firstlen,
1465 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1466 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
1468 IWL_DEBUG_TX(trans, "sequence nr = 0X%x\n",
1469 le16_to_cpu(dev_cmd->hdr.sequence));
1470 IWL_DEBUG_TX(trans, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
1472 /* Set up entry for this TFD in Tx byte-count array */
1473 iwl_trans_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len));
1475 dma_sync_single_for_device(trans->dev, txcmd_phys, firstlen,
1478 trace_iwlwifi_dev_tx(trans->dev,
1479 &((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr],
1480 sizeof(struct iwl_tfd),
1481 &dev_cmd->hdr, firstlen,
1482 skb->data + hdr_len, secondlen);
1484 /* Tell device the write index *just past* this latest filled TFD */
1485 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1486 iwl_txq_update_write_ptr(trans, txq);
1489 * At this point the frame is "transmitted" successfully
1490 * and we will get a TX status notification eventually,
1491 * regardless of the value of ret. "ret" only indicates
1492 * whether or not we should update the write pointer.
1494 if (iwl_queue_space(q) < q->high_mark) {
1495 if (wait_write_ptr) {
1496 txq->need_update = 1;
1497 iwl_txq_update_write_ptr(trans, txq);
1499 iwl_stop_queue(trans, txq);
1502 spin_unlock(&txq->lock);
1505 spin_unlock(&txq->lock);
1509 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
1511 struct iwl_trans_pcie *trans_pcie =
1512 IWL_TRANS_GET_PCIE_TRANS(trans);
1516 trans_pcie->inta_mask = CSR_INI_SET_MASK;
1518 if (!trans_pcie->irq_requested) {
1519 tasklet_init(&trans_pcie->irq_tasklet, (void (*)(unsigned long))
1520 iwl_irq_tasklet, (unsigned long)trans);
1522 iwl_alloc_isr_ict(trans);
1524 err = request_irq(trans_pcie->irq, iwl_isr_ict, IRQF_SHARED,
1527 IWL_ERR(trans, "Error allocating IRQ %d\n",
1532 INIT_WORK(&trans_pcie->rx_replenish, iwl_bg_rx_replenish);
1533 trans_pcie->irq_requested = true;
1536 err = iwl_prepare_card_hw(trans);
1538 IWL_ERR(trans, "Error while preparing HW: %d", err);
1542 iwl_apm_init(trans);
1544 hw_rfkill = !(iwl_read32(trans, CSR_GP_CNTRL) &
1545 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
1546 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1551 free_irq(trans_pcie->irq, trans);
1553 iwl_free_isr_ict(trans);
1554 tasklet_kill(&trans_pcie->irq_tasklet);
1558 static void iwl_trans_pcie_stop_hw(struct iwl_trans *trans)
1560 iwl_apm_stop(trans);
1562 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1564 /* Even if we stop the HW, we still want the RF kill interrupt */
1565 iwl_enable_rfkill_int(trans);
1568 static int iwl_trans_pcie_reclaim(struct iwl_trans *trans, int sta_id, int tid,
1569 int txq_id, int ssn, struct sk_buff_head *skbs)
1571 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1572 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
1573 /* n_bd is usually 256 => n_bd - 1 = 0xff */
1574 int tfd_num = ssn & (txq->q.n_bd - 1);
1577 spin_lock(&txq->lock);
1579 txq->time_stamp = jiffies;
1581 if (unlikely(txq_id >= IWLAGN_FIRST_AMPDU_QUEUE &&
1582 tid != IWL_TID_NON_QOS &&
1583 txq_id != trans_pcie->agg_txq[sta_id][tid])) {
1585 * FIXME: this is a uCode bug which need to be addressed,
1586 * log the information and return for now.
1587 * Since it is can possibly happen very often and in order
1588 * not to fill the syslog, don't use IWL_ERR or IWL_WARN
1590 IWL_DEBUG_TX_QUEUES(trans, "Bad queue mapping txq_id %d, "
1591 "agg_txq[sta_id[tid] %d", txq_id,
1592 trans_pcie->agg_txq[sta_id][tid]);
1593 spin_unlock(&txq->lock);
1597 if (txq->q.read_ptr != tfd_num) {
1598 IWL_DEBUG_TX_REPLY(trans, "[Q %d | AC %d] %d -> %d (%d)\n",
1599 txq_id, iwl_get_queue_ac(txq), txq->q.read_ptr,
1601 freed = iwl_tx_queue_reclaim(trans, txq_id, tfd_num, skbs);
1602 if (iwl_queue_space(&txq->q) > txq->q.low_mark)
1603 iwl_wake_queue(trans, txq);
1606 spin_unlock(&txq->lock);
1610 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1612 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1615 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1617 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1620 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1622 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1625 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
1626 const struct iwl_trans_config *trans_cfg)
1628 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1630 trans_pcie->cmd_queue = trans_cfg->cmd_queue;
1631 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1632 trans_pcie->n_no_reclaim_cmds = 0;
1634 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1635 if (trans_pcie->n_no_reclaim_cmds)
1636 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1637 trans_pcie->n_no_reclaim_cmds * sizeof(u8));
1640 static void iwl_trans_pcie_free(struct iwl_trans *trans)
1642 struct iwl_trans_pcie *trans_pcie =
1643 IWL_TRANS_GET_PCIE_TRANS(trans);
1645 iwl_trans_pcie_tx_free(trans);
1646 #ifndef CONFIG_IWLWIFI_IDI
1647 iwl_trans_pcie_rx_free(trans);
1649 if (trans_pcie->irq_requested == true) {
1650 free_irq(trans_pcie->irq, trans);
1651 iwl_free_isr_ict(trans);
1654 pci_disable_msi(trans_pcie->pci_dev);
1655 iounmap(trans_pcie->hw_base);
1656 pci_release_regions(trans_pcie->pci_dev);
1657 pci_disable_device(trans_pcie->pci_dev);
1659 trans->shrd->trans = NULL;
1663 #ifdef CONFIG_PM_SLEEP
1664 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
1669 static int iwl_trans_pcie_resume(struct iwl_trans *trans)
1673 hw_rfkill = !(iwl_read32(trans, CSR_GP_CNTRL) &
1674 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
1677 iwl_enable_rfkill_int(trans);
1679 iwl_enable_interrupts(trans);
1681 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1685 #endif /* CONFIG_PM_SLEEP */
1687 #define IWL_FLUSH_WAIT_MS 2000
1689 static int iwl_trans_pcie_wait_tx_queue_empty(struct iwl_trans *trans)
1691 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1692 struct iwl_tx_queue *txq;
1693 struct iwl_queue *q;
1695 unsigned long now = jiffies;
1698 /* waiting for all the tx frames complete might take a while */
1699 for (cnt = 0; cnt < cfg(trans)->base_params->num_of_queues; cnt++) {
1700 if (cnt == trans_pcie->cmd_queue)
1702 txq = &trans_pcie->txq[cnt];
1704 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
1705 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
1708 if (q->read_ptr != q->write_ptr) {
1709 IWL_ERR(trans, "fail to flush all tx fifo queues\n");
1718 * On every watchdog tick we check (latest) time stamp. If it does not
1719 * change during timeout period and queue is not empty we reset firmware.
1721 static int iwl_trans_pcie_check_stuck_queue(struct iwl_trans *trans, int cnt)
1723 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1724 struct iwl_tx_queue *txq = &trans_pcie->txq[cnt];
1725 struct iwl_queue *q = &txq->q;
1726 unsigned long timeout;
1728 if (q->read_ptr == q->write_ptr) {
1729 txq->time_stamp = jiffies;
1733 timeout = txq->time_stamp +
1734 msecs_to_jiffies(hw_params(trans).wd_timeout);
1736 if (time_after(jiffies, timeout)) {
1737 IWL_ERR(trans, "Queue %d stuck for %u ms.\n", q->id,
1738 hw_params(trans).wd_timeout);
1739 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
1740 q->read_ptr, q->write_ptr);
1741 IWL_ERR(trans, "Current HW read_ptr %d write_ptr %d\n",
1742 iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt))
1743 & (TFD_QUEUE_SIZE_MAX - 1),
1744 iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
1751 static const char *get_fh_string(int cmd)
1754 IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
1755 IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
1756 IWL_CMD(FH_RSCSR_CHNL0_WPTR);
1757 IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
1758 IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
1759 IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
1760 IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
1761 IWL_CMD(FH_TSSR_TX_STATUS_REG);
1762 IWL_CMD(FH_TSSR_TX_ERROR_REG);
1768 int iwl_dump_fh(struct iwl_trans *trans, char **buf, bool display)
1771 #ifdef CONFIG_IWLWIFI_DEBUG
1775 static const u32 fh_tbl[] = {
1776 FH_RSCSR_CHNL0_STTS_WPTR_REG,
1777 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
1778 FH_RSCSR_CHNL0_WPTR,
1779 FH_MEM_RCSR_CHNL0_CONFIG_REG,
1780 FH_MEM_RSSR_SHARED_CTRL_REG,
1781 FH_MEM_RSSR_RX_STATUS_REG,
1782 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
1783 FH_TSSR_TX_STATUS_REG,
1784 FH_TSSR_TX_ERROR_REG
1786 #ifdef CONFIG_IWLWIFI_DEBUG
1788 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
1789 *buf = kmalloc(bufsz, GFP_KERNEL);
1792 pos += scnprintf(*buf + pos, bufsz - pos,
1793 "FH register values:\n");
1794 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1795 pos += scnprintf(*buf + pos, bufsz - pos,
1797 get_fh_string(fh_tbl[i]),
1798 iwl_read_direct32(trans, fh_tbl[i]));
1803 IWL_ERR(trans, "FH register values:\n");
1804 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1805 IWL_ERR(trans, " %34s: 0X%08x\n",
1806 get_fh_string(fh_tbl[i]),
1807 iwl_read_direct32(trans, fh_tbl[i]));
1812 static const char *get_csr_string(int cmd)
1815 IWL_CMD(CSR_HW_IF_CONFIG_REG);
1816 IWL_CMD(CSR_INT_COALESCING);
1818 IWL_CMD(CSR_INT_MASK);
1819 IWL_CMD(CSR_FH_INT_STATUS);
1820 IWL_CMD(CSR_GPIO_IN);
1822 IWL_CMD(CSR_GP_CNTRL);
1823 IWL_CMD(CSR_HW_REV);
1824 IWL_CMD(CSR_EEPROM_REG);
1825 IWL_CMD(CSR_EEPROM_GP);
1826 IWL_CMD(CSR_OTP_GP_REG);
1827 IWL_CMD(CSR_GIO_REG);
1828 IWL_CMD(CSR_GP_UCODE_REG);
1829 IWL_CMD(CSR_GP_DRIVER_REG);
1830 IWL_CMD(CSR_UCODE_DRV_GP1);
1831 IWL_CMD(CSR_UCODE_DRV_GP2);
1832 IWL_CMD(CSR_LED_REG);
1833 IWL_CMD(CSR_DRAM_INT_TBL_REG);
1834 IWL_CMD(CSR_GIO_CHICKEN_BITS);
1835 IWL_CMD(CSR_ANA_PLL_CFG);
1836 IWL_CMD(CSR_HW_REV_WA_REG);
1837 IWL_CMD(CSR_DBG_HPET_MEM_REG);
1843 void iwl_dump_csr(struct iwl_trans *trans)
1846 static const u32 csr_tbl[] = {
1847 CSR_HW_IF_CONFIG_REG,
1865 CSR_DRAM_INT_TBL_REG,
1866 CSR_GIO_CHICKEN_BITS,
1869 CSR_DBG_HPET_MEM_REG
1871 IWL_ERR(trans, "CSR values:\n");
1872 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1873 "CSR_INT_PERIODIC_REG)\n");
1874 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
1875 IWL_ERR(trans, " %25s: 0X%08x\n",
1876 get_csr_string(csr_tbl[i]),
1877 iwl_read32(trans, csr_tbl[i]));
1881 #ifdef CONFIG_IWLWIFI_DEBUGFS
1882 /* create and remove of files */
1883 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \
1884 if (!debugfs_create_file(#name, mode, parent, trans, \
1885 &iwl_dbgfs_##name##_ops)) \
1889 /* file operation */
1890 #define DEBUGFS_READ_FUNC(name) \
1891 static ssize_t iwl_dbgfs_##name##_read(struct file *file, \
1892 char __user *user_buf, \
1893 size_t count, loff_t *ppos);
1895 #define DEBUGFS_WRITE_FUNC(name) \
1896 static ssize_t iwl_dbgfs_##name##_write(struct file *file, \
1897 const char __user *user_buf, \
1898 size_t count, loff_t *ppos);
1901 #define DEBUGFS_READ_FILE_OPS(name) \
1902 DEBUGFS_READ_FUNC(name); \
1903 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1904 .read = iwl_dbgfs_##name##_read, \
1905 .open = simple_open, \
1906 .llseek = generic_file_llseek, \
1909 #define DEBUGFS_WRITE_FILE_OPS(name) \
1910 DEBUGFS_WRITE_FUNC(name); \
1911 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1912 .write = iwl_dbgfs_##name##_write, \
1913 .open = simple_open, \
1914 .llseek = generic_file_llseek, \
1917 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \
1918 DEBUGFS_READ_FUNC(name); \
1919 DEBUGFS_WRITE_FUNC(name); \
1920 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1921 .write = iwl_dbgfs_##name##_write, \
1922 .read = iwl_dbgfs_##name##_read, \
1923 .open = simple_open, \
1924 .llseek = generic_file_llseek, \
1927 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1928 char __user *user_buf,
1929 size_t count, loff_t *ppos)
1931 struct iwl_trans *trans = file->private_data;
1932 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1933 struct iwl_tx_queue *txq;
1934 struct iwl_queue *q;
1941 bufsz = sizeof(char) * 64 * cfg(trans)->base_params->num_of_queues;
1943 if (!trans_pcie->txq) {
1944 IWL_ERR(trans, "txq not ready\n");
1947 buf = kzalloc(bufsz, GFP_KERNEL);
1951 for (cnt = 0; cnt < cfg(trans)->base_params->num_of_queues; cnt++) {
1952 txq = &trans_pcie->txq[cnt];
1954 pos += scnprintf(buf + pos, bufsz - pos,
1955 "hwq %.2d: read=%u write=%u stop=%d"
1956 " swq_id=%#.2x (ac %d/hwq %d)\n",
1957 cnt, q->read_ptr, q->write_ptr,
1958 !!test_bit(cnt, trans_pcie->queue_stopped),
1959 txq->swq_id, txq->swq_id & 3,
1960 (txq->swq_id >> 2) & 0x1f);
1963 /* for the ACs, display the stop count too */
1964 pos += scnprintf(buf + pos, bufsz - pos,
1965 " stop-count: %d\n",
1966 atomic_read(&trans_pcie->queue_stop_count[cnt]));
1968 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1973 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1974 char __user *user_buf,
1975 size_t count, loff_t *ppos) {
1976 struct iwl_trans *trans = file->private_data;
1977 struct iwl_trans_pcie *trans_pcie =
1978 IWL_TRANS_GET_PCIE_TRANS(trans);
1979 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
1982 const size_t bufsz = sizeof(buf);
1984 pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1986 pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1988 pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1991 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1992 le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF);
1994 pos += scnprintf(buf + pos, bufsz - pos,
1995 "closed_rb_num: Not Allocated\n");
1997 return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2000 static ssize_t iwl_dbgfs_log_event_read(struct file *file,
2001 char __user *user_buf,
2002 size_t count, loff_t *ppos)
2004 struct iwl_trans *trans = file->private_data;
2007 ssize_t ret = -ENOMEM;
2009 ret = pos = iwl_dump_nic_event_log(trans, true, &buf, true);
2011 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2017 static ssize_t iwl_dbgfs_log_event_write(struct file *file,
2018 const char __user *user_buf,
2019 size_t count, loff_t *ppos)
2021 struct iwl_trans *trans = file->private_data;
2026 memset(buf, 0, sizeof(buf));
2027 buf_size = min(count, sizeof(buf) - 1);
2028 if (copy_from_user(buf, user_buf, buf_size))
2030 if (sscanf(buf, "%d", &event_log_flag) != 1)
2032 if (event_log_flag == 1)
2033 iwl_dump_nic_event_log(trans, true, NULL, false);
2038 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
2039 char __user *user_buf,
2040 size_t count, loff_t *ppos) {
2042 struct iwl_trans *trans = file->private_data;
2043 struct iwl_trans_pcie *trans_pcie =
2044 IWL_TRANS_GET_PCIE_TRANS(trans);
2045 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2049 int bufsz = 24 * 64; /* 24 items * 64 char per item */
2052 buf = kzalloc(bufsz, GFP_KERNEL);
2054 IWL_ERR(trans, "Can not allocate Buffer\n");
2058 pos += scnprintf(buf + pos, bufsz - pos,
2059 "Interrupt Statistics Report:\n");
2061 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
2063 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
2065 if (isr_stats->sw || isr_stats->hw) {
2066 pos += scnprintf(buf + pos, bufsz - pos,
2067 "\tLast Restarting Code: 0x%X\n",
2068 isr_stats->err_code);
2070 #ifdef CONFIG_IWLWIFI_DEBUG
2071 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
2073 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
2076 pos += scnprintf(buf + pos, bufsz - pos,
2077 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
2079 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
2082 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
2085 pos += scnprintf(buf + pos, bufsz - pos,
2086 "Rx command responses:\t\t %u\n", isr_stats->rx);
2088 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
2091 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
2092 isr_stats->unhandled);
2094 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2099 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
2100 const char __user *user_buf,
2101 size_t count, loff_t *ppos)
2103 struct iwl_trans *trans = file->private_data;
2104 struct iwl_trans_pcie *trans_pcie =
2105 IWL_TRANS_GET_PCIE_TRANS(trans);
2106 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2112 memset(buf, 0, sizeof(buf));
2113 buf_size = min(count, sizeof(buf) - 1);
2114 if (copy_from_user(buf, user_buf, buf_size))
2116 if (sscanf(buf, "%x", &reset_flag) != 1)
2118 if (reset_flag == 0)
2119 memset(isr_stats, 0, sizeof(*isr_stats));
2124 static ssize_t iwl_dbgfs_csr_write(struct file *file,
2125 const char __user *user_buf,
2126 size_t count, loff_t *ppos)
2128 struct iwl_trans *trans = file->private_data;
2133 memset(buf, 0, sizeof(buf));
2134 buf_size = min(count, sizeof(buf) - 1);
2135 if (copy_from_user(buf, user_buf, buf_size))
2137 if (sscanf(buf, "%d", &csr) != 1)
2140 iwl_dump_csr(trans);
2145 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
2146 char __user *user_buf,
2147 size_t count, loff_t *ppos)
2149 struct iwl_trans *trans = file->private_data;
2152 ssize_t ret = -EFAULT;
2154 ret = pos = iwl_dump_fh(trans, &buf, true);
2156 ret = simple_read_from_buffer(user_buf,
2157 count, ppos, buf, pos);
2164 DEBUGFS_READ_WRITE_FILE_OPS(log_event);
2165 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
2166 DEBUGFS_READ_FILE_OPS(fh_reg);
2167 DEBUGFS_READ_FILE_OPS(rx_queue);
2168 DEBUGFS_READ_FILE_OPS(tx_queue);
2169 DEBUGFS_WRITE_FILE_OPS(csr);
2172 * Create the debugfs files and directories
2175 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2178 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
2179 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
2180 DEBUGFS_ADD_FILE(log_event, dir, S_IWUSR | S_IRUSR);
2181 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
2182 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
2183 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
2187 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2191 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2193 const struct iwl_trans_ops trans_ops_pcie = {
2194 .start_hw = iwl_trans_pcie_start_hw,
2195 .stop_hw = iwl_trans_pcie_stop_hw,
2196 .fw_alive = iwl_trans_pcie_fw_alive,
2197 .start_fw = iwl_trans_pcie_start_fw,
2198 .stop_device = iwl_trans_pcie_stop_device,
2200 .wowlan_suspend = iwl_trans_pcie_wowlan_suspend,
2202 .send_cmd = iwl_trans_pcie_send_cmd,
2204 .tx = iwl_trans_pcie_tx,
2205 .reclaim = iwl_trans_pcie_reclaim,
2207 .tx_agg_disable = iwl_trans_pcie_tx_agg_disable,
2208 .tx_agg_alloc = iwl_trans_pcie_tx_agg_alloc,
2209 .tx_agg_setup = iwl_trans_pcie_tx_agg_setup,
2211 .free = iwl_trans_pcie_free,
2213 .dbgfs_register = iwl_trans_pcie_dbgfs_register,
2215 .wait_tx_queue_empty = iwl_trans_pcie_wait_tx_queue_empty,
2216 .check_stuck_queue = iwl_trans_pcie_check_stuck_queue,
2218 #ifdef CONFIG_PM_SLEEP
2219 .suspend = iwl_trans_pcie_suspend,
2220 .resume = iwl_trans_pcie_resume,
2222 .write8 = iwl_trans_pcie_write8,
2223 .write32 = iwl_trans_pcie_write32,
2224 .read32 = iwl_trans_pcie_read32,
2225 .configure = iwl_trans_pcie_configure,
2228 struct iwl_trans *iwl_trans_pcie_alloc(struct iwl_shared *shrd,
2229 struct pci_dev *pdev,
2230 const struct pci_device_id *ent)
2232 struct iwl_trans_pcie *trans_pcie;
2233 struct iwl_trans *trans;
2237 trans = kzalloc(sizeof(struct iwl_trans) +
2238 sizeof(struct iwl_trans_pcie), GFP_KERNEL);
2240 if (WARN_ON(!trans))
2243 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2245 trans->ops = &trans_ops_pcie;
2247 trans_pcie->trans = trans;
2248 spin_lock_init(&trans_pcie->irq_lock);
2249 init_waitqueue_head(&trans_pcie->ucode_write_waitq);
2251 /* W/A - seems to solve weird behavior. We need to remove this if we
2252 * don't want to stay in L1 all the time. This wastes a lot of power */
2253 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
2254 PCIE_LINK_STATE_CLKPM);
2256 if (pci_enable_device(pdev)) {
2261 pci_set_master(pdev);
2263 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
2265 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
2267 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2269 err = pci_set_consistent_dma_mask(pdev,
2271 /* both attempts failed: */
2273 dev_printk(KERN_ERR, &pdev->dev,
2274 "No suitable DMA available.\n");
2275 goto out_pci_disable_device;
2279 err = pci_request_regions(pdev, DRV_NAME);
2281 dev_printk(KERN_ERR, &pdev->dev, "pci_request_regions failed");
2282 goto out_pci_disable_device;
2285 trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
2286 if (!trans_pcie->hw_base) {
2287 dev_printk(KERN_ERR, &pdev->dev, "pci_ioremap_bar failed");
2289 goto out_pci_release_regions;
2292 dev_printk(KERN_INFO, &pdev->dev,
2293 "pci_resource_len = 0x%08llx\n",
2294 (unsigned long long) pci_resource_len(pdev, 0));
2295 dev_printk(KERN_INFO, &pdev->dev,
2296 "pci_resource_base = %p\n", trans_pcie->hw_base);
2298 dev_printk(KERN_INFO, &pdev->dev,
2299 "HW Revision ID = 0x%X\n", pdev->revision);
2301 /* We disable the RETRY_TIMEOUT register (0x41) to keep
2302 * PCI Tx retries from interfering with C3 CPU state */
2303 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2305 err = pci_enable_msi(pdev);
2307 dev_printk(KERN_ERR, &pdev->dev,
2308 "pci_enable_msi failed(0X%x)", err);
2310 trans->dev = &pdev->dev;
2311 trans_pcie->irq = pdev->irq;
2312 trans_pcie->pci_dev = pdev;
2313 trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
2314 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
2315 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
2316 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
2318 /* TODO: Move this away, not needed if not MSI */
2319 /* enable rfkill interrupt: hw bug w/a */
2320 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2321 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
2322 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
2323 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2326 /* Initialize the wait queue for commands */
2327 init_waitqueue_head(&trans->wait_command_queue);
2331 out_pci_release_regions:
2332 pci_release_regions(pdev);
2333 out_pci_disable_device:
2334 pci_disable_device(pdev);