1 /******************************************************************************
3 * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
21 * Contact Information:
22 * Intel Linux Wireless <ilw@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 *****************************************************************************/
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/init.h>
30 #include <linux/slab.h>
31 #include <linux/pci.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/delay.h>
34 #include <linux/sched.h>
35 #include <linux/skbuff.h>
36 #include <linux/netdevice.h>
37 #include <linux/wireless.h>
38 #include <linux/firmware.h>
39 #include <linux/etherdevice.h>
40 #include <asm/unaligned.h>
41 #include <net/mac80211.h>
44 #include "iwl-3945-fh.h"
45 #include "iwl-commands.h"
48 #include "iwl-eeprom.h"
50 #include "iwl-helpers.h"
52 #include "iwl-3945-led.h"
53 #include "iwl-3945-debugfs.h"
55 #define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np) \
56 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
57 IWL_RATE_##r##M_IEEE, \
58 IWL_RATE_##ip##M_INDEX, \
59 IWL_RATE_##in##M_INDEX, \
60 IWL_RATE_##rp##M_INDEX, \
61 IWL_RATE_##rn##M_INDEX, \
62 IWL_RATE_##pp##M_INDEX, \
63 IWL_RATE_##np##M_INDEX, \
64 IWL_RATE_##r##M_INDEX_TABLE, \
65 IWL_RATE_##ip##M_INDEX_TABLE }
69 * rate, prev rate, next rate, prev tgg rate, next tgg rate
71 * If there isn't a valid next or previous rate then INV is used which
72 * maps to IWL_RATE_INVALID
75 const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT_3945] = {
76 IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2), /* 1mbps */
77 IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5), /* 2mbps */
78 IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11), /*5.5mbps */
79 IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18), /* 11mbps */
80 IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11), /* 6mbps */
81 IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11), /* 9mbps */
82 IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18), /* 12mbps */
83 IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24), /* 18mbps */
84 IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36), /* 24mbps */
85 IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48), /* 36mbps */
86 IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54), /* 48mbps */
87 IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */
90 /* 1 = enable the iwl3945_disable_events() function */
91 #define IWL_EVT_DISABLE (0)
92 #define IWL_EVT_DISABLE_SIZE (1532/32)
95 * iwl3945_disable_events - Disable selected events in uCode event log
97 * Disable an event by writing "1"s into "disable"
98 * bitmap in SRAM. Bit position corresponds to Event # (id/type).
99 * Default values of 0 enable uCode events to be logged.
100 * Use for only special debugging. This function is just a placeholder as-is,
101 * you'll need to provide the special bits! ...
102 * ... and set IWL_EVT_DISABLE to 1. */
103 void iwl3945_disable_events(struct iwl_priv *priv)
106 u32 base; /* SRAM address of event log header */
107 u32 disable_ptr; /* SRAM address of event-disable bitmap array */
108 u32 array_size; /* # of u32 entries in array */
109 u32 evt_disable[IWL_EVT_DISABLE_SIZE] = {
110 0x00000000, /* 31 - 0 Event id numbers */
111 0x00000000, /* 63 - 32 */
112 0x00000000, /* 95 - 64 */
113 0x00000000, /* 127 - 96 */
114 0x00000000, /* 159 - 128 */
115 0x00000000, /* 191 - 160 */
116 0x00000000, /* 223 - 192 */
117 0x00000000, /* 255 - 224 */
118 0x00000000, /* 287 - 256 */
119 0x00000000, /* 319 - 288 */
120 0x00000000, /* 351 - 320 */
121 0x00000000, /* 383 - 352 */
122 0x00000000, /* 415 - 384 */
123 0x00000000, /* 447 - 416 */
124 0x00000000, /* 479 - 448 */
125 0x00000000, /* 511 - 480 */
126 0x00000000, /* 543 - 512 */
127 0x00000000, /* 575 - 544 */
128 0x00000000, /* 607 - 576 */
129 0x00000000, /* 639 - 608 */
130 0x00000000, /* 671 - 640 */
131 0x00000000, /* 703 - 672 */
132 0x00000000, /* 735 - 704 */
133 0x00000000, /* 767 - 736 */
134 0x00000000, /* 799 - 768 */
135 0x00000000, /* 831 - 800 */
136 0x00000000, /* 863 - 832 */
137 0x00000000, /* 895 - 864 */
138 0x00000000, /* 927 - 896 */
139 0x00000000, /* 959 - 928 */
140 0x00000000, /* 991 - 960 */
141 0x00000000, /* 1023 - 992 */
142 0x00000000, /* 1055 - 1024 */
143 0x00000000, /* 1087 - 1056 */
144 0x00000000, /* 1119 - 1088 */
145 0x00000000, /* 1151 - 1120 */
146 0x00000000, /* 1183 - 1152 */
147 0x00000000, /* 1215 - 1184 */
148 0x00000000, /* 1247 - 1216 */
149 0x00000000, /* 1279 - 1248 */
150 0x00000000, /* 1311 - 1280 */
151 0x00000000, /* 1343 - 1312 */
152 0x00000000, /* 1375 - 1344 */
153 0x00000000, /* 1407 - 1376 */
154 0x00000000, /* 1439 - 1408 */
155 0x00000000, /* 1471 - 1440 */
156 0x00000000, /* 1503 - 1472 */
159 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
160 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
161 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
165 disable_ptr = iwl_read_targ_mem(priv, base + (4 * sizeof(u32)));
166 array_size = iwl_read_targ_mem(priv, base + (5 * sizeof(u32)));
168 if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
169 IWL_DEBUG_INFO(priv, "Disabling selected uCode log events at 0x%x\n",
171 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
172 iwl_write_targ_mem(priv,
173 disable_ptr + (i * sizeof(u32)),
177 IWL_DEBUG_INFO(priv, "Selected uCode log events may be disabled\n");
178 IWL_DEBUG_INFO(priv, " by writing \"1\"s into disable bitmap\n");
179 IWL_DEBUG_INFO(priv, " in SRAM at 0x%x, size %d u32s\n",
180 disable_ptr, array_size);
185 static int iwl3945_hwrate_to_plcp_idx(u8 plcp)
189 for (idx = 0; idx < IWL_RATE_COUNT_3945; idx++)
190 if (iwl3945_rates[idx].plcp == plcp)
195 #ifdef CONFIG_IWLWIFI_DEBUG
196 #define TX_STATUS_ENTRY(x) case TX_3945_STATUS_FAIL_ ## x: return #x
198 static const char *iwl3945_get_tx_fail_reason(u32 status)
200 switch (status & TX_STATUS_MSK) {
201 case TX_3945_STATUS_SUCCESS:
203 TX_STATUS_ENTRY(SHORT_LIMIT);
204 TX_STATUS_ENTRY(LONG_LIMIT);
205 TX_STATUS_ENTRY(FIFO_UNDERRUN);
206 TX_STATUS_ENTRY(MGMNT_ABORT);
207 TX_STATUS_ENTRY(NEXT_FRAG);
208 TX_STATUS_ENTRY(LIFE_EXPIRE);
209 TX_STATUS_ENTRY(DEST_PS);
210 TX_STATUS_ENTRY(ABORTED);
211 TX_STATUS_ENTRY(BT_RETRY);
212 TX_STATUS_ENTRY(STA_INVALID);
213 TX_STATUS_ENTRY(FRAG_DROPPED);
214 TX_STATUS_ENTRY(TID_DISABLE);
215 TX_STATUS_ENTRY(FRAME_FLUSHED);
216 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
217 TX_STATUS_ENTRY(TX_LOCKED);
218 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
224 static inline const char *iwl3945_get_tx_fail_reason(u32 status)
231 * get ieee prev rate from rate scale table.
232 * for A and B mode we need to overright prev
235 int iwl3945_rs_next_rate(struct iwl_priv *priv, int rate)
237 int next_rate = iwl3945_get_prev_ieee_rate(rate);
239 switch (priv->band) {
240 case IEEE80211_BAND_5GHZ:
241 if (rate == IWL_RATE_12M_INDEX)
242 next_rate = IWL_RATE_9M_INDEX;
243 else if (rate == IWL_RATE_6M_INDEX)
244 next_rate = IWL_RATE_6M_INDEX;
246 case IEEE80211_BAND_2GHZ:
247 if (!(priv->_3945.sta_supp_rates & IWL_OFDM_RATES_MASK) &&
248 iwl_is_associated(priv)) {
249 if (rate == IWL_RATE_11M_INDEX)
250 next_rate = IWL_RATE_5M_INDEX;
263 * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
265 * When FW advances 'R' index, all entries between old and new 'R' index
266 * need to be reclaimed. As result, some free space forms. If there is
267 * enough free space (> low mark), wake the stack that feeds us.
269 static void iwl3945_tx_queue_reclaim(struct iwl_priv *priv,
270 int txq_id, int index)
272 struct iwl_tx_queue *txq = &priv->txq[txq_id];
273 struct iwl_queue *q = &txq->q;
274 struct iwl_tx_info *tx_info;
276 BUG_ON(txq_id == IWL_CMD_QUEUE_NUM);
278 for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
279 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
281 tx_info = &txq->txb[txq->q.read_ptr];
282 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
283 tx_info->skb[0] = NULL;
284 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
287 if (iwl_queue_space(q) > q->low_mark && (txq_id >= 0) &&
288 (txq_id != IWL_CMD_QUEUE_NUM) &&
289 priv->mac80211_registered)
290 iwl_wake_queue(priv, txq_id);
294 * iwl3945_rx_reply_tx - Handle Tx response
296 static void iwl3945_rx_reply_tx(struct iwl_priv *priv,
297 struct iwl_rx_mem_buffer *rxb)
299 struct iwl_rx_packet *pkt = rxb_addr(rxb);
300 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
301 int txq_id = SEQ_TO_QUEUE(sequence);
302 int index = SEQ_TO_INDEX(sequence);
303 struct iwl_tx_queue *txq = &priv->txq[txq_id];
304 struct ieee80211_tx_info *info;
305 struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
306 u32 status = le32_to_cpu(tx_resp->status);
310 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
311 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
312 "is out of range [0-%d] %d %d\n", txq_id,
313 index, txq->q.n_bd, txq->q.write_ptr,
318 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
319 ieee80211_tx_info_clear_status(info);
321 /* Fill the MRR chain with some info about on-chip retransmissions */
322 rate_idx = iwl3945_hwrate_to_plcp_idx(tx_resp->rate);
323 if (info->band == IEEE80211_BAND_5GHZ)
324 rate_idx -= IWL_FIRST_OFDM_RATE;
326 fail = tx_resp->failure_frame;
328 info->status.rates[0].idx = rate_idx;
329 info->status.rates[0].count = fail + 1; /* add final attempt */
331 /* tx_status->rts_retry_count = tx_resp->failure_rts; */
332 info->flags |= ((status & TX_STATUS_MSK) == TX_STATUS_SUCCESS) ?
333 IEEE80211_TX_STAT_ACK : 0;
335 IWL_DEBUG_TX(priv, "Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
336 txq_id, iwl3945_get_tx_fail_reason(status), status,
337 tx_resp->rate, tx_resp->failure_frame);
339 IWL_DEBUG_TX_REPLY(priv, "Tx queue reclaim %d\n", index);
340 iwl3945_tx_queue_reclaim(priv, txq_id, index);
342 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
343 IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n");
348 /*****************************************************************************
350 * Intel PRO/Wireless 3945ABG/BG Network Connection
352 * RX handler implementations
354 *****************************************************************************/
355 #ifdef CONFIG_IWLWIFI_DEBUG
357 * based on the assumption of all statistics counter are in DWORD
358 * FIXME: This function is for debugging, do not deal with
359 * the case of counters roll-over.
361 static void iwl3945_accumulative_statistics(struct iwl_priv *priv,
367 u32 *delta, *max_delta;
369 prev_stats = (__le32 *)&priv->_3945.statistics;
370 accum_stats = (u32 *)&priv->_3945.accum_statistics;
371 delta = (u32 *)&priv->_3945.delta_statistics;
372 max_delta = (u32 *)&priv->_3945.max_delta;
374 for (i = sizeof(__le32); i < sizeof(struct iwl3945_notif_statistics);
375 i += sizeof(__le32), stats++, prev_stats++, delta++,
376 max_delta++, accum_stats++) {
377 if (le32_to_cpu(*stats) > le32_to_cpu(*prev_stats)) {
378 *delta = (le32_to_cpu(*stats) -
379 le32_to_cpu(*prev_stats));
380 *accum_stats += *delta;
381 if (*delta > *max_delta)
386 /* reset accumulative statistics for "no-counter" type statistics */
387 priv->_3945.accum_statistics.general.temperature =
388 priv->_3945.statistics.general.temperature;
389 priv->_3945.accum_statistics.general.ttl_timestamp =
390 priv->_3945.statistics.general.ttl_timestamp;
394 void iwl3945_hw_rx_statistics(struct iwl_priv *priv,
395 struct iwl_rx_mem_buffer *rxb)
397 struct iwl_rx_packet *pkt = rxb_addr(rxb);
399 IWL_DEBUG_RX(priv, "Statistics notification received (%d vs %d).\n",
400 (int)sizeof(struct iwl3945_notif_statistics),
401 le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
402 #ifdef CONFIG_IWLWIFI_DEBUG
403 iwl3945_accumulative_statistics(priv, (__le32 *)&pkt->u.raw);
406 memcpy(&priv->_3945.statistics, pkt->u.raw, sizeof(priv->_3945.statistics));
409 void iwl3945_reply_statistics(struct iwl_priv *priv,
410 struct iwl_rx_mem_buffer *rxb)
412 struct iwl_rx_packet *pkt = rxb_addr(rxb);
413 __le32 *flag = (__le32 *)&pkt->u.raw;
415 if (le32_to_cpu(*flag) & UCODE_STATISTICS_CLEAR_MSK) {
416 #ifdef CONFIG_IWLWIFI_DEBUG
417 memset(&priv->_3945.accum_statistics, 0,
418 sizeof(struct iwl3945_notif_statistics));
419 memset(&priv->_3945.delta_statistics, 0,
420 sizeof(struct iwl3945_notif_statistics));
421 memset(&priv->_3945.max_delta, 0,
422 sizeof(struct iwl3945_notif_statistics));
424 IWL_DEBUG_RX(priv, "Statistics have been cleared\n");
426 iwl3945_hw_rx_statistics(priv, rxb);
430 /******************************************************************************
432 * Misc. internal state and helper functions
434 ******************************************************************************/
435 #ifdef CONFIG_IWLWIFI_DEBUG
438 * iwl3945_report_frame - dump frame to syslog during debug sessions
440 * You may hack this function to show different aspects of received frames,
441 * including selective frame dumps.
442 * group100 parameter selects whether to show 1 out of 100 good frames.
444 static void _iwl3945_dbg_report_frame(struct iwl_priv *priv,
445 struct iwl_rx_packet *pkt,
446 struct ieee80211_hdr *header, int group100)
449 u32 print_summary = 0;
450 u32 print_dump = 0; /* set to 1 to dump all frames' contents */
466 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
467 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
468 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
469 u8 *data = IWL_RX_DATA(pkt);
472 fc = header->frame_control;
473 seq_ctl = le16_to_cpu(header->seq_ctrl);
476 channel = le16_to_cpu(rx_hdr->channel);
477 phy_flags = le16_to_cpu(rx_hdr->phy_flags);
478 length = le16_to_cpu(rx_hdr->len);
480 /* end-of-frame status and timestamp */
481 status = le32_to_cpu(rx_end->status);
482 bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
483 tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
484 tsf = le64_to_cpu(rx_end->timestamp);
486 /* signal statistics */
487 rssi = rx_stats->rssi;
489 sig_avg = le16_to_cpu(rx_stats->sig_avg);
490 noise_diff = le16_to_cpu(rx_stats->noise_diff);
492 to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
494 /* if data frame is to us and all is good,
495 * (optionally) print summary for only 1 out of every 100 */
496 if (to_us && (fc & ~cpu_to_le16(IEEE80211_FCTL_PROTECTED)) ==
497 cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
500 print_summary = 1; /* print each frame */
501 else if (priv->framecnt_to_us < 100) {
502 priv->framecnt_to_us++;
505 priv->framecnt_to_us = 0;
510 /* print summary for all other frames */
520 else if (ieee80211_has_retry(fc))
522 else if (ieee80211_is_assoc_resp(fc))
524 else if (ieee80211_is_reassoc_resp(fc))
526 else if (ieee80211_is_probe_resp(fc)) {
528 print_dump = 1; /* dump frame contents */
529 } else if (ieee80211_is_beacon(fc)) {
531 print_dump = 1; /* dump frame contents */
532 } else if (ieee80211_is_atim(fc))
534 else if (ieee80211_is_auth(fc))
536 else if (ieee80211_is_deauth(fc))
538 else if (ieee80211_is_disassoc(fc))
543 rate = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
547 rate = iwl3945_rates[rate].ieee / 2;
549 /* print frame summary.
550 * MAC addresses show just the last byte (for brevity),
551 * but you can hack it to show more, if you'd like to. */
553 IWL_DEBUG_RX(priv, "%s: mhd=0x%04x, dst=0x%02x, "
554 "len=%u, rssi=%d, chnl=%d, rate=%d,\n",
555 title, le16_to_cpu(fc), header->addr1[5],
556 length, rssi, channel, rate);
558 /* src/dst addresses assume managed mode */
559 IWL_DEBUG_RX(priv, "%s: 0x%04x, dst=0x%02x, "
560 "src=0x%02x, rssi=%u, tim=%lu usec, "
561 "phy=0x%02x, chnl=%d\n",
562 title, le16_to_cpu(fc), header->addr1[5],
563 header->addr3[5], rssi,
564 tsf_low - priv->scan_start_tsf,
569 iwl_print_hex_dump(priv, IWL_DL_RX, data, length);
572 static void iwl3945_dbg_report_frame(struct iwl_priv *priv,
573 struct iwl_rx_packet *pkt,
574 struct ieee80211_hdr *header, int group100)
576 if (iwl_get_debug_level(priv) & IWL_DL_RX)
577 _iwl3945_dbg_report_frame(priv, pkt, header, group100);
581 static inline void iwl3945_dbg_report_frame(struct iwl_priv *priv,
582 struct iwl_rx_packet *pkt,
583 struct ieee80211_hdr *header, int group100)
588 /* This is necessary only for a number of statistics, see the caller. */
589 static int iwl3945_is_network_packet(struct iwl_priv *priv,
590 struct ieee80211_hdr *header)
592 /* Filter incoming packets to determine if they are targeted toward
593 * this network, discarding packets coming from ourselves */
594 switch (priv->iw_mode) {
595 case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source | BSSID */
596 /* packets to our IBSS update information */
597 return !compare_ether_addr(header->addr3, priv->bssid);
598 case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
599 /* packets to our IBSS update information */
600 return !compare_ether_addr(header->addr2, priv->bssid);
606 static void iwl3945_pass_packet_to_mac80211(struct iwl_priv *priv,
607 struct iwl_rx_mem_buffer *rxb,
608 struct ieee80211_rx_status *stats)
610 struct iwl_rx_packet *pkt = rxb_addr(rxb);
611 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
612 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
613 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
614 u16 len = le16_to_cpu(rx_hdr->len);
616 __le16 fc = hdr->frame_control;
618 /* We received data from the HW, so stop the watchdog */
619 if (unlikely(len + IWL39_RX_FRAME_SIZE >
620 PAGE_SIZE << priv->hw_params.rx_page_order)) {
621 IWL_DEBUG_DROP(priv, "Corruption detected!\n");
625 /* We only process data packets if the interface is open */
626 if (unlikely(!priv->is_open)) {
627 IWL_DEBUG_DROP_LIMIT(priv,
628 "Dropping packet while interface is not open.\n");
632 skb = dev_alloc_skb(128);
634 IWL_ERR(priv, "dev_alloc_skb failed\n");
638 if (!iwl3945_mod_params.sw_crypto)
639 iwl_set_decrypted_flag(priv,
640 (struct ieee80211_hdr *)rxb_addr(rxb),
641 le32_to_cpu(rx_end->status), stats);
643 skb_add_rx_frag(skb, 0, rxb->page,
644 (void *)rx_hdr->payload - (void *)pkt, len);
646 iwl_update_stats(priv, false, fc, len);
647 memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats));
649 ieee80211_rx(priv->hw, skb);
650 priv->alloc_rxb_page--;
654 #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
656 static void iwl3945_rx_reply_rx(struct iwl_priv *priv,
657 struct iwl_rx_mem_buffer *rxb)
659 struct ieee80211_hdr *header;
660 struct ieee80211_rx_status rx_status;
661 struct iwl_rx_packet *pkt = rxb_addr(rxb);
662 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
663 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
664 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
665 u16 rx_stats_sig_avg __maybe_unused = le16_to_cpu(rx_stats->sig_avg);
666 u16 rx_stats_noise_diff __maybe_unused = le16_to_cpu(rx_stats->noise_diff);
670 rx_status.mactime = le64_to_cpu(rx_end->timestamp);
672 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel));
673 rx_status.band = (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
674 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
676 rx_status.rate_idx = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
677 if (rx_status.band == IEEE80211_BAND_5GHZ)
678 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
680 rx_status.antenna = (le16_to_cpu(rx_hdr->phy_flags) &
681 RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
683 /* set the preamble flag if appropriate */
684 if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
685 rx_status.flag |= RX_FLAG_SHORTPRE;
687 if ((unlikely(rx_stats->phy_count > 20))) {
688 IWL_DEBUG_DROP(priv, "dsp size out of range [0,20]: %d/n",
689 rx_stats->phy_count);
693 if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR)
694 || !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
695 IWL_DEBUG_RX(priv, "Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
701 /* Convert 3945's rssi indicator to dBm */
702 rx_status.signal = rx_stats->rssi - IWL39_RSSI_OFFSET;
704 IWL_DEBUG_STATS(priv, "Rssi %d sig_avg %d noise_diff %d\n",
705 rx_status.signal, rx_stats_sig_avg,
706 rx_stats_noise_diff);
708 header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
710 network_packet = iwl3945_is_network_packet(priv, header);
712 IWL_DEBUG_STATS_LIMIT(priv, "[%c] %d RSSI:%d Signal:%u, Rate:%u\n",
713 network_packet ? '*' : ' ',
714 le16_to_cpu(rx_hdr->channel),
715 rx_status.signal, rx_status.signal,
718 /* Set "1" to report good data frames in groups of 100 */
719 iwl3945_dbg_report_frame(priv, pkt, header, 1);
720 iwl_dbg_log_rx_data_frame(priv, le16_to_cpu(rx_hdr->len), header);
722 if (network_packet) {
723 priv->_3945.last_beacon_time =
724 le32_to_cpu(rx_end->beacon_timestamp);
725 priv->_3945.last_tsf = le64_to_cpu(rx_end->timestamp);
726 priv->_3945.last_rx_rssi = rx_status.signal;
729 iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status);
732 int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
733 struct iwl_tx_queue *txq,
734 dma_addr_t addr, u16 len, u8 reset, u8 pad)
738 struct iwl3945_tfd *tfd, *tfd_tmp;
741 tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
742 tfd = &tfd_tmp[q->write_ptr];
745 memset(tfd, 0, sizeof(*tfd));
747 count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
749 if ((count >= NUM_TFD_CHUNKS) || (count < 0)) {
750 IWL_ERR(priv, "Error can not send more than %d chunks\n",
755 tfd->tbs[count].addr = cpu_to_le32(addr);
756 tfd->tbs[count].len = cpu_to_le32(len);
760 tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(count) |
761 TFD_CTL_PAD_SET(pad));
767 * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
769 * Does NOT advance any indexes
771 void iwl3945_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
773 struct iwl3945_tfd *tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
774 int index = txq->q.read_ptr;
775 struct iwl3945_tfd *tfd = &tfd_tmp[index];
776 struct pci_dev *dev = priv->pci_dev;
781 counter = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
782 if (counter > NUM_TFD_CHUNKS) {
783 IWL_ERR(priv, "Too many chunks: %i\n", counter);
784 /* @todo issue fatal error, it is quite serious situation */
790 pci_unmap_single(dev,
791 pci_unmap_addr(&txq->meta[index], mapping),
792 pci_unmap_len(&txq->meta[index], len),
795 /* unmap chunks if any */
797 for (i = 1; i < counter; i++) {
798 pci_unmap_single(dev, le32_to_cpu(tfd->tbs[i].addr),
799 le32_to_cpu(tfd->tbs[i].len), PCI_DMA_TODEVICE);
800 if (txq->txb[txq->q.read_ptr].skb[0]) {
801 struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[0];
802 if (txq->txb[txq->q.read_ptr].skb[0]) {
803 /* Can be called from interrupt context */
804 dev_kfree_skb_any(skb);
805 txq->txb[txq->q.read_ptr].skb[0] = NULL;
813 * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
816 void iwl3945_hw_build_tx_cmd_rate(struct iwl_priv *priv,
817 struct iwl_device_cmd *cmd,
818 struct ieee80211_tx_info *info,
819 struct ieee80211_hdr *hdr,
820 int sta_id, int tx_id)
822 u16 hw_value = ieee80211_get_tx_rate(priv->hw, info)->hw_value;
823 u16 rate_index = min(hw_value & 0xffff, IWL_RATE_COUNT_3945);
829 __le16 fc = hdr->frame_control;
830 struct iwl3945_tx_cmd *tx_cmd = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
832 rate = iwl3945_rates[rate_index].plcp;
833 tx_flags = tx_cmd->tx_flags;
835 /* We need to figure out how to get the sta->supp_rates while
836 * in this running context */
837 rate_mask = IWL_RATES_MASK;
840 /* Set retry limit on DATA packets and Probe Responses*/
841 if (ieee80211_is_probe_resp(fc))
842 data_retry_limit = 3;
844 data_retry_limit = IWL_DEFAULT_TX_RETRY;
845 tx_cmd->data_retry_limit = data_retry_limit;
847 if (tx_id >= IWL_CMD_QUEUE_NUM)
852 if (data_retry_limit < rts_retry_limit)
853 rts_retry_limit = data_retry_limit;
854 tx_cmd->rts_retry_limit = rts_retry_limit;
856 if (ieee80211_is_mgmt(fc)) {
857 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
858 case cpu_to_le16(IEEE80211_STYPE_AUTH):
859 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
860 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
861 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
862 if (tx_flags & TX_CMD_FLG_RTS_MSK) {
863 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
864 tx_flags |= TX_CMD_FLG_CTS_MSK;
873 tx_cmd->tx_flags = tx_flags;
876 tx_cmd->supp_rates[0] =
877 ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF;
880 tx_cmd->supp_rates[1] = (rate_mask & 0xF);
882 IWL_DEBUG_RATE(priv, "Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
883 "cck/ofdm mask: 0x%x/0x%x\n", sta_id,
884 tx_cmd->rate, le32_to_cpu(tx_cmd->tx_flags),
885 tx_cmd->supp_rates[1], tx_cmd->supp_rates[0]);
888 u8 iwl3945_sync_sta(struct iwl_priv *priv, int sta_id, u16 tx_rate, u8 flags)
890 unsigned long flags_spin;
891 struct iwl_station_entry *station;
893 if (sta_id == IWL_INVALID_STATION)
894 return IWL_INVALID_STATION;
896 spin_lock_irqsave(&priv->sta_lock, flags_spin);
897 station = &priv->stations[sta_id];
899 station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
900 station->sta.rate_n_flags = cpu_to_le16(tx_rate);
901 station->sta.mode = STA_CONTROL_MODIFY_MSK;
903 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
905 iwl_send_add_sta(priv, &station->sta, flags);
906 IWL_DEBUG_RATE(priv, "SCALE sync station %d to rate %d\n",
911 static int iwl3945_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
913 if (src == IWL_PWR_SRC_VAUX) {
914 if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) {
915 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
916 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
917 ~APMG_PS_CTRL_MSK_PWR_SRC);
919 iwl_poll_bit(priv, CSR_GPIO_IN,
920 CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
921 CSR_GPIO_IN_BIT_AUX_POWER, 5000);
924 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
925 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
926 ~APMG_PS_CTRL_MSK_PWR_SRC);
928 iwl_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
929 CSR_GPIO_IN_BIT_AUX_POWER, 5000); /* uS */
935 static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
937 iwl_write_direct32(priv, FH39_RCSR_RBD_BASE(0), rxq->dma_addr);
938 iwl_write_direct32(priv, FH39_RCSR_RPTR_ADDR(0), rxq->rb_stts_dma);
939 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), 0);
940 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0),
941 FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
942 FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
943 FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
944 FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
945 (RX_QUEUE_SIZE_LOG << FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
946 FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
947 (1 << FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
948 FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
950 /* fake read to flush all prev I/O */
951 iwl_read_direct32(priv, FH39_RSSR_CTRL);
956 static int iwl3945_tx_reset(struct iwl_priv *priv)
960 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
963 iwl_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
965 /* all 6 fifo are active */
966 iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
968 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
969 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
970 iwl_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
971 iwl_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
973 iwl_write_direct32(priv, FH39_TSSR_CBB_BASE,
974 priv->_3945.shared_phys);
976 iwl_write_direct32(priv, FH39_TSSR_MSG_CONFIG,
977 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
978 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
979 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
980 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
981 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
982 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
983 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
990 * iwl3945_txq_ctx_reset - Reset TX queue context
992 * Destroys all DMA structures and initialize them again
994 static int iwl3945_txq_ctx_reset(struct iwl_priv *priv)
997 int txq_id, slots_num;
999 iwl3945_hw_txq_ctx_free(priv);
1001 /* allocate tx queue structure */
1002 rc = iwl_alloc_txq_mem(priv);
1007 rc = iwl3945_tx_reset(priv);
1012 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
1013 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
1014 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
1015 rc = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
1018 IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
1026 iwl3945_hw_txq_ctx_free(priv);
1032 * Start up 3945's basic functionality after it has been reset
1033 * (e.g. after platform boot, or shutdown via iwl_apm_stop())
1034 * NOTE: This does not load uCode nor start the embedded processor
1036 static int iwl3945_apm_init(struct iwl_priv *priv)
1038 int ret = iwl_apm_init(priv);
1040 /* Clear APMG (NIC's internal power management) interrupts */
1041 iwl_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
1042 iwl_write_prph(priv, APMG_RTC_INT_STT_REG, 0xFFFFFFFF);
1044 /* Reset radio chip */
1045 iwl_set_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
1047 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
1052 static void iwl3945_nic_config(struct iwl_priv *priv)
1054 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1055 unsigned long flags;
1058 spin_lock_irqsave(&priv->lock, flags);
1060 /* Determine HW type */
1061 pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
1063 IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", rev_id);
1065 if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
1066 IWL_DEBUG_INFO(priv, "RTP type\n");
1067 else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
1068 IWL_DEBUG_INFO(priv, "3945 RADIO-MB type\n");
1069 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1070 CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
1072 IWL_DEBUG_INFO(priv, "3945 RADIO-MM type\n");
1073 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1074 CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
1077 if (EEPROM_SKU_CAP_OP_MODE_MRC == eeprom->sku_cap) {
1078 IWL_DEBUG_INFO(priv, "SKU OP mode is mrc\n");
1079 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1080 CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
1082 IWL_DEBUG_INFO(priv, "SKU OP mode is basic\n");
1084 if ((eeprom->board_revision & 0xF0) == 0xD0) {
1085 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
1086 eeprom->board_revision);
1087 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1088 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1090 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
1091 eeprom->board_revision);
1092 iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
1093 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1096 if (eeprom->almgor_m_version <= 1) {
1097 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1098 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
1099 IWL_DEBUG_INFO(priv, "Card M type A version is 0x%X\n",
1100 eeprom->almgor_m_version);
1102 IWL_DEBUG_INFO(priv, "Card M type B version is 0x%X\n",
1103 eeprom->almgor_m_version);
1104 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1105 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
1107 spin_unlock_irqrestore(&priv->lock, flags);
1109 if (eeprom->sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
1110 IWL_DEBUG_RF_KILL(priv, "SW RF KILL supported in EEPROM.\n");
1112 if (eeprom->sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
1113 IWL_DEBUG_RF_KILL(priv, "HW RF KILL supported in EEPROM.\n");
1116 int iwl3945_hw_nic_init(struct iwl_priv *priv)
1119 unsigned long flags;
1120 struct iwl_rx_queue *rxq = &priv->rxq;
1122 spin_lock_irqsave(&priv->lock, flags);
1123 priv->cfg->ops->lib->apm_ops.init(priv);
1124 spin_unlock_irqrestore(&priv->lock, flags);
1126 rc = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
1130 priv->cfg->ops->lib->apm_ops.config(priv);
1132 /* Allocate the RX queue, or reset if it is already allocated */
1134 rc = iwl_rx_queue_alloc(priv);
1136 IWL_ERR(priv, "Unable to initialize Rx queue\n");
1140 iwl3945_rx_queue_reset(priv, rxq);
1142 iwl3945_rx_replenish(priv);
1144 iwl3945_rx_init(priv, rxq);
1147 /* Look at using this instead:
1148 rxq->need_update = 1;
1149 iwl_rx_queue_update_write_ptr(priv, rxq);
1152 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), rxq->write & ~7);
1154 rc = iwl3945_txq_ctx_reset(priv);
1158 set_bit(STATUS_INIT, &priv->status);
1164 * iwl3945_hw_txq_ctx_free - Free TXQ Context
1166 * Destroy all TX DMA queues and structures
1168 void iwl3945_hw_txq_ctx_free(struct iwl_priv *priv)
1174 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num;
1176 if (txq_id == IWL_CMD_QUEUE_NUM)
1177 iwl_cmd_queue_free(priv);
1179 iwl_tx_queue_free(priv, txq_id);
1181 /* free tx queue structure */
1182 iwl_free_txq_mem(priv);
1185 void iwl3945_hw_txq_ctx_stop(struct iwl_priv *priv)
1190 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0);
1191 iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0);
1193 /* reset TFD queues */
1194 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
1195 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id), 0x0);
1196 iwl_poll_direct_bit(priv, FH39_TSSR_TX_STATUS,
1197 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
1201 iwl3945_hw_txq_ctx_free(priv);
1205 * iwl3945_hw_reg_adjust_power_by_temp
1206 * return index delta into power gain settings table
1208 static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
1210 return (new_reading - old_reading) * (-11) / 100;
1214 * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range
1216 static inline int iwl3945_hw_reg_temp_out_of_range(int temperature)
1218 return ((temperature < -260) || (temperature > 25)) ? 1 : 0;
1221 int iwl3945_hw_get_temperature(struct iwl_priv *priv)
1223 return iwl_read32(priv, CSR_UCODE_DRV_GP2);
1227 * iwl3945_hw_reg_txpower_get_temperature
1228 * get the current temperature by reading from NIC
1230 static int iwl3945_hw_reg_txpower_get_temperature(struct iwl_priv *priv)
1232 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1235 temperature = iwl3945_hw_get_temperature(priv);
1237 /* driver's okay range is -260 to +25.
1238 * human readable okay range is 0 to +285 */
1239 IWL_DEBUG_INFO(priv, "Temperature: %d\n", temperature + IWL_TEMP_CONVERT);
1241 /* handle insane temp reading */
1242 if (iwl3945_hw_reg_temp_out_of_range(temperature)) {
1243 IWL_ERR(priv, "Error bad temperature value %d\n", temperature);
1245 /* if really really hot(?),
1246 * substitute the 3rd band/group's temp measured at factory */
1247 if (priv->last_temperature > 100)
1248 temperature = eeprom->groups[2].temperature;
1249 else /* else use most recent "sane" value from driver */
1250 temperature = priv->last_temperature;
1253 return temperature; /* raw, not "human readable" */
1256 /* Adjust Txpower only if temperature variance is greater than threshold.
1258 * Both are lower than older versions' 9 degrees */
1259 #define IWL_TEMPERATURE_LIMIT_TIMER 6
1262 * is_temp_calib_needed - determines if new calibration is needed
1264 * records new temperature in tx_mgr->temperature.
1265 * replaces tx_mgr->last_temperature *only* if calib needed
1266 * (assumes caller will actually do the calibration!). */
1267 static int is_temp_calib_needed(struct iwl_priv *priv)
1271 priv->temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
1272 temp_diff = priv->temperature - priv->last_temperature;
1274 /* get absolute value */
1275 if (temp_diff < 0) {
1276 IWL_DEBUG_POWER(priv, "Getting cooler, delta %d,\n", temp_diff);
1277 temp_diff = -temp_diff;
1278 } else if (temp_diff == 0)
1279 IWL_DEBUG_POWER(priv, "Same temp,\n");
1281 IWL_DEBUG_POWER(priv, "Getting warmer, delta %d,\n", temp_diff);
1283 /* if we don't need calibration, *don't* update last_temperature */
1284 if (temp_diff < IWL_TEMPERATURE_LIMIT_TIMER) {
1285 IWL_DEBUG_POWER(priv, "Timed thermal calib not needed\n");
1289 IWL_DEBUG_POWER(priv, "Timed thermal calib needed\n");
1291 /* assume that caller will actually do calib ...
1292 * update the "last temperature" value */
1293 priv->last_temperature = priv->temperature;
1297 #define IWL_MAX_GAIN_ENTRIES 78
1298 #define IWL_CCK_FROM_OFDM_POWER_DIFF -5
1299 #define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
1301 /* radio and DSP power table, each step is 1/2 dB.
1302 * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
1303 static struct iwl3945_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = {
1305 {251, 127}, /* 2.4 GHz, highest power */
1382 {3, 95} }, /* 2.4 GHz, lowest power */
1384 {251, 127}, /* 5.x GHz, highest power */
1461 {3, 120} } /* 5.x GHz, lowest power */
1464 static inline u8 iwl3945_hw_reg_fix_power_index(int index)
1468 if (index >= IWL_MAX_GAIN_ENTRIES)
1469 return IWL_MAX_GAIN_ENTRIES - 1;
1473 /* Kick off thermal recalibration check every 60 seconds */
1474 #define REG_RECALIB_PERIOD (60)
1477 * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
1479 * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1480 * or 6 Mbit (OFDM) rates.
1482 static void iwl3945_hw_reg_set_scan_power(struct iwl_priv *priv, u32 scan_tbl_index,
1483 s32 rate_index, const s8 *clip_pwrs,
1484 struct iwl_channel_info *ch_info,
1487 struct iwl3945_scan_power_info *scan_power_info;
1491 scan_power_info = &ch_info->scan_pwr_info[scan_tbl_index];
1493 /* use this channel group's 6Mbit clipping/saturation pwr,
1494 * but cap at regulatory scan power restriction (set during init
1495 * based on eeprom channel data) for this channel. */
1496 power = min(ch_info->scan_power, clip_pwrs[IWL_RATE_6M_INDEX_TABLE]);
1498 /* further limit to user's max power preference.
1499 * FIXME: Other spectrum management power limitations do not
1500 * seem to apply?? */
1501 power = min(power, priv->tx_power_user_lmt);
1502 scan_power_info->requested_power = power;
1504 /* find difference between new scan *power* and current "normal"
1505 * Tx *power* for 6Mb. Use this difference (x2) to adjust the
1506 * current "normal" temperature-compensated Tx power *index* for
1507 * this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1509 power_index = ch_info->power_info[rate_index].power_table_index
1510 - (power - ch_info->power_info
1511 [IWL_RATE_6M_INDEX_TABLE].requested_power) * 2;
1513 /* store reference index that we use when adjusting *all* scan
1514 * powers. So we can accommodate user (all channel) or spectrum
1515 * management (single channel) power changes "between" temperature
1516 * feedback compensation procedures.
1517 * don't force fit this reference index into gain table; it may be a
1518 * negative number. This will help avoid errors when we're at
1519 * the lower bounds (highest gains, for warmest temperatures)
1522 /* don't exceed table bounds for "real" setting */
1523 power_index = iwl3945_hw_reg_fix_power_index(power_index);
1525 scan_power_info->power_table_index = power_index;
1526 scan_power_info->tpc.tx_gain =
1527 power_gain_table[band_index][power_index].tx_gain;
1528 scan_power_info->tpc.dsp_atten =
1529 power_gain_table[band_index][power_index].dsp_atten;
1533 * iwl3945_send_tx_power - fill in Tx Power command with gain settings
1535 * Configures power settings for all rates for the current channel,
1536 * using values from channel info struct, and send to NIC
1538 static int iwl3945_send_tx_power(struct iwl_priv *priv)
1541 const struct iwl_channel_info *ch_info = NULL;
1542 struct iwl3945_txpowertable_cmd txpower = {
1543 .channel = priv->active_rxon.channel,
1546 txpower.band = (priv->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
1547 ch_info = iwl_get_channel_info(priv,
1549 le16_to_cpu(priv->active_rxon.channel));
1552 "Failed to get channel info for channel %d [%d]\n",
1553 le16_to_cpu(priv->active_rxon.channel), priv->band);
1557 if (!is_channel_valid(ch_info)) {
1558 IWL_DEBUG_POWER(priv, "Not calling TX_PWR_TABLE_CMD on "
1559 "non-Tx channel.\n");
1563 /* fill cmd with power settings for all rates for current channel */
1564 /* Fill OFDM rate */
1565 for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0;
1566 rate_idx <= IWL39_LAST_OFDM_RATE; rate_idx++, i++) {
1568 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1569 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1571 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1572 le16_to_cpu(txpower.channel),
1574 txpower.power[i].tpc.tx_gain,
1575 txpower.power[i].tpc.dsp_atten,
1576 txpower.power[i].rate);
1578 /* Fill CCK rates */
1579 for (rate_idx = IWL_FIRST_CCK_RATE;
1580 rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) {
1581 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1582 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1584 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1585 le16_to_cpu(txpower.channel),
1587 txpower.power[i].tpc.tx_gain,
1588 txpower.power[i].tpc.dsp_atten,
1589 txpower.power[i].rate);
1592 return iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD,
1593 sizeof(struct iwl3945_txpowertable_cmd),
1599 * iwl3945_hw_reg_set_new_power - Configures power tables at new levels
1600 * @ch_info: Channel to update. Uses power_info.requested_power.
1602 * Replace requested_power and base_power_index ch_info fields for
1605 * Called if user or spectrum management changes power preferences.
1606 * Takes into account h/w and modulation limitations (clip power).
1608 * This does *not* send anything to NIC, just sets up ch_info for one channel.
1610 * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1611 * properly fill out the scan powers, and actual h/w gain settings,
1612 * and send changes to NIC
1614 static int iwl3945_hw_reg_set_new_power(struct iwl_priv *priv,
1615 struct iwl_channel_info *ch_info)
1617 struct iwl3945_channel_power_info *power_info;
1618 int power_changed = 0;
1620 const s8 *clip_pwrs;
1623 /* Get this chnlgrp's rate-to-max/clip-powers table */
1624 clip_pwrs = priv->_3945.clip_groups[ch_info->group_index].clip_powers;
1626 /* Get this channel's rate-to-current-power settings table */
1627 power_info = ch_info->power_info;
1629 /* update OFDM Txpower settings */
1630 for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE;
1631 i++, ++power_info) {
1634 /* limit new power to be no more than h/w capability */
1635 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1636 if (power == power_info->requested_power)
1639 /* find difference between old and new requested powers,
1640 * update base (non-temp-compensated) power index */
1641 delta_idx = (power - power_info->requested_power) * 2;
1642 power_info->base_power_index -= delta_idx;
1644 /* save new requested power value */
1645 power_info->requested_power = power;
1650 /* update CCK Txpower settings, based on OFDM 12M setting ...
1651 * ... all CCK power settings for a given channel are the *same*. */
1652 if (power_changed) {
1654 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1655 requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF;
1657 /* do all CCK rates' iwl3945_channel_power_info structures */
1658 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) {
1659 power_info->requested_power = power;
1660 power_info->base_power_index =
1661 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1662 base_power_index + IWL_CCK_FROM_OFDM_INDEX_DIFF;
1671 * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
1673 * NOTE: Returned power limit may be less (but not more) than requested,
1674 * based strictly on regulatory (eeprom and spectrum mgt) limitations
1675 * (no consideration for h/w clipping limitations).
1677 static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl_channel_info *ch_info)
1682 /* if we're using TGd limits, use lower of TGd or EEPROM */
1683 if (ch_info->tgd_data.max_power != 0)
1684 max_power = min(ch_info->tgd_data.max_power,
1685 ch_info->eeprom.max_power_avg);
1687 /* else just use EEPROM limits */
1690 max_power = ch_info->eeprom.max_power_avg;
1692 return min(max_power, ch_info->max_power_avg);
1696 * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature
1698 * Compensate txpower settings of *all* channels for temperature.
1699 * This only accounts for the difference between current temperature
1700 * and the factory calibration temperatures, and bases the new settings
1701 * on the channel's base_power_index.
1703 * If RxOn is "associated", this sends the new Txpower to NIC!
1705 static int iwl3945_hw_reg_comp_txpower_temp(struct iwl_priv *priv)
1707 struct iwl_channel_info *ch_info = NULL;
1708 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1710 const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
1716 int temperature = priv->temperature;
1718 /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1719 for (i = 0; i < priv->channel_count; i++) {
1720 ch_info = &priv->channel_info[i];
1721 a_band = is_channel_a_band(ch_info);
1723 /* Get this chnlgrp's factory calibration temperature */
1724 ref_temp = (s16)eeprom->groups[ch_info->group_index].
1727 /* get power index adjustment based on current and factory
1729 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
1732 /* set tx power value for all rates, OFDM and CCK */
1733 for (rate_index = 0; rate_index < IWL_RATE_COUNT;
1736 ch_info->power_info[rate_index].base_power_index;
1738 /* temperature compensate */
1739 power_idx += delta_index;
1741 /* stay within table range */
1742 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
1743 ch_info->power_info[rate_index].
1744 power_table_index = (u8) power_idx;
1745 ch_info->power_info[rate_index].tpc =
1746 power_gain_table[a_band][power_idx];
1749 /* Get this chnlgrp's rate-to-max/clip-powers table */
1750 clip_pwrs = priv->_3945.clip_groups[ch_info->group_index].clip_powers;
1752 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1753 for (scan_tbl_index = 0;
1754 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
1755 s32 actual_index = (scan_tbl_index == 0) ?
1756 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
1757 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
1758 actual_index, clip_pwrs,
1763 /* send Txpower command for current channel to ucode */
1764 return priv->cfg->ops->lib->send_tx_power(priv);
1767 int iwl3945_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
1769 struct iwl_channel_info *ch_info;
1774 if (priv->tx_power_user_lmt == power) {
1775 IWL_DEBUG_POWER(priv, "Requested Tx power same as current "
1776 "limit: %ddBm.\n", power);
1780 IWL_DEBUG_POWER(priv, "Setting upper limit clamp to %ddBm.\n", power);
1781 priv->tx_power_user_lmt = power;
1783 /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1785 for (i = 0; i < priv->channel_count; i++) {
1786 ch_info = &priv->channel_info[i];
1787 a_band = is_channel_a_band(ch_info);
1789 /* find minimum power of all user and regulatory constraints
1790 * (does not consider h/w clipping limitations) */
1791 max_power = iwl3945_hw_reg_get_ch_txpower_limit(ch_info);
1792 max_power = min(power, max_power);
1793 if (max_power != ch_info->curr_txpow) {
1794 ch_info->curr_txpow = max_power;
1796 /* this considers the h/w clipping limitations */
1797 iwl3945_hw_reg_set_new_power(priv, ch_info);
1801 /* update txpower settings for all channels,
1802 * send to NIC if associated. */
1803 is_temp_calib_needed(priv);
1804 iwl3945_hw_reg_comp_txpower_temp(priv);
1809 static int iwl3945_send_rxon_assoc(struct iwl_priv *priv)
1812 struct iwl_rx_packet *pkt;
1813 struct iwl3945_rxon_assoc_cmd rxon_assoc;
1814 struct iwl_host_cmd cmd = {
1815 .id = REPLY_RXON_ASSOC,
1816 .len = sizeof(rxon_assoc),
1817 .flags = CMD_WANT_SKB,
1818 .data = &rxon_assoc,
1820 const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1821 const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1823 if ((rxon1->flags == rxon2->flags) &&
1824 (rxon1->filter_flags == rxon2->filter_flags) &&
1825 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1826 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1827 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC. Not resending.\n");
1831 rxon_assoc.flags = priv->staging_rxon.flags;
1832 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1833 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1834 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1835 rxon_assoc.reserved = 0;
1837 rc = iwl_send_cmd_sync(priv, &cmd);
1841 pkt = (struct iwl_rx_packet *)cmd.reply_page;
1842 if (pkt->hdr.flags & IWL_CMD_FAILED_MSK) {
1843 IWL_ERR(priv, "Bad return from REPLY_RXON_ASSOC command\n");
1847 iwl_free_pages(priv, cmd.reply_page);
1853 * iwl3945_commit_rxon - commit staging_rxon to hardware
1855 * The RXON command in staging_rxon is committed to the hardware and
1856 * the active_rxon structure is updated with the new data. This
1857 * function correctly transitions out of the RXON_ASSOC_MSK state if
1858 * a HW tune is required based on the RXON structure changes.
1860 static int iwl3945_commit_rxon(struct iwl_priv *priv)
1862 /* cast away the const for active_rxon in this function */
1863 struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
1864 struct iwl3945_rxon_cmd *staging_rxon = (void *)&priv->staging_rxon;
1867 !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
1869 if (!iwl_is_alive(priv))
1872 /* always get timestamp with Rx frame */
1873 staging_rxon->flags |= RXON_FLG_TSF2HOST_MSK;
1875 /* select antenna */
1876 staging_rxon->flags &=
1877 ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
1878 staging_rxon->flags |= iwl3945_get_antenna_flags(priv);
1880 rc = iwl_check_rxon_cmd(priv);
1882 IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
1886 /* If we don't need to send a full RXON, we can use
1887 * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
1888 * and other flags for the current radio configuration. */
1889 if (!iwl_full_rxon_required(priv)) {
1890 rc = iwl_send_rxon_assoc(priv);
1892 IWL_ERR(priv, "Error setting RXON_ASSOC "
1893 "configuration (%d).\n", rc);
1897 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1902 /* If we are currently associated and the new config requires
1903 * an RXON_ASSOC and the new config wants the associated mask enabled,
1904 * we must clear the associated from the active configuration
1905 * before we apply the new config */
1906 if (iwl_is_associated(priv) && new_assoc) {
1907 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
1908 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1911 * reserved4 and 5 could have been filled by the iwlcore code.
1912 * Let's clear them before pushing to the 3945.
1914 active_rxon->reserved4 = 0;
1915 active_rxon->reserved5 = 0;
1916 rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
1917 sizeof(struct iwl3945_rxon_cmd),
1918 &priv->active_rxon);
1920 /* If the mask clearing failed then we set
1921 * active_rxon back to what it was previously */
1923 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
1924 IWL_ERR(priv, "Error clearing ASSOC_MSK on current "
1925 "configuration (%d).\n", rc);
1928 iwl_clear_ucode_stations(priv, false);
1929 iwl_restore_stations(priv);
1932 IWL_DEBUG_INFO(priv, "Sending RXON\n"
1933 "* with%s RXON_FILTER_ASSOC_MSK\n"
1936 (new_assoc ? "" : "out"),
1937 le16_to_cpu(staging_rxon->channel),
1938 staging_rxon->bssid_addr);
1941 * reserved4 and 5 could have been filled by the iwlcore code.
1942 * Let's clear them before pushing to the 3945.
1944 staging_rxon->reserved4 = 0;
1945 staging_rxon->reserved5 = 0;
1947 iwl_set_rxon_hwcrypto(priv, !iwl3945_mod_params.sw_crypto);
1949 /* Apply the new configuration */
1950 rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
1951 sizeof(struct iwl3945_rxon_cmd),
1954 IWL_ERR(priv, "Error setting new configuration (%d).\n", rc);
1958 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1961 iwl_clear_ucode_stations(priv, false);
1962 iwl_restore_stations(priv);
1965 /* If we issue a new RXON command which required a tune then we must
1966 * send a new TXPOWER command or we won't be able to Tx any frames */
1967 rc = priv->cfg->ops->lib->send_tx_power(priv);
1969 IWL_ERR(priv, "Error setting Tx power (%d).\n", rc);
1973 /* Init the hardware's rate fallback order based on the band */
1974 rc = iwl3945_init_hw_rate_table(priv);
1976 IWL_ERR(priv, "Error setting HW rate table: %02X\n", rc);
1984 * iwl3945_reg_txpower_periodic - called when time to check our temperature.
1986 * -- reset periodic timer
1987 * -- see if temp has changed enough to warrant re-calibration ... if so:
1988 * -- correct coeffs for temp (can reset temp timer)
1989 * -- save this temp as "last",
1990 * -- send new set of gain settings to NIC
1991 * NOTE: This should continue working, even when we're not associated,
1992 * so we can keep our internal table of scan powers current. */
1993 void iwl3945_reg_txpower_periodic(struct iwl_priv *priv)
1995 /* This will kick in the "brute force"
1996 * iwl3945_hw_reg_comp_txpower_temp() below */
1997 if (!is_temp_calib_needed(priv))
2000 /* Set up a new set of temp-adjusted TxPowers, send to NIC.
2001 * This is based *only* on current temperature,
2002 * ignoring any previous power measurements */
2003 iwl3945_hw_reg_comp_txpower_temp(priv);
2006 queue_delayed_work(priv->workqueue,
2007 &priv->_3945.thermal_periodic, REG_RECALIB_PERIOD * HZ);
2010 static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work)
2012 struct iwl_priv *priv = container_of(work, struct iwl_priv,
2013 _3945.thermal_periodic.work);
2015 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2018 mutex_lock(&priv->mutex);
2019 iwl3945_reg_txpower_periodic(priv);
2020 mutex_unlock(&priv->mutex);
2024 * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
2027 * This function is used when initializing channel-info structs.
2029 * NOTE: These channel groups do *NOT* match the bands above!
2030 * These channel groups are based on factory-tested channels;
2031 * on A-band, EEPROM's "group frequency" entries represent the top
2032 * channel in each group 1-4. Group 5 All B/G channels are in group 0.
2034 static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl_priv *priv,
2035 const struct iwl_channel_info *ch_info)
2037 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2038 struct iwl3945_eeprom_txpower_group *ch_grp = &eeprom->groups[0];
2040 u16 group_index = 0; /* based on factory calib frequencies */
2043 /* Find the group index for the channel ... don't use index 1(?) */
2044 if (is_channel_a_band(ch_info)) {
2045 for (group = 1; group < 5; group++) {
2046 grp_channel = ch_grp[group].group_channel;
2047 if (ch_info->channel <= grp_channel) {
2048 group_index = group;
2052 /* group 4 has a few channels *above* its factory cal freq */
2056 group_index = 0; /* 2.4 GHz, group 0 */
2058 IWL_DEBUG_POWER(priv, "Chnl %d mapped to grp %d\n", ch_info->channel,
2064 * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index
2066 * Interpolate to get nominal (i.e. at factory calibration temperature) index
2067 * into radio/DSP gain settings table for requested power.
2069 static int iwl3945_hw_reg_get_matched_power_index(struct iwl_priv *priv,
2071 s32 setting_index, s32 *new_index)
2073 const struct iwl3945_eeprom_txpower_group *chnl_grp = NULL;
2074 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2076 s32 power = 2 * requested_power;
2078 const struct iwl3945_eeprom_txpower_sample *samples;
2083 chnl_grp = &eeprom->groups[setting_index];
2084 samples = chnl_grp->samples;
2085 for (i = 0; i < 5; i++) {
2086 if (power == samples[i].power) {
2087 *new_index = samples[i].gain_index;
2092 if (power > samples[1].power) {
2095 } else if (power > samples[2].power) {
2098 } else if (power > samples[3].power) {
2106 denominator = (s32) samples[index1].power - (s32) samples[index0].power;
2107 if (denominator == 0)
2109 gains0 = (s32) samples[index0].gain_index * (1 << 19);
2110 gains1 = (s32) samples[index1].gain_index * (1 << 19);
2111 res = gains0 + (gains1 - gains0) *
2112 ((s32) power - (s32) samples[index0].power) / denominator +
2114 *new_index = res >> 19;
2118 static void iwl3945_hw_reg_init_channel_groups(struct iwl_priv *priv)
2122 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2123 const struct iwl3945_eeprom_txpower_group *group;
2125 IWL_DEBUG_POWER(priv, "Initializing factory calib info from EEPROM\n");
2127 for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) {
2128 s8 *clip_pwrs; /* table of power levels for each rate */
2129 s8 satur_pwr; /* saturation power for each chnl group */
2130 group = &eeprom->groups[i];
2132 /* sanity check on factory saturation power value */
2133 if (group->saturation_power < 40) {
2134 IWL_WARN(priv, "Error: saturation power is %d, "
2135 "less than minimum expected 40\n",
2136 group->saturation_power);
2141 * Derive requested power levels for each rate, based on
2142 * hardware capabilities (saturation power for band).
2143 * Basic value is 3dB down from saturation, with further
2144 * power reductions for highest 3 data rates. These
2145 * backoffs provide headroom for high rate modulation
2146 * power peaks, without too much distortion (clipping).
2148 /* we'll fill in this array with h/w max power levels */
2149 clip_pwrs = (s8 *) priv->_3945.clip_groups[i].clip_powers;
2151 /* divide factory saturation power by 2 to find -3dB level */
2152 satur_pwr = (s8) (group->saturation_power >> 1);
2154 /* fill in channel group's nominal powers for each rate */
2155 for (rate_index = 0;
2156 rate_index < IWL_RATE_COUNT_3945; rate_index++, clip_pwrs++) {
2157 switch (rate_index) {
2158 case IWL_RATE_36M_INDEX_TABLE:
2159 if (i == 0) /* B/G */
2160 *clip_pwrs = satur_pwr;
2162 *clip_pwrs = satur_pwr - 5;
2164 case IWL_RATE_48M_INDEX_TABLE:
2166 *clip_pwrs = satur_pwr - 7;
2168 *clip_pwrs = satur_pwr - 10;
2170 case IWL_RATE_54M_INDEX_TABLE:
2172 *clip_pwrs = satur_pwr - 9;
2174 *clip_pwrs = satur_pwr - 12;
2177 *clip_pwrs = satur_pwr;
2185 * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2187 * Second pass (during init) to set up priv->channel_info
2189 * Set up Tx-power settings in our channel info database for each VALID
2190 * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2191 * and current temperature.
2193 * Since this is based on current temperature (at init time), these values may
2194 * not be valid for very long, but it gives us a starting/default point,
2195 * and allows us to active (i.e. using Tx) scan.
2197 * This does *not* write values to NIC, just sets up our internal table.
2199 int iwl3945_txpower_set_from_eeprom(struct iwl_priv *priv)
2201 struct iwl_channel_info *ch_info = NULL;
2202 struct iwl3945_channel_power_info *pwr_info;
2203 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2207 const s8 *clip_pwrs; /* array of power levels for each rate */
2210 u8 pwr_index, base_pwr_index, a_band;
2214 /* save temperature reference,
2215 * so we can determine next time to calibrate */
2216 temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
2217 priv->last_temperature = temperature;
2219 iwl3945_hw_reg_init_channel_groups(priv);
2221 /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2222 for (i = 0, ch_info = priv->channel_info; i < priv->channel_count;
2224 a_band = is_channel_a_band(ch_info);
2225 if (!is_channel_valid(ch_info))
2228 /* find this channel's channel group (*not* "band") index */
2229 ch_info->group_index =
2230 iwl3945_hw_reg_get_ch_grp_index(priv, ch_info);
2232 /* Get this chnlgrp's rate->max/clip-powers table */
2233 clip_pwrs = priv->_3945.clip_groups[ch_info->group_index].clip_powers;
2235 /* calculate power index *adjustment* value according to
2236 * diff between current temperature and factory temperature */
2237 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
2238 eeprom->groups[ch_info->group_index].
2241 IWL_DEBUG_POWER(priv, "Delta index for channel %d: %d [%d]\n",
2242 ch_info->channel, delta_index, temperature +
2245 /* set tx power value for all OFDM rates */
2246 for (rate_index = 0; rate_index < IWL_OFDM_RATES;
2248 s32 uninitialized_var(power_idx);
2251 /* use channel group's clip-power table,
2252 * but don't exceed channel's max power */
2253 s8 pwr = min(ch_info->max_power_avg,
2254 clip_pwrs[rate_index]);
2256 pwr_info = &ch_info->power_info[rate_index];
2258 /* get base (i.e. at factory-measured temperature)
2259 * power table index for this rate's power */
2260 rc = iwl3945_hw_reg_get_matched_power_index(priv, pwr,
2261 ch_info->group_index,
2264 IWL_ERR(priv, "Invalid power index\n");
2267 pwr_info->base_power_index = (u8) power_idx;
2269 /* temperature compensate */
2270 power_idx += delta_index;
2272 /* stay within range of gain table */
2273 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
2275 /* fill 1 OFDM rate's iwl3945_channel_power_info struct */
2276 pwr_info->requested_power = pwr;
2277 pwr_info->power_table_index = (u8) power_idx;
2278 pwr_info->tpc.tx_gain =
2279 power_gain_table[a_band][power_idx].tx_gain;
2280 pwr_info->tpc.dsp_atten =
2281 power_gain_table[a_band][power_idx].dsp_atten;
2284 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
2285 pwr_info = &ch_info->power_info[IWL_RATE_12M_INDEX_TABLE];
2286 power = pwr_info->requested_power +
2287 IWL_CCK_FROM_OFDM_POWER_DIFF;
2288 pwr_index = pwr_info->power_table_index +
2289 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2290 base_pwr_index = pwr_info->base_power_index +
2291 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2293 /* stay within table range */
2294 pwr_index = iwl3945_hw_reg_fix_power_index(pwr_index);
2295 gain = power_gain_table[a_band][pwr_index].tx_gain;
2296 dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten;
2298 /* fill each CCK rate's iwl3945_channel_power_info structure
2299 * NOTE: All CCK-rate Txpwrs are the same for a given chnl!
2300 * NOTE: CCK rates start at end of OFDM rates! */
2301 for (rate_index = 0;
2302 rate_index < IWL_CCK_RATES; rate_index++) {
2303 pwr_info = &ch_info->power_info[rate_index+IWL_OFDM_RATES];
2304 pwr_info->requested_power = power;
2305 pwr_info->power_table_index = pwr_index;
2306 pwr_info->base_power_index = base_pwr_index;
2307 pwr_info->tpc.tx_gain = gain;
2308 pwr_info->tpc.dsp_atten = dsp_atten;
2311 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2312 for (scan_tbl_index = 0;
2313 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
2314 s32 actual_index = (scan_tbl_index == 0) ?
2315 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
2316 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
2317 actual_index, clip_pwrs, ch_info, a_band);
2324 int iwl3945_hw_rxq_stop(struct iwl_priv *priv)
2328 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0), 0);
2329 rc = iwl_poll_direct_bit(priv, FH39_RSSR_STATUS,
2330 FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
2332 IWL_ERR(priv, "Can't stop Rx DMA.\n");
2337 int iwl3945_hw_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq)
2339 int txq_id = txq->q.id;
2341 struct iwl3945_shared *shared_data = priv->_3945.shared_virt;
2343 shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2345 iwl_write_direct32(priv, FH39_CBCC_CTRL(txq_id), 0);
2346 iwl_write_direct32(priv, FH39_CBCC_BASE(txq_id), 0);
2348 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id),
2349 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2350 FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2351 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2352 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2353 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
2355 /* fake read to flush all prev. writes */
2356 iwl_read32(priv, FH39_TSSR_CBB_BASE);
2364 static u16 iwl3945_get_hcmd_size(u8 cmd_id, u16 len)
2368 return sizeof(struct iwl3945_rxon_cmd);
2369 case POWER_TABLE_CMD:
2370 return sizeof(struct iwl3945_powertable_cmd);
2377 static u16 iwl3945_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
2379 struct iwl3945_addsta_cmd *addsta = (struct iwl3945_addsta_cmd *)data;
2380 addsta->mode = cmd->mode;
2381 memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify));
2382 memcpy(&addsta->key, &cmd->key, sizeof(struct iwl4965_keyinfo));
2383 addsta->station_flags = cmd->station_flags;
2384 addsta->station_flags_msk = cmd->station_flags_msk;
2385 addsta->tid_disable_tx = cpu_to_le16(0);
2386 addsta->rate_n_flags = cmd->rate_n_flags;
2387 addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid;
2388 addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid;
2389 addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn;
2391 return (u16)sizeof(struct iwl3945_addsta_cmd);
2396 * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2398 int iwl3945_init_hw_rate_table(struct iwl_priv *priv)
2400 int rc, i, index, prev_index;
2401 struct iwl3945_rate_scaling_cmd rate_cmd = {
2402 .reserved = {0, 0, 0},
2404 struct iwl3945_rate_scaling_info *table = rate_cmd.table;
2406 for (i = 0; i < ARRAY_SIZE(iwl3945_rates); i++) {
2407 index = iwl3945_rates[i].table_rs_index;
2409 table[index].rate_n_flags =
2410 iwl3945_hw_set_rate_n_flags(iwl3945_rates[i].plcp, 0);
2411 table[index].try_cnt = priv->retry_rate;
2412 prev_index = iwl3945_get_prev_ieee_rate(i);
2413 table[index].next_rate_index =
2414 iwl3945_rates[prev_index].table_rs_index;
2417 switch (priv->band) {
2418 case IEEE80211_BAND_5GHZ:
2419 IWL_DEBUG_RATE(priv, "Select A mode rate scale\n");
2420 /* If one of the following CCK rates is used,
2421 * have it fall back to the 6M OFDM rate */
2422 for (i = IWL_RATE_1M_INDEX_TABLE;
2423 i <= IWL_RATE_11M_INDEX_TABLE; i++)
2424 table[i].next_rate_index =
2425 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2427 /* Don't fall back to CCK rates */
2428 table[IWL_RATE_12M_INDEX_TABLE].next_rate_index =
2429 IWL_RATE_9M_INDEX_TABLE;
2431 /* Don't drop out of OFDM rates */
2432 table[IWL_RATE_6M_INDEX_TABLE].next_rate_index =
2433 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2436 case IEEE80211_BAND_2GHZ:
2437 IWL_DEBUG_RATE(priv, "Select B/G mode rate scale\n");
2438 /* If an OFDM rate is used, have it fall back to the
2441 if (!(priv->_3945.sta_supp_rates & IWL_OFDM_RATES_MASK) &&
2442 iwl_is_associated(priv)) {
2444 index = IWL_FIRST_CCK_RATE;
2445 for (i = IWL_RATE_6M_INDEX_TABLE;
2446 i <= IWL_RATE_54M_INDEX_TABLE; i++)
2447 table[i].next_rate_index =
2448 iwl3945_rates[index].table_rs_index;
2450 index = IWL_RATE_11M_INDEX_TABLE;
2451 /* CCK shouldn't fall back to OFDM... */
2452 table[index].next_rate_index = IWL_RATE_5M_INDEX_TABLE;
2461 /* Update the rate scaling for control frame Tx */
2462 rate_cmd.table_id = 0;
2463 rc = iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2468 /* Update the rate scaling for data frame Tx */
2469 rate_cmd.table_id = 1;
2470 return iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2474 /* Called when initializing driver */
2475 int iwl3945_hw_set_hw_params(struct iwl_priv *priv)
2477 memset((void *)&priv->hw_params, 0,
2478 sizeof(struct iwl_hw_params));
2480 priv->_3945.shared_virt =
2481 dma_alloc_coherent(&priv->pci_dev->dev,
2482 sizeof(struct iwl3945_shared),
2483 &priv->_3945.shared_phys, GFP_KERNEL);
2484 if (!priv->_3945.shared_virt) {
2485 IWL_ERR(priv, "failed to allocate pci memory\n");
2486 mutex_unlock(&priv->mutex);
2490 /* Assign number of Usable TX queues */
2491 priv->hw_params.max_txq_num = priv->cfg->num_of_queues;
2493 priv->hw_params.tfd_size = sizeof(struct iwl3945_tfd);
2494 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_3K);
2495 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
2496 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
2497 priv->hw_params.max_stations = IWL3945_STATION_COUNT;
2498 priv->hw_params.bcast_sta_id = IWL3945_BROADCAST_ID;
2500 priv->hw_params.rx_wrt_ptr_reg = FH39_RSCSR_CHNL0_WPTR;
2501 priv->hw_params.max_beacon_itrvl = IWL39_MAX_UCODE_BEACON_INTERVAL;
2506 unsigned int iwl3945_hw_get_beacon_cmd(struct iwl_priv *priv,
2507 struct iwl3945_frame *frame, u8 rate)
2509 struct iwl3945_tx_beacon_cmd *tx_beacon_cmd;
2510 unsigned int frame_size;
2512 tx_beacon_cmd = (struct iwl3945_tx_beacon_cmd *)&frame->u;
2513 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2515 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
2516 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2518 frame_size = iwl3945_fill_beacon_frame(priv,
2519 tx_beacon_cmd->frame,
2520 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2522 BUG_ON(frame_size > MAX_MPDU_SIZE);
2523 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2525 tx_beacon_cmd->tx.rate = rate;
2526 tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2527 TX_CMD_FLG_TSF_MSK);
2529 /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
2530 tx_beacon_cmd->tx.supp_rates[0] =
2531 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2533 tx_beacon_cmd->tx.supp_rates[1] =
2534 (IWL_CCK_BASIC_RATES_MASK & 0xF);
2536 return sizeof(struct iwl3945_tx_beacon_cmd) + frame_size;
2539 void iwl3945_hw_rx_handler_setup(struct iwl_priv *priv)
2541 priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
2542 priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx;
2545 void iwl3945_hw_setup_deferred_work(struct iwl_priv *priv)
2547 INIT_DELAYED_WORK(&priv->_3945.thermal_periodic,
2548 iwl3945_bg_reg_txpower_periodic);
2551 void iwl3945_hw_cancel_deferred_work(struct iwl_priv *priv)
2553 cancel_delayed_work(&priv->_3945.thermal_periodic);
2556 /* check contents of special bootstrap uCode SRAM */
2557 static int iwl3945_verify_bsm(struct iwl_priv *priv)
2559 __le32 *image = priv->ucode_boot.v_addr;
2560 u32 len = priv->ucode_boot.len;
2564 IWL_DEBUG_INFO(priv, "Begin verify bsm\n");
2566 /* verify BSM SRAM contents */
2567 val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
2568 for (reg = BSM_SRAM_LOWER_BOUND;
2569 reg < BSM_SRAM_LOWER_BOUND + len;
2570 reg += sizeof(u32), image++) {
2571 val = iwl_read_prph(priv, reg);
2572 if (val != le32_to_cpu(*image)) {
2573 IWL_ERR(priv, "BSM uCode verification failed at "
2574 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
2575 BSM_SRAM_LOWER_BOUND,
2576 reg - BSM_SRAM_LOWER_BOUND, len,
2577 val, le32_to_cpu(*image));
2582 IWL_DEBUG_INFO(priv, "BSM bootstrap uCode image OK\n");
2588 /******************************************************************************
2590 * EEPROM related functions
2592 ******************************************************************************/
2595 * Clear the OWNER_MSK, to establish driver (instead of uCode running on
2596 * embedded controller) as EEPROM reader; each read is a series of pulses
2597 * to/from the EEPROM chip, not a single event, so even reads could conflict
2598 * if they weren't arbitrated by some ownership mechanism. Here, the driver
2599 * simply claims ownership, which should be safe when this function is called
2600 * (i.e. before loading uCode!).
2602 static int iwl3945_eeprom_acquire_semaphore(struct iwl_priv *priv)
2604 _iwl_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
2609 static void iwl3945_eeprom_release_semaphore(struct iwl_priv *priv)
2615 * iwl3945_load_bsm - Load bootstrap instructions
2619 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
2620 * in special SRAM that does not power down during RFKILL. When powering back
2621 * up after power-saving sleeps (or during initial uCode load), the BSM loads
2622 * the bootstrap program into the on-board processor, and starts it.
2624 * The bootstrap program loads (via DMA) instructions and data for a new
2625 * program from host DRAM locations indicated by the host driver in the
2626 * BSM_DRAM_* registers. Once the new program is loaded, it starts
2629 * When initializing the NIC, the host driver points the BSM to the
2630 * "initialize" uCode image. This uCode sets up some internal data, then
2631 * notifies host via "initialize alive" that it is complete.
2633 * The host then replaces the BSM_DRAM_* pointer values to point to the
2634 * normal runtime uCode instructions and a backup uCode data cache buffer
2635 * (filled initially with starting data values for the on-board processor),
2636 * then triggers the "initialize" uCode to load and launch the runtime uCode,
2637 * which begins normal operation.
2639 * When doing a power-save shutdown, runtime uCode saves data SRAM into
2640 * the backup data cache in DRAM before SRAM is powered down.
2642 * When powering back up, the BSM loads the bootstrap program. This reloads
2643 * the runtime uCode instructions and the backup data cache into SRAM,
2644 * and re-launches the runtime uCode from where it left off.
2646 static int iwl3945_load_bsm(struct iwl_priv *priv)
2648 __le32 *image = priv->ucode_boot.v_addr;
2649 u32 len = priv->ucode_boot.len;
2659 IWL_DEBUG_INFO(priv, "Begin load bsm\n");
2661 /* make sure bootstrap program is no larger than BSM's SRAM size */
2662 if (len > IWL39_MAX_BSM_SIZE)
2665 /* Tell bootstrap uCode where to find the "Initialize" uCode
2666 * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
2667 * NOTE: iwl3945_initialize_alive_start() will replace these values,
2668 * after the "initialize" uCode has run, to point to
2669 * runtime/protocol instructions and backup data cache. */
2670 pinst = priv->ucode_init.p_addr;
2671 pdata = priv->ucode_init_data.p_addr;
2672 inst_len = priv->ucode_init.len;
2673 data_len = priv->ucode_init_data.len;
2675 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
2676 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
2677 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
2678 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
2680 /* Fill BSM memory with bootstrap instructions */
2681 for (reg_offset = BSM_SRAM_LOWER_BOUND;
2682 reg_offset < BSM_SRAM_LOWER_BOUND + len;
2683 reg_offset += sizeof(u32), image++)
2684 _iwl_write_prph(priv, reg_offset,
2685 le32_to_cpu(*image));
2687 rc = iwl3945_verify_bsm(priv);
2691 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
2692 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
2693 iwl_write_prph(priv, BSM_WR_MEM_DST_REG,
2694 IWL39_RTC_INST_LOWER_BOUND);
2695 iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
2697 /* Load bootstrap code into instruction SRAM now,
2698 * to prepare to load "initialize" uCode */
2699 iwl_write_prph(priv, BSM_WR_CTRL_REG,
2700 BSM_WR_CTRL_REG_BIT_START);
2702 /* Wait for load of bootstrap uCode to finish */
2703 for (i = 0; i < 100; i++) {
2704 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
2705 if (!(done & BSM_WR_CTRL_REG_BIT_START))
2710 IWL_DEBUG_INFO(priv, "BSM write complete, poll %d iterations\n", i);
2712 IWL_ERR(priv, "BSM write did not complete!\n");
2716 /* Enable future boot loads whenever power management unit triggers it
2717 * (e.g. when powering back up after power-save shutdown) */
2718 iwl_write_prph(priv, BSM_WR_CTRL_REG,
2719 BSM_WR_CTRL_REG_BIT_START_EN);
2724 #define IWL3945_UCODE_GET(item) \
2725 static u32 iwl3945_ucode_get_##item(const struct iwl_ucode_header *ucode,\
2728 return le32_to_cpu(ucode->u.v1.item); \
2731 static u32 iwl3945_ucode_get_header_size(u32 api_ver)
2733 return UCODE_HEADER_SIZE(1);
2735 static u32 iwl3945_ucode_get_build(const struct iwl_ucode_header *ucode,
2740 static u8 *iwl3945_ucode_get_data(const struct iwl_ucode_header *ucode,
2743 return (u8 *) ucode->u.v1.data;
2746 IWL3945_UCODE_GET(inst_size);
2747 IWL3945_UCODE_GET(data_size);
2748 IWL3945_UCODE_GET(init_size);
2749 IWL3945_UCODE_GET(init_data_size);
2750 IWL3945_UCODE_GET(boot_size);
2752 static struct iwl_hcmd_ops iwl3945_hcmd = {
2753 .rxon_assoc = iwl3945_send_rxon_assoc,
2754 .commit_rxon = iwl3945_commit_rxon,
2755 .send_bt_config = iwl_send_bt_config,
2758 static struct iwl_ucode_ops iwl3945_ucode = {
2759 .get_header_size = iwl3945_ucode_get_header_size,
2760 .get_build = iwl3945_ucode_get_build,
2761 .get_inst_size = iwl3945_ucode_get_inst_size,
2762 .get_data_size = iwl3945_ucode_get_data_size,
2763 .get_init_size = iwl3945_ucode_get_init_size,
2764 .get_init_data_size = iwl3945_ucode_get_init_data_size,
2765 .get_boot_size = iwl3945_ucode_get_boot_size,
2766 .get_data = iwl3945_ucode_get_data,
2769 static struct iwl_lib_ops iwl3945_lib = {
2770 .txq_attach_buf_to_tfd = iwl3945_hw_txq_attach_buf_to_tfd,
2771 .txq_free_tfd = iwl3945_hw_txq_free_tfd,
2772 .txq_init = iwl3945_hw_tx_queue_init,
2773 .load_ucode = iwl3945_load_bsm,
2774 .dump_nic_event_log = iwl3945_dump_nic_event_log,
2775 .dump_nic_error_log = iwl3945_dump_nic_error_log,
2777 .init = iwl3945_apm_init,
2778 .stop = iwl_apm_stop,
2779 .config = iwl3945_nic_config,
2780 .set_pwr_src = iwl3945_set_pwr_src,
2783 .regulatory_bands = {
2784 EEPROM_REGULATORY_BAND_1_CHANNELS,
2785 EEPROM_REGULATORY_BAND_2_CHANNELS,
2786 EEPROM_REGULATORY_BAND_3_CHANNELS,
2787 EEPROM_REGULATORY_BAND_4_CHANNELS,
2788 EEPROM_REGULATORY_BAND_5_CHANNELS,
2789 EEPROM_REGULATORY_BAND_NO_HT40,
2790 EEPROM_REGULATORY_BAND_NO_HT40,
2792 .verify_signature = iwlcore_eeprom_verify_signature,
2793 .acquire_semaphore = iwl3945_eeprom_acquire_semaphore,
2794 .release_semaphore = iwl3945_eeprom_release_semaphore,
2795 .query_addr = iwlcore_eeprom_query_addr,
2797 .send_tx_power = iwl3945_send_tx_power,
2798 .is_valid_rtc_data_addr = iwl3945_hw_valid_rtc_data_addr,
2799 .post_associate = iwl3945_post_associate,
2800 .isr = iwl_isr_legacy,
2801 .config_ap = iwl3945_config_ap,
2802 .add_bcast_station = iwl3945_add_bcast_station,
2805 .rx_stats_read = iwl3945_ucode_rx_stats_read,
2806 .tx_stats_read = iwl3945_ucode_tx_stats_read,
2807 .general_stats_read = iwl3945_ucode_general_stats_read,
2811 static struct iwl_hcmd_utils_ops iwl3945_hcmd_utils = {
2812 .get_hcmd_size = iwl3945_get_hcmd_size,
2813 .build_addsta_hcmd = iwl3945_build_addsta_hcmd,
2814 .rts_tx_cmd_flag = iwlcore_rts_tx_cmd_flag,
2815 .request_scan = iwl3945_request_scan,
2818 static const struct iwl_ops iwl3945_ops = {
2819 .ucode = &iwl3945_ucode,
2820 .lib = &iwl3945_lib,
2821 .hcmd = &iwl3945_hcmd,
2822 .utils = &iwl3945_hcmd_utils,
2823 .led = &iwl3945_led_ops,
2826 static struct iwl_cfg iwl3945_bg_cfg = {
2828 .fw_name_pre = IWL3945_FW_PRE,
2829 .ucode_api_max = IWL3945_UCODE_API_MAX,
2830 .ucode_api_min = IWL3945_UCODE_API_MIN,
2832 .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2833 .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
2834 .ops = &iwl3945_ops,
2835 .num_of_queues = IWL39_NUM_QUEUES,
2836 .mod_params = &iwl3945_mod_params,
2837 .pll_cfg_val = CSR39_ANA_PLL_CFG_VAL,
2840 .use_isr_legacy = true,
2841 .ht_greenfield_support = false,
2842 .led_compensation = 64,
2843 .broken_powersave = true,
2844 .plcp_delta_threshold = IWL_MAX_PLCP_ERR_THRESHOLD_DEF,
2845 .monitor_recover_period = IWL_MONITORING_PERIOD,
2846 .max_event_log_size = 512,
2849 static struct iwl_cfg iwl3945_abg_cfg = {
2851 .fw_name_pre = IWL3945_FW_PRE,
2852 .ucode_api_max = IWL3945_UCODE_API_MAX,
2853 .ucode_api_min = IWL3945_UCODE_API_MIN,
2854 .sku = IWL_SKU_A|IWL_SKU_G,
2855 .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2856 .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
2857 .ops = &iwl3945_ops,
2858 .num_of_queues = IWL39_NUM_QUEUES,
2859 .mod_params = &iwl3945_mod_params,
2860 .use_isr_legacy = true,
2861 .ht_greenfield_support = false,
2862 .led_compensation = 64,
2863 .broken_powersave = true,
2864 .plcp_delta_threshold = IWL_MAX_PLCP_ERR_THRESHOLD_DEF,
2865 .monitor_recover_period = IWL_MONITORING_PERIOD,
2866 .max_event_log_size = 512,
2869 DEFINE_PCI_DEVICE_TABLE(iwl3945_hw_card_ids) = {
2870 {IWL_PCI_DEVICE(0x4222, 0x1005, iwl3945_bg_cfg)},
2871 {IWL_PCI_DEVICE(0x4222, 0x1034, iwl3945_bg_cfg)},
2872 {IWL_PCI_DEVICE(0x4222, 0x1044, iwl3945_bg_cfg)},
2873 {IWL_PCI_DEVICE(0x4227, 0x1014, iwl3945_bg_cfg)},
2874 {IWL_PCI_DEVICE(0x4222, PCI_ANY_ID, iwl3945_abg_cfg)},
2875 {IWL_PCI_DEVICE(0x4227, PCI_ANY_ID, iwl3945_abg_cfg)},
2879 MODULE_DEVICE_TABLE(pci, iwl3945_hw_card_ids);