1 /******************************************************************************
3 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *****************************************************************************/
30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
32 #include <linux/kernel.h>
33 #include <linux/module.h>
34 #include <linux/init.h>
35 #include <linux/pci.h>
36 #include <linux/pci-aspm.h>
37 #include <linux/slab.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/delay.h>
40 #include <linux/sched.h>
41 #include <linux/skbuff.h>
42 #include <linux/netdevice.h>
43 #include <linux/firmware.h>
44 #include <linux/etherdevice.h>
45 #include <linux/if_arp.h>
47 #include <net/mac80211.h>
49 #include <asm/div64.h>
51 #define DRV_NAME "iwl4965"
56 /******************************************************************************
60 ******************************************************************************/
63 * module name, copyright, version, etc.
65 #define DRV_DESCRIPTION "Intel(R) Wireless WiFi 4965 driver for Linux"
67 #ifdef CONFIG_IWLEGACY_DEBUG
73 #define DRV_VERSION IWLWIFI_VERSION VD
75 MODULE_DESCRIPTION(DRV_DESCRIPTION);
76 MODULE_VERSION(DRV_VERSION);
77 MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
78 MODULE_LICENSE("GPL");
79 MODULE_ALIAS("iwl4965");
82 il4965_check_abort_status(struct il_priv *il, u8 frame_count, u32 status)
84 if (frame_count == 1 && status == TX_STATUS_FAIL_RFKILL_FLUSH) {
85 IL_ERR("Tx flush command to flush out all frames\n");
86 if (!test_bit(S_EXIT_PENDING, &il->status))
87 queue_work(il->workqueue, &il->tx_flush);
94 struct il_mod_params il4965_mod_params = {
97 /* the rest are 0 by default */
101 il4965_rx_queue_reset(struct il_priv *il, struct il_rx_queue *rxq)
105 spin_lock_irqsave(&rxq->lock, flags);
106 INIT_LIST_HEAD(&rxq->rx_free);
107 INIT_LIST_HEAD(&rxq->rx_used);
108 /* Fill the rx_used queue with _all_ of the Rx buffers */
109 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
110 /* In the reset function, these buffers may have been allocated
111 * to an SKB, so we need to unmap and free potential storage */
112 if (rxq->pool[i].page != NULL) {
113 pci_unmap_page(il->pci_dev, rxq->pool[i].page_dma,
114 PAGE_SIZE << il->hw_params.rx_page_order,
116 __il_free_pages(il, rxq->pool[i].page);
117 rxq->pool[i].page = NULL;
119 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
122 for (i = 0; i < RX_QUEUE_SIZE; i++)
123 rxq->queue[i] = NULL;
125 /* Set us so that we have processed and used all buffers, but have
126 * not restocked the Rx queue with fresh buffers */
127 rxq->read = rxq->write = 0;
128 rxq->write_actual = 0;
130 spin_unlock_irqrestore(&rxq->lock, flags);
134 il4965_rx_init(struct il_priv *il, struct il_rx_queue *rxq)
137 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
140 if (il->cfg->mod_params->amsdu_size_8K)
141 rb_size = FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
143 rb_size = FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
146 il_wr(il, FH49_MEM_RCSR_CHNL0_CONFIG_REG, 0);
148 /* Reset driver's Rx queue write idx */
149 il_wr(il, FH49_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
151 /* Tell device where to find RBD circular buffer in DRAM */
152 il_wr(il, FH49_RSCSR_CHNL0_RBDCB_BASE_REG, (u32) (rxq->bd_dma >> 8));
154 /* Tell device where in DRAM to update its Rx status */
155 il_wr(il, FH49_RSCSR_CHNL0_STTS_WPTR_REG, rxq->rb_stts_dma >> 4);
158 * Direct rx interrupts to hosts
159 * Rx buffer size 4 or 8k
163 il_wr(il, FH49_MEM_RCSR_CHNL0_CONFIG_REG,
164 FH49_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
165 FH49_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
166 FH49_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
168 (rb_timeout << FH49_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS) |
169 (rfdnlog << FH49_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
171 /* Set interrupt coalescing timer to default (2048 usecs) */
172 il_write8(il, CSR_INT_COALESCING, IL_HOST_INT_TIMEOUT_DEF);
178 il4965_set_pwr_vmain(struct il_priv *il)
181 * (for documentation purposes)
182 * to set power to V_AUX, do:
184 if (pci_pme_capable(il->pci_dev, PCI_D3cold))
185 il_set_bits_mask_prph(il, APMG_PS_CTRL_REG,
186 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
187 ~APMG_PS_CTRL_MSK_PWR_SRC);
190 il_set_bits_mask_prph(il, APMG_PS_CTRL_REG,
191 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
192 ~APMG_PS_CTRL_MSK_PWR_SRC);
196 il4965_hw_nic_init(struct il_priv *il)
199 struct il_rx_queue *rxq = &il->rxq;
202 spin_lock_irqsave(&il->lock, flags);
204 /* Set interrupt coalescing calibration timer to default (512 usecs) */
205 il_write8(il, CSR_INT_COALESCING, IL_HOST_INT_CALIB_TIMEOUT_DEF);
206 spin_unlock_irqrestore(&il->lock, flags);
208 il4965_set_pwr_vmain(il);
209 il4965_nic_config(il);
211 /* Allocate the RX queue, or reset if it is already allocated */
213 ret = il_rx_queue_alloc(il);
215 IL_ERR("Unable to initialize Rx queue\n");
219 il4965_rx_queue_reset(il, rxq);
221 il4965_rx_replenish(il);
223 il4965_rx_init(il, rxq);
225 spin_lock_irqsave(&il->lock, flags);
227 rxq->need_update = 1;
228 il_rx_queue_update_write_ptr(il, rxq);
230 spin_unlock_irqrestore(&il->lock, flags);
232 /* Allocate or reset and init all Tx and Command queues */
234 ret = il4965_txq_ctx_alloc(il);
238 il4965_txq_ctx_reset(il);
240 set_bit(S_INIT, &il->status);
246 * il4965_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
249 il4965_dma_addr2rbd_ptr(struct il_priv *il, dma_addr_t dma_addr)
251 return cpu_to_le32((u32) (dma_addr >> 8));
255 * il4965_rx_queue_restock - refill RX queue from pre-allocated pool
257 * If there are slots in the RX queue that need to be restocked,
258 * and we have free pre-allocated buffers, fill the ranks as much
259 * as we can, pulling from rx_free.
261 * This moves the 'write' idx forward to catch up with 'processed', and
262 * also updates the memory address in the firmware to reference the new
266 il4965_rx_queue_restock(struct il_priv *il)
268 struct il_rx_queue *rxq = &il->rxq;
269 struct list_head *element;
270 struct il_rx_buf *rxb;
273 spin_lock_irqsave(&rxq->lock, flags);
274 while (il_rx_queue_space(rxq) > 0 && rxq->free_count) {
275 /* The overwritten rxb must be a used one */
276 rxb = rxq->queue[rxq->write];
277 BUG_ON(rxb && rxb->page);
279 /* Get next free Rx buffer, remove from free list */
280 element = rxq->rx_free.next;
281 rxb = list_entry(element, struct il_rx_buf, list);
284 /* Point to Rx buffer via next RBD in circular buffer */
285 rxq->bd[rxq->write] =
286 il4965_dma_addr2rbd_ptr(il, rxb->page_dma);
287 rxq->queue[rxq->write] = rxb;
288 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
291 spin_unlock_irqrestore(&rxq->lock, flags);
292 /* If the pre-allocated buffer pool is dropping low, schedule to
294 if (rxq->free_count <= RX_LOW_WATERMARK)
295 queue_work(il->workqueue, &il->rx_replenish);
297 /* If we've added more space for the firmware to place data, tell it.
298 * Increment device's write pointer in multiples of 8. */
299 if (rxq->write_actual != (rxq->write & ~0x7)) {
300 spin_lock_irqsave(&rxq->lock, flags);
301 rxq->need_update = 1;
302 spin_unlock_irqrestore(&rxq->lock, flags);
303 il_rx_queue_update_write_ptr(il, rxq);
308 * il4965_rx_replenish - Move all used packet from rx_used to rx_free
310 * When moving to rx_free an SKB is allocated for the slot.
312 * Also restock the Rx queue via il_rx_queue_restock.
313 * This is called as a scheduled work item (except for during initialization)
316 il4965_rx_allocate(struct il_priv *il, gfp_t priority)
318 struct il_rx_queue *rxq = &il->rxq;
319 struct list_head *element;
320 struct il_rx_buf *rxb;
324 gfp_t gfp_mask = priority;
327 spin_lock_irqsave(&rxq->lock, flags);
328 if (list_empty(&rxq->rx_used)) {
329 spin_unlock_irqrestore(&rxq->lock, flags);
332 spin_unlock_irqrestore(&rxq->lock, flags);
334 if (rxq->free_count > RX_LOW_WATERMARK)
335 gfp_mask |= __GFP_NOWARN;
337 if (il->hw_params.rx_page_order > 0)
338 gfp_mask |= __GFP_COMP;
340 /* Alloc a new receive buffer */
341 page = alloc_pages(gfp_mask, il->hw_params.rx_page_order);
344 D_INFO("alloc_pages failed, " "order: %d\n",
345 il->hw_params.rx_page_order);
347 if (rxq->free_count <= RX_LOW_WATERMARK &&
349 IL_ERR("Failed to alloc_pages with %s. "
350 "Only %u free buffers remaining.\n",
352 GFP_ATOMIC ? "GFP_ATOMIC" : "GFP_KERNEL",
354 /* We don't reschedule replenish work here -- we will
355 * call the restock method and if it still needs
356 * more buffers it will schedule replenish */
360 /* Get physical address of the RB */
362 pci_map_page(il->pci_dev, page, 0,
363 PAGE_SIZE << il->hw_params.rx_page_order,
365 if (unlikely(pci_dma_mapping_error(il->pci_dev, page_dma))) {
366 __free_pages(page, il->hw_params.rx_page_order);
370 spin_lock_irqsave(&rxq->lock, flags);
372 if (list_empty(&rxq->rx_used)) {
373 spin_unlock_irqrestore(&rxq->lock, flags);
374 pci_unmap_page(il->pci_dev, page_dma,
375 PAGE_SIZE << il->hw_params.rx_page_order,
377 __free_pages(page, il->hw_params.rx_page_order);
381 element = rxq->rx_used.next;
382 rxb = list_entry(element, struct il_rx_buf, list);
388 rxb->page_dma = page_dma;
389 list_add_tail(&rxb->list, &rxq->rx_free);
391 il->alloc_rxb_page++;
393 spin_unlock_irqrestore(&rxq->lock, flags);
398 il4965_rx_replenish(struct il_priv *il)
402 il4965_rx_allocate(il, GFP_KERNEL);
404 spin_lock_irqsave(&il->lock, flags);
405 il4965_rx_queue_restock(il);
406 spin_unlock_irqrestore(&il->lock, flags);
410 il4965_rx_replenish_now(struct il_priv *il)
412 il4965_rx_allocate(il, GFP_ATOMIC);
414 il4965_rx_queue_restock(il);
417 /* Assumes that the skb field of the buffers in 'pool' is kept accurate.
418 * If an SKB has been detached, the POOL needs to have its SKB set to NULL
419 * This free routine walks the list of POOL entries and if SKB is set to
420 * non NULL it is unmapped and freed
423 il4965_rx_queue_free(struct il_priv *il, struct il_rx_queue *rxq)
426 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
427 if (rxq->pool[i].page != NULL) {
428 pci_unmap_page(il->pci_dev, rxq->pool[i].page_dma,
429 PAGE_SIZE << il->hw_params.rx_page_order,
431 __il_free_pages(il, rxq->pool[i].page);
432 rxq->pool[i].page = NULL;
436 dma_free_coherent(&il->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
438 dma_free_coherent(&il->pci_dev->dev, sizeof(struct il_rb_status),
439 rxq->rb_stts, rxq->rb_stts_dma);
445 il4965_rxq_stop(struct il_priv *il)
449 _il_wr(il, FH49_MEM_RCSR_CHNL0_CONFIG_REG, 0);
450 ret = _il_poll_bit(il, FH49_MEM_RSSR_RX_STATUS_REG,
451 FH49_RSSR_CHNL0_RX_STATUS_CHNL_IDLE,
452 FH49_RSSR_CHNL0_RX_STATUS_CHNL_IDLE,
455 IL_ERR("Can't stop Rx DMA.\n");
461 il4965_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band)
466 /* HT rate format: mac80211 wants an MCS number, which is just LSB */
467 if (rate_n_flags & RATE_MCS_HT_MSK) {
468 idx = (rate_n_flags & 0xff);
470 /* Legacy rate format, search for match in table */
472 if (band == IEEE80211_BAND_5GHZ)
473 band_offset = IL_FIRST_OFDM_RATE;
474 for (idx = band_offset; idx < RATE_COUNT_LEGACY; idx++)
475 if (il_rates[idx].plcp == (rate_n_flags & 0xFF))
476 return idx - band_offset;
483 il4965_calc_rssi(struct il_priv *il, struct il_rx_phy_res *rx_resp)
485 /* data from PHY/DSP regarding signal strength, etc.,
486 * contents are always there, not configurable by host. */
487 struct il4965_rx_non_cfg_phy *ncphy =
488 (struct il4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
490 (le16_to_cpu(ncphy->agc_info) & IL49_AGC_DB_MASK) >>
494 (le16_to_cpu(rx_resp->phy_flags) & IL49_RX_PHY_FLAGS_ANTENNAE_MASK)
495 >> IL49_RX_PHY_FLAGS_ANTENNAE_OFFSET;
499 /* Find max rssi among 3 possible receivers.
500 * These values are measured by the digital signal processor (DSP).
501 * They should stay fairly constant even as the signal strength varies,
502 * if the radio's automatic gain control (AGC) is working right.
503 * AGC value (see below) will provide the "interesting" info. */
504 for (i = 0; i < 3; i++)
505 if (valid_antennae & (1 << i))
506 max_rssi = max(ncphy->rssi_info[i << 1], max_rssi);
508 D_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n",
509 ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4],
512 /* dBm = max_rssi dB - agc dB - constant.
513 * Higher AGC (higher radio gain) means lower signal. */
514 return max_rssi - agc - IL4965_RSSI_OFFSET;
518 il4965_translate_rx_status(struct il_priv *il, u32 decrypt_in)
522 if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) ==
523 RX_RES_STATUS_STATION_FOUND)
525 (RX_RES_STATUS_STATION_FOUND |
526 RX_RES_STATUS_NO_STATION_INFO_MISMATCH);
528 decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK);
530 /* packet was not encrypted */
531 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
532 RX_RES_STATUS_SEC_TYPE_NONE)
535 /* packet was encrypted with unknown alg */
536 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
537 RX_RES_STATUS_SEC_TYPE_ERR)
540 /* decryption was not done in HW */
541 if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) !=
542 RX_MPDU_RES_STATUS_DEC_DONE_MSK)
545 switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) {
547 case RX_RES_STATUS_SEC_TYPE_CCMP:
548 /* alg is CCM: check MIC only */
549 if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK))
551 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
553 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
557 case RX_RES_STATUS_SEC_TYPE_TKIP:
558 if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) {
560 decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK;
563 /* fall through if TTAK OK */
565 if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK))
566 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
568 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
572 D_RX("decrypt_in:0x%x decrypt_out = 0x%x\n", decrypt_in, decrypt_out);
577 #define SMALL_PACKET_SIZE 256
580 il4965_pass_packet_to_mac80211(struct il_priv *il, struct ieee80211_hdr *hdr,
581 u32 len, u32 ampdu_status, struct il_rx_buf *rxb,
582 struct ieee80211_rx_status *stats)
585 __le16 fc = hdr->frame_control;
587 /* We only process data packets if the interface is open */
588 if (unlikely(!il->is_open)) {
589 D_DROP("Dropping packet while interface is not open.\n");
593 /* In case of HW accelerated crypto and bad decryption, drop */
594 if (!il->cfg->mod_params->sw_crypto &&
595 il_set_decrypted_flag(il, hdr, ampdu_status, stats))
598 skb = dev_alloc_skb(SMALL_PACKET_SIZE);
600 IL_ERR("dev_alloc_skb failed\n");
604 if (len <= SMALL_PACKET_SIZE) {
605 memcpy(skb_put(skb, len), hdr, len);
607 skb_add_rx_frag(skb, 0, rxb->page, (void *)hdr - rxb_addr(rxb),
608 len, PAGE_SIZE << il->hw_params.rx_page_order);
609 il->alloc_rxb_page--;
613 il_update_stats(il, false, fc, len);
614 memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats));
616 ieee80211_rx(il->hw, skb);
619 /* Called for N_RX (legacy ABG frames), or
620 * N_RX_MPDU (HT high-throughput N frames). */
622 il4965_hdl_rx(struct il_priv *il, struct il_rx_buf *rxb)
624 struct ieee80211_hdr *header;
625 struct ieee80211_rx_status rx_status = {};
626 struct il_rx_pkt *pkt = rxb_addr(rxb);
627 struct il_rx_phy_res *phy_res;
628 __le32 rx_pkt_status;
629 struct il_rx_mpdu_res_start *amsdu;
635 * N_RX and N_RX_MPDU are handled differently.
636 * N_RX: physical layer info is in this buffer
637 * N_RX_MPDU: physical layer info was sent in separate
638 * command and cached in il->last_phy_res
640 * Here we set up local variables depending on which command is
643 if (pkt->hdr.cmd == N_RX) {
644 phy_res = (struct il_rx_phy_res *)pkt->u.raw;
646 (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*phy_res) +
647 phy_res->cfg_phy_cnt);
649 len = le16_to_cpu(phy_res->byte_count);
651 *(__le32 *) (pkt->u.raw + sizeof(*phy_res) +
652 phy_res->cfg_phy_cnt + len);
653 ampdu_status = le32_to_cpu(rx_pkt_status);
655 if (!il->_4965.last_phy_res_valid) {
656 IL_ERR("MPDU frame without cached PHY data\n");
659 phy_res = &il->_4965.last_phy_res;
660 amsdu = (struct il_rx_mpdu_res_start *)pkt->u.raw;
661 header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*amsdu));
662 len = le16_to_cpu(amsdu->byte_count);
663 rx_pkt_status = *(__le32 *) (pkt->u.raw + sizeof(*amsdu) + len);
665 il4965_translate_rx_status(il, le32_to_cpu(rx_pkt_status));
668 if ((unlikely(phy_res->cfg_phy_cnt > 20))) {
669 D_DROP("dsp size out of range [0,20]: %d/n",
670 phy_res->cfg_phy_cnt);
674 if (!(rx_pkt_status & RX_RES_STATUS_NO_CRC32_ERROR) ||
675 !(rx_pkt_status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
676 D_RX("Bad CRC or FIFO: 0x%08X.\n", le32_to_cpu(rx_pkt_status));
680 /* This will be used in several places later */
681 rate_n_flags = le32_to_cpu(phy_res->rate_n_flags);
683 /* rx_status carries information about the packet to mac80211 */
684 rx_status.mactime = le64_to_cpu(phy_res->timestamp);
687 phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ? IEEE80211_BAND_2GHZ :
690 ieee80211_channel_to_frequency(le16_to_cpu(phy_res->channel),
693 il4965_hwrate_to_mac80211_idx(rate_n_flags, rx_status.band);
696 /* TSF isn't reliable. In order to allow smooth user experience,
697 * this W/A doesn't propagate it to the mac80211 */
698 /*rx_status.flag |= RX_FLAG_MACTIME_START; */
700 il->ucode_beacon_time = le32_to_cpu(phy_res->beacon_time_stamp);
702 /* Find max signal strength (dBm) among 3 antenna/receiver chains */
703 rx_status.signal = il4965_calc_rssi(il, phy_res);
705 D_STATS("Rssi %d, TSF %llu\n", rx_status.signal,
706 (unsigned long long)rx_status.mactime);
711 * It seems that the antenna field in the phy flags value
712 * is actually a bit field. This is undefined by radiotap,
713 * it wants an actual antenna number but I always get "7"
714 * for most legacy frames I receive indicating that the
715 * same frame was received on all three RX chains.
717 * I think this field should be removed in favor of a
718 * new 802.11n radiotap field "RX chains" that is defined
722 (le16_to_cpu(phy_res->phy_flags) & RX_RES_PHY_FLAGS_ANTENNA_MSK) >>
723 RX_RES_PHY_FLAGS_ANTENNA_POS;
725 /* set the preamble flag if appropriate */
726 if (phy_res->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
727 rx_status.flag |= RX_FLAG_SHORTPRE;
729 /* Set up the HT phy flags */
730 if (rate_n_flags & RATE_MCS_HT_MSK)
731 rx_status.flag |= RX_FLAG_HT;
732 if (rate_n_flags & RATE_MCS_HT40_MSK)
733 rx_status.flag |= RX_FLAG_40MHZ;
734 if (rate_n_flags & RATE_MCS_SGI_MSK)
735 rx_status.flag |= RX_FLAG_SHORT_GI;
737 if (phy_res->phy_flags & RX_RES_PHY_FLAGS_AGG_MSK) {
738 /* We know which subframes of an A-MPDU belong
739 * together since we get a single PHY response
740 * from the firmware for all of them.
743 rx_status.flag |= RX_FLAG_AMPDU_DETAILS;
744 rx_status.ampdu_reference = il->_4965.ampdu_ref;
747 il4965_pass_packet_to_mac80211(il, header, len, ampdu_status, rxb,
751 /* Cache phy data (Rx signal strength, etc) for HT frame (N_RX_PHY).
752 * This will be used later in il_hdl_rx() for N_RX_MPDU. */
754 il4965_hdl_rx_phy(struct il_priv *il, struct il_rx_buf *rxb)
756 struct il_rx_pkt *pkt = rxb_addr(rxb);
757 il->_4965.last_phy_res_valid = true;
758 il->_4965.ampdu_ref++;
759 memcpy(&il->_4965.last_phy_res, pkt->u.raw,
760 sizeof(struct il_rx_phy_res));
764 il4965_get_channels_for_scan(struct il_priv *il, struct ieee80211_vif *vif,
765 enum ieee80211_band band, u8 is_active,
766 u8 n_probes, struct il_scan_channel *scan_ch)
768 struct ieee80211_channel *chan;
769 const struct ieee80211_supported_band *sband;
770 const struct il_channel_info *ch_info;
771 u16 passive_dwell = 0;
772 u16 active_dwell = 0;
776 sband = il_get_hw_mode(il, band);
780 active_dwell = il_get_active_dwell_time(il, band, n_probes);
781 passive_dwell = il_get_passive_dwell_time(il, band, vif);
783 if (passive_dwell <= active_dwell)
784 passive_dwell = active_dwell + 1;
786 for (i = 0, added = 0; i < il->scan_request->n_channels; i++) {
787 chan = il->scan_request->channels[i];
789 if (chan->band != band)
792 channel = chan->hw_value;
793 scan_ch->channel = cpu_to_le16(channel);
795 ch_info = il_get_channel_info(il, band, channel);
796 if (!il_is_channel_valid(ch_info)) {
797 D_SCAN("Channel %d is INVALID for this band.\n",
802 if (!is_active || il_is_channel_passive(ch_info) ||
803 (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN))
804 scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
806 scan_ch->type = SCAN_CHANNEL_TYPE_ACTIVE;
809 scan_ch->type |= IL_SCAN_PROBE_MASK(n_probes);
811 scan_ch->active_dwell = cpu_to_le16(active_dwell);
812 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
814 /* Set txpower levels to defaults */
815 scan_ch->dsp_atten = 110;
817 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
819 * scan_ch->tx_gain = ((1 << 5) | (2 << 3)) | 3;
821 if (band == IEEE80211_BAND_5GHZ)
822 scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
824 scan_ch->tx_gain = ((1 << 5) | (5 << 3));
826 D_SCAN("Scanning ch=%d prob=0x%X [%s %d]\n", channel,
827 le32_to_cpu(scan_ch->type),
829 type & SCAN_CHANNEL_TYPE_ACTIVE) ? "ACTIVE" : "PASSIVE",
831 type & SCAN_CHANNEL_TYPE_ACTIVE) ? active_dwell :
838 D_SCAN("total channels to scan %d\n", added);
843 il4965_toggle_tx_ant(struct il_priv *il, u8 *ant, u8 valid)
848 for (i = 0; i < RATE_ANT_NUM - 1; i++) {
849 ind = (ind + 1) < RATE_ANT_NUM ? ind + 1 : 0;
850 if (valid & BIT(ind)) {
858 il4965_request_scan(struct il_priv *il, struct ieee80211_vif *vif)
860 struct il_host_cmd cmd = {
862 .len = sizeof(struct il_scan_cmd),
863 .flags = CMD_SIZE_HUGE,
865 struct il_scan_cmd *scan;
869 enum ieee80211_band band;
871 u8 rx_ant = il->hw_params.valid_rx_ant;
873 bool is_active = false;
876 u8 scan_tx_antennas = il->hw_params.valid_tx_ant;
879 lockdep_assert_held(&il->mutex);
883 kmalloc(sizeof(struct il_scan_cmd) + IL_MAX_SCAN_SIZE,
886 D_SCAN("fail to allocate memory for scan\n");
891 memset(scan, 0, sizeof(struct il_scan_cmd) + IL_MAX_SCAN_SIZE);
893 scan->quiet_plcp_th = IL_PLCP_QUIET_THRESH;
894 scan->quiet_time = IL_ACTIVE_QUIET_TIME;
896 if (il_is_any_associated(il)) {
899 u32 suspend_time = 100;
900 u32 scan_suspend_time = 100;
902 D_INFO("Scanning while associated...\n");
903 interval = vif->bss_conf.beacon_int;
905 scan->suspend_time = 0;
906 scan->max_out_time = cpu_to_le32(200 * 1024);
908 interval = suspend_time;
910 extra = (suspend_time / interval) << 22;
912 (extra | ((suspend_time % interval) * 1024));
913 scan->suspend_time = cpu_to_le32(scan_suspend_time);
914 D_SCAN("suspend_time 0x%X beacon interval %d\n",
915 scan_suspend_time, interval);
918 if (il->scan_request->n_ssids) {
920 D_SCAN("Kicking off active scan\n");
921 for (i = 0; i < il->scan_request->n_ssids; i++) {
922 /* always does wildcard anyway */
923 if (!il->scan_request->ssids[i].ssid_len)
925 scan->direct_scan[p].id = WLAN_EID_SSID;
926 scan->direct_scan[p].len =
927 il->scan_request->ssids[i].ssid_len;
928 memcpy(scan->direct_scan[p].ssid,
929 il->scan_request->ssids[i].ssid,
930 il->scan_request->ssids[i].ssid_len);
936 D_SCAN("Start passive scan.\n");
938 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
939 scan->tx_cmd.sta_id = il->hw_params.bcast_id;
940 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
942 switch (il->scan_band) {
943 case IEEE80211_BAND_2GHZ:
944 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
946 le32_to_cpu(il->active.flags & RXON_FLG_CHANNEL_MODE_MSK) >>
947 RXON_FLG_CHANNEL_MODE_POS;
948 if (chan_mod == CHANNEL_MODE_PURE_40) {
952 rate_flags = RATE_MCS_CCK_MSK;
955 case IEEE80211_BAND_5GHZ:
959 IL_WARN("Invalid scan band\n");
964 * If active scanning is requested but a certain channel is
965 * marked passive, we can do active scanning if we detect
968 * There is an issue with some firmware versions that triggers
969 * a sysassert on a "good CRC threshold" of zero (== disabled),
970 * on a radar channel even though this means that we should NOT
973 * The "good CRC threshold" is the number of frames that we
974 * need to receive during our dwell time on a channel before
975 * sending out probes -- setting this to a huge value will
976 * mean we never reach it, but at the same time work around
977 * the aforementioned issue. Thus use IL_GOOD_CRC_TH_NEVER
978 * here instead of IL_GOOD_CRC_TH_DISABLED.
981 is_active ? IL_GOOD_CRC_TH_DEFAULT : IL_GOOD_CRC_TH_NEVER;
983 band = il->scan_band;
985 if (il->cfg->scan_rx_antennas[band])
986 rx_ant = il->cfg->scan_rx_antennas[band];
988 il4965_toggle_tx_ant(il, &il->scan_tx_ant[band], scan_tx_antennas);
989 rate_flags |= BIT(il->scan_tx_ant[band]) << RATE_MCS_ANT_POS;
990 scan->tx_cmd.rate_n_flags = cpu_to_le32(rate | rate_flags);
992 /* In power save mode use one chain, otherwise use all chains */
993 if (test_bit(S_POWER_PMI, &il->status)) {
994 /* rx_ant has been set to all valid chains previously */
996 rx_ant & ((u8) (il->chain_noise_data.active_chains));
998 active_chains = rx_ant;
1000 D_SCAN("chain_noise_data.active_chains: %u\n",
1001 il->chain_noise_data.active_chains);
1003 rx_ant = il4965_first_antenna(active_chains);
1006 /* MIMO is not used here, but value is required */
1007 rx_chain |= il->hw_params.valid_rx_ant << RXON_RX_CHAIN_VALID_POS;
1008 rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS;
1009 rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_SEL_POS;
1010 rx_chain |= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS;
1011 scan->rx_chain = cpu_to_le16(rx_chain);
1014 il_fill_probe_req(il, (struct ieee80211_mgmt *)scan->data,
1015 vif->addr, il->scan_request->ie,
1016 il->scan_request->ie_len,
1017 IL_MAX_SCAN_SIZE - sizeof(*scan));
1018 scan->tx_cmd.len = cpu_to_le16(cmd_len);
1020 scan->filter_flags |=
1021 (RXON_FILTER_ACCEPT_GRP_MSK | RXON_FILTER_BCON_AWARE_MSK);
1023 scan->channel_count =
1024 il4965_get_channels_for_scan(il, vif, band, is_active, n_probes,
1025 (void *)&scan->data[cmd_len]);
1026 if (scan->channel_count == 0) {
1027 D_SCAN("channel count %d\n", scan->channel_count);
1032 le16_to_cpu(scan->tx_cmd.len) +
1033 scan->channel_count * sizeof(struct il_scan_channel);
1035 scan->len = cpu_to_le16(cmd.len);
1037 set_bit(S_SCAN_HW, &il->status);
1039 ret = il_send_cmd_sync(il, &cmd);
1041 clear_bit(S_SCAN_HW, &il->status);
1047 il4965_manage_ibss_station(struct il_priv *il, struct ieee80211_vif *vif,
1050 struct il_vif_priv *vif_priv = (void *)vif->drv_priv;
1053 return il4965_add_bssid_station(il, vif->bss_conf.bssid,
1054 &vif_priv->ibss_bssid_sta_id);
1055 return il_remove_station(il, vif_priv->ibss_bssid_sta_id,
1056 vif->bss_conf.bssid);
1060 il4965_free_tfds_in_queue(struct il_priv *il, int sta_id, int tid, int freed)
1062 lockdep_assert_held(&il->sta_lock);
1064 if (il->stations[sta_id].tid[tid].tfds_in_queue >= freed)
1065 il->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1067 D_TX("free more than tfds_in_queue (%u:%d)\n",
1068 il->stations[sta_id].tid[tid].tfds_in_queue, freed);
1069 il->stations[sta_id].tid[tid].tfds_in_queue = 0;
1073 #define IL_TX_QUEUE_MSK 0xfffff
1076 il4965_is_single_rx_stream(struct il_priv *il)
1078 return il->current_ht_config.smps == IEEE80211_SMPS_STATIC ||
1079 il->current_ht_config.single_chain_sufficient;
1082 #define IL_NUM_RX_CHAINS_MULTIPLE 3
1083 #define IL_NUM_RX_CHAINS_SINGLE 2
1084 #define IL_NUM_IDLE_CHAINS_DUAL 2
1085 #define IL_NUM_IDLE_CHAINS_SINGLE 1
1088 * Determine how many receiver/antenna chains to use.
1090 * More provides better reception via diversity. Fewer saves power
1091 * at the expense of throughput, but only when not in powersave to
1094 * MIMO (dual stream) requires at least 2, but works better with 3.
1095 * This does not determine *which* chains to use, just how many.
1098 il4965_get_active_rx_chain_count(struct il_priv *il)
1100 /* # of Rx chains to use when expecting MIMO. */
1101 if (il4965_is_single_rx_stream(il))
1102 return IL_NUM_RX_CHAINS_SINGLE;
1104 return IL_NUM_RX_CHAINS_MULTIPLE;
1108 * When we are in power saving mode, unless device support spatial
1109 * multiplexing power save, use the active count for rx chain count.
1112 il4965_get_idle_rx_chain_count(struct il_priv *il, int active_cnt)
1114 /* # Rx chains when idling, depending on SMPS mode */
1115 switch (il->current_ht_config.smps) {
1116 case IEEE80211_SMPS_STATIC:
1117 case IEEE80211_SMPS_DYNAMIC:
1118 return IL_NUM_IDLE_CHAINS_SINGLE;
1119 case IEEE80211_SMPS_OFF:
1122 WARN(1, "invalid SMPS mode %d", il->current_ht_config.smps);
1127 /* up to 4 chains */
1129 il4965_count_chain_bitmap(u32 chain_bitmap)
1132 res = (chain_bitmap & BIT(0)) >> 0;
1133 res += (chain_bitmap & BIT(1)) >> 1;
1134 res += (chain_bitmap & BIT(2)) >> 2;
1135 res += (chain_bitmap & BIT(3)) >> 3;
1140 * il4965_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
1142 * Selects how many and which Rx receivers/antennas/chains to use.
1143 * This should not be used for scan command ... it puts data in wrong place.
1146 il4965_set_rxon_chain(struct il_priv *il)
1148 bool is_single = il4965_is_single_rx_stream(il);
1149 bool is_cam = !test_bit(S_POWER_PMI, &il->status);
1150 u8 idle_rx_cnt, active_rx_cnt, valid_rx_cnt;
1154 /* Tell uCode which antennas are actually connected.
1155 * Before first association, we assume all antennas are connected.
1156 * Just after first association, il4965_chain_noise_calibration()
1157 * checks which antennas actually *are* connected. */
1158 if (il->chain_noise_data.active_chains)
1159 active_chains = il->chain_noise_data.active_chains;
1161 active_chains = il->hw_params.valid_rx_ant;
1163 rx_chain = active_chains << RXON_RX_CHAIN_VALID_POS;
1165 /* How many receivers should we use? */
1166 active_rx_cnt = il4965_get_active_rx_chain_count(il);
1167 idle_rx_cnt = il4965_get_idle_rx_chain_count(il, active_rx_cnt);
1169 /* correct rx chain count according hw settings
1170 * and chain noise calibration
1172 valid_rx_cnt = il4965_count_chain_bitmap(active_chains);
1173 if (valid_rx_cnt < active_rx_cnt)
1174 active_rx_cnt = valid_rx_cnt;
1176 if (valid_rx_cnt < idle_rx_cnt)
1177 idle_rx_cnt = valid_rx_cnt;
1179 rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS;
1180 rx_chain |= idle_rx_cnt << RXON_RX_CHAIN_CNT_POS;
1182 il->staging.rx_chain = cpu_to_le16(rx_chain);
1184 if (!is_single && active_rx_cnt >= IL_NUM_RX_CHAINS_SINGLE && is_cam)
1185 il->staging.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
1187 il->staging.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
1189 D_ASSOC("rx_chain=0x%X active=%d idle=%d\n", il->staging.rx_chain,
1190 active_rx_cnt, idle_rx_cnt);
1192 WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 ||
1193 active_rx_cnt < idle_rx_cnt);
1197 il4965_get_fh_string(int cmd)
1200 IL_CMD(FH49_RSCSR_CHNL0_STTS_WPTR_REG);
1201 IL_CMD(FH49_RSCSR_CHNL0_RBDCB_BASE_REG);
1202 IL_CMD(FH49_RSCSR_CHNL0_WPTR);
1203 IL_CMD(FH49_MEM_RCSR_CHNL0_CONFIG_REG);
1204 IL_CMD(FH49_MEM_RSSR_SHARED_CTRL_REG);
1205 IL_CMD(FH49_MEM_RSSR_RX_STATUS_REG);
1206 IL_CMD(FH49_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
1207 IL_CMD(FH49_TSSR_TX_STATUS_REG);
1208 IL_CMD(FH49_TSSR_TX_ERROR_REG);
1215 il4965_dump_fh(struct il_priv *il, char **buf, bool display)
1218 #ifdef CONFIG_IWLEGACY_DEBUG
1222 static const u32 fh_tbl[] = {
1223 FH49_RSCSR_CHNL0_STTS_WPTR_REG,
1224 FH49_RSCSR_CHNL0_RBDCB_BASE_REG,
1225 FH49_RSCSR_CHNL0_WPTR,
1226 FH49_MEM_RCSR_CHNL0_CONFIG_REG,
1227 FH49_MEM_RSSR_SHARED_CTRL_REG,
1228 FH49_MEM_RSSR_RX_STATUS_REG,
1229 FH49_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
1230 FH49_TSSR_TX_STATUS_REG,
1231 FH49_TSSR_TX_ERROR_REG
1233 #ifdef CONFIG_IWLEGACY_DEBUG
1235 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
1236 *buf = kmalloc(bufsz, GFP_KERNEL);
1240 scnprintf(*buf + pos, bufsz - pos, "FH register values:\n");
1241 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1243 scnprintf(*buf + pos, bufsz - pos,
1245 il4965_get_fh_string(fh_tbl[i]),
1246 il_rd(il, fh_tbl[i]));
1251 IL_ERR("FH register values:\n");
1252 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1253 IL_ERR(" %34s: 0X%08x\n", il4965_get_fh_string(fh_tbl[i]),
1254 il_rd(il, fh_tbl[i]));
1260 il4965_hdl_missed_beacon(struct il_priv *il, struct il_rx_buf *rxb)
1262 struct il_rx_pkt *pkt = rxb_addr(rxb);
1263 struct il_missed_beacon_notif *missed_beacon;
1265 missed_beacon = &pkt->u.missed_beacon;
1266 if (le32_to_cpu(missed_beacon->consecutive_missed_beacons) >
1267 il->missed_beacon_threshold) {
1268 D_CALIB("missed bcn cnsq %d totl %d rcd %d expctd %d\n",
1269 le32_to_cpu(missed_beacon->consecutive_missed_beacons),
1270 le32_to_cpu(missed_beacon->total_missed_becons),
1271 le32_to_cpu(missed_beacon->num_recvd_beacons),
1272 le32_to_cpu(missed_beacon->num_expected_beacons));
1273 if (!test_bit(S_SCANNING, &il->status))
1274 il4965_init_sensitivity(il);
1278 /* Calculate noise level, based on measurements during network silence just
1279 * before arriving beacon. This measurement can be done only if we know
1280 * exactly when to expect beacons, therefore only when we're associated. */
1282 il4965_rx_calc_noise(struct il_priv *il)
1284 struct stats_rx_non_phy *rx_info;
1285 int num_active_rx = 0;
1286 int total_silence = 0;
1287 int bcn_silence_a, bcn_silence_b, bcn_silence_c;
1290 rx_info = &(il->_4965.stats.rx.general);
1292 le32_to_cpu(rx_info->beacon_silence_rssi_a) & IN_BAND_FILTER;
1294 le32_to_cpu(rx_info->beacon_silence_rssi_b) & IN_BAND_FILTER;
1296 le32_to_cpu(rx_info->beacon_silence_rssi_c) & IN_BAND_FILTER;
1298 if (bcn_silence_a) {
1299 total_silence += bcn_silence_a;
1302 if (bcn_silence_b) {
1303 total_silence += bcn_silence_b;
1306 if (bcn_silence_c) {
1307 total_silence += bcn_silence_c;
1311 /* Average among active antennas */
1313 last_rx_noise = (total_silence / num_active_rx) - 107;
1315 last_rx_noise = IL_NOISE_MEAS_NOT_AVAILABLE;
1317 D_CALIB("inband silence a %u, b %u, c %u, dBm %d\n", bcn_silence_a,
1318 bcn_silence_b, bcn_silence_c, last_rx_noise);
1321 #ifdef CONFIG_IWLEGACY_DEBUGFS
1323 * based on the assumption of all stats counter are in DWORD
1324 * FIXME: This function is for debugging, do not deal with
1325 * the case of counters roll-over.
1328 il4965_accumulative_stats(struct il_priv *il, __le32 * stats)
1333 u32 *delta, *max_delta;
1334 struct stats_general_common *general, *accum_general;
1335 struct stats_tx *tx, *accum_tx;
1337 prev_stats = (__le32 *) &il->_4965.stats;
1338 accum_stats = (u32 *) &il->_4965.accum_stats;
1339 size = sizeof(struct il_notif_stats);
1340 general = &il->_4965.stats.general.common;
1341 accum_general = &il->_4965.accum_stats.general.common;
1342 tx = &il->_4965.stats.tx;
1343 accum_tx = &il->_4965.accum_stats.tx;
1344 delta = (u32 *) &il->_4965.delta_stats;
1345 max_delta = (u32 *) &il->_4965.max_delta;
1347 for (i = sizeof(__le32); i < size;
1349 sizeof(__le32), stats++, prev_stats++, delta++, max_delta++,
1351 if (le32_to_cpu(*stats) > le32_to_cpu(*prev_stats)) {
1353 (le32_to_cpu(*stats) - le32_to_cpu(*prev_stats));
1354 *accum_stats += *delta;
1355 if (*delta > *max_delta)
1356 *max_delta = *delta;
1360 /* reset accumulative stats for "no-counter" type stats */
1361 accum_general->temperature = general->temperature;
1362 accum_general->ttl_timestamp = general->ttl_timestamp;
1367 il4965_hdl_stats(struct il_priv *il, struct il_rx_buf *rxb)
1369 const int recalib_seconds = 60;
1371 struct il_rx_pkt *pkt = rxb_addr(rxb);
1373 D_RX("Statistics notification received (%d vs %d).\n",
1374 (int)sizeof(struct il_notif_stats),
1375 le32_to_cpu(pkt->len_n_flags) & IL_RX_FRAME_SIZE_MSK);
1378 ((il->_4965.stats.general.common.temperature !=
1379 pkt->u.stats.general.common.temperature) ||
1380 ((il->_4965.stats.flag & STATS_REPLY_FLG_HT40_MODE_MSK) !=
1381 (pkt->u.stats.flag & STATS_REPLY_FLG_HT40_MODE_MSK)));
1382 #ifdef CONFIG_IWLEGACY_DEBUGFS
1383 il4965_accumulative_stats(il, (__le32 *) &pkt->u.stats);
1386 /* TODO: reading some of stats is unneeded */
1387 memcpy(&il->_4965.stats, &pkt->u.stats, sizeof(il->_4965.stats));
1389 set_bit(S_STATS, &il->status);
1392 * Reschedule the stats timer to occur in recalib_seconds to ensure
1393 * we get a thermal update even if the uCode doesn't give us one
1395 mod_timer(&il->stats_periodic,
1396 jiffies + msecs_to_jiffies(recalib_seconds * 1000));
1398 if (unlikely(!test_bit(S_SCANNING, &il->status)) &&
1399 (pkt->hdr.cmd == N_STATS)) {
1400 il4965_rx_calc_noise(il);
1401 queue_work(il->workqueue, &il->run_time_calib_work);
1405 il4965_temperature_calib(il);
1409 il4965_hdl_c_stats(struct il_priv *il, struct il_rx_buf *rxb)
1411 struct il_rx_pkt *pkt = rxb_addr(rxb);
1413 if (le32_to_cpu(pkt->u.stats.flag) & UCODE_STATS_CLEAR_MSK) {
1414 #ifdef CONFIG_IWLEGACY_DEBUGFS
1415 memset(&il->_4965.accum_stats, 0,
1416 sizeof(struct il_notif_stats));
1417 memset(&il->_4965.delta_stats, 0,
1418 sizeof(struct il_notif_stats));
1419 memset(&il->_4965.max_delta, 0, sizeof(struct il_notif_stats));
1421 D_RX("Statistics have been cleared\n");
1423 il4965_hdl_stats(il, rxb);
1428 * mac80211 queues, ACs, hardware queues, FIFOs.
1430 * Cf. http://wireless.kernel.org/en/developers/Documentation/mac80211/queues
1432 * Mac80211 uses the following numbers, which we get as from it
1433 * by way of skb_get_queue_mapping(skb):
1441 * Regular (not A-MPDU) frames are put into hardware queues corresponding
1442 * to the FIFOs, see comments in iwl-prph.h. Aggregated frames get their
1443 * own queue per aggregation session (RA/TID combination), such queues are
1444 * set up to map into FIFOs too, for which we need an AC->FIFO mapping. In
1445 * order to map frames to the right queue, we also need an AC->hw queue
1446 * mapping. This is implemented here.
1448 * Due to the way hw queues are set up (by the hw specific modules like
1449 * 4965.c), the AC->hw queue mapping is the identity
1453 static const u8 tid_to_ac[] = {
1465 il4965_get_ac_from_tid(u16 tid)
1467 if (likely(tid < ARRAY_SIZE(tid_to_ac)))
1468 return tid_to_ac[tid];
1470 /* no support for TIDs 8-15 yet */
1475 il4965_get_fifo_from_tid(u16 tid)
1477 const u8 ac_to_fifo[] = {
1484 if (likely(tid < ARRAY_SIZE(tid_to_ac)))
1485 return ac_to_fifo[tid_to_ac[tid]];
1487 /* no support for TIDs 8-15 yet */
1492 * handle build C_TX command notification.
1495 il4965_tx_cmd_build_basic(struct il_priv *il, struct sk_buff *skb,
1496 struct il_tx_cmd *tx_cmd,
1497 struct ieee80211_tx_info *info,
1498 struct ieee80211_hdr *hdr, u8 std_id)
1500 __le16 fc = hdr->frame_control;
1501 __le32 tx_flags = tx_cmd->tx_flags;
1503 tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
1504 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
1505 tx_flags |= TX_CMD_FLG_ACK_MSK;
1506 if (ieee80211_is_mgmt(fc))
1507 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
1508 if (ieee80211_is_probe_resp(fc) &&
1509 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
1510 tx_flags |= TX_CMD_FLG_TSF_MSK;
1512 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
1513 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
1516 if (ieee80211_is_back_req(fc))
1517 tx_flags |= TX_CMD_FLG_ACK_MSK | TX_CMD_FLG_IMM_BA_RSP_MASK;
1519 tx_cmd->sta_id = std_id;
1520 if (ieee80211_has_morefrags(fc))
1521 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
1523 if (ieee80211_is_data_qos(fc)) {
1524 u8 *qc = ieee80211_get_qos_ctl(hdr);
1525 tx_cmd->tid_tspec = qc[0] & 0xf;
1526 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
1528 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
1531 il_tx_cmd_protection(il, info, fc, &tx_flags);
1533 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
1534 if (ieee80211_is_mgmt(fc)) {
1535 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
1536 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3);
1538 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2);
1540 tx_cmd->timeout.pm_frame_timeout = 0;
1543 tx_cmd->driver_txop = 0;
1544 tx_cmd->tx_flags = tx_flags;
1545 tx_cmd->next_frame_len = 0;
1549 il4965_tx_cmd_build_rate(struct il_priv *il,
1550 struct il_tx_cmd *tx_cmd,
1551 struct ieee80211_tx_info *info,
1552 struct ieee80211_sta *sta,
1555 const u8 rts_retry_limit = 60;
1558 u8 data_retry_limit;
1561 /* Set retry limit on DATA packets and Probe Responses */
1562 if (ieee80211_is_probe_resp(fc))
1563 data_retry_limit = 3;
1565 data_retry_limit = IL4965_DEFAULT_TX_RETRY;
1566 tx_cmd->data_retry_limit = data_retry_limit;
1567 /* Set retry limit on RTS packets */
1568 tx_cmd->rts_retry_limit = min(data_retry_limit, rts_retry_limit);
1570 /* DATA packets will use the uCode station table for rate/antenna
1572 if (ieee80211_is_data(fc)) {
1573 tx_cmd->initial_rate_idx = 0;
1574 tx_cmd->tx_flags |= TX_CMD_FLG_STA_RATE_MSK;
1579 * If the current TX rate stored in mac80211 has the MCS bit set, it's
1580 * not really a TX rate. Thus, we use the lowest supported rate for
1581 * this band. Also use the lowest supported rate if the stored rate
1584 rate_idx = info->control.rates[0].idx;
1585 if ((info->control.rates[0].flags & IEEE80211_TX_RC_MCS) || rate_idx < 0
1586 || rate_idx > RATE_COUNT_LEGACY)
1587 rate_idx = rate_lowest_index(&il->bands[info->band], sta);
1588 /* For 5 GHZ band, remap mac80211 rate indices into driver indices */
1589 if (info->band == IEEE80211_BAND_5GHZ)
1590 rate_idx += IL_FIRST_OFDM_RATE;
1591 /* Get PLCP rate for tx_cmd->rate_n_flags */
1592 rate_plcp = il_rates[rate_idx].plcp;
1593 /* Zero out flags for this packet */
1596 /* Set CCK flag as needed */
1597 if (rate_idx >= IL_FIRST_CCK_RATE && rate_idx <= IL_LAST_CCK_RATE)
1598 rate_flags |= RATE_MCS_CCK_MSK;
1600 /* Set up antennas */
1601 il4965_toggle_tx_ant(il, &il->mgmt_tx_ant, il->hw_params.valid_tx_ant);
1602 rate_flags |= BIT(il->mgmt_tx_ant) << RATE_MCS_ANT_POS;
1604 /* Set the rate in the TX cmd */
1605 tx_cmd->rate_n_flags = cpu_to_le32(rate_plcp | rate_flags);
1609 il4965_tx_cmd_build_hwcrypto(struct il_priv *il, struct ieee80211_tx_info *info,
1610 struct il_tx_cmd *tx_cmd, struct sk_buff *skb_frag,
1613 struct ieee80211_key_conf *keyconf = info->control.hw_key;
1615 switch (keyconf->cipher) {
1616 case WLAN_CIPHER_SUITE_CCMP:
1617 tx_cmd->sec_ctl = TX_CMD_SEC_CCM;
1618 memcpy(tx_cmd->key, keyconf->key, keyconf->keylen);
1619 if (info->flags & IEEE80211_TX_CTL_AMPDU)
1620 tx_cmd->tx_flags |= TX_CMD_FLG_AGG_CCMP_MSK;
1621 D_TX("tx_cmd with AES hwcrypto\n");
1624 case WLAN_CIPHER_SUITE_TKIP:
1625 tx_cmd->sec_ctl = TX_CMD_SEC_TKIP;
1626 ieee80211_get_tkip_p2k(keyconf, skb_frag, tx_cmd->key);
1627 D_TX("tx_cmd with tkip hwcrypto\n");
1630 case WLAN_CIPHER_SUITE_WEP104:
1631 tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128;
1633 case WLAN_CIPHER_SUITE_WEP40:
1635 (TX_CMD_SEC_WEP | (keyconf->keyidx & TX_CMD_SEC_MSK) <<
1638 memcpy(&tx_cmd->key[3], keyconf->key, keyconf->keylen);
1640 D_TX("Configuring packet for WEP encryption " "with key %d\n",
1645 IL_ERR("Unknown encode cipher %x\n", keyconf->cipher);
1651 * start C_TX command process
1654 il4965_tx_skb(struct il_priv *il,
1655 struct ieee80211_sta *sta,
1656 struct sk_buff *skb)
1658 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1659 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1660 struct il_station_priv *sta_priv = NULL;
1661 struct il_tx_queue *txq;
1663 struct il_device_cmd *out_cmd;
1664 struct il_cmd_meta *out_meta;
1665 struct il_tx_cmd *tx_cmd;
1667 dma_addr_t phys_addr;
1668 dma_addr_t txcmd_phys;
1669 dma_addr_t scratch_phys;
1670 u16 len, firstlen, secondlen;
1675 u8 wait_write_ptr = 0;
1678 unsigned long flags;
1679 bool is_agg = false;
1681 spin_lock_irqsave(&il->lock, flags);
1682 if (il_is_rfkill(il)) {
1683 D_DROP("Dropping - RF KILL\n");
1687 fc = hdr->frame_control;
1689 #ifdef CONFIG_IWLEGACY_DEBUG
1690 if (ieee80211_is_auth(fc))
1691 D_TX("Sending AUTH frame\n");
1692 else if (ieee80211_is_assoc_req(fc))
1693 D_TX("Sending ASSOC frame\n");
1694 else if (ieee80211_is_reassoc_req(fc))
1695 D_TX("Sending REASSOC frame\n");
1698 hdr_len = ieee80211_hdrlen(fc);
1700 /* For management frames use broadcast id to do not break aggregation */
1701 if (!ieee80211_is_data(fc))
1702 sta_id = il->hw_params.bcast_id;
1704 /* Find idx into station table for destination station */
1705 sta_id = il_sta_id_or_broadcast(il, sta);
1707 if (sta_id == IL_INVALID_STATION) {
1708 D_DROP("Dropping - INVALID STATION: %pM\n", hdr->addr1);
1713 D_TX("station Id %d\n", sta_id);
1716 sta_priv = (void *)sta->drv_priv;
1718 if (sta_priv && sta_priv->asleep &&
1719 (info->flags & IEEE80211_TX_CTL_NO_PS_BUFFER)) {
1721 * This sends an asynchronous command to the device,
1722 * but we can rely on it being processed before the
1723 * next frame is processed -- and the next frame to
1724 * this station is the one that will consume this
1726 * For now set the counter to just 1 since we do not
1727 * support uAPSD yet.
1729 il4965_sta_modify_sleep_tx_count(il, sta_id, 1);
1732 /* FIXME: remove me ? */
1733 WARN_ON_ONCE(info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM);
1735 /* Access category (AC) is also the queue number */
1736 txq_id = skb_get_queue_mapping(skb);
1738 /* irqs already disabled/saved above when locking il->lock */
1739 spin_lock(&il->sta_lock);
1741 if (ieee80211_is_data_qos(fc)) {
1742 qc = ieee80211_get_qos_ctl(hdr);
1743 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
1744 if (WARN_ON_ONCE(tid >= MAX_TID_COUNT)) {
1745 spin_unlock(&il->sta_lock);
1748 seq_number = il->stations[sta_id].tid[tid].seq_number;
1749 seq_number &= IEEE80211_SCTL_SEQ;
1751 hdr->seq_ctrl & cpu_to_le16(IEEE80211_SCTL_FRAG);
1752 hdr->seq_ctrl |= cpu_to_le16(seq_number);
1754 /* aggregation is on for this <sta,tid> */
1755 if (info->flags & IEEE80211_TX_CTL_AMPDU &&
1756 il->stations[sta_id].tid[tid].agg.state == IL_AGG_ON) {
1757 txq_id = il->stations[sta_id].tid[tid].agg.txq_id;
1762 txq = &il->txq[txq_id];
1765 if (unlikely(il_queue_space(q) < q->high_mark)) {
1766 spin_unlock(&il->sta_lock);
1770 if (ieee80211_is_data_qos(fc)) {
1771 il->stations[sta_id].tid[tid].tfds_in_queue++;
1772 if (!ieee80211_has_morefrags(fc))
1773 il->stations[sta_id].tid[tid].seq_number = seq_number;
1776 spin_unlock(&il->sta_lock);
1778 txq->skbs[q->write_ptr] = skb;
1780 /* Set up first empty entry in queue's array of Tx/cmd buffers */
1781 out_cmd = txq->cmd[q->write_ptr];
1782 out_meta = &txq->meta[q->write_ptr];
1783 tx_cmd = &out_cmd->cmd.tx;
1784 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
1785 memset(tx_cmd, 0, sizeof(struct il_tx_cmd));
1788 * Set up the Tx-command (not MAC!) header.
1789 * Store the chosen Tx queue and TFD idx within the sequence field;
1790 * after Tx, uCode's Tx response will return this value so driver can
1791 * locate the frame within the tx queue and do post-tx processing.
1793 out_cmd->hdr.cmd = C_TX;
1794 out_cmd->hdr.sequence =
1796 (QUEUE_TO_SEQ(txq_id) | IDX_TO_SEQ(q->write_ptr)));
1798 /* Copy MAC header from skb into command buffer */
1799 memcpy(tx_cmd->hdr, hdr, hdr_len);
1801 /* Total # bytes to be transmitted */
1802 tx_cmd->len = cpu_to_le16((u16) skb->len);
1804 if (info->control.hw_key)
1805 il4965_tx_cmd_build_hwcrypto(il, info, tx_cmd, skb, sta_id);
1807 /* TODO need this for burst mode later on */
1808 il4965_tx_cmd_build_basic(il, skb, tx_cmd, info, hdr, sta_id);
1810 il4965_tx_cmd_build_rate(il, tx_cmd, info, sta, fc);
1813 * Use the first empty entry in this queue's command buffer array
1814 * to contain the Tx command and MAC header concatenated together
1815 * (payload data will be in another buffer).
1816 * Size of this varies, due to varying MAC header length.
1817 * If end is not dword aligned, we'll have 2 extra bytes at the end
1818 * of the MAC header (device reads on dword boundaries).
1819 * We'll tell device about this padding later.
1821 len = sizeof(struct il_tx_cmd) + sizeof(struct il_cmd_header) + hdr_len;
1822 firstlen = (len + 3) & ~3;
1824 /* Tell NIC about any 2-byte padding after MAC header */
1825 if (firstlen != len)
1826 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1828 /* Physical address of this Tx command's header (not MAC header!),
1829 * within command buffer array. */
1831 pci_map_single(il->pci_dev, &out_cmd->hdr, firstlen,
1832 PCI_DMA_BIDIRECTIONAL);
1833 if (unlikely(pci_dma_mapping_error(il->pci_dev, txcmd_phys)))
1836 /* Set up TFD's 2nd entry to point directly to remainder of skb,
1837 * if any (802.11 null frames have no payload). */
1838 secondlen = skb->len - hdr_len;
1839 if (secondlen > 0) {
1841 pci_map_single(il->pci_dev, skb->data + hdr_len, secondlen,
1843 if (unlikely(pci_dma_mapping_error(il->pci_dev, phys_addr)))
1847 /* Add buffer containing Tx command and MAC(!) header to TFD's
1849 il->ops->txq_attach_buf_to_tfd(il, txq, txcmd_phys, firstlen, 1, 0);
1850 dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
1851 dma_unmap_len_set(out_meta, len, firstlen);
1853 il->ops->txq_attach_buf_to_tfd(il, txq, phys_addr, secondlen,
1856 if (!ieee80211_has_morefrags(hdr->frame_control)) {
1857 txq->need_update = 1;
1860 txq->need_update = 0;
1864 txcmd_phys + sizeof(struct il_cmd_header) +
1865 offsetof(struct il_tx_cmd, scratch);
1867 /* take back ownership of DMA buffer to enable update */
1868 pci_dma_sync_single_for_cpu(il->pci_dev, txcmd_phys, firstlen,
1869 PCI_DMA_BIDIRECTIONAL);
1870 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1871 tx_cmd->dram_msb_ptr = il_get_dma_hi_addr(scratch_phys);
1873 il_update_stats(il, true, fc, skb->len);
1875 D_TX("sequence nr = 0X%x\n", le16_to_cpu(out_cmd->hdr.sequence));
1876 D_TX("tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
1877 il_print_hex_dump(il, IL_DL_TX, (u8 *) tx_cmd, sizeof(*tx_cmd));
1878 il_print_hex_dump(il, IL_DL_TX, (u8 *) tx_cmd->hdr, hdr_len);
1880 /* Set up entry for this TFD in Tx byte-count array */
1881 if (info->flags & IEEE80211_TX_CTL_AMPDU)
1882 il->ops->txq_update_byte_cnt_tbl(il, txq, le16_to_cpu(tx_cmd->len));
1884 pci_dma_sync_single_for_device(il->pci_dev, txcmd_phys, firstlen,
1885 PCI_DMA_BIDIRECTIONAL);
1887 /* Tell device the write idx *just past* this latest filled TFD */
1888 q->write_ptr = il_queue_inc_wrap(q->write_ptr, q->n_bd);
1889 il_txq_update_write_ptr(il, txq);
1890 spin_unlock_irqrestore(&il->lock, flags);
1893 * At this point the frame is "transmitted" successfully
1894 * and we will get a TX status notification eventually,
1895 * regardless of the value of ret. "ret" only indicates
1896 * whether or not we should update the write pointer.
1900 * Avoid atomic ops if it isn't an associated client.
1901 * Also, if this is a packet for aggregation, don't
1902 * increase the counter because the ucode will stop
1903 * aggregation queues when their respective station
1906 if (sta_priv && sta_priv->client && !is_agg)
1907 atomic_inc(&sta_priv->pending_frames);
1909 if (il_queue_space(q) < q->high_mark && il->mac80211_registered) {
1910 if (wait_write_ptr) {
1911 spin_lock_irqsave(&il->lock, flags);
1912 txq->need_update = 1;
1913 il_txq_update_write_ptr(il, txq);
1914 spin_unlock_irqrestore(&il->lock, flags);
1916 il_stop_queue(il, txq);
1923 spin_unlock_irqrestore(&il->lock, flags);
1928 il4965_alloc_dma_ptr(struct il_priv *il, struct il_dma_ptr *ptr, size_t size)
1930 ptr->addr = dma_alloc_coherent(&il->pci_dev->dev, size, &ptr->dma,
1939 il4965_free_dma_ptr(struct il_priv *il, struct il_dma_ptr *ptr)
1941 if (unlikely(!ptr->addr))
1944 dma_free_coherent(&il->pci_dev->dev, ptr->size, ptr->addr, ptr->dma);
1945 memset(ptr, 0, sizeof(*ptr));
1949 * il4965_hw_txq_ctx_free - Free TXQ Context
1951 * Destroy all TX DMA queues and structures
1954 il4965_hw_txq_ctx_free(struct il_priv *il)
1960 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++)
1961 if (txq_id == il->cmd_queue)
1962 il_cmd_queue_free(il);
1964 il_tx_queue_free(il, txq_id);
1966 il4965_free_dma_ptr(il, &il->kw);
1968 il4965_free_dma_ptr(il, &il->scd_bc_tbls);
1970 /* free tx queue structure */
1971 il_free_txq_mem(il);
1975 * il4965_txq_ctx_alloc - allocate TX queue context
1976 * Allocate all Tx DMA structures and initialize them
1979 * @return error code
1982 il4965_txq_ctx_alloc(struct il_priv *il)
1985 unsigned long flags;
1987 /* Free all tx/cmd queues and keep-warm buffer */
1988 il4965_hw_txq_ctx_free(il);
1991 il4965_alloc_dma_ptr(il, &il->scd_bc_tbls,
1992 il->hw_params.scd_bc_tbls_size);
1994 IL_ERR("Scheduler BC Table allocation failed\n");
1997 /* Alloc keep-warm buffer */
1998 ret = il4965_alloc_dma_ptr(il, &il->kw, IL_KW_SIZE);
2000 IL_ERR("Keep Warm allocation failed\n");
2004 /* allocate tx queue structure */
2005 ret = il_alloc_txq_mem(il);
2009 spin_lock_irqsave(&il->lock, flags);
2011 /* Turn off all Tx DMA fifos */
2012 il4965_txq_set_sched(il, 0);
2014 /* Tell NIC where to find the "keep warm" buffer */
2015 il_wr(il, FH49_KW_MEM_ADDR_REG, il->kw.dma >> 4);
2017 spin_unlock_irqrestore(&il->lock, flags);
2019 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
2020 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) {
2021 ret = il_tx_queue_init(il, txq_id);
2023 IL_ERR("Tx %d queue init failed\n", txq_id);
2031 il4965_hw_txq_ctx_free(il);
2032 il4965_free_dma_ptr(il, &il->kw);
2034 il4965_free_dma_ptr(il, &il->scd_bc_tbls);
2040 il4965_txq_ctx_reset(struct il_priv *il)
2043 unsigned long flags;
2045 spin_lock_irqsave(&il->lock, flags);
2047 /* Turn off all Tx DMA fifos */
2048 il4965_txq_set_sched(il, 0);
2049 /* Tell NIC where to find the "keep warm" buffer */
2050 il_wr(il, FH49_KW_MEM_ADDR_REG, il->kw.dma >> 4);
2052 spin_unlock_irqrestore(&il->lock, flags);
2054 /* Alloc and init all Tx queues, including the command queue (#4) */
2055 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++)
2056 il_tx_queue_reset(il, txq_id);
2060 il4965_txq_ctx_unmap(struct il_priv *il)
2067 /* Unmap DMA from host system and free skb's */
2068 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++)
2069 if (txq_id == il->cmd_queue)
2070 il_cmd_queue_unmap(il);
2072 il_tx_queue_unmap(il, txq_id);
2076 * il4965_txq_ctx_stop - Stop all Tx DMA channels
2079 il4965_txq_ctx_stop(struct il_priv *il)
2083 _il_wr_prph(il, IL49_SCD_TXFACT, 0);
2085 /* Stop each Tx DMA channel, and wait for it to be idle */
2086 for (ch = 0; ch < il->hw_params.dma_chnl_num; ch++) {
2087 _il_wr(il, FH49_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
2089 _il_poll_bit(il, FH49_TSSR_TX_STATUS_REG,
2090 FH49_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
2091 FH49_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
2094 IL_ERR("Timeout stopping DMA channel %d [0x%08x]",
2095 ch, _il_rd(il, FH49_TSSR_TX_STATUS_REG));
2100 * Find first available (lowest unused) Tx Queue, mark it "active".
2101 * Called only when finding queue for aggregation.
2102 * Should never return anything < 7, because they should already
2103 * be in use as EDCA AC (0-3), Command (4), reserved (5, 6)
2106 il4965_txq_ctx_activate_free(struct il_priv *il)
2110 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++)
2111 if (!test_and_set_bit(txq_id, &il->txq_ctx_active_msk))
2117 * il4965_tx_queue_stop_scheduler - Stop queue, but keep configuration
2120 il4965_tx_queue_stop_scheduler(struct il_priv *il, u16 txq_id)
2122 /* Simply stop the queue, but don't change any configuration;
2123 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
2124 il_wr_prph(il, IL49_SCD_QUEUE_STATUS_BITS(txq_id),
2125 (0 << IL49_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
2126 (1 << IL49_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
2130 * il4965_tx_queue_set_q2ratid - Map unique receiver/tid combination to a queue
2133 il4965_tx_queue_set_q2ratid(struct il_priv *il, u16 ra_tid, u16 txq_id)
2139 scd_q2ratid = ra_tid & IL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
2142 il->scd_base_addr + IL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
2144 tbl_dw = il_read_targ_mem(il, tbl_dw_addr);
2147 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
2149 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
2151 il_write_targ_mem(il, tbl_dw_addr, tbl_dw);
2157 * il4965_tx_queue_agg_enable - Set up & enable aggregation for selected queue
2159 * NOTE: txq_id must be greater than IL49_FIRST_AMPDU_QUEUE,
2160 * i.e. it must be one of the higher queues used for aggregation
2163 il4965_txq_agg_enable(struct il_priv *il, int txq_id, int tx_fifo, int sta_id,
2164 int tid, u16 ssn_idx)
2166 unsigned long flags;
2170 if ((IL49_FIRST_AMPDU_QUEUE > txq_id) ||
2171 (IL49_FIRST_AMPDU_QUEUE +
2172 il->cfg->num_of_ampdu_queues <= txq_id)) {
2173 IL_WARN("queue number out of range: %d, must be %d to %d\n",
2174 txq_id, IL49_FIRST_AMPDU_QUEUE,
2175 IL49_FIRST_AMPDU_QUEUE +
2176 il->cfg->num_of_ampdu_queues - 1);
2180 ra_tid = BUILD_RAxTID(sta_id, tid);
2182 /* Modify device's station table to Tx this TID */
2183 ret = il4965_sta_tx_modify_enable_tid(il, sta_id, tid);
2187 spin_lock_irqsave(&il->lock, flags);
2189 /* Stop this Tx queue before configuring it */
2190 il4965_tx_queue_stop_scheduler(il, txq_id);
2192 /* Map receiver-address / traffic-ID to this queue */
2193 il4965_tx_queue_set_q2ratid(il, ra_tid, txq_id);
2195 /* Set this queue as a chain-building queue */
2196 il_set_bits_prph(il, IL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
2198 /* Place first TFD at idx corresponding to start sequence number.
2199 * Assumes that ssn_idx is valid (!= 0xFFF) */
2200 il->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
2201 il->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
2202 il4965_set_wr_ptrs(il, txq_id, ssn_idx);
2204 /* Set up Tx win size and frame limit for this queue */
2205 il_write_targ_mem(il,
2207 IL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id),
2208 (SCD_WIN_SIZE << IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS)
2209 & IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
2211 il_write_targ_mem(il,
2213 IL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
2215 IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
2216 IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
2218 il_set_bits_prph(il, IL49_SCD_INTERRUPT_MASK, (1 << txq_id));
2220 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
2221 il4965_tx_queue_set_status(il, &il->txq[txq_id], tx_fifo, 1);
2223 spin_unlock_irqrestore(&il->lock, flags);
2229 il4965_tx_agg_start(struct il_priv *il, struct ieee80211_vif *vif,
2230 struct ieee80211_sta *sta, u16 tid, u16 * ssn)
2236 unsigned long flags;
2237 struct il_tid_data *tid_data;
2239 /* FIXME: warning if tx fifo not found ? */
2240 tx_fifo = il4965_get_fifo_from_tid(tid);
2241 if (unlikely(tx_fifo < 0))
2244 D_HT("%s on ra = %pM tid = %d\n", __func__, sta->addr, tid);
2246 sta_id = il_sta_id(sta);
2247 if (sta_id == IL_INVALID_STATION) {
2248 IL_ERR("Start AGG on invalid station\n");
2251 if (unlikely(tid >= MAX_TID_COUNT))
2254 if (il->stations[sta_id].tid[tid].agg.state != IL_AGG_OFF) {
2255 IL_ERR("Start AGG when state is not IL_AGG_OFF !\n");
2259 txq_id = il4965_txq_ctx_activate_free(il);
2261 IL_ERR("No free aggregation queue available\n");
2265 spin_lock_irqsave(&il->sta_lock, flags);
2266 tid_data = &il->stations[sta_id].tid[tid];
2267 *ssn = IEEE80211_SEQ_TO_SN(tid_data->seq_number);
2268 tid_data->agg.txq_id = txq_id;
2269 il_set_swq_id(&il->txq[txq_id], il4965_get_ac_from_tid(tid), txq_id);
2270 spin_unlock_irqrestore(&il->sta_lock, flags);
2272 ret = il4965_txq_agg_enable(il, txq_id, tx_fifo, sta_id, tid, *ssn);
2276 spin_lock_irqsave(&il->sta_lock, flags);
2277 tid_data = &il->stations[sta_id].tid[tid];
2278 if (tid_data->tfds_in_queue == 0) {
2279 D_HT("HW queue is empty\n");
2280 tid_data->agg.state = IL_AGG_ON;
2281 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
2283 D_HT("HW queue is NOT empty: %d packets in HW queue\n",
2284 tid_data->tfds_in_queue);
2285 tid_data->agg.state = IL_EMPTYING_HW_QUEUE_ADDBA;
2287 spin_unlock_irqrestore(&il->sta_lock, flags);
2292 * txq_id must be greater than IL49_FIRST_AMPDU_QUEUE
2293 * il->lock must be held by the caller
2296 il4965_txq_agg_disable(struct il_priv *il, u16 txq_id, u16 ssn_idx, u8 tx_fifo)
2298 if ((IL49_FIRST_AMPDU_QUEUE > txq_id) ||
2299 (IL49_FIRST_AMPDU_QUEUE +
2300 il->cfg->num_of_ampdu_queues <= txq_id)) {
2301 IL_WARN("queue number out of range: %d, must be %d to %d\n",
2302 txq_id, IL49_FIRST_AMPDU_QUEUE,
2303 IL49_FIRST_AMPDU_QUEUE +
2304 il->cfg->num_of_ampdu_queues - 1);
2308 il4965_tx_queue_stop_scheduler(il, txq_id);
2310 il_clear_bits_prph(il, IL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
2312 il->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
2313 il->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
2314 /* supposes that ssn_idx is valid (!= 0xFFF) */
2315 il4965_set_wr_ptrs(il, txq_id, ssn_idx);
2317 il_clear_bits_prph(il, IL49_SCD_INTERRUPT_MASK, (1 << txq_id));
2318 il_txq_ctx_deactivate(il, txq_id);
2319 il4965_tx_queue_set_status(il, &il->txq[txq_id], tx_fifo, 0);
2325 il4965_tx_agg_stop(struct il_priv *il, struct ieee80211_vif *vif,
2326 struct ieee80211_sta *sta, u16 tid)
2328 int tx_fifo_id, txq_id, sta_id, ssn;
2329 struct il_tid_data *tid_data;
2330 int write_ptr, read_ptr;
2331 unsigned long flags;
2333 /* FIXME: warning if tx_fifo_id not found ? */
2334 tx_fifo_id = il4965_get_fifo_from_tid(tid);
2335 if (unlikely(tx_fifo_id < 0))
2338 sta_id = il_sta_id(sta);
2340 if (sta_id == IL_INVALID_STATION) {
2341 IL_ERR("Invalid station for AGG tid %d\n", tid);
2345 spin_lock_irqsave(&il->sta_lock, flags);
2347 tid_data = &il->stations[sta_id].tid[tid];
2348 ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
2349 txq_id = tid_data->agg.txq_id;
2351 switch (il->stations[sta_id].tid[tid].agg.state) {
2352 case IL_EMPTYING_HW_QUEUE_ADDBA:
2354 * This can happen if the peer stops aggregation
2355 * again before we've had a chance to drain the
2356 * queue we selected previously, i.e. before the
2357 * session was really started completely.
2359 D_HT("AGG stop before setup done\n");
2364 IL_WARN("Stopping AGG while state not ON or starting\n");
2367 write_ptr = il->txq[txq_id].q.write_ptr;
2368 read_ptr = il->txq[txq_id].q.read_ptr;
2370 /* The queue is not empty */
2371 if (write_ptr != read_ptr) {
2372 D_HT("Stopping a non empty AGG HW QUEUE\n");
2373 il->stations[sta_id].tid[tid].agg.state =
2374 IL_EMPTYING_HW_QUEUE_DELBA;
2375 spin_unlock_irqrestore(&il->sta_lock, flags);
2379 D_HT("HW queue is empty\n");
2381 il->stations[sta_id].tid[tid].agg.state = IL_AGG_OFF;
2383 /* do not restore/save irqs */
2384 spin_unlock(&il->sta_lock);
2385 spin_lock(&il->lock);
2388 * the only reason this call can fail is queue number out of range,
2389 * which can happen if uCode is reloaded and all the station
2390 * information are lost. if it is outside the range, there is no need
2391 * to deactivate the uCode queue, just return "success" to allow
2392 * mac80211 to clean up it own data.
2394 il4965_txq_agg_disable(il, txq_id, ssn, tx_fifo_id);
2395 spin_unlock_irqrestore(&il->lock, flags);
2397 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
2403 il4965_txq_check_empty(struct il_priv *il, int sta_id, u8 tid, int txq_id)
2405 struct il_queue *q = &il->txq[txq_id].q;
2406 u8 *addr = il->stations[sta_id].sta.sta.addr;
2407 struct il_tid_data *tid_data = &il->stations[sta_id].tid[tid];
2409 lockdep_assert_held(&il->sta_lock);
2411 switch (il->stations[sta_id].tid[tid].agg.state) {
2412 case IL_EMPTYING_HW_QUEUE_DELBA:
2413 /* We are reclaiming the last packet of the */
2414 /* aggregated HW queue */
2415 if (txq_id == tid_data->agg.txq_id &&
2416 q->read_ptr == q->write_ptr) {
2417 u16 ssn = IEEE80211_SEQ_TO_SN(tid_data->seq_number);
2418 int tx_fifo = il4965_get_fifo_from_tid(tid);
2419 D_HT("HW queue empty: continue DELBA flow\n");
2420 il4965_txq_agg_disable(il, txq_id, ssn, tx_fifo);
2421 tid_data->agg.state = IL_AGG_OFF;
2422 ieee80211_stop_tx_ba_cb_irqsafe(il->vif, addr, tid);
2425 case IL_EMPTYING_HW_QUEUE_ADDBA:
2426 /* We are reclaiming the last packet of the queue */
2427 if (tid_data->tfds_in_queue == 0) {
2428 D_HT("HW queue empty: continue ADDBA flow\n");
2429 tid_data->agg.state = IL_AGG_ON;
2430 ieee80211_start_tx_ba_cb_irqsafe(il->vif, addr, tid);
2439 il4965_non_agg_tx_status(struct il_priv *il, const u8 *addr1)
2441 struct ieee80211_sta *sta;
2442 struct il_station_priv *sta_priv;
2445 sta = ieee80211_find_sta(il->vif, addr1);
2447 sta_priv = (void *)sta->drv_priv;
2448 /* avoid atomic ops if this isn't a client */
2449 if (sta_priv->client &&
2450 atomic_dec_return(&sta_priv->pending_frames) == 0)
2451 ieee80211_sta_block_awake(il->hw, sta, false);
2457 il4965_tx_status(struct il_priv *il, struct sk_buff *skb, bool is_agg)
2459 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2462 il4965_non_agg_tx_status(il, hdr->addr1);
2464 ieee80211_tx_status_irqsafe(il->hw, skb);
2468 il4965_tx_queue_reclaim(struct il_priv *il, int txq_id, int idx)
2470 struct il_tx_queue *txq = &il->txq[txq_id];
2471 struct il_queue *q = &txq->q;
2473 struct ieee80211_hdr *hdr;
2474 struct sk_buff *skb;
2476 if (idx >= q->n_bd || il_queue_used(q, idx) == 0) {
2477 IL_ERR("Read idx for DMA queue txq id (%d), idx %d, "
2478 "is out of range [0-%d] %d %d.\n", txq_id, idx, q->n_bd,
2479 q->write_ptr, q->read_ptr);
2483 for (idx = il_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
2484 q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd)) {
2486 skb = txq->skbs[txq->q.read_ptr];
2488 if (WARN_ON_ONCE(skb == NULL))
2491 hdr = (struct ieee80211_hdr *) skb->data;
2492 if (ieee80211_is_data_qos(hdr->frame_control))
2495 il4965_tx_status(il, skb, txq_id >= IL4965_FIRST_AMPDU_QUEUE);
2497 txq->skbs[txq->q.read_ptr] = NULL;
2498 il->ops->txq_free_tfd(il, txq);
2504 * il4965_tx_status_reply_compressed_ba - Update tx status from block-ack
2506 * Go through block-ack's bitmap of ACK'd frames, update driver's record of
2507 * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
2510 il4965_tx_status_reply_compressed_ba(struct il_priv *il, struct il_ht_agg *agg,
2511 struct il_compressed_ba_resp *ba_resp)
2514 u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
2515 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
2517 struct ieee80211_tx_info *info;
2518 u64 bitmap, sent_bitmap;
2520 if (unlikely(!agg->wait_for_ba)) {
2521 if (unlikely(ba_resp->bitmap))
2522 IL_ERR("Received BA when not expected\n");
2526 /* Mark that the expected block-ack response arrived */
2527 agg->wait_for_ba = 0;
2528 D_TX_REPLY("BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
2530 /* Calculate shift to align block-ack bits with our Tx win bits */
2531 sh = agg->start_idx - SEQ_TO_IDX(seq_ctl >> 4);
2532 if (sh < 0) /* tbw something is wrong with indices */
2535 if (agg->frame_count > (64 - sh)) {
2536 D_TX_REPLY("more frames than bitmap size");
2540 /* don't use 64-bit values for now */
2541 bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
2543 /* check for success or failure according to the
2544 * transmitted bitmap and block-ack bitmap */
2545 sent_bitmap = bitmap & agg->bitmap;
2547 /* For each frame attempted in aggregation,
2548 * update driver's record of tx frame's status. */
2550 while (sent_bitmap) {
2551 ack = sent_bitmap & 1ULL;
2553 D_TX_REPLY("%s ON i=%d idx=%d raw=%d\n", ack ? "ACK" : "NACK",
2554 i, (agg->start_idx + i) & 0xff, agg->start_idx + i);
2559 D_TX_REPLY("Bitmap %llx\n", (unsigned long long)bitmap);
2561 info = IEEE80211_SKB_CB(il->txq[scd_flow].skbs[agg->start_idx]);
2562 memset(&info->status, 0, sizeof(info->status));
2563 info->flags |= IEEE80211_TX_STAT_ACK;
2564 info->flags |= IEEE80211_TX_STAT_AMPDU;
2565 info->status.ampdu_ack_len = successes;
2566 info->status.ampdu_len = agg->frame_count;
2567 il4965_hwrate_to_tx_control(il, agg->rate_n_flags, info);
2573 il4965_is_tx_success(u32 status)
2575 status &= TX_STATUS_MSK;
2576 return (status == TX_STATUS_SUCCESS || status == TX_STATUS_DIRECT_DONE);
2580 il4965_find_station(struct il_priv *il, const u8 *addr)
2584 int ret = IL_INVALID_STATION;
2585 unsigned long flags;
2587 if (il->iw_mode == NL80211_IFTYPE_ADHOC)
2590 if (is_broadcast_ether_addr(addr))
2591 return il->hw_params.bcast_id;
2593 spin_lock_irqsave(&il->sta_lock, flags);
2594 for (i = start; i < il->hw_params.max_stations; i++)
2595 if (il->stations[i].used &&
2596 ether_addr_equal(il->stations[i].sta.sta.addr, addr)) {
2601 D_ASSOC("can not find STA %pM total %d\n", addr, il->num_stations);
2605 * It may be possible that more commands interacting with stations
2606 * arrive before we completed processing the adding of
2609 if (ret != IL_INVALID_STATION &&
2610 (!(il->stations[ret].used & IL_STA_UCODE_ACTIVE) ||
2611 ((il->stations[ret].used & IL_STA_UCODE_ACTIVE) &&
2612 (il->stations[ret].used & IL_STA_UCODE_INPROGRESS)))) {
2613 IL_ERR("Requested station info for sta %d before ready.\n",
2615 ret = IL_INVALID_STATION;
2617 spin_unlock_irqrestore(&il->sta_lock, flags);
2622 il4965_get_ra_sta_id(struct il_priv *il, struct ieee80211_hdr *hdr)
2624 if (il->iw_mode == NL80211_IFTYPE_STATION)
2627 u8 *da = ieee80211_get_DA(hdr);
2629 return il4965_find_station(il, da);
2634 il4965_get_scd_ssn(struct il4965_tx_resp *tx_resp)
2636 return le32_to_cpup(&tx_resp->u.status +
2637 tx_resp->frame_count) & IEEE80211_MAX_SN;
2641 il4965_tx_status_to_mac80211(u32 status)
2643 status &= TX_STATUS_MSK;
2646 case TX_STATUS_SUCCESS:
2647 case TX_STATUS_DIRECT_DONE:
2648 return IEEE80211_TX_STAT_ACK;
2649 case TX_STATUS_FAIL_DEST_PS:
2650 return IEEE80211_TX_STAT_TX_FILTERED;
2657 * il4965_tx_status_reply_tx - Handle Tx response for frames in aggregation queue
2660 il4965_tx_status_reply_tx(struct il_priv *il, struct il_ht_agg *agg,
2661 struct il4965_tx_resp *tx_resp, int txq_id,
2665 struct agg_tx_status *frame_status = tx_resp->u.agg_status;
2666 struct ieee80211_tx_info *info = NULL;
2667 struct ieee80211_hdr *hdr = NULL;
2668 u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
2671 if (agg->wait_for_ba)
2672 D_TX_REPLY("got tx response w/o block-ack\n");
2674 agg->frame_count = tx_resp->frame_count;
2675 agg->start_idx = start_idx;
2676 agg->rate_n_flags = rate_n_flags;
2679 /* num frames attempted by Tx command */
2680 if (agg->frame_count == 1) {
2681 /* Only one frame was attempted; no block-ack will arrive */
2682 status = le16_to_cpu(frame_status[0].status);
2685 D_TX_REPLY("FrameCnt = %d, StartIdx=%d idx=%d\n",
2686 agg->frame_count, agg->start_idx, idx);
2688 info = IEEE80211_SKB_CB(il->txq[txq_id].skbs[idx]);
2689 info->status.rates[0].count = tx_resp->failure_frame + 1;
2690 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
2691 info->flags |= il4965_tx_status_to_mac80211(status);
2692 il4965_hwrate_to_tx_control(il, rate_n_flags, info);
2694 D_TX_REPLY("1 Frame 0x%x failure :%d\n", status & 0xff,
2695 tx_resp->failure_frame);
2696 D_TX_REPLY("Rate Info rate_n_flags=%x\n", rate_n_flags);
2698 agg->wait_for_ba = 0;
2700 /* Two or more frames were attempted; expect block-ack */
2702 int start = agg->start_idx;
2703 struct sk_buff *skb;
2705 /* Construct bit-map of pending frames within Tx win */
2706 for (i = 0; i < agg->frame_count; i++) {
2708 status = le16_to_cpu(frame_status[i].status);
2709 seq = le16_to_cpu(frame_status[i].sequence);
2710 idx = SEQ_TO_IDX(seq);
2711 txq_id = SEQ_TO_QUEUE(seq);
2714 (AGG_TX_STATE_FEW_BYTES_MSK |
2715 AGG_TX_STATE_ABORT_MSK))
2718 D_TX_REPLY("FrameCnt = %d, txq_id=%d idx=%d\n",
2719 agg->frame_count, txq_id, idx);
2721 skb = il->txq[txq_id].skbs[idx];
2722 if (WARN_ON_ONCE(skb == NULL))
2724 hdr = (struct ieee80211_hdr *) skb->data;
2726 sc = le16_to_cpu(hdr->seq_ctrl);
2727 if (idx != (IEEE80211_SEQ_TO_SN(sc) & 0xff)) {
2728 IL_ERR("BUG_ON idx doesn't match seq control"
2729 " idx=%d, seq_idx=%d, seq=%d\n", idx,
2730 IEEE80211_SEQ_TO_SN(sc), hdr->seq_ctrl);
2734 D_TX_REPLY("AGG Frame i=%d idx %d seq=%d\n", i, idx,
2735 IEEE80211_SEQ_TO_SN(sc));
2739 sh = (start - idx) + 0xff;
2740 bitmap = bitmap << sh;
2743 } else if (sh < -64)
2744 sh = 0xff - (start - idx);
2748 bitmap = bitmap << sh;
2751 bitmap |= 1ULL << sh;
2752 D_TX_REPLY("start=%d bitmap=0x%llx\n", start,
2753 (unsigned long long)bitmap);
2756 agg->bitmap = bitmap;
2757 agg->start_idx = start;
2758 D_TX_REPLY("Frames %d start_idx=%d bitmap=0x%llx\n",
2759 agg->frame_count, agg->start_idx,
2760 (unsigned long long)agg->bitmap);
2763 agg->wait_for_ba = 1;
2769 * il4965_hdl_tx - Handle standard (non-aggregation) Tx response
2772 il4965_hdl_tx(struct il_priv *il, struct il_rx_buf *rxb)
2774 struct il_rx_pkt *pkt = rxb_addr(rxb);
2775 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
2776 int txq_id = SEQ_TO_QUEUE(sequence);
2777 int idx = SEQ_TO_IDX(sequence);
2778 struct il_tx_queue *txq = &il->txq[txq_id];
2779 struct sk_buff *skb;
2780 struct ieee80211_hdr *hdr;
2781 struct ieee80211_tx_info *info;
2782 struct il4965_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
2783 u32 status = le32_to_cpu(tx_resp->u.status);
2784 int uninitialized_var(tid);
2788 unsigned long flags;
2790 if (idx >= txq->q.n_bd || il_queue_used(&txq->q, idx) == 0) {
2791 IL_ERR("Read idx for DMA queue txq_id (%d) idx %d "
2792 "is out of range [0-%d] %d %d\n", txq_id, idx,
2793 txq->q.n_bd, txq->q.write_ptr, txq->q.read_ptr);
2797 txq->time_stamp = jiffies;
2799 skb = txq->skbs[txq->q.read_ptr];
2800 info = IEEE80211_SKB_CB(skb);
2801 memset(&info->status, 0, sizeof(info->status));
2803 hdr = (struct ieee80211_hdr *) skb->data;
2804 if (ieee80211_is_data_qos(hdr->frame_control)) {
2805 qc = ieee80211_get_qos_ctl(hdr);
2809 sta_id = il4965_get_ra_sta_id(il, hdr);
2810 if (txq->sched_retry && unlikely(sta_id == IL_INVALID_STATION)) {
2811 IL_ERR("Station not known\n");
2815 spin_lock_irqsave(&il->sta_lock, flags);
2816 if (txq->sched_retry) {
2817 const u32 scd_ssn = il4965_get_scd_ssn(tx_resp);
2818 struct il_ht_agg *agg = NULL;
2821 agg = &il->stations[sta_id].tid[tid].agg;
2823 il4965_tx_status_reply_tx(il, agg, tx_resp, txq_id, idx);
2825 /* check if BAR is needed */
2826 if (tx_resp->frame_count == 1 &&
2827 !il4965_is_tx_success(status))
2828 info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
2830 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
2831 idx = il_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
2832 D_TX_REPLY("Retry scheduler reclaim scd_ssn "
2833 "%d idx %d\n", scd_ssn, idx);
2834 freed = il4965_tx_queue_reclaim(il, txq_id, idx);
2836 il4965_free_tfds_in_queue(il, sta_id, tid,
2839 if (il->mac80211_registered &&
2840 il_queue_space(&txq->q) > txq->q.low_mark &&
2841 agg->state != IL_EMPTYING_HW_QUEUE_DELBA)
2842 il_wake_queue(il, txq);
2845 info->status.rates[0].count = tx_resp->failure_frame + 1;
2846 info->flags |= il4965_tx_status_to_mac80211(status);
2847 il4965_hwrate_to_tx_control(il,
2848 le32_to_cpu(tx_resp->rate_n_flags),
2851 D_TX_REPLY("TXQ %d status %s (0x%08x) "
2852 "rate_n_flags 0x%x retries %d\n", txq_id,
2853 il4965_get_tx_fail_reason(status), status,
2854 le32_to_cpu(tx_resp->rate_n_flags),
2855 tx_resp->failure_frame);
2857 freed = il4965_tx_queue_reclaim(il, txq_id, idx);
2858 if (qc && likely(sta_id != IL_INVALID_STATION))
2859 il4965_free_tfds_in_queue(il, sta_id, tid, freed);
2860 else if (sta_id == IL_INVALID_STATION)
2861 D_TX_REPLY("Station not known\n");
2863 if (il->mac80211_registered &&
2864 il_queue_space(&txq->q) > txq->q.low_mark)
2865 il_wake_queue(il, txq);
2867 if (qc && likely(sta_id != IL_INVALID_STATION))
2868 il4965_txq_check_empty(il, sta_id, tid, txq_id);
2870 il4965_check_abort_status(il, tx_resp->frame_count, status);
2872 spin_unlock_irqrestore(&il->sta_lock, flags);
2876 * translate ucode response to mac80211 tx status control values
2879 il4965_hwrate_to_tx_control(struct il_priv *il, u32 rate_n_flags,
2880 struct ieee80211_tx_info *info)
2882 struct ieee80211_tx_rate *r = &info->status.rates[0];
2884 info->status.antenna =
2885 ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
2886 if (rate_n_flags & RATE_MCS_HT_MSK)
2887 r->flags |= IEEE80211_TX_RC_MCS;
2888 if (rate_n_flags & RATE_MCS_GF_MSK)
2889 r->flags |= IEEE80211_TX_RC_GREEN_FIELD;
2890 if (rate_n_flags & RATE_MCS_HT40_MSK)
2891 r->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
2892 if (rate_n_flags & RATE_MCS_DUP_MSK)
2893 r->flags |= IEEE80211_TX_RC_DUP_DATA;
2894 if (rate_n_flags & RATE_MCS_SGI_MSK)
2895 r->flags |= IEEE80211_TX_RC_SHORT_GI;
2896 r->idx = il4965_hwrate_to_mac80211_idx(rate_n_flags, info->band);
2900 * il4965_hdl_compressed_ba - Handler for N_COMPRESSED_BA
2902 * Handles block-acknowledge notification from device, which reports success
2903 * of frames sent via aggregation.
2906 il4965_hdl_compressed_ba(struct il_priv *il, struct il_rx_buf *rxb)
2908 struct il_rx_pkt *pkt = rxb_addr(rxb);
2909 struct il_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
2910 struct il_tx_queue *txq = NULL;
2911 struct il_ht_agg *agg;
2915 unsigned long flags;
2917 /* "flow" corresponds to Tx queue */
2918 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
2920 /* "ssn" is start of block-ack Tx win, corresponds to idx
2921 * (in Tx queue's circular buffer) of first TFD/frame in win */
2922 u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
2924 if (scd_flow >= il->hw_params.max_txq_num) {
2925 IL_ERR("BUG_ON scd_flow is bigger than number of queues\n");
2929 txq = &il->txq[scd_flow];
2930 sta_id = ba_resp->sta_id;
2932 agg = &il->stations[sta_id].tid[tid].agg;
2933 if (unlikely(agg->txq_id != scd_flow)) {
2935 * FIXME: this is a uCode bug which need to be addressed,
2936 * log the information and return for now!
2937 * since it is possible happen very often and in order
2938 * not to fill the syslog, don't enable the logging by default
2940 D_TX_REPLY("BA scd_flow %d does not match txq_id %d\n",
2941 scd_flow, agg->txq_id);
2945 /* Find idx just before block-ack win */
2946 idx = il_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
2948 spin_lock_irqsave(&il->sta_lock, flags);
2950 D_TX_REPLY("N_COMPRESSED_BA [%d] Received from %pM, " "sta_id = %d\n",
2951 agg->wait_for_ba, (u8 *) &ba_resp->sta_addr_lo32,
2953 D_TX_REPLY("TID = %d, SeqCtl = %d, bitmap = 0x%llx," "scd_flow = "
2954 "%d, scd_ssn = %d\n", ba_resp->tid, ba_resp->seq_ctl,
2955 (unsigned long long)le64_to_cpu(ba_resp->bitmap),
2956 ba_resp->scd_flow, ba_resp->scd_ssn);
2957 D_TX_REPLY("DAT start_idx = %d, bitmap = 0x%llx\n", agg->start_idx,
2958 (unsigned long long)agg->bitmap);
2960 /* Update driver's record of ACK vs. not for each frame in win */
2961 il4965_tx_status_reply_compressed_ba(il, agg, ba_resp);
2963 /* Release all TFDs before the SSN, i.e. all TFDs in front of
2964 * block-ack win (we assume that they've been successfully
2965 * transmitted ... if not, it's too late anyway). */
2966 if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
2967 /* calculate mac80211 ampdu sw queue to wake */
2968 int freed = il4965_tx_queue_reclaim(il, scd_flow, idx);
2969 il4965_free_tfds_in_queue(il, sta_id, tid, freed);
2971 if (il_queue_space(&txq->q) > txq->q.low_mark &&
2972 il->mac80211_registered &&
2973 agg->state != IL_EMPTYING_HW_QUEUE_DELBA)
2974 il_wake_queue(il, txq);
2976 il4965_txq_check_empty(il, sta_id, tid, scd_flow);
2979 spin_unlock_irqrestore(&il->sta_lock, flags);
2982 #ifdef CONFIG_IWLEGACY_DEBUG
2984 il4965_get_tx_fail_reason(u32 status)
2986 #define TX_STATUS_FAIL(x) case TX_STATUS_FAIL_ ## x: return #x
2987 #define TX_STATUS_POSTPONE(x) case TX_STATUS_POSTPONE_ ## x: return #x
2989 switch (status & TX_STATUS_MSK) {
2990 case TX_STATUS_SUCCESS:
2992 TX_STATUS_POSTPONE(DELAY);
2993 TX_STATUS_POSTPONE(FEW_BYTES);
2994 TX_STATUS_POSTPONE(QUIET_PERIOD);
2995 TX_STATUS_POSTPONE(CALC_TTAK);
2996 TX_STATUS_FAIL(INTERNAL_CROSSED_RETRY);
2997 TX_STATUS_FAIL(SHORT_LIMIT);
2998 TX_STATUS_FAIL(LONG_LIMIT);
2999 TX_STATUS_FAIL(FIFO_UNDERRUN);
3000 TX_STATUS_FAIL(DRAIN_FLOW);
3001 TX_STATUS_FAIL(RFKILL_FLUSH);
3002 TX_STATUS_FAIL(LIFE_EXPIRE);
3003 TX_STATUS_FAIL(DEST_PS);
3004 TX_STATUS_FAIL(HOST_ABORTED);
3005 TX_STATUS_FAIL(BT_RETRY);
3006 TX_STATUS_FAIL(STA_INVALID);
3007 TX_STATUS_FAIL(FRAG_DROPPED);
3008 TX_STATUS_FAIL(TID_DISABLE);
3009 TX_STATUS_FAIL(FIFO_FLUSHED);
3010 TX_STATUS_FAIL(INSUFFICIENT_CF_POLL);
3011 TX_STATUS_FAIL(PASSIVE_NO_RX);
3012 TX_STATUS_FAIL(NO_BEACON_ON_RADAR);
3017 #undef TX_STATUS_FAIL
3018 #undef TX_STATUS_POSTPONE
3020 #endif /* CONFIG_IWLEGACY_DEBUG */
3022 static struct il_link_quality_cmd *
3023 il4965_sta_alloc_lq(struct il_priv *il, u8 sta_id)
3026 struct il_link_quality_cmd *link_cmd;
3028 __le32 rate_n_flags;
3030 link_cmd = kzalloc(sizeof(struct il_link_quality_cmd), GFP_KERNEL);
3032 IL_ERR("Unable to allocate memory for LQ cmd.\n");
3035 /* Set up the rate scaling to start at selected rate, fall back
3036 * all the way down to 1M in IEEE order, and then spin on 1M */
3037 if (il->band == IEEE80211_BAND_5GHZ)
3042 if (r >= IL_FIRST_CCK_RATE && r <= IL_LAST_CCK_RATE)
3043 rate_flags |= RATE_MCS_CCK_MSK;
3046 il4965_first_antenna(il->hw_params.
3047 valid_tx_ant) << RATE_MCS_ANT_POS;
3048 rate_n_flags = cpu_to_le32(il_rates[r].plcp | rate_flags);
3049 for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++)
3050 link_cmd->rs_table[i].rate_n_flags = rate_n_flags;
3052 link_cmd->general_params.single_stream_ant_msk =
3053 il4965_first_antenna(il->hw_params.valid_tx_ant);
3055 link_cmd->general_params.dual_stream_ant_msk =
3056 il->hw_params.valid_tx_ant & ~il4965_first_antenna(il->hw_params.
3058 if (!link_cmd->general_params.dual_stream_ant_msk) {
3059 link_cmd->general_params.dual_stream_ant_msk = ANT_AB;
3060 } else if (il4965_num_of_ant(il->hw_params.valid_tx_ant) == 2) {
3061 link_cmd->general_params.dual_stream_ant_msk =
3062 il->hw_params.valid_tx_ant;
3065 link_cmd->agg_params.agg_dis_start_th = LINK_QUAL_AGG_DISABLE_START_DEF;
3066 link_cmd->agg_params.agg_time_limit =
3067 cpu_to_le16(LINK_QUAL_AGG_TIME_LIMIT_DEF);
3069 link_cmd->sta_id = sta_id;
3075 * il4965_add_bssid_station - Add the special IBSS BSSID station
3080 il4965_add_bssid_station(struct il_priv *il, const u8 *addr, u8 *sta_id_r)
3084 struct il_link_quality_cmd *link_cmd;
3085 unsigned long flags;
3088 *sta_id_r = IL_INVALID_STATION;
3090 ret = il_add_station_common(il, addr, 0, NULL, &sta_id);
3092 IL_ERR("Unable to add station %pM\n", addr);
3099 spin_lock_irqsave(&il->sta_lock, flags);
3100 il->stations[sta_id].used |= IL_STA_LOCAL;
3101 spin_unlock_irqrestore(&il->sta_lock, flags);
3103 /* Set up default rate scaling table in device's station table */
3104 link_cmd = il4965_sta_alloc_lq(il, sta_id);
3106 IL_ERR("Unable to initialize rate scaling for station %pM.\n",
3111 ret = il_send_lq_cmd(il, link_cmd, CMD_SYNC, true);
3113 IL_ERR("Link quality command failed (%d)\n", ret);
3115 spin_lock_irqsave(&il->sta_lock, flags);
3116 il->stations[sta_id].lq = link_cmd;
3117 spin_unlock_irqrestore(&il->sta_lock, flags);
3123 il4965_static_wepkey_cmd(struct il_priv *il, bool send_if_empty)
3126 u8 buff[sizeof(struct il_wep_cmd) +
3127 sizeof(struct il_wep_key) * WEP_KEYS_MAX];
3128 struct il_wep_cmd *wep_cmd = (struct il_wep_cmd *)buff;
3129 size_t cmd_size = sizeof(struct il_wep_cmd);
3130 struct il_host_cmd cmd = {
3135 bool not_empty = false;
3140 cmd_size + (sizeof(struct il_wep_key) * WEP_KEYS_MAX));
3142 for (i = 0; i < WEP_KEYS_MAX; i++) {
3143 u8 key_size = il->_4965.wep_keys[i].key_size;
3145 wep_cmd->key[i].key_idx = i;
3147 wep_cmd->key[i].key_offset = i;
3150 wep_cmd->key[i].key_offset = WEP_INVALID_OFFSET;
3152 wep_cmd->key[i].key_size = key_size;
3153 memcpy(&wep_cmd->key[i].key[3], il->_4965.wep_keys[i].key, key_size);
3156 wep_cmd->global_key_type = WEP_KEY_WEP_TYPE;
3157 wep_cmd->num_keys = WEP_KEYS_MAX;
3159 cmd_size += sizeof(struct il_wep_key) * WEP_KEYS_MAX;
3162 if (not_empty || send_if_empty)
3163 return il_send_cmd(il, &cmd);
3169 il4965_restore_default_wep_keys(struct il_priv *il)
3171 lockdep_assert_held(&il->mutex);
3173 return il4965_static_wepkey_cmd(il, false);
3177 il4965_remove_default_wep_key(struct il_priv *il,
3178 struct ieee80211_key_conf *keyconf)
3181 int idx = keyconf->keyidx;
3183 lockdep_assert_held(&il->mutex);
3185 D_WEP("Removing default WEP key: idx=%d\n", idx);
3187 memset(&il->_4965.wep_keys[idx], 0, sizeof(struct il_wep_key));
3188 if (il_is_rfkill(il)) {
3189 D_WEP("Not sending C_WEPKEY command due to RFKILL.\n");
3190 /* but keys in device are clear anyway so return success */
3193 ret = il4965_static_wepkey_cmd(il, 1);
3194 D_WEP("Remove default WEP key: idx=%d ret=%d\n", idx, ret);
3200 il4965_set_default_wep_key(struct il_priv *il,
3201 struct ieee80211_key_conf *keyconf)
3204 int len = keyconf->keylen;
3205 int idx = keyconf->keyidx;
3207 lockdep_assert_held(&il->mutex);
3209 if (len != WEP_KEY_LEN_128 && len != WEP_KEY_LEN_64) {
3210 D_WEP("Bad WEP key length %d\n", keyconf->keylen);
3214 keyconf->flags &= ~IEEE80211_KEY_FLAG_GENERATE_IV;
3215 keyconf->hw_key_idx = HW_KEY_DEFAULT;
3216 il->stations[IL_AP_ID].keyinfo.cipher = keyconf->cipher;
3218 il->_4965.wep_keys[idx].key_size = len;
3219 memcpy(&il->_4965.wep_keys[idx].key, &keyconf->key, len);
3221 ret = il4965_static_wepkey_cmd(il, false);
3223 D_WEP("Set default WEP key: len=%d idx=%d ret=%d\n", len, idx, ret);
3228 il4965_set_wep_dynamic_key_info(struct il_priv *il,
3229 struct ieee80211_key_conf *keyconf, u8 sta_id)
3231 unsigned long flags;
3232 __le16 key_flags = 0;
3233 struct il_addsta_cmd sta_cmd;
3235 lockdep_assert_held(&il->mutex);
3237 keyconf->flags &= ~IEEE80211_KEY_FLAG_GENERATE_IV;
3239 key_flags |= (STA_KEY_FLG_WEP | STA_KEY_FLG_MAP_KEY_MSK);
3240 key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
3241 key_flags &= ~STA_KEY_FLG_INVALID;
3243 if (keyconf->keylen == WEP_KEY_LEN_128)
3244 key_flags |= STA_KEY_FLG_KEY_SIZE_MSK;
3246 if (sta_id == il->hw_params.bcast_id)
3247 key_flags |= STA_KEY_MULTICAST_MSK;
3249 spin_lock_irqsave(&il->sta_lock, flags);
3251 il->stations[sta_id].keyinfo.cipher = keyconf->cipher;
3252 il->stations[sta_id].keyinfo.keylen = keyconf->keylen;
3253 il->stations[sta_id].keyinfo.keyidx = keyconf->keyidx;
3255 memcpy(il->stations[sta_id].keyinfo.key, keyconf->key, keyconf->keylen);
3257 memcpy(&il->stations[sta_id].sta.key.key[3], keyconf->key,
3260 if ((il->stations[sta_id].sta.key.
3261 key_flags & STA_KEY_FLG_ENCRYPT_MSK) == STA_KEY_FLG_NO_ENC)
3262 il->stations[sta_id].sta.key.key_offset =
3263 il_get_free_ucode_key_idx(il);
3264 /* else, we are overriding an existing key => no need to allocated room
3267 WARN(il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
3268 "no space for a new key");
3270 il->stations[sta_id].sta.key.key_flags = key_flags;
3271 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
3272 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3274 memcpy(&sta_cmd, &il->stations[sta_id].sta,
3275 sizeof(struct il_addsta_cmd));
3276 spin_unlock_irqrestore(&il->sta_lock, flags);
3278 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
3282 il4965_set_ccmp_dynamic_key_info(struct il_priv *il,
3283 struct ieee80211_key_conf *keyconf, u8 sta_id)
3285 unsigned long flags;
3286 __le16 key_flags = 0;
3287 struct il_addsta_cmd sta_cmd;
3289 lockdep_assert_held(&il->mutex);
3291 key_flags |= (STA_KEY_FLG_CCMP | STA_KEY_FLG_MAP_KEY_MSK);
3292 key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
3293 key_flags &= ~STA_KEY_FLG_INVALID;
3295 if (sta_id == il->hw_params.bcast_id)
3296 key_flags |= STA_KEY_MULTICAST_MSK;
3298 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
3300 spin_lock_irqsave(&il->sta_lock, flags);
3301 il->stations[sta_id].keyinfo.cipher = keyconf->cipher;
3302 il->stations[sta_id].keyinfo.keylen = keyconf->keylen;
3304 memcpy(il->stations[sta_id].keyinfo.key, keyconf->key, keyconf->keylen);
3306 memcpy(il->stations[sta_id].sta.key.key, keyconf->key, keyconf->keylen);
3308 if ((il->stations[sta_id].sta.key.
3309 key_flags & STA_KEY_FLG_ENCRYPT_MSK) == STA_KEY_FLG_NO_ENC)
3310 il->stations[sta_id].sta.key.key_offset =
3311 il_get_free_ucode_key_idx(il);
3312 /* else, we are overriding an existing key => no need to allocated room
3315 WARN(il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
3316 "no space for a new key");
3318 il->stations[sta_id].sta.key.key_flags = key_flags;
3319 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
3320 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3322 memcpy(&sta_cmd, &il->stations[sta_id].sta,
3323 sizeof(struct il_addsta_cmd));
3324 spin_unlock_irqrestore(&il->sta_lock, flags);
3326 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
3330 il4965_set_tkip_dynamic_key_info(struct il_priv *il,
3331 struct ieee80211_key_conf *keyconf, u8 sta_id)
3333 unsigned long flags;
3335 __le16 key_flags = 0;
3337 key_flags |= (STA_KEY_FLG_TKIP | STA_KEY_FLG_MAP_KEY_MSK);
3338 key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
3339 key_flags &= ~STA_KEY_FLG_INVALID;
3341 if (sta_id == il->hw_params.bcast_id)
3342 key_flags |= STA_KEY_MULTICAST_MSK;
3344 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
3345 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
3347 spin_lock_irqsave(&il->sta_lock, flags);
3349 il->stations[sta_id].keyinfo.cipher = keyconf->cipher;
3350 il->stations[sta_id].keyinfo.keylen = 16;
3352 if ((il->stations[sta_id].sta.key.
3353 key_flags & STA_KEY_FLG_ENCRYPT_MSK) == STA_KEY_FLG_NO_ENC)
3354 il->stations[sta_id].sta.key.key_offset =
3355 il_get_free_ucode_key_idx(il);
3356 /* else, we are overriding an existing key => no need to allocated room
3359 WARN(il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
3360 "no space for a new key");
3362 il->stations[sta_id].sta.key.key_flags = key_flags;
3364 /* This copy is acutally not needed: we get the key with each TX */
3365 memcpy(il->stations[sta_id].keyinfo.key, keyconf->key, 16);
3367 memcpy(il->stations[sta_id].sta.key.key, keyconf->key, 16);
3369 spin_unlock_irqrestore(&il->sta_lock, flags);
3375 il4965_update_tkip_key(struct il_priv *il, struct ieee80211_key_conf *keyconf,
3376 struct ieee80211_sta *sta, u32 iv32, u16 *phase1key)
3379 unsigned long flags;
3382 if (il_scan_cancel(il)) {
3383 /* cancel scan failed, just live w/ bad key and rely
3384 briefly on SW decryption */
3388 sta_id = il_sta_id_or_broadcast(il, sta);
3389 if (sta_id == IL_INVALID_STATION)
3392 spin_lock_irqsave(&il->sta_lock, flags);
3394 il->stations[sta_id].sta.key.tkip_rx_tsc_byte2 = (u8) iv32;
3396 for (i = 0; i < 5; i++)
3397 il->stations[sta_id].sta.key.tkip_rx_ttak[i] =
3398 cpu_to_le16(phase1key[i]);
3400 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
3401 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3403 il_send_add_sta(il, &il->stations[sta_id].sta, CMD_ASYNC);
3405 spin_unlock_irqrestore(&il->sta_lock, flags);
3409 il4965_remove_dynamic_key(struct il_priv *il,
3410 struct ieee80211_key_conf *keyconf, u8 sta_id)
3412 unsigned long flags;
3415 struct il_addsta_cmd sta_cmd;
3417 lockdep_assert_held(&il->mutex);
3419 il->_4965.key_mapping_keys--;
3421 spin_lock_irqsave(&il->sta_lock, flags);
3422 key_flags = le16_to_cpu(il->stations[sta_id].sta.key.key_flags);
3423 keyidx = (key_flags >> STA_KEY_FLG_KEYID_POS) & 0x3;
3425 D_WEP("Remove dynamic key: idx=%d sta=%d\n", keyconf->keyidx, sta_id);
3427 if (keyconf->keyidx != keyidx) {
3428 /* We need to remove a key with idx different that the one
3429 * in the uCode. This means that the key we need to remove has
3430 * been replaced by another one with different idx.
3431 * Don't do anything and return ok
3433 spin_unlock_irqrestore(&il->sta_lock, flags);
3437 if (il->stations[sta_id].sta.key.key_flags & STA_KEY_FLG_INVALID) {
3438 IL_WARN("Removing wrong key %d 0x%x\n", keyconf->keyidx,
3440 spin_unlock_irqrestore(&il->sta_lock, flags);
3444 if (!test_and_clear_bit
3445 (il->stations[sta_id].sta.key.key_offset, &il->ucode_key_table))
3446 IL_ERR("idx %d not used in uCode key table.\n",
3447 il->stations[sta_id].sta.key.key_offset);
3448 memset(&il->stations[sta_id].keyinfo, 0, sizeof(struct il_hw_key));
3449 memset(&il->stations[sta_id].sta.key, 0, sizeof(struct il4965_keyinfo));
3450 il->stations[sta_id].sta.key.key_flags =
3451 STA_KEY_FLG_NO_ENC | STA_KEY_FLG_INVALID;
3452 il->stations[sta_id].sta.key.key_offset = keyconf->hw_key_idx;
3453 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
3454 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3456 if (il_is_rfkill(il)) {
3458 ("Not sending C_ADD_STA command because RFKILL enabled.\n");
3459 spin_unlock_irqrestore(&il->sta_lock, flags);
3462 memcpy(&sta_cmd, &il->stations[sta_id].sta,
3463 sizeof(struct il_addsta_cmd));
3464 spin_unlock_irqrestore(&il->sta_lock, flags);
3466 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
3470 il4965_set_dynamic_key(struct il_priv *il, struct ieee80211_key_conf *keyconf,
3475 lockdep_assert_held(&il->mutex);
3477 il->_4965.key_mapping_keys++;
3478 keyconf->hw_key_idx = HW_KEY_DYNAMIC;
3480 switch (keyconf->cipher) {
3481 case WLAN_CIPHER_SUITE_CCMP:
3483 il4965_set_ccmp_dynamic_key_info(il, keyconf, sta_id);
3485 case WLAN_CIPHER_SUITE_TKIP:
3487 il4965_set_tkip_dynamic_key_info(il, keyconf, sta_id);
3489 case WLAN_CIPHER_SUITE_WEP40:
3490 case WLAN_CIPHER_SUITE_WEP104:
3491 ret = il4965_set_wep_dynamic_key_info(il, keyconf, sta_id);
3494 IL_ERR("Unknown alg: %s cipher = %x\n", __func__,
3499 D_WEP("Set dynamic key: cipher=%x len=%d idx=%d sta=%d ret=%d\n",
3500 keyconf->cipher, keyconf->keylen, keyconf->keyidx, sta_id, ret);
3506 * il4965_alloc_bcast_station - add broadcast station into driver's station table.
3508 * This adds the broadcast station into the driver's station table
3509 * and marks it driver active, so that it will be restored to the
3510 * device at the next best time.
3513 il4965_alloc_bcast_station(struct il_priv *il)
3515 struct il_link_quality_cmd *link_cmd;
3516 unsigned long flags;
3519 spin_lock_irqsave(&il->sta_lock, flags);
3520 sta_id = il_prep_station(il, il_bcast_addr, false, NULL);
3521 if (sta_id == IL_INVALID_STATION) {
3522 IL_ERR("Unable to prepare broadcast station\n");
3523 spin_unlock_irqrestore(&il->sta_lock, flags);
3528 il->stations[sta_id].used |= IL_STA_DRIVER_ACTIVE;
3529 il->stations[sta_id].used |= IL_STA_BCAST;
3530 spin_unlock_irqrestore(&il->sta_lock, flags);
3532 link_cmd = il4965_sta_alloc_lq(il, sta_id);
3535 ("Unable to initialize rate scaling for bcast station.\n");
3539 spin_lock_irqsave(&il->sta_lock, flags);
3540 il->stations[sta_id].lq = link_cmd;
3541 spin_unlock_irqrestore(&il->sta_lock, flags);
3547 * il4965_update_bcast_station - update broadcast station's LQ command
3549 * Only used by iwl4965. Placed here to have all bcast station management
3553 il4965_update_bcast_station(struct il_priv *il)
3555 unsigned long flags;
3556 struct il_link_quality_cmd *link_cmd;
3557 u8 sta_id = il->hw_params.bcast_id;
3559 link_cmd = il4965_sta_alloc_lq(il, sta_id);
3561 IL_ERR("Unable to initialize rate scaling for bcast sta.\n");
3565 spin_lock_irqsave(&il->sta_lock, flags);
3566 if (il->stations[sta_id].lq)
3567 kfree(il->stations[sta_id].lq);
3569 D_INFO("Bcast sta rate scaling has not been initialized.\n");
3570 il->stations[sta_id].lq = link_cmd;
3571 spin_unlock_irqrestore(&il->sta_lock, flags);
3577 il4965_update_bcast_stations(struct il_priv *il)
3579 return il4965_update_bcast_station(il);
3583 * il4965_sta_tx_modify_enable_tid - Enable Tx for this TID in station table
3586 il4965_sta_tx_modify_enable_tid(struct il_priv *il, int sta_id, int tid)
3588 unsigned long flags;
3589 struct il_addsta_cmd sta_cmd;
3591 lockdep_assert_held(&il->mutex);
3593 /* Remove "disable" flag, to enable Tx for this TID */
3594 spin_lock_irqsave(&il->sta_lock, flags);
3595 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_TID_DISABLE_TX;
3596 il->stations[sta_id].sta.tid_disable_tx &= cpu_to_le16(~(1 << tid));
3597 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3598 memcpy(&sta_cmd, &il->stations[sta_id].sta,
3599 sizeof(struct il_addsta_cmd));
3600 spin_unlock_irqrestore(&il->sta_lock, flags);
3602 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
3606 il4965_sta_rx_agg_start(struct il_priv *il, struct ieee80211_sta *sta, int tid,
3609 unsigned long flags;
3611 struct il_addsta_cmd sta_cmd;
3613 lockdep_assert_held(&il->mutex);
3615 sta_id = il_sta_id(sta);
3616 if (sta_id == IL_INVALID_STATION)
3619 spin_lock_irqsave(&il->sta_lock, flags);
3620 il->stations[sta_id].sta.station_flags_msk = 0;
3621 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_ADDBA_TID_MSK;
3622 il->stations[sta_id].sta.add_immediate_ba_tid = (u8) tid;
3623 il->stations[sta_id].sta.add_immediate_ba_ssn = cpu_to_le16(ssn);
3624 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3625 memcpy(&sta_cmd, &il->stations[sta_id].sta,
3626 sizeof(struct il_addsta_cmd));
3627 spin_unlock_irqrestore(&il->sta_lock, flags);
3629 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
3633 il4965_sta_rx_agg_stop(struct il_priv *il, struct ieee80211_sta *sta, int tid)
3635 unsigned long flags;
3637 struct il_addsta_cmd sta_cmd;
3639 lockdep_assert_held(&il->mutex);
3641 sta_id = il_sta_id(sta);
3642 if (sta_id == IL_INVALID_STATION) {
3643 IL_ERR("Invalid station for AGG tid %d\n", tid);
3647 spin_lock_irqsave(&il->sta_lock, flags);
3648 il->stations[sta_id].sta.station_flags_msk = 0;
3649 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_DELBA_TID_MSK;
3650 il->stations[sta_id].sta.remove_immediate_ba_tid = (u8) tid;
3651 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3652 memcpy(&sta_cmd, &il->stations[sta_id].sta,
3653 sizeof(struct il_addsta_cmd));
3654 spin_unlock_irqrestore(&il->sta_lock, flags);
3656 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
3660 il4965_sta_modify_sleep_tx_count(struct il_priv *il, int sta_id, int cnt)
3662 unsigned long flags;
3664 spin_lock_irqsave(&il->sta_lock, flags);
3665 il->stations[sta_id].sta.station_flags |= STA_FLG_PWR_SAVE_MSK;
3666 il->stations[sta_id].sta.station_flags_msk = STA_FLG_PWR_SAVE_MSK;
3667 il->stations[sta_id].sta.sta.modify_mask =
3668 STA_MODIFY_SLEEP_TX_COUNT_MSK;
3669 il->stations[sta_id].sta.sleep_tx_count = cpu_to_le16(cnt);
3670 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3671 il_send_add_sta(il, &il->stations[sta_id].sta, CMD_ASYNC);
3672 spin_unlock_irqrestore(&il->sta_lock, flags);
3677 il4965_update_chain_flags(struct il_priv *il)
3679 if (il->ops->set_rxon_chain) {
3680 il->ops->set_rxon_chain(il);
3681 if (il->active.rx_chain != il->staging.rx_chain)
3687 il4965_clear_free_frames(struct il_priv *il)
3689 struct list_head *element;
3691 D_INFO("%d frames on pre-allocated heap on clear.\n", il->frames_count);
3693 while (!list_empty(&il->free_frames)) {
3694 element = il->free_frames.next;
3696 kfree(list_entry(element, struct il_frame, list));
3700 if (il->frames_count) {
3701 IL_WARN("%d frames still in use. Did we lose one?\n",
3703 il->frames_count = 0;
3707 static struct il_frame *
3708 il4965_get_free_frame(struct il_priv *il)
3710 struct il_frame *frame;
3711 struct list_head *element;
3712 if (list_empty(&il->free_frames)) {
3713 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
3715 IL_ERR("Could not allocate frame!\n");
3723 element = il->free_frames.next;
3725 return list_entry(element, struct il_frame, list);
3729 il4965_free_frame(struct il_priv *il, struct il_frame *frame)
3731 memset(frame, 0, sizeof(*frame));
3732 list_add(&frame->list, &il->free_frames);
3736 il4965_fill_beacon_frame(struct il_priv *il, struct ieee80211_hdr *hdr,
3739 lockdep_assert_held(&il->mutex);
3741 if (!il->beacon_skb)
3744 if (il->beacon_skb->len > left)
3747 memcpy(hdr, il->beacon_skb->data, il->beacon_skb->len);
3749 return il->beacon_skb->len;
3752 /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
3754 il4965_set_beacon_tim(struct il_priv *il,
3755 struct il_tx_beacon_cmd *tx_beacon_cmd, u8 * beacon,
3759 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
3762 * The idx is relative to frame start but we start looking at the
3763 * variable-length part of the beacon.
3765 tim_idx = mgmt->u.beacon.variable - beacon;
3767 /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
3768 while ((tim_idx < (frame_size - 2)) &&
3769 (beacon[tim_idx] != WLAN_EID_TIM))
3770 tim_idx += beacon[tim_idx + 1] + 2;
3772 /* If TIM field was found, set variables */
3773 if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
3774 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
3775 tx_beacon_cmd->tim_size = beacon[tim_idx + 1];
3777 IL_WARN("Unable to find TIM Element in beacon\n");
3781 il4965_hw_get_beacon_cmd(struct il_priv *il, struct il_frame *frame)
3783 struct il_tx_beacon_cmd *tx_beacon_cmd;
3788 * We have to set up the TX command, the TX Beacon command, and the
3792 lockdep_assert_held(&il->mutex);
3794 if (!il->beacon_enabled) {
3795 IL_ERR("Trying to build beacon without beaconing enabled\n");
3799 /* Initialize memory */
3800 tx_beacon_cmd = &frame->u.beacon;
3801 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
3803 /* Set up TX beacon contents */
3805 il4965_fill_beacon_frame(il, tx_beacon_cmd->frame,
3806 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
3807 if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
3812 /* Set up TX command fields */
3813 tx_beacon_cmd->tx.len = cpu_to_le16((u16) frame_size);
3814 tx_beacon_cmd->tx.sta_id = il->hw_params.bcast_id;
3815 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
3816 tx_beacon_cmd->tx.tx_flags =
3817 TX_CMD_FLG_SEQ_CTL_MSK | TX_CMD_FLG_TSF_MSK |
3818 TX_CMD_FLG_STA_RATE_MSK;
3820 /* Set up TX beacon command fields */
3821 il4965_set_beacon_tim(il, tx_beacon_cmd, (u8 *) tx_beacon_cmd->frame,
3824 /* Set up packet rate and flags */
3825 rate = il_get_lowest_plcp(il);
3826 il4965_toggle_tx_ant(il, &il->mgmt_tx_ant, il->hw_params.valid_tx_ant);
3827 rate_flags = BIT(il->mgmt_tx_ant) << RATE_MCS_ANT_POS;
3828 if ((rate >= IL_FIRST_CCK_RATE) && (rate <= IL_LAST_CCK_RATE))
3829 rate_flags |= RATE_MCS_CCK_MSK;
3830 tx_beacon_cmd->tx.rate_n_flags = cpu_to_le32(rate | rate_flags);
3832 return sizeof(*tx_beacon_cmd) + frame_size;
3836 il4965_send_beacon_cmd(struct il_priv *il)
3838 struct il_frame *frame;
3839 unsigned int frame_size;
3842 frame = il4965_get_free_frame(il);
3844 IL_ERR("Could not obtain free frame buffer for beacon "
3849 frame_size = il4965_hw_get_beacon_cmd(il, frame);
3851 IL_ERR("Error configuring the beacon command\n");
3852 il4965_free_frame(il, frame);
3856 rc = il_send_cmd_pdu(il, C_TX_BEACON, frame_size, &frame->u.cmd[0]);
3858 il4965_free_frame(il, frame);
3863 static inline dma_addr_t
3864 il4965_tfd_tb_get_addr(struct il_tfd *tfd, u8 idx)
3866 struct il_tfd_tb *tb = &tfd->tbs[idx];
3868 dma_addr_t addr = get_unaligned_le32(&tb->lo);
3869 if (sizeof(dma_addr_t) > sizeof(u32))
3871 ((dma_addr_t) (le16_to_cpu(tb->hi_n_len) & 0xF) << 16) <<
3878 il4965_tfd_tb_get_len(struct il_tfd *tfd, u8 idx)
3880 struct il_tfd_tb *tb = &tfd->tbs[idx];
3882 return le16_to_cpu(tb->hi_n_len) >> 4;
3886 il4965_tfd_set_tb(struct il_tfd *tfd, u8 idx, dma_addr_t addr, u16 len)
3888 struct il_tfd_tb *tb = &tfd->tbs[idx];
3889 u16 hi_n_len = len << 4;
3891 put_unaligned_le32(addr, &tb->lo);
3892 if (sizeof(dma_addr_t) > sizeof(u32))
3893 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
3895 tb->hi_n_len = cpu_to_le16(hi_n_len);
3897 tfd->num_tbs = idx + 1;
3901 il4965_tfd_get_num_tbs(struct il_tfd *tfd)
3903 return tfd->num_tbs & 0x1f;
3907 * il4965_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
3908 * @il - driver ilate data
3911 * Does NOT advance any TFD circular buffer read/write idxes
3912 * Does NOT free the TFD itself (which is within circular buffer)
3915 il4965_hw_txq_free_tfd(struct il_priv *il, struct il_tx_queue *txq)
3917 struct il_tfd *tfd_tmp = (struct il_tfd *)txq->tfds;
3919 struct pci_dev *dev = il->pci_dev;
3920 int idx = txq->q.read_ptr;
3924 tfd = &tfd_tmp[idx];
3926 /* Sanity check on number of chunks */
3927 num_tbs = il4965_tfd_get_num_tbs(tfd);
3929 if (num_tbs >= IL_NUM_OF_TBS) {
3930 IL_ERR("Too many chunks: %i\n", num_tbs);
3931 /* @todo issue fatal error, it is quite serious situation */
3937 pci_unmap_single(dev, dma_unmap_addr(&txq->meta[idx], mapping),
3938 dma_unmap_len(&txq->meta[idx], len),
3939 PCI_DMA_BIDIRECTIONAL);
3941 /* Unmap chunks, if any. */
3942 for (i = 1; i < num_tbs; i++)
3943 pci_unmap_single(dev, il4965_tfd_tb_get_addr(tfd, i),
3944 il4965_tfd_tb_get_len(tfd, i),
3949 struct sk_buff *skb = txq->skbs[txq->q.read_ptr];
3951 /* can be called from irqs-disabled context */
3953 dev_kfree_skb_any(skb);
3954 txq->skbs[txq->q.read_ptr] = NULL;
3960 il4965_hw_txq_attach_buf_to_tfd(struct il_priv *il, struct il_tx_queue *txq,
3961 dma_addr_t addr, u16 len, u8 reset, u8 pad)
3964 struct il_tfd *tfd, *tfd_tmp;
3968 tfd_tmp = (struct il_tfd *)txq->tfds;
3969 tfd = &tfd_tmp[q->write_ptr];
3972 memset(tfd, 0, sizeof(*tfd));
3974 num_tbs = il4965_tfd_get_num_tbs(tfd);
3976 /* Each TFD can point to a maximum 20 Tx buffers */
3977 if (num_tbs >= IL_NUM_OF_TBS) {
3978 IL_ERR("Error can not send more than %d chunks\n",
3983 BUG_ON(addr & ~DMA_BIT_MASK(36));
3984 if (unlikely(addr & ~IL_TX_DMA_MASK))
3985 IL_ERR("Unaligned address = %llx\n", (unsigned long long)addr);
3987 il4965_tfd_set_tb(tfd, num_tbs, addr, len);
3993 * Tell nic where to find circular buffer of Tx Frame Descriptors for
3994 * given Tx queue, and enable the DMA channel used for that queue.
3996 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
3997 * channels supported in hardware.
4000 il4965_hw_tx_queue_init(struct il_priv *il, struct il_tx_queue *txq)
4002 int txq_id = txq->q.id;
4004 /* Circular buffer (TFD queue in DRAM) physical base address */
4005 il_wr(il, FH49_MEM_CBBC_QUEUE(txq_id), txq->q.dma_addr >> 8);
4010 /******************************************************************************
4012 * Generic RX handler implementations
4014 ******************************************************************************/
4016 il4965_hdl_alive(struct il_priv *il, struct il_rx_buf *rxb)
4018 struct il_rx_pkt *pkt = rxb_addr(rxb);
4019 struct il_alive_resp *palive;
4020 struct delayed_work *pwork;
4022 palive = &pkt->u.alive_frame;
4024 D_INFO("Alive ucode status 0x%08X revision " "0x%01X 0x%01X\n",
4025 palive->is_valid, palive->ver_type, palive->ver_subtype);
4027 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
4028 D_INFO("Initialization Alive received.\n");
4029 memcpy(&il->card_alive_init, &pkt->u.alive_frame,
4030 sizeof(struct il_init_alive_resp));
4031 pwork = &il->init_alive_start;
4033 D_INFO("Runtime Alive received.\n");
4034 memcpy(&il->card_alive, &pkt->u.alive_frame,
4035 sizeof(struct il_alive_resp));
4036 pwork = &il->alive_start;
4039 /* We delay the ALIVE response by 5ms to
4040 * give the HW RF Kill time to activate... */
4041 if (palive->is_valid == UCODE_VALID_OK)
4042 queue_delayed_work(il->workqueue, pwork, msecs_to_jiffies(5));
4044 IL_WARN("uCode did not respond OK.\n");
4048 * il4965_bg_stats_periodic - Timer callback to queue stats
4050 * This callback is provided in order to send a stats request.
4052 * This timer function is continually reset to execute within
4053 * 60 seconds since the last N_STATS was received. We need to
4054 * ensure we receive the stats in order to update the temperature
4055 * used for calibrating the TXPOWER.
4058 il4965_bg_stats_periodic(unsigned long data)
4060 struct il_priv *il = (struct il_priv *)data;
4062 if (test_bit(S_EXIT_PENDING, &il->status))
4065 /* dont send host command if rf-kill is on */
4066 if (!il_is_ready_rf(il))
4069 il_send_stats_request(il, CMD_ASYNC, false);
4073 il4965_hdl_beacon(struct il_priv *il, struct il_rx_buf *rxb)
4075 struct il_rx_pkt *pkt = rxb_addr(rxb);
4076 struct il4965_beacon_notif *beacon =
4077 (struct il4965_beacon_notif *)pkt->u.raw;
4078 #ifdef CONFIG_IWLEGACY_DEBUG
4079 u8 rate = il4965_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
4081 D_RX("beacon status %x retries %d iss %d tsf:0x%.8x%.8x rate %d\n",
4082 le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
4083 beacon->beacon_notify_hdr.failure_frame,
4084 le32_to_cpu(beacon->ibss_mgr_status),
4085 le32_to_cpu(beacon->high_tsf), le32_to_cpu(beacon->low_tsf), rate);
4087 il->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status);
4091 il4965_perform_ct_kill_task(struct il_priv *il)
4093 unsigned long flags;
4095 D_POWER("Stop all queues\n");
4097 if (il->mac80211_registered)
4098 ieee80211_stop_queues(il->hw);
4100 _il_wr(il, CSR_UCODE_DRV_GP1_SET,
4101 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
4102 _il_rd(il, CSR_UCODE_DRV_GP1);
4104 spin_lock_irqsave(&il->reg_lock, flags);
4105 if (likely(_il_grab_nic_access(il)))
4106 _il_release_nic_access(il);
4107 spin_unlock_irqrestore(&il->reg_lock, flags);
4110 /* Handle notification from uCode that card's power state is changing
4111 * due to software, hardware, or critical temperature RFKILL */
4113 il4965_hdl_card_state(struct il_priv *il, struct il_rx_buf *rxb)
4115 struct il_rx_pkt *pkt = rxb_addr(rxb);
4116 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
4117 unsigned long status = il->status;
4119 D_RF_KILL("Card state received: HW:%s SW:%s CT:%s\n",
4120 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
4121 (flags & SW_CARD_DISABLED) ? "Kill" : "On",
4122 (flags & CT_CARD_DISABLED) ? "Reached" : "Not reached");
4124 if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED | CT_CARD_DISABLED)) {
4126 _il_wr(il, CSR_UCODE_DRV_GP1_SET,
4127 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
4129 il_wr(il, HBUS_TARG_MBX_C, HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
4131 if (!(flags & RXON_CARD_DISABLED)) {
4132 _il_wr(il, CSR_UCODE_DRV_GP1_CLR,
4133 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
4134 il_wr(il, HBUS_TARG_MBX_C,
4135 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
4139 if (flags & CT_CARD_DISABLED)
4140 il4965_perform_ct_kill_task(il);
4142 if (flags & HW_CARD_DISABLED)
4143 set_bit(S_RFKILL, &il->status);
4145 clear_bit(S_RFKILL, &il->status);
4147 if (!(flags & RXON_CARD_DISABLED))
4150 if ((test_bit(S_RFKILL, &status) !=
4151 test_bit(S_RFKILL, &il->status)))
4152 wiphy_rfkill_set_hw_state(il->hw->wiphy,
4153 test_bit(S_RFKILL, &il->status));
4155 wake_up(&il->wait_command_queue);
4159 * il4965_setup_handlers - Initialize Rx handler callbacks
4161 * Setup the RX handlers for each of the reply types sent from the uCode
4164 * This function chains into the hardware specific files for them to setup
4165 * any hardware specific handlers as well.
4168 il4965_setup_handlers(struct il_priv *il)
4170 il->handlers[N_ALIVE] = il4965_hdl_alive;
4171 il->handlers[N_ERROR] = il_hdl_error;
4172 il->handlers[N_CHANNEL_SWITCH] = il_hdl_csa;
4173 il->handlers[N_SPECTRUM_MEASUREMENT] = il_hdl_spectrum_measurement;
4174 il->handlers[N_PM_SLEEP] = il_hdl_pm_sleep;
4175 il->handlers[N_PM_DEBUG_STATS] = il_hdl_pm_debug_stats;
4176 il->handlers[N_BEACON] = il4965_hdl_beacon;
4179 * The same handler is used for both the REPLY to a discrete
4180 * stats request from the host as well as for the periodic
4181 * stats notifications (after received beacons) from the uCode.
4183 il->handlers[C_STATS] = il4965_hdl_c_stats;
4184 il->handlers[N_STATS] = il4965_hdl_stats;
4186 il_setup_rx_scan_handlers(il);
4188 /* status change handler */
4189 il->handlers[N_CARD_STATE] = il4965_hdl_card_state;
4191 il->handlers[N_MISSED_BEACONS] = il4965_hdl_missed_beacon;
4193 il->handlers[N_RX_PHY] = il4965_hdl_rx_phy;
4194 il->handlers[N_RX_MPDU] = il4965_hdl_rx;
4195 il->handlers[N_RX] = il4965_hdl_rx;
4197 il->handlers[N_COMPRESSED_BA] = il4965_hdl_compressed_ba;
4199 il->handlers[C_TX] = il4965_hdl_tx;
4203 * il4965_rx_handle - Main entry function for receiving responses from uCode
4205 * Uses the il->handlers callback function array to invoke
4206 * the appropriate handlers, including command responses,
4207 * frame-received notifications, and other notifications.
4210 il4965_rx_handle(struct il_priv *il)
4212 struct il_rx_buf *rxb;
4213 struct il_rx_pkt *pkt;
4214 struct il_rx_queue *rxq = &il->rxq;
4217 unsigned long flags;
4222 /* uCode's read idx (stored in shared DRAM) indicates the last Rx
4223 * buffer that the driver may process (last buffer filled by ucode). */
4224 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
4227 /* Rx interrupt, but nothing sent from uCode */
4229 D_RX("r = %d, i = %d\n", r, i);
4231 /* calculate total frames need to be restock after handling RX */
4232 total_empty = r - rxq->write_actual;
4233 if (total_empty < 0)
4234 total_empty += RX_QUEUE_SIZE;
4236 if (total_empty > (RX_QUEUE_SIZE / 2))
4242 rxb = rxq->queue[i];
4244 /* If an RXB doesn't have a Rx queue slot associated with it,
4245 * then a bug has been introduced in the queue refilling
4246 * routines -- catch it here */
4247 BUG_ON(rxb == NULL);
4249 rxq->queue[i] = NULL;
4251 pci_unmap_page(il->pci_dev, rxb->page_dma,
4252 PAGE_SIZE << il->hw_params.rx_page_order,
4253 PCI_DMA_FROMDEVICE);
4254 pkt = rxb_addr(rxb);
4256 len = le32_to_cpu(pkt->len_n_flags) & IL_RX_FRAME_SIZE_MSK;
4257 len += sizeof(u32); /* account for status word */
4259 /* Reclaim a command buffer only if this packet is a response
4260 * to a (driver-originated) command.
4261 * If the packet (e.g. Rx frame) originated from uCode,
4262 * there is no command buffer to reclaim.
4263 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
4264 * but apparently a few don't get set; catch them here. */
4265 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
4266 (pkt->hdr.cmd != N_RX_PHY) && (pkt->hdr.cmd != N_RX) &&
4267 (pkt->hdr.cmd != N_RX_MPDU) &&
4268 (pkt->hdr.cmd != N_COMPRESSED_BA) &&
4269 (pkt->hdr.cmd != N_STATS) && (pkt->hdr.cmd != C_TX);
4271 /* Based on type of command response or notification,
4272 * handle those that need handling via function in
4273 * handlers table. See il4965_setup_handlers() */
4274 if (il->handlers[pkt->hdr.cmd]) {
4275 D_RX("r = %d, i = %d, %s, 0x%02x\n", r, i,
4276 il_get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
4277 il->isr_stats.handlers[pkt->hdr.cmd]++;
4278 il->handlers[pkt->hdr.cmd] (il, rxb);
4280 /* No handling needed */
4281 D_RX("r %d i %d No handler needed for %s, 0x%02x\n", r,
4282 i, il_get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
4286 * XXX: After here, we should always check rxb->page
4287 * against NULL before touching it or its virtual
4288 * memory (pkt). Because some handler might have
4289 * already taken or freed the pages.
4293 /* Invoke any callbacks, transfer the buffer to caller,
4294 * and fire off the (possibly) blocking il_send_cmd()
4295 * as we reclaim the driver command queue */
4297 il_tx_cmd_complete(il, rxb);
4299 IL_WARN("Claim null rxb?\n");
4302 /* Reuse the page if possible. For notification packets and
4303 * SKBs that fail to Rx correctly, add them back into the
4304 * rx_free list for reuse later. */
4305 spin_lock_irqsave(&rxq->lock, flags);
4306 if (rxb->page != NULL) {
4308 pci_map_page(il->pci_dev, rxb->page, 0,
4309 PAGE_SIZE << il->hw_params.
4310 rx_page_order, PCI_DMA_FROMDEVICE);
4312 if (unlikely(pci_dma_mapping_error(il->pci_dev,
4314 __il_free_pages(il, rxb->page);
4316 list_add_tail(&rxb->list, &rxq->rx_used);
4318 list_add_tail(&rxb->list, &rxq->rx_free);
4322 list_add_tail(&rxb->list, &rxq->rx_used);
4324 spin_unlock_irqrestore(&rxq->lock, flags);
4326 i = (i + 1) & RX_QUEUE_MASK;
4327 /* If there are a lot of unused frames,
4328 * restock the Rx queue so ucode wont assert. */
4333 il4965_rx_replenish_now(il);
4339 /* Backtrack one entry */
4342 il4965_rx_replenish_now(il);
4344 il4965_rx_queue_restock(il);
4347 /* call this function to flush any scheduled tasklet */
4349 il4965_synchronize_irq(struct il_priv *il)
4351 /* wait to make sure we flush pending tasklet */
4352 synchronize_irq(il->pci_dev->irq);
4353 tasklet_kill(&il->irq_tasklet);
4357 il4965_irq_tasklet(struct il_priv *il)
4359 u32 inta, handled = 0;
4361 unsigned long flags;
4363 #ifdef CONFIG_IWLEGACY_DEBUG
4367 spin_lock_irqsave(&il->lock, flags);
4369 /* Ack/clear/reset pending uCode interrupts.
4370 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
4371 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
4372 inta = _il_rd(il, CSR_INT);
4373 _il_wr(il, CSR_INT, inta);
4375 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
4376 * Any new interrupts that happen after this, either while we're
4377 * in this tasklet, or later, will show up in next ISR/tasklet. */
4378 inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
4379 _il_wr(il, CSR_FH_INT_STATUS, inta_fh);
4381 #ifdef CONFIG_IWLEGACY_DEBUG
4382 if (il_get_debug_level(il) & IL_DL_ISR) {
4383 /* just for debug */
4384 inta_mask = _il_rd(il, CSR_INT_MASK);
4385 D_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", inta,
4386 inta_mask, inta_fh);
4390 spin_unlock_irqrestore(&il->lock, flags);
4392 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
4393 * atomic, make sure that inta covers all the interrupts that
4394 * we've discovered, even if FH interrupt came in just after
4395 * reading CSR_INT. */
4396 if (inta_fh & CSR49_FH_INT_RX_MASK)
4397 inta |= CSR_INT_BIT_FH_RX;
4398 if (inta_fh & CSR49_FH_INT_TX_MASK)
4399 inta |= CSR_INT_BIT_FH_TX;
4401 /* Now service all interrupt bits discovered above. */
4402 if (inta & CSR_INT_BIT_HW_ERR) {
4403 IL_ERR("Hardware error detected. Restarting.\n");
4405 /* Tell the device to stop sending interrupts */
4406 il_disable_interrupts(il);
4409 il_irq_handle_error(il);
4411 handled |= CSR_INT_BIT_HW_ERR;
4415 #ifdef CONFIG_IWLEGACY_DEBUG
4416 if (il_get_debug_level(il) & (IL_DL_ISR)) {
4417 /* NIC fires this, but we don't use it, redundant with WAKEUP */
4418 if (inta & CSR_INT_BIT_SCD) {
4419 D_ISR("Scheduler finished to transmit "
4420 "the frame/frames.\n");
4421 il->isr_stats.sch++;
4424 /* Alive notification via Rx interrupt will do the real work */
4425 if (inta & CSR_INT_BIT_ALIVE) {
4426 D_ISR("Alive interrupt\n");
4427 il->isr_stats.alive++;
4431 /* Safely ignore these bits for debug checks below */
4432 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
4434 /* HW RF KILL switch toggled */
4435 if (inta & CSR_INT_BIT_RF_KILL) {
4438 if (!(_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
4441 IL_WARN("RF_KILL bit toggled to %s.\n",
4442 hw_rf_kill ? "disable radio" : "enable radio");
4444 il->isr_stats.rfkill++;
4446 /* driver only loads ucode once setting the interface up.
4447 * the driver allows loading the ucode even if the radio
4448 * is killed. Hence update the killswitch state here. The
4449 * rfkill handler will care about restarting if needed.
4452 set_bit(S_RFKILL, &il->status);
4454 clear_bit(S_RFKILL, &il->status);
4455 il_force_reset(il, true);
4457 wiphy_rfkill_set_hw_state(il->hw->wiphy, hw_rf_kill);
4459 handled |= CSR_INT_BIT_RF_KILL;
4462 /* Chip got too hot and stopped itself */
4463 if (inta & CSR_INT_BIT_CT_KILL) {
4464 IL_ERR("Microcode CT kill error detected.\n");
4465 il->isr_stats.ctkill++;
4466 handled |= CSR_INT_BIT_CT_KILL;
4469 /* Error detected by uCode */
4470 if (inta & CSR_INT_BIT_SW_ERR) {
4471 IL_ERR("Microcode SW error detected. " " Restarting 0x%X.\n",
4474 il_irq_handle_error(il);
4475 handled |= CSR_INT_BIT_SW_ERR;
4479 * uCode wakes up after power-down sleep.
4480 * Tell device about any new tx or host commands enqueued,
4481 * and about any Rx buffers made available while asleep.
4483 if (inta & CSR_INT_BIT_WAKEUP) {
4484 D_ISR("Wakeup interrupt\n");
4485 il_rx_queue_update_write_ptr(il, &il->rxq);
4486 for (i = 0; i < il->hw_params.max_txq_num; i++)
4487 il_txq_update_write_ptr(il, &il->txq[i]);
4488 il->isr_stats.wakeup++;
4489 handled |= CSR_INT_BIT_WAKEUP;
4492 /* All uCode command responses, including Tx command responses,
4493 * Rx "responses" (frame-received notification), and other
4494 * notifications from uCode come through here*/
4495 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
4496 il4965_rx_handle(il);
4498 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
4501 /* This "Tx" DMA channel is used only for loading uCode */
4502 if (inta & CSR_INT_BIT_FH_TX) {
4503 D_ISR("uCode load interrupt\n");
4505 handled |= CSR_INT_BIT_FH_TX;
4506 /* Wake up uCode load routine, now that load is complete */
4507 il->ucode_write_complete = 1;
4508 wake_up(&il->wait_command_queue);
4511 if (inta & ~handled) {
4512 IL_ERR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
4513 il->isr_stats.unhandled++;
4516 if (inta & ~(il->inta_mask)) {
4517 IL_WARN("Disabled INTA bits 0x%08x were pending\n",
4518 inta & ~il->inta_mask);
4519 IL_WARN(" with FH49_INT = 0x%08x\n", inta_fh);
4522 /* Re-enable all interrupts */
4523 /* only Re-enable if disabled by irq */
4524 if (test_bit(S_INT_ENABLED, &il->status))
4525 il_enable_interrupts(il);
4526 /* Re-enable RF_KILL if it occurred */
4527 else if (handled & CSR_INT_BIT_RF_KILL)
4528 il_enable_rfkill_int(il);
4530 #ifdef CONFIG_IWLEGACY_DEBUG
4531 if (il_get_debug_level(il) & (IL_DL_ISR)) {
4532 inta = _il_rd(il, CSR_INT);
4533 inta_mask = _il_rd(il, CSR_INT_MASK);
4534 inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
4535 D_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
4536 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
4541 /*****************************************************************************
4545 *****************************************************************************/
4547 #ifdef CONFIG_IWLEGACY_DEBUG
4550 * The following adds a new attribute to the sysfs representation
4551 * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
4552 * used for controlling the debug level.
4554 * See the level definitions in iwl for details.
4556 * The debug_level being managed using sysfs below is a per device debug
4557 * level that is used instead of the global debug level if it (the per
4558 * device debug level) is set.
4561 il4965_show_debug_level(struct device *d, struct device_attribute *attr,
4564 struct il_priv *il = dev_get_drvdata(d);
4565 return sprintf(buf, "0x%08X\n", il_get_debug_level(il));
4569 il4965_store_debug_level(struct device *d, struct device_attribute *attr,
4570 const char *buf, size_t count)
4572 struct il_priv *il = dev_get_drvdata(d);
4576 ret = strict_strtoul(buf, 0, &val);
4578 IL_ERR("%s is not in hex or decimal form.\n", buf);
4580 il->debug_level = val;
4582 return strnlen(buf, count);
4585 static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO, il4965_show_debug_level,
4586 il4965_store_debug_level);
4588 #endif /* CONFIG_IWLEGACY_DEBUG */
4591 il4965_show_temperature(struct device *d, struct device_attribute *attr,
4594 struct il_priv *il = dev_get_drvdata(d);
4596 if (!il_is_alive(il))
4599 return sprintf(buf, "%d\n", il->temperature);
4602 static DEVICE_ATTR(temperature, S_IRUGO, il4965_show_temperature, NULL);
4605 il4965_show_tx_power(struct device *d, struct device_attribute *attr, char *buf)
4607 struct il_priv *il = dev_get_drvdata(d);
4609 if (!il_is_ready_rf(il))
4610 return sprintf(buf, "off\n");
4612 return sprintf(buf, "%d\n", il->tx_power_user_lmt);
4616 il4965_store_tx_power(struct device *d, struct device_attribute *attr,
4617 const char *buf, size_t count)
4619 struct il_priv *il = dev_get_drvdata(d);
4623 ret = strict_strtoul(buf, 10, &val);
4625 IL_INFO("%s is not in decimal form.\n", buf);
4627 ret = il_set_tx_power(il, val, false);
4629 IL_ERR("failed setting tx power (0x%d).\n", ret);
4636 static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, il4965_show_tx_power,
4637 il4965_store_tx_power);
4639 static struct attribute *il_sysfs_entries[] = {
4640 &dev_attr_temperature.attr,
4641 &dev_attr_tx_power.attr,
4642 #ifdef CONFIG_IWLEGACY_DEBUG
4643 &dev_attr_debug_level.attr,
4648 static struct attribute_group il_attribute_group = {
4649 .name = NULL, /* put in device directory */
4650 .attrs = il_sysfs_entries,
4653 /******************************************************************************
4655 * uCode download functions
4657 ******************************************************************************/
4660 il4965_dealloc_ucode_pci(struct il_priv *il)
4662 il_free_fw_desc(il->pci_dev, &il->ucode_code);
4663 il_free_fw_desc(il->pci_dev, &il->ucode_data);
4664 il_free_fw_desc(il->pci_dev, &il->ucode_data_backup);
4665 il_free_fw_desc(il->pci_dev, &il->ucode_init);
4666 il_free_fw_desc(il->pci_dev, &il->ucode_init_data);
4667 il_free_fw_desc(il->pci_dev, &il->ucode_boot);
4671 il4965_nic_start(struct il_priv *il)
4673 /* Remove all resets to allow NIC to operate */
4674 _il_wr(il, CSR_RESET, 0);
4677 static void il4965_ucode_callback(const struct firmware *ucode_raw,
4679 static int il4965_mac_setup_register(struct il_priv *il, u32 max_probe_length);
4681 static int __must_check
4682 il4965_request_firmware(struct il_priv *il, bool first)
4684 const char *name_pre = il->cfg->fw_name_pre;
4688 il->fw_idx = il->cfg->ucode_api_max;
4689 sprintf(tag, "%d", il->fw_idx);
4692 sprintf(tag, "%d", il->fw_idx);
4695 if (il->fw_idx < il->cfg->ucode_api_min) {
4696 IL_ERR("no suitable firmware found!\n");
4700 sprintf(il->firmware_name, "%s%s%s", name_pre, tag, ".ucode");
4702 D_INFO("attempting to load firmware '%s'\n", il->firmware_name);
4704 return request_firmware_nowait(THIS_MODULE, 1, il->firmware_name,
4705 &il->pci_dev->dev, GFP_KERNEL, il,
4706 il4965_ucode_callback);
4709 struct il4965_firmware_pieces {
4710 const void *inst, *data, *init, *init_data, *boot;
4711 size_t inst_size, data_size, init_size, init_data_size, boot_size;
4715 il4965_load_firmware(struct il_priv *il, const struct firmware *ucode_raw,
4716 struct il4965_firmware_pieces *pieces)
4718 struct il_ucode_header *ucode = (void *)ucode_raw->data;
4719 u32 api_ver, hdr_size;
4722 il->ucode_ver = le32_to_cpu(ucode->ver);
4723 api_ver = IL_UCODE_API(il->ucode_ver);
4731 if (ucode_raw->size < hdr_size) {
4732 IL_ERR("File size too small!\n");
4735 pieces->inst_size = le32_to_cpu(ucode->v1.inst_size);
4736 pieces->data_size = le32_to_cpu(ucode->v1.data_size);
4737 pieces->init_size = le32_to_cpu(ucode->v1.init_size);
4738 pieces->init_data_size = le32_to_cpu(ucode->v1.init_data_size);
4739 pieces->boot_size = le32_to_cpu(ucode->v1.boot_size);
4740 src = ucode->v1.data;
4744 /* Verify size of file vs. image size info in file's header */
4745 if (ucode_raw->size !=
4746 hdr_size + pieces->inst_size + pieces->data_size +
4747 pieces->init_size + pieces->init_data_size + pieces->boot_size) {
4749 IL_ERR("uCode file size %d does not match expected size\n",
4750 (int)ucode_raw->size);
4755 src += pieces->inst_size;
4757 src += pieces->data_size;
4759 src += pieces->init_size;
4760 pieces->init_data = src;
4761 src += pieces->init_data_size;
4763 src += pieces->boot_size;
4769 * il4965_ucode_callback - callback when firmware was loaded
4771 * If loaded successfully, copies the firmware into buffers
4772 * for the card to fetch (via DMA).
4775 il4965_ucode_callback(const struct firmware *ucode_raw, void *context)
4777 struct il_priv *il = context;
4778 struct il_ucode_header *ucode;
4780 struct il4965_firmware_pieces pieces;
4781 const unsigned int api_max = il->cfg->ucode_api_max;
4782 const unsigned int api_min = il->cfg->ucode_api_min;
4785 u32 max_probe_length = 200;
4786 u32 standard_phy_calibration_size =
4787 IL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE;
4789 memset(&pieces, 0, sizeof(pieces));
4792 if (il->fw_idx <= il->cfg->ucode_api_max)
4793 IL_ERR("request for firmware file '%s' failed.\n",
4798 D_INFO("Loaded firmware file '%s' (%zd bytes).\n", il->firmware_name,
4801 /* Make sure that we got at least the API version number */
4802 if (ucode_raw->size < 4) {
4803 IL_ERR("File size way too small!\n");
4807 /* Data from ucode file: header followed by uCode images */
4808 ucode = (struct il_ucode_header *)ucode_raw->data;
4810 err = il4965_load_firmware(il, ucode_raw, &pieces);
4815 api_ver = IL_UCODE_API(il->ucode_ver);
4818 * api_ver should match the api version forming part of the
4819 * firmware filename ... but we don't check for that and only rely
4820 * on the API version read from firmware header from here on forward
4822 if (api_ver < api_min || api_ver > api_max) {
4823 IL_ERR("Driver unable to support your firmware API. "
4824 "Driver supports v%u, firmware is v%u.\n", api_max,
4829 if (api_ver != api_max)
4830 IL_ERR("Firmware has old API version. Expected v%u, "
4831 "got v%u. New firmware can be obtained "
4832 "from http://www.intellinuxwireless.org.\n", api_max,
4835 IL_INFO("loaded firmware version %u.%u.%u.%u\n",
4836 IL_UCODE_MAJOR(il->ucode_ver), IL_UCODE_MINOR(il->ucode_ver),
4837 IL_UCODE_API(il->ucode_ver), IL_UCODE_SERIAL(il->ucode_ver));
4839 snprintf(il->hw->wiphy->fw_version, sizeof(il->hw->wiphy->fw_version),
4840 "%u.%u.%u.%u", IL_UCODE_MAJOR(il->ucode_ver),
4841 IL_UCODE_MINOR(il->ucode_ver), IL_UCODE_API(il->ucode_ver),
4842 IL_UCODE_SERIAL(il->ucode_ver));
4845 * For any of the failures below (before allocating pci memory)
4846 * we will try to load a version with a smaller API -- maybe the
4847 * user just got a corrupted version of the latest API.
4850 D_INFO("f/w package hdr ucode version raw = 0x%x\n", il->ucode_ver);
4851 D_INFO("f/w package hdr runtime inst size = %Zd\n", pieces.inst_size);
4852 D_INFO("f/w package hdr runtime data size = %Zd\n", pieces.data_size);
4853 D_INFO("f/w package hdr init inst size = %Zd\n", pieces.init_size);
4854 D_INFO("f/w package hdr init data size = %Zd\n", pieces.init_data_size);
4855 D_INFO("f/w package hdr boot inst size = %Zd\n", pieces.boot_size);
4857 /* Verify that uCode images will fit in card's SRAM */
4858 if (pieces.inst_size > il->hw_params.max_inst_size) {
4859 IL_ERR("uCode instr len %Zd too large to fit in\n",
4864 if (pieces.data_size > il->hw_params.max_data_size) {
4865 IL_ERR("uCode data len %Zd too large to fit in\n",
4870 if (pieces.init_size > il->hw_params.max_inst_size) {
4871 IL_ERR("uCode init instr len %Zd too large to fit in\n",
4876 if (pieces.init_data_size > il->hw_params.max_data_size) {
4877 IL_ERR("uCode init data len %Zd too large to fit in\n",
4878 pieces.init_data_size);
4882 if (pieces.boot_size > il->hw_params.max_bsm_size) {
4883 IL_ERR("uCode boot instr len %Zd too large to fit in\n",
4888 /* Allocate ucode buffers for card's bus-master loading ... */
4890 /* Runtime instructions and 2 copies of data:
4891 * 1) unmodified from disk
4892 * 2) backup cache for save/restore during power-downs */
4893 il->ucode_code.len = pieces.inst_size;
4894 il_alloc_fw_desc(il->pci_dev, &il->ucode_code);
4896 il->ucode_data.len = pieces.data_size;
4897 il_alloc_fw_desc(il->pci_dev, &il->ucode_data);
4899 il->ucode_data_backup.len = pieces.data_size;
4900 il_alloc_fw_desc(il->pci_dev, &il->ucode_data_backup);
4902 if (!il->ucode_code.v_addr || !il->ucode_data.v_addr ||
4903 !il->ucode_data_backup.v_addr)
4906 /* Initialization instructions and data */
4907 if (pieces.init_size && pieces.init_data_size) {
4908 il->ucode_init.len = pieces.init_size;
4909 il_alloc_fw_desc(il->pci_dev, &il->ucode_init);
4911 il->ucode_init_data.len = pieces.init_data_size;
4912 il_alloc_fw_desc(il->pci_dev, &il->ucode_init_data);
4914 if (!il->ucode_init.v_addr || !il->ucode_init_data.v_addr)
4918 /* Bootstrap (instructions only, no data) */
4919 if (pieces.boot_size) {
4920 il->ucode_boot.len = pieces.boot_size;
4921 il_alloc_fw_desc(il->pci_dev, &il->ucode_boot);
4923 if (!il->ucode_boot.v_addr)
4927 /* Now that we can no longer fail, copy information */
4929 il->sta_key_max_num = STA_KEY_MAX_NUM;
4931 /* Copy images into buffers for card's bus-master reads ... */
4933 /* Runtime instructions (first block of data in file) */
4934 D_INFO("Copying (but not loading) uCode instr len %Zd\n",
4936 memcpy(il->ucode_code.v_addr, pieces.inst, pieces.inst_size);
4938 D_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
4939 il->ucode_code.v_addr, (u32) il->ucode_code.p_addr);
4943 * NOTE: Copy into backup buffer will be done in il_up()
4945 D_INFO("Copying (but not loading) uCode data len %Zd\n",
4947 memcpy(il->ucode_data.v_addr, pieces.data, pieces.data_size);
4948 memcpy(il->ucode_data_backup.v_addr, pieces.data, pieces.data_size);
4950 /* Initialization instructions */
4951 if (pieces.init_size) {
4952 D_INFO("Copying (but not loading) init instr len %Zd\n",
4954 memcpy(il->ucode_init.v_addr, pieces.init, pieces.init_size);
4957 /* Initialization data */
4958 if (pieces.init_data_size) {
4959 D_INFO("Copying (but not loading) init data len %Zd\n",
4960 pieces.init_data_size);
4961 memcpy(il->ucode_init_data.v_addr, pieces.init_data,
4962 pieces.init_data_size);
4965 /* Bootstrap instructions */
4966 D_INFO("Copying (but not loading) boot instr len %Zd\n",
4968 memcpy(il->ucode_boot.v_addr, pieces.boot, pieces.boot_size);
4971 * figure out the offset of chain noise reset and gain commands
4972 * base on the size of standard phy calibration commands table size
4974 il->_4965.phy_calib_chain_noise_reset_cmd =
4975 standard_phy_calibration_size;
4976 il->_4965.phy_calib_chain_noise_gain_cmd =
4977 standard_phy_calibration_size + 1;
4979 /**************************************************
4980 * This is still part of probe() in a sense...
4982 * 9. Setup and register with mac80211 and debugfs
4983 **************************************************/
4984 err = il4965_mac_setup_register(il, max_probe_length);
4988 err = il_dbgfs_register(il, DRV_NAME);
4990 IL_ERR("failed to create debugfs files. Ignoring error: %d\n",
4993 err = sysfs_create_group(&il->pci_dev->dev.kobj, &il_attribute_group);
4995 IL_ERR("failed to create sysfs device attributes\n");
4999 /* We have our copies now, allow OS release its copies */
5000 release_firmware(ucode_raw);
5001 complete(&il->_4965.firmware_loading_complete);
5005 /* try next, if any */
5006 if (il4965_request_firmware(il, false))
5008 release_firmware(ucode_raw);
5012 IL_ERR("failed to allocate pci memory\n");
5013 il4965_dealloc_ucode_pci(il);
5015 complete(&il->_4965.firmware_loading_complete);
5016 device_release_driver(&il->pci_dev->dev);
5017 release_firmware(ucode_raw);
5020 static const char *const desc_lookup_text[] = {
5025 "NMI_INTERRUPT_WDG",
5029 "HW_ERROR_TUNE_LOCK",
5030 "HW_ERROR_TEMPERATURE",
5031 "ILLEGAL_CHAN_FREQ",
5034 "NMI_INTERRUPT_HOST",
5035 "NMI_INTERRUPT_ACTION_PT",
5036 "NMI_INTERRUPT_UNKNOWN",
5037 "UCODE_VERSION_MISMATCH",
5038 "HW_ERROR_ABS_LOCK",
5039 "HW_ERROR_CAL_LOCK_FAIL",
5040 "NMI_INTERRUPT_INST_ACTION_PT",
5041 "NMI_INTERRUPT_DATA_ACTION_PT",
5043 "NMI_INTERRUPT_TRM",
5044 "NMI_INTERRUPT_BREAK_POINT",
5054 } advanced_lookup[] = {
5056 "NMI_INTERRUPT_WDG", 0x34}, {
5057 "SYSASSERT", 0x35}, {
5058 "UCODE_VERSION_MISMATCH", 0x37}, {
5059 "BAD_COMMAND", 0x38}, {
5060 "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C}, {
5061 "FATAL_ERROR", 0x3D}, {
5062 "NMI_TRM_HW_ERR", 0x46}, {
5063 "NMI_INTERRUPT_TRM", 0x4C}, {
5064 "NMI_INTERRUPT_BREAK_POINT", 0x54}, {
5065 "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C}, {
5066 "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64}, {
5067 "NMI_INTERRUPT_HOST", 0x66}, {
5068 "NMI_INTERRUPT_ACTION_PT", 0x7C}, {
5069 "NMI_INTERRUPT_UNKNOWN", 0x84}, {
5070 "NMI_INTERRUPT_INST_ACTION_PT", 0x86}, {
5071 "ADVANCED_SYSASSERT", 0},};
5074 il4965_desc_lookup(u32 num)
5077 int max = ARRAY_SIZE(desc_lookup_text);
5080 return desc_lookup_text[num];
5082 max = ARRAY_SIZE(advanced_lookup) - 1;
5083 for (i = 0; i < max; i++) {
5084 if (advanced_lookup[i].num == num)
5087 return advanced_lookup[i].name;
5090 #define ERROR_START_OFFSET (1 * sizeof(u32))
5091 #define ERROR_ELEM_SIZE (7 * sizeof(u32))
5094 il4965_dump_nic_error_log(struct il_priv *il)
5097 u32 desc, time, count, base, data1;
5098 u32 blink1, blink2, ilink1, ilink2;
5101 if (il->ucode_type == UCODE_INIT)
5102 base = le32_to_cpu(il->card_alive_init.error_event_table_ptr);
5104 base = le32_to_cpu(il->card_alive.error_event_table_ptr);
5106 if (!il->ops->is_valid_rtc_data_addr(base)) {
5107 IL_ERR("Not valid error log pointer 0x%08X for %s uCode\n",
5108 base, (il->ucode_type == UCODE_INIT) ? "Init" : "RT");
5112 count = il_read_targ_mem(il, base);
5114 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
5115 IL_ERR("Start IWL Error Log Dump:\n");
5116 IL_ERR("Status: 0x%08lX, count: %d\n", il->status, count);
5119 desc = il_read_targ_mem(il, base + 1 * sizeof(u32));
5120 il->isr_stats.err_code = desc;
5121 pc = il_read_targ_mem(il, base + 2 * sizeof(u32));
5122 blink1 = il_read_targ_mem(il, base + 3 * sizeof(u32));
5123 blink2 = il_read_targ_mem(il, base + 4 * sizeof(u32));
5124 ilink1 = il_read_targ_mem(il, base + 5 * sizeof(u32));
5125 ilink2 = il_read_targ_mem(il, base + 6 * sizeof(u32));
5126 data1 = il_read_targ_mem(il, base + 7 * sizeof(u32));
5127 data2 = il_read_targ_mem(il, base + 8 * sizeof(u32));
5128 line = il_read_targ_mem(il, base + 9 * sizeof(u32));
5129 time = il_read_targ_mem(il, base + 11 * sizeof(u32));
5130 hcmd = il_read_targ_mem(il, base + 22 * sizeof(u32));
5133 "data1 data2 line\n");
5134 IL_ERR("%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n",
5135 il4965_desc_lookup(desc), desc, time, data1, data2, line);
5136 IL_ERR("pc blink1 blink2 ilink1 ilink2 hcmd\n");
5137 IL_ERR("0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n", pc, blink1,
5138 blink2, ilink1, ilink2, hcmd);
5142 il4965_rf_kill_ct_config(struct il_priv *il)
5144 struct il_ct_kill_config cmd;
5145 unsigned long flags;
5148 spin_lock_irqsave(&il->lock, flags);
5149 _il_wr(il, CSR_UCODE_DRV_GP1_CLR,
5150 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
5151 spin_unlock_irqrestore(&il->lock, flags);
5153 cmd.critical_temperature_R =
5154 cpu_to_le32(il->hw_params.ct_kill_threshold);
5156 ret = il_send_cmd_pdu(il, C_CT_KILL_CONFIG, sizeof(cmd), &cmd);
5158 IL_ERR("C_CT_KILL_CONFIG failed\n");
5160 D_INFO("C_CT_KILL_CONFIG " "succeeded, "
5161 "critical temperature is %d\n",
5162 il->hw_params.ct_kill_threshold);
5165 static const s8 default_queue_to_tx_fifo[] = {
5175 #define IL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo))))
5178 il4965_alive_notify(struct il_priv *il)
5181 unsigned long flags;
5185 spin_lock_irqsave(&il->lock, flags);
5187 /* Clear 4965's internal Tx Scheduler data base */
5188 il->scd_base_addr = il_rd_prph(il, IL49_SCD_SRAM_BASE_ADDR);
5189 a = il->scd_base_addr + IL49_SCD_CONTEXT_DATA_OFFSET;
5190 for (; a < il->scd_base_addr + IL49_SCD_TX_STTS_BITMAP_OFFSET; a += 4)
5191 il_write_targ_mem(il, a, 0);
5192 for (; a < il->scd_base_addr + IL49_SCD_TRANSLATE_TBL_OFFSET; a += 4)
5193 il_write_targ_mem(il, a, 0);
5197 IL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(il->hw_params.max_txq_num);
5199 il_write_targ_mem(il, a, 0);
5201 /* Tel 4965 where to find Tx byte count tables */
5202 il_wr_prph(il, IL49_SCD_DRAM_BASE_ADDR, il->scd_bc_tbls.dma >> 10);
5204 /* Enable DMA channel */
5205 for (chan = 0; chan < FH49_TCSR_CHNL_NUM; chan++)
5206 il_wr(il, FH49_TCSR_CHNL_TX_CONFIG_REG(chan),
5207 FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
5208 FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
5210 /* Update FH chicken bits */
5211 reg_val = il_rd(il, FH49_TX_CHICKEN_BITS_REG);
5212 il_wr(il, FH49_TX_CHICKEN_BITS_REG,
5213 reg_val | FH49_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
5215 /* Disable chain mode for all queues */
5216 il_wr_prph(il, IL49_SCD_QUEUECHAIN_SEL, 0);
5218 /* Initialize each Tx queue (including the command queue) */
5219 for (i = 0; i < il->hw_params.max_txq_num; i++) {
5221 /* TFD circular buffer read/write idxes */
5222 il_wr_prph(il, IL49_SCD_QUEUE_RDPTR(i), 0);
5223 il_wr(il, HBUS_TARG_WRPTR, 0 | (i << 8));
5225 /* Max Tx Window size for Scheduler-ACK mode */
5226 il_write_targ_mem(il,
5228 IL49_SCD_CONTEXT_QUEUE_OFFSET(i),
5230 IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
5231 IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
5234 il_write_targ_mem(il,
5236 IL49_SCD_CONTEXT_QUEUE_OFFSET(i) +
5239 IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
5240 IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
5243 il_wr_prph(il, IL49_SCD_INTERRUPT_MASK,
5244 (1 << il->hw_params.max_txq_num) - 1);
5246 /* Activate all Tx DMA/FIFO channels */
5247 il4965_txq_set_sched(il, IL_MASK(0, 6));
5249 il4965_set_wr_ptrs(il, IL_DEFAULT_CMD_QUEUE_NUM, 0);
5251 /* make sure all queue are not stopped */
5252 memset(&il->queue_stopped[0], 0, sizeof(il->queue_stopped));
5253 for (i = 0; i < 4; i++)
5254 atomic_set(&il->queue_stop_count[i], 0);
5256 /* reset to 0 to enable all the queue first */
5257 il->txq_ctx_active_msk = 0;
5258 /* Map each Tx/cmd queue to its corresponding fifo */
5259 BUILD_BUG_ON(ARRAY_SIZE(default_queue_to_tx_fifo) != 7);
5261 for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) {
5262 int ac = default_queue_to_tx_fifo[i];
5264 il_txq_ctx_activate(il, i);
5266 if (ac == IL_TX_FIFO_UNUSED)
5269 il4965_tx_queue_set_status(il, &il->txq[i], ac, 0);
5272 spin_unlock_irqrestore(&il->lock, flags);
5278 * il4965_alive_start - called after N_ALIVE notification received
5279 * from protocol/runtime uCode (initialization uCode's
5280 * Alive gets handled by il_init_alive_start()).
5283 il4965_alive_start(struct il_priv *il)
5287 D_INFO("Runtime Alive received.\n");
5289 if (il->card_alive.is_valid != UCODE_VALID_OK) {
5290 /* We had an error bringing up the hardware, so take it
5291 * all the way back down so we can try again */
5292 D_INFO("Alive failed.\n");
5296 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
5297 * This is a paranoid check, because we would not have gotten the
5298 * "runtime" alive if code weren't properly loaded. */
5299 if (il4965_verify_ucode(il)) {
5300 /* Runtime instruction load was bad;
5301 * take it all the way back down so we can try again */
5302 D_INFO("Bad runtime uCode load.\n");
5306 ret = il4965_alive_notify(il);
5308 IL_WARN("Could not complete ALIVE transition [ntf]: %d\n", ret);
5312 /* After the ALIVE response, we can send host commands to the uCode */
5313 set_bit(S_ALIVE, &il->status);
5315 /* Enable watchdog to monitor the driver tx queues */
5316 il_setup_watchdog(il);
5318 if (il_is_rfkill(il))
5321 ieee80211_wake_queues(il->hw);
5323 il->active_rate = RATES_MASK;
5325 il_power_update_mode(il, true);
5326 D_INFO("Updated power mode\n");
5328 if (il_is_associated(il)) {
5329 struct il_rxon_cmd *active_rxon =
5330 (struct il_rxon_cmd *)&il->active;
5331 /* apply any changes in staging */
5332 il->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
5333 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
5335 /* Initialize our rx_config data */
5336 il_connection_init_rx_config(il);
5338 if (il->ops->set_rxon_chain)
5339 il->ops->set_rxon_chain(il);
5342 /* Configure bluetooth coexistence if enabled */
5343 il_send_bt_config(il);
5345 il4965_reset_run_time_calib(il);
5347 set_bit(S_READY, &il->status);
5349 /* Configure the adapter for unassociated operation */
5352 /* At this point, the NIC is initialized and operational */
5353 il4965_rf_kill_ct_config(il);
5355 D_INFO("ALIVE processing complete.\n");
5356 wake_up(&il->wait_command_queue);
5361 queue_work(il->workqueue, &il->restart);
5364 static void il4965_cancel_deferred_work(struct il_priv *il);
5367 __il4965_down(struct il_priv *il)
5369 unsigned long flags;
5372 D_INFO(DRV_NAME " is going down\n");
5374 il_scan_cancel_timeout(il, 200);
5376 exit_pending = test_and_set_bit(S_EXIT_PENDING, &il->status);
5378 /* Stop TX queues watchdog. We need to have S_EXIT_PENDING bit set
5379 * to prevent rearm timer */
5380 del_timer_sync(&il->watchdog);
5382 il_clear_ucode_stations(il);
5384 /* FIXME: race conditions ? */
5385 spin_lock_irq(&il->sta_lock);
5387 * Remove all key information that is not stored as part
5388 * of station information since mac80211 may not have had
5389 * a chance to remove all the keys. When device is
5390 * reconfigured by mac80211 after an error all keys will
5393 memset(il->_4965.wep_keys, 0, sizeof(il->_4965.wep_keys));
5394 il->_4965.key_mapping_keys = 0;
5395 spin_unlock_irq(&il->sta_lock);
5397 il_dealloc_bcast_stations(il);
5398 il_clear_driver_stations(il);
5400 /* Unblock any waiting calls */
5401 wake_up_all(&il->wait_command_queue);
5403 /* Wipe out the EXIT_PENDING status bit if we are not actually
5404 * exiting the module */
5406 clear_bit(S_EXIT_PENDING, &il->status);
5408 /* stop and reset the on-board processor */
5409 _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
5411 /* tell the device to stop sending interrupts */
5412 spin_lock_irqsave(&il->lock, flags);
5413 il_disable_interrupts(il);
5414 spin_unlock_irqrestore(&il->lock, flags);
5415 il4965_synchronize_irq(il);
5417 if (il->mac80211_registered)
5418 ieee80211_stop_queues(il->hw);
5420 /* If we have not previously called il_init() then
5421 * clear all bits but the RF Kill bit and return */
5422 if (!il_is_init(il)) {
5424 test_bit(S_RFKILL, &il->status) << S_RFKILL |
5425 test_bit(S_GEO_CONFIGURED, &il->status) << S_GEO_CONFIGURED |
5426 test_bit(S_EXIT_PENDING, &il->status) << S_EXIT_PENDING;
5430 /* ...otherwise clear out all the status bits but the RF Kill
5431 * bit and continue taking the NIC down. */
5433 test_bit(S_RFKILL, &il->status) << S_RFKILL |
5434 test_bit(S_GEO_CONFIGURED, &il->status) << S_GEO_CONFIGURED |
5435 test_bit(S_FW_ERROR, &il->status) << S_FW_ERROR |
5436 test_bit(S_EXIT_PENDING, &il->status) << S_EXIT_PENDING;
5439 * We disabled and synchronized interrupt, and priv->mutex is taken, so
5440 * here is the only thread which will program device registers, but
5441 * still have lockdep assertions, so we are taking reg_lock.
5443 spin_lock_irq(&il->reg_lock);
5444 /* FIXME: il_grab_nic_access if rfkill is off ? */
5446 il4965_txq_ctx_stop(il);
5447 il4965_rxq_stop(il);
5448 /* Power-down device's busmaster DMA clocks */
5449 _il_wr_prph(il, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
5451 /* Make sure (redundant) we've released our request to stay awake */
5452 _il_clear_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
5453 /* Stop the device, and put it in low power state */
5456 spin_unlock_irq(&il->reg_lock);
5458 il4965_txq_ctx_unmap(il);
5460 memset(&il->card_alive, 0, sizeof(struct il_alive_resp));
5462 dev_kfree_skb(il->beacon_skb);
5463 il->beacon_skb = NULL;
5465 /* clear out any free frames */
5466 il4965_clear_free_frames(il);
5470 il4965_down(struct il_priv *il)
5472 mutex_lock(&il->mutex);
5474 mutex_unlock(&il->mutex);
5476 il4965_cancel_deferred_work(il);
5481 il4965_set_hw_ready(struct il_priv *il)
5485 il_set_bit(il, CSR_HW_IF_CONFIG_REG,
5486 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
5488 /* See if we got it */
5489 ret = _il_poll_bit(il, CSR_HW_IF_CONFIG_REG,
5490 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
5491 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
5494 il->hw_ready = true;
5496 D_INFO("hardware %s ready\n", (il->hw_ready) ? "" : "not");
5500 il4965_prepare_card_hw(struct il_priv *il)
5504 il->hw_ready = false;
5506 il4965_set_hw_ready(il);
5510 /* If HW is not ready, prepare the conditions to check again */
5511 il_set_bit(il, CSR_HW_IF_CONFIG_REG, CSR_HW_IF_CONFIG_REG_PREPARE);
5514 _il_poll_bit(il, CSR_HW_IF_CONFIG_REG,
5515 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
5516 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
5518 /* HW should be ready by now, check again. */
5519 if (ret != -ETIMEDOUT)
5520 il4965_set_hw_ready(il);
5523 #define MAX_HW_RESTARTS 5
5526 __il4965_up(struct il_priv *il)
5531 if (test_bit(S_EXIT_PENDING, &il->status)) {
5532 IL_WARN("Exit pending; will not bring the NIC up\n");
5536 if (!il->ucode_data_backup.v_addr || !il->ucode_data.v_addr) {
5537 IL_ERR("ucode not available for device bringup\n");
5541 ret = il4965_alloc_bcast_station(il);
5543 il_dealloc_bcast_stations(il);
5547 il4965_prepare_card_hw(il);
5548 if (!il->hw_ready) {
5549 IL_ERR("HW not ready\n");
5553 /* If platform's RF_KILL switch is NOT set to KILL */
5554 if (_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
5555 clear_bit(S_RFKILL, &il->status);
5557 set_bit(S_RFKILL, &il->status);
5558 wiphy_rfkill_set_hw_state(il->hw->wiphy, true);
5560 il_enable_rfkill_int(il);
5561 IL_WARN("Radio disabled by HW RF Kill switch\n");
5565 _il_wr(il, CSR_INT, 0xFFFFFFFF);
5567 /* must be initialised before il_hw_nic_init */
5568 il->cmd_queue = IL_DEFAULT_CMD_QUEUE_NUM;
5570 ret = il4965_hw_nic_init(il);
5572 IL_ERR("Unable to init nic\n");
5576 /* make sure rfkill handshake bits are cleared */
5577 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
5578 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
5580 /* clear (again), then enable host interrupts */
5581 _il_wr(il, CSR_INT, 0xFFFFFFFF);
5582 il_enable_interrupts(il);
5584 /* really make sure rfkill handshake bits are cleared */
5585 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
5586 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
5588 /* Copy original ucode data image from disk into backup cache.
5589 * This will be used to initialize the on-board processor's
5590 * data SRAM for a clean start when the runtime program first loads. */
5591 memcpy(il->ucode_data_backup.v_addr, il->ucode_data.v_addr,
5592 il->ucode_data.len);
5594 for (i = 0; i < MAX_HW_RESTARTS; i++) {
5596 /* load bootstrap state machine,
5597 * load bootstrap program into processor's memory,
5598 * prepare to load the "initialize" uCode */
5599 ret = il->ops->load_ucode(il);
5602 IL_ERR("Unable to set up bootstrap uCode: %d\n", ret);
5606 /* start card; "initialize" will load runtime ucode */
5607 il4965_nic_start(il);
5609 D_INFO(DRV_NAME " is coming up\n");
5614 set_bit(S_EXIT_PENDING, &il->status);
5616 clear_bit(S_EXIT_PENDING, &il->status);
5618 /* tried to restart and config the device for as long as our
5619 * patience could withstand */
5620 IL_ERR("Unable to initialize device after %d attempts.\n", i);
5624 /*****************************************************************************
5626 * Workqueue callbacks
5628 *****************************************************************************/
5631 il4965_bg_init_alive_start(struct work_struct *data)
5633 struct il_priv *il =
5634 container_of(data, struct il_priv, init_alive_start.work);
5636 mutex_lock(&il->mutex);
5637 if (test_bit(S_EXIT_PENDING, &il->status))
5640 il->ops->init_alive_start(il);
5642 mutex_unlock(&il->mutex);
5646 il4965_bg_alive_start(struct work_struct *data)
5648 struct il_priv *il =
5649 container_of(data, struct il_priv, alive_start.work);
5651 mutex_lock(&il->mutex);
5652 if (test_bit(S_EXIT_PENDING, &il->status))
5655 il4965_alive_start(il);
5657 mutex_unlock(&il->mutex);
5661 il4965_bg_run_time_calib_work(struct work_struct *work)
5663 struct il_priv *il = container_of(work, struct il_priv,
5664 run_time_calib_work);
5666 mutex_lock(&il->mutex);
5668 if (test_bit(S_EXIT_PENDING, &il->status) ||
5669 test_bit(S_SCANNING, &il->status)) {
5670 mutex_unlock(&il->mutex);
5674 if (il->start_calib) {
5675 il4965_chain_noise_calibration(il, (void *)&il->_4965.stats);
5676 il4965_sensitivity_calibration(il, (void *)&il->_4965.stats);
5679 mutex_unlock(&il->mutex);
5683 il4965_bg_restart(struct work_struct *data)
5685 struct il_priv *il = container_of(data, struct il_priv, restart);
5687 if (test_bit(S_EXIT_PENDING, &il->status))
5690 if (test_and_clear_bit(S_FW_ERROR, &il->status)) {
5691 mutex_lock(&il->mutex);
5696 mutex_unlock(&il->mutex);
5697 il4965_cancel_deferred_work(il);
5698 ieee80211_restart_hw(il->hw);
5702 mutex_lock(&il->mutex);
5703 if (test_bit(S_EXIT_PENDING, &il->status)) {
5704 mutex_unlock(&il->mutex);
5709 mutex_unlock(&il->mutex);
5714 il4965_bg_rx_replenish(struct work_struct *data)
5716 struct il_priv *il = container_of(data, struct il_priv, rx_replenish);
5718 if (test_bit(S_EXIT_PENDING, &il->status))
5721 mutex_lock(&il->mutex);
5722 il4965_rx_replenish(il);
5723 mutex_unlock(&il->mutex);
5726 /*****************************************************************************
5728 * mac80211 entry point functions
5730 *****************************************************************************/
5732 #define UCODE_READY_TIMEOUT (4 * HZ)
5735 * Not a mac80211 entry point function, but it fits in with all the
5736 * other mac80211 functions grouped here.
5739 il4965_mac_setup_register(struct il_priv *il, u32 max_probe_length)
5742 struct ieee80211_hw *hw = il->hw;
5744 hw->rate_control_algorithm = "iwl-4965-rs";
5746 /* Tell mac80211 our characteristics */
5748 IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_AMPDU_AGGREGATION |
5749 IEEE80211_HW_NEED_DTIM_BEFORE_ASSOC | IEEE80211_HW_SPECTRUM_MGMT |
5750 IEEE80211_HW_SUPPORTS_PS | IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
5751 if (il->cfg->sku & IL_SKU_N)
5753 IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
5754 IEEE80211_HW_SUPPORTS_STATIC_SMPS;
5756 hw->sta_data_size = sizeof(struct il_station_priv);
5757 hw->vif_data_size = sizeof(struct il_vif_priv);
5759 hw->wiphy->interface_modes =
5760 BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_ADHOC);
5763 WIPHY_FLAG_CUSTOM_REGULATORY | WIPHY_FLAG_DISABLE_BEACON_HINTS |
5764 WIPHY_FLAG_IBSS_RSN;
5767 * For now, disable PS by default because it affects
5768 * RX performance significantly.
5770 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
5772 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
5773 /* we create the 802.11 header and a zero-length SSID element */
5774 hw->wiphy->max_scan_ie_len = max_probe_length - 24 - 2;
5776 /* Default value; 4 EDCA QOS priorities */
5779 hw->max_listen_interval = IL_CONN_MAX_LISTEN_INTERVAL;
5781 if (il->bands[IEEE80211_BAND_2GHZ].n_channels)
5782 il->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
5783 &il->bands[IEEE80211_BAND_2GHZ];
5784 if (il->bands[IEEE80211_BAND_5GHZ].n_channels)
5785 il->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
5786 &il->bands[IEEE80211_BAND_5GHZ];
5790 ret = ieee80211_register_hw(il->hw);
5792 IL_ERR("Failed to register hw (error %d)\n", ret);
5795 il->mac80211_registered = 1;
5801 il4965_mac_start(struct ieee80211_hw *hw)
5803 struct il_priv *il = hw->priv;
5806 D_MAC80211("enter\n");
5808 /* we should be verifying the device is ready to be opened */
5809 mutex_lock(&il->mutex);
5810 ret = __il4965_up(il);
5811 mutex_unlock(&il->mutex);
5816 if (il_is_rfkill(il))
5819 D_INFO("Start UP work done.\n");
5821 /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
5822 * mac80211 will not be run successfully. */
5823 ret = wait_event_timeout(il->wait_command_queue,
5824 test_bit(S_READY, &il->status),
5825 UCODE_READY_TIMEOUT);
5827 if (!test_bit(S_READY, &il->status)) {
5828 IL_ERR("START_ALIVE timeout after %dms.\n",
5829 jiffies_to_msecs(UCODE_READY_TIMEOUT));
5834 il4965_led_enable(il);
5838 D_MAC80211("leave\n");
5843 il4965_mac_stop(struct ieee80211_hw *hw)
5845 struct il_priv *il = hw->priv;
5847 D_MAC80211("enter\n");
5856 flush_workqueue(il->workqueue);
5858 /* User space software may expect getting rfkill changes
5859 * even if interface is down */
5860 _il_wr(il, CSR_INT, 0xFFFFFFFF);
5861 il_enable_rfkill_int(il);
5863 D_MAC80211("leave\n");
5867 il4965_mac_tx(struct ieee80211_hw *hw,
5868 struct ieee80211_tx_control *control,
5869 struct sk_buff *skb)
5871 struct il_priv *il = hw->priv;
5873 D_MACDUMP("enter\n");
5875 D_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
5876 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
5878 if (il4965_tx_skb(il, control->sta, skb))
5879 dev_kfree_skb_any(skb);
5881 D_MACDUMP("leave\n");
5885 il4965_mac_update_tkip_key(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5886 struct ieee80211_key_conf *keyconf,
5887 struct ieee80211_sta *sta, u32 iv32, u16 * phase1key)
5889 struct il_priv *il = hw->priv;
5891 D_MAC80211("enter\n");
5893 il4965_update_tkip_key(il, keyconf, sta, iv32, phase1key);
5895 D_MAC80211("leave\n");
5899 il4965_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
5900 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
5901 struct ieee80211_key_conf *key)
5903 struct il_priv *il = hw->priv;
5906 bool is_default_wep_key = false;
5908 D_MAC80211("enter\n");
5910 if (il->cfg->mod_params->sw_crypto) {
5911 D_MAC80211("leave - hwcrypto disabled\n");
5916 * To support IBSS RSN, don't program group keys in IBSS, the
5917 * hardware will then not attempt to decrypt the frames.
5919 if (vif->type == NL80211_IFTYPE_ADHOC &&
5920 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
5921 D_MAC80211("leave - ad-hoc group key\n");
5925 sta_id = il_sta_id_or_broadcast(il, sta);
5926 if (sta_id == IL_INVALID_STATION)
5929 mutex_lock(&il->mutex);
5930 il_scan_cancel_timeout(il, 100);
5933 * If we are getting WEP group key and we didn't receive any key mapping
5934 * so far, we are in legacy wep mode (group key only), otherwise we are
5936 * In legacy wep mode, we use another host command to the uCode.
5938 if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
5939 key->cipher == WLAN_CIPHER_SUITE_WEP104) && !sta) {
5941 is_default_wep_key = !il->_4965.key_mapping_keys;
5943 is_default_wep_key =
5944 (key->hw_key_idx == HW_KEY_DEFAULT);
5949 if (is_default_wep_key)
5950 ret = il4965_set_default_wep_key(il, key);
5952 ret = il4965_set_dynamic_key(il, key, sta_id);
5954 D_MAC80211("enable hwcrypto key\n");
5957 if (is_default_wep_key)
5958 ret = il4965_remove_default_wep_key(il, key);
5960 ret = il4965_remove_dynamic_key(il, key, sta_id);
5962 D_MAC80211("disable hwcrypto key\n");
5968 mutex_unlock(&il->mutex);
5969 D_MAC80211("leave\n");
5975 il4965_mac_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5976 enum ieee80211_ampdu_mlme_action action,
5977 struct ieee80211_sta *sta, u16 tid, u16 * ssn,
5980 struct il_priv *il = hw->priv;
5983 D_HT("A-MPDU action on addr %pM tid %d\n", sta->addr, tid);
5985 if (!(il->cfg->sku & IL_SKU_N))
5988 mutex_lock(&il->mutex);
5991 case IEEE80211_AMPDU_RX_START:
5993 ret = il4965_sta_rx_agg_start(il, sta, tid, *ssn);
5995 case IEEE80211_AMPDU_RX_STOP:
5997 ret = il4965_sta_rx_agg_stop(il, sta, tid);
5998 if (test_bit(S_EXIT_PENDING, &il->status))
6001 case IEEE80211_AMPDU_TX_START:
6003 ret = il4965_tx_agg_start(il, vif, sta, tid, ssn);
6005 case IEEE80211_AMPDU_TX_STOP_CONT:
6006 case IEEE80211_AMPDU_TX_STOP_FLUSH:
6007 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
6009 ret = il4965_tx_agg_stop(il, vif, sta, tid);
6010 if (test_bit(S_EXIT_PENDING, &il->status))
6013 case IEEE80211_AMPDU_TX_OPERATIONAL:
6017 mutex_unlock(&il->mutex);
6023 il4965_mac_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
6024 struct ieee80211_sta *sta)
6026 struct il_priv *il = hw->priv;
6027 struct il_station_priv *sta_priv = (void *)sta->drv_priv;
6028 bool is_ap = vif->type == NL80211_IFTYPE_STATION;
6032 D_INFO("received request to add station %pM\n", sta->addr);
6033 mutex_lock(&il->mutex);
6034 D_INFO("proceeding to add station %pM\n", sta->addr);
6035 sta_priv->common.sta_id = IL_INVALID_STATION;
6037 atomic_set(&sta_priv->pending_frames, 0);
6040 il_add_station_common(il, sta->addr, is_ap, sta, &sta_id);
6042 IL_ERR("Unable to add station %pM (%d)\n", sta->addr, ret);
6043 /* Should we return success if return code is EEXIST ? */
6044 mutex_unlock(&il->mutex);
6048 sta_priv->common.sta_id = sta_id;
6050 /* Initialize rate scaling */
6051 D_INFO("Initializing rate scaling for station %pM\n", sta->addr);
6052 il4965_rs_rate_init(il, sta, sta_id);
6053 mutex_unlock(&il->mutex);
6059 il4965_mac_channel_switch(struct ieee80211_hw *hw,
6060 struct ieee80211_channel_switch *ch_switch)
6062 struct il_priv *il = hw->priv;
6063 const struct il_channel_info *ch_info;
6064 struct ieee80211_conf *conf = &hw->conf;
6065 struct ieee80211_channel *channel = ch_switch->chandef.chan;
6066 struct il_ht_config *ht_conf = &il->current_ht_config;
6069 D_MAC80211("enter\n");
6071 mutex_lock(&il->mutex);
6073 if (il_is_rfkill(il))
6076 if (test_bit(S_EXIT_PENDING, &il->status) ||
6077 test_bit(S_SCANNING, &il->status) ||
6078 test_bit(S_CHANNEL_SWITCH_PENDING, &il->status))
6081 if (!il_is_associated(il))
6084 if (!il->ops->set_channel_switch)
6087 ch = channel->hw_value;
6088 if (le16_to_cpu(il->active.channel) == ch)
6091 ch_info = il_get_channel_info(il, channel->band, ch);
6092 if (!il_is_channel_valid(ch_info)) {
6093 D_MAC80211("invalid channel\n");
6097 spin_lock_irq(&il->lock);
6099 il->current_ht_config.smps = conf->smps_mode;
6101 /* Configure HT40 channels */
6102 switch (cfg80211_get_chandef_type(&ch_switch->chandef)) {
6103 case NL80211_CHAN_NO_HT:
6104 case NL80211_CHAN_HT20:
6105 il->ht.is_40mhz = false;
6106 il->ht.extension_chan_offset = IEEE80211_HT_PARAM_CHA_SEC_NONE;
6108 case NL80211_CHAN_HT40MINUS:
6109 il->ht.extension_chan_offset = IEEE80211_HT_PARAM_CHA_SEC_BELOW;
6110 il->ht.is_40mhz = true;
6112 case NL80211_CHAN_HT40PLUS:
6113 il->ht.extension_chan_offset = IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
6114 il->ht.is_40mhz = true;
6118 if ((le16_to_cpu(il->staging.channel) != ch))
6119 il->staging.flags = 0;
6121 il_set_rxon_channel(il, channel);
6122 il_set_rxon_ht(il, ht_conf);
6123 il_set_flags_for_band(il, channel->band, il->vif);
6125 spin_unlock_irq(&il->lock);
6129 * at this point, staging_rxon has the
6130 * configuration for channel switch
6132 set_bit(S_CHANNEL_SWITCH_PENDING, &il->status);
6133 il->switch_channel = cpu_to_le16(ch);
6134 if (il->ops->set_channel_switch(il, ch_switch)) {
6135 clear_bit(S_CHANNEL_SWITCH_PENDING, &il->status);
6136 il->switch_channel = 0;
6137 ieee80211_chswitch_done(il->vif, false);
6141 mutex_unlock(&il->mutex);
6142 D_MAC80211("leave\n");
6146 il4965_configure_filter(struct ieee80211_hw *hw, unsigned int changed_flags,
6147 unsigned int *total_flags, u64 multicast)
6149 struct il_priv *il = hw->priv;
6150 __le32 filter_or = 0, filter_nand = 0;
6152 #define CHK(test, flag) do { \
6153 if (*total_flags & (test)) \
6154 filter_or |= (flag); \
6156 filter_nand |= (flag); \
6159 D_MAC80211("Enter: changed: 0x%x, total: 0x%x\n", changed_flags,
6162 CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
6163 /* Setting _just_ RXON_FILTER_CTL2HOST_MSK causes FH errors */
6164 CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_PROMISC_MSK);
6165 CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
6169 mutex_lock(&il->mutex);
6171 il->staging.filter_flags &= ~filter_nand;
6172 il->staging.filter_flags |= filter_or;
6175 * Not committing directly because hardware can perform a scan,
6176 * but we'll eventually commit the filter flags change anyway.
6179 mutex_unlock(&il->mutex);
6182 * Receiving all multicast frames is always enabled by the
6183 * default flags setup in il_connection_init_rx_config()
6184 * since we currently do not support programming multicast
6185 * filters into the device.
6188 FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
6189 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
6192 /*****************************************************************************
6194 * driver setup and teardown
6196 *****************************************************************************/
6199 il4965_bg_txpower_work(struct work_struct *work)
6201 struct il_priv *il = container_of(work, struct il_priv,
6204 mutex_lock(&il->mutex);
6206 /* If a scan happened to start before we got here
6207 * then just return; the stats notification will
6208 * kick off another scheduled work to compensate for
6209 * any temperature delta we missed here. */
6210 if (test_bit(S_EXIT_PENDING, &il->status) ||
6211 test_bit(S_SCANNING, &il->status))
6214 /* Regardless of if we are associated, we must reconfigure the
6215 * TX power since frames can be sent on non-radar channels while
6217 il->ops->send_tx_power(il);
6219 /* Update last_temperature to keep is_calib_needed from running
6220 * when it isn't needed... */
6221 il->last_temperature = il->temperature;
6223 mutex_unlock(&il->mutex);
6227 il4965_setup_deferred_work(struct il_priv *il)
6229 il->workqueue = create_singlethread_workqueue(DRV_NAME);
6231 init_waitqueue_head(&il->wait_command_queue);
6233 INIT_WORK(&il->restart, il4965_bg_restart);
6234 INIT_WORK(&il->rx_replenish, il4965_bg_rx_replenish);
6235 INIT_WORK(&il->run_time_calib_work, il4965_bg_run_time_calib_work);
6236 INIT_DELAYED_WORK(&il->init_alive_start, il4965_bg_init_alive_start);
6237 INIT_DELAYED_WORK(&il->alive_start, il4965_bg_alive_start);
6239 il_setup_scan_deferred_work(il);
6241 INIT_WORK(&il->txpower_work, il4965_bg_txpower_work);
6243 init_timer(&il->stats_periodic);
6244 il->stats_periodic.data = (unsigned long)il;
6245 il->stats_periodic.function = il4965_bg_stats_periodic;
6247 init_timer(&il->watchdog);
6248 il->watchdog.data = (unsigned long)il;
6249 il->watchdog.function = il_bg_watchdog;
6251 tasklet_init(&il->irq_tasklet,
6252 (void (*)(unsigned long))il4965_irq_tasklet,
6257 il4965_cancel_deferred_work(struct il_priv *il)
6259 cancel_work_sync(&il->txpower_work);
6260 cancel_delayed_work_sync(&il->init_alive_start);
6261 cancel_delayed_work(&il->alive_start);
6262 cancel_work_sync(&il->run_time_calib_work);
6264 il_cancel_scan_deferred_work(il);
6266 del_timer_sync(&il->stats_periodic);
6270 il4965_init_hw_rates(struct il_priv *il, struct ieee80211_rate *rates)
6274 for (i = 0; i < RATE_COUNT_LEGACY; i++) {
6275 rates[i].bitrate = il_rates[i].ieee * 5;
6276 rates[i].hw_value = i; /* Rate scaling will work on idxes */
6277 rates[i].hw_value_short = i;
6279 if ((i >= IL_FIRST_CCK_RATE) && (i <= IL_LAST_CCK_RATE)) {
6281 * If CCK != 1M then set short preamble rate flag.
6284 (il_rates[i].plcp ==
6285 RATE_1M_PLCP) ? 0 : IEEE80211_RATE_SHORT_PREAMBLE;
6291 * Acquire il->lock before calling this function !
6294 il4965_set_wr_ptrs(struct il_priv *il, int txq_id, u32 idx)
6296 il_wr(il, HBUS_TARG_WRPTR, (idx & 0xff) | (txq_id << 8));
6297 il_wr_prph(il, IL49_SCD_QUEUE_RDPTR(txq_id), idx);
6301 il4965_tx_queue_set_status(struct il_priv *il, struct il_tx_queue *txq,
6302 int tx_fifo_id, int scd_retry)
6304 int txq_id = txq->q.id;
6306 /* Find out whether to activate Tx queue */
6307 int active = test_bit(txq_id, &il->txq_ctx_active_msk) ? 1 : 0;
6309 /* Set up and activate */
6310 il_wr_prph(il, IL49_SCD_QUEUE_STATUS_BITS(txq_id),
6311 (active << IL49_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
6312 (tx_fifo_id << IL49_SCD_QUEUE_STTS_REG_POS_TXF) |
6313 (scd_retry << IL49_SCD_QUEUE_STTS_REG_POS_WSL) |
6314 (scd_retry << IL49_SCD_QUEUE_STTS_REG_POS_SCD_ACK) |
6315 IL49_SCD_QUEUE_STTS_REG_MSK);
6317 txq->sched_retry = scd_retry;
6319 D_INFO("%s %s Queue %d on AC %d\n", active ? "Activate" : "Deactivate",
6320 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
6323 static const struct ieee80211_ops il4965_mac_ops = {
6324 .tx = il4965_mac_tx,
6325 .start = il4965_mac_start,
6326 .stop = il4965_mac_stop,
6327 .add_interface = il_mac_add_interface,
6328 .remove_interface = il_mac_remove_interface,
6329 .change_interface = il_mac_change_interface,
6330 .config = il_mac_config,
6331 .configure_filter = il4965_configure_filter,
6332 .set_key = il4965_mac_set_key,
6333 .update_tkip_key = il4965_mac_update_tkip_key,
6334 .conf_tx = il_mac_conf_tx,
6335 .reset_tsf = il_mac_reset_tsf,
6336 .bss_info_changed = il_mac_bss_info_changed,
6337 .ampdu_action = il4965_mac_ampdu_action,
6338 .hw_scan = il_mac_hw_scan,
6339 .sta_add = il4965_mac_sta_add,
6340 .sta_remove = il_mac_sta_remove,
6341 .channel_switch = il4965_mac_channel_switch,
6342 .tx_last_beacon = il_mac_tx_last_beacon,
6343 .flush = il_mac_flush,
6347 il4965_init_drv(struct il_priv *il)
6351 spin_lock_init(&il->sta_lock);
6352 spin_lock_init(&il->hcmd_lock);
6354 INIT_LIST_HEAD(&il->free_frames);
6356 mutex_init(&il->mutex);
6358 il->ieee_channels = NULL;
6359 il->ieee_rates = NULL;
6360 il->band = IEEE80211_BAND_2GHZ;
6362 il->iw_mode = NL80211_IFTYPE_STATION;
6363 il->current_ht_config.smps = IEEE80211_SMPS_STATIC;
6364 il->missed_beacon_threshold = IL_MISSED_BEACON_THRESHOLD_DEF;
6366 /* initialize force reset */
6367 il->force_reset.reset_duration = IL_DELAY_NEXT_FORCE_FW_RELOAD;
6369 /* Choose which receivers/antennas to use */
6370 if (il->ops->set_rxon_chain)
6371 il->ops->set_rxon_chain(il);
6373 il_init_scan_params(il);
6375 ret = il_init_channel_map(il);
6377 IL_ERR("initializing regulatory failed: %d\n", ret);
6381 ret = il_init_geos(il);
6383 IL_ERR("initializing geos failed: %d\n", ret);
6384 goto err_free_channel_map;
6386 il4965_init_hw_rates(il, il->ieee_rates);
6390 err_free_channel_map:
6391 il_free_channel_map(il);
6397 il4965_uninit_drv(struct il_priv *il)
6400 il_free_channel_map(il);
6401 kfree(il->scan_cmd);
6405 il4965_hw_detect(struct il_priv *il)
6407 il->hw_rev = _il_rd(il, CSR_HW_REV);
6408 il->hw_wa_rev = _il_rd(il, CSR_HW_REV_WA_REG);
6409 il->rev_id = il->pci_dev->revision;
6410 D_INFO("HW Revision ID = 0x%X\n", il->rev_id);
6413 static struct il_sensitivity_ranges il4965_sensitivity = {
6415 .max_nrg_cck = 0, /* not used, set to 0 */
6417 .auto_corr_min_ofdm = 85,
6418 .auto_corr_min_ofdm_mrc = 170,
6419 .auto_corr_min_ofdm_x1 = 105,
6420 .auto_corr_min_ofdm_mrc_x1 = 220,
6422 .auto_corr_max_ofdm = 120,
6423 .auto_corr_max_ofdm_mrc = 210,
6424 .auto_corr_max_ofdm_x1 = 140,
6425 .auto_corr_max_ofdm_mrc_x1 = 270,
6427 .auto_corr_min_cck = 125,
6428 .auto_corr_max_cck = 200,
6429 .auto_corr_min_cck_mrc = 200,
6430 .auto_corr_max_cck_mrc = 400,
6435 .barker_corr_th_min = 190,
6436 .barker_corr_th_min_mrc = 390,
6441 il4965_set_hw_params(struct il_priv *il)
6443 il->hw_params.bcast_id = IL4965_BROADCAST_ID;
6444 il->hw_params.max_rxq_size = RX_QUEUE_SIZE;
6445 il->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
6446 if (il->cfg->mod_params->amsdu_size_8K)
6447 il->hw_params.rx_page_order = get_order(IL_RX_BUF_SIZE_8K);
6449 il->hw_params.rx_page_order = get_order(IL_RX_BUF_SIZE_4K);
6451 il->hw_params.max_beacon_itrvl = IL_MAX_UCODE_BEACON_INTERVAL;
6453 if (il->cfg->mod_params->disable_11n)
6454 il->cfg->sku &= ~IL_SKU_N;
6456 if (il->cfg->mod_params->num_of_queues >= IL_MIN_NUM_QUEUES &&
6457 il->cfg->mod_params->num_of_queues <= IL49_NUM_QUEUES)
6458 il->cfg->num_of_queues =
6459 il->cfg->mod_params->num_of_queues;
6461 il->hw_params.max_txq_num = il->cfg->num_of_queues;
6462 il->hw_params.dma_chnl_num = FH49_TCSR_CHNL_NUM;
6463 il->hw_params.scd_bc_tbls_size =
6464 il->cfg->num_of_queues *
6465 sizeof(struct il4965_scd_bc_tbl);
6467 il->hw_params.tfd_size = sizeof(struct il_tfd);
6468 il->hw_params.max_stations = IL4965_STATION_COUNT;
6469 il->hw_params.max_data_size = IL49_RTC_DATA_SIZE;
6470 il->hw_params.max_inst_size = IL49_RTC_INST_SIZE;
6471 il->hw_params.max_bsm_size = BSM_SRAM_SIZE;
6472 il->hw_params.ht40_channel = BIT(IEEE80211_BAND_5GHZ);
6474 il->hw_params.rx_wrt_ptr_reg = FH49_RSCSR_CHNL0_WPTR;
6476 il->hw_params.tx_chains_num = il4965_num_of_ant(il->cfg->valid_tx_ant);
6477 il->hw_params.rx_chains_num = il4965_num_of_ant(il->cfg->valid_rx_ant);
6478 il->hw_params.valid_tx_ant = il->cfg->valid_tx_ant;
6479 il->hw_params.valid_rx_ant = il->cfg->valid_rx_ant;
6481 il->hw_params.ct_kill_threshold =
6482 CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD_LEGACY);
6484 il->hw_params.sens = &il4965_sensitivity;
6485 il->hw_params.beacon_time_tsf_bits = IL4965_EXT_BEACON_TIME_POS;
6489 il4965_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
6493 struct ieee80211_hw *hw;
6494 struct il_cfg *cfg = (struct il_cfg *)(ent->driver_data);
6495 unsigned long flags;
6498 /************************
6499 * 1. Allocating HW data
6500 ************************/
6502 hw = ieee80211_alloc_hw(sizeof(struct il_priv), &il4965_mac_ops);
6509 SET_IEEE80211_DEV(hw, &pdev->dev);
6511 D_INFO("*** LOAD DRIVER ***\n");
6513 il->ops = &il4965_ops;
6514 #ifdef CONFIG_IWLEGACY_DEBUGFS
6515 il->debugfs_ops = &il4965_debugfs_ops;
6518 il->inta_mask = CSR_INI_SET_MASK;
6520 /**************************
6521 * 2. Initializing PCI bus
6522 **************************/
6523 pci_disable_link_state(pdev,
6524 PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
6525 PCIE_LINK_STATE_CLKPM);
6527 if (pci_enable_device(pdev)) {
6529 goto out_ieee80211_free_hw;
6532 pci_set_master(pdev);
6534 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
6536 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
6538 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6541 pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
6542 /* both attempts failed: */
6544 IL_WARN("No suitable DMA available.\n");
6545 goto out_pci_disable_device;
6549 err = pci_request_regions(pdev, DRV_NAME);
6551 goto out_pci_disable_device;
6553 pci_set_drvdata(pdev, il);
6555 /***********************
6556 * 3. Read REV register
6557 ***********************/
6558 il->hw_base = pci_ioremap_bar(pdev, 0);
6561 goto out_pci_release_regions;
6564 D_INFO("pci_resource_len = 0x%08llx\n",
6565 (unsigned long long)pci_resource_len(pdev, 0));
6566 D_INFO("pci_resource_base = %p\n", il->hw_base);
6568 /* these spin locks will be used in apm_ops.init and EEPROM access
6569 * we should init now
6571 spin_lock_init(&il->reg_lock);
6572 spin_lock_init(&il->lock);
6575 * stop and reset the on-board processor just in case it is in a
6576 * strange state ... like being left stranded by a primary kernel
6577 * and this is now the kdump kernel trying to start up
6579 _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
6581 il4965_hw_detect(il);
6582 IL_INFO("Detected %s, REV=0x%X\n", il->cfg->name, il->hw_rev);
6584 /* We disable the RETRY_TIMEOUT register (0x41) to keep
6585 * PCI Tx retries from interfering with C3 CPU state */
6586 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
6588 il4965_prepare_card_hw(il);
6589 if (!il->hw_ready) {
6590 IL_WARN("Failed, HW not ready\n");
6598 /* Read the EEPROM */
6599 err = il_eeprom_init(il);
6601 IL_ERR("Unable to init EEPROM\n");
6604 err = il4965_eeprom_check_version(il);
6606 goto out_free_eeprom;
6608 /* extract MAC Address */
6609 il4965_eeprom_get_mac(il, il->addresses[0].addr);
6610 D_INFO("MAC address: %pM\n", il->addresses[0].addr);
6611 il->hw->wiphy->addresses = il->addresses;
6612 il->hw->wiphy->n_addresses = 1;
6614 /************************
6615 * 5. Setup HW constants
6616 ************************/
6617 il4965_set_hw_params(il);
6619 /*******************
6621 *******************/
6623 err = il4965_init_drv(il);
6625 goto out_free_eeprom;
6626 /* At this point both hw and il are initialized. */
6628 /********************
6630 ********************/
6631 spin_lock_irqsave(&il->lock, flags);
6632 il_disable_interrupts(il);
6633 spin_unlock_irqrestore(&il->lock, flags);
6635 pci_enable_msi(il->pci_dev);
6637 err = request_irq(il->pci_dev->irq, il_isr, IRQF_SHARED, DRV_NAME, il);
6639 IL_ERR("Error allocating IRQ %d\n", il->pci_dev->irq);
6640 goto out_disable_msi;
6643 il4965_setup_deferred_work(il);
6644 il4965_setup_handlers(il);
6646 /*********************************************
6647 * 8. Enable interrupts and read RFKILL state
6648 *********************************************/
6650 /* enable rfkill interrupt: hw bug w/a */
6651 pci_read_config_word(il->pci_dev, PCI_COMMAND, &pci_cmd);
6652 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
6653 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
6654 pci_write_config_word(il->pci_dev, PCI_COMMAND, pci_cmd);
6657 il_enable_rfkill_int(il);
6659 /* If platform's RF_KILL switch is NOT set to KILL */
6660 if (_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
6661 clear_bit(S_RFKILL, &il->status);
6663 set_bit(S_RFKILL, &il->status);
6665 wiphy_rfkill_set_hw_state(il->hw->wiphy,
6666 test_bit(S_RFKILL, &il->status));
6668 il_power_initialize(il);
6670 init_completion(&il->_4965.firmware_loading_complete);
6672 err = il4965_request_firmware(il, true);
6674 goto out_destroy_workqueue;
6678 out_destroy_workqueue:
6679 destroy_workqueue(il->workqueue);
6680 il->workqueue = NULL;
6681 free_irq(il->pci_dev->irq, il);
6683 pci_disable_msi(il->pci_dev);
6684 il4965_uninit_drv(il);
6688 iounmap(il->hw_base);
6689 out_pci_release_regions:
6690 pci_set_drvdata(pdev, NULL);
6691 pci_release_regions(pdev);
6692 out_pci_disable_device:
6693 pci_disable_device(pdev);
6694 out_ieee80211_free_hw:
6695 ieee80211_free_hw(il->hw);
6701 il4965_pci_remove(struct pci_dev *pdev)
6703 struct il_priv *il = pci_get_drvdata(pdev);
6704 unsigned long flags;
6709 wait_for_completion(&il->_4965.firmware_loading_complete);
6711 D_INFO("*** UNLOAD DRIVER ***\n");
6713 il_dbgfs_unregister(il);
6714 sysfs_remove_group(&pdev->dev.kobj, &il_attribute_group);
6716 /* ieee80211_unregister_hw call wil cause il_mac_stop to
6717 * to be called and il4965_down since we are removing the device
6718 * we need to set S_EXIT_PENDING bit.
6720 set_bit(S_EXIT_PENDING, &il->status);
6724 if (il->mac80211_registered) {
6725 ieee80211_unregister_hw(il->hw);
6726 il->mac80211_registered = 0;
6732 * Make sure device is reset to low power before unloading driver.
6733 * This may be redundant with il4965_down(), but there are paths to
6734 * run il4965_down() without calling apm_ops.stop(), and there are
6735 * paths to avoid running il4965_down() at all before leaving driver.
6736 * This (inexpensive) call *makes sure* device is reset.
6740 /* make sure we flush any pending irq or
6741 * tasklet for the driver
6743 spin_lock_irqsave(&il->lock, flags);
6744 il_disable_interrupts(il);
6745 spin_unlock_irqrestore(&il->lock, flags);
6747 il4965_synchronize_irq(il);
6749 il4965_dealloc_ucode_pci(il);
6752 il4965_rx_queue_free(il, &il->rxq);
6753 il4965_hw_txq_ctx_free(il);
6757 /*netif_stop_queue(dev); */
6758 flush_workqueue(il->workqueue);
6760 /* ieee80211_unregister_hw calls il_mac_stop, which flushes
6761 * il->workqueue... so we can't take down the workqueue
6763 destroy_workqueue(il->workqueue);
6764 il->workqueue = NULL;
6766 free_irq(il->pci_dev->irq, il);
6767 pci_disable_msi(il->pci_dev);
6768 iounmap(il->hw_base);
6769 pci_release_regions(pdev);
6770 pci_disable_device(pdev);
6771 pci_set_drvdata(pdev, NULL);
6773 il4965_uninit_drv(il);
6775 dev_kfree_skb(il->beacon_skb);
6777 ieee80211_free_hw(il->hw);
6781 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
6782 * must be called under il->lock and mac access
6785 il4965_txq_set_sched(struct il_priv *il, u32 mask)
6787 il_wr_prph(il, IL49_SCD_TXFACT, mask);
6790 /*****************************************************************************
6792 * driver and module entry point
6794 *****************************************************************************/
6796 /* Hardware specific file defines the PCI IDs table for that hardware module */
6797 static DEFINE_PCI_DEVICE_TABLE(il4965_hw_card_ids) = {
6798 {IL_PCI_DEVICE(0x4229, PCI_ANY_ID, il4965_cfg)},
6799 {IL_PCI_DEVICE(0x4230, PCI_ANY_ID, il4965_cfg)},
6802 MODULE_DEVICE_TABLE(pci, il4965_hw_card_ids);
6804 static struct pci_driver il4965_driver = {
6806 .id_table = il4965_hw_card_ids,
6807 .probe = il4965_pci_probe,
6808 .remove = il4965_pci_remove,
6809 .driver.pm = IL_LEGACY_PM_OPS,
6817 pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
6818 pr_info(DRV_COPYRIGHT "\n");
6820 ret = il4965_rate_control_register();
6822 pr_err("Unable to register rate control algorithm: %d\n", ret);
6826 ret = pci_register_driver(&il4965_driver);
6828 pr_err("Unable to initialize PCI module\n");
6829 goto error_register;
6835 il4965_rate_control_unregister();
6842 pci_unregister_driver(&il4965_driver);
6843 il4965_rate_control_unregister();
6846 module_exit(il4965_exit);
6847 module_init(il4965_init);
6849 #ifdef CONFIG_IWLEGACY_DEBUG
6850 module_param_named(debug, il_debug_level, uint, S_IRUGO | S_IWUSR);
6851 MODULE_PARM_DESC(debug, "debug output mask");
6854 module_param_named(swcrypto, il4965_mod_params.sw_crypto, int, S_IRUGO);
6855 MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
6856 module_param_named(queues_num, il4965_mod_params.num_of_queues, int, S_IRUGO);
6857 MODULE_PARM_DESC(queues_num, "number of hw queues.");
6858 module_param_named(11n_disable, il4965_mod_params.disable_11n, int, S_IRUGO);
6859 MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
6860 module_param_named(amsdu_size_8K, il4965_mod_params.amsdu_size_8K, int,
6862 MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
6863 module_param_named(fw_restart, il4965_mod_params.restart_fw, int, S_IRUGO);
6864 MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");