1 /* Copyright (c) 2014 Broadcom Corporation
3 * Permission to use, copy, modify, and/or distribute this software for any
4 * purpose with or without fee is hereby granted, provided that the above
5 * copyright notice and this permission notice appear in all copies.
7 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
8 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
9 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
10 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
11 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
12 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
13 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/firmware.h>
19 #include <linux/pci.h>
20 #include <linux/vmalloc.h>
21 #include <linux/delay.h>
22 #include <linux/unaligned/access_ok.h>
23 #include <linux/interrupt.h>
24 #include <linux/bcma/bcma.h>
25 #include <linux/sched.h>
28 #include <chipcommon.h>
29 #include <brcmu_utils.h>
30 #include <brcmu_wifi.h>
31 #include <brcm_hw_ids.h>
35 #include "commonring.h"
42 enum brcmf_pcie_state {
43 BRCMFMAC_PCIE_STATE_DOWN,
44 BRCMFMAC_PCIE_STATE_UP
48 #define BRCMF_PCIE_43602_FW_NAME "brcm/brcmfmac43602-pcie.bin"
49 #define BRCMF_PCIE_43602_NVRAM_NAME "brcm/brcmfmac43602-pcie.txt"
50 #define BRCMF_PCIE_4354_FW_NAME "brcm/brcmfmac4354-pcie.bin"
51 #define BRCMF_PCIE_4354_NVRAM_NAME "brcm/brcmfmac4354-pcie.txt"
52 #define BRCMF_PCIE_4356_FW_NAME "brcm/brcmfmac4356-pcie.bin"
53 #define BRCMF_PCIE_4356_NVRAM_NAME "brcm/brcmfmac4356-pcie.txt"
54 #define BRCMF_PCIE_43570_FW_NAME "brcm/brcmfmac43570-pcie.bin"
55 #define BRCMF_PCIE_43570_NVRAM_NAME "brcm/brcmfmac43570-pcie.txt"
57 #define BRCMF_PCIE_FW_UP_TIMEOUT 2000 /* msec */
59 #define BRCMF_PCIE_TCM_MAP_SIZE (4096 * 1024)
60 #define BRCMF_PCIE_REG_MAP_SIZE (32 * 1024)
62 /* backplane addres space accessed by BAR0 */
63 #define BRCMF_PCIE_BAR0_WINDOW 0x80
64 #define BRCMF_PCIE_BAR0_REG_SIZE 0x1000
65 #define BRCMF_PCIE_BAR0_WRAPPERBASE 0x70
67 #define BRCMF_PCIE_BAR0_WRAPBASE_DMP_OFFSET 0x1000
68 #define BRCMF_PCIE_BARO_PCIE_ENUM_OFFSET 0x2000
70 #define BRCMF_PCIE_ARMCR4REG_BANKIDX 0x40
71 #define BRCMF_PCIE_ARMCR4REG_BANKPDA 0x4C
73 #define BRCMF_PCIE_REG_INTSTATUS 0x90
74 #define BRCMF_PCIE_REG_INTMASK 0x94
75 #define BRCMF_PCIE_REG_SBMBX 0x98
77 #define BRCMF_PCIE_PCIE2REG_INTMASK 0x24
78 #define BRCMF_PCIE_PCIE2REG_MAILBOXINT 0x48
79 #define BRCMF_PCIE_PCIE2REG_MAILBOXMASK 0x4C
80 #define BRCMF_PCIE_PCIE2REG_CONFIGADDR 0x120
81 #define BRCMF_PCIE_PCIE2REG_CONFIGDATA 0x124
82 #define BRCMF_PCIE_PCIE2REG_H2D_MAILBOX 0x140
84 #define BRCMF_PCIE_GENREV1 1
85 #define BRCMF_PCIE_GENREV2 2
87 #define BRCMF_PCIE2_INTA 0x01
88 #define BRCMF_PCIE2_INTB 0x02
90 #define BRCMF_PCIE_INT_0 0x01
91 #define BRCMF_PCIE_INT_1 0x02
92 #define BRCMF_PCIE_INT_DEF (BRCMF_PCIE_INT_0 | \
95 #define BRCMF_PCIE_MB_INT_FN0_0 0x0100
96 #define BRCMF_PCIE_MB_INT_FN0_1 0x0200
97 #define BRCMF_PCIE_MB_INT_D2H0_DB0 0x10000
98 #define BRCMF_PCIE_MB_INT_D2H0_DB1 0x20000
99 #define BRCMF_PCIE_MB_INT_D2H1_DB0 0x40000
100 #define BRCMF_PCIE_MB_INT_D2H1_DB1 0x80000
101 #define BRCMF_PCIE_MB_INT_D2H2_DB0 0x100000
102 #define BRCMF_PCIE_MB_INT_D2H2_DB1 0x200000
103 #define BRCMF_PCIE_MB_INT_D2H3_DB0 0x400000
104 #define BRCMF_PCIE_MB_INT_D2H3_DB1 0x800000
106 #define BRCMF_PCIE_MB_INT_D2H_DB (BRCMF_PCIE_MB_INT_D2H0_DB0 | \
107 BRCMF_PCIE_MB_INT_D2H0_DB1 | \
108 BRCMF_PCIE_MB_INT_D2H1_DB0 | \
109 BRCMF_PCIE_MB_INT_D2H1_DB1 | \
110 BRCMF_PCIE_MB_INT_D2H2_DB0 | \
111 BRCMF_PCIE_MB_INT_D2H2_DB1 | \
112 BRCMF_PCIE_MB_INT_D2H3_DB0 | \
113 BRCMF_PCIE_MB_INT_D2H3_DB1)
115 #define BRCMF_PCIE_MIN_SHARED_VERSION 4
116 #define BRCMF_PCIE_MAX_SHARED_VERSION 5
117 #define BRCMF_PCIE_SHARED_VERSION_MASK 0x00FF
118 #define BRCMF_PCIE_SHARED_TXPUSH_SUPPORT 0x4000
120 #define BRCMF_PCIE_FLAGS_HTOD_SPLIT 0x4000
121 #define BRCMF_PCIE_FLAGS_DTOH_SPLIT 0x8000
123 #define BRCMF_SHARED_MAX_RXBUFPOST_OFFSET 34
124 #define BRCMF_SHARED_RING_BASE_OFFSET 52
125 #define BRCMF_SHARED_RX_DATAOFFSET_OFFSET 36
126 #define BRCMF_SHARED_CONSOLE_ADDR_OFFSET 20
127 #define BRCMF_SHARED_HTOD_MB_DATA_ADDR_OFFSET 40
128 #define BRCMF_SHARED_DTOH_MB_DATA_ADDR_OFFSET 44
129 #define BRCMF_SHARED_RING_INFO_ADDR_OFFSET 48
130 #define BRCMF_SHARED_DMA_SCRATCH_LEN_OFFSET 52
131 #define BRCMF_SHARED_DMA_SCRATCH_ADDR_OFFSET 56
132 #define BRCMF_SHARED_DMA_RINGUPD_LEN_OFFSET 64
133 #define BRCMF_SHARED_DMA_RINGUPD_ADDR_OFFSET 68
135 #define BRCMF_RING_H2D_RING_COUNT_OFFSET 0
136 #define BRCMF_RING_D2H_RING_COUNT_OFFSET 1
137 #define BRCMF_RING_H2D_RING_MEM_OFFSET 4
138 #define BRCMF_RING_H2D_RING_STATE_OFFSET 8
140 #define BRCMF_RING_MEM_BASE_ADDR_OFFSET 8
141 #define BRCMF_RING_MAX_ITEM_OFFSET 4
142 #define BRCMF_RING_LEN_ITEMS_OFFSET 6
143 #define BRCMF_RING_MEM_SZ 16
144 #define BRCMF_RING_STATE_SZ 8
146 #define BRCMF_SHARED_RING_H2D_W_IDX_PTR_OFFSET 4
147 #define BRCMF_SHARED_RING_H2D_R_IDX_PTR_OFFSET 8
148 #define BRCMF_SHARED_RING_D2H_W_IDX_PTR_OFFSET 12
149 #define BRCMF_SHARED_RING_D2H_R_IDX_PTR_OFFSET 16
150 #define BRCMF_SHARED_RING_TCM_MEMLOC_OFFSET 0
151 #define BRCMF_SHARED_RING_MAX_SUB_QUEUES 52
153 #define BRCMF_DEF_MAX_RXBUFPOST 255
155 #define BRCMF_CONSOLE_BUFADDR_OFFSET 8
156 #define BRCMF_CONSOLE_BUFSIZE_OFFSET 12
157 #define BRCMF_CONSOLE_WRITEIDX_OFFSET 16
159 #define BRCMF_DMA_D2H_SCRATCH_BUF_LEN 8
160 #define BRCMF_DMA_D2H_RINGUPD_BUF_LEN 1024
162 #define BRCMF_D2H_DEV_D3_ACK 0x00000001
163 #define BRCMF_D2H_DEV_DS_ENTER_REQ 0x00000002
164 #define BRCMF_D2H_DEV_DS_EXIT_NOTE 0x00000004
166 #define BRCMF_H2D_HOST_D3_INFORM 0x00000001
167 #define BRCMF_H2D_HOST_DS_ACK 0x00000002
169 #define BRCMF_PCIE_MBDATA_TIMEOUT 2000
171 #define BRCMF_PCIE_CFGREG_STATUS_CMD 0x4
172 #define BRCMF_PCIE_CFGREG_PM_CSR 0x4C
173 #define BRCMF_PCIE_CFGREG_MSI_CAP 0x58
174 #define BRCMF_PCIE_CFGREG_MSI_ADDR_L 0x5C
175 #define BRCMF_PCIE_CFGREG_MSI_ADDR_H 0x60
176 #define BRCMF_PCIE_CFGREG_MSI_DATA 0x64
177 #define BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL 0xBC
178 #define BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2 0xDC
179 #define BRCMF_PCIE_CFGREG_RBAR_CTRL 0x228
180 #define BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1 0x248
181 #define BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG 0x4E0
182 #define BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG 0x4F4
183 #define BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB 3
186 MODULE_FIRMWARE(BRCMF_PCIE_43602_FW_NAME);
187 MODULE_FIRMWARE(BRCMF_PCIE_43602_NVRAM_NAME);
188 MODULE_FIRMWARE(BRCMF_PCIE_4354_FW_NAME);
189 MODULE_FIRMWARE(BRCMF_PCIE_4354_NVRAM_NAME);
190 MODULE_FIRMWARE(BRCMF_PCIE_43570_FW_NAME);
191 MODULE_FIRMWARE(BRCMF_PCIE_43570_NVRAM_NAME);
194 struct brcmf_pcie_console {
203 struct brcmf_pcie_shared_info {
204 u32 tcm_base_address;
206 struct brcmf_pcie_ringbuf *commonrings[BRCMF_NROF_COMMON_MSGRINGS];
207 struct brcmf_pcie_ringbuf *flowrings;
211 u32 htod_mb_data_addr;
212 u32 dtoh_mb_data_addr;
214 struct brcmf_pcie_console console;
216 dma_addr_t scratch_dmahandle;
218 dma_addr_t ringupd_dmahandle;
221 struct brcmf_pcie_core_info {
226 struct brcmf_pciedev_info {
227 enum brcmf_pcie_state state;
230 struct pci_dev *pdev;
231 char fw_name[BRCMF_FW_PATH_LEN + BRCMF_FW_NAME_LEN];
232 char nvram_name[BRCMF_FW_PATH_LEN + BRCMF_FW_NAME_LEN];
238 struct brcmf_chip *ci;
241 struct brcmf_pcie_shared_info shared;
242 void (*ringbell)(struct brcmf_pciedev_info *devinfo);
243 wait_queue_head_t mbdata_resp_wait;
244 bool mbdata_completed;
248 struct brcmf_pcie_ringbuf {
249 struct brcmf_commonring commonring;
250 dma_addr_t dma_handle;
253 struct brcmf_pciedev_info *devinfo;
258 static const u32 brcmf_ring_max_item[BRCMF_NROF_COMMON_MSGRINGS] = {
259 BRCMF_H2D_MSGRING_CONTROL_SUBMIT_MAX_ITEM,
260 BRCMF_H2D_MSGRING_RXPOST_SUBMIT_MAX_ITEM,
261 BRCMF_D2H_MSGRING_CONTROL_COMPLETE_MAX_ITEM,
262 BRCMF_D2H_MSGRING_TX_COMPLETE_MAX_ITEM,
263 BRCMF_D2H_MSGRING_RX_COMPLETE_MAX_ITEM
266 static const u32 brcmf_ring_itemsize[BRCMF_NROF_COMMON_MSGRINGS] = {
267 BRCMF_H2D_MSGRING_CONTROL_SUBMIT_ITEMSIZE,
268 BRCMF_H2D_MSGRING_RXPOST_SUBMIT_ITEMSIZE,
269 BRCMF_D2H_MSGRING_CONTROL_COMPLETE_ITEMSIZE,
270 BRCMF_D2H_MSGRING_TX_COMPLETE_ITEMSIZE,
271 BRCMF_D2H_MSGRING_RX_COMPLETE_ITEMSIZE
275 /* dma flushing needs implementation for mips and arm platforms. Should
276 * be put in util. Note, this is not real flushing. It is virtual non
277 * cached memory. Only write buffers should have to be drained. Though
278 * this may be different depending on platform......
280 #define brcmf_dma_flush(addr, len)
281 #define brcmf_dma_invalidate_cache(addr, len)
285 brcmf_pcie_read_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset)
287 void __iomem *address = devinfo->regs + reg_offset;
289 return (ioread32(address));
294 brcmf_pcie_write_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset,
297 void __iomem *address = devinfo->regs + reg_offset;
299 iowrite32(value, address);
304 brcmf_pcie_read_tcm8(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
306 void __iomem *address = devinfo->tcm + mem_offset;
308 return (ioread8(address));
313 brcmf_pcie_read_tcm16(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
315 void __iomem *address = devinfo->tcm + mem_offset;
317 return (ioread16(address));
322 brcmf_pcie_write_tcm16(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
325 void __iomem *address = devinfo->tcm + mem_offset;
327 iowrite16(value, address);
332 brcmf_pcie_read_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
334 void __iomem *address = devinfo->tcm + mem_offset;
336 return (ioread32(address));
341 brcmf_pcie_write_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
344 void __iomem *address = devinfo->tcm + mem_offset;
346 iowrite32(value, address);
351 brcmf_pcie_read_ram32(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
353 void __iomem *addr = devinfo->tcm + devinfo->ci->rambase + mem_offset;
355 return (ioread32(addr));
360 brcmf_pcie_write_ram32(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
363 void __iomem *addr = devinfo->tcm + devinfo->ci->rambase + mem_offset;
365 iowrite32(value, addr);
370 brcmf_pcie_copy_mem_todev(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
371 void *srcaddr, u32 len)
373 void __iomem *address = devinfo->tcm + mem_offset;
378 if (((ulong)address & 4) || ((ulong)srcaddr & 4) || (len & 4)) {
379 if (((ulong)address & 2) || ((ulong)srcaddr & 2) || (len & 2)) {
380 src8 = (u8 *)srcaddr;
382 iowrite8(*src8, address);
389 src16 = (__le16 *)srcaddr;
391 iowrite16(le16_to_cpu(*src16), address);
399 src32 = (__le32 *)srcaddr;
401 iowrite32(le32_to_cpu(*src32), address);
410 #define WRITECC32(devinfo, reg, value) brcmf_pcie_write_reg32(devinfo, \
411 CHIPCREGOFFS(reg), value)
415 brcmf_pcie_select_core(struct brcmf_pciedev_info *devinfo, u16 coreid)
417 const struct pci_dev *pdev = devinfo->pdev;
418 struct brcmf_core *core;
421 core = brcmf_chip_get_core(devinfo->ci, coreid);
423 bar0_win = core->base;
424 pci_write_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, bar0_win);
425 if (pci_read_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW,
427 if (bar0_win != core->base) {
428 bar0_win = core->base;
429 pci_write_config_dword(pdev,
430 BRCMF_PCIE_BAR0_WINDOW,
435 brcmf_err("Unsupported core selected %x\n", coreid);
440 static void brcmf_pcie_reset_device(struct brcmf_pciedev_info *devinfo)
442 u16 cfg_offset[] = { BRCMF_PCIE_CFGREG_STATUS_CMD,
443 BRCMF_PCIE_CFGREG_PM_CSR,
444 BRCMF_PCIE_CFGREG_MSI_CAP,
445 BRCMF_PCIE_CFGREG_MSI_ADDR_L,
446 BRCMF_PCIE_CFGREG_MSI_ADDR_H,
447 BRCMF_PCIE_CFGREG_MSI_DATA,
448 BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2,
449 BRCMF_PCIE_CFGREG_RBAR_CTRL,
450 BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1,
451 BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG,
452 BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG };
460 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
461 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGADDR,
462 BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL);
463 lsc = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA);
464 val = lsc & (~BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB);
465 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA, val);
467 brcmf_pcie_select_core(devinfo, BCMA_CORE_CHIPCOMMON);
468 WRITECC32(devinfo, watchdog, 4);
471 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
472 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGADDR,
473 BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL);
474 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA, lsc);
476 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
477 for (i = 0; i < ARRAY_SIZE(cfg_offset); i++) {
478 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGADDR,
480 val = brcmf_pcie_read_reg32(devinfo,
481 BRCMF_PCIE_PCIE2REG_CONFIGDATA);
482 brcmf_dbg(PCIE, "config offset 0x%04x, value 0x%04x\n",
484 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA,
490 static void brcmf_pcie_attach(struct brcmf_pciedev_info *devinfo)
494 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
495 if (brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_INTMASK) != 0)
496 brcmf_pcie_reset_device(devinfo);
497 /* BAR1 window may not be sized properly */
498 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
499 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGADDR, 0x4e0);
500 config = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA);
501 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA, config);
503 device_wakeup_enable(&devinfo->pdev->dev);
507 static int brcmf_pcie_enter_download_state(struct brcmf_pciedev_info *devinfo)
509 brcmf_chip_enter_download(devinfo->ci);
511 if (devinfo->ci->chip == BRCM_CC_43602_CHIP_ID) {
512 brcmf_pcie_select_core(devinfo, BCMA_CORE_ARM_CR4);
513 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKIDX,
515 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKPDA,
517 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKIDX,
519 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKPDA,
526 static int brcmf_pcie_exit_download_state(struct brcmf_pciedev_info *devinfo,
529 struct brcmf_core *core;
531 if (devinfo->ci->chip == BRCM_CC_43602_CHIP_ID) {
532 core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_INTERNAL_MEM);
533 brcmf_chip_resetcore(core, 0, 0, 0);
536 return !brcmf_chip_exit_download(devinfo->ci, resetintr);
541 brcmf_pcie_send_mb_data(struct brcmf_pciedev_info *devinfo, u32 htod_mb_data)
543 struct brcmf_pcie_shared_info *shared;
545 u32 cur_htod_mb_data;
548 shared = &devinfo->shared;
549 addr = shared->htod_mb_data_addr;
550 cur_htod_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
552 if (cur_htod_mb_data != 0)
553 brcmf_dbg(PCIE, "MB transaction is already pending 0x%04x\n",
557 while (cur_htod_mb_data != 0) {
562 cur_htod_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
565 brcmf_pcie_write_tcm32(devinfo, addr, htod_mb_data);
566 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_SBMBX, 1);
567 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_SBMBX, 1);
571 static void brcmf_pcie_handle_mb_data(struct brcmf_pciedev_info *devinfo)
573 struct brcmf_pcie_shared_info *shared;
577 shared = &devinfo->shared;
578 addr = shared->dtoh_mb_data_addr;
579 dtoh_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
584 brcmf_pcie_write_tcm32(devinfo, addr, 0);
586 brcmf_dbg(PCIE, "D2H_MB_DATA: 0x%04x\n", dtoh_mb_data);
587 if (dtoh_mb_data & BRCMF_D2H_DEV_DS_ENTER_REQ) {
588 brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP REQ\n");
589 brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_DS_ACK);
590 brcmf_dbg(PCIE, "D2H_MB_DATA: sent DEEP SLEEP ACK\n");
592 if (dtoh_mb_data & BRCMF_D2H_DEV_DS_EXIT_NOTE)
593 brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP EXIT\n");
594 if (dtoh_mb_data & BRCMF_D2H_DEV_D3_ACK) {
595 brcmf_dbg(PCIE, "D2H_MB_DATA: D3 ACK\n");
596 if (waitqueue_active(&devinfo->mbdata_resp_wait)) {
597 devinfo->mbdata_completed = true;
598 wake_up(&devinfo->mbdata_resp_wait);
604 static void brcmf_pcie_bus_console_init(struct brcmf_pciedev_info *devinfo)
606 struct brcmf_pcie_shared_info *shared;
607 struct brcmf_pcie_console *console;
610 shared = &devinfo->shared;
611 console = &shared->console;
612 addr = shared->tcm_base_address + BRCMF_SHARED_CONSOLE_ADDR_OFFSET;
613 console->base_addr = brcmf_pcie_read_tcm32(devinfo, addr);
615 addr = console->base_addr + BRCMF_CONSOLE_BUFADDR_OFFSET;
616 console->buf_addr = brcmf_pcie_read_tcm32(devinfo, addr);
617 addr = console->base_addr + BRCMF_CONSOLE_BUFSIZE_OFFSET;
618 console->bufsize = brcmf_pcie_read_tcm32(devinfo, addr);
620 brcmf_dbg(PCIE, "Console: base %x, buf %x, size %d\n",
621 console->base_addr, console->buf_addr, console->bufsize);
625 static void brcmf_pcie_bus_console_read(struct brcmf_pciedev_info *devinfo)
627 struct brcmf_pcie_console *console;
632 console = &devinfo->shared.console;
633 addr = console->base_addr + BRCMF_CONSOLE_WRITEIDX_OFFSET;
634 newidx = brcmf_pcie_read_tcm32(devinfo, addr);
635 while (newidx != console->read_idx) {
636 addr = console->buf_addr + console->read_idx;
637 ch = brcmf_pcie_read_tcm8(devinfo, addr);
639 if (console->read_idx == console->bufsize)
640 console->read_idx = 0;
643 console->log_str[console->log_idx] = ch;
646 (console->log_idx == (sizeof(console->log_str) - 2))) {
648 console->log_str[console->log_idx] = ch;
653 console->log_str[console->log_idx] = 0;
654 brcmf_dbg(PCIE, "CONSOLE: %s\n", console->log_str);
655 console->log_idx = 0;
661 static __used void brcmf_pcie_ringbell_v1(struct brcmf_pciedev_info *devinfo)
665 brcmf_dbg(PCIE, "RING !\n");
666 reg_value = brcmf_pcie_read_reg32(devinfo,
667 BRCMF_PCIE_PCIE2REG_MAILBOXINT);
668 reg_value |= BRCMF_PCIE2_INTB;
669 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT,
674 static void brcmf_pcie_ringbell_v2(struct brcmf_pciedev_info *devinfo)
676 brcmf_dbg(PCIE, "RING !\n");
677 /* Any arbitrary value will do, lets use 1 */
678 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_H2D_MAILBOX, 1);
682 static void brcmf_pcie_intr_disable(struct brcmf_pciedev_info *devinfo)
684 if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1)
685 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_INTMASK,
688 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXMASK,
693 static void brcmf_pcie_intr_enable(struct brcmf_pciedev_info *devinfo)
695 if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1)
696 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_INTMASK,
699 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXMASK,
700 BRCMF_PCIE_MB_INT_D2H_DB |
701 BRCMF_PCIE_MB_INT_FN0_0 |
702 BRCMF_PCIE_MB_INT_FN0_1);
706 static irqreturn_t brcmf_pcie_quick_check_isr_v1(int irq, void *arg)
708 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
712 pci_read_config_dword(devinfo->pdev, BRCMF_PCIE_REG_INTSTATUS, &status);
714 brcmf_pcie_intr_disable(devinfo);
715 brcmf_dbg(PCIE, "Enter\n");
716 return IRQ_WAKE_THREAD;
722 static irqreturn_t brcmf_pcie_quick_check_isr_v2(int irq, void *arg)
724 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
726 if (brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT)) {
727 brcmf_pcie_intr_disable(devinfo);
728 brcmf_dbg(PCIE, "Enter\n");
729 return IRQ_WAKE_THREAD;
735 static irqreturn_t brcmf_pcie_isr_thread_v1(int irq, void *arg)
737 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
738 const struct pci_dev *pdev = devinfo->pdev;
741 devinfo->in_irq = true;
743 pci_read_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, &status);
744 brcmf_dbg(PCIE, "Enter %x\n", status);
746 pci_write_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, status);
747 if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
748 brcmf_proto_msgbuf_rx_trigger(&devinfo->pdev->dev);
750 if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
751 brcmf_pcie_intr_enable(devinfo);
752 devinfo->in_irq = false;
757 static irqreturn_t brcmf_pcie_isr_thread_v2(int irq, void *arg)
759 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
762 devinfo->in_irq = true;
763 status = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT);
764 brcmf_dbg(PCIE, "Enter %x\n", status);
766 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT,
768 if (status & (BRCMF_PCIE_MB_INT_FN0_0 |
769 BRCMF_PCIE_MB_INT_FN0_1))
770 brcmf_pcie_handle_mb_data(devinfo);
771 if (status & BRCMF_PCIE_MB_INT_D2H_DB) {
772 if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
773 brcmf_proto_msgbuf_rx_trigger(
774 &devinfo->pdev->dev);
777 brcmf_pcie_bus_console_read(devinfo);
778 if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
779 brcmf_pcie_intr_enable(devinfo);
780 devinfo->in_irq = false;
785 static int brcmf_pcie_request_irq(struct brcmf_pciedev_info *devinfo)
787 struct pci_dev *pdev;
789 pdev = devinfo->pdev;
791 brcmf_pcie_intr_disable(devinfo);
793 brcmf_dbg(PCIE, "Enter\n");
794 /* is it a v1 or v2 implementation */
795 devinfo->irq_requested = false;
796 if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1) {
797 if (request_threaded_irq(pdev->irq,
798 brcmf_pcie_quick_check_isr_v1,
799 brcmf_pcie_isr_thread_v1,
800 IRQF_SHARED, "brcmf_pcie_intr",
802 brcmf_err("Failed to request IRQ %d\n", pdev->irq);
806 if (request_threaded_irq(pdev->irq,
807 brcmf_pcie_quick_check_isr_v2,
808 brcmf_pcie_isr_thread_v2,
809 IRQF_SHARED, "brcmf_pcie_intr",
811 brcmf_err("Failed to request IRQ %d\n", pdev->irq);
815 devinfo->irq_requested = true;
816 devinfo->irq_allocated = true;
821 static void brcmf_pcie_release_irq(struct brcmf_pciedev_info *devinfo)
823 struct pci_dev *pdev;
827 if (!devinfo->irq_allocated)
830 pdev = devinfo->pdev;
832 brcmf_pcie_intr_disable(devinfo);
833 if (!devinfo->irq_requested)
835 devinfo->irq_requested = false;
836 free_irq(pdev->irq, devinfo);
840 while ((devinfo->in_irq) && (count < 20)) {
845 brcmf_err("Still in IRQ (processing) !!!\n");
847 if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1) {
849 pci_read_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, &status);
850 pci_write_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, status);
852 status = brcmf_pcie_read_reg32(devinfo,
853 BRCMF_PCIE_PCIE2REG_MAILBOXINT);
854 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT,
857 devinfo->irq_allocated = false;
861 static int brcmf_pcie_ring_mb_write_rptr(void *ctx)
863 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
864 struct brcmf_pciedev_info *devinfo = ring->devinfo;
865 struct brcmf_commonring *commonring = &ring->commonring;
867 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
870 brcmf_dbg(PCIE, "W r_ptr %d (%d), ring %d\n", commonring->r_ptr,
871 commonring->w_ptr, ring->id);
873 brcmf_pcie_write_tcm16(devinfo, ring->r_idx_addr, commonring->r_ptr);
879 static int brcmf_pcie_ring_mb_write_wptr(void *ctx)
881 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
882 struct brcmf_pciedev_info *devinfo = ring->devinfo;
883 struct brcmf_commonring *commonring = &ring->commonring;
885 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
888 brcmf_dbg(PCIE, "W w_ptr %d (%d), ring %d\n", commonring->w_ptr,
889 commonring->r_ptr, ring->id);
891 brcmf_pcie_write_tcm16(devinfo, ring->w_idx_addr, commonring->w_ptr);
897 static int brcmf_pcie_ring_mb_ring_bell(void *ctx)
899 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
900 struct brcmf_pciedev_info *devinfo = ring->devinfo;
902 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
905 devinfo->ringbell(devinfo);
911 static int brcmf_pcie_ring_mb_update_rptr(void *ctx)
913 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
914 struct brcmf_pciedev_info *devinfo = ring->devinfo;
915 struct brcmf_commonring *commonring = &ring->commonring;
917 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
920 commonring->r_ptr = brcmf_pcie_read_tcm16(devinfo, ring->r_idx_addr);
922 brcmf_dbg(PCIE, "R r_ptr %d (%d), ring %d\n", commonring->r_ptr,
923 commonring->w_ptr, ring->id);
929 static int brcmf_pcie_ring_mb_update_wptr(void *ctx)
931 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
932 struct brcmf_pciedev_info *devinfo = ring->devinfo;
933 struct brcmf_commonring *commonring = &ring->commonring;
935 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
938 commonring->w_ptr = brcmf_pcie_read_tcm16(devinfo, ring->w_idx_addr);
940 brcmf_dbg(PCIE, "R w_ptr %d (%d), ring %d\n", commonring->w_ptr,
941 commonring->r_ptr, ring->id);
948 brcmf_pcie_init_dmabuffer_for_device(struct brcmf_pciedev_info *devinfo,
949 u32 size, u32 tcm_dma_phys_addr,
950 dma_addr_t *dma_handle)
955 ring = dma_alloc_coherent(&devinfo->pdev->dev, size, dma_handle,
960 address = (long long)(long)*dma_handle;
961 brcmf_pcie_write_tcm32(devinfo, tcm_dma_phys_addr,
962 address & 0xffffffff);
963 brcmf_pcie_write_tcm32(devinfo, tcm_dma_phys_addr + 4, address >> 32);
965 memset(ring, 0, size);
971 static struct brcmf_pcie_ringbuf *
972 brcmf_pcie_alloc_dma_and_ring(struct brcmf_pciedev_info *devinfo, u32 ring_id,
973 u32 tcm_ring_phys_addr)
976 dma_addr_t dma_handle;
977 struct brcmf_pcie_ringbuf *ring;
981 size = brcmf_ring_max_item[ring_id] * brcmf_ring_itemsize[ring_id];
982 dma_buf = brcmf_pcie_init_dmabuffer_for_device(devinfo, size,
983 tcm_ring_phys_addr + BRCMF_RING_MEM_BASE_ADDR_OFFSET,
988 addr = tcm_ring_phys_addr + BRCMF_RING_MAX_ITEM_OFFSET;
989 brcmf_pcie_write_tcm16(devinfo, addr, brcmf_ring_max_item[ring_id]);
990 addr = tcm_ring_phys_addr + BRCMF_RING_LEN_ITEMS_OFFSET;
991 brcmf_pcie_write_tcm16(devinfo, addr, brcmf_ring_itemsize[ring_id]);
993 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
995 dma_free_coherent(&devinfo->pdev->dev, size, dma_buf,
999 brcmf_commonring_config(&ring->commonring, brcmf_ring_max_item[ring_id],
1000 brcmf_ring_itemsize[ring_id], dma_buf);
1001 ring->dma_handle = dma_handle;
1002 ring->devinfo = devinfo;
1003 brcmf_commonring_register_cb(&ring->commonring,
1004 brcmf_pcie_ring_mb_ring_bell,
1005 brcmf_pcie_ring_mb_update_rptr,
1006 brcmf_pcie_ring_mb_update_wptr,
1007 brcmf_pcie_ring_mb_write_rptr,
1008 brcmf_pcie_ring_mb_write_wptr, ring);
1014 static void brcmf_pcie_release_ringbuffer(struct device *dev,
1015 struct brcmf_pcie_ringbuf *ring)
1023 dma_buf = ring->commonring.buf_addr;
1025 size = ring->commonring.depth * ring->commonring.item_len;
1026 dma_free_coherent(dev, size, dma_buf, ring->dma_handle);
1032 static void brcmf_pcie_release_ringbuffers(struct brcmf_pciedev_info *devinfo)
1036 for (i = 0; i < BRCMF_NROF_COMMON_MSGRINGS; i++) {
1037 brcmf_pcie_release_ringbuffer(&devinfo->pdev->dev,
1038 devinfo->shared.commonrings[i]);
1039 devinfo->shared.commonrings[i] = NULL;
1041 kfree(devinfo->shared.flowrings);
1042 devinfo->shared.flowrings = NULL;
1046 static int brcmf_pcie_init_ringbuffers(struct brcmf_pciedev_info *devinfo)
1048 struct brcmf_pcie_ringbuf *ring;
1049 struct brcmf_pcie_ringbuf *rings;
1060 ring_addr = devinfo->shared.ring_info_addr;
1061 brcmf_dbg(PCIE, "Base ring addr = 0x%08x\n", ring_addr);
1063 addr = ring_addr + BRCMF_SHARED_RING_D2H_W_IDX_PTR_OFFSET;
1064 d2h_w_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
1065 addr = ring_addr + BRCMF_SHARED_RING_D2H_R_IDX_PTR_OFFSET;
1066 d2h_r_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
1067 addr = ring_addr + BRCMF_SHARED_RING_H2D_W_IDX_PTR_OFFSET;
1068 h2d_w_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
1069 addr = ring_addr + BRCMF_SHARED_RING_H2D_R_IDX_PTR_OFFSET;
1070 h2d_r_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
1072 addr = ring_addr + BRCMF_SHARED_RING_TCM_MEMLOC_OFFSET;
1073 ring_mem_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
1075 for (i = 0; i < BRCMF_NROF_H2D_COMMON_MSGRINGS; i++) {
1076 ring = brcmf_pcie_alloc_dma_and_ring(devinfo, i, ring_mem_ptr);
1079 ring->w_idx_addr = h2d_w_idx_ptr;
1080 ring->r_idx_addr = h2d_r_idx_ptr;
1082 devinfo->shared.commonrings[i] = ring;
1084 h2d_w_idx_ptr += sizeof(u32);
1085 h2d_r_idx_ptr += sizeof(u32);
1086 ring_mem_ptr += BRCMF_RING_MEM_SZ;
1089 for (i = BRCMF_NROF_H2D_COMMON_MSGRINGS;
1090 i < BRCMF_NROF_COMMON_MSGRINGS; i++) {
1091 ring = brcmf_pcie_alloc_dma_and_ring(devinfo, i, ring_mem_ptr);
1094 ring->w_idx_addr = d2h_w_idx_ptr;
1095 ring->r_idx_addr = d2h_r_idx_ptr;
1097 devinfo->shared.commonrings[i] = ring;
1099 d2h_w_idx_ptr += sizeof(u32);
1100 d2h_r_idx_ptr += sizeof(u32);
1101 ring_mem_ptr += BRCMF_RING_MEM_SZ;
1104 addr = ring_addr + BRCMF_SHARED_RING_MAX_SUB_QUEUES;
1105 max_sub_queues = brcmf_pcie_read_tcm16(devinfo, addr);
1106 devinfo->shared.nrof_flowrings =
1107 max_sub_queues - BRCMF_NROF_H2D_COMMON_MSGRINGS;
1108 rings = kcalloc(devinfo->shared.nrof_flowrings, sizeof(*ring),
1113 brcmf_dbg(PCIE, "Nr of flowrings is %d\n",
1114 devinfo->shared.nrof_flowrings);
1116 for (i = 0; i < devinfo->shared.nrof_flowrings; i++) {
1118 ring->devinfo = devinfo;
1119 ring->id = i + BRCMF_NROF_COMMON_MSGRINGS;
1120 brcmf_commonring_register_cb(&ring->commonring,
1121 brcmf_pcie_ring_mb_ring_bell,
1122 brcmf_pcie_ring_mb_update_rptr,
1123 brcmf_pcie_ring_mb_update_wptr,
1124 brcmf_pcie_ring_mb_write_rptr,
1125 brcmf_pcie_ring_mb_write_wptr,
1127 ring->w_idx_addr = h2d_w_idx_ptr;
1128 ring->r_idx_addr = h2d_r_idx_ptr;
1129 h2d_w_idx_ptr += sizeof(u32);
1130 h2d_r_idx_ptr += sizeof(u32);
1132 devinfo->shared.flowrings = rings;
1137 brcmf_err("Allocating commonring buffers failed\n");
1138 brcmf_pcie_release_ringbuffers(devinfo);
1144 brcmf_pcie_release_scratchbuffers(struct brcmf_pciedev_info *devinfo)
1146 if (devinfo->shared.scratch)
1147 dma_free_coherent(&devinfo->pdev->dev,
1148 BRCMF_DMA_D2H_SCRATCH_BUF_LEN,
1149 devinfo->shared.scratch,
1150 devinfo->shared.scratch_dmahandle);
1151 if (devinfo->shared.ringupd)
1152 dma_free_coherent(&devinfo->pdev->dev,
1153 BRCMF_DMA_D2H_RINGUPD_BUF_LEN,
1154 devinfo->shared.ringupd,
1155 devinfo->shared.ringupd_dmahandle);
1158 static int brcmf_pcie_init_scratchbuffers(struct brcmf_pciedev_info *devinfo)
1163 devinfo->shared.scratch = dma_alloc_coherent(&devinfo->pdev->dev,
1164 BRCMF_DMA_D2H_SCRATCH_BUF_LEN,
1165 &devinfo->shared.scratch_dmahandle, GFP_KERNEL);
1166 if (!devinfo->shared.scratch)
1169 memset(devinfo->shared.scratch, 0, BRCMF_DMA_D2H_SCRATCH_BUF_LEN);
1170 brcmf_dma_flush(devinfo->shared.scratch, BRCMF_DMA_D2H_SCRATCH_BUF_LEN);
1172 addr = devinfo->shared.tcm_base_address +
1173 BRCMF_SHARED_DMA_SCRATCH_ADDR_OFFSET;
1174 address = (long long)(long)devinfo->shared.scratch_dmahandle;
1175 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1176 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1177 addr = devinfo->shared.tcm_base_address +
1178 BRCMF_SHARED_DMA_SCRATCH_LEN_OFFSET;
1179 brcmf_pcie_write_tcm32(devinfo, addr, BRCMF_DMA_D2H_SCRATCH_BUF_LEN);
1181 devinfo->shared.ringupd = dma_alloc_coherent(&devinfo->pdev->dev,
1182 BRCMF_DMA_D2H_RINGUPD_BUF_LEN,
1183 &devinfo->shared.ringupd_dmahandle, GFP_KERNEL);
1184 if (!devinfo->shared.ringupd)
1187 memset(devinfo->shared.ringupd, 0, BRCMF_DMA_D2H_RINGUPD_BUF_LEN);
1188 brcmf_dma_flush(devinfo->shared.ringupd, BRCMF_DMA_D2H_RINGUPD_BUF_LEN);
1190 addr = devinfo->shared.tcm_base_address +
1191 BRCMF_SHARED_DMA_RINGUPD_ADDR_OFFSET;
1192 address = (long long)(long)devinfo->shared.ringupd_dmahandle;
1193 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1194 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1195 addr = devinfo->shared.tcm_base_address +
1196 BRCMF_SHARED_DMA_RINGUPD_LEN_OFFSET;
1197 brcmf_pcie_write_tcm32(devinfo, addr, BRCMF_DMA_D2H_RINGUPD_BUF_LEN);
1201 brcmf_err("Allocating scratch buffers failed\n");
1202 brcmf_pcie_release_scratchbuffers(devinfo);
1207 static void brcmf_pcie_down(struct device *dev)
1212 static int brcmf_pcie_tx(struct device *dev, struct sk_buff *skb)
1218 static int brcmf_pcie_tx_ctlpkt(struct device *dev, unsigned char *msg,
1225 static int brcmf_pcie_rx_ctlpkt(struct device *dev, unsigned char *msg,
1232 static struct brcmf_bus_ops brcmf_pcie_bus_ops = {
1233 .txdata = brcmf_pcie_tx,
1234 .stop = brcmf_pcie_down,
1235 .txctl = brcmf_pcie_tx_ctlpkt,
1236 .rxctl = brcmf_pcie_rx_ctlpkt,
1241 brcmf_pcie_init_share_ram_info(struct brcmf_pciedev_info *devinfo,
1244 struct brcmf_pcie_shared_info *shared;
1248 shared = &devinfo->shared;
1249 shared->tcm_base_address = sharedram_addr;
1251 shared->flags = brcmf_pcie_read_tcm32(devinfo, sharedram_addr);
1252 version = shared->flags & BRCMF_PCIE_SHARED_VERSION_MASK;
1253 brcmf_dbg(PCIE, "PCIe protocol version %d\n", version);
1254 if ((version > BRCMF_PCIE_MAX_SHARED_VERSION) ||
1255 (version < BRCMF_PCIE_MIN_SHARED_VERSION)) {
1256 brcmf_err("Unsupported PCIE version %d\n", version);
1259 if (shared->flags & BRCMF_PCIE_SHARED_TXPUSH_SUPPORT) {
1260 brcmf_err("Unsupported legacy TX mode 0x%x\n",
1261 shared->flags & BRCMF_PCIE_SHARED_TXPUSH_SUPPORT);
1265 addr = sharedram_addr + BRCMF_SHARED_MAX_RXBUFPOST_OFFSET;
1266 shared->max_rxbufpost = brcmf_pcie_read_tcm16(devinfo, addr);
1267 if (shared->max_rxbufpost == 0)
1268 shared->max_rxbufpost = BRCMF_DEF_MAX_RXBUFPOST;
1270 addr = sharedram_addr + BRCMF_SHARED_RX_DATAOFFSET_OFFSET;
1271 shared->rx_dataoffset = brcmf_pcie_read_tcm32(devinfo, addr);
1273 addr = sharedram_addr + BRCMF_SHARED_HTOD_MB_DATA_ADDR_OFFSET;
1274 shared->htod_mb_data_addr = brcmf_pcie_read_tcm32(devinfo, addr);
1276 addr = sharedram_addr + BRCMF_SHARED_DTOH_MB_DATA_ADDR_OFFSET;
1277 shared->dtoh_mb_data_addr = brcmf_pcie_read_tcm32(devinfo, addr);
1279 addr = sharedram_addr + BRCMF_SHARED_RING_INFO_ADDR_OFFSET;
1280 shared->ring_info_addr = brcmf_pcie_read_tcm32(devinfo, addr);
1282 brcmf_dbg(PCIE, "max rx buf post %d, rx dataoffset %d\n",
1283 shared->max_rxbufpost, shared->rx_dataoffset);
1285 brcmf_pcie_bus_console_init(devinfo);
1291 static int brcmf_pcie_get_fwnames(struct brcmf_pciedev_info *devinfo)
1295 uint fw_len, nv_len;
1298 brcmf_dbg(PCIE, "Enter, chip 0x%04x chiprev %d\n", devinfo->ci->chip,
1299 devinfo->ci->chiprev);
1301 switch (devinfo->ci->chip) {
1302 case BRCM_CC_43602_CHIP_ID:
1303 fw_name = BRCMF_PCIE_43602_FW_NAME;
1304 nvram_name = BRCMF_PCIE_43602_NVRAM_NAME;
1306 case BRCM_CC_4354_CHIP_ID:
1307 fw_name = BRCMF_PCIE_4354_FW_NAME;
1308 nvram_name = BRCMF_PCIE_4354_NVRAM_NAME;
1310 case BRCM_CC_4356_CHIP_ID:
1311 fw_name = BRCMF_PCIE_4356_FW_NAME;
1312 nvram_name = BRCMF_PCIE_4356_NVRAM_NAME;
1314 case BRCM_CC_43567_CHIP_ID:
1315 case BRCM_CC_43569_CHIP_ID:
1316 case BRCM_CC_43570_CHIP_ID:
1317 fw_name = BRCMF_PCIE_43570_FW_NAME;
1318 nvram_name = BRCMF_PCIE_43570_NVRAM_NAME;
1321 brcmf_err("Unsupported chip 0x%04x\n", devinfo->ci->chip);
1325 fw_len = sizeof(devinfo->fw_name) - 1;
1326 nv_len = sizeof(devinfo->nvram_name) - 1;
1327 /* check if firmware path is provided by module parameter */
1328 if (brcmf_firmware_path[0] != '\0') {
1329 strncpy(devinfo->fw_name, brcmf_firmware_path, fw_len);
1330 strncpy(devinfo->nvram_name, brcmf_firmware_path, nv_len);
1331 fw_len -= strlen(devinfo->fw_name);
1332 nv_len -= strlen(devinfo->nvram_name);
1334 end = brcmf_firmware_path[strlen(brcmf_firmware_path) - 1];
1336 strncat(devinfo->fw_name, "/", fw_len);
1337 strncat(devinfo->nvram_name, "/", nv_len);
1342 strncat(devinfo->fw_name, fw_name, fw_len);
1343 strncat(devinfo->nvram_name, nvram_name, nv_len);
1349 static int brcmf_pcie_download_fw_nvram(struct brcmf_pciedev_info *devinfo,
1350 const struct firmware *fw, void *nvram,
1354 u32 sharedram_addr_written;
1360 devinfo->ringbell = brcmf_pcie_ringbell_v2;
1361 devinfo->generic_corerev = BRCMF_PCIE_GENREV2;
1363 brcmf_dbg(PCIE, "Halt ARM.\n");
1364 err = brcmf_pcie_enter_download_state(devinfo);
1368 brcmf_dbg(PCIE, "Download FW %s\n", devinfo->fw_name);
1369 brcmf_pcie_copy_mem_todev(devinfo, devinfo->ci->rambase,
1370 (void *)fw->data, fw->size);
1372 resetintr = get_unaligned_le32(fw->data);
1373 release_firmware(fw);
1375 /* reset last 4 bytes of RAM address. to be used for shared
1376 * area. This identifies when FW is running
1378 brcmf_pcie_write_ram32(devinfo, devinfo->ci->ramsize - 4, 0);
1381 brcmf_dbg(PCIE, "Download NVRAM %s\n", devinfo->nvram_name);
1382 address = devinfo->ci->rambase + devinfo->ci->ramsize -
1384 brcmf_pcie_copy_mem_todev(devinfo, address, nvram, nvram_len);
1385 brcmf_fw_nvram_free(nvram);
1387 brcmf_dbg(PCIE, "No matching NVRAM file found %s\n",
1388 devinfo->nvram_name);
1391 sharedram_addr_written = brcmf_pcie_read_ram32(devinfo,
1392 devinfo->ci->ramsize -
1394 brcmf_dbg(PCIE, "Bring ARM in running state\n");
1395 err = brcmf_pcie_exit_download_state(devinfo, resetintr);
1399 brcmf_dbg(PCIE, "Wait for FW init\n");
1400 sharedram_addr = sharedram_addr_written;
1401 loop_counter = BRCMF_PCIE_FW_UP_TIMEOUT / 50;
1402 while ((sharedram_addr == sharedram_addr_written) && (loop_counter)) {
1404 sharedram_addr = brcmf_pcie_read_ram32(devinfo,
1405 devinfo->ci->ramsize -
1409 if (sharedram_addr == sharedram_addr_written) {
1410 brcmf_err("FW failed to initialize\n");
1413 brcmf_dbg(PCIE, "Shared RAM addr: 0x%08x\n", sharedram_addr);
1415 return (brcmf_pcie_init_share_ram_info(devinfo, sharedram_addr));
1419 static int brcmf_pcie_get_resource(struct brcmf_pciedev_info *devinfo)
1421 struct pci_dev *pdev;
1423 phys_addr_t bar0_addr, bar1_addr;
1426 pdev = devinfo->pdev;
1428 err = pci_enable_device(pdev);
1430 brcmf_err("pci_enable_device failed err=%d\n", err);
1434 pci_set_master(pdev);
1436 /* Bar-0 mapped address */
1437 bar0_addr = pci_resource_start(pdev, 0);
1438 /* Bar-1 mapped address */
1439 bar1_addr = pci_resource_start(pdev, 2);
1440 /* read Bar-1 mapped memory range */
1441 bar1_size = pci_resource_len(pdev, 2);
1442 if ((bar1_size == 0) || (bar1_addr == 0)) {
1443 brcmf_err("BAR1 Not enabled, device size=%ld, addr=%#016llx\n",
1444 bar1_size, (unsigned long long)bar1_addr);
1448 devinfo->regs = ioremap_nocache(bar0_addr, BRCMF_PCIE_REG_MAP_SIZE);
1449 devinfo->tcm = ioremap_nocache(bar1_addr, BRCMF_PCIE_TCM_MAP_SIZE);
1450 devinfo->tcm_size = BRCMF_PCIE_TCM_MAP_SIZE;
1452 if (!devinfo->regs || !devinfo->tcm) {
1453 brcmf_err("ioremap() failed (%p,%p)\n", devinfo->regs,
1457 brcmf_dbg(PCIE, "Phys addr : reg space = %p base addr %#016llx\n",
1458 devinfo->regs, (unsigned long long)bar0_addr);
1459 brcmf_dbg(PCIE, "Phys addr : mem space = %p base addr %#016llx\n",
1460 devinfo->tcm, (unsigned long long)bar1_addr);
1466 static void brcmf_pcie_release_resource(struct brcmf_pciedev_info *devinfo)
1469 iounmap(devinfo->tcm);
1471 iounmap(devinfo->regs);
1473 pci_disable_device(devinfo->pdev);
1477 static int brcmf_pcie_attach_bus(struct device *dev)
1481 /* Attach to the common driver interface */
1482 ret = brcmf_attach(dev);
1484 brcmf_err("brcmf_attach failed\n");
1486 ret = brcmf_bus_start(dev);
1488 brcmf_err("dongle is not responding\n");
1495 static u32 brcmf_pcie_buscore_prep_addr(const struct pci_dev *pdev, u32 addr)
1499 ret_addr = addr & (BRCMF_PCIE_BAR0_REG_SIZE - 1);
1500 addr &= ~(BRCMF_PCIE_BAR0_REG_SIZE - 1);
1501 pci_write_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, addr);
1507 static u32 brcmf_pcie_buscore_read32(void *ctx, u32 addr)
1509 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1511 addr = brcmf_pcie_buscore_prep_addr(devinfo->pdev, addr);
1512 return brcmf_pcie_read_reg32(devinfo, addr);
1516 static void brcmf_pcie_buscore_write32(void *ctx, u32 addr, u32 value)
1518 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1520 addr = brcmf_pcie_buscore_prep_addr(devinfo->pdev, addr);
1521 brcmf_pcie_write_reg32(devinfo, addr, value);
1525 static int brcmf_pcie_buscoreprep(void *ctx)
1527 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1530 err = brcmf_pcie_get_resource(devinfo);
1532 /* Set CC watchdog to reset all the cores on the chip to bring
1533 * back dongle to a sane state.
1535 brcmf_pcie_buscore_write32(ctx, CORE_CC_REG(SI_ENUM_BASE,
1544 static void brcmf_pcie_buscore_exitdl(void *ctx, struct brcmf_chip *chip,
1547 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1549 brcmf_pcie_write_tcm32(devinfo, 0, rstvec);
1553 static const struct brcmf_buscore_ops brcmf_pcie_buscore_ops = {
1554 .prepare = brcmf_pcie_buscoreprep,
1555 .exit_dl = brcmf_pcie_buscore_exitdl,
1556 .read32 = brcmf_pcie_buscore_read32,
1557 .write32 = brcmf_pcie_buscore_write32,
1560 static void brcmf_pcie_setup(struct device *dev, const struct firmware *fw,
1561 void *nvram, u32 nvram_len)
1563 struct brcmf_bus *bus = dev_get_drvdata(dev);
1564 struct brcmf_pciedev *pcie_bus_dev = bus->bus_priv.pcie;
1565 struct brcmf_pciedev_info *devinfo = pcie_bus_dev->devinfo;
1566 struct brcmf_commonring **flowrings;
1570 brcmf_pcie_attach(devinfo);
1572 ret = brcmf_pcie_download_fw_nvram(devinfo, fw, nvram, nvram_len);
1576 devinfo->state = BRCMFMAC_PCIE_STATE_UP;
1578 ret = brcmf_pcie_init_ringbuffers(devinfo);
1582 ret = brcmf_pcie_init_scratchbuffers(devinfo);
1586 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
1587 ret = brcmf_pcie_request_irq(devinfo);
1591 /* hook the commonrings in the bus structure. */
1592 for (i = 0; i < BRCMF_NROF_COMMON_MSGRINGS; i++)
1593 bus->msgbuf->commonrings[i] =
1594 &devinfo->shared.commonrings[i]->commonring;
1596 flowrings = kcalloc(devinfo->shared.nrof_flowrings, sizeof(flowrings),
1601 for (i = 0; i < devinfo->shared.nrof_flowrings; i++)
1602 flowrings[i] = &devinfo->shared.flowrings[i].commonring;
1603 bus->msgbuf->flowrings = flowrings;
1605 bus->msgbuf->rx_dataoffset = devinfo->shared.rx_dataoffset;
1606 bus->msgbuf->max_rxbufpost = devinfo->shared.max_rxbufpost;
1607 bus->msgbuf->nrof_flowrings = devinfo->shared.nrof_flowrings;
1609 init_waitqueue_head(&devinfo->mbdata_resp_wait);
1611 brcmf_pcie_intr_enable(devinfo);
1612 if (brcmf_pcie_attach_bus(bus->dev) == 0)
1615 brcmf_pcie_bus_console_read(devinfo);
1618 device_release_driver(dev);
1622 brcmf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1625 struct brcmf_pciedev_info *devinfo;
1626 struct brcmf_pciedev *pcie_bus_dev;
1627 struct brcmf_bus *bus;
1629 brcmf_dbg(PCIE, "Enter %x:%x\n", pdev->vendor, pdev->device);
1632 devinfo = kzalloc(sizeof(*devinfo), GFP_KERNEL);
1633 if (devinfo == NULL)
1636 devinfo->pdev = pdev;
1637 pcie_bus_dev = NULL;
1638 devinfo->ci = brcmf_chip_attach(devinfo, &brcmf_pcie_buscore_ops);
1639 if (IS_ERR(devinfo->ci)) {
1640 ret = PTR_ERR(devinfo->ci);
1645 pcie_bus_dev = kzalloc(sizeof(*pcie_bus_dev), GFP_KERNEL);
1646 if (pcie_bus_dev == NULL) {
1651 bus = kzalloc(sizeof(*bus), GFP_KERNEL);
1656 bus->msgbuf = kzalloc(sizeof(*bus->msgbuf), GFP_KERNEL);
1663 /* hook it all together. */
1664 pcie_bus_dev->devinfo = devinfo;
1665 pcie_bus_dev->bus = bus;
1666 bus->dev = &pdev->dev;
1667 bus->bus_priv.pcie = pcie_bus_dev;
1668 bus->ops = &brcmf_pcie_bus_ops;
1669 bus->proto_type = BRCMF_PROTO_MSGBUF;
1670 bus->chip = devinfo->coreid;
1671 dev_set_drvdata(&pdev->dev, bus);
1673 ret = brcmf_pcie_get_fwnames(devinfo);
1677 ret = brcmf_fw_get_firmwares(bus->dev, BRCMF_FW_REQUEST_NVRAM |
1678 BRCMF_FW_REQ_NV_OPTIONAL,
1679 devinfo->fw_name, devinfo->nvram_name,
1687 brcmf_err("failed %x:%x\n", pdev->vendor, pdev->device);
1688 brcmf_pcie_release_resource(devinfo);
1690 brcmf_chip_detach(devinfo->ci);
1691 kfree(pcie_bus_dev);
1698 brcmf_pcie_remove(struct pci_dev *pdev)
1700 struct brcmf_pciedev_info *devinfo;
1701 struct brcmf_bus *bus;
1703 brcmf_dbg(PCIE, "Enter\n");
1705 bus = dev_get_drvdata(&pdev->dev);
1709 devinfo = bus->bus_priv.pcie->devinfo;
1711 devinfo->state = BRCMFMAC_PCIE_STATE_DOWN;
1713 brcmf_pcie_intr_disable(devinfo);
1715 brcmf_detach(&pdev->dev);
1717 kfree(bus->bus_priv.pcie);
1718 kfree(bus->msgbuf->flowrings);
1722 brcmf_pcie_release_irq(devinfo);
1723 brcmf_pcie_release_scratchbuffers(devinfo);
1724 brcmf_pcie_release_ringbuffers(devinfo);
1725 brcmf_pcie_reset_device(devinfo);
1726 brcmf_pcie_release_resource(devinfo);
1729 brcmf_chip_detach(devinfo->ci);
1732 dev_set_drvdata(&pdev->dev, NULL);
1739 static int brcmf_pcie_suspend(struct pci_dev *pdev, pm_message_t state)
1741 struct brcmf_pciedev_info *devinfo;
1742 struct brcmf_bus *bus;
1745 brcmf_dbg(PCIE, "Enter, state=%d, pdev=%p\n", state.event, pdev);
1747 bus = dev_get_drvdata(&pdev->dev);
1748 devinfo = bus->bus_priv.pcie->devinfo;
1750 brcmf_bus_change_state(bus, BRCMF_BUS_DOWN);
1752 devinfo->mbdata_completed = false;
1753 brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_D3_INFORM);
1755 wait_event_timeout(devinfo->mbdata_resp_wait,
1756 devinfo->mbdata_completed,
1757 msecs_to_jiffies(BRCMF_PCIE_MBDATA_TIMEOUT));
1758 if (!devinfo->mbdata_completed) {
1759 brcmf_err("Timeout on response for entering D3 substate\n");
1762 brcmf_pcie_release_irq(devinfo);
1764 err = pci_save_state(pdev);
1766 brcmf_err("pci_save_state failed, err=%d\n", err);
1770 brcmf_chip_detach(devinfo->ci);
1773 brcmf_pcie_remove(pdev);
1775 return pci_prepare_to_sleep(pdev);
1779 static int brcmf_pcie_resume(struct pci_dev *pdev)
1783 brcmf_dbg(PCIE, "Enter, pdev=%p\n", pdev);
1785 err = pci_set_power_state(pdev, PCI_D0);
1787 brcmf_err("pci_set_power_state failed, err=%d\n", err);
1790 pci_restore_state(pdev);
1792 err = brcmf_pcie_probe(pdev, NULL);
1794 brcmf_err("probe after resume failed, err=%d\n", err);
1800 #endif /* CONFIG_PM */
1803 #define BRCMF_PCIE_DEVICE(dev_id) { BRCM_PCIE_VENDOR_ID_BROADCOM, dev_id,\
1804 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_OTHER << 8, 0xffff00, 0 }
1806 static struct pci_device_id brcmf_pcie_devid_table[] = {
1807 BRCMF_PCIE_DEVICE(BRCM_PCIE_4354_DEVICE_ID),
1808 BRCMF_PCIE_DEVICE(BRCM_PCIE_4356_DEVICE_ID),
1809 BRCMF_PCIE_DEVICE(BRCM_PCIE_43567_DEVICE_ID),
1810 BRCMF_PCIE_DEVICE(BRCM_PCIE_43570_DEVICE_ID),
1811 BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_DEVICE_ID),
1812 { /* end: all zeroes */ }
1816 MODULE_DEVICE_TABLE(pci, brcmf_pcie_devid_table);
1819 static struct pci_driver brcmf_pciedrvr = {
1821 .name = KBUILD_MODNAME,
1822 .id_table = brcmf_pcie_devid_table,
1823 .probe = brcmf_pcie_probe,
1824 .remove = brcmf_pcie_remove,
1826 .suspend = brcmf_pcie_suspend,
1827 .resume = brcmf_pcie_resume
1828 #endif /* CONFIG_PM */
1832 void brcmf_pcie_register(void)
1836 brcmf_dbg(PCIE, "Enter\n");
1837 err = pci_register_driver(&brcmf_pciedrvr);
1839 brcmf_err("PCIE driver registration failed, err=%d\n", err);
1843 void brcmf_pcie_exit(void)
1845 brcmf_dbg(PCIE, "Enter\n");
1846 pci_unregister_driver(&brcmf_pciedrvr);