drivers/net/wireless/brcm80211/brcmfmac/pcie.c

   1 /* Copyright (c) 2014 Broadcom Corporation
   2  *
   3  * Permission to use, copy, modify, and/or distribute this software for any
   4  * purpose with or without fee is hereby granted, provided that the above
   5  * copyright notice and this permission notice appear in all copies.
   6  *
   7  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   8  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
   9  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  10  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  11  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  12  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  13  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/module.h>
  18 #include <linux/firmware.h>
  19 #include <linux/pci.h>
  20 #include <linux/vmalloc.h>
  21 #include <linux/delay.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/bcma/bcma.h>
  24 #include <linux/sched.h>
  25 #include <asm/unaligned.h>
  26
  27 #include <soc.h>
  28 #include <chipcommon.h>
  29 #include <brcmu_utils.h>
  30 #include <brcmu_wifi.h>
  31 #include <brcm_hw_ids.h>
  32
  33 #include "debug.h"
  34 #include "bus.h"
  35 #include "commonring.h"
  36 #include "msgbuf.h"
  37 #include "pcie.h"
  38 #include "firmware.h"
  39 #include "chip.h"
  40
  41
  42 enum brcmf_pcie_state {
  43         BRCMFMAC_PCIE_STATE_DOWN,
  44         BRCMFMAC_PCIE_STATE_UP
  45 };
  46
  47
  48 #define BRCMF_PCIE_43602_FW_NAME                "brcm/brcmfmac43602-pcie.bin"
  49 #define BRCMF_PCIE_43602_NVRAM_NAME             "brcm/brcmfmac43602-pcie.txt"
  50 #define BRCMF_PCIE_4356_FW_NAME                 "brcm/brcmfmac4356-pcie.bin"
  51 #define BRCMF_PCIE_4356_NVRAM_NAME              "brcm/brcmfmac4356-pcie.txt"
  52 #define BRCMF_PCIE_43570_FW_NAME                "brcm/brcmfmac43570-pcie.bin"
  53 #define BRCMF_PCIE_43570_NVRAM_NAME             "brcm/brcmfmac43570-pcie.txt"
  54 #define BRCMF_PCIE_4358_FW_NAME                 "brcm/brcmfmac4358-pcie.bin"
  55 #define BRCMF_PCIE_4358_NVRAM_NAME              "brcm/brcmfmac4358-pcie.txt"
  56
  57 #define BRCMF_PCIE_FW_UP_TIMEOUT                2000 /* msec */
  58
  59 #define BRCMF_PCIE_TCM_MAP_SIZE                 (4096 * 1024)
  60 #define BRCMF_PCIE_REG_MAP_SIZE                 (32 * 1024)
  61
  62 /* backplane addres space accessed by BAR0 */
  63 #define BRCMF_PCIE_BAR0_WINDOW                  0x80
  64 #define BRCMF_PCIE_BAR0_REG_SIZE                0x1000
  65 #define BRCMF_PCIE_BAR0_WRAPPERBASE             0x70
  66
  67 #define BRCMF_PCIE_BAR0_WRAPBASE_DMP_OFFSET     0x1000
  68 #define BRCMF_PCIE_BARO_PCIE_ENUM_OFFSET        0x2000
  69
  70 #define BRCMF_PCIE_ARMCR4REG_BANKIDX            0x40
  71 #define BRCMF_PCIE_ARMCR4REG_BANKPDA            0x4C
  72
  73 #define BRCMF_PCIE_REG_INTSTATUS                0x90
  74 #define BRCMF_PCIE_REG_INTMASK                  0x94
  75 #define BRCMF_PCIE_REG_SBMBX                    0x98
  76
  77 #define BRCMF_PCIE_PCIE2REG_INTMASK             0x24
  78 #define BRCMF_PCIE_PCIE2REG_MAILBOXINT          0x48
  79 #define BRCMF_PCIE_PCIE2REG_MAILBOXMASK         0x4C
  80 #define BRCMF_PCIE_PCIE2REG_CONFIGADDR          0x120
  81 #define BRCMF_PCIE_PCIE2REG_CONFIGDATA          0x124
  82 #define BRCMF_PCIE_PCIE2REG_H2D_MAILBOX         0x140
  83
  84 #define BRCMF_PCIE_GENREV1                      1
  85 #define BRCMF_PCIE_GENREV2                      2
  86
  87 #define BRCMF_PCIE2_INTA                        0x01
  88 #define BRCMF_PCIE2_INTB                        0x02
  89
  90 #define BRCMF_PCIE_INT_0                        0x01
  91 #define BRCMF_PCIE_INT_1                        0x02
  92 #define BRCMF_PCIE_INT_DEF                      (BRCMF_PCIE_INT_0 | \
  93                                                  BRCMF_PCIE_INT_1)
  94
  95 #define BRCMF_PCIE_MB_INT_FN0_0                 0x0100
  96 #define BRCMF_PCIE_MB_INT_FN0_1                 0x0200
  97 #define BRCMF_PCIE_MB_INT_D2H0_DB0              0x10000
  98 #define BRCMF_PCIE_MB_INT_D2H0_DB1              0x20000
  99 #define BRCMF_PCIE_MB_INT_D2H1_DB0              0x40000
 100 #define BRCMF_PCIE_MB_INT_D2H1_DB1              0x80000
 101 #define BRCMF_PCIE_MB_INT_D2H2_DB0              0x100000
 102 #define BRCMF_PCIE_MB_INT_D2H2_DB1              0x200000
 103 #define BRCMF_PCIE_MB_INT_D2H3_DB0              0x400000
 104 #define BRCMF_PCIE_MB_INT_D2H3_DB1              0x800000
 105
 106 #define BRCMF_PCIE_MB_INT_D2H_DB                (BRCMF_PCIE_MB_INT_D2H0_DB0 | \
 107                                                  BRCMF_PCIE_MB_INT_D2H0_DB1 | \
 108                                                  BRCMF_PCIE_MB_INT_D2H1_DB0 | \
 109                                                  BRCMF_PCIE_MB_INT_D2H1_DB1 | \
 110                                                  BRCMF_PCIE_MB_INT_D2H2_DB0 | \
 111                                                  BRCMF_PCIE_MB_INT_D2H2_DB1 | \
 112                                                  BRCMF_PCIE_MB_INT_D2H3_DB0 | \
 113                                                  BRCMF_PCIE_MB_INT_D2H3_DB1)
 114
 115 #define BRCMF_PCIE_MIN_SHARED_VERSION           5
 116 #define BRCMF_PCIE_MAX_SHARED_VERSION           5
 117 #define BRCMF_PCIE_SHARED_VERSION_MASK          0x00FF
 118 #define BRCMF_PCIE_SHARED_DMA_INDEX             0x10000
 119 #define BRCMF_PCIE_SHARED_DMA_2B_IDX            0x100000
 120
 121 #define BRCMF_PCIE_FLAGS_HTOD_SPLIT             0x4000
 122 #define BRCMF_PCIE_FLAGS_DTOH_SPLIT             0x8000
 123
 124 #define BRCMF_SHARED_MAX_RXBUFPOST_OFFSET       34
 125 #define BRCMF_SHARED_RING_BASE_OFFSET           52
 126 #define BRCMF_SHARED_RX_DATAOFFSET_OFFSET       36
 127 #define BRCMF_SHARED_CONSOLE_ADDR_OFFSET        20
 128 #define BRCMF_SHARED_HTOD_MB_DATA_ADDR_OFFSET   40
 129 #define BRCMF_SHARED_DTOH_MB_DATA_ADDR_OFFSET   44
 130 #define BRCMF_SHARED_RING_INFO_ADDR_OFFSET      48
 131 #define BRCMF_SHARED_DMA_SCRATCH_LEN_OFFSET     52
 132 #define BRCMF_SHARED_DMA_SCRATCH_ADDR_OFFSET    56
 133 #define BRCMF_SHARED_DMA_RINGUPD_LEN_OFFSET     64
 134 #define BRCMF_SHARED_DMA_RINGUPD_ADDR_OFFSET    68
 135
 136 #define BRCMF_RING_H2D_RING_COUNT_OFFSET        0
 137 #define BRCMF_RING_D2H_RING_COUNT_OFFSET        1
 138 #define BRCMF_RING_H2D_RING_MEM_OFFSET          4
 139 #define BRCMF_RING_H2D_RING_STATE_OFFSET        8
 140
 141 #define BRCMF_RING_MEM_BASE_ADDR_OFFSET         8
 142 #define BRCMF_RING_MAX_ITEM_OFFSET              4
 143 #define BRCMF_RING_LEN_ITEMS_OFFSET             6
 144 #define BRCMF_RING_MEM_SZ                       16
 145 #define BRCMF_RING_STATE_SZ                     8
 146
 147 #define BRCMF_SHARED_RING_H2D_W_IDX_PTR_OFFSET  4
 148 #define BRCMF_SHARED_RING_H2D_R_IDX_PTR_OFFSET  8
 149 #define BRCMF_SHARED_RING_D2H_W_IDX_PTR_OFFSET  12
 150 #define BRCMF_SHARED_RING_D2H_R_IDX_PTR_OFFSET  16
 151 #define BRCMF_SHARED_RING_H2D_WP_HADDR_OFFSET   20
 152 #define BRCMF_SHARED_RING_H2D_RP_HADDR_OFFSET   28
 153 #define BRCMF_SHARED_RING_D2H_WP_HADDR_OFFSET   36
 154 #define BRCMF_SHARED_RING_D2H_RP_HADDR_OFFSET   44
 155 #define BRCMF_SHARED_RING_TCM_MEMLOC_OFFSET     0
 156 #define BRCMF_SHARED_RING_MAX_SUB_QUEUES        52
 157
 158 #define BRCMF_DEF_MAX_RXBUFPOST                 255
 159
 160 #define BRCMF_CONSOLE_BUFADDR_OFFSET            8
 161 #define BRCMF_CONSOLE_BUFSIZE_OFFSET            12
 162 #define BRCMF_CONSOLE_WRITEIDX_OFFSET           16
 163
 164 #define BRCMF_DMA_D2H_SCRATCH_BUF_LEN           8
 165 #define BRCMF_DMA_D2H_RINGUPD_BUF_LEN           1024
 166
 167 #define BRCMF_D2H_DEV_D3_ACK                    0x00000001
 168 #define BRCMF_D2H_DEV_DS_ENTER_REQ              0x00000002
 169 #define BRCMF_D2H_DEV_DS_EXIT_NOTE              0x00000004
 170
 171 #define BRCMF_H2D_HOST_D3_INFORM                0x00000001
 172 #define BRCMF_H2D_HOST_DS_ACK                   0x00000002
 173 #define BRCMF_H2D_HOST_D0_INFORM_IN_USE         0x00000008
 174 #define BRCMF_H2D_HOST_D0_INFORM                0x00000010
 175
 176 #define BRCMF_PCIE_MBDATA_TIMEOUT               2000
 177
 178 #define BRCMF_PCIE_CFGREG_STATUS_CMD            0x4
 179 #define BRCMF_PCIE_CFGREG_PM_CSR                0x4C
 180 #define BRCMF_PCIE_CFGREG_MSI_CAP               0x58
 181 #define BRCMF_PCIE_CFGREG_MSI_ADDR_L            0x5C
 182 #define BRCMF_PCIE_CFGREG_MSI_ADDR_H            0x60
 183 #define BRCMF_PCIE_CFGREG_MSI_DATA              0x64
 184 #define BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL      0xBC
 185 #define BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2     0xDC
 186 #define BRCMF_PCIE_CFGREG_RBAR_CTRL             0x228
 187 #define BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1        0x248
 188 #define BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG       0x4E0
 189 #define BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG       0x4F4
 190 #define BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB   3
 191
 192
 193 MODULE_FIRMWARE(BRCMF_PCIE_43602_FW_NAME);
 194 MODULE_FIRMWARE(BRCMF_PCIE_43602_NVRAM_NAME);
 195 MODULE_FIRMWARE(BRCMF_PCIE_4356_FW_NAME);
 196 MODULE_FIRMWARE(BRCMF_PCIE_4356_NVRAM_NAME);
 197 MODULE_FIRMWARE(BRCMF_PCIE_43570_FW_NAME);
 198 MODULE_FIRMWARE(BRCMF_PCIE_43570_NVRAM_NAME);
 199 MODULE_FIRMWARE(BRCMF_PCIE_4358_FW_NAME);
 200 MODULE_FIRMWARE(BRCMF_PCIE_4358_NVRAM_NAME);
 201
 202
 203 struct brcmf_pcie_console {
 204         u32 base_addr;
 205         u32 buf_addr;
 206         u32 bufsize;
 207         u32 read_idx;
 208         u8 log_str[256];
 209         u8 log_idx;
 210 };
 211
 212 struct brcmf_pcie_shared_info {
 213         u32 tcm_base_address;
 214         u32 flags;
 215         struct brcmf_pcie_ringbuf *commonrings[BRCMF_NROF_COMMON_MSGRINGS];
 216         struct brcmf_pcie_ringbuf *flowrings;
 217         u16 max_rxbufpost;
 218         u32 nrof_flowrings;
 219         u32 rx_dataoffset;
 220         u32 htod_mb_data_addr;
 221         u32 dtoh_mb_data_addr;
 222         u32 ring_info_addr;
 223         struct brcmf_pcie_console console;
 224         void *scratch;
 225         dma_addr_t scratch_dmahandle;
 226         void *ringupd;
 227         dma_addr_t ringupd_dmahandle;
 228 };
 229
 230 struct brcmf_pcie_core_info {
 231         u32 base;
 232         u32 wrapbase;
 233 };
 234
 235 struct brcmf_pciedev_info {
 236         enum brcmf_pcie_state state;
 237         bool in_irq;
 238         bool irq_requested;
 239         struct pci_dev *pdev;
 240         char fw_name[BRCMF_FW_PATH_LEN + BRCMF_FW_NAME_LEN];
 241         char nvram_name[BRCMF_FW_PATH_LEN + BRCMF_FW_NAME_LEN];
 242         void __iomem *regs;
 243         void __iomem *tcm;
 244         u32 tcm_size;
 245         u32 ram_base;
 246         u32 ram_size;
 247         struct brcmf_chip *ci;
 248         u32 coreid;
 249         u32 generic_corerev;
 250         struct brcmf_pcie_shared_info shared;
 251         void (*ringbell)(struct brcmf_pciedev_info *devinfo);
 252         wait_queue_head_t mbdata_resp_wait;
 253         bool mbdata_completed;
 254         bool irq_allocated;
 255         bool wowl_enabled;
 256         u8 dma_idx_sz;
 257         void *idxbuf;
 258         u32 idxbuf_sz;
 259         dma_addr_t idxbuf_dmahandle;
 260         u16 (*read_ptr)(struct brcmf_pciedev_info *devinfo, u32 mem_offset);
 261         void (*write_ptr)(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 262                           u16 value);
 263 };
 264
 265 struct brcmf_pcie_ringbuf {
 266         struct brcmf_commonring commonring;
 267         dma_addr_t dma_handle;
 268         u32 w_idx_addr;
 269         u32 r_idx_addr;
 270         struct brcmf_pciedev_info *devinfo;
 271         u8 id;
 272 };
 273
 274
 275 static const u32 brcmf_ring_max_item[BRCMF_NROF_COMMON_MSGRINGS] = {
 276         BRCMF_H2D_MSGRING_CONTROL_SUBMIT_MAX_ITEM,
 277         BRCMF_H2D_MSGRING_RXPOST_SUBMIT_MAX_ITEM,
 278         BRCMF_D2H_MSGRING_CONTROL_COMPLETE_MAX_ITEM,
 279         BRCMF_D2H_MSGRING_TX_COMPLETE_MAX_ITEM,
 280         BRCMF_D2H_MSGRING_RX_COMPLETE_MAX_ITEM
 281 };
 282
 283 static const u32 brcmf_ring_itemsize[BRCMF_NROF_COMMON_MSGRINGS] = {
 284         BRCMF_H2D_MSGRING_CONTROL_SUBMIT_ITEMSIZE,
 285         BRCMF_H2D_MSGRING_RXPOST_SUBMIT_ITEMSIZE,
 286         BRCMF_D2H_MSGRING_CONTROL_COMPLETE_ITEMSIZE,
 287         BRCMF_D2H_MSGRING_TX_COMPLETE_ITEMSIZE,
 288         BRCMF_D2H_MSGRING_RX_COMPLETE_ITEMSIZE
 289 };
 290
 291
 292 static u32
 293 brcmf_pcie_read_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset)
 294 {
 295         void __iomem *address = devinfo->regs + reg_offset;
 296
 297         return (ioread32(address));
 298 }
 299
 300
 301 static void
 302 brcmf_pcie_write_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset,
 303                        u32 value)
 304 {
 305         void __iomem *address = devinfo->regs + reg_offset;
 306
 307         iowrite32(value, address);
 308 }
 309
 310
 311 static u8
 312 brcmf_pcie_read_tcm8(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
 313 {
 314         void __iomem *address = devinfo->tcm + mem_offset;
 315
 316         return (ioread8(address));
 317 }
 318
 319
 320 static u16
 321 brcmf_pcie_read_tcm16(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
 322 {
 323         void __iomem *address = devinfo->tcm + mem_offset;
 324
 325         return (ioread16(address));
 326 }
 327
 328
 329 static void
 330 brcmf_pcie_write_tcm16(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 331                        u16 value)
 332 {
 333         void __iomem *address = devinfo->tcm + mem_offset;
 334
 335         iowrite16(value, address);
 336 }
 337
 338
 339 static u16
 340 brcmf_pcie_read_idx(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
 341 {
 342         u16 *address = devinfo->idxbuf + mem_offset;
 343
 344         return (*(address));
 345 }
 346
 347
 348 static void
 349 brcmf_pcie_write_idx(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 350                      u16 value)
 351 {
 352         u16 *address = devinfo->idxbuf + mem_offset;
 353
 354         *(address) = value;
 355 }
 356
 357
 358 static u32
 359 brcmf_pcie_read_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
 360 {
 361         void __iomem *address = devinfo->tcm + mem_offset;
 362
 363         return (ioread32(address));
 364 }
 365
 366
 367 static void
 368 brcmf_pcie_write_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 369                        u32 value)
 370 {
 371         void __iomem *address = devinfo->tcm + mem_offset;
 372
 373         iowrite32(value, address);
 374 }
 375
 376
 377 static u32
 378 brcmf_pcie_read_ram32(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
 379 {
 380         void __iomem *addr = devinfo->tcm + devinfo->ci->rambase + mem_offset;
 381
 382         return (ioread32(addr));
 383 }
 384
 385
 386 static void
 387 brcmf_pcie_write_ram32(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 388                        u32 value)
 389 {
 390         void __iomem *addr = devinfo->tcm + devinfo->ci->rambase + mem_offset;
 391
 392         iowrite32(value, addr);
 393 }
 394
 395
 396 static void
 397 brcmf_pcie_copy_mem_todev(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 398                           void *srcaddr, u32 len)
 399 {
 400         void __iomem *address = devinfo->tcm + mem_offset;
 401         __le32 *src32;
 402         __le16 *src16;
 403         u8 *src8;
 404
 405         if (((ulong)address & 4) || ((ulong)srcaddr & 4) || (len & 4)) {
 406                 if (((ulong)address & 2) || ((ulong)srcaddr & 2) || (len & 2)) {
 407                         src8 = (u8 *)srcaddr;
 408                         while (len) {
 409                                 iowrite8(*src8, address);
 410                                 address++;
 411                                 src8++;
 412                                 len--;
 413                         }
 414                 } else {
 415                         len = len / 2;
 416                         src16 = (__le16 *)srcaddr;
 417                         while (len) {
 418                                 iowrite16(le16_to_cpu(*src16), address);
 419                                 address += 2;
 420                                 src16++;
 421                                 len--;
 422                         }
 423                 }
 424         } else {
 425                 len = len / 4;
 426                 src32 = (__le32 *)srcaddr;
 427                 while (len) {
 428                         iowrite32(le32_to_cpu(*src32), address);
 429                         address += 4;
 430                         src32++;
 431                         len--;
 432                 }
 433         }
 434 }
 435
 436
 437 #define WRITECC32(devinfo, reg, value) brcmf_pcie_write_reg32(devinfo, \
 438                 CHIPCREGOFFS(reg), value)
 439
 440
 441 static void
 442 brcmf_pcie_select_core(struct brcmf_pciedev_info *devinfo, u16 coreid)
 443 {
 444         const struct pci_dev *pdev = devinfo->pdev;
 445         struct brcmf_core *core;
 446         u32 bar0_win;
 447
 448         core = brcmf_chip_get_core(devinfo->ci, coreid);
 449         if (core) {
 450                 bar0_win = core->base;
 451                 pci_write_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, bar0_win);
 452                 if (pci_read_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW,
 453                                           &bar0_win) == 0) {
 454                         if (bar0_win != core->base) {
 455                                 bar0_win = core->base;
 456                                 pci_write_config_dword(pdev,
 457                                                        BRCMF_PCIE_BAR0_WINDOW,
 458                                                        bar0_win);
 459                         }
 460                 }
 461         } else {
 462                 brcmf_err("Unsupported core selected %x\n", coreid);
 463         }
 464 }
 465
 466
 467 static void brcmf_pcie_reset_device(struct brcmf_pciedev_info *devinfo)
 468 {
 469         u16 cfg_offset[] = { BRCMF_PCIE_CFGREG_STATUS_CMD,
 470                              BRCMF_PCIE_CFGREG_PM_CSR,
 471                              BRCMF_PCIE_CFGREG_MSI_CAP,
 472                              BRCMF_PCIE_CFGREG_MSI_ADDR_L,
 473                              BRCMF_PCIE_CFGREG_MSI_ADDR_H,
 474                              BRCMF_PCIE_CFGREG_MSI_DATA,
 475                              BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2,
 476                              BRCMF_PCIE_CFGREG_RBAR_CTRL,
 477                              BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1,
 478                              BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG,
 479                              BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG };
 480         u32 i;
 481         u32 val;
 482         u32 lsc;
 483
 484         if (!devinfo->ci)
 485                 return;
 486
 487         brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
 488         brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGADDR,
 489                                BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL);
 490         lsc = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA);
 491         val = lsc & (~BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB);
 492         brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA, val);
 493
 494         brcmf_pcie_select_core(devinfo, BCMA_CORE_CHIPCOMMON);
 495         WRITECC32(devinfo, watchdog, 4);
 496         msleep(100);
 497
 498         brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
 499         brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGADDR,
 500                                BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL);
 501         brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA, lsc);
 502
 503         brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
 504         for (i = 0; i < ARRAY_SIZE(cfg_offset); i++) {
 505                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGADDR,
 506                                        cfg_offset[i]);
 507                 val = brcmf_pcie_read_reg32(devinfo,
 508                                             BRCMF_PCIE_PCIE2REG_CONFIGDATA);
 509                 brcmf_dbg(PCIE, "config offset 0x%04x, value 0x%04x\n",
 510                           cfg_offset[i], val);
 511                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA,
 512                                        val);
 513         }
 514 }
 515
 516
 517 static void brcmf_pcie_attach(struct brcmf_pciedev_info *devinfo)
 518 {
 519         u32 config;
 520
 521         brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
 522         if (brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_INTMASK) != 0)
 523                 brcmf_pcie_reset_device(devinfo);
 524         /* BAR1 window may not be sized properly */
 525         brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
 526         brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGADDR, 0x4e0);
 527         config = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA);
 528         brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA, config);
 529
 530         device_wakeup_enable(&devinfo->pdev->dev);
 531 }
 532
 533
 534 static int brcmf_pcie_enter_download_state(struct brcmf_pciedev_info *devinfo)
 535 {
 536         if (devinfo->ci->chip == BRCM_CC_43602_CHIP_ID) {
 537                 brcmf_pcie_select_core(devinfo, BCMA_CORE_ARM_CR4);
 538                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKIDX,
 539                                        5);
 540                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKPDA,
 541                                        0);
 542                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKIDX,
 543                                        7);
 544                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKPDA,
 545                                        0);
 546         }
 547         return 0;
 548 }
 549
 550
 551 static int brcmf_pcie_exit_download_state(struct brcmf_pciedev_info *devinfo,
 552                                           u32 resetintr)
 553 {
 554         struct brcmf_core *core;
 555
 556         if (devinfo->ci->chip == BRCM_CC_43602_CHIP_ID) {
 557                 core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_INTERNAL_MEM);
 558                 brcmf_chip_resetcore(core, 0, 0, 0);
 559         }
 560
 561         return !brcmf_chip_set_active(devinfo->ci, resetintr);
 562 }
 563
 564
 565 static int
 566 brcmf_pcie_send_mb_data(struct brcmf_pciedev_info *devinfo, u32 htod_mb_data)
 567 {
 568         struct brcmf_pcie_shared_info *shared;
 569         u32 addr;
 570         u32 cur_htod_mb_data;
 571         u32 i;
 572
 573         shared = &devinfo->shared;
 574         addr = shared->htod_mb_data_addr;
 575         cur_htod_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
 576
 577         if (cur_htod_mb_data != 0)
 578                 brcmf_dbg(PCIE, "MB transaction is already pending 0x%04x\n",
 579                           cur_htod_mb_data);
 580
 581         i = 0;
 582         while (cur_htod_mb_data != 0) {
 583                 msleep(10);
 584                 i++;
 585                 if (i > 100)
 586                         return -EIO;
 587                 cur_htod_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
 588         }
 589
 590         brcmf_pcie_write_tcm32(devinfo, addr, htod_mb_data);
 591         pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_SBMBX, 1);
 592         pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_SBMBX, 1);
 593
 594         return 0;
 595 }
 596
 597
 598 static void brcmf_pcie_handle_mb_data(struct brcmf_pciedev_info *devinfo)
 599 {
 600         struct brcmf_pcie_shared_info *shared;
 601         u32 addr;
 602         u32 dtoh_mb_data;
 603
 604         shared = &devinfo->shared;
 605         addr = shared->dtoh_mb_data_addr;
 606         dtoh_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
 607
 608         if (!dtoh_mb_data)
 609                 return;
 610
 611         brcmf_pcie_write_tcm32(devinfo, addr, 0);
 612
 613         brcmf_dbg(PCIE, "D2H_MB_DATA: 0x%04x\n", dtoh_mb_data);
 614         if (dtoh_mb_data & BRCMF_D2H_DEV_DS_ENTER_REQ)  {
 615                 brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP REQ\n");
 616                 brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_DS_ACK);
 617                 brcmf_dbg(PCIE, "D2H_MB_DATA: sent DEEP SLEEP ACK\n");
 618         }
 619         if (dtoh_mb_data & BRCMF_D2H_DEV_DS_EXIT_NOTE)
 620                 brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP EXIT\n");
 621         if (dtoh_mb_data & BRCMF_D2H_DEV_D3_ACK) {
 622                 brcmf_dbg(PCIE, "D2H_MB_DATA: D3 ACK\n");
 623                 if (waitqueue_active(&devinfo->mbdata_resp_wait)) {
 624                         devinfo->mbdata_completed = true;
 625                         wake_up(&devinfo->mbdata_resp_wait);
 626                 }
 627         }
 628 }
 629
 630
 631 static void brcmf_pcie_bus_console_init(struct brcmf_pciedev_info *devinfo)
 632 {
 633         struct brcmf_pcie_shared_info *shared;
 634         struct brcmf_pcie_console *console;
 635         u32 addr;
 636
 637         shared = &devinfo->shared;
 638         console = &shared->console;
 639         addr = shared->tcm_base_address + BRCMF_SHARED_CONSOLE_ADDR_OFFSET;
 640         console->base_addr = brcmf_pcie_read_tcm32(devinfo, addr);
 641
 642         addr = console->base_addr + BRCMF_CONSOLE_BUFADDR_OFFSET;
 643         console->buf_addr = brcmf_pcie_read_tcm32(devinfo, addr);
 644         addr = console->base_addr + BRCMF_CONSOLE_BUFSIZE_OFFSET;
 645         console->bufsize = brcmf_pcie_read_tcm32(devinfo, addr);
 646
 647         brcmf_dbg(PCIE, "Console: base %x, buf %x, size %d\n",
 648                   console->base_addr, console->buf_addr, console->bufsize);
 649 }
 650
 651
 652 static void brcmf_pcie_bus_console_read(struct brcmf_pciedev_info *devinfo)
 653 {
 654         struct brcmf_pcie_console *console;
 655         u32 addr;
 656         u8 ch;
 657         u32 newidx;
 658
 659         console = &devinfo->shared.console;
 660         addr = console->base_addr + BRCMF_CONSOLE_WRITEIDX_OFFSET;
 661         newidx = brcmf_pcie_read_tcm32(devinfo, addr);
 662         while (newidx != console->read_idx) {
 663                 addr = console->buf_addr + console->read_idx;
 664                 ch = brcmf_pcie_read_tcm8(devinfo, addr);
 665                 console->read_idx++;
 666                 if (console->read_idx == console->bufsize)
 667                         console->read_idx = 0;
 668                 if (ch == '\r')
 669                         continue;
 670                 console->log_str[console->log_idx] = ch;
 671                 console->log_idx++;
 672                 if ((ch != '\n') &&
 673                     (console->log_idx == (sizeof(console->log_str) - 2))) {
 674                         ch = '\n';
 675                         console->log_str[console->log_idx] = ch;
 676                         console->log_idx++;
 677                 }
 678                 if (ch == '\n') {
 679                         console->log_str[console->log_idx] = 0;
 680                         brcmf_dbg(PCIE, "CONSOLE: %s", console->log_str);
 681                         console->log_idx = 0;
 682                 }
 683         }
 684 }
 685
 686
 687 static __used void brcmf_pcie_ringbell_v1(struct brcmf_pciedev_info *devinfo)
 688 {
 689         u32 reg_value;
 690
 691         brcmf_dbg(PCIE, "RING !\n");
 692         reg_value = brcmf_pcie_read_reg32(devinfo,
 693                                           BRCMF_PCIE_PCIE2REG_MAILBOXINT);
 694         reg_value |= BRCMF_PCIE2_INTB;
 695         brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT,
 696                                reg_value);
 697 }
 698
 699
 700 static void brcmf_pcie_ringbell_v2(struct brcmf_pciedev_info *devinfo)
 701 {
 702         brcmf_dbg(PCIE, "RING !\n");
 703         /* Any arbitrary value will do, lets use 1 */
 704         brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_H2D_MAILBOX, 1);
 705 }
 706
 707
 708 static void brcmf_pcie_intr_disable(struct brcmf_pciedev_info *devinfo)
 709 {
 710         if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1)
 711                 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_INTMASK,
 712                                        0);
 713         else
 714                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXMASK,
 715                                        0);
 716 }
 717
 718
 719 static void brcmf_pcie_intr_enable(struct brcmf_pciedev_info *devinfo)
 720 {
 721         if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1)
 722                 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_INTMASK,
 723                                        BRCMF_PCIE_INT_DEF);
 724         else
 725                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXMASK,
 726                                        BRCMF_PCIE_MB_INT_D2H_DB |
 727                                        BRCMF_PCIE_MB_INT_FN0_0 |
 728                                        BRCMF_PCIE_MB_INT_FN0_1);
 729 }
 730
 731
 732 static irqreturn_t brcmf_pcie_quick_check_isr_v1(int irq, void *arg)
 733 {
 734         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
 735         u32 status;
 736
 737         status = 0;
 738         pci_read_config_dword(devinfo->pdev, BRCMF_PCIE_REG_INTSTATUS, &status);
 739         if (status) {
 740                 brcmf_pcie_intr_disable(devinfo);
 741                 brcmf_dbg(PCIE, "Enter\n");
 742                 return IRQ_WAKE_THREAD;
 743         }
 744         return IRQ_NONE;
 745 }
 746
 747
 748 static irqreturn_t brcmf_pcie_quick_check_isr_v2(int irq, void *arg)
 749 {
 750         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
 751
 752         if (brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT)) {
 753                 brcmf_pcie_intr_disable(devinfo);
 754                 brcmf_dbg(PCIE, "Enter\n");
 755                 return IRQ_WAKE_THREAD;
 756         }
 757         return IRQ_NONE;
 758 }
 759
 760
 761 static irqreturn_t brcmf_pcie_isr_thread_v1(int irq, void *arg)
 762 {
 763         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
 764         const struct pci_dev *pdev = devinfo->pdev;
 765         u32 status;
 766
 767         devinfo->in_irq = true;
 768         status = 0;
 769         pci_read_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, &status);
 770         brcmf_dbg(PCIE, "Enter %x\n", status);
 771         if (status) {
 772                 pci_write_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, status);
 773                 if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
 774                         brcmf_proto_msgbuf_rx_trigger(&devinfo->pdev->dev);
 775         }
 776         if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
 777                 brcmf_pcie_intr_enable(devinfo);
 778         devinfo->in_irq = false;
 779         return IRQ_HANDLED;
 780 }
 781
 782
 783 static irqreturn_t brcmf_pcie_isr_thread_v2(int irq, void *arg)
 784 {
 785         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
 786         u32 status;
 787
 788         devinfo->in_irq = true;
 789         status = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT);
 790         brcmf_dbg(PCIE, "Enter %x\n", status);
 791         if (status) {
 792                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT,
 793                                        status);
 794                 if (status & (BRCMF_PCIE_MB_INT_FN0_0 |
 795                               BRCMF_PCIE_MB_INT_FN0_1))
 796                         brcmf_pcie_handle_mb_data(devinfo);
 797                 if (status & BRCMF_PCIE_MB_INT_D2H_DB) {
 798                         if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
 799                                 brcmf_proto_msgbuf_rx_trigger(
 800                                                         &devinfo->pdev->dev);
 801                 }
 802         }
 803         brcmf_pcie_bus_console_read(devinfo);
 804         if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
 805                 brcmf_pcie_intr_enable(devinfo);
 806         devinfo->in_irq = false;
 807         return IRQ_HANDLED;
 808 }
 809
 810
 811 static int brcmf_pcie_request_irq(struct brcmf_pciedev_info *devinfo)
 812 {
 813         struct pci_dev *pdev;
 814
 815         pdev = devinfo->pdev;
 816
 817         brcmf_pcie_intr_disable(devinfo);
 818
 819         brcmf_dbg(PCIE, "Enter\n");
 820         /* is it a v1 or v2 implementation */
 821         devinfo->irq_requested = false;
 822         pci_enable_msi(pdev);
 823         if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1) {
 824                 if (request_threaded_irq(pdev->irq,
 825                                          brcmf_pcie_quick_check_isr_v1,
 826                                          brcmf_pcie_isr_thread_v1,
 827                                          IRQF_SHARED, "brcmf_pcie_intr",
 828                                          devinfo)) {
 829                         pci_disable_msi(pdev);
 830                         brcmf_err("Failed to request IRQ %d\n", pdev->irq);
 831                         return -EIO;
 832                 }
 833         } else {
 834                 if (request_threaded_irq(pdev->irq,
 835                                          brcmf_pcie_quick_check_isr_v2,
 836                                          brcmf_pcie_isr_thread_v2,
 837                                          IRQF_SHARED, "brcmf_pcie_intr",
 838                                          devinfo)) {
 839                         pci_disable_msi(pdev);
 840                         brcmf_err("Failed to request IRQ %d\n", pdev->irq);
 841                         return -EIO;
 842                 }
 843         }
 844         devinfo->irq_requested = true;
 845         devinfo->irq_allocated = true;
 846         return 0;
 847 }
 848
 849
 850 static void brcmf_pcie_release_irq(struct brcmf_pciedev_info *devinfo)
 851 {
 852         struct pci_dev *pdev;
 853         u32 status;
 854         u32 count;
 855
 856         if (!devinfo->irq_allocated)
 857                 return;
 858
 859         pdev = devinfo->pdev;
 860
 861         brcmf_pcie_intr_disable(devinfo);
 862         if (!devinfo->irq_requested)
 863                 return;
 864         devinfo->irq_requested = false;
 865         free_irq(pdev->irq, devinfo);
 866         pci_disable_msi(pdev);
 867
 868         msleep(50);
 869         count = 0;
 870         while ((devinfo->in_irq) && (count < 20)) {
 871                 msleep(50);
 872                 count++;
 873         }
 874         if (devinfo->in_irq)
 875                 brcmf_err("Still in IRQ (processing) !!!\n");
 876
 877         if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1) {
 878                 status = 0;
 879                 pci_read_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, &status);
 880                 pci_write_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, status);
 881         } else {
 882                 status = brcmf_pcie_read_reg32(devinfo,
 883                                                BRCMF_PCIE_PCIE2REG_MAILBOXINT);
 884                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT,
 885                                        status);
 886         }
 887         devinfo->irq_allocated = false;
 888 }
 889
 890
 891 static int brcmf_pcie_ring_mb_write_rptr(void *ctx)
 892 {
 893         struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
 894         struct brcmf_pciedev_info *devinfo = ring->devinfo;
 895         struct brcmf_commonring *commonring = &ring->commonring;
 896
 897         if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
 898                 return -EIO;
 899
 900         brcmf_dbg(PCIE, "W r_ptr %d (%d), ring %d\n", commonring->r_ptr,
 901                   commonring->w_ptr, ring->id);
 902
 903         devinfo->write_ptr(devinfo, ring->r_idx_addr, commonring->r_ptr);
 904
 905         return 0;
 906 }
 907
 908
 909 static int brcmf_pcie_ring_mb_write_wptr(void *ctx)
 910 {
 911         struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
 912         struct brcmf_pciedev_info *devinfo = ring->devinfo;
 913         struct brcmf_commonring *commonring = &ring->commonring;
 914
 915         if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
 916                 return -EIO;
 917
 918         brcmf_dbg(PCIE, "W w_ptr %d (%d), ring %d\n", commonring->w_ptr,
 919                   commonring->r_ptr, ring->id);
 920
 921         devinfo->write_ptr(devinfo, ring->w_idx_addr, commonring->w_ptr);
 922
 923         return 0;
 924 }
 925
 926
 927 static int brcmf_pcie_ring_mb_ring_bell(void *ctx)
 928 {
 929         struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
 930         struct brcmf_pciedev_info *devinfo = ring->devinfo;
 931
 932         if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
 933                 return -EIO;
 934
 935         devinfo->ringbell(devinfo);
 936
 937         return 0;
 938 }
 939
 940
 941 static int brcmf_pcie_ring_mb_update_rptr(void *ctx)
 942 {
 943         struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
 944         struct brcmf_pciedev_info *devinfo = ring->devinfo;
 945         struct brcmf_commonring *commonring = &ring->commonring;
 946
 947         if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
 948                 return -EIO;
 949
 950         commonring->r_ptr = devinfo->read_ptr(devinfo, ring->r_idx_addr);
 951
 952         brcmf_dbg(PCIE, "R r_ptr %d (%d), ring %d\n", commonring->r_ptr,
 953                   commonring->w_ptr, ring->id);
 954
 955         return 0;
 956 }
 957
 958
 959 static int brcmf_pcie_ring_mb_update_wptr(void *ctx)
 960 {
 961         struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
 962         struct brcmf_pciedev_info *devinfo = ring->devinfo;
 963         struct brcmf_commonring *commonring = &ring->commonring;
 964
 965         if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
 966                 return -EIO;
 967
 968         commonring->w_ptr = devinfo->read_ptr(devinfo, ring->w_idx_addr);
 969
 970         brcmf_dbg(PCIE, "R w_ptr %d (%d), ring %d\n", commonring->w_ptr,
 971                   commonring->r_ptr, ring->id);
 972
 973         return 0;
 974 }
 975
 976
 977 static void *
 978 brcmf_pcie_init_dmabuffer_for_device(struct brcmf_pciedev_info *devinfo,
 979                                      u32 size, u32 tcm_dma_phys_addr,
 980                                      dma_addr_t *dma_handle)
 981 {
 982         void *ring;
 983         u64 address;
 984
 985         ring = dma_alloc_coherent(&devinfo->pdev->dev, size, dma_handle,
 986                                   GFP_KERNEL);
 987         if (!ring)
 988                 return NULL;
 989
 990         address = (u64)*dma_handle;
 991         brcmf_pcie_write_tcm32(devinfo, tcm_dma_phys_addr,
 992                                address & 0xffffffff);
 993         brcmf_pcie_write_tcm32(devinfo, tcm_dma_phys_addr + 4, address >> 32);
 994
 995         memset(ring, 0, size);
 996
 997         return (ring);
 998 }
 999
1000
1001 static struct brcmf_pcie_ringbuf *
1002 brcmf_pcie_alloc_dma_and_ring(struct brcmf_pciedev_info *devinfo, u32 ring_id,
1003                               u32 tcm_ring_phys_addr)
1004 {
1005         void *dma_buf;
1006         dma_addr_t dma_handle;
1007         struct brcmf_pcie_ringbuf *ring;
1008         u32 size;
1009         u32 addr;
1010
1011         size = brcmf_ring_max_item[ring_id] * brcmf_ring_itemsize[ring_id];
1012         dma_buf = brcmf_pcie_init_dmabuffer_for_device(devinfo, size,
1013                         tcm_ring_phys_addr + BRCMF_RING_MEM_BASE_ADDR_OFFSET,
1014                         &dma_handle);
1015         if (!dma_buf)
1016                 return NULL;
1017
1018         addr = tcm_ring_phys_addr + BRCMF_RING_MAX_ITEM_OFFSET;
1019         brcmf_pcie_write_tcm16(devinfo, addr, brcmf_ring_max_item[ring_id]);
1020         addr = tcm_ring_phys_addr + BRCMF_RING_LEN_ITEMS_OFFSET;
1021         brcmf_pcie_write_tcm16(devinfo, addr, brcmf_ring_itemsize[ring_id]);
1022
1023         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
1024         if (!ring) {
1025                 dma_free_coherent(&devinfo->pdev->dev, size, dma_buf,
1026                                   dma_handle);
1027                 return NULL;
1028         }
1029         brcmf_commonring_config(&ring->commonring, brcmf_ring_max_item[ring_id],
1030                                 brcmf_ring_itemsize[ring_id], dma_buf);
1031         ring->dma_handle = dma_handle;
1032         ring->devinfo = devinfo;
1033         brcmf_commonring_register_cb(&ring->commonring,
1034                                      brcmf_pcie_ring_mb_ring_bell,
1035                                      brcmf_pcie_ring_mb_update_rptr,
1036                                      brcmf_pcie_ring_mb_update_wptr,
1037                                      brcmf_pcie_ring_mb_write_rptr,
1038                                      brcmf_pcie_ring_mb_write_wptr, ring);
1039
1040         return (ring);
1041 }
1042
1043
1044 static void brcmf_pcie_release_ringbuffer(struct device *dev,
1045                                           struct brcmf_pcie_ringbuf *ring)
1046 {
1047         void *dma_buf;
1048         u32 size;
1049
1050         if (!ring)
1051                 return;
1052
1053         dma_buf = ring->commonring.buf_addr;
1054         if (dma_buf) {
1055                 size = ring->commonring.depth * ring->commonring.item_len;
1056                 dma_free_coherent(dev, size, dma_buf, ring->dma_handle);
1057         }
1058         kfree(ring);
1059 }
1060
1061
1062 static void brcmf_pcie_release_ringbuffers(struct brcmf_pciedev_info *devinfo)
1063 {
1064         u32 i;
1065
1066         for (i = 0; i < BRCMF_NROF_COMMON_MSGRINGS; i++) {
1067                 brcmf_pcie_release_ringbuffer(&devinfo->pdev->dev,
1068                                               devinfo->shared.commonrings[i]);
1069                 devinfo->shared.commonrings[i] = NULL;
1070         }
1071         kfree(devinfo->shared.flowrings);
1072         devinfo->shared.flowrings = NULL;
1073         if (devinfo->idxbuf) {
1074                 dma_free_coherent(&devinfo->pdev->dev,
1075                                   devinfo->idxbuf_sz,
1076                                   devinfo->idxbuf,
1077                                   devinfo->idxbuf_dmahandle);
1078                 devinfo->idxbuf = NULL;
1079         }
1080 }
1081
1082
1083 static int brcmf_pcie_init_ringbuffers(struct brcmf_pciedev_info *devinfo)
1084 {
1085         struct brcmf_pcie_ringbuf *ring;
1086         struct brcmf_pcie_ringbuf *rings;
1087         u32 ring_addr;
1088         u32 d2h_w_idx_ptr;
1089         u32 d2h_r_idx_ptr;
1090         u32 h2d_w_idx_ptr;
1091         u32 h2d_r_idx_ptr;
1092         u32 addr;
1093         u32 ring_mem_ptr;
1094         u32 i;
1095         u64 address;
1096         u32 bufsz;
1097         u16 max_sub_queues;
1098         u8 idx_offset;
1099
1100         ring_addr = devinfo->shared.ring_info_addr;
1101         brcmf_dbg(PCIE, "Base ring addr = 0x%08x\n", ring_addr);
1102         addr = ring_addr + BRCMF_SHARED_RING_MAX_SUB_QUEUES;
1103         max_sub_queues = brcmf_pcie_read_tcm16(devinfo, addr);
1104
1105         if (devinfo->dma_idx_sz != 0) {
1106                 bufsz = (BRCMF_NROF_D2H_COMMON_MSGRINGS + max_sub_queues) *
1107                         devinfo->dma_idx_sz * 2;
1108                 devinfo->idxbuf = dma_alloc_coherent(&devinfo->pdev->dev, bufsz,
1109                                                      &devinfo->idxbuf_dmahandle,
1110                                                      GFP_KERNEL);
1111                 if (!devinfo->idxbuf)
1112                         devinfo->dma_idx_sz = 0;
1113         }
1114
1115         if (devinfo->dma_idx_sz == 0) {
1116                 addr = ring_addr + BRCMF_SHARED_RING_D2H_W_IDX_PTR_OFFSET;
1117                 d2h_w_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
1118                 addr = ring_addr + BRCMF_SHARED_RING_D2H_R_IDX_PTR_OFFSET;
1119                 d2h_r_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
1120                 addr = ring_addr + BRCMF_SHARED_RING_H2D_W_IDX_PTR_OFFSET;
1121                 h2d_w_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
1122                 addr = ring_addr + BRCMF_SHARED_RING_H2D_R_IDX_PTR_OFFSET;
1123                 h2d_r_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
1124                 idx_offset = sizeof(u32);
1125                 devinfo->write_ptr = brcmf_pcie_write_tcm16;
1126                 devinfo->read_ptr = brcmf_pcie_read_tcm16;
1127                 brcmf_dbg(PCIE, "Using TCM indices\n");
1128         } else {
1129                 memset(devinfo->idxbuf, 0, bufsz);
1130                 devinfo->idxbuf_sz = bufsz;
1131                 idx_offset = devinfo->dma_idx_sz;
1132                 devinfo->write_ptr = brcmf_pcie_write_idx;
1133                 devinfo->read_ptr = brcmf_pcie_read_idx;
1134
1135                 h2d_w_idx_ptr = 0;
1136                 addr = ring_addr + BRCMF_SHARED_RING_H2D_WP_HADDR_OFFSET;
1137                 address = (u64)devinfo->idxbuf_dmahandle;
1138                 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1139                 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1140
1141                 h2d_r_idx_ptr = h2d_w_idx_ptr + max_sub_queues * idx_offset;
1142                 addr = ring_addr + BRCMF_SHARED_RING_H2D_RP_HADDR_OFFSET;
1143                 address += max_sub_queues * idx_offset;
1144                 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1145                 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1146
1147                 d2h_w_idx_ptr = h2d_r_idx_ptr + max_sub_queues * idx_offset;
1148                 addr = ring_addr + BRCMF_SHARED_RING_D2H_WP_HADDR_OFFSET;
1149                 address += max_sub_queues * idx_offset;
1150                 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1151                 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1152
1153                 d2h_r_idx_ptr = d2h_w_idx_ptr +
1154                                 BRCMF_NROF_D2H_COMMON_MSGRINGS * idx_offset;
1155                 addr = ring_addr + BRCMF_SHARED_RING_D2H_RP_HADDR_OFFSET;
1156                 address += BRCMF_NROF_D2H_COMMON_MSGRINGS * idx_offset;
1157                 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1158                 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1159                 brcmf_dbg(PCIE, "Using host memory indices\n");
1160         }
1161
1162         addr = ring_addr + BRCMF_SHARED_RING_TCM_MEMLOC_OFFSET;
1163         ring_mem_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
1164
1165         for (i = 0; i < BRCMF_NROF_H2D_COMMON_MSGRINGS; i++) {
1166                 ring = brcmf_pcie_alloc_dma_and_ring(devinfo, i, ring_mem_ptr);
1167                 if (!ring)
1168                         goto fail;
1169                 ring->w_idx_addr = h2d_w_idx_ptr;
1170                 ring->r_idx_addr = h2d_r_idx_ptr;
1171                 ring->id = i;
1172                 devinfo->shared.commonrings[i] = ring;
1173
1174                 h2d_w_idx_ptr += idx_offset;
1175                 h2d_r_idx_ptr += idx_offset;
1176                 ring_mem_ptr += BRCMF_RING_MEM_SZ;
1177         }
1178
1179         for (i = BRCMF_NROF_H2D_COMMON_MSGRINGS;
1180              i < BRCMF_NROF_COMMON_MSGRINGS; i++) {
1181                 ring = brcmf_pcie_alloc_dma_and_ring(devinfo, i, ring_mem_ptr);
1182                 if (!ring)
1183                         goto fail;
1184                 ring->w_idx_addr = d2h_w_idx_ptr;
1185                 ring->r_idx_addr = d2h_r_idx_ptr;
1186                 ring->id = i;
1187                 devinfo->shared.commonrings[i] = ring;
1188
1189                 d2h_w_idx_ptr += idx_offset;
1190                 d2h_r_idx_ptr += idx_offset;
1191                 ring_mem_ptr += BRCMF_RING_MEM_SZ;
1192         }
1193
1194         devinfo->shared.nrof_flowrings =
1195                         max_sub_queues - BRCMF_NROF_H2D_COMMON_MSGRINGS;
1196         rings = kcalloc(devinfo->shared.nrof_flowrings, sizeof(*ring),
1197                         GFP_KERNEL);
1198         if (!rings)
1199                 goto fail;
1200
1201         brcmf_dbg(PCIE, "Nr of flowrings is %d\n",
1202                   devinfo->shared.nrof_flowrings);
1203
1204         for (i = 0; i < devinfo->shared.nrof_flowrings; i++) {
1205                 ring = &rings[i];
1206                 ring->devinfo = devinfo;
1207                 ring->id = i + BRCMF_NROF_COMMON_MSGRINGS;
1208                 brcmf_commonring_register_cb(&ring->commonring,
1209                                              brcmf_pcie_ring_mb_ring_bell,
1210                                              brcmf_pcie_ring_mb_update_rptr,
1211                                              brcmf_pcie_ring_mb_update_wptr,
1212                                              brcmf_pcie_ring_mb_write_rptr,
1213                                              brcmf_pcie_ring_mb_write_wptr,
1214                                              ring);
1215                 ring->w_idx_addr = h2d_w_idx_ptr;
1216                 ring->r_idx_addr = h2d_r_idx_ptr;
1217                 h2d_w_idx_ptr += idx_offset;
1218                 h2d_r_idx_ptr += idx_offset;
1219         }
1220         devinfo->shared.flowrings = rings;
1221
1222         return 0;
1223
1224 fail:
1225         brcmf_err("Allocating ring buffers failed\n");
1226         brcmf_pcie_release_ringbuffers(devinfo);
1227         return -ENOMEM;
1228 }
1229
1230
1231 static void
1232 brcmf_pcie_release_scratchbuffers(struct brcmf_pciedev_info *devinfo)
1233 {
1234         if (devinfo->shared.scratch)
1235                 dma_free_coherent(&devinfo->pdev->dev,
1236                                   BRCMF_DMA_D2H_SCRATCH_BUF_LEN,
1237                                   devinfo->shared.scratch,
1238                                   devinfo->shared.scratch_dmahandle);
1239         if (devinfo->shared.ringupd)
1240                 dma_free_coherent(&devinfo->pdev->dev,
1241                                   BRCMF_DMA_D2H_RINGUPD_BUF_LEN,
1242                                   devinfo->shared.ringupd,
1243                                   devinfo->shared.ringupd_dmahandle);
1244 }
1245
1246 static int brcmf_pcie_init_scratchbuffers(struct brcmf_pciedev_info *devinfo)
1247 {
1248         u64 address;
1249         u32 addr;
1250
1251         devinfo->shared.scratch = dma_alloc_coherent(&devinfo->pdev->dev,
1252                 BRCMF_DMA_D2H_SCRATCH_BUF_LEN,
1253                 &devinfo->shared.scratch_dmahandle, GFP_KERNEL);
1254         if (!devinfo->shared.scratch)
1255                 goto fail;
1256
1257         memset(devinfo->shared.scratch, 0, BRCMF_DMA_D2H_SCRATCH_BUF_LEN);
1258
1259         addr = devinfo->shared.tcm_base_address +
1260                BRCMF_SHARED_DMA_SCRATCH_ADDR_OFFSET;
1261         address = (u64)devinfo->shared.scratch_dmahandle;
1262         brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1263         brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1264         addr = devinfo->shared.tcm_base_address +
1265                BRCMF_SHARED_DMA_SCRATCH_LEN_OFFSET;
1266         brcmf_pcie_write_tcm32(devinfo, addr, BRCMF_DMA_D2H_SCRATCH_BUF_LEN);
1267
1268         devinfo->shared.ringupd = dma_alloc_coherent(&devinfo->pdev->dev,
1269                 BRCMF_DMA_D2H_RINGUPD_BUF_LEN,
1270                 &devinfo->shared.ringupd_dmahandle, GFP_KERNEL);
1271         if (!devinfo->shared.ringupd)
1272                 goto fail;
1273
1274         memset(devinfo->shared.ringupd, 0, BRCMF_DMA_D2H_RINGUPD_BUF_LEN);
1275
1276         addr = devinfo->shared.tcm_base_address +
1277                BRCMF_SHARED_DMA_RINGUPD_ADDR_OFFSET;
1278         address = (u64)devinfo->shared.ringupd_dmahandle;
1279         brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1280         brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1281         addr = devinfo->shared.tcm_base_address +
1282                BRCMF_SHARED_DMA_RINGUPD_LEN_OFFSET;
1283         brcmf_pcie_write_tcm32(devinfo, addr, BRCMF_DMA_D2H_RINGUPD_BUF_LEN);
1284         return 0;
1285
1286 fail:
1287         brcmf_err("Allocating scratch buffers failed\n");
1288         brcmf_pcie_release_scratchbuffers(devinfo);
1289         return -ENOMEM;
1290 }
1291
1292
1293 static void brcmf_pcie_down(struct device *dev)
1294 {
1295 }
1296
1297
1298 static int brcmf_pcie_tx(struct device *dev, struct sk_buff *skb)
1299 {
1300         return 0;
1301 }
1302
1303
1304 static int brcmf_pcie_tx_ctlpkt(struct device *dev, unsigned char *msg,
1305                                 uint len)
1306 {
1307         return 0;
1308 }
1309
1310
1311 static int brcmf_pcie_rx_ctlpkt(struct device *dev, unsigned char *msg,
1312                                 uint len)
1313 {
1314         return 0;
1315 }
1316
1317
1318 static void brcmf_pcie_wowl_config(struct device *dev, bool enabled)
1319 {
1320         struct brcmf_bus *bus_if = dev_get_drvdata(dev);
1321         struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie;
1322         struct brcmf_pciedev_info *devinfo = buspub->devinfo;
1323
1324         brcmf_dbg(PCIE, "Configuring WOWL, enabled=%d\n", enabled);
1325         devinfo->wowl_enabled = enabled;
1326         if (enabled)
1327                 device_set_wakeup_enable(&devinfo->pdev->dev, true);
1328         else
1329                 device_set_wakeup_enable(&devinfo->pdev->dev, false);
1330 }
1331
1332
1333 static struct brcmf_bus_ops brcmf_pcie_bus_ops = {
1334         .txdata = brcmf_pcie_tx,
1335         .stop = brcmf_pcie_down,
1336         .txctl = brcmf_pcie_tx_ctlpkt,
1337         .rxctl = brcmf_pcie_rx_ctlpkt,
1338         .wowl_config = brcmf_pcie_wowl_config,
1339 };
1340
1341
1342 static int
1343 brcmf_pcie_init_share_ram_info(struct brcmf_pciedev_info *devinfo,
1344                                u32 sharedram_addr)
1345 {
1346         struct brcmf_pcie_shared_info *shared;
1347         u32 addr;
1348         u32 version;
1349
1350         shared = &devinfo->shared;
1351         shared->tcm_base_address = sharedram_addr;
1352
1353         shared->flags = brcmf_pcie_read_tcm32(devinfo, sharedram_addr);
1354         version = shared->flags & BRCMF_PCIE_SHARED_VERSION_MASK;
1355         brcmf_dbg(PCIE, "PCIe protocol version %d\n", version);
1356         if ((version > BRCMF_PCIE_MAX_SHARED_VERSION) ||
1357             (version < BRCMF_PCIE_MIN_SHARED_VERSION)) {
1358                 brcmf_err("Unsupported PCIE version %d\n", version);
1359                 return -EINVAL;
1360         }
1361
1362         /* check firmware support dma indicies */
1363         if (shared->flags & BRCMF_PCIE_SHARED_DMA_INDEX) {
1364                 if (shared->flags & BRCMF_PCIE_SHARED_DMA_2B_IDX)
1365                         devinfo->dma_idx_sz = sizeof(u16);
1366                 else
1367                         devinfo->dma_idx_sz = sizeof(u32);
1368         }
1369
1370         addr = sharedram_addr + BRCMF_SHARED_MAX_RXBUFPOST_OFFSET;
1371         shared->max_rxbufpost = brcmf_pcie_read_tcm16(devinfo, addr);
1372         if (shared->max_rxbufpost == 0)
1373                 shared->max_rxbufpost = BRCMF_DEF_MAX_RXBUFPOST;
1374
1375         addr = sharedram_addr + BRCMF_SHARED_RX_DATAOFFSET_OFFSET;
1376         shared->rx_dataoffset = brcmf_pcie_read_tcm32(devinfo, addr);
1377
1378         addr = sharedram_addr + BRCMF_SHARED_HTOD_MB_DATA_ADDR_OFFSET;
1379         shared->htod_mb_data_addr = brcmf_pcie_read_tcm32(devinfo, addr);
1380
1381         addr = sharedram_addr + BRCMF_SHARED_DTOH_MB_DATA_ADDR_OFFSET;
1382         shared->dtoh_mb_data_addr = brcmf_pcie_read_tcm32(devinfo, addr);
1383
1384         addr = sharedram_addr + BRCMF_SHARED_RING_INFO_ADDR_OFFSET;
1385         shared->ring_info_addr = brcmf_pcie_read_tcm32(devinfo, addr);
1386
1387         brcmf_dbg(PCIE, "max rx buf post %d, rx dataoffset %d\n",
1388                   shared->max_rxbufpost, shared->rx_dataoffset);
1389
1390         brcmf_pcie_bus_console_init(devinfo);
1391
1392         return 0;
1393 }
1394
1395
1396 static int brcmf_pcie_get_fwnames(struct brcmf_pciedev_info *devinfo)
1397 {
1398         char *fw_name;
1399         char *nvram_name;
1400         uint fw_len, nv_len;
1401         char end;
1402
1403         brcmf_dbg(PCIE, "Enter, chip 0x%04x chiprev %d\n", devinfo->ci->chip,
1404                   devinfo->ci->chiprev);
1405
1406         switch (devinfo->ci->chip) {
1407         case BRCM_CC_43602_CHIP_ID:
1408                 fw_name = BRCMF_PCIE_43602_FW_NAME;
1409                 nvram_name = BRCMF_PCIE_43602_NVRAM_NAME;
1410                 break;
1411         case BRCM_CC_4356_CHIP_ID:
1412                 fw_name = BRCMF_PCIE_4356_FW_NAME;
1413                 nvram_name = BRCMF_PCIE_4356_NVRAM_NAME;
1414                 break;
1415         case BRCM_CC_43567_CHIP_ID:
1416         case BRCM_CC_43569_CHIP_ID:
1417         case BRCM_CC_43570_CHIP_ID:
1418                 fw_name = BRCMF_PCIE_43570_FW_NAME;
1419                 nvram_name = BRCMF_PCIE_43570_NVRAM_NAME;
1420                 break;
1421         case BRCM_CC_4358_CHIP_ID:
1422                 fw_name = BRCMF_PCIE_4358_FW_NAME;
1423                 nvram_name = BRCMF_PCIE_4358_NVRAM_NAME;
1424                 break;
1425         default:
1426                 brcmf_err("Unsupported chip 0x%04x\n", devinfo->ci->chip);
1427                 return -ENODEV;
1428         }
1429
1430         fw_len = sizeof(devinfo->fw_name) - 1;
1431         nv_len = sizeof(devinfo->nvram_name) - 1;
1432         /* check if firmware path is provided by module parameter */
1433         if (brcmf_firmware_path[0] != '\0') {
1434                 strncpy(devinfo->fw_name, brcmf_firmware_path, fw_len);
1435                 strncpy(devinfo->nvram_name, brcmf_firmware_path, nv_len);
1436                 fw_len -= strlen(devinfo->fw_name);
1437                 nv_len -= strlen(devinfo->nvram_name);
1438
1439                 end = brcmf_firmware_path[strlen(brcmf_firmware_path) - 1];
1440                 if (end != '/') {
1441                         strncat(devinfo->fw_name, "/", fw_len);
1442                         strncat(devinfo->nvram_name, "/", nv_len);
1443                         fw_len--;
1444                         nv_len--;
1445                 }
1446         }
1447         strncat(devinfo->fw_name, fw_name, fw_len);
1448         strncat(devinfo->nvram_name, nvram_name, nv_len);
1449
1450         return 0;
1451 }
1452
1453
1454 static int brcmf_pcie_download_fw_nvram(struct brcmf_pciedev_info *devinfo,
1455                                         const struct firmware *fw, void *nvram,
1456                                         u32 nvram_len)
1457 {
1458         u32 sharedram_addr;
1459         u32 sharedram_addr_written;
1460         u32 loop_counter;
1461         int err;
1462         u32 address;
1463         u32 resetintr;
1464
1465         devinfo->ringbell = brcmf_pcie_ringbell_v2;
1466         devinfo->generic_corerev = BRCMF_PCIE_GENREV2;
1467
1468         brcmf_dbg(PCIE, "Halt ARM.\n");
1469         err = brcmf_pcie_enter_download_state(devinfo);
1470         if (err)
1471                 return err;
1472
1473         brcmf_dbg(PCIE, "Download FW %s\n", devinfo->fw_name);
1474         brcmf_pcie_copy_mem_todev(devinfo, devinfo->ci->rambase,
1475                                   (void *)fw->data, fw->size);
1476
1477         resetintr = get_unaligned_le32(fw->data);
1478         release_firmware(fw);
1479
1480         /* reset last 4 bytes of RAM address. to be used for shared
1481          * area. This identifies when FW is running
1482          */
1483         brcmf_pcie_write_ram32(devinfo, devinfo->ci->ramsize - 4, 0);
1484
1485         if (nvram) {
1486                 brcmf_dbg(PCIE, "Download NVRAM %s\n", devinfo->nvram_name);
1487                 address = devinfo->ci->rambase + devinfo->ci->ramsize -
1488                           nvram_len;
1489                 brcmf_pcie_copy_mem_todev(devinfo, address, nvram, nvram_len);
1490                 brcmf_fw_nvram_free(nvram);
1491         } else {
1492                 brcmf_dbg(PCIE, "No matching NVRAM file found %s\n",
1493                           devinfo->nvram_name);
1494         }
1495
1496         sharedram_addr_written = brcmf_pcie_read_ram32(devinfo,
1497                                                        devinfo->ci->ramsize -
1498                                                        4);
1499         brcmf_dbg(PCIE, "Bring ARM in running state\n");
1500         err = brcmf_pcie_exit_download_state(devinfo, resetintr);
1501         if (err)
1502                 return err;
1503
1504         brcmf_dbg(PCIE, "Wait for FW init\n");
1505         sharedram_addr = sharedram_addr_written;
1506         loop_counter = BRCMF_PCIE_FW_UP_TIMEOUT / 50;
1507         while ((sharedram_addr == sharedram_addr_written) && (loop_counter)) {
1508                 msleep(50);
1509                 sharedram_addr = brcmf_pcie_read_ram32(devinfo,
1510                                                        devinfo->ci->ramsize -
1511                                                        4);
1512                 loop_counter--;
1513         }
1514         if (sharedram_addr == sharedram_addr_written) {
1515                 brcmf_err("FW failed to initialize\n");
1516                 return -ENODEV;
1517         }
1518         brcmf_dbg(PCIE, "Shared RAM addr: 0x%08x\n", sharedram_addr);
1519
1520         return (brcmf_pcie_init_share_ram_info(devinfo, sharedram_addr));
1521 }
1522
1523
1524 static int brcmf_pcie_get_resource(struct brcmf_pciedev_info *devinfo)
1525 {
1526         struct pci_dev *pdev;
1527         int err;
1528         phys_addr_t  bar0_addr, bar1_addr;
1529         ulong bar1_size;
1530
1531         pdev = devinfo->pdev;
1532
1533         err = pci_enable_device(pdev);
1534         if (err) {
1535                 brcmf_err("pci_enable_device failed err=%d\n", err);
1536                 return err;
1537         }
1538
1539         pci_set_master(pdev);
1540
1541         /* Bar-0 mapped address */
1542         bar0_addr = pci_resource_start(pdev, 0);
1543         /* Bar-1 mapped address */
1544         bar1_addr = pci_resource_start(pdev, 2);
1545         /* read Bar-1 mapped memory range */
1546         bar1_size = pci_resource_len(pdev, 2);
1547         if ((bar1_size == 0) || (bar1_addr == 0)) {
1548                 brcmf_err("BAR1 Not enabled, device size=%ld, addr=%#016llx\n",
1549                           bar1_size, (unsigned long long)bar1_addr);
1550                 return -EINVAL;
1551         }
1552
1553         devinfo->regs = ioremap_nocache(bar0_addr, BRCMF_PCIE_REG_MAP_SIZE);
1554         devinfo->tcm = ioremap_nocache(bar1_addr, BRCMF_PCIE_TCM_MAP_SIZE);
1555         devinfo->tcm_size = BRCMF_PCIE_TCM_MAP_SIZE;
1556
1557         if (!devinfo->regs || !devinfo->tcm) {
1558                 brcmf_err("ioremap() failed (%p,%p)\n", devinfo->regs,
1559                           devinfo->tcm);
1560                 return -EINVAL;
1561         }
1562         brcmf_dbg(PCIE, "Phys addr : reg space = %p base addr %#016llx\n",
1563                   devinfo->regs, (unsigned long long)bar0_addr);
1564         brcmf_dbg(PCIE, "Phys addr : mem space = %p base addr %#016llx\n",
1565                   devinfo->tcm, (unsigned long long)bar1_addr);
1566
1567         return 0;
1568 }
1569
1570
1571 static void brcmf_pcie_release_resource(struct brcmf_pciedev_info *devinfo)
1572 {
1573         if (devinfo->tcm)
1574                 iounmap(devinfo->tcm);
1575         if (devinfo->regs)
1576                 iounmap(devinfo->regs);
1577
1578         pci_disable_device(devinfo->pdev);
1579 }
1580
1581
1582 static int brcmf_pcie_attach_bus(struct device *dev)
1583 {
1584         int ret;
1585
1586         /* Attach to the common driver interface */
1587         ret = brcmf_attach(dev);
1588         if (ret) {
1589                 brcmf_err("brcmf_attach failed\n");
1590         } else {
1591                 ret = brcmf_bus_start(dev);
1592                 if (ret)
1593                         brcmf_err("dongle is not responding\n");
1594         }
1595
1596         return ret;
1597 }
1598
1599
1600 static u32 brcmf_pcie_buscore_prep_addr(const struct pci_dev *pdev, u32 addr)
1601 {
1602         u32 ret_addr;
1603
1604         ret_addr = addr & (BRCMF_PCIE_BAR0_REG_SIZE - 1);
1605         addr &= ~(BRCMF_PCIE_BAR0_REG_SIZE - 1);
1606         pci_write_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, addr);
1607
1608         return ret_addr;
1609 }
1610
1611
1612 static u32 brcmf_pcie_buscore_read32(void *ctx, u32 addr)
1613 {
1614         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1615
1616         addr = brcmf_pcie_buscore_prep_addr(devinfo->pdev, addr);
1617         return brcmf_pcie_read_reg32(devinfo, addr);
1618 }
1619
1620
1621 static void brcmf_pcie_buscore_write32(void *ctx, u32 addr, u32 value)
1622 {
1623         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1624
1625         addr = brcmf_pcie_buscore_prep_addr(devinfo->pdev, addr);
1626         brcmf_pcie_write_reg32(devinfo, addr, value);
1627 }
1628
1629
1630 static int brcmf_pcie_buscoreprep(void *ctx)
1631 {
1632         return brcmf_pcie_get_resource(ctx);
1633 }
1634
1635
1636 static void brcmf_pcie_buscore_activate(void *ctx, struct brcmf_chip *chip,
1637                                         u32 rstvec)
1638 {
1639         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1640
1641         brcmf_pcie_write_tcm32(devinfo, 0, rstvec);
1642 }
1643
1644
1645 static const struct brcmf_buscore_ops brcmf_pcie_buscore_ops = {
1646         .prepare = brcmf_pcie_buscoreprep,
1647         .activate = brcmf_pcie_buscore_activate,
1648         .read32 = brcmf_pcie_buscore_read32,
1649         .write32 = brcmf_pcie_buscore_write32,
1650 };
1651
1652 static void brcmf_pcie_setup(struct device *dev, const struct firmware *fw,
1653                              void *nvram, u32 nvram_len)
1654 {
1655         struct brcmf_bus *bus = dev_get_drvdata(dev);
1656         struct brcmf_pciedev *pcie_bus_dev = bus->bus_priv.pcie;
1657         struct brcmf_pciedev_info *devinfo = pcie_bus_dev->devinfo;
1658         struct brcmf_commonring **flowrings;
1659         int ret;
1660         u32 i;
1661
1662         brcmf_pcie_attach(devinfo);
1663
1664         ret = brcmf_pcie_download_fw_nvram(devinfo, fw, nvram, nvram_len);
1665         if (ret)
1666                 goto fail;
1667
1668         devinfo->state = BRCMFMAC_PCIE_STATE_UP;
1669
1670         ret = brcmf_pcie_init_ringbuffers(devinfo);
1671         if (ret)
1672                 goto fail;
1673
1674         ret = brcmf_pcie_init_scratchbuffers(devinfo);
1675         if (ret)
1676                 goto fail;
1677
1678         brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
1679         ret = brcmf_pcie_request_irq(devinfo);
1680         if (ret)
1681                 goto fail;
1682
1683         /* hook the commonrings in the bus structure. */
1684         for (i = 0; i < BRCMF_NROF_COMMON_MSGRINGS; i++)
1685                 bus->msgbuf->commonrings[i] =
1686                                 &devinfo->shared.commonrings[i]->commonring;
1687
1688         flowrings = kcalloc(devinfo->shared.nrof_flowrings, sizeof(*flowrings),
1689                             GFP_KERNEL);
1690         if (!flowrings)
1691                 goto fail;
1692
1693         for (i = 0; i < devinfo->shared.nrof_flowrings; i++)
1694                 flowrings[i] = &devinfo->shared.flowrings[i].commonring;
1695         bus->msgbuf->flowrings = flowrings;
1696
1697         bus->msgbuf->rx_dataoffset = devinfo->shared.rx_dataoffset;
1698         bus->msgbuf->max_rxbufpost = devinfo->shared.max_rxbufpost;
1699         bus->msgbuf->nrof_flowrings = devinfo->shared.nrof_flowrings;
1700
1701         init_waitqueue_head(&devinfo->mbdata_resp_wait);
1702
1703         brcmf_pcie_intr_enable(devinfo);
1704         if (brcmf_pcie_attach_bus(bus->dev) == 0)
1705                 return;
1706
1707         brcmf_pcie_bus_console_read(devinfo);
1708
1709 fail:
1710         device_release_driver(dev);
1711 }
1712
1713 static int
1714 brcmf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1715 {
1716         int ret;
1717         struct brcmf_pciedev_info *devinfo;
1718         struct brcmf_pciedev *pcie_bus_dev;
1719         struct brcmf_bus *bus;
1720         u16 domain_nr;
1721         u16 bus_nr;
1722
1723         domain_nr = pci_domain_nr(pdev->bus) + 1;
1724         bus_nr = pdev->bus->number;
1725         brcmf_dbg(PCIE, "Enter %x:%x (%d/%d)\n", pdev->vendor, pdev->device,
1726                   domain_nr, bus_nr);
1727
1728         ret = -ENOMEM;
1729         devinfo = kzalloc(sizeof(*devinfo), GFP_KERNEL);
1730         if (devinfo == NULL)
1731                 return ret;
1732
1733         devinfo->pdev = pdev;
1734         pcie_bus_dev = NULL;
1735         devinfo->ci = brcmf_chip_attach(devinfo, &brcmf_pcie_buscore_ops);
1736         if (IS_ERR(devinfo->ci)) {
1737                 ret = PTR_ERR(devinfo->ci);
1738                 devinfo->ci = NULL;
1739                 goto fail;
1740         }
1741
1742         pcie_bus_dev = kzalloc(sizeof(*pcie_bus_dev), GFP_KERNEL);
1743         if (pcie_bus_dev == NULL) {
1744                 ret = -ENOMEM;
1745                 goto fail;
1746         }
1747
1748         bus = kzalloc(sizeof(*bus), GFP_KERNEL);
1749         if (!bus) {
1750                 ret = -ENOMEM;
1751                 goto fail;
1752         }
1753         bus->msgbuf = kzalloc(sizeof(*bus->msgbuf), GFP_KERNEL);
1754         if (!bus->msgbuf) {
1755                 ret = -ENOMEM;
1756                 kfree(bus);
1757                 goto fail;
1758         }
1759
1760         /* hook it all together. */
1761         pcie_bus_dev->devinfo = devinfo;
1762         pcie_bus_dev->bus = bus;
1763         bus->dev = &pdev->dev;
1764         bus->bus_priv.pcie = pcie_bus_dev;
1765         bus->ops = &brcmf_pcie_bus_ops;
1766         bus->proto_type = BRCMF_PROTO_MSGBUF;
1767         bus->chip = devinfo->coreid;
1768         bus->wowl_supported = pci_pme_capable(pdev, PCI_D3hot);
1769         dev_set_drvdata(&pdev->dev, bus);
1770
1771         ret = brcmf_pcie_get_fwnames(devinfo);
1772         if (ret)
1773                 goto fail_bus;
1774
1775         ret = brcmf_fw_get_firmwares_pcie(bus->dev, BRCMF_FW_REQUEST_NVRAM |
1776                                                     BRCMF_FW_REQ_NV_OPTIONAL,
1777                                           devinfo->fw_name, devinfo->nvram_name,
1778                                           brcmf_pcie_setup, domain_nr, bus_nr);
1779         if (ret == 0)
1780                 return 0;
1781 fail_bus:
1782         kfree(bus->msgbuf);
1783         kfree(bus);
1784 fail:
1785         brcmf_err("failed %x:%x\n", pdev->vendor, pdev->device);
1786         brcmf_pcie_release_resource(devinfo);
1787         if (devinfo->ci)
1788                 brcmf_chip_detach(devinfo->ci);
1789         kfree(pcie_bus_dev);
1790         kfree(devinfo);
1791         return ret;
1792 }
1793
1794
1795 static void
1796 brcmf_pcie_remove(struct pci_dev *pdev)
1797 {
1798         struct brcmf_pciedev_info *devinfo;
1799         struct brcmf_bus *bus;
1800
1801         brcmf_dbg(PCIE, "Enter\n");
1802
1803         bus = dev_get_drvdata(&pdev->dev);
1804         if (bus == NULL)
1805                 return;
1806
1807         devinfo = bus->bus_priv.pcie->devinfo;
1808
1809         devinfo->state = BRCMFMAC_PCIE_STATE_DOWN;
1810         if (devinfo->ci)
1811                 brcmf_pcie_intr_disable(devinfo);
1812
1813         brcmf_detach(&pdev->dev);
1814         brcmf_pcie_reset_device(devinfo);
1815
1816         kfree(bus->bus_priv.pcie);
1817         kfree(bus->msgbuf->flowrings);
1818         kfree(bus->msgbuf);
1819         kfree(bus);
1820
1821         brcmf_pcie_release_irq(devinfo);
1822         brcmf_pcie_release_scratchbuffers(devinfo);
1823         brcmf_pcie_release_ringbuffers(devinfo);
1824         brcmf_pcie_reset_device(devinfo);
1825         brcmf_pcie_release_resource(devinfo);
1826
1827         if (devinfo->ci)
1828                 brcmf_chip_detach(devinfo->ci);
1829
1830         kfree(devinfo);
1831         dev_set_drvdata(&pdev->dev, NULL);
1832 }
1833
1834
1835 #ifdef CONFIG_PM
1836
1837
1838 static int brcmf_pcie_suspend(struct pci_dev *pdev, pm_message_t state)
1839 {
1840         struct brcmf_pciedev_info *devinfo;
1841         struct brcmf_bus *bus;
1842         int err;
1843
1844         brcmf_dbg(PCIE, "Enter, state=%d, pdev=%p\n", state.event, pdev);
1845
1846         bus = dev_get_drvdata(&pdev->dev);
1847         devinfo = bus->bus_priv.pcie->devinfo;
1848
1849         brcmf_bus_change_state(bus, BRCMF_BUS_DOWN);
1850
1851         devinfo->mbdata_completed = false;
1852         brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_D3_INFORM);
1853
1854         wait_event_timeout(devinfo->mbdata_resp_wait,
1855                            devinfo->mbdata_completed,
1856                            msecs_to_jiffies(BRCMF_PCIE_MBDATA_TIMEOUT));
1857         if (!devinfo->mbdata_completed) {
1858                 brcmf_err("Timeout on response for entering D3 substate\n");
1859                 return -EIO;
1860         }
1861         brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_D0_INFORM_IN_USE);
1862
1863         err = pci_save_state(pdev);
1864         if (err)
1865                 brcmf_err("pci_save_state failed, err=%d\n", err);
1866         if ((err) || (!devinfo->wowl_enabled)) {
1867                 brcmf_chip_detach(devinfo->ci);
1868                 devinfo->ci = NULL;
1869                 brcmf_pcie_remove(pdev);
1870                 return 0;
1871         }
1872
1873         return pci_prepare_to_sleep(pdev);
1874 }
1875
1876 static int brcmf_pcie_resume(struct pci_dev *pdev)
1877 {
1878         struct brcmf_pciedev_info *devinfo;
1879         struct brcmf_bus *bus;
1880         int err;
1881
1882         bus = dev_get_drvdata(&pdev->dev);
1883         brcmf_dbg(PCIE, "Enter, pdev=%p, bus=%p\n", pdev, bus);
1884
1885         err = pci_set_power_state(pdev, PCI_D0);
1886         if (err) {
1887                 brcmf_err("pci_set_power_state failed, err=%d\n", err);
1888                 goto cleanup;
1889         }
1890         pci_restore_state(pdev);
1891         pci_enable_wake(pdev, PCI_D3hot, false);
1892         pci_enable_wake(pdev, PCI_D3cold, false);
1893
1894         /* Check if device is still up and running, if so we are ready */
1895         if (bus) {
1896                 devinfo = bus->bus_priv.pcie->devinfo;
1897                 if (brcmf_pcie_read_reg32(devinfo,
1898                                           BRCMF_PCIE_PCIE2REG_INTMASK) != 0) {
1899                         if (brcmf_pcie_send_mb_data(devinfo,
1900                                                     BRCMF_H2D_HOST_D0_INFORM))
1901                                 goto cleanup;
1902                         brcmf_dbg(PCIE, "Hot resume, continue....\n");
1903                         brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
1904                         brcmf_bus_change_state(bus, BRCMF_BUS_UP);
1905                         brcmf_pcie_intr_enable(devinfo);
1906                         return 0;
1907                 }
1908         }
1909
1910 cleanup:
1911         if (bus) {
1912                 devinfo = bus->bus_priv.pcie->devinfo;
1913                 brcmf_chip_detach(devinfo->ci);
1914                 devinfo->ci = NULL;
1915                 brcmf_pcie_remove(pdev);
1916         }
1917         err = brcmf_pcie_probe(pdev, NULL);
1918         if (err)
1919                 brcmf_err("probe after resume failed, err=%d\n", err);
1920
1921         return err;
1922 }
1923
1924
1925 #endif /* CONFIG_PM */
1926
1927
1928 #define BRCMF_PCIE_DEVICE(dev_id)       { BRCM_PCIE_VENDOR_ID_BROADCOM, dev_id,\
1929         PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_OTHER << 8, 0xffff00, 0 }
1930
1931 static struct pci_device_id brcmf_pcie_devid_table[] = {
1932         BRCMF_PCIE_DEVICE(BRCM_PCIE_4356_DEVICE_ID),
1933         BRCMF_PCIE_DEVICE(BRCM_PCIE_43567_DEVICE_ID),
1934         BRCMF_PCIE_DEVICE(BRCM_PCIE_43570_DEVICE_ID),
1935         BRCMF_PCIE_DEVICE(BRCM_PCIE_4358_DEVICE_ID),
1936         BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_DEVICE_ID),
1937         BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_2G_DEVICE_ID),
1938         BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_5G_DEVICE_ID),
1939         BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_RAW_DEVICE_ID),
1940         { /* end: all zeroes */ }
1941 };
1942
1943
1944 MODULE_DEVICE_TABLE(pci, brcmf_pcie_devid_table);
1945
1946
1947 static struct pci_driver brcmf_pciedrvr = {
1948         .node = {},
1949         .name = KBUILD_MODNAME,
1950         .id_table = brcmf_pcie_devid_table,
1951         .probe = brcmf_pcie_probe,
1952         .remove = brcmf_pcie_remove,
1953 #ifdef CONFIG_PM
1954         .suspend = brcmf_pcie_suspend,
1955         .resume = brcmf_pcie_resume
1956 #endif /* CONFIG_PM */
1957 };
1958
1959
1960 void brcmf_pcie_register(void)
1961 {
1962         int err;
1963
1964         brcmf_dbg(PCIE, "Enter\n");
1965         err = pci_register_driver(&brcmf_pciedrvr);
1966         if (err)
1967                 brcmf_err("PCIE driver registration failed, err=%d\n", err);
1968 }
1969
1970
1971 void brcmf_pcie_exit(void)
1972 {
1973         brcmf_dbg(PCIE, "Enter\n");
1974         pci_unregister_driver(&brcmf_pciedrvr);
1975 }