2 * Copyright (c) 2010 Broadcom Corporation
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/types.h>
18 #include <linux/kernel.h>
19 #include <linux/kthread.h>
20 #include <linux/printk.h>
21 #include <linux/pci_ids.h>
22 #include <linux/netdevice.h>
23 #include <linux/interrupt.h>
24 #include <linux/sched.h>
25 #include <linux/mmc/sdio.h>
26 #include <linux/mmc/sdio_func.h>
27 #include <linux/mmc/card.h>
28 #include <linux/semaphore.h>
29 #include <linux/firmware.h>
30 #include <asm/unaligned.h>
32 #include <brcmu_wifi.h>
33 #include <brcmu_utils.h>
34 #include <brcm_hw_ids.h>
36 #include "sdio_host.h"
38 #define DCMD_RESP_TIMEOUT 2000 /* In milli second */
42 #define BRCMF_TRAP_INFO_SIZE 80
44 #define CBUF_LEN (128)
47 __le32 buf; /* Can't be pointer on (64-bit) hosts */
50 char *_buf_compat; /* Redundant pointer for backward compat. */
55 * When there is no UART (e.g. Quickturn),
56 * the host should write a complete
57 * input line directly into cbuf and then write
58 * the length into vcons_in.
59 * This may also be used when there is a real UART
60 * (at risk of conflicting with
61 * the real UART). vcons_out is currently unused.
66 /* Output (logging) buffer
67 * Console output is written to a ring buffer log_buf at index log_idx.
68 * The host may read the output when it sees log_idx advance.
69 * Output will be lost if the output wraps around faster than the host
72 struct rte_log_le log_le;
74 /* Console input line buffer
75 * Characters are read one at a time into cbuf
76 * until <CR> is received, then
77 * the buffer is processed as a command line.
78 * Also used for virtual UART.
85 #include <chipcommon.h>
89 #include "dhd_proto.h"
93 #define TXQLEN 2048 /* bulk tx queue length */
94 #define TXHI (TXQLEN - 256) /* turn on flow control above TXHI */
95 #define TXLOW (TXHI - 256) /* turn off flow control below TXLOW */
98 #define TXRETRIES 2 /* # of retries for tx frames */
100 #define BRCMF_RXBOUND 50 /* Default for max rx frames in
103 #define BRCMF_TXBOUND 20 /* Default for max tx frames in
106 #define BRCMF_TXMINMAX 1 /* Max tx frames if rx still pending */
108 #define MEMBLOCK 2048 /* Block size used for downloading
110 #define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold
111 biggest possible glom */
113 #define BRCMF_FIRSTREAD (1 << 6)
116 /* SBSDIO_DEVICE_CTL */
118 /* 1: device will assert busy signal when receiving CMD53 */
119 #define SBSDIO_DEVCTL_SETBUSY 0x01
120 /* 1: assertion of sdio interrupt is synchronous to the sdio clock */
121 #define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02
122 /* 1: mask all interrupts to host except the chipActive (rev 8) */
123 #define SBSDIO_DEVCTL_CA_INT_ONLY 0x04
124 /* 1: isolate internal sdio signals, put external pads in tri-state; requires
125 * sdio bus power cycle to clear (rev 9) */
126 #define SBSDIO_DEVCTL_PADS_ISO 0x08
127 /* Force SD->SB reset mapping (rev 11) */
128 #define SBSDIO_DEVCTL_SB_RST_CTL 0x30
129 /* Determined by CoreControl bit */
130 #define SBSDIO_DEVCTL_RST_CORECTL 0x00
131 /* Force backplane reset */
132 #define SBSDIO_DEVCTL_RST_BPRESET 0x10
133 /* Force no backplane reset */
134 #define SBSDIO_DEVCTL_RST_NOBPRESET 0x20
136 /* SBSDIO_FUNC1_CHIPCLKCSR */
138 /* Force ALP request to backplane */
139 #define SBSDIO_FORCE_ALP 0x01
140 /* Force HT request to backplane */
141 #define SBSDIO_FORCE_HT 0x02
142 /* Force ILP request to backplane */
143 #define SBSDIO_FORCE_ILP 0x04
144 /* Make ALP ready (power up xtal) */
145 #define SBSDIO_ALP_AVAIL_REQ 0x08
146 /* Make HT ready (power up PLL) */
147 #define SBSDIO_HT_AVAIL_REQ 0x10
148 /* Squelch clock requests from HW */
149 #define SBSDIO_FORCE_HW_CLKREQ_OFF 0x20
150 /* Status: ALP is ready */
151 #define SBSDIO_ALP_AVAIL 0x40
152 /* Status: HT is ready */
153 #define SBSDIO_HT_AVAIL 0x80
155 #define SBSDIO_AVBITS (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL)
156 #define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS)
157 #define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS)
158 #define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval))
160 #define SBSDIO_CLKAV(regval, alponly) \
161 (SBSDIO_ALPAV(regval) && (alponly ? 1 : SBSDIO_HTAV(regval)))
163 /* direct(mapped) cis space */
165 /* MAPPED common CIS address */
166 #define SBSDIO_CIS_BASE_COMMON 0x1000
167 /* maximum bytes in one CIS */
168 #define SBSDIO_CIS_SIZE_LIMIT 0x200
169 /* cis offset addr is < 17 bits */
170 #define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF
172 /* manfid tuple length, include tuple, link bytes */
173 #define SBSDIO_CIS_MANFID_TUPLE_LEN 6
176 #define I_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */
177 #define I_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */
178 #define I_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */
179 #define I_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */
180 #define I_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */
181 #define I_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */
182 #define I_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */
183 #define I_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */
184 #define I_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */
185 #define I_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */
186 #define I_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */
187 #define I_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */
188 #define I_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */
189 #define I_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */
190 #define I_PC (1 << 10) /* descriptor error */
191 #define I_PD (1 << 11) /* data error */
192 #define I_DE (1 << 12) /* Descriptor protocol Error */
193 #define I_RU (1 << 13) /* Receive descriptor Underflow */
194 #define I_RO (1 << 14) /* Receive fifo Overflow */
195 #define I_XU (1 << 15) /* Transmit fifo Underflow */
196 #define I_RI (1 << 16) /* Receive Interrupt */
197 #define I_BUSPWR (1 << 17) /* SDIO Bus Power Change (rev 9) */
198 #define I_XMTDATA_AVAIL (1 << 23) /* bits in fifo */
199 #define I_XI (1 << 24) /* Transmit Interrupt */
200 #define I_RF_TERM (1 << 25) /* Read Frame Terminate */
201 #define I_WF_TERM (1 << 26) /* Write Frame Terminate */
202 #define I_PCMCIA_XU (1 << 27) /* PCMCIA Transmit FIFO Underflow */
203 #define I_SBINT (1 << 28) /* sbintstatus Interrupt */
204 #define I_CHIPACTIVE (1 << 29) /* chip from doze to active state */
205 #define I_SRESET (1 << 30) /* CCCR RES interrupt */
206 #define I_IOE2 (1U << 31) /* CCCR IOE2 Bit Changed */
207 #define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU)
208 #define I_DMA (I_RI | I_XI | I_ERRORS)
211 #define CC_CISRDY (1 << 0) /* CIS Ready */
212 #define CC_BPRESEN (1 << 1) /* CCCR RES signal */
213 #define CC_F2RDY (1 << 2) /* set CCCR IOR2 bit */
214 #define CC_CLRPADSISO (1 << 3) /* clear SDIO pads isolation */
215 #define CC_XMTDATAAVAIL_MODE (1 << 4)
216 #define CC_XMTDATAAVAIL_CTRL (1 << 5)
219 #define SFC_RF_TERM (1 << 0) /* Read Frame Terminate */
220 #define SFC_WF_TERM (1 << 1) /* Write Frame Terminate */
221 #define SFC_CRC4WOOS (1 << 2) /* CRC error for write out of sync */
222 #define SFC_ABORTALL (1 << 3) /* Abort all in-progress frames */
225 #define SDPCM_FRAMETAG_LEN 4 /* 2 bytes len, 2 bytes check val */
227 /* Total length of frame header for dongle protocol */
228 #define SDPCM_HDRLEN (SDPCM_FRAMETAG_LEN + SDPCM_SWHEADER_LEN)
229 #define SDPCM_RESERVE (SDPCM_HDRLEN + BRCMF_SDALIGN)
232 * Software allocation of To SB Mailbox resources
235 /* tosbmailbox bits corresponding to intstatus bits */
236 #define SMB_NAK (1 << 0) /* Frame NAK */
237 #define SMB_INT_ACK (1 << 1) /* Host Interrupt ACK */
238 #define SMB_USE_OOB (1 << 2) /* Use OOB Wakeup */
239 #define SMB_DEV_INT (1 << 3) /* Miscellaneous Interrupt */
241 /* tosbmailboxdata */
242 #define SMB_DATA_VERSION_SHIFT 16 /* host protocol version */
245 * Software allocation of To Host Mailbox resources
249 #define I_HMB_FC_STATE I_HMB_SW0 /* Flow Control State */
250 #define I_HMB_FC_CHANGE I_HMB_SW1 /* Flow Control State Changed */
251 #define I_HMB_FRAME_IND I_HMB_SW2 /* Frame Indication */
252 #define I_HMB_HOST_INT I_HMB_SW3 /* Miscellaneous Interrupt */
254 /* tohostmailboxdata */
255 #define HMB_DATA_NAKHANDLED 1 /* retransmit NAK'd frame */
256 #define HMB_DATA_DEVREADY 2 /* talk to host after enable */
257 #define HMB_DATA_FC 4 /* per prio flowcontrol update flag */
258 #define HMB_DATA_FWREADY 8 /* fw ready for protocol activity */
260 #define HMB_DATA_FCDATA_MASK 0xff000000
261 #define HMB_DATA_FCDATA_SHIFT 24
263 #define HMB_DATA_VERSION_MASK 0x00ff0000
264 #define HMB_DATA_VERSION_SHIFT 16
267 * Software-defined protocol header
270 /* Current protocol version */
271 #define SDPCM_PROT_VERSION 4
273 /* SW frame header */
274 #define SDPCM_PACKET_SEQUENCE(p) (((u8 *)p)[0] & 0xff)
276 #define SDPCM_CHANNEL_MASK 0x00000f00
277 #define SDPCM_CHANNEL_SHIFT 8
278 #define SDPCM_PACKET_CHANNEL(p) (((u8 *)p)[1] & 0x0f)
280 #define SDPCM_NEXTLEN_OFFSET 2
282 /* Data Offset from SOF (HW Tag, SW Tag, Pad) */
283 #define SDPCM_DOFFSET_OFFSET 3 /* Data Offset */
284 #define SDPCM_DOFFSET_VALUE(p) (((u8 *)p)[SDPCM_DOFFSET_OFFSET] & 0xff)
285 #define SDPCM_DOFFSET_MASK 0xff000000
286 #define SDPCM_DOFFSET_SHIFT 24
287 #define SDPCM_FCMASK_OFFSET 4 /* Flow control */
288 #define SDPCM_FCMASK_VALUE(p) (((u8 *)p)[SDPCM_FCMASK_OFFSET] & 0xff)
289 #define SDPCM_WINDOW_OFFSET 5 /* Credit based fc */
290 #define SDPCM_WINDOW_VALUE(p) (((u8 *)p)[SDPCM_WINDOW_OFFSET] & 0xff)
292 #define SDPCM_SWHEADER_LEN 8 /* SW header is 64 bits */
294 /* logical channel numbers */
295 #define SDPCM_CONTROL_CHANNEL 0 /* Control channel Id */
296 #define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication Channel Id */
297 #define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv Channel Id */
298 #define SDPCM_GLOM_CHANNEL 3 /* For coalesced packets */
299 #define SDPCM_TEST_CHANNEL 15 /* Reserved for test/debug packets */
301 #define SDPCM_SEQUENCE_WRAP 256 /* wrap-around val for 8bit frame seq */
303 #define SDPCM_GLOMDESC(p) (((u8 *)p)[1] & 0x80)
306 * Shared structure between dongle and the host.
307 * The structure contains pointers to trap or assert information.
309 #define SDPCM_SHARED_VERSION 0x0002
310 #define SDPCM_SHARED_VERSION_MASK 0x00FF
311 #define SDPCM_SHARED_ASSERT_BUILT 0x0100
312 #define SDPCM_SHARED_ASSERT 0x0200
313 #define SDPCM_SHARED_TRAP 0x0400
315 /* Space for header read, limit for data packets */
316 #define MAX_HDR_READ (1 << 6)
317 #define MAX_RX_DATASZ 2048
319 /* Maximum milliseconds to wait for F2 to come up */
320 #define BRCMF_WAIT_F2RDY 3000
322 /* Bump up limit on waiting for HT to account for first startup;
323 * if the image is doing a CRC calculation before programming the PMU
324 * for HT availability, it could take a couple hundred ms more, so
325 * max out at a 1 second (1000000us).
327 #undef PMU_MAX_TRANSITION_DLY
328 #define PMU_MAX_TRANSITION_DLY 1000000
330 /* Value for ChipClockCSR during initial setup */
331 #define BRCMF_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \
332 SBSDIO_ALP_AVAIL_REQ)
334 /* Flags for SDH calls */
335 #define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED)
338 #define SBIM_IBE 0x20000 /* inbanderror */
339 #define SBIM_TO 0x40000 /* timeout */
340 #define SBIM_BY 0x01800000 /* busy (sonics >= 2.3) */
341 #define SBIM_RJ 0x02000000 /* reject (sonics >= 2.3) */
346 #define SBTML_RESET 0x0001
348 #define SBTML_REJ_MASK 0x0006
350 #define SBTML_REJ 0x0002
351 /* temporary reject, for error recovery */
352 #define SBTML_TMPREJ 0x0004
354 /* Shift to locate the SI control flags in sbtml */
355 #define SBTML_SICF_SHIFT 16
358 #define SBTMH_SERR 0x0001 /* serror */
359 #define SBTMH_INT 0x0002 /* interrupt */
360 #define SBTMH_BUSY 0x0004 /* busy */
361 #define SBTMH_TO 0x0020 /* timeout (sonics >= 2.3) */
363 /* Shift to locate the SI status flags in sbtmh */
364 #define SBTMH_SISF_SHIFT 16
367 #define SBIDL_INIT 0x80 /* initiator */
370 #define SBIDH_RC_MASK 0x000f /* revision code */
371 #define SBIDH_RCE_MASK 0x7000 /* revision code extension field */
372 #define SBIDH_RCE_SHIFT 8
373 #define SBCOREREV(sbidh) \
374 ((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | \
375 ((sbidh) & SBIDH_RC_MASK))
376 #define SBIDH_CC_MASK 0x8ff0 /* core code */
377 #define SBIDH_CC_SHIFT 4
378 #define SBIDH_VC_MASK 0xffff0000 /* vendor code */
379 #define SBIDH_VC_SHIFT 16
382 * Conversion of 802.1D priority to precedence level
384 static uint prio2prec(u32 prio)
386 return (prio == PRIO_8021D_NONE || prio == PRIO_8021D_BE) ?
391 * Core reg address translation.
392 * Both macro's returns a 32 bits byte address on the backplane bus.
394 #define CORE_CC_REG(base, field) \
395 (base + offsetof(struct chipcregs, field))
396 #define CORE_BUS_REG(base, field) \
397 (base + offsetof(struct sdpcmd_regs, field))
398 #define CORE_SB(base, field) \
399 (base + SBCONFIGOFF + offsetof(struct sbconfig, field))
403 u32 corecontrol; /* 0x00, rev8 */
404 u32 corestatus; /* rev8 */
406 u32 biststatus; /* rev8 */
409 u16 pcmciamesportaladdr; /* 0x010, rev8 */
411 u16 pcmciamesportalmask; /* rev8 */
413 u16 pcmciawrframebc; /* rev8 */
415 u16 pcmciaunderflowtimer; /* rev8 */
419 u32 intstatus; /* 0x020, rev8 */
420 u32 hostintmask; /* rev8 */
421 u32 intmask; /* rev8 */
422 u32 sbintstatus; /* rev8 */
423 u32 sbintmask; /* rev8 */
424 u32 funcintmask; /* rev4 */
426 u32 tosbmailbox; /* 0x040, rev8 */
427 u32 tohostmailbox; /* rev8 */
428 u32 tosbmailboxdata; /* rev8 */
429 u32 tohostmailboxdata; /* rev8 */
431 /* synchronized access to registers in SDIO clock domain */
432 u32 sdioaccess; /* 0x050, rev8 */
435 /* PCMCIA frame control */
436 u8 pcmciaframectrl; /* 0x060, rev8 */
438 u8 pcmciawatermark; /* rev8 */
441 /* interrupt batching control */
442 u32 intrcvlazy; /* 0x100, rev8 */
446 u32 cmd52rd; /* 0x110, rev8 */
447 u32 cmd52wr; /* rev8 */
448 u32 cmd53rd; /* rev8 */
449 u32 cmd53wr; /* rev8 */
450 u32 abort; /* rev8 */
451 u32 datacrcerror; /* rev8 */
452 u32 rdoutofsync; /* rev8 */
453 u32 wroutofsync; /* rev8 */
454 u32 writebusy; /* rev8 */
455 u32 readwait; /* rev8 */
456 u32 readterm; /* rev8 */
457 u32 writeterm; /* rev8 */
459 u32 clockctlstatus; /* rev8 */
462 u32 PAD[128]; /* DMA engines */
464 /* SDIO/PCMCIA CIS region */
465 char cis[512]; /* 0x400-0x5ff, rev6 */
467 /* PCMCIA function control registers */
468 char pcmciafcr[256]; /* 0x600-6ff, rev6 */
471 /* PCMCIA backplane access */
472 u16 backplanecsr; /* 0x76E, rev6 */
473 u16 backplaneaddr0; /* rev6 */
474 u16 backplaneaddr1; /* rev6 */
475 u16 backplaneaddr2; /* rev6 */
476 u16 backplaneaddr3; /* rev6 */
477 u16 backplanedata0; /* rev6 */
478 u16 backplanedata1; /* rev6 */
479 u16 backplanedata2; /* rev6 */
480 u16 backplanedata3; /* rev6 */
483 /* sprom "size" & "blank" info */
484 u16 spromstatus; /* 0x7BE, rev2 */
491 /* Device console log buffer state */
492 struct brcmf_console {
493 uint count; /* Poll interval msec counter */
494 uint log_addr; /* Log struct address (fixed) */
495 struct rte_log_le log_le; /* Log struct (host copy) */
496 uint bufsize; /* Size of log buffer */
497 u8 *buf; /* Log buffer (host copy) */
498 uint last; /* Last buffer read index */
502 struct sdpcm_shared {
506 u32 assert_file_addr;
508 u32 console_addr; /* Address of struct rte_console */
513 struct sdpcm_shared_le {
516 __le32 assert_exp_addr;
517 __le32 assert_file_addr;
519 __le32 console_addr; /* Address of struct rte_console */
520 __le32 msgtrace_addr;
525 /* misc chip info needed by some of the routines */
532 u32 buscorebase; /* 32 bits backplane bus address */
541 /* Private data for SDIO bus interaction */
543 struct brcmf_pub *drvr;
545 struct brcmf_sdio_dev *sdiodev; /* sdio device handler */
546 struct chip_info *ci; /* Chip info struct */
547 char *vars; /* Variables (from CIS and/or other) */
548 uint varsz; /* Size of variables buffer */
550 u32 ramsize; /* Size of RAM in SOCRAM (bytes) */
552 u32 hostintmask; /* Copy of Host Interrupt Mask */
553 u32 intstatus; /* Intstatus bits (events) pending */
554 bool dpc_sched; /* Indicates DPC schedule (intrpt rcvd) */
555 bool fcstate; /* State of dongle flow-control */
557 uint blocksize; /* Block size of SDIO transfers */
558 uint roundup; /* Max roundup limit */
560 struct pktq txq; /* Queue length used for flow-control */
561 u8 flowcontrol; /* per prio flow control bitmask */
562 u8 tx_seq; /* Transmit sequence number (next) */
563 u8 tx_max; /* Maximum transmit sequence allowed */
565 u8 hdrbuf[MAX_HDR_READ + BRCMF_SDALIGN];
566 u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */
567 u16 nextlen; /* Next Read Len from last header */
568 u8 rx_seq; /* Receive sequence number (expected) */
569 bool rxskip; /* Skip receive (awaiting NAK ACK) */
571 uint rxbound; /* Rx frames to read before resched */
572 uint txbound; /* Tx frames to send before resched */
575 struct sk_buff *glomd; /* Packet containing glomming descriptor */
576 struct sk_buff *glom; /* Packet chain for glommed superframe */
577 uint glomerr; /* Glom packet read errors */
579 u8 *rxbuf; /* Buffer for receiving control packets */
580 uint rxblen; /* Allocated length of rxbuf */
581 u8 *rxctl; /* Aligned pointer into rxbuf */
582 u8 *databuf; /* Buffer for receiving big glom packet */
583 u8 *dataptr; /* Aligned pointer into databuf */
584 uint rxlen; /* Length of valid data in buffer */
586 u8 sdpcm_ver; /* Bus protocol reported by dongle */
588 bool intr; /* Use interrupts */
589 bool poll; /* Use polling */
590 bool ipend; /* Device interrupt is pending */
591 uint intrcount; /* Count of device interrupt callbacks */
592 uint lastintrs; /* Count as of last watchdog timer */
593 uint spurious; /* Count of spurious interrupts */
594 uint pollrate; /* Ticks between device polls */
595 uint polltick; /* Tick counter */
596 uint pollcnt; /* Count of active polls */
599 uint console_interval;
600 struct brcmf_console console; /* Console output polling support */
601 uint console_addr; /* Console address from shared struct */
604 uint regfails; /* Count of R_REG failures */
606 uint clkstate; /* State of sd and backplane clock(s) */
607 bool activity; /* Activity flag for clock down */
608 s32 idletime; /* Control for activity timeout */
609 s32 idlecount; /* Activity timeout counter */
610 s32 idleclock; /* How to set bus driver when idle */
612 bool use_rxchain; /* If brcmf should use PKT chains */
613 bool sleeping; /* Is SDIO bus sleeping? */
614 bool rxflow_mode; /* Rx flow control mode */
615 bool rxflow; /* Is rx flow control on */
616 bool alp_only; /* Don't use HT clock (ALP only) */
617 /* Field to decide if rx of control frames happen in rxbuf or lb-pool */
620 /* Some additional counters */
621 uint tx_sderrs; /* Count of tx attempts with sd errors */
622 uint fcqueued; /* Tx packets that got queued */
623 uint rxrtx; /* Count of rtx requests (NAK to dongle) */
624 uint rx_toolong; /* Receive frames too long to receive */
625 uint rxc_errors; /* SDIO errors when reading control frames */
626 uint rx_hdrfail; /* SDIO errors on header reads */
627 uint rx_badhdr; /* Bad received headers (roosync?) */
628 uint rx_badseq; /* Mismatched rx sequence number */
629 uint fc_rcvd; /* Number of flow-control events received */
630 uint fc_xoff; /* Number which turned on flow-control */
631 uint fc_xon; /* Number which turned off flow-control */
632 uint rxglomfail; /* Failed deglom attempts */
633 uint rxglomframes; /* Number of glom frames (superframes) */
634 uint rxglompkts; /* Number of packets from glom frames */
635 uint f2rxhdrs; /* Number of header reads */
636 uint f2rxdata; /* Number of frame data reads */
637 uint f2txdata; /* Number of f2 frame writes */
638 uint f1regdata; /* Number of f1 register accesses */
642 bool ctrl_frame_stat;
645 wait_queue_head_t ctrl_wait;
646 wait_queue_head_t dcmd_resp_wait;
648 struct timer_list timer;
649 struct completion watchdog_wait;
650 struct task_struct *watchdog_tsk;
654 struct task_struct *dpc_tsk;
655 struct completion dpc_wait;
657 struct semaphore sdsem;
660 const struct firmware *firmware;
667 u32 sbipsflag; /* initiator port ocp slave flag */
669 u32 sbtpsflag; /* target port ocp slave flag */
671 u32 sbtmerrloga; /* (sonics >= 2.3) */
673 u32 sbtmerrlog; /* (sonics >= 2.3) */
675 u32 sbadmatch3; /* address match3 */
677 u32 sbadmatch2; /* address match2 */
679 u32 sbadmatch1; /* address match1 */
681 u32 sbimstate; /* initiator agent state */
682 u32 sbintvec; /* interrupt mask */
683 u32 sbtmstatelow; /* target state */
684 u32 sbtmstatehigh; /* target state */
685 u32 sbbwa0; /* bandwidth allocation table0 */
687 u32 sbimconfiglow; /* initiator configuration */
688 u32 sbimconfighigh; /* initiator configuration */
689 u32 sbadmatch0; /* address match0 */
691 u32 sbtmconfiglow; /* target configuration */
692 u32 sbtmconfighigh; /* target configuration */
693 u32 sbbconfig; /* broadcast configuration */
695 u32 sbbstate; /* broadcast state */
697 u32 sbactcnfg; /* activate configuration */
699 u32 sbflagst; /* current sbflags */
701 u32 sbidlow; /* identification */
702 u32 sbidhigh; /* identification */
708 #define CLK_PENDING 2 /* Not used yet */
712 static int qcount[NUMPRIO];
713 static int tx_packets[NUMPRIO];
716 #define SDIO_DRIVE_STRENGTH 6 /* in milliamps */
718 #define RETRYCHAN(chan) ((chan) == SDPCM_EVENT_CHANNEL)
720 /* Retry count for register access failures */
721 static const uint retry_limit = 2;
723 /* Limit on rounding up frames */
724 static const uint max_roundup = 512;
728 static void pkt_align(struct sk_buff *p, int len, int align)
731 datalign = (unsigned long)(p->data);
732 datalign = roundup(datalign, (align)) - datalign;
734 skb_pull(p, datalign);
738 /* To check if there's window offered */
739 static bool data_ok(struct brcmf_bus *bus)
741 return (u8)(bus->tx_max - bus->tx_seq) != 0 &&
742 ((u8)(bus->tx_max - bus->tx_seq) & 0x80) == 0;
746 * Reads a register in the SDIO hardware block. This block occupies a series of
747 * adresses on the 32 bit backplane bus.
750 r_sdreg32(struct brcmf_bus *bus, u32 *regvar, u32 reg_offset, u32 *retryvar)
754 *regvar = brcmf_sdcard_reg_read(bus->sdiodev,
755 bus->ci->buscorebase + reg_offset, sizeof(u32));
756 } while (brcmf_sdcard_regfail(bus->sdiodev) &&
757 (++(*retryvar) <= retry_limit));
759 bus->regfails += (*retryvar-1);
760 if (*retryvar > retry_limit) {
761 brcmf_dbg(ERROR, "FAILED READ %Xh\n", reg_offset);
768 w_sdreg32(struct brcmf_bus *bus, u32 regval, u32 reg_offset, u32 *retryvar)
772 brcmf_sdcard_reg_write(bus->sdiodev,
773 bus->ci->buscorebase + reg_offset,
774 sizeof(u32), regval);
775 } while (brcmf_sdcard_regfail(bus->sdiodev) &&
776 (++(*retryvar) <= retry_limit));
778 bus->regfails += (*retryvar-1);
779 if (*retryvar > retry_limit)
780 brcmf_dbg(ERROR, "FAILED REGISTER WRITE %Xh\n",
785 #define PKT_AVAILABLE() (intstatus & I_HMB_FRAME_IND)
787 #define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE)
789 /* Packet free applicable unconditionally for sdio and sdspi.
790 * Conditional if bufpool was present for gspi bus.
792 static void brcmf_sdbrcm_pktfree2(struct brcmf_bus *bus, struct sk_buff *pkt)
795 brcmu_pkt_buf_free_skb(pkt);
798 /* Turn backplane clock on or off */
799 static int brcmf_sdbrcm_htclk(struct brcmf_bus *bus, bool on, bool pendok)
802 u8 clkctl, clkreq, devctl;
803 unsigned long timeout;
805 brcmf_dbg(TRACE, "Enter\n");
810 /* Request HT Avail */
812 bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ;
814 if ((bus->ci->chip == BCM4329_CHIP_ID)
815 && (bus->ci->chiprev == 0))
816 clkreq |= SBSDIO_FORCE_ALP;
818 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
819 SBSDIO_FUNC1_CHIPCLKCSR, clkreq, &err);
821 brcmf_dbg(ERROR, "HT Avail request error: %d\n", err);
825 if (pendok && ((bus->ci->buscoretype == PCMCIA_CORE_ID)
826 && (bus->ci->buscorerev == 9))) {
828 r_sdreg32(bus, &dummy,
829 offsetof(struct sdpcmd_regs, clockctlstatus),
833 /* Check current status */
834 clkctl = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
835 SBSDIO_FUNC1_CHIPCLKCSR, &err);
837 brcmf_dbg(ERROR, "HT Avail read error: %d\n", err);
841 /* Go to pending and await interrupt if appropriate */
842 if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) {
843 /* Allow only clock-available interrupt */
844 devctl = brcmf_sdcard_cfg_read(bus->sdiodev,
846 SBSDIO_DEVICE_CTL, &err);
848 brcmf_dbg(ERROR, "Devctl error setting CA: %d\n",
853 devctl |= SBSDIO_DEVCTL_CA_INT_ONLY;
854 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
855 SBSDIO_DEVICE_CTL, devctl, &err);
856 brcmf_dbg(INFO, "CLKCTL: set PENDING\n");
857 bus->clkstate = CLK_PENDING;
860 } else if (bus->clkstate == CLK_PENDING) {
861 /* Cancel CA-only interrupt filter */
863 brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
864 SBSDIO_DEVICE_CTL, &err);
865 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
866 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
867 SBSDIO_DEVICE_CTL, devctl, &err);
870 /* Otherwise, wait here (polling) for HT Avail */
872 msecs_to_jiffies(PMU_MAX_TRANSITION_DLY/1000);
873 while (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
874 clkctl = brcmf_sdcard_cfg_read(bus->sdiodev,
876 SBSDIO_FUNC1_CHIPCLKCSR,
878 if (time_after(jiffies, timeout))
881 usleep_range(5000, 10000);
884 brcmf_dbg(ERROR, "HT Avail request error: %d\n", err);
887 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
888 brcmf_dbg(ERROR, "HT Avail timeout (%d): clkctl 0x%02x\n",
889 PMU_MAX_TRANSITION_DLY, clkctl);
893 /* Mark clock available */
894 bus->clkstate = CLK_AVAIL;
895 brcmf_dbg(INFO, "CLKCTL: turned ON\n");
898 if (bus->alp_only != true) {
899 if (SBSDIO_ALPONLY(clkctl))
900 brcmf_dbg(ERROR, "HT Clock should be on\n");
902 #endif /* defined (BCMDBG) */
904 bus->activity = true;
908 if (bus->clkstate == CLK_PENDING) {
909 /* Cancel CA-only interrupt filter */
910 devctl = brcmf_sdcard_cfg_read(bus->sdiodev,
912 SBSDIO_DEVICE_CTL, &err);
913 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
914 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
915 SBSDIO_DEVICE_CTL, devctl, &err);
918 bus->clkstate = CLK_SDONLY;
919 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
920 SBSDIO_FUNC1_CHIPCLKCSR, clkreq, &err);
921 brcmf_dbg(INFO, "CLKCTL: turned OFF\n");
923 brcmf_dbg(ERROR, "Failed access turning clock off: %d\n",
931 /* Change idle/active SD state */
932 static int brcmf_sdbrcm_sdclk(struct brcmf_bus *bus, bool on)
934 brcmf_dbg(TRACE, "Enter\n");
937 bus->clkstate = CLK_SDONLY;
939 bus->clkstate = CLK_NONE;
944 /* Transition SD and backplane clock readiness */
945 static int brcmf_sdbrcm_clkctl(struct brcmf_bus *bus, uint target, bool pendok)
948 uint oldstate = bus->clkstate;
951 brcmf_dbg(TRACE, "Enter\n");
953 /* Early exit if we're already there */
954 if (bus->clkstate == target) {
955 if (target == CLK_AVAIL) {
956 brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
957 bus->activity = true;
964 /* Make sure SD clock is available */
965 if (bus->clkstate == CLK_NONE)
966 brcmf_sdbrcm_sdclk(bus, true);
967 /* Now request HT Avail on the backplane */
968 brcmf_sdbrcm_htclk(bus, true, pendok);
969 brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
970 bus->activity = true;
974 /* Remove HT request, or bring up SD clock */
975 if (bus->clkstate == CLK_NONE)
976 brcmf_sdbrcm_sdclk(bus, true);
977 else if (bus->clkstate == CLK_AVAIL)
978 brcmf_sdbrcm_htclk(bus, false, false);
980 brcmf_dbg(ERROR, "request for %d -> %d\n",
981 bus->clkstate, target);
982 brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
986 /* Make sure to remove HT request */
987 if (bus->clkstate == CLK_AVAIL)
988 brcmf_sdbrcm_htclk(bus, false, false);
989 /* Now remove the SD clock */
990 brcmf_sdbrcm_sdclk(bus, false);
991 brcmf_sdbrcm_wd_timer(bus, 0);
995 brcmf_dbg(INFO, "%d -> %d\n", oldstate, bus->clkstate);
1001 static int brcmf_sdbrcm_bussleep(struct brcmf_bus *bus, bool sleep)
1005 brcmf_dbg(INFO, "request %s (currently %s)\n",
1006 sleep ? "SLEEP" : "WAKE",
1007 bus->sleeping ? "SLEEP" : "WAKE");
1009 /* Done if we're already in the requested state */
1010 if (sleep == bus->sleeping)
1013 /* Going to sleep: set the alarm and turn off the lights... */
1015 /* Don't sleep if something is pending */
1016 if (bus->dpc_sched || bus->rxskip || pktq_len(&bus->txq))
1019 /* Make sure the controller has the bus up */
1020 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
1022 /* Tell device to start using OOB wakeup */
1023 w_sdreg32(bus, SMB_USE_OOB,
1024 offsetof(struct sdpcmd_regs, tosbmailbox), &retries);
1025 if (retries > retry_limit)
1026 brcmf_dbg(ERROR, "CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n");
1028 /* Turn off our contribution to the HT clock request */
1029 brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
1031 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
1032 SBSDIO_FUNC1_CHIPCLKCSR,
1033 SBSDIO_FORCE_HW_CLKREQ_OFF, NULL);
1035 /* Isolate the bus */
1036 if (bus->ci->chip != BCM4329_CHIP_ID) {
1037 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
1039 SBSDIO_DEVCTL_PADS_ISO, NULL);
1043 bus->sleeping = true;
1046 /* Waking up: bus power up is ok, set local state */
1048 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
1049 SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
1051 /* Force pad isolation off if possible
1052 (in case power never toggled) */
1053 if ((bus->ci->buscoretype == PCMCIA_CORE_ID)
1054 && (bus->ci->buscorerev >= 10))
1055 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
1056 SBSDIO_DEVICE_CTL, 0, NULL);
1058 /* Make sure the controller has the bus up */
1059 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
1061 /* Send misc interrupt to indicate OOB not needed */
1062 w_sdreg32(bus, 0, offsetof(struct sdpcmd_regs, tosbmailboxdata),
1064 if (retries <= retry_limit)
1065 w_sdreg32(bus, SMB_DEV_INT,
1066 offsetof(struct sdpcmd_regs, tosbmailbox),
1069 if (retries > retry_limit)
1070 brcmf_dbg(ERROR, "CANNOT SIGNAL CHIP TO CLEAR OOB!!\n");
1072 /* Make sure we have SD bus access */
1073 brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
1076 bus->sleeping = false;
1082 static void bus_wake(struct brcmf_bus *bus)
1085 brcmf_sdbrcm_bussleep(bus, false);
1088 static u32 brcmf_sdbrcm_hostmail(struct brcmf_bus *bus)
1095 brcmf_dbg(TRACE, "Enter\n");
1097 /* Read mailbox data and ack that we did so */
1098 r_sdreg32(bus, &hmb_data,
1099 offsetof(struct sdpcmd_regs, tohostmailboxdata), &retries);
1101 if (retries <= retry_limit)
1102 w_sdreg32(bus, SMB_INT_ACK,
1103 offsetof(struct sdpcmd_regs, tosbmailbox), &retries);
1104 bus->f1regdata += 2;
1106 /* Dongle recomposed rx frames, accept them again */
1107 if (hmb_data & HMB_DATA_NAKHANDLED) {
1108 brcmf_dbg(INFO, "Dongle reports NAK handled, expect rtx of %d\n",
1111 brcmf_dbg(ERROR, "unexpected NAKHANDLED!\n");
1113 bus->rxskip = false;
1114 intstatus |= I_HMB_FRAME_IND;
1118 * DEVREADY does not occur with gSPI.
1120 if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) {
1122 (hmb_data & HMB_DATA_VERSION_MASK) >>
1123 HMB_DATA_VERSION_SHIFT;
1124 if (bus->sdpcm_ver != SDPCM_PROT_VERSION)
1125 brcmf_dbg(ERROR, "Version mismatch, dongle reports %d, "
1127 bus->sdpcm_ver, SDPCM_PROT_VERSION);
1129 brcmf_dbg(INFO, "Dongle ready, protocol version %d\n",
1134 * Flow Control has been moved into the RX headers and this out of band
1135 * method isn't used any more.
1136 * remaining backward compatible with older dongles.
1138 if (hmb_data & HMB_DATA_FC) {
1139 fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >>
1140 HMB_DATA_FCDATA_SHIFT;
1142 if (fcbits & ~bus->flowcontrol)
1145 if (bus->flowcontrol & ~fcbits)
1149 bus->flowcontrol = fcbits;
1152 /* Shouldn't be any others */
1153 if (hmb_data & ~(HMB_DATA_DEVREADY |
1154 HMB_DATA_NAKHANDLED |
1157 HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK))
1158 brcmf_dbg(ERROR, "Unknown mailbox data content: 0x%02x\n",
1164 static void brcmf_sdbrcm_rxfail(struct brcmf_bus *bus, bool abort, bool rtx)
1171 brcmf_dbg(ERROR, "%sterminate frame%s\n",
1172 abort ? "abort command, " : "",
1173 rtx ? ", send NAK" : "");
1176 brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
1178 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
1179 SBSDIO_FUNC1_FRAMECTRL,
1183 /* Wait until the packet has been flushed (device/FIFO stable) */
1184 for (lastrbc = retries = 0xffff; retries > 0; retries--) {
1185 hi = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
1186 SBSDIO_FUNC1_RFRAMEBCHI, NULL);
1187 lo = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
1188 SBSDIO_FUNC1_RFRAMEBCLO, NULL);
1189 bus->f1regdata += 2;
1191 if ((hi == 0) && (lo == 0))
1194 if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) {
1195 brcmf_dbg(ERROR, "count growing: last 0x%04x now 0x%04x\n",
1196 lastrbc, (hi << 8) + lo);
1198 lastrbc = (hi << 8) + lo;
1202 brcmf_dbg(ERROR, "count never zeroed: last 0x%04x\n", lastrbc);
1204 brcmf_dbg(INFO, "flush took %d iterations\n", 0xffff - retries);
1208 w_sdreg32(bus, SMB_NAK,
1209 offsetof(struct sdpcmd_regs, tosbmailbox), &retries);
1212 if (retries <= retry_limit)
1216 /* Clear partial in any case */
1219 /* If we can't reach the device, signal failure */
1220 if (err || brcmf_sdcard_regfail(bus->sdiodev))
1221 bus->drvr->busstate = BRCMF_BUS_DOWN;
1224 static u8 brcmf_sdbrcm_rxglom(struct brcmf_bus *bus, u8 rxseq)
1230 struct sk_buff *pfirst, *plast, *pnext, *save_pfirst;
1233 u8 chan, seq, doff, sfdoff;
1237 bool usechain = bus->use_rxchain;
1239 /* If packets, issue read(s) and send up packet chain */
1240 /* Return sequence numbers consumed? */
1242 brcmf_dbg(TRACE, "start: glomd %p glom %p\n", bus->glomd, bus->glom);
1244 /* If there's a descriptor, generate the packet chain */
1246 pfirst = plast = pnext = NULL;
1247 dlen = (u16) (bus->glomd->len);
1248 dptr = bus->glomd->data;
1249 if (!dlen || (dlen & 1)) {
1250 brcmf_dbg(ERROR, "bad glomd len(%d), ignore descriptor\n",
1255 for (totlen = num = 0; dlen; num++) {
1256 /* Get (and move past) next length */
1257 sublen = get_unaligned_le16(dptr);
1258 dlen -= sizeof(u16);
1259 dptr += sizeof(u16);
1260 if ((sublen < SDPCM_HDRLEN) ||
1261 ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) {
1262 brcmf_dbg(ERROR, "descriptor len %d bad: %d\n",
1267 if (sublen % BRCMF_SDALIGN) {
1268 brcmf_dbg(ERROR, "sublen %d not multiple of %d\n",
1269 sublen, BRCMF_SDALIGN);
1274 /* For last frame, adjust read len so total
1275 is a block multiple */
1278 (roundup(totlen, bus->blocksize) - totlen);
1279 totlen = roundup(totlen, bus->blocksize);
1282 /* Allocate/chain packet for next subframe */
1283 pnext = brcmu_pkt_buf_get_skb(sublen + BRCMF_SDALIGN);
1284 if (pnext == NULL) {
1285 brcmf_dbg(ERROR, "bcm_pkt_buf_get_skb failed, num %d len %d\n",
1290 pfirst = plast = pnext;
1292 plast->next = pnext;
1296 /* Adhere to start alignment requirements */
1297 pkt_align(pnext, sublen, BRCMF_SDALIGN);
1300 /* If all allocations succeeded, save packet chain
1303 brcmf_dbg(GLOM, "allocated %d-byte packet chain for %d subframes\n",
1305 if (BRCMF_GLOM_ON() && bus->nextlen &&
1306 totlen != bus->nextlen) {
1307 brcmf_dbg(GLOM, "glomdesc mismatch: nextlen %d glomdesc %d rxseq %d\n",
1308 bus->nextlen, totlen, rxseq);
1311 pfirst = pnext = NULL;
1314 brcmu_pkt_buf_free_skb(pfirst);
1319 /* Done with descriptor packet */
1320 brcmu_pkt_buf_free_skb(bus->glomd);
1325 /* Ok -- either we just generated a packet chain,
1326 or had one from before */
1328 if (BRCMF_GLOM_ON()) {
1329 brcmf_dbg(GLOM, "try superframe read, packet chain:\n");
1330 for (pnext = bus->glom; pnext; pnext = pnext->next) {
1331 brcmf_dbg(GLOM, " %p: %p len 0x%04x (%d)\n",
1332 pnext, (u8 *) (pnext->data),
1333 pnext->len, pnext->len);
1338 dlen = (u16) brcmu_pkttotlen(pfirst);
1340 /* Do an SDIO read for the superframe. Configurable iovar to
1341 * read directly into the chained packet, or allocate a large
1342 * packet and and copy into the chain.
1345 errcode = brcmf_sdcard_recv_buf(bus->sdiodev,
1346 bus->sdiodev->sbwad,
1348 F2SYNC, (u8 *) pfirst->data, dlen,
1350 } else if (bus->dataptr) {
1351 errcode = brcmf_sdcard_recv_buf(bus->sdiodev,
1352 bus->sdiodev->sbwad,
1354 F2SYNC, bus->dataptr, dlen,
1356 sublen = (u16) brcmu_pktfrombuf(pfirst, 0, dlen,
1358 if (sublen != dlen) {
1359 brcmf_dbg(ERROR, "FAILED TO COPY, dlen %d sublen %d\n",
1365 brcmf_dbg(ERROR, "COULDN'T ALLOC %d-BYTE GLOM, FORCE FAILURE\n",
1371 /* On failure, kill the superframe, allow a couple retries */
1373 brcmf_dbg(ERROR, "glom read of %d bytes failed: %d\n",
1375 bus->drvr->rx_errors++;
1377 if (bus->glomerr++ < 3) {
1378 brcmf_sdbrcm_rxfail(bus, true, true);
1381 brcmf_sdbrcm_rxfail(bus, true, false);
1382 brcmu_pkt_buf_free_skb(bus->glom);
1389 if (BRCMF_GLOM_ON()) {
1390 printk(KERN_DEBUG "SUPERFRAME:\n");
1391 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1392 pfirst->data, min_t(int, pfirst->len, 48));
1396 /* Validate the superframe header */
1397 dptr = (u8 *) (pfirst->data);
1398 sublen = get_unaligned_le16(dptr);
1399 check = get_unaligned_le16(dptr + sizeof(u16));
1401 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
1402 seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
1403 bus->nextlen = dptr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
1404 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
1405 brcmf_dbg(INFO, "nextlen too large (%d) seq %d\n",
1409 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
1410 txmax = SDPCM_WINDOW_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
1413 if ((u16)~(sublen ^ check)) {
1414 brcmf_dbg(ERROR, "(superframe): HW hdr error: len/check 0x%04x/0x%04x\n",
1417 } else if (roundup(sublen, bus->blocksize) != dlen) {
1418 brcmf_dbg(ERROR, "(superframe): len 0x%04x, rounded 0x%04x, expect 0x%04x\n",
1419 sublen, roundup(sublen, bus->blocksize),
1422 } else if (SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]) !=
1423 SDPCM_GLOM_CHANNEL) {
1424 brcmf_dbg(ERROR, "(superframe): bad channel %d\n",
1425 SDPCM_PACKET_CHANNEL(
1426 &dptr[SDPCM_FRAMETAG_LEN]));
1428 } else if (SDPCM_GLOMDESC(&dptr[SDPCM_FRAMETAG_LEN])) {
1429 brcmf_dbg(ERROR, "(superframe): got 2nd descriptor?\n");
1431 } else if ((doff < SDPCM_HDRLEN) ||
1432 (doff > (pfirst->len - SDPCM_HDRLEN))) {
1433 brcmf_dbg(ERROR, "(superframe): Bad data offset %d: HW %d pkt %d min %d\n",
1434 doff, sublen, pfirst->len, SDPCM_HDRLEN);
1438 /* Check sequence number of superframe SW header */
1440 brcmf_dbg(INFO, "(superframe) rx_seq %d, expected %d\n",
1446 /* Check window for sanity */
1447 if ((u8) (txmax - bus->tx_seq) > 0x40) {
1448 brcmf_dbg(ERROR, "unlikely tx max %d with tx_seq %d\n",
1449 txmax, bus->tx_seq);
1450 txmax = bus->tx_seq + 2;
1452 bus->tx_max = txmax;
1454 /* Remove superframe header, remember offset */
1455 skb_pull(pfirst, doff);
1458 /* Validate all the subframe headers */
1459 for (num = 0, pnext = pfirst; pnext && !errcode;
1460 num++, pnext = pnext->next) {
1461 dptr = (u8 *) (pnext->data);
1462 dlen = (u16) (pnext->len);
1463 sublen = get_unaligned_le16(dptr);
1464 check = get_unaligned_le16(dptr + sizeof(u16));
1465 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
1466 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
1468 if (BRCMF_GLOM_ON()) {
1469 printk(KERN_DEBUG "subframe:\n");
1470 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1475 if ((u16)~(sublen ^ check)) {
1476 brcmf_dbg(ERROR, "(subframe %d): HW hdr error: len/check 0x%04x/0x%04x\n",
1477 num, sublen, check);
1479 } else if ((sublen > dlen) || (sublen < SDPCM_HDRLEN)) {
1480 brcmf_dbg(ERROR, "(subframe %d): length mismatch: len 0x%04x, expect 0x%04x\n",
1483 } else if ((chan != SDPCM_DATA_CHANNEL) &&
1484 (chan != SDPCM_EVENT_CHANNEL)) {
1485 brcmf_dbg(ERROR, "(subframe %d): bad channel %d\n",
1488 } else if ((doff < SDPCM_HDRLEN) || (doff > sublen)) {
1489 brcmf_dbg(ERROR, "(subframe %d): Bad data offset %d: HW %d min %d\n",
1490 num, doff, sublen, SDPCM_HDRLEN);
1496 /* Terminate frame on error, request
1498 if (bus->glomerr++ < 3) {
1499 /* Restore superframe header space */
1500 skb_push(pfirst, sfdoff);
1501 brcmf_sdbrcm_rxfail(bus, true, true);
1504 brcmf_sdbrcm_rxfail(bus, true, false);
1505 brcmu_pkt_buf_free_skb(bus->glom);
1513 /* Basic SD framing looks ok - process each packet (header) */
1514 save_pfirst = pfirst;
1518 for (num = 0; pfirst; rxseq++, pfirst = pnext) {
1519 pnext = pfirst->next;
1520 pfirst->next = NULL;
1522 dptr = (u8 *) (pfirst->data);
1523 sublen = get_unaligned_le16(dptr);
1524 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
1525 seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
1526 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
1528 brcmf_dbg(GLOM, "Get subframe %d, %p(%p/%d), sublen %d chan %d seq %d\n",
1529 num, pfirst, pfirst->data,
1530 pfirst->len, sublen, chan, seq);
1532 /* precondition: chan == SDPCM_DATA_CHANNEL ||
1533 chan == SDPCM_EVENT_CHANNEL */
1536 brcmf_dbg(GLOM, "rx_seq %d, expected %d\n",
1542 if (BRCMF_BYTES_ON() && BRCMF_DATA_ON()) {
1543 printk(KERN_DEBUG "Rx Subframe Data:\n");
1544 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1549 __skb_trim(pfirst, sublen);
1550 skb_pull(pfirst, doff);
1552 if (pfirst->len == 0) {
1553 brcmu_pkt_buf_free_skb(pfirst);
1555 plast->next = pnext;
1557 save_pfirst = pnext;
1560 } else if (brcmf_proto_hdrpull(bus->drvr, &ifidx,
1562 brcmf_dbg(ERROR, "rx protocol error\n");
1563 bus->drvr->rx_errors++;
1564 brcmu_pkt_buf_free_skb(pfirst);
1566 plast->next = pnext;
1568 save_pfirst = pnext;
1573 /* this packet will go up, link back into
1574 chain and count it */
1575 pfirst->next = pnext;
1580 if (BRCMF_GLOM_ON()) {
1581 brcmf_dbg(GLOM, "subframe %d to stack, %p (%p/%d) nxt/lnk %p/%p\n",
1582 num, pfirst, pfirst->data,
1583 pfirst->len, pfirst->next,
1585 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1587 min_t(int, pfirst->len, 32));
1593 brcmf_rx_frame(bus->drvr, ifidx, save_pfirst, num);
1597 bus->rxglomframes++;
1598 bus->rxglompkts += num;
1603 static int brcmf_sdbrcm_dcmd_resp_wait(struct brcmf_bus *bus, uint *condition,
1606 DECLARE_WAITQUEUE(wait, current);
1607 int timeout = msecs_to_jiffies(DCMD_RESP_TIMEOUT);
1609 /* Wait until control frame is available */
1610 add_wait_queue(&bus->dcmd_resp_wait, &wait);
1611 set_current_state(TASK_INTERRUPTIBLE);
1613 while (!(*condition) && (!signal_pending(current) && timeout))
1614 timeout = schedule_timeout(timeout);
1616 if (signal_pending(current))
1619 set_current_state(TASK_RUNNING);
1620 remove_wait_queue(&bus->dcmd_resp_wait, &wait);
1625 static int brcmf_sdbrcm_dcmd_resp_wake(struct brcmf_bus *bus)
1627 if (waitqueue_active(&bus->dcmd_resp_wait))
1628 wake_up_interruptible(&bus->dcmd_resp_wait);
1633 brcmf_sdbrcm_read_control(struct brcmf_bus *bus, u8 *hdr, uint len, uint doff)
1639 brcmf_dbg(TRACE, "Enter\n");
1641 /* Set rxctl for frame (w/optional alignment) */
1642 bus->rxctl = bus->rxbuf;
1643 bus->rxctl += BRCMF_FIRSTREAD;
1644 pad = ((unsigned long)bus->rxctl % BRCMF_SDALIGN);
1646 bus->rxctl += (BRCMF_SDALIGN - pad);
1647 bus->rxctl -= BRCMF_FIRSTREAD;
1649 /* Copy the already-read portion over */
1650 memcpy(bus->rxctl, hdr, BRCMF_FIRSTREAD);
1651 if (len <= BRCMF_FIRSTREAD)
1654 /* Raise rdlen to next SDIO block to avoid tail command */
1655 rdlen = len - BRCMF_FIRSTREAD;
1656 if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) {
1657 pad = bus->blocksize - (rdlen % bus->blocksize);
1658 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
1659 ((len + pad) < bus->drvr->maxctl))
1661 } else if (rdlen % BRCMF_SDALIGN) {
1662 rdlen += BRCMF_SDALIGN - (rdlen % BRCMF_SDALIGN);
1665 /* Satisfy length-alignment requirements */
1666 if (rdlen & (ALIGNMENT - 1))
1667 rdlen = roundup(rdlen, ALIGNMENT);
1669 /* Drop if the read is too big or it exceeds our maximum */
1670 if ((rdlen + BRCMF_FIRSTREAD) > bus->drvr->maxctl) {
1671 brcmf_dbg(ERROR, "%d-byte control read exceeds %d-byte buffer\n",
1672 rdlen, bus->drvr->maxctl);
1673 bus->drvr->rx_errors++;
1674 brcmf_sdbrcm_rxfail(bus, false, false);
1678 if ((len - doff) > bus->drvr->maxctl) {
1679 brcmf_dbg(ERROR, "%d-byte ctl frame (%d-byte ctl data) exceeds %d-byte limit\n",
1680 len, len - doff, bus->drvr->maxctl);
1681 bus->drvr->rx_errors++;
1683 brcmf_sdbrcm_rxfail(bus, false, false);
1687 /* Read remainder of frame body into the rxctl buffer */
1688 sdret = brcmf_sdcard_recv_buf(bus->sdiodev,
1689 bus->sdiodev->sbwad,
1691 F2SYNC, (bus->rxctl + BRCMF_FIRSTREAD), rdlen,
1695 /* Control frame failures need retransmission */
1697 brcmf_dbg(ERROR, "read %d control bytes failed: %d\n",
1700 brcmf_sdbrcm_rxfail(bus, true, true);
1707 if (BRCMF_BYTES_ON() && BRCMF_CTL_ON()) {
1708 printk(KERN_DEBUG "RxCtrl:\n");
1709 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, bus->rxctl, len);
1713 /* Point to valid data and indicate its length */
1715 bus->rxlen = len - doff;
1718 /* Awake any waiters */
1719 brcmf_sdbrcm_dcmd_resp_wake(bus);
1722 /* Pad read to blocksize for efficiency */
1723 static void brcmf_pad(struct brcmf_bus *bus, u16 *pad, u16 *rdlen)
1725 if (bus->roundup && bus->blocksize && *rdlen > bus->blocksize) {
1726 *pad = bus->blocksize - (*rdlen % bus->blocksize);
1727 if (*pad <= bus->roundup && *pad < bus->blocksize &&
1728 *rdlen + *pad + BRCMF_FIRSTREAD < MAX_RX_DATASZ)
1730 } else if (*rdlen % BRCMF_SDALIGN) {
1731 *rdlen += BRCMF_SDALIGN - (*rdlen % BRCMF_SDALIGN);
1736 brcmf_alloc_pkt_and_read(struct brcmf_bus *bus, u16 rdlen,
1737 struct sk_buff **pkt, u8 **rxbuf)
1739 int sdret; /* Return code from calls */
1741 *pkt = brcmu_pkt_buf_get_skb(rdlen + BRCMF_SDALIGN);
1745 pkt_align(*pkt, rdlen, BRCMF_SDALIGN);
1746 *rxbuf = (u8 *) ((*pkt)->data);
1747 /* Read the entire frame */
1748 sdret = brcmf_sdcard_recv_buf(bus->sdiodev, bus->sdiodev->sbwad,
1749 SDIO_FUNC_2, F2SYNC,
1750 *rxbuf, rdlen, *pkt);
1754 brcmf_dbg(ERROR, "(nextlen): read %d bytes failed: %d\n",
1756 brcmu_pkt_buf_free_skb(*pkt);
1757 bus->drvr->rx_errors++;
1758 /* Force retry w/normal header read.
1759 * Don't attempt NAK for
1762 brcmf_sdbrcm_rxfail(bus, true, true);
1767 /* Checks the header */
1769 brcmf_check_rxbuf(struct brcmf_bus *bus, struct sk_buff *pkt, u8 *rxbuf,
1770 u8 rxseq, u16 nextlen, u16 *len)
1773 bool len_consistent; /* Result of comparing readahead len and
1776 memcpy(bus->rxhdr, rxbuf, SDPCM_HDRLEN);
1778 /* Extract hardware header fields */
1779 *len = get_unaligned_le16(bus->rxhdr);
1780 check = get_unaligned_le16(bus->rxhdr + sizeof(u16));
1782 /* All zeros means readahead info was bad */
1783 if (!(*len | check)) {
1784 brcmf_dbg(INFO, "(nextlen): read zeros in HW header???\n");
1788 /* Validate check bytes */
1789 if ((u16)~(*len ^ check)) {
1790 brcmf_dbg(ERROR, "(nextlen): HW hdr error: nextlen/len/check 0x%04x/0x%04x/0x%04x\n",
1791 nextlen, *len, check);
1793 brcmf_sdbrcm_rxfail(bus, false, false);
1797 /* Validate frame length */
1798 if (*len < SDPCM_HDRLEN) {
1799 brcmf_dbg(ERROR, "(nextlen): HW hdr length invalid: %d\n",
1804 /* Check for consistency with readahead info */
1805 len_consistent = (nextlen != (roundup(*len, 16) >> 4));
1806 if (len_consistent) {
1807 /* Mismatch, force retry w/normal
1808 header (may be >4K) */
1809 brcmf_dbg(ERROR, "(nextlen): mismatch, nextlen %d len %d rnd %d; expected rxseq %d\n",
1810 nextlen, *len, roundup(*len, 16),
1812 brcmf_sdbrcm_rxfail(bus, true, true);
1819 brcmf_sdbrcm_pktfree2(bus, pkt);
1823 /* Return true if there may be more frames to read */
1825 brcmf_sdbrcm_readframes(struct brcmf_bus *bus, uint maxframes, bool *finished)
1827 u16 len, check; /* Extracted hardware header fields */
1828 u8 chan, seq, doff; /* Extracted software header fields */
1829 u8 fcbits; /* Extracted fcbits from software header */
1831 struct sk_buff *pkt; /* Packet for event or data frames */
1832 u16 pad; /* Number of pad bytes to read */
1833 u16 rdlen; /* Total number of bytes to read */
1834 u8 rxseq; /* Next sequence number to expect */
1835 uint rxleft = 0; /* Remaining number of frames allowed */
1836 int sdret; /* Return code from calls */
1837 u8 txmax; /* Maximum tx sequence offered */
1840 uint rxcount = 0; /* Total frames read */
1842 brcmf_dbg(TRACE, "Enter\n");
1844 /* Not finished unless we encounter no more frames indication */
1847 for (rxseq = bus->rx_seq, rxleft = maxframes;
1848 !bus->rxskip && rxleft && bus->drvr->busstate != BRCMF_BUS_DOWN;
1849 rxseq++, rxleft--) {
1851 /* Handle glomming separately */
1852 if (bus->glom || bus->glomd) {
1854 brcmf_dbg(GLOM, "calling rxglom: glomd %p, glom %p\n",
1855 bus->glomd, bus->glom);
1856 cnt = brcmf_sdbrcm_rxglom(bus, rxseq);
1857 brcmf_dbg(GLOM, "rxglom returned %d\n", cnt);
1859 rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1;
1863 /* Try doing single read if we can */
1865 u16 nextlen = bus->nextlen;
1868 rdlen = len = nextlen << 4;
1869 brcmf_pad(bus, &pad, &rdlen);
1872 * After the frame is received we have to
1873 * distinguish whether it is data
1874 * or non-data frame.
1876 brcmf_alloc_pkt_and_read(bus, rdlen, &pkt, &rxbuf);
1878 /* Give up on data, request rtx of events */
1879 brcmf_dbg(ERROR, "(nextlen): brcmf_alloc_pkt_and_read failed: len %d rdlen %d expected rxseq %d\n",
1884 if (brcmf_check_rxbuf(bus, pkt, rxbuf, rxseq, nextlen,
1888 /* Extract software header fields */
1889 chan = SDPCM_PACKET_CHANNEL(
1890 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
1891 seq = SDPCM_PACKET_SEQUENCE(
1892 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
1893 doff = SDPCM_DOFFSET_VALUE(
1894 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
1895 txmax = SDPCM_WINDOW_VALUE(
1896 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
1899 bus->rxhdr[SDPCM_FRAMETAG_LEN +
1900 SDPCM_NEXTLEN_OFFSET];
1901 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
1902 brcmf_dbg(INFO, "(nextlen): got frame w/nextlen too large (%d), seq %d\n",
1907 bus->drvr->rx_readahead_cnt++;
1909 /* Handle Flow Control */
1910 fcbits = SDPCM_FCMASK_VALUE(
1911 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
1913 if (bus->flowcontrol != fcbits) {
1914 if (~bus->flowcontrol & fcbits)
1917 if (bus->flowcontrol & ~fcbits)
1921 bus->flowcontrol = fcbits;
1924 /* Check and update sequence number */
1926 brcmf_dbg(INFO, "(nextlen): rx_seq %d, expected %d\n",
1932 /* Check window for sanity */
1933 if ((u8) (txmax - bus->tx_seq) > 0x40) {
1934 brcmf_dbg(ERROR, "got unlikely tx max %d with tx_seq %d\n",
1935 txmax, bus->tx_seq);
1936 txmax = bus->tx_seq + 2;
1938 bus->tx_max = txmax;
1941 if (BRCMF_BYTES_ON() && BRCMF_DATA_ON()) {
1942 printk(KERN_DEBUG "Rx Data:\n");
1943 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1945 } else if (BRCMF_HDRS_ON()) {
1946 printk(KERN_DEBUG "RxHdr:\n");
1947 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1948 bus->rxhdr, SDPCM_HDRLEN);
1952 if (chan == SDPCM_CONTROL_CHANNEL) {
1953 brcmf_dbg(ERROR, "(nextlen): readahead on control packet %d?\n",
1955 /* Force retry w/normal header read */
1957 brcmf_sdbrcm_rxfail(bus, false, true);
1958 brcmf_sdbrcm_pktfree2(bus, pkt);
1962 /* Validate data offset */
1963 if ((doff < SDPCM_HDRLEN) || (doff > len)) {
1964 brcmf_dbg(ERROR, "(nextlen): bad data offset %d: HW len %d min %d\n",
1965 doff, len, SDPCM_HDRLEN);
1966 brcmf_sdbrcm_rxfail(bus, false, false);
1967 brcmf_sdbrcm_pktfree2(bus, pkt);
1971 /* All done with this one -- now deliver the packet */
1975 /* Read frame header (hardware and software) */
1976 sdret = brcmf_sdcard_recv_buf(bus->sdiodev, bus->sdiodev->sbwad,
1977 SDIO_FUNC_2, F2SYNC, bus->rxhdr,
1978 BRCMF_FIRSTREAD, NULL);
1982 brcmf_dbg(ERROR, "RXHEADER FAILED: %d\n", sdret);
1984 brcmf_sdbrcm_rxfail(bus, true, true);
1988 if (BRCMF_BYTES_ON() || BRCMF_HDRS_ON()) {
1989 printk(KERN_DEBUG "RxHdr:\n");
1990 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1991 bus->rxhdr, SDPCM_HDRLEN);
1995 /* Extract hardware header fields */
1996 len = get_unaligned_le16(bus->rxhdr);
1997 check = get_unaligned_le16(bus->rxhdr + sizeof(u16));
1999 /* All zeros means no more frames */
2000 if (!(len | check)) {
2005 /* Validate check bytes */
2006 if ((u16) ~(len ^ check)) {
2007 brcmf_dbg(ERROR, "HW hdr err: len/check 0x%04x/0x%04x\n",
2010 brcmf_sdbrcm_rxfail(bus, false, false);
2014 /* Validate frame length */
2015 if (len < SDPCM_HDRLEN) {
2016 brcmf_dbg(ERROR, "HW hdr length invalid: %d\n", len);
2020 /* Extract software header fields */
2021 chan = SDPCM_PACKET_CHANNEL(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
2022 seq = SDPCM_PACKET_SEQUENCE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
2023 doff = SDPCM_DOFFSET_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
2024 txmax = SDPCM_WINDOW_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
2026 /* Validate data offset */
2027 if ((doff < SDPCM_HDRLEN) || (doff > len)) {
2028 brcmf_dbg(ERROR, "Bad data offset %d: HW len %d, min %d seq %d\n",
2029 doff, len, SDPCM_HDRLEN, seq);
2031 brcmf_sdbrcm_rxfail(bus, false, false);
2035 /* Save the readahead length if there is one */
2037 bus->rxhdr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
2038 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
2039 brcmf_dbg(INFO, "(nextlen): got frame w/nextlen too large (%d), seq %d\n",
2044 /* Handle Flow Control */
2045 fcbits = SDPCM_FCMASK_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
2047 if (bus->flowcontrol != fcbits) {
2048 if (~bus->flowcontrol & fcbits)
2051 if (bus->flowcontrol & ~fcbits)
2055 bus->flowcontrol = fcbits;
2058 /* Check and update sequence number */
2060 brcmf_dbg(INFO, "rx_seq %d, expected %d\n", seq, rxseq);
2065 /* Check window for sanity */
2066 if ((u8) (txmax - bus->tx_seq) > 0x40) {
2067 brcmf_dbg(ERROR, "unlikely tx max %d with tx_seq %d\n",
2068 txmax, bus->tx_seq);
2069 txmax = bus->tx_seq + 2;
2071 bus->tx_max = txmax;
2073 /* Call a separate function for control frames */
2074 if (chan == SDPCM_CONTROL_CHANNEL) {
2075 brcmf_sdbrcm_read_control(bus, bus->rxhdr, len, doff);
2079 /* precondition: chan is either SDPCM_DATA_CHANNEL,
2080 SDPCM_EVENT_CHANNEL, SDPCM_TEST_CHANNEL or
2081 SDPCM_GLOM_CHANNEL */
2083 /* Length to read */
2084 rdlen = (len > BRCMF_FIRSTREAD) ? (len - BRCMF_FIRSTREAD) : 0;
2086 /* May pad read to blocksize for efficiency */
2087 if (bus->roundup && bus->blocksize &&
2088 (rdlen > bus->blocksize)) {
2089 pad = bus->blocksize - (rdlen % bus->blocksize);
2090 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
2091 ((rdlen + pad + BRCMF_FIRSTREAD) < MAX_RX_DATASZ))
2093 } else if (rdlen % BRCMF_SDALIGN) {
2094 rdlen += BRCMF_SDALIGN - (rdlen % BRCMF_SDALIGN);
2097 /* Satisfy length-alignment requirements */
2098 if (rdlen & (ALIGNMENT - 1))
2099 rdlen = roundup(rdlen, ALIGNMENT);
2101 if ((rdlen + BRCMF_FIRSTREAD) > MAX_RX_DATASZ) {
2102 /* Too long -- skip this frame */
2103 brcmf_dbg(ERROR, "too long: len %d rdlen %d\n",
2105 bus->drvr->rx_errors++;
2107 brcmf_sdbrcm_rxfail(bus, false, false);
2111 pkt = brcmu_pkt_buf_get_skb(rdlen +
2112 BRCMF_FIRSTREAD + BRCMF_SDALIGN);
2114 /* Give up on data, request rtx of events */
2115 brcmf_dbg(ERROR, "brcmu_pkt_buf_get_skb failed: rdlen %d chan %d\n",
2117 bus->drvr->rx_dropped++;
2118 brcmf_sdbrcm_rxfail(bus, false, RETRYCHAN(chan));
2122 /* Leave room for what we already read, and align remainder */
2123 skb_pull(pkt, BRCMF_FIRSTREAD);
2124 pkt_align(pkt, rdlen, BRCMF_SDALIGN);
2126 /* Read the remaining frame data */
2127 sdret = brcmf_sdcard_recv_buf(bus->sdiodev, bus->sdiodev->sbwad,
2128 SDIO_FUNC_2, F2SYNC, ((u8 *) (pkt->data)),
2133 brcmf_dbg(ERROR, "read %d %s bytes failed: %d\n", rdlen,
2134 ((chan == SDPCM_EVENT_CHANNEL) ? "event"
2135 : ((chan == SDPCM_DATA_CHANNEL) ? "data"
2137 brcmu_pkt_buf_free_skb(pkt);
2138 bus->drvr->rx_errors++;
2139 brcmf_sdbrcm_rxfail(bus, true, RETRYCHAN(chan));
2143 /* Copy the already-read portion */
2144 skb_push(pkt, BRCMF_FIRSTREAD);
2145 memcpy(pkt->data, bus->rxhdr, BRCMF_FIRSTREAD);
2148 if (BRCMF_BYTES_ON() && BRCMF_DATA_ON()) {
2149 printk(KERN_DEBUG "Rx Data:\n");
2150 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
2156 /* Save superframe descriptor and allocate packet frame */
2157 if (chan == SDPCM_GLOM_CHANNEL) {
2158 if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_FRAMETAG_LEN])) {
2159 brcmf_dbg(GLOM, "glom descriptor, %d bytes:\n",
2162 if (BRCMF_GLOM_ON()) {
2163 printk(KERN_DEBUG "Glom Data:\n");
2164 print_hex_dump_bytes("",
2169 __skb_trim(pkt, len);
2170 skb_pull(pkt, SDPCM_HDRLEN);
2173 brcmf_dbg(ERROR, "%s: glom superframe w/o "
2174 "descriptor!\n", __func__);
2175 brcmf_sdbrcm_rxfail(bus, false, false);
2180 /* Fill in packet len and prio, deliver upward */
2181 __skb_trim(pkt, len);
2182 skb_pull(pkt, doff);
2184 if (pkt->len == 0) {
2185 brcmu_pkt_buf_free_skb(pkt);
2187 } else if (brcmf_proto_hdrpull(bus->drvr, &ifidx, pkt) != 0) {
2188 brcmf_dbg(ERROR, "rx protocol error\n");
2189 brcmu_pkt_buf_free_skb(pkt);
2190 bus->drvr->rx_errors++;
2194 /* Unlock during rx call */
2196 brcmf_rx_frame(bus->drvr, ifidx, pkt, 1);
2199 rxcount = maxframes - rxleft;
2201 /* Message if we hit the limit */
2203 brcmf_dbg(DATA, "hit rx limit of %d frames\n",
2207 brcmf_dbg(DATA, "processed %d frames\n", rxcount);
2208 /* Back off rxseq if awaiting rtx, update rx_seq */
2211 bus->rx_seq = rxseq;
2217 brcmf_sdbrcm_send_buf(struct brcmf_bus *bus, u32 addr, uint fn, uint flags,
2218 u8 *buf, uint nbytes, struct sk_buff *pkt)
2220 return brcmf_sdcard_send_buf
2221 (bus->sdiodev, addr, fn, flags, buf, nbytes, pkt);
2225 brcmf_sdbrcm_wait_for_event(struct brcmf_bus *bus, bool *lockvar)
2228 wait_event_interruptible_timeout(bus->ctrl_wait,
2229 (*lockvar == false), HZ * 2);
2235 brcmf_sdbrcm_wait_event_wakeup(struct brcmf_bus *bus)
2237 if (waitqueue_active(&bus->ctrl_wait))
2238 wake_up_interruptible(&bus->ctrl_wait);
2242 /* Writes a HW/SW header into the packet and sends it. */
2243 /* Assumes: (a) header space already there, (b) caller holds lock */
2244 static int brcmf_sdbrcm_txpkt(struct brcmf_bus *bus, struct sk_buff *pkt,
2245 uint chan, bool free_pkt)
2251 struct sk_buff *new;
2254 brcmf_dbg(TRACE, "Enter\n");
2256 frame = (u8 *) (pkt->data);
2258 /* Add alignment padding, allocate new packet if needed */
2259 pad = ((unsigned long)frame % BRCMF_SDALIGN);
2261 if (skb_headroom(pkt) < pad) {
2262 brcmf_dbg(INFO, "insufficient headroom %d for %d pad\n",
2263 skb_headroom(pkt), pad);
2264 bus->drvr->tx_realloc++;
2265 new = brcmu_pkt_buf_get_skb(pkt->len + BRCMF_SDALIGN);
2267 brcmf_dbg(ERROR, "couldn't allocate new %d-byte packet\n",
2268 pkt->len + BRCMF_SDALIGN);
2273 pkt_align(new, pkt->len, BRCMF_SDALIGN);
2274 memcpy(new->data, pkt->data, pkt->len);
2276 brcmu_pkt_buf_free_skb(pkt);
2277 /* free the pkt if canned one is not used */
2280 frame = (u8 *) (pkt->data);
2281 /* precondition: (frame % BRCMF_SDALIGN) == 0) */
2285 frame = (u8 *) (pkt->data);
2286 /* precondition: pad + SDPCM_HDRLEN <= pkt->len */
2287 memset(frame, 0, pad + SDPCM_HDRLEN);
2290 /* precondition: pad < BRCMF_SDALIGN */
2292 /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
2293 len = (u16) (pkt->len);
2294 *(__le16 *) frame = cpu_to_le16(len);
2295 *(((__le16 *) frame) + 1) = cpu_to_le16(~len);
2297 /* Software tag: channel, sequence number, data offset */
2299 ((chan << SDPCM_CHANNEL_SHIFT) & SDPCM_CHANNEL_MASK) | bus->tx_seq |
2301 SDPCM_HDRLEN) << SDPCM_DOFFSET_SHIFT) & SDPCM_DOFFSET_MASK);
2303 put_unaligned_le32(swheader, frame + SDPCM_FRAMETAG_LEN);
2304 put_unaligned_le32(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
2307 tx_packets[pkt->priority]++;
2308 if (BRCMF_BYTES_ON() &&
2309 (((BRCMF_CTL_ON() && (chan == SDPCM_CONTROL_CHANNEL)) ||
2310 (BRCMF_DATA_ON() && (chan != SDPCM_CONTROL_CHANNEL))))) {
2311 printk(KERN_DEBUG "Tx Frame:\n");
2312 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, frame, len);
2313 } else if (BRCMF_HDRS_ON()) {
2314 printk(KERN_DEBUG "TxHdr:\n");
2315 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
2316 frame, min_t(u16, len, 16));
2320 /* Raise len to next SDIO block to eliminate tail command */
2321 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
2322 u16 pad = bus->blocksize - (len % bus->blocksize);
2323 if ((pad <= bus->roundup) && (pad < bus->blocksize))
2325 } else if (len % BRCMF_SDALIGN) {
2326 len += BRCMF_SDALIGN - (len % BRCMF_SDALIGN);
2329 /* Some controllers have trouble with odd bytes -- round to even */
2330 if (len & (ALIGNMENT - 1))
2331 len = roundup(len, ALIGNMENT);
2333 ret = brcmf_sdbrcm_send_buf(bus, bus->sdiodev->sbwad,
2334 SDIO_FUNC_2, F2SYNC, frame,
2339 /* On failure, abort the command and terminate the frame */
2340 brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n",
2344 brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
2345 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
2346 SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM,
2350 for (i = 0; i < 3; i++) {
2352 hi = brcmf_sdcard_cfg_read(bus->sdiodev,
2354 SBSDIO_FUNC1_WFRAMEBCHI,
2356 lo = brcmf_sdcard_cfg_read(bus->sdiodev,
2358 SBSDIO_FUNC1_WFRAMEBCLO,
2360 bus->f1regdata += 2;
2361 if ((hi == 0) && (lo == 0))
2367 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
2370 /* restore pkt buffer pointer before calling tx complete routine */
2371 skb_pull(pkt, SDPCM_HDRLEN + pad);
2373 brcmf_txcomplete(bus->drvr, pkt, ret != 0);
2377 brcmu_pkt_buf_free_skb(pkt);
2382 static uint brcmf_sdbrcm_sendfromq(struct brcmf_bus *bus, uint maxframes)
2384 struct sk_buff *pkt;
2387 int ret = 0, prec_out;
2392 struct brcmf_pub *drvr = bus->drvr;
2394 brcmf_dbg(TRACE, "Enter\n");
2396 tx_prec_map = ~bus->flowcontrol;
2398 /* Send frames until the limit or some other event */
2399 for (cnt = 0; (cnt < maxframes) && data_ok(bus); cnt++) {
2400 spin_lock_bh(&bus->txqlock);
2401 pkt = brcmu_pktq_mdeq(&bus->txq, tx_prec_map, &prec_out);
2403 spin_unlock_bh(&bus->txqlock);
2406 spin_unlock_bh(&bus->txqlock);
2407 datalen = pkt->len - SDPCM_HDRLEN;
2409 ret = brcmf_sdbrcm_txpkt(bus, pkt, SDPCM_DATA_CHANNEL, true);
2411 bus->drvr->tx_errors++;
2413 bus->drvr->dstats.tx_bytes += datalen;
2415 /* In poll mode, need to check for other events */
2416 if (!bus->intr && cnt) {
2417 /* Check device status, signal pending interrupt */
2418 r_sdreg32(bus, &intstatus,
2419 offsetof(struct sdpcmd_regs, intstatus),
2422 if (brcmf_sdcard_regfail(bus->sdiodev))
2424 if (intstatus & bus->hostintmask)
2429 /* Deflow-control stack if needed */
2430 if (drvr->up && (drvr->busstate == BRCMF_BUS_DATA) &&
2431 drvr->txoff && (pktq_len(&bus->txq) < TXLOW))
2432 brcmf_txflowcontrol(drvr, 0, OFF);
2437 static bool brcmf_sdbrcm_dpc(struct brcmf_bus *bus)
2439 u32 intstatus, newstatus = 0;
2441 uint rxlimit = bus->rxbound; /* Rx frames to read before resched */
2442 uint txlimit = bus->txbound; /* Tx frames to send before resched */
2443 uint framecnt = 0; /* Temporary counter of tx/rx frames */
2444 bool rxdone = true; /* Flag for no more read data */
2445 bool resched = false; /* Flag indicating resched wanted */
2447 brcmf_dbg(TRACE, "Enter\n");
2449 /* Start with leftover status bits */
2450 intstatus = bus->intstatus;
2454 /* If waiting for HTAVAIL, check status */
2455 if (bus->clkstate == CLK_PENDING) {
2457 u8 clkctl, devctl = 0;
2460 /* Check for inconsistent device control */
2461 devctl = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
2462 SBSDIO_DEVICE_CTL, &err);
2464 brcmf_dbg(ERROR, "error reading DEVCTL: %d\n", err);
2465 bus->drvr->busstate = BRCMF_BUS_DOWN;
2469 /* Read CSR, if clock on switch to AVAIL, else ignore */
2470 clkctl = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
2471 SBSDIO_FUNC1_CHIPCLKCSR, &err);
2473 brcmf_dbg(ERROR, "error reading CSR: %d\n",
2475 bus->drvr->busstate = BRCMF_BUS_DOWN;
2478 brcmf_dbg(INFO, "DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n",
2481 if (SBSDIO_HTAV(clkctl)) {
2482 devctl = brcmf_sdcard_cfg_read(bus->sdiodev,
2484 SBSDIO_DEVICE_CTL, &err);
2486 brcmf_dbg(ERROR, "error reading DEVCTL: %d\n",
2488 bus->drvr->busstate = BRCMF_BUS_DOWN;
2490 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
2491 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
2492 SBSDIO_DEVICE_CTL, devctl, &err);
2494 brcmf_dbg(ERROR, "error writing DEVCTL: %d\n",
2496 bus->drvr->busstate = BRCMF_BUS_DOWN;
2498 bus->clkstate = CLK_AVAIL;
2506 /* Make sure backplane clock is on */
2507 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, true);
2508 if (bus->clkstate == CLK_PENDING)
2511 /* Pending interrupt indicates new device status */
2514 r_sdreg32(bus, &newstatus,
2515 offsetof(struct sdpcmd_regs, intstatus), &retries);
2517 if (brcmf_sdcard_regfail(bus->sdiodev))
2519 newstatus &= bus->hostintmask;
2520 bus->fcstate = !!(newstatus & I_HMB_FC_STATE);
2522 w_sdreg32(bus, newstatus,
2523 offsetof(struct sdpcmd_regs, intstatus),
2529 /* Merge new bits with previous */
2530 intstatus |= newstatus;
2533 /* Handle flow-control change: read new state in case our ack
2534 * crossed another change interrupt. If change still set, assume
2535 * FC ON for safety, let next loop through do the debounce.
2537 if (intstatus & I_HMB_FC_CHANGE) {
2538 intstatus &= ~I_HMB_FC_CHANGE;
2539 w_sdreg32(bus, I_HMB_FC_CHANGE,
2540 offsetof(struct sdpcmd_regs, intstatus), &retries);
2542 r_sdreg32(bus, &newstatus,
2543 offsetof(struct sdpcmd_regs, intstatus), &retries);
2544 bus->f1regdata += 2;
2546 !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE));
2547 intstatus |= (newstatus & bus->hostintmask);
2550 /* Handle host mailbox indication */
2551 if (intstatus & I_HMB_HOST_INT) {
2552 intstatus &= ~I_HMB_HOST_INT;
2553 intstatus |= brcmf_sdbrcm_hostmail(bus);
2556 /* Generally don't ask for these, can get CRC errors... */
2557 if (intstatus & I_WR_OOSYNC) {
2558 brcmf_dbg(ERROR, "Dongle reports WR_OOSYNC\n");
2559 intstatus &= ~I_WR_OOSYNC;
2562 if (intstatus & I_RD_OOSYNC) {
2563 brcmf_dbg(ERROR, "Dongle reports RD_OOSYNC\n");
2564 intstatus &= ~I_RD_OOSYNC;
2567 if (intstatus & I_SBINT) {
2568 brcmf_dbg(ERROR, "Dongle reports SBINT\n");
2569 intstatus &= ~I_SBINT;
2572 /* Would be active due to wake-wlan in gSPI */
2573 if (intstatus & I_CHIPACTIVE) {
2574 brcmf_dbg(INFO, "Dongle reports CHIPACTIVE\n");
2575 intstatus &= ~I_CHIPACTIVE;
2578 /* Ignore frame indications if rxskip is set */
2580 intstatus &= ~I_HMB_FRAME_IND;
2582 /* On frame indication, read available frames */
2583 if (PKT_AVAILABLE()) {
2584 framecnt = brcmf_sdbrcm_readframes(bus, rxlimit, &rxdone);
2585 if (rxdone || bus->rxskip)
2586 intstatus &= ~I_HMB_FRAME_IND;
2587 rxlimit -= min(framecnt, rxlimit);
2590 /* Keep still-pending events for next scheduling */
2591 bus->intstatus = intstatus;
2594 if (data_ok(bus) && bus->ctrl_frame_stat &&
2595 (bus->clkstate == CLK_AVAIL)) {
2598 ret = brcmf_sdbrcm_send_buf(bus, bus->sdiodev->sbwad,
2599 SDIO_FUNC_2, F2SYNC, (u8 *) bus->ctrl_frame_buf,
2600 (u32) bus->ctrl_frame_len, NULL);
2603 /* On failure, abort the command and
2604 terminate the frame */
2605 brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n",
2609 brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
2611 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
2612 SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM,
2616 for (i = 0; i < 3; i++) {
2618 hi = brcmf_sdcard_cfg_read(bus->sdiodev,
2620 SBSDIO_FUNC1_WFRAMEBCHI,
2622 lo = brcmf_sdcard_cfg_read(bus->sdiodev,
2624 SBSDIO_FUNC1_WFRAMEBCLO,
2626 bus->f1regdata += 2;
2627 if ((hi == 0) && (lo == 0))
2633 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
2635 brcmf_dbg(INFO, "Return_dpc value is : %d\n", ret);
2636 bus->ctrl_frame_stat = false;
2637 brcmf_sdbrcm_wait_event_wakeup(bus);
2639 /* Send queued frames (limit 1 if rx may still be pending) */
2640 else if ((bus->clkstate == CLK_AVAIL) && !bus->fcstate &&
2641 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit
2643 framecnt = rxdone ? txlimit : min(txlimit, bus->txminmax);
2644 framecnt = brcmf_sdbrcm_sendfromq(bus, framecnt);
2645 txlimit -= framecnt;
2648 /* Resched if events or tx frames are pending,
2649 else await next interrupt */
2650 /* On failed register access, all bets are off:
2651 no resched or interrupts */
2652 if ((bus->drvr->busstate == BRCMF_BUS_DOWN) ||
2653 brcmf_sdcard_regfail(bus->sdiodev)) {
2654 brcmf_dbg(ERROR, "failed backplane access over SDIO, halting operation %d\n",
2655 brcmf_sdcard_regfail(bus->sdiodev));
2656 bus->drvr->busstate = BRCMF_BUS_DOWN;
2658 } else if (bus->clkstate == CLK_PENDING) {
2659 brcmf_dbg(INFO, "rescheduled due to CLK_PENDING awaiting I_CHIPACTIVE interrupt\n");
2661 } else if (bus->intstatus || bus->ipend ||
2662 (!bus->fcstate && brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol)
2663 && data_ok(bus)) || PKT_AVAILABLE()) {
2667 bus->dpc_sched = resched;
2669 /* If we're done for now, turn off clock request. */
2670 if ((bus->clkstate != CLK_PENDING)
2671 && bus->idletime == BRCMF_IDLE_IMMEDIATE) {
2672 bus->activity = false;
2673 brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
2681 static int brcmf_sdbrcm_dpc_thread(void *data)
2683 struct brcmf_bus *bus = (struct brcmf_bus *) data;
2685 allow_signal(SIGTERM);
2686 /* Run until signal received */
2688 if (kthread_should_stop())
2690 if (!wait_for_completion_interruptible(&bus->dpc_wait)) {
2691 /* Call bus dpc unless it indicated down
2692 (then clean stop) */
2693 if (bus->drvr->busstate != BRCMF_BUS_DOWN) {
2694 if (brcmf_sdbrcm_dpc(bus))
2695 complete(&bus->dpc_wait);
2697 /* after stopping the bus, exit thread */
2698 brcmf_sdbrcm_bus_stop(bus);
2699 bus->dpc_tsk = NULL;
2708 int brcmf_sdbrcm_bus_txdata(struct brcmf_bus *bus, struct sk_buff *pkt)
2713 brcmf_dbg(TRACE, "Enter\n");
2717 /* Add space for the header */
2718 skb_push(pkt, SDPCM_HDRLEN);
2719 /* precondition: IS_ALIGNED((unsigned long)(pkt->data), 2) */
2721 prec = prio2prec((pkt->priority & PRIOMASK));
2723 /* Check for existing queue, current flow-control,
2724 pending event, or pending clock */
2725 brcmf_dbg(TRACE, "deferring pktq len %d\n", pktq_len(&bus->txq));
2728 /* Priority based enq */
2729 spin_lock_bh(&bus->txqlock);
2730 if (brcmf_c_prec_enq(bus->drvr, &bus->txq, pkt, prec) == false) {
2731 skb_pull(pkt, SDPCM_HDRLEN);
2732 brcmf_txcomplete(bus->drvr, pkt, false);
2733 brcmu_pkt_buf_free_skb(pkt);
2734 brcmf_dbg(ERROR, "out of bus->txq !!!\n");
2739 spin_unlock_bh(&bus->txqlock);
2741 if (pktq_len(&bus->txq) >= TXHI)
2742 brcmf_txflowcontrol(bus->drvr, 0, ON);
2745 if (pktq_plen(&bus->txq, prec) > qcount[prec])
2746 qcount[prec] = pktq_plen(&bus->txq, prec);
2748 /* Schedule DPC if needed to send queued packet(s) */
2749 if (!bus->dpc_sched) {
2750 bus->dpc_sched = true;
2752 complete(&bus->dpc_wait);
2759 brcmf_sdbrcm_membytes(struct brcmf_bus *bus, bool write, u32 address, u8 *data,
2766 /* Determine initial transfer parameters */
2767 sdaddr = address & SBSDIO_SB_OFT_ADDR_MASK;
2768 if ((sdaddr + size) & SBSDIO_SBWINDOW_MASK)
2769 dsize = (SBSDIO_SB_OFT_ADDR_LIMIT - sdaddr);
2773 /* Set the backplane window to include the start address */
2774 bcmerror = brcmf_sdcard_set_sbaddr_window(bus->sdiodev, address);
2776 brcmf_dbg(ERROR, "window change failed\n");
2780 /* Do the transfer(s) */
2782 brcmf_dbg(INFO, "%s %d bytes at offset 0x%08x in window 0x%08x\n",
2783 write ? "write" : "read", dsize,
2784 sdaddr, address & SBSDIO_SBWINDOW_MASK);
2785 bcmerror = brcmf_sdcard_rwdata(bus->sdiodev, write,
2786 sdaddr, data, dsize);
2788 brcmf_dbg(ERROR, "membytes transfer failed\n");
2792 /* Adjust for next transfer (if any) */
2797 bcmerror = brcmf_sdcard_set_sbaddr_window(bus->sdiodev,
2800 brcmf_dbg(ERROR, "window change failed\n");
2804 dsize = min_t(uint, SBSDIO_SB_OFT_ADDR_LIMIT, size);
2809 /* Return the window to backplane enumeration space for core access */
2810 if (brcmf_sdcard_set_sbaddr_window(bus->sdiodev, bus->sdiodev->sbwad))
2811 brcmf_dbg(ERROR, "FAILED to set window back to 0x%x\n",
2812 bus->sdiodev->sbwad);
2818 #define CONSOLE_LINE_MAX 192
2820 static int brcmf_sdbrcm_readconsole(struct brcmf_bus *bus)
2822 struct brcmf_console *c = &bus->console;
2823 u8 line[CONSOLE_LINE_MAX], ch;
2827 /* Don't do anything until FWREADY updates console address */
2828 if (bus->console_addr == 0)
2831 /* Read console log struct */
2832 addr = bus->console_addr + offsetof(struct rte_console, log_le);
2833 rv = brcmf_sdbrcm_membytes(bus, false, addr, (u8 *)&c->log_le,
2838 /* Allocate console buffer (one time only) */
2839 if (c->buf == NULL) {
2840 c->bufsize = le32_to_cpu(c->log_le.buf_size);
2841 c->buf = kmalloc(c->bufsize, GFP_ATOMIC);
2846 idx = le32_to_cpu(c->log_le.idx);
2848 /* Protect against corrupt value */
2849 if (idx > c->bufsize)
2852 /* Skip reading the console buffer if the index pointer
2857 /* Read the console buffer */
2858 addr = le32_to_cpu(c->log_le.buf);
2859 rv = brcmf_sdbrcm_membytes(bus, false, addr, c->buf, c->bufsize);
2863 while (c->last != idx) {
2864 for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
2865 if (c->last == idx) {
2866 /* This would output a partial line.
2868 * the buffer pointer and output this
2869 * line next time around.
2874 c->last = c->bufsize - n;
2877 ch = c->buf[c->last];
2878 c->last = (c->last + 1) % c->bufsize;
2885 if (line[n - 1] == '\r')
2888 printk(KERN_DEBUG "CONSOLE: %s\n", line);
2897 static int brcmf_tx_frame(struct brcmf_bus *bus, u8 *frame, u16 len)
2902 bus->ctrl_frame_stat = false;
2903 ret = brcmf_sdbrcm_send_buf(bus, bus->sdiodev->sbwad,
2904 SDIO_FUNC_2, F2SYNC, frame, len, NULL);
2907 /* On failure, abort the command and terminate the frame */
2908 brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n",
2912 brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
2914 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
2915 SBSDIO_FUNC1_FRAMECTRL,
2919 for (i = 0; i < 3; i++) {
2921 hi = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
2922 SBSDIO_FUNC1_WFRAMEBCHI,
2924 lo = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
2925 SBSDIO_FUNC1_WFRAMEBCLO,
2927 bus->f1regdata += 2;
2928 if (hi == 0 && lo == 0)
2934 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
2940 brcmf_sdbrcm_bus_txctl(struct brcmf_bus *bus, unsigned char *msg, uint msglen)
2949 brcmf_dbg(TRACE, "Enter\n");
2951 /* Back the pointer to make a room for bus header */
2952 frame = msg - SDPCM_HDRLEN;
2953 len = (msglen += SDPCM_HDRLEN);
2955 /* Add alignment padding (optional for ctl frames) */
2956 doff = ((unsigned long)frame % BRCMF_SDALIGN);
2961 memset(frame, 0, doff + SDPCM_HDRLEN);
2963 /* precondition: doff < BRCMF_SDALIGN */
2964 doff += SDPCM_HDRLEN;
2966 /* Round send length to next SDIO block */
2967 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
2968 u16 pad = bus->blocksize - (len % bus->blocksize);
2969 if ((pad <= bus->roundup) && (pad < bus->blocksize))
2971 } else if (len % BRCMF_SDALIGN) {
2972 len += BRCMF_SDALIGN - (len % BRCMF_SDALIGN);
2975 /* Satisfy length-alignment requirements */
2976 if (len & (ALIGNMENT - 1))
2977 len = roundup(len, ALIGNMENT);
2979 /* precondition: IS_ALIGNED((unsigned long)frame, 2) */
2981 /* Need to lock here to protect txseq and SDIO tx calls */
2986 /* Make sure backplane clock is on */
2987 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
2989 /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
2990 *(__le16 *) frame = cpu_to_le16((u16) msglen);
2991 *(((__le16 *) frame) + 1) = cpu_to_le16(~msglen);
2993 /* Software tag: channel, sequence number, data offset */
2995 ((SDPCM_CONTROL_CHANNEL << SDPCM_CHANNEL_SHIFT) &
2997 | bus->tx_seq | ((doff << SDPCM_DOFFSET_SHIFT) &
2998 SDPCM_DOFFSET_MASK);
2999 put_unaligned_le32(swheader, frame + SDPCM_FRAMETAG_LEN);
3000 put_unaligned_le32(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
3002 if (!data_ok(bus)) {
3003 brcmf_dbg(INFO, "No bus credit bus->tx_max %d, bus->tx_seq %d\n",
3004 bus->tx_max, bus->tx_seq);
3005 bus->ctrl_frame_stat = true;
3007 bus->ctrl_frame_buf = frame;
3008 bus->ctrl_frame_len = len;
3010 brcmf_sdbrcm_wait_for_event(bus, &bus->ctrl_frame_stat);
3012 if (bus->ctrl_frame_stat == false) {
3013 brcmf_dbg(INFO, "ctrl_frame_stat == false\n");
3016 brcmf_dbg(INFO, "ctrl_frame_stat == true\n");
3023 if (BRCMF_BYTES_ON() && BRCMF_CTL_ON()) {
3024 printk(KERN_DEBUG "Tx Frame:\n");
3025 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3027 } else if (BRCMF_HDRS_ON()) {
3028 printk(KERN_DEBUG "TxHdr:\n");
3029 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3030 frame, min_t(u16, len, 16));
3035 ret = brcmf_tx_frame(bus, frame, len);
3036 } while (ret < 0 && retries++ < TXRETRIES);
3039 if ((bus->idletime == BRCMF_IDLE_IMMEDIATE) && !bus->dpc_sched) {
3040 bus->activity = false;
3041 brcmf_sdbrcm_clkctl(bus, CLK_NONE, true);
3047 bus->drvr->tx_ctlerrs++;
3049 bus->drvr->tx_ctlpkts++;
3051 return ret ? -EIO : 0;
3055 brcmf_sdbrcm_bus_rxctl(struct brcmf_bus *bus, unsigned char *msg, uint msglen)
3061 brcmf_dbg(TRACE, "Enter\n");
3063 /* Wait until control frame is available */
3064 timeleft = brcmf_sdbrcm_dcmd_resp_wait(bus, &bus->rxlen, &pending);
3068 memcpy(msg, bus->rxctl, min(msglen, rxlen));
3073 brcmf_dbg(CTL, "resumed on rxctl frame, got %d expected %d\n",
3075 } else if (timeleft == 0) {
3076 brcmf_dbg(ERROR, "resumed on timeout\n");
3077 } else if (pending == true) {
3078 brcmf_dbg(CTL, "cancelled\n");
3079 return -ERESTARTSYS;
3081 brcmf_dbg(CTL, "resumed for unknown reason?\n");
3085 bus->drvr->rx_ctlpkts++;
3087 bus->drvr->rx_ctlerrs++;
3089 return rxlen ? (int)rxlen : -ETIMEDOUT;
3092 static int brcmf_sdbrcm_downloadvars(struct brcmf_bus *bus, void *arg, int len)
3096 brcmf_dbg(TRACE, "Enter\n");
3098 /* Basic sanity checks */
3099 if (bus->drvr->up) {
3100 bcmerror = -EISCONN;
3104 bcmerror = -EOVERFLOW;
3108 /* Free the old ones and replace with passed variables */
3111 bus->vars = kmalloc(len, GFP_ATOMIC);
3112 bus->varsz = bus->vars ? len : 0;
3113 if (bus->vars == NULL) {
3118 /* Copy the passed variables, which should include the
3119 terminating double-null */
3120 memcpy(bus->vars, arg, bus->varsz);
3125 static int brcmf_sdbrcm_write_vars(struct brcmf_bus *bus)
3134 char *nvram_ularray;
3137 /* Even if there are no vars are to be written, we still
3138 need to set the ramsize. */
3139 varsize = bus->varsz ? roundup(bus->varsz, 4) : 0;
3140 varaddr = (bus->ramsize - 4) - varsize;
3143 vbuffer = kzalloc(varsize, GFP_ATOMIC);
3147 memcpy(vbuffer, bus->vars, bus->varsz);
3149 /* Write the vars list */
3151 brcmf_sdbrcm_membytes(bus, true, varaddr, vbuffer, varsize);
3153 /* Verify NVRAM bytes */
3154 brcmf_dbg(INFO, "Compare NVRAM dl & ul; varsize=%d\n", varsize);
3155 nvram_ularray = kmalloc(varsize, GFP_ATOMIC);
3159 /* Upload image to verify downloaded contents. */
3160 memset(nvram_ularray, 0xaa, varsize);
3162 /* Read the vars list to temp buffer for comparison */
3164 brcmf_sdbrcm_membytes(bus, false, varaddr, nvram_ularray,
3167 brcmf_dbg(ERROR, "error %d on reading %d nvram bytes at 0x%08x\n",
3168 bcmerror, varsize, varaddr);
3170 /* Compare the org NVRAM with the one read from RAM */
3171 if (memcmp(vbuffer, nvram_ularray, varsize))
3172 brcmf_dbg(ERROR, "Downloaded NVRAM image is corrupted\n");
3174 brcmf_dbg(ERROR, "Download/Upload/Compare of NVRAM ok\n");
3176 kfree(nvram_ularray);
3182 /* adjust to the user specified RAM */
3183 brcmf_dbg(INFO, "Physical memory size: %d\n", bus->ramsize);
3184 brcmf_dbg(INFO, "Vars are at %d, orig varsize is %d\n",
3186 varsize = ((bus->ramsize - 4) - varaddr);
3189 * Determine the length token:
3190 * Varsize, converted to words, in lower 16-bits, checksum
3195 varsizew_le = cpu_to_le32(0);
3197 varsizew = varsize / 4;
3198 varsizew = (~varsizew << 16) | (varsizew & 0x0000FFFF);
3199 varsizew_le = cpu_to_le32(varsizew);
3202 brcmf_dbg(INFO, "New varsize is %d, length token=0x%08x\n",
3205 /* Write the length token to the last word */
3206 bcmerror = brcmf_sdbrcm_membytes(bus, true, (bus->ramsize - 4),
3207 (u8 *)&varsizew_le, 4);
3213 brcmf_sdbrcm_chip_disablecore(struct brcmf_sdio_dev *sdiodev, u32 corebase)
3217 regdata = brcmf_sdcard_reg_read(sdiodev,
3218 CORE_SB(corebase, sbtmstatelow), 4);
3219 if (regdata & SBTML_RESET)
3222 regdata = brcmf_sdcard_reg_read(sdiodev,
3223 CORE_SB(corebase, sbtmstatelow), 4);
3224 if ((regdata & (SICF_CLOCK_EN << SBTML_SICF_SHIFT)) != 0) {
3226 * set target reject and spin until busy is clear
3227 * (preserve core-specific bits)
3229 regdata = brcmf_sdcard_reg_read(sdiodev,
3230 CORE_SB(corebase, sbtmstatelow), 4);
3231 brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow),
3232 4, regdata | SBTML_REJ);
3234 regdata = brcmf_sdcard_reg_read(sdiodev,
3235 CORE_SB(corebase, sbtmstatelow), 4);
3237 SPINWAIT((brcmf_sdcard_reg_read(sdiodev,
3238 CORE_SB(corebase, sbtmstatehigh), 4) &
3239 SBTMH_BUSY), 100000);
3241 regdata = brcmf_sdcard_reg_read(sdiodev,
3242 CORE_SB(corebase, sbtmstatehigh), 4);
3243 if (regdata & SBTMH_BUSY)
3244 brcmf_dbg(ERROR, "ARM core still busy\n");
3246 regdata = brcmf_sdcard_reg_read(sdiodev,
3247 CORE_SB(corebase, sbidlow), 4);
3248 if (regdata & SBIDL_INIT) {
3249 regdata = brcmf_sdcard_reg_read(sdiodev,
3250 CORE_SB(corebase, sbimstate), 4) |
3252 brcmf_sdcard_reg_write(sdiodev,
3253 CORE_SB(corebase, sbimstate), 4,
3255 regdata = brcmf_sdcard_reg_read(sdiodev,
3256 CORE_SB(corebase, sbimstate), 4);
3258 SPINWAIT((brcmf_sdcard_reg_read(sdiodev,
3259 CORE_SB(corebase, sbimstate), 4) &
3263 /* set reset and reject while enabling the clocks */
3264 brcmf_sdcard_reg_write(sdiodev,
3265 CORE_SB(corebase, sbtmstatelow), 4,
3266 (((SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT) |
3267 SBTML_REJ | SBTML_RESET));
3268 regdata = brcmf_sdcard_reg_read(sdiodev,
3269 CORE_SB(corebase, sbtmstatelow), 4);
3272 /* clear the initiator reject bit */
3273 regdata = brcmf_sdcard_reg_read(sdiodev,
3274 CORE_SB(corebase, sbidlow), 4);
3275 if (regdata & SBIDL_INIT) {
3276 regdata = brcmf_sdcard_reg_read(sdiodev,
3277 CORE_SB(corebase, sbimstate), 4) &
3279 brcmf_sdcard_reg_write(sdiodev,
3280 CORE_SB(corebase, sbimstate), 4,
3285 /* leave reset and reject asserted */
3286 brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), 4,
3287 (SBTML_REJ | SBTML_RESET));
3292 brcmf_sdbrcm_chip_resetcore(struct brcmf_sdio_dev *sdiodev, u32 corebase)
3297 * Must do the disable sequence first to work for
3298 * arbitrary current core state.
3300 brcmf_sdbrcm_chip_disablecore(sdiodev, corebase);
3303 * Now do the initialization sequence.
3304 * set reset while enabling the clock and
3305 * forcing them on throughout the core
3307 brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), 4,
3308 ((SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT) |
3312 regdata = brcmf_sdcard_reg_read(sdiodev,
3313 CORE_SB(corebase, sbtmstatehigh), 4);
3314 if (regdata & SBTMH_SERR)
3315 brcmf_sdcard_reg_write(sdiodev,
3316 CORE_SB(corebase, sbtmstatehigh), 4, 0);
3318 regdata = brcmf_sdcard_reg_read(sdiodev,
3319 CORE_SB(corebase, sbimstate), 4);
3320 if (regdata & (SBIM_IBE | SBIM_TO))
3321 brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbimstate), 4,
3322 regdata & ~(SBIM_IBE | SBIM_TO));
3324 /* clear reset and allow it to propagate throughout the core */
3325 brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), 4,
3326 (SICF_FGC << SBTML_SICF_SHIFT) |
3327 (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
3330 /* leave clock enabled */
3331 brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), 4,
3332 (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
3336 static int brcmf_sdbrcm_download_state(struct brcmf_bus *bus, bool enter)
3342 /* To enter download state, disable ARM and reset SOCRAM.
3343 * To exit download state, simply reset ARM (default is RAM boot).
3346 bus->alp_only = true;
3348 brcmf_sdbrcm_chip_disablecore(bus->sdiodev,
3349 bus->ci->armcorebase);
3351 brcmf_sdbrcm_chip_resetcore(bus->sdiodev, bus->ci->ramcorebase);
3353 /* Clear the top bit of memory */
3356 brcmf_sdbrcm_membytes(bus, true, bus->ramsize - 4,
3360 regdata = brcmf_sdcard_reg_read(bus->sdiodev,
3361 CORE_SB(bus->ci->ramcorebase, sbtmstatelow), 4);
3362 regdata &= (SBTML_RESET | SBTML_REJ_MASK |
3363 (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
3364 if ((SICF_CLOCK_EN << SBTML_SICF_SHIFT) != regdata) {
3365 brcmf_dbg(ERROR, "SOCRAM core is down after reset?\n");
3370 bcmerror = brcmf_sdbrcm_write_vars(bus);
3372 brcmf_dbg(ERROR, "no vars written to RAM\n");
3376 w_sdreg32(bus, 0xFFFFFFFF,
3377 offsetof(struct sdpcmd_regs, intstatus), &retries);
3379 brcmf_sdbrcm_chip_resetcore(bus->sdiodev, bus->ci->armcorebase);
3381 /* Allow HT Clock now that the ARM is running. */
3382 bus->alp_only = false;
3384 bus->drvr->busstate = BRCMF_BUS_LOAD;
3390 static int brcmf_sdbrcm_get_image(char *buf, int len, struct brcmf_bus *bus)
3392 if (bus->firmware->size < bus->fw_ptr + len)
3393 len = bus->firmware->size - bus->fw_ptr;
3395 memcpy(buf, &bus->firmware->data[bus->fw_ptr], len);
3400 MODULE_FIRMWARE(BCM4329_FW_NAME);
3401 MODULE_FIRMWARE(BCM4329_NV_NAME);
3403 static int brcmf_sdbrcm_download_code_file(struct brcmf_bus *bus)
3407 u8 *memblock = NULL, *memptr;
3410 brcmf_dbg(INFO, "Enter\n");
3412 bus->fw_name = BCM4329_FW_NAME;
3413 ret = request_firmware(&bus->firmware, bus->fw_name,
3414 &bus->sdiodev->func[2]->dev);
3416 brcmf_dbg(ERROR, "Fail to request firmware %d\n", ret);
3421 memptr = memblock = kmalloc(MEMBLOCK + BRCMF_SDALIGN, GFP_ATOMIC);
3422 if (memblock == NULL) {
3426 if ((u32)(unsigned long)memblock % BRCMF_SDALIGN)
3427 memptr += (BRCMF_SDALIGN -
3428 ((u32)(unsigned long)memblock % BRCMF_SDALIGN));
3430 /* Download image */
3432 brcmf_sdbrcm_get_image((char *)memptr, MEMBLOCK, bus))) {
3433 ret = brcmf_sdbrcm_membytes(bus, true, offset, memptr, len);
3435 brcmf_dbg(ERROR, "error %d on writing %d membytes at 0x%08x\n",
3436 ret, MEMBLOCK, offset);
3446 release_firmware(bus->firmware);
3453 * ProcessVars:Takes a buffer of "<var>=<value>\n" lines read from a file
3454 * and ending in a NUL.
3455 * Removes carriage returns, empty lines, comment lines, and converts
3457 * Shortens buffer as needed and pads with NULs. End of buffer is marked
3461 static uint brcmf_process_nvram_vars(char *varbuf, uint len)
3470 findNewline = false;
3473 for (n = 0; n < len; n++) {
3476 if (varbuf[n] == '\r')
3478 if (findNewline && varbuf[n] != '\n')
3480 findNewline = false;
3481 if (varbuf[n] == '#') {
3485 if (varbuf[n] == '\n') {
3495 buf_len = dp - varbuf;
3497 while (dp < varbuf + n)
3503 static int brcmf_sdbrcm_download_nvram(struct brcmf_bus *bus)
3506 char *memblock = NULL;
3510 bus->nv_name = BCM4329_NV_NAME;
3511 ret = request_firmware(&bus->firmware, bus->nv_name,
3512 &bus->sdiodev->func[2]->dev);
3514 brcmf_dbg(ERROR, "Fail to request nvram %d\n", ret);
3519 memblock = kmalloc(MEMBLOCK, GFP_ATOMIC);
3520 if (memblock == NULL) {
3525 len = brcmf_sdbrcm_get_image(memblock, MEMBLOCK, bus);
3527 if (len > 0 && len < MEMBLOCK) {
3528 bufp = (char *)memblock;
3530 len = brcmf_process_nvram_vars(bufp, len);
3534 ret = brcmf_sdbrcm_downloadvars(bus, memblock, len + 1);
3536 brcmf_dbg(ERROR, "error downloading vars: %d\n", ret);
3538 brcmf_dbg(ERROR, "error reading nvram file: %d\n", len);
3545 release_firmware(bus->firmware);
3551 static int _brcmf_sdbrcm_download_firmware(struct brcmf_bus *bus)
3555 /* Keep arm in reset */
3556 if (brcmf_sdbrcm_download_state(bus, true)) {
3557 brcmf_dbg(ERROR, "error placing ARM core in reset\n");
3561 /* External image takes precedence if specified */
3562 if (brcmf_sdbrcm_download_code_file(bus)) {
3563 brcmf_dbg(ERROR, "dongle image file download failed\n");
3567 /* External nvram takes precedence if specified */
3568 if (brcmf_sdbrcm_download_nvram(bus))
3569 brcmf_dbg(ERROR, "dongle nvram file download failed\n");
3571 /* Take arm out of reset */
3572 if (brcmf_sdbrcm_download_state(bus, false)) {
3573 brcmf_dbg(ERROR, "error getting out of ARM core reset\n");
3584 brcmf_sdbrcm_download_firmware(struct brcmf_bus *bus)
3588 /* Download the firmware */
3589 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
3591 ret = _brcmf_sdbrcm_download_firmware(bus) == 0;
3593 brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
3598 void brcmf_sdbrcm_bus_stop(struct brcmf_bus *bus)
3600 u32 local_hostintmask;
3605 brcmf_dbg(TRACE, "Enter\n");
3607 if (bus->watchdog_tsk) {
3608 send_sig(SIGTERM, bus->watchdog_tsk, 1);
3609 kthread_stop(bus->watchdog_tsk);
3610 bus->watchdog_tsk = NULL;
3613 if (bus->dpc_tsk && bus->dpc_tsk != current) {
3614 send_sig(SIGTERM, bus->dpc_tsk, 1);
3615 kthread_stop(bus->dpc_tsk);
3616 bus->dpc_tsk = NULL;
3623 /* Enable clock for device interrupts */
3624 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
3626 /* Disable and clear interrupts at the chip level also */
3627 w_sdreg32(bus, 0, offsetof(struct sdpcmd_regs, hostintmask), &retries);
3628 local_hostintmask = bus->hostintmask;
3629 bus->hostintmask = 0;
3631 /* Change our idea of bus state */
3632 bus->drvr->busstate = BRCMF_BUS_DOWN;
3634 /* Force clocks on backplane to be sure F2 interrupt propagates */
3635 saveclk = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
3636 SBSDIO_FUNC1_CHIPCLKCSR, &err);
3638 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
3639 SBSDIO_FUNC1_CHIPCLKCSR,
3640 (saveclk | SBSDIO_FORCE_HT), &err);
3643 brcmf_dbg(ERROR, "Failed to force clock for F2: err %d\n", err);
3645 /* Turn off the bus (F2), free any pending packets */
3646 brcmf_dbg(INTR, "disable SDIO interrupts\n");
3647 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0, SDIO_CCCR_IOEx,
3648 SDIO_FUNC_ENABLE_1, NULL);
3650 /* Clear any pending interrupts now that F2 is disabled */
3651 w_sdreg32(bus, local_hostintmask,
3652 offsetof(struct sdpcmd_regs, intstatus), &retries);
3654 /* Turn off the backplane clock (only) */
3655 brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
3657 /* Clear the data packet queues */
3658 brcmu_pktq_flush(&bus->txq, true, NULL, NULL);
3660 /* Clear any held glomming stuff */
3662 brcmu_pkt_buf_free_skb(bus->glomd);
3665 brcmu_pkt_buf_free_skb(bus->glom);
3667 bus->glom = bus->glomd = NULL;
3669 /* Clear rx control and wake any waiters */
3671 brcmf_sdbrcm_dcmd_resp_wake(bus);
3673 /* Reset some F2 state stuff */
3674 bus->rxskip = false;
3675 bus->tx_seq = bus->rx_seq = 0;
3680 int brcmf_sdbrcm_bus_init(struct brcmf_pub *drvr)
3682 struct brcmf_bus *bus = drvr->bus;
3683 unsigned long timeout;
3689 brcmf_dbg(TRACE, "Enter\n");
3691 /* try to download image and nvram to the dongle */
3692 if (drvr->busstate == BRCMF_BUS_DOWN) {
3693 if (!(brcmf_sdbrcm_download_firmware(bus)))
3700 /* Start the watchdog timer */
3701 bus->drvr->tickcnt = 0;
3702 brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
3706 /* Make sure backplane clock is on, needed to generate F2 interrupt */
3707 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
3708 if (bus->clkstate != CLK_AVAIL)
3711 /* Force clocks on backplane to be sure F2 interrupt propagates */
3713 brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
3714 SBSDIO_FUNC1_CHIPCLKCSR, &err);
3716 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
3717 SBSDIO_FUNC1_CHIPCLKCSR,
3718 (saveclk | SBSDIO_FORCE_HT), &err);
3721 brcmf_dbg(ERROR, "Failed to force clock for F2: err %d\n", err);
3725 /* Enable function 2 (frame transfers) */
3726 w_sdreg32(bus, SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT,
3727 offsetof(struct sdpcmd_regs, tosbmailboxdata), &retries);
3728 enable = (SDIO_FUNC_ENABLE_1 | SDIO_FUNC_ENABLE_2);
3730 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0, SDIO_CCCR_IOEx,
3733 timeout = jiffies + msecs_to_jiffies(BRCMF_WAIT_F2RDY);
3735 while (enable != ready) {
3736 ready = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_0,
3737 SDIO_CCCR_IORx, NULL);
3738 if (time_after(jiffies, timeout))
3740 else if (time_after(jiffies, timeout - BRCMF_WAIT_F2RDY + 50))
3741 /* prevent busy waiting if it takes too long */
3742 msleep_interruptible(20);
3745 brcmf_dbg(INFO, "enable 0x%02x, ready 0x%02x\n", enable, ready);
3747 /* If F2 successfully enabled, set core and enable interrupts */
3748 if (ready == enable) {
3749 /* Set up the interrupt mask and enable interrupts */
3750 bus->hostintmask = HOSTINTMASK;
3751 w_sdreg32(bus, bus->hostintmask,
3752 offsetof(struct sdpcmd_regs, hostintmask), &retries);
3754 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
3755 SBSDIO_WATERMARK, 8, &err);
3757 /* Set bus state according to enable result */
3758 drvr->busstate = BRCMF_BUS_DATA;
3762 /* Disable F2 again */
3763 enable = SDIO_FUNC_ENABLE_1;
3764 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0,
3765 SDIO_CCCR_IOEx, enable, NULL);
3768 /* Restore previous clock setting */
3769 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
3770 SBSDIO_FUNC1_CHIPCLKCSR, saveclk, &err);
3772 /* If we didn't come up, turn off backplane clock */
3773 if (drvr->busstate != BRCMF_BUS_DATA)
3774 brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
3782 void brcmf_sdbrcm_isr(void *arg)
3784 struct brcmf_bus *bus = (struct brcmf_bus *) arg;
3786 brcmf_dbg(TRACE, "Enter\n");
3789 brcmf_dbg(ERROR, "bus is null pointer, exiting\n");
3793 if (bus->drvr->busstate == BRCMF_BUS_DOWN) {
3794 brcmf_dbg(ERROR, "bus is down. we have nothing to do\n");
3797 /* Count the interrupt call */
3801 /* Shouldn't get this interrupt if we're sleeping? */
3802 if (bus->sleeping) {
3803 brcmf_dbg(ERROR, "INTERRUPT WHILE SLEEPING??\n");
3807 /* Disable additional interrupts (is this needed now)? */
3809 brcmf_dbg(ERROR, "isr w/o interrupt configured!\n");
3811 bus->dpc_sched = true;
3813 complete(&bus->dpc_wait);
3816 static bool brcmf_sdbrcm_bus_watchdog(struct brcmf_pub *drvr)
3818 struct brcmf_bus *bus;
3820 brcmf_dbg(TIMER, "Enter\n");
3824 /* Ignore the timer if simulating bus down */
3830 /* Poll period: check device if appropriate. */
3831 if (bus->poll && (++bus->polltick >= bus->pollrate)) {
3834 /* Reset poll tick */
3837 /* Check device if no interrupts */
3838 if (!bus->intr || (bus->intrcount == bus->lastintrs)) {
3840 if (!bus->dpc_sched) {
3842 devpend = brcmf_sdcard_cfg_read(bus->sdiodev,
3843 SDIO_FUNC_0, SDIO_CCCR_INTx,
3846 devpend & (INTR_STATUS_FUNC1 |
3850 /* If there is something, make like the ISR and
3856 bus->dpc_sched = true;
3858 complete(&bus->dpc_wait);
3862 /* Update interrupt tracking */
3863 bus->lastintrs = bus->intrcount;
3866 /* Poll for console output periodically */
3867 if (drvr->busstate == BRCMF_BUS_DATA && bus->console_interval != 0) {
3868 bus->console.count += BRCMF_WD_POLL_MS;
3869 if (bus->console.count >= bus->console_interval) {
3870 bus->console.count -= bus->console_interval;
3871 /* Make sure backplane clock is on */
3872 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
3873 if (brcmf_sdbrcm_readconsole(bus) < 0)
3875 bus->console_interval = 0;
3880 /* On idle timeout clear activity flag and/or turn off clock */
3881 if ((bus->idletime > 0) && (bus->clkstate == CLK_AVAIL)) {
3882 if (++bus->idlecount >= bus->idletime) {
3884 if (bus->activity) {
3885 bus->activity = false;
3886 brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
3888 brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
3898 static bool brcmf_sdbrcm_chipmatch(u16 chipid)
3900 if (chipid == BCM4329_CHIP_ID)
3905 static void brcmf_sdbrcm_release_malloc(struct brcmf_bus *bus)
3907 brcmf_dbg(TRACE, "Enter\n");
3910 bus->rxctl = bus->rxbuf = NULL;
3913 kfree(bus->databuf);
3914 bus->databuf = NULL;
3917 static bool brcmf_sdbrcm_probe_malloc(struct brcmf_bus *bus)
3919 brcmf_dbg(TRACE, "Enter\n");
3921 if (bus->drvr->maxctl) {
3923 roundup((bus->drvr->maxctl + SDPCM_HDRLEN),
3924 ALIGNMENT) + BRCMF_SDALIGN;
3925 bus->rxbuf = kmalloc(bus->rxblen, GFP_ATOMIC);
3930 /* Allocate buffer to receive glomed packet */
3931 bus->databuf = kmalloc(MAX_DATA_BUF, GFP_ATOMIC);
3932 if (!(bus->databuf)) {
3933 /* release rxbuf which was already located as above */
3939 /* Align the buffer */
3940 if ((unsigned long)bus->databuf % BRCMF_SDALIGN)
3941 bus->dataptr = bus->databuf + (BRCMF_SDALIGN -
3942 ((unsigned long)bus->databuf % BRCMF_SDALIGN));
3944 bus->dataptr = bus->databuf;
3952 /* SDIO Pad drive strength to select value mappings */
3953 struct sdiod_drive_str {
3954 u8 strength; /* Pad Drive Strength in mA */
3955 u8 sel; /* Chip-specific select value */
3958 /* SDIO Drive Strength to sel value table for PMU Rev 1 */
3959 static const struct sdiod_drive_str sdiod_drive_strength_tab1[] = {
3967 /* SDIO Drive Strength to sel value table for PMU Rev 2, 3 */
3968 static const struct sdiod_drive_str sdiod_drive_strength_tab2[] = {
3979 /* SDIO Drive Strength to sel value table for PMU Rev 8 (1.8V) */
3980 static const struct sdiod_drive_str sdiod_drive_strength_tab3[] = {
3992 #define SDIOD_DRVSTR_KEY(chip, pmu) (((chip) << 16) | (pmu))
3994 static void brcmf_sdbrcm_sdiod_drive_strength_init(struct brcmf_bus *bus,
3995 u32 drivestrength) {
3996 struct sdiod_drive_str *str_tab = NULL;
4001 if (!(bus->ci->cccaps & CC_CAP_PMU))
4004 switch (SDIOD_DRVSTR_KEY(bus->ci->chip, bus->ci->pmurev)) {
4005 case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 1):
4006 str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab1;
4007 str_mask = 0x30000000;
4010 case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 2):
4011 case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 3):
4012 str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab2;
4013 str_mask = 0x00003800;
4016 case SDIOD_DRVSTR_KEY(BCM4336_CHIP_ID, 8):
4017 str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab3;
4018 str_mask = 0x00003800;
4022 brcmf_dbg(ERROR, "No SDIO Drive strength init done for chip %s rev %d pmurev %d\n",
4023 brcmu_chipname(bus->ci->chip, chn, 8),
4024 bus->ci->chiprev, bus->ci->pmurev);
4028 if (str_tab != NULL) {
4029 u32 drivestrength_sel = 0;
4033 for (i = 0; str_tab[i].strength != 0; i++) {
4034 if (drivestrength >= str_tab[i].strength) {
4035 drivestrength_sel = str_tab[i].sel;
4040 brcmf_sdcard_reg_write(bus->sdiodev,
4041 CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr),
4043 cc_data_temp = brcmf_sdcard_reg_read(bus->sdiodev,
4044 CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr), 4);
4045 cc_data_temp &= ~str_mask;
4046 drivestrength_sel <<= str_shift;
4047 cc_data_temp |= drivestrength_sel;
4048 brcmf_sdcard_reg_write(bus->sdiodev,
4049 CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr),
4052 brcmf_dbg(INFO, "SDIO: %dmA drive strength selected, set to 0x%08x\n",
4053 drivestrength, cc_data_temp);
4058 brcmf_sdbrcm_chip_recognition(struct brcmf_sdio_dev *sdiodev,
4059 struct chip_info *ci, u32 regs)
4065 * Chipid is assume to be at offset 0 from regs arg
4066 * For different chiptypes or old sdio hosts w/o chipcommon,
4067 * other ways of recognition should be added here.
4069 ci->cccorebase = regs;
4070 regdata = brcmf_sdcard_reg_read(sdiodev,
4071 CORE_CC_REG(ci->cccorebase, chipid), 4);
4072 ci->chip = regdata & CID_ID_MASK;
4073 ci->chiprev = (regdata & CID_REV_MASK) >> CID_REV_SHIFT;
4075 brcmf_dbg(INFO, "chipid=0x%x chiprev=%d\n", ci->chip, ci->chiprev);
4077 /* Address of cores for new chips should be added here */
4079 case BCM4329_CHIP_ID:
4080 ci->buscorebase = BCM4329_CORE_BUS_BASE;
4081 ci->ramcorebase = BCM4329_CORE_SOCRAM_BASE;
4082 ci->armcorebase = BCM4329_CORE_ARM_BASE;
4083 ci->ramsize = BCM4329_RAMSIZE;
4086 brcmf_dbg(ERROR, "chipid 0x%x is not supported\n", ci->chip);
4090 regdata = brcmf_sdcard_reg_read(sdiodev,
4091 CORE_SB(ci->cccorebase, sbidhigh), 4);
4092 ci->ccrev = SBCOREREV(regdata);
4094 regdata = brcmf_sdcard_reg_read(sdiodev,
4095 CORE_CC_REG(ci->cccorebase, pmucapabilities), 4);
4096 ci->pmurev = regdata & PCAP_REV_MASK;
4098 regdata = brcmf_sdcard_reg_read(sdiodev,
4099 CORE_SB(ci->buscorebase, sbidhigh), 4);
4100 ci->buscorerev = SBCOREREV(regdata);
4101 ci->buscoretype = (regdata & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT;
4103 brcmf_dbg(INFO, "ccrev=%d, pmurev=%d, buscore rev/type=%d/0x%x\n",
4104 ci->ccrev, ci->pmurev, ci->buscorerev, ci->buscoretype);
4106 /* get chipcommon capabilites */
4107 ci->cccaps = brcmf_sdcard_reg_read(sdiodev,
4108 CORE_CC_REG(ci->cccorebase, capabilities), 4);
4114 brcmf_sdbrcm_chip_attach(struct brcmf_bus *bus, u32 regs)
4116 struct chip_info *ci;
4120 brcmf_dbg(TRACE, "Enter\n");
4122 /* alloc chip_info_t */
4123 ci = kzalloc(sizeof(struct chip_info), GFP_ATOMIC);
4127 /* bus/core/clk setup for register access */
4128 /* Try forcing SDIO core to do ALPAvail request only */
4129 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ;
4130 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
4131 SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err);
4133 brcmf_dbg(ERROR, "error writing for HT off\n");
4137 /* If register supported, wait for ALPAvail and then force ALP */
4138 /* This may take up to 15 milliseconds */
4139 clkval = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
4140 SBSDIO_FUNC1_CHIPCLKCSR, NULL);
4141 if ((clkval & ~SBSDIO_AVBITS) == clkset) {
4143 brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
4144 SBSDIO_FUNC1_CHIPCLKCSR,
4146 !SBSDIO_ALPAV(clkval)),
4147 PMU_MAX_TRANSITION_DLY);
4148 if (!SBSDIO_ALPAV(clkval)) {
4149 brcmf_dbg(ERROR, "timeout on ALPAV wait, clkval 0x%02x\n",
4154 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF |
4156 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
4157 SBSDIO_FUNC1_CHIPCLKCSR,
4161 brcmf_dbg(ERROR, "ChipClkCSR access: wrote 0x%02x read 0x%02x\n",
4167 /* Also, disable the extra SDIO pull-ups */
4168 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
4169 SBSDIO_FUNC1_SDIOPULLUP, 0, NULL);
4171 err = brcmf_sdbrcm_chip_recognition(bus->sdiodev, ci, regs);
4176 * Make sure any on-chip ARM is off (in case strapping is wrong),
4177 * or downloaded code was already running.
4179 brcmf_sdbrcm_chip_disablecore(bus->sdiodev, ci->armcorebase);
4181 brcmf_sdcard_reg_write(bus->sdiodev,
4182 CORE_CC_REG(ci->cccorebase, gpiopullup), 4, 0);
4183 brcmf_sdcard_reg_write(bus->sdiodev,
4184 CORE_CC_REG(ci->cccorebase, gpiopulldown), 4, 0);
4186 /* Disable F2 to clear any intermediate frame state on the dongle */
4187 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0, SDIO_CCCR_IOEx,
4188 SDIO_FUNC_ENABLE_1, NULL);
4190 /* WAR: cmd52 backplane read so core HW will drop ALPReq */
4191 clkval = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
4194 /* Done with backplane-dependent accesses, can drop clock... */
4195 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
4196 SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
4207 brcmf_sdbrcm_probe_attach(struct brcmf_bus *bus, u32 regsva)
4214 bus->alp_only = true;
4216 /* Return the window to backplane enumeration space for core access */
4217 if (brcmf_sdcard_set_sbaddr_window(bus->sdiodev, SI_ENUM_BASE))
4218 brcmf_dbg(ERROR, "FAILED to return to SI_ENUM_BASE\n");
4221 printk(KERN_DEBUG "F1 signature read @0x18000000=0x%4x\n",
4222 brcmf_sdcard_reg_read(bus->sdiodev, SI_ENUM_BASE, 4));
4227 * Force PLL off until brcmf_sdbrcm_chip_attach()
4228 * programs PLL control regs
4231 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
4232 SBSDIO_FUNC1_CHIPCLKCSR,
4233 BRCMF_INIT_CLKCTL1, &err);
4236 brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
4237 SBSDIO_FUNC1_CHIPCLKCSR, &err);
4239 if (err || ((clkctl & ~SBSDIO_AVBITS) != BRCMF_INIT_CLKCTL1)) {
4240 brcmf_dbg(ERROR, "ChipClkCSR access: err %d wrote 0x%02x read 0x%02x\n",
4241 err, BRCMF_INIT_CLKCTL1, clkctl);
4245 if (brcmf_sdbrcm_chip_attach(bus, regsva)) {
4246 brcmf_dbg(ERROR, "brcmf_sdbrcm_chip_attach failed!\n");
4250 if (!brcmf_sdbrcm_chipmatch((u16) bus->ci->chip)) {
4251 brcmf_dbg(ERROR, "unsupported chip: 0x%04x\n", bus->ci->chip);
4255 brcmf_sdbrcm_sdiod_drive_strength_init(bus, SDIO_DRIVE_STRENGTH);
4257 /* Get info on the ARM and SOCRAM cores... */
4258 brcmf_sdcard_reg_read(bus->sdiodev,
4259 CORE_SB(bus->ci->armcorebase, sbidhigh), 4);
4260 bus->ramsize = bus->ci->ramsize;
4261 if (!(bus->ramsize)) {
4262 brcmf_dbg(ERROR, "failed to find SOCRAM memory!\n");
4266 /* Set core control so an SDIO reset does a backplane reset */
4267 reg_addr = bus->ci->buscorebase +
4268 offsetof(struct sdpcmd_regs, corecontrol);
4269 reg_val = brcmf_sdcard_reg_read(bus->sdiodev, reg_addr, sizeof(u32));
4270 brcmf_sdcard_reg_write(bus->sdiodev, reg_addr, sizeof(u32),
4271 reg_val | CC_BPRESEN);
4273 brcmu_pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN);
4275 /* Locate an appropriately-aligned portion of hdrbuf */
4276 bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0],
4279 /* Set the poll and/or interrupt flags */
4291 static bool brcmf_sdbrcm_probe_init(struct brcmf_bus *bus)
4293 brcmf_dbg(TRACE, "Enter\n");
4295 /* Disable F2 to clear any intermediate frame state on the dongle */
4296 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0, SDIO_CCCR_IOEx,
4297 SDIO_FUNC_ENABLE_1, NULL);
4299 bus->drvr->busstate = BRCMF_BUS_DOWN;
4300 bus->sleeping = false;
4301 bus->rxflow = false;
4303 /* Done with backplane-dependent accesses, can drop clock... */
4304 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
4305 SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
4307 /* ...and initialize clock/power states */
4308 bus->clkstate = CLK_SDONLY;
4309 bus->idletime = BRCMF_IDLE_INTERVAL;
4310 bus->idleclock = BRCMF_IDLE_ACTIVE;
4312 /* Query the F2 block size, set roundup accordingly */
4313 bus->blocksize = bus->sdiodev->func[2]->cur_blksize;
4314 bus->roundup = min(max_roundup, bus->blocksize);
4316 /* bus module does not support packet chaining */
4317 bus->use_rxchain = false;
4318 bus->sd_rxchain = false;
4324 brcmf_sdbrcm_watchdog_thread(void *data)
4326 struct brcmf_bus *bus = (struct brcmf_bus *)data;
4328 allow_signal(SIGTERM);
4329 /* Run until signal received */
4331 if (kthread_should_stop())
4333 if (!wait_for_completion_interruptible(&bus->watchdog_wait)) {
4334 brcmf_sdbrcm_bus_watchdog(bus->drvr);
4335 /* Count the tick for reference */
4336 bus->drvr->tickcnt++;
4344 brcmf_sdbrcm_watchdog(unsigned long data)
4346 struct brcmf_bus *bus = (struct brcmf_bus *)data;
4348 if (bus->watchdog_tsk) {
4349 complete(&bus->watchdog_wait);
4350 /* Reschedule the watchdog */
4351 if (bus->wd_timer_valid)
4352 mod_timer(&bus->timer,
4353 jiffies + BRCMF_WD_POLL_MS * HZ / 1000);
4358 brcmf_sdbrcm_chip_detach(struct brcmf_bus *bus)
4360 brcmf_dbg(TRACE, "Enter\n");
4366 static void brcmf_sdbrcm_release_dongle(struct brcmf_bus *bus)
4368 brcmf_dbg(TRACE, "Enter\n");
4371 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
4372 brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
4373 brcmf_sdbrcm_chip_detach(bus);
4374 if (bus->vars && bus->varsz)
4379 brcmf_dbg(TRACE, "Disconnected\n");
4382 /* Detach and free everything */
4383 static void brcmf_sdbrcm_release(struct brcmf_bus *bus)
4385 brcmf_dbg(TRACE, "Enter\n");
4388 /* De-register interrupt handler */
4389 brcmf_sdcard_intr_dereg(bus->sdiodev);
4392 brcmf_detach(bus->drvr);
4393 brcmf_sdbrcm_release_dongle(bus);
4397 brcmf_sdbrcm_release_malloc(bus);
4402 brcmf_dbg(TRACE, "Disconnected\n");
4405 void *brcmf_sdbrcm_probe(u16 bus_no, u16 slot, u16 func, uint bustype,
4406 u32 regsva, struct brcmf_sdio_dev *sdiodev)
4409 struct brcmf_bus *bus;
4411 /* Init global variables at run-time, not as part of the declaration.
4412 * This is required to support init/de-init of the driver.
4414 * of globals as part of the declaration results in non-deterministic
4415 * behavior since the value of the globals may be different on the
4416 * first time that the driver is initialized vs subsequent
4421 brcmf_dbg(TRACE, "Enter\n");
4423 /* We make an assumption about address window mappings:
4424 * regsva == SI_ENUM_BASE*/
4426 /* Allocate private bus interface state */
4427 bus = kzalloc(sizeof(struct brcmf_bus), GFP_ATOMIC);
4431 bus->sdiodev = sdiodev;
4433 bus->txbound = BRCMF_TXBOUND;
4434 bus->rxbound = BRCMF_RXBOUND;
4435 bus->txminmax = BRCMF_TXMINMAX;
4436 bus->tx_seq = SDPCM_SEQUENCE_WRAP - 1;
4437 bus->usebufpool = false; /* Use bufpool if allocated,
4438 else use locally malloced rxbuf */
4440 /* attempt to attach to the dongle */
4441 if (!(brcmf_sdbrcm_probe_attach(bus, regsva))) {
4442 brcmf_dbg(ERROR, "brcmf_sdbrcm_probe_attach failed\n");
4446 spin_lock_init(&bus->txqlock);
4447 init_waitqueue_head(&bus->ctrl_wait);
4448 init_waitqueue_head(&bus->dcmd_resp_wait);
4450 /* Set up the watchdog timer */
4451 init_timer(&bus->timer);
4452 bus->timer.data = (unsigned long)bus;
4453 bus->timer.function = brcmf_sdbrcm_watchdog;
4455 /* Initialize thread based operation and lock */
4456 sema_init(&bus->sdsem, 1);
4458 /* Initialize watchdog thread */
4459 init_completion(&bus->watchdog_wait);
4460 bus->watchdog_tsk = kthread_run(brcmf_sdbrcm_watchdog_thread,
4461 bus, "brcmf_watchdog");
4462 if (IS_ERR(bus->watchdog_tsk)) {
4464 "brcmf_watchdog thread failed to start\n");
4465 bus->watchdog_tsk = NULL;
4467 /* Initialize DPC thread */
4468 init_completion(&bus->dpc_wait);
4469 bus->dpc_tsk = kthread_run(brcmf_sdbrcm_dpc_thread,
4471 if (IS_ERR(bus->dpc_tsk)) {
4473 "brcmf_dpc thread failed to start\n");
4474 bus->dpc_tsk = NULL;
4477 /* Attach to the brcmf/OS/network interface */
4478 bus->drvr = brcmf_attach(bus, SDPCM_RESERVE);
4480 brcmf_dbg(ERROR, "brcmf_attach failed\n");
4484 /* Allocate buffers */
4485 if (!(brcmf_sdbrcm_probe_malloc(bus))) {
4486 brcmf_dbg(ERROR, "brcmf_sdbrcm_probe_malloc failed\n");
4490 if (!(brcmf_sdbrcm_probe_init(bus))) {
4491 brcmf_dbg(ERROR, "brcmf_sdbrcm_probe_init failed\n");
4495 /* Register interrupt callback, but mask it (not operational yet). */
4496 brcmf_dbg(INTR, "disable SDIO interrupts (not interested yet)\n");
4497 ret = brcmf_sdcard_intr_reg(bus->sdiodev);
4499 brcmf_dbg(ERROR, "FAILED: sdcard_intr_reg returned %d\n", ret);
4502 brcmf_dbg(INTR, "registered SDIO interrupt function ok\n");
4504 brcmf_dbg(INFO, "completed!!\n");
4506 /* if firmware path present try to download and bring up bus */
4507 ret = brcmf_bus_start(bus->drvr);
4509 if (ret == -ENOLINK) {
4510 brcmf_dbg(ERROR, "dongle is not responding\n");
4514 /* Ok, have the per-port tell the stack we're open for business */
4515 if (brcmf_net_attach(bus->drvr, 0) != 0) {
4516 brcmf_dbg(ERROR, "Net attach failed!!\n");
4523 brcmf_sdbrcm_release(bus);
4527 void brcmf_sdbrcm_disconnect(void *ptr)
4529 struct brcmf_bus *bus = (struct brcmf_bus *)ptr;
4531 brcmf_dbg(TRACE, "Enter\n");
4534 brcmf_sdbrcm_release(bus);
4536 brcmf_dbg(TRACE, "Disconnected\n");
4539 struct device *brcmf_bus_get_device(struct brcmf_bus *bus)
4541 return &bus->sdiodev->func[2]->dev;
4545 brcmf_sdbrcm_wd_timer(struct brcmf_bus *bus, uint wdtick)
4547 /* don't start the wd until fw is loaded */
4548 if (bus->drvr->busstate == BRCMF_BUS_DOWN)
4551 /* Totally stop the timer */
4552 if (!wdtick && bus->wd_timer_valid == true) {
4553 del_timer_sync(&bus->timer);
4554 bus->wd_timer_valid = false;
4555 bus->save_ms = wdtick;
4560 if (bus->save_ms != BRCMF_WD_POLL_MS) {
4561 if (bus->wd_timer_valid == true)
4562 /* Stop timer and restart at new value */
4563 del_timer_sync(&bus->timer);
4565 /* Create timer again when watchdog period is
4566 dynamically changed or in the first instance
4568 bus->timer.expires =
4569 jiffies + BRCMF_WD_POLL_MS * HZ / 1000;
4570 add_timer(&bus->timer);
4573 /* Re arm the timer, at last watchdog period */
4574 mod_timer(&bus->timer,
4575 jiffies + BRCMF_WD_POLL_MS * HZ / 1000);
4578 bus->wd_timer_valid = true;
4579 bus->save_ms = wdtick;