2 * SiliconBackplane Chipcommon core hardware definitions.
4 * The chipcommon core provides chip identification, SB control,
5 * JTAG, 0/1/2 UARTs, clock frequency control, a watchdog interrupt timer,
6 * GPIO interface, extbus, and support for serial and parallel flashes.
8 * $Id: sbchipc.h 343982 2012-07-11 00:29:37Z $
10 * Copyright (C) 1999-2011, Broadcom Corporation
12 * Unless you and Broadcom execute a separate written software license
13 * agreement governing use of this software, this software is licensed to you
14 * under the terms of the GNU General Public License version 2 (the "GPL"),
15 * available at http://www.broadcom.com/licenses/GPLv2.php, with the
16 * following added to such license:
18 * As a special exception, the copyright holders of this software give you
19 * permission to link this software with independent modules, and to copy and
20 * distribute the resulting executable under terms of your choice, provided that
21 * you also meet, for each linked independent module, the terms and conditions of
22 * the license of that module. An independent module is a module which is not
23 * derived from this software. The special exception does not apply to any
24 * modifications of the software.
26 * Notwithstanding the above, under no circumstances may you combine this
27 * software in any way with any other Broadcom software provided under a license
28 * other than the GPL, without Broadcom's express prior written consent.
35 #ifndef _LANGUAGE_ASSEMBLY
39 #define _PADLINE(line) pad ## line
40 #define _XSTR(line) _PADLINE(line)
41 #define PAD _XSTR(__LINE__)
44 typedef struct eci_prerev35 {
50 uint32 eci_inputintpolaritylo;
51 uint32 eci_inputintpolaritymi;
52 uint32 eci_inputintpolarityhi;
59 uint32 eci_eventmasklo;
60 uint32 eci_eventmaskmi;
61 uint32 eci_eventmaskhi;
65 typedef struct eci_rev35 {
72 uint32 eci_inputintpolaritylo;
73 uint32 eci_inputintpolarityhi;
78 uint32 eci_eventmasklo;
79 uint32 eci_eventmaskhi;
83 uint32 eci_uartescvalue;
84 uint32 eci_autobaudctr;
85 uint32 eci_uartfifolevel;
88 typedef volatile struct {
121 uint32 broadcastaddress;
122 uint32 broadcastdata;
131 uint32 gpiointpolarity;
136 uint32 gpioeventintmask;
142 uint32 gpioeventintpolarity;
146 uint32 gpiotimeroutmask;
149 uint32 clockcontrol_n;
150 uint32 clockcontrol_sb;
151 uint32 clockcontrol_pci;
152 uint32 clockcontrol_m2;
153 uint32 clockcontrol_m3;
156 uint32 capabilities_ext;
160 uint32 fref_sel_delay;
165 uint32 system_clk_ctl;
166 uint32 clkstatestretch;
188 uint32 pcmcia_config;
189 uint32 pcmcia_memwait;
190 uint32 pcmcia_attrwait;
191 uint32 pcmcia_iowait;
197 uint32 prog_waitcount;
199 uint32 flash_waitcount;
202 uint32 SECI_statusmask;
203 uint32 SECI_rxnibchanged;
212 uint32 seci_uart_data;
213 uint32 seci_uart_bauddiv;
214 uint32 seci_uart_fcr;
215 uint32 seci_uart_lcr;
216 uint32 seci_uart_mcr;
217 uint32 seci_uart_lsr;
218 uint32 seci_uart_msr;
219 uint32 seci_uart_baudadj;
249 uint32 pmucapabilities;
256 uint32 res_table_sel;
258 uint32 res_updn_timer;
264 uint32 res_req_timer_sel;
265 uint32 res_req_timer;
268 uint32 chipcontrol_addr;
269 uint32 chipcontrol_data;
270 uint32 regcontrol_addr;
271 uint32 regcontrol_data;
272 uint32 pllcontrol_addr;
273 uint32 pllcontrol_data;
284 #define CC_CAPABILITIES 4
285 #define CC_CHIPST 0x2c
286 #define CC_EROMPTR 0xfc
289 #define CC_OTPST 0x10
290 #define CC_JTAGCMD 0x30
291 #define CC_JTAGIR 0x34
292 #define CC_JTAGDR 0x38
293 #define CC_JTAGCTRL 0x3c
294 #define CC_GPIOPU 0x58
295 #define CC_GPIOPD 0x5c
296 #define CC_GPIOIN 0x60
297 #define CC_GPIOOUT 0x64
298 #define CC_GPIOOUTEN 0x68
299 #define CC_GPIOCTRL 0x6c
300 #define CC_GPIOPOL 0x70
301 #define CC_GPIOINTM 0x74
302 #define CC_WATCHDOG 0x80
303 #define CC_CLKC_N 0x90
304 #define CC_CLKC_M0 0x94
305 #define CC_CLKC_M1 0x98
306 #define CC_CLKC_M2 0x9c
307 #define CC_CLKC_M3 0xa0
308 #define CC_CLKDIV 0xa4
309 #define CC_SYS_CLK_CTL 0xc0
310 #define CC_CLK_CTL_ST SI_CLK_CTL_ST
311 #define PMU_CTL 0x600
312 #define PMU_CAP 0x604
314 #define PMU_RES_STATE 0x60c
315 #define PMU_TIMER 0x614
316 #define PMU_MIN_RES_MASK 0x618
317 #define PMU_MAX_RES_MASK 0x61c
318 #define CC_CHIPCTL_ADDR 0x650
319 #define CC_CHIPCTL_DATA 0x654
320 #define PMU_REG_CONTROL_ADDR 0x658
321 #define PMU_REG_CONTROL_DATA 0x65C
322 #define PMU_PLL_CONTROL_ADDR 0x660
323 #define PMU_PLL_CONTROL_DATA 0x664
324 #define CC_SROM_OTP 0x800
327 #define CID_ID_MASK 0x0000ffff
328 #define CID_REV_MASK 0x000f0000
329 #define CID_REV_SHIFT 16
330 #define CID_PKG_MASK 0x00f00000
331 #define CID_PKG_SHIFT 20
332 #define CID_CC_MASK 0x0f000000
333 #define CID_CC_SHIFT 24
334 #define CID_TYPE_MASK 0xf0000000
335 #define CID_TYPE_SHIFT 28
338 #define CC_CAP_UARTS_MASK 0x00000003
339 #define CC_CAP_MIPSEB 0x00000004
340 #define CC_CAP_UCLKSEL 0x00000018
341 #define CC_CAP_UINTCLK 0x00000008
342 #define CC_CAP_UARTGPIO 0x00000020
343 #define CC_CAP_EXTBUS_MASK 0x000000c0
344 #define CC_CAP_EXTBUS_NONE 0x00000000
345 #define CC_CAP_EXTBUS_FULL 0x00000040
346 #define CC_CAP_EXTBUS_PROG 0x00000080
347 #define CC_CAP_FLASH_MASK 0x00000700
348 #define CC_CAP_PLL_MASK 0x00038000
349 #define CC_CAP_PWR_CTL 0x00040000
350 #define CC_CAP_OTPSIZE 0x00380000
351 #define CC_CAP_OTPSIZE_SHIFT 19
352 #define CC_CAP_OTPSIZE_BASE 5
353 #define CC_CAP_JTAGP 0x00400000
354 #define CC_CAP_ROM 0x00800000
355 #define CC_CAP_BKPLN64 0x08000000
356 #define CC_CAP_PMU 0x10000000
357 #define CC_CAP_ECI 0x20000000
358 #define CC_CAP_SROM 0x40000000
359 #define CC_CAP_NFLASH 0x80000000
361 #define CC_CAP2_SECI 0x00000001
362 #define CC_CAP2_GSIO 0x00000002
365 #define CC_CAP_EXT_SECI_PRESENT 0x00000001
368 #define PLL_NONE 0x00000000
369 #define PLL_TYPE1 0x00010000
370 #define PLL_TYPE2 0x00020000
371 #define PLL_TYPE3 0x00030000
372 #define PLL_TYPE4 0x00008000
373 #define PLL_TYPE5 0x00018000
374 #define PLL_TYPE6 0x00028000
375 #define PLL_TYPE7 0x00038000
378 #define ILP_CLOCK 32000
381 #define ALP_CLOCK 20000000
384 #define HT_CLOCK 80000000
387 #define CC_UARTCLKO 0x00000001
388 #define CC_SE 0x00000002
389 #define CC_ASYNCGPIO 0x00000004
390 #define CC_UARTCLKEN 0x00000008
393 #define CHIPCTRL_4321A0_DEFAULT 0x3a4
394 #define CHIPCTRL_4321A1_DEFAULT 0x0a4
395 #define CHIPCTRL_4321_PLL_DOWN 0x800000
398 #define OTPS_OL_MASK 0x000000ff
399 #define OTPS_OL_MFG 0x00000001
400 #define OTPS_OL_OR1 0x00000002
401 #define OTPS_OL_OR2 0x00000004
402 #define OTPS_OL_GU 0x00000008
403 #define OTPS_GUP_MASK 0x00000f00
404 #define OTPS_GUP_SHIFT 8
405 #define OTPS_GUP_HW 0x00000100
406 #define OTPS_GUP_SW 0x00000200
407 #define OTPS_GUP_CI 0x00000400
408 #define OTPS_GUP_FUSE 0x00000800
409 #define OTPS_READY 0x00001000
410 #define OTPS_RV(x) (1 << (16 + (x)))
411 #define OTPS_RV_MASK 0x0fff0000
414 #define OTPC_PROGSEL 0x00000001
415 #define OTPC_PCOUNT_MASK 0x0000000e
416 #define OTPC_PCOUNT_SHIFT 1
417 #define OTPC_VSEL_MASK 0x000000f0
418 #define OTPC_VSEL_SHIFT 4
419 #define OTPC_TMM_MASK 0x00000700
420 #define OTPC_TMM_SHIFT 8
421 #define OTPC_ODM 0x00000800
422 #define OTPC_PROGEN 0x80000000
425 #define OTPP_COL_MASK 0x000000ff
426 #define OTPP_COL_SHIFT 0
427 #define OTPP_ROW_MASK 0x0000ff00
428 #define OTPP_ROW_SHIFT 8
429 #define OTPP_OC_MASK 0x0f000000
430 #define OTPP_OC_SHIFT 24
431 #define OTPP_READERR 0x10000000
432 #define OTPP_VALUE_MASK 0x20000000
433 #define OTPP_VALUE_SHIFT 29
434 #define OTPP_START_BUSY 0x80000000
435 #define OTPP_READ 0x40000000
438 #define OTP_CISFORMAT_NEW 0x80000000
441 #define OTPPOC_READ 0
442 #define OTPPOC_BIT_PROG 1
443 #define OTPPOC_VERIFY 3
444 #define OTPPOC_INIT 4
446 #define OTPPOC_RESET 6
447 #define OTPPOC_OCST 7
448 #define OTPPOC_ROW_LOCK 8
449 #define OTPPOC_PRESCN_TEST 9
453 #define JTAGM_CREV_OLD 10
454 #define JTAGM_CREV_IRP 22
455 #define JTAGM_CREV_RTI 28
458 #define JCMD_START 0x80000000
459 #define JCMD_BUSY 0x80000000
460 #define JCMD_STATE_MASK 0x60000000
461 #define JCMD_STATE_TLR 0x00000000
462 #define JCMD_STATE_PIR 0x20000000
463 #define JCMD_STATE_PDR 0x40000000
464 #define JCMD_STATE_RTI 0x60000000
465 #define JCMD0_ACC_MASK 0x0000f000
466 #define JCMD0_ACC_IRDR 0x00000000
467 #define JCMD0_ACC_DR 0x00001000
468 #define JCMD0_ACC_IR 0x00002000
469 #define JCMD0_ACC_RESET 0x00003000
470 #define JCMD0_ACC_IRPDR 0x00004000
471 #define JCMD0_ACC_PDR 0x00005000
472 #define JCMD0_IRW_MASK 0x00000f00
473 #define JCMD_ACC_MASK 0x000f0000
474 #define JCMD_ACC_IRDR 0x00000000
475 #define JCMD_ACC_DR 0x00010000
476 #define JCMD_ACC_IR 0x00020000
477 #define JCMD_ACC_RESET 0x00030000
478 #define JCMD_ACC_IRPDR 0x00040000
479 #define JCMD_ACC_PDR 0x00050000
480 #define JCMD_ACC_PIR 0x00060000
481 #define JCMD_ACC_IRDR_I 0x00070000
482 #define JCMD_ACC_DR_I 0x00080000
483 #define JCMD_IRW_MASK 0x00001f00
484 #define JCMD_IRW_SHIFT 8
485 #define JCMD_DRW_MASK 0x0000003f
488 #define JCTRL_FORCE_CLK 4
489 #define JCTRL_EXT_EN 2
493 #define CLKD_SFLASH 0x0f000000
494 #define CLKD_SFLASH_SHIFT 24
495 #define CLKD_OTP 0x000f0000
496 #define CLKD_OTP_SHIFT 16
497 #define CLKD_JTAG 0x00000f00
498 #define CLKD_JTAG_SHIFT 8
499 #define CLKD_UART 0x000000ff
501 #define CLKD2_SROM 0x00000003
504 #define CI_GPIO 0x00000001
505 #define CI_EI 0x00000002
506 #define CI_TEMP 0x00000004
507 #define CI_SIRQ 0x00000008
508 #define CI_ECI 0x00000010
509 #define CI_PMU 0x00000020
510 #define CI_UART 0x00000040
511 #define CI_WDRESET 0x80000000
514 #define SCC_SS_MASK 0x00000007
515 #define SCC_SS_LPO 0x00000000
516 #define SCC_SS_XTAL 0x00000001
517 #define SCC_SS_PCI 0x00000002
518 #define SCC_LF 0x00000200
519 #define SCC_LP 0x00000400
520 #define SCC_FS 0x00000800
521 #define SCC_IP 0x00001000
522 #define SCC_XC 0x00002000
523 #define SCC_XP 0x00004000
524 #define SCC_CD_MASK 0xffff0000
525 #define SCC_CD_SHIFT 16
528 #define SYCC_IE 0x00000001
529 #define SYCC_AE 0x00000002
530 #define SYCC_FP 0x00000004
531 #define SYCC_AR 0x00000008
532 #define SYCC_HR 0x00000010
533 #define SYCC_CD_MASK 0xffff0000
534 #define SYCC_CD_SHIFT 16
537 #define BPIA_BYTEEN 0x0000000f
538 #define BPIA_SZ1 0x00000001
539 #define BPIA_SZ2 0x00000003
540 #define BPIA_SZ4 0x00000007
541 #define BPIA_SZ8 0x0000000f
542 #define BPIA_WRITE 0x00000100
543 #define BPIA_START 0x00000200
544 #define BPIA_BUSY 0x00000200
545 #define BPIA_ERROR 0x00000400
548 #define CF_EN 0x00000001
549 #define CF_EM_MASK 0x0000000e
550 #define CF_EM_SHIFT 1
551 #define CF_EM_FLASH 0
553 #define CF_EM_PCMCIA 4
554 #define CF_DS 0x00000010
555 #define CF_BS 0x00000020
556 #define CF_CD_MASK 0x000000c0
557 #define CF_CD_SHIFT 6
558 #define CF_CD_DIV2 0x00000000
559 #define CF_CD_DIV3 0x00000040
560 #define CF_CD_DIV4 0x00000080
561 #define CF_CE 0x00000100
562 #define CF_SB 0x00000200
565 #define PM_W0_MASK 0x0000003f
566 #define PM_W1_MASK 0x00001f00
567 #define PM_W1_SHIFT 8
568 #define PM_W2_MASK 0x001f0000
569 #define PM_W2_SHIFT 16
570 #define PM_W3_MASK 0x1f000000
571 #define PM_W3_SHIFT 24
574 #define PA_W0_MASK 0x0000003f
575 #define PA_W1_MASK 0x00001f00
576 #define PA_W1_SHIFT 8
577 #define PA_W2_MASK 0x001f0000
578 #define PA_W2_SHIFT 16
579 #define PA_W3_MASK 0x1f000000
580 #define PA_W3_SHIFT 24
583 #define PI_W0_MASK 0x0000003f
584 #define PI_W1_MASK 0x00001f00
585 #define PI_W1_SHIFT 8
586 #define PI_W2_MASK 0x001f0000
587 #define PI_W2_SHIFT 16
588 #define PI_W3_MASK 0x1f000000
589 #define PI_W3_SHIFT 24
592 #define PW_W0_MASK 0x0000001f
593 #define PW_W1_MASK 0x00001f00
594 #define PW_W1_SHIFT 8
595 #define PW_W2_MASK 0x001f0000
596 #define PW_W2_SHIFT 16
597 #define PW_W3_MASK 0x1f000000
598 #define PW_W3_SHIFT 24
600 #define PW_W0 0x0000000c
601 #define PW_W1 0x00000a00
602 #define PW_W2 0x00020000
603 #define PW_W3 0x01000000
606 #define FW_W0_MASK 0x0000003f
607 #define FW_W1_MASK 0x00001f00
608 #define FW_W1_SHIFT 8
609 #define FW_W2_MASK 0x001f0000
610 #define FW_W2_SHIFT 16
611 #define FW_W3_MASK 0x1f000000
612 #define FW_W3_SHIFT 24
615 #define SRC_START 0x80000000
616 #define SRC_BUSY 0x80000000
617 #define SRC_OPCODE 0x60000000
618 #define SRC_OP_READ 0x00000000
619 #define SRC_OP_WRITE 0x20000000
620 #define SRC_OP_WRDIS 0x40000000
621 #define SRC_OP_WREN 0x60000000
622 #define SRC_OTPSEL 0x00000010
623 #define SRC_LOCK 0x00000008
624 #define SRC_SIZE_MASK 0x00000006
625 #define SRC_SIZE_1K 0x00000000
626 #define SRC_SIZE_4K 0x00000002
627 #define SRC_SIZE_16K 0x00000004
628 #define SRC_SIZE_SHIFT 1
629 #define SRC_PRESENT 0x00000001
632 #define PCTL_ILP_DIV_MASK 0xffff0000
633 #define PCTL_ILP_DIV_SHIFT 16
634 #define PCTL_PLL_PLLCTL_UPD 0x00000400
635 #define PCTL_NOILP_ON_WAIT 0x00000200
636 #define PCTL_HT_REQ_EN 0x00000100
637 #define PCTL_ALP_REQ_EN 0x00000080
638 #define PCTL_XTALFREQ_MASK 0x0000007c
639 #define PCTL_XTALFREQ_SHIFT 2
640 #define PCTL_ILP_DIV_EN 0x00000002
641 #define PCTL_LPO_SEL 0x00000001
644 #define CSTRETCH_HT 0xffff0000
645 #define CSTRETCH_ALP 0x0000ffff
648 #define GPIO_ONTIME_SHIFT 16
651 #define CN_N1_MASK 0x3f
652 #define CN_N2_MASK 0x3f00
653 #define CN_N2_SHIFT 8
654 #define CN_PLLC_MASK 0xf0000
655 #define CN_PLLC_SHIFT 16
658 #define CC_M1_MASK 0x3f
659 #define CC_M2_MASK 0x3f00
660 #define CC_M2_SHIFT 8
661 #define CC_M3_MASK 0x3f0000
662 #define CC_M3_SHIFT 16
663 #define CC_MC_MASK 0x1f000000
664 #define CC_MC_SHIFT 24
676 #define CC_MC_BYPASS 0x08
677 #define CC_MC_M1 0x04
678 #define CC_MC_M1M2 0x02
679 #define CC_MC_M1M2M3 0x01
680 #define CC_MC_M1M3 0x11
684 #define CC_T2M2_BIAS 3
686 #define CC_T2MC_M1BYP 1
687 #define CC_T2MC_M2BYP 2
688 #define CC_T2MC_M3BYP 4
691 #define CC_T6_MMASK 1
692 #define CC_T6_M0 120000000
693 #define CC_T6_M1 100000000
694 #define SB2MIPS_T6(sb) (2 * (sb))
697 #define CC_CLOCK_BASE1 24000000
698 #define CC_CLOCK_BASE2 12500000
701 #define CLKC_5350_N 0x0311
702 #define CLKC_5350_M 0x04020009
705 #define FLASH_NONE 0x000
706 #define SFLASH_ST 0x100
707 #define SFLASH_AT 0x200
711 #define CC_CFG_EN 0x0001
712 #define CC_CFG_EM_MASK 0x000e
713 #define CC_CFG_EM_ASYNC 0x0000
714 #define CC_CFG_EM_SYNC 0x0002
715 #define CC_CFG_EM_PCMCIA 0x0004
716 #define CC_CFG_EM_IDE 0x0006
717 #define CC_CFG_DS 0x0010
718 #define CC_CFG_CD_MASK 0x00e0
719 #define CC_CFG_CE 0x0100
720 #define CC_CFG_SB 0x0200
721 #define CC_CFG_IS 0x0400
724 #define CC_EB_BASE 0x1a000000
725 #define CC_EB_PCMCIA_MEM 0x1a000000
726 #define CC_EB_PCMCIA_IO 0x1a200000
727 #define CC_EB_PCMCIA_CFG 0x1a400000
728 #define CC_EB_IDE 0x1a800000
729 #define CC_EB_PCMCIA1_MEM 0x1a800000
730 #define CC_EB_PCMCIA1_IO 0x1aa00000
731 #define CC_EB_PCMCIA1_CFG 0x1ac00000
732 #define CC_EB_PROGIF 0x1b000000
736 #define SFLASH_OPCODE 0x000000ff
737 #define SFLASH_ACTION 0x00000700
738 #define SFLASH_CS_ACTIVE 0x00001000
739 #define SFLASH_START 0x80000000
740 #define SFLASH_BUSY SFLASH_START
743 #define SFLASH_ACT_OPONLY 0x0000
744 #define SFLASH_ACT_OP1D 0x0100
745 #define SFLASH_ACT_OP3A 0x0200
746 #define SFLASH_ACT_OP3A1D 0x0300
747 #define SFLASH_ACT_OP3A4D 0x0400
748 #define SFLASH_ACT_OP3A4X4D 0x0500
749 #define SFLASH_ACT_OP3A1X4D 0x0700
752 #define SFLASH_ST_WREN 0x0006
753 #define SFLASH_ST_WRDIS 0x0004
754 #define SFLASH_ST_RDSR 0x0105
755 #define SFLASH_ST_WRSR 0x0101
756 #define SFLASH_ST_READ 0x0303
757 #define SFLASH_ST_PP 0x0302
758 #define SFLASH_ST_SE 0x02d8
759 #define SFLASH_ST_BE 0x00c7
760 #define SFLASH_ST_DP 0x00b9
761 #define SFLASH_ST_RES 0x03ab
762 #define SFLASH_ST_CSA 0x1000
763 #define SFLASH_ST_SSE 0x0220
766 #define SFLASH_ST_WIP 0x01
767 #define SFLASH_ST_WEL 0x02
768 #define SFLASH_ST_BP_MASK 0x1c
769 #define SFLASH_ST_BP_SHIFT 2
770 #define SFLASH_ST_SRWD 0x80
773 #define SFLASH_AT_READ 0x07e8
774 #define SFLASH_AT_PAGE_READ 0x07d2
775 #define SFLASH_AT_BUF1_READ
776 #define SFLASH_AT_BUF2_READ
777 #define SFLASH_AT_STATUS 0x01d7
778 #define SFLASH_AT_BUF1_WRITE 0x0384
779 #define SFLASH_AT_BUF2_WRITE 0x0387
780 #define SFLASH_AT_BUF1_ERASE_PROGRAM 0x0283
781 #define SFLASH_AT_BUF2_ERASE_PROGRAM 0x0286
782 #define SFLASH_AT_BUF1_PROGRAM 0x0288
783 #define SFLASH_AT_BUF2_PROGRAM 0x0289
784 #define SFLASH_AT_PAGE_ERASE 0x0281
785 #define SFLASH_AT_BLOCK_ERASE 0x0250
786 #define SFLASH_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382
787 #define SFLASH_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385
788 #define SFLASH_AT_BUF1_LOAD 0x0253
789 #define SFLASH_AT_BUF2_LOAD 0x0255
790 #define SFLASH_AT_BUF1_COMPARE 0x0260
791 #define SFLASH_AT_BUF2_COMPARE 0x0261
792 #define SFLASH_AT_BUF1_REPROGRAM 0x0258
793 #define SFLASH_AT_BUF2_REPROGRAM 0x0259
796 #define SFLASH_AT_READY 0x80
797 #define SFLASH_AT_MISMATCH 0x40
798 #define SFLASH_AT_ID_MASK 0x38
799 #define SFLASH_AT_ID_SHIFT 3
802 #define GSIO_START 0x80000000
803 #define GSIO_BUSY GSIO_START
819 #define UART_LCR_DLAB 0x80
820 #define UART_LCR_WLEN8 0x03
821 #define UART_MCR_OUT2 0x08
822 #define UART_MCR_LOOP 0x10
823 #define UART_LSR_RX_FIFO 0x80
824 #define UART_LSR_TDHR 0x40
825 #define UART_LSR_THRE 0x20
826 #define UART_LSR_BREAK 0x10
827 #define UART_LSR_FRAMING 0x08
828 #define UART_LSR_PARITY 0x04
829 #define UART_LSR_OVERRUN 0x02
830 #define UART_LSR_RXRDY 0x01
831 #define UART_FCR_FIFO_ENABLE 1
834 #define UART_IIR_FIFO_MASK 0xc0
835 #define UART_IIR_INT_MASK 0xf
836 #define UART_IIR_MDM_CHG 0x0
837 #define UART_IIR_NOINT 0x1
838 #define UART_IIR_THRE 0x2
839 #define UART_IIR_RCVD_DATA 0x4
840 #define UART_IIR_RCVR_STATUS 0x6
841 #define UART_IIR_CHAR_TIME 0xc
844 #define UART_IER_EDSSI 8
845 #define UART_IER_ELSI 4
846 #define UART_IER_ETBEI 2
847 #define UART_IER_ERBFI 1
850 #define PST_EXTLPOAVAIL 0x0100
851 #define PST_WDRESET 0x0080
852 #define PST_INTPEND 0x0040
853 #define PST_SBCLKST 0x0030
854 #define PST_SBCLKST_ILP 0x0010
855 #define PST_SBCLKST_ALP 0x0020
856 #define PST_SBCLKST_HT 0x0030
857 #define PST_ALPAVAIL 0x0008
858 #define PST_HTAVAIL 0x0004
859 #define PST_RESINIT 0x0003
862 #define PCAP_REV_MASK 0x000000ff
863 #define PCAP_RC_MASK 0x00001f00
864 #define PCAP_RC_SHIFT 8
865 #define PCAP_TC_MASK 0x0001e000
866 #define PCAP_TC_SHIFT 13
867 #define PCAP_PC_MASK 0x001e0000
868 #define PCAP_PC_SHIFT 17
869 #define PCAP_VC_MASK 0x01e00000
870 #define PCAP_VC_SHIFT 21
871 #define PCAP_CC_MASK 0x1e000000
872 #define PCAP_CC_SHIFT 25
873 #define PCAP5_PC_MASK 0x003e0000
874 #define PCAP5_PC_SHIFT 17
875 #define PCAP5_VC_MASK 0x07c00000
876 #define PCAP5_VC_SHIFT 22
877 #define PCAP5_CC_MASK 0xf8000000
878 #define PCAP5_CC_SHIFT 27
882 #define PRRT_TIME_MASK 0x03ff
883 #define PRRT_INTEN 0x0400
884 #define PRRT_REQ_ACTIVE 0x0800
885 #define PRRT_ALP_REQ 0x1000
886 #define PRRT_HT_REQ 0x2000
889 #define PMURES_BIT(bit) (1 << (bit))
892 #define PMURES_MAX_RESNUM 30
895 #define PMU_CHIPCTL0 0
898 #define PMU_CC1_CLKREQ_TYPE_SHIFT 19
899 #define PMU_CC1_CLKREQ_TYPE_MASK (1 << PMU_CC1_CLKREQ_TYPE_SHIFT)
901 #define CLKREQ_TYPE_CONFIG_OPENDRAIN 0
902 #define CLKREQ_TYPE_CONFIG_PUSHPULL 1
905 #define PMU_CHIPCTL1 1
906 #define PMU_CC1_RXC_DLL_BYPASS 0x00010000
908 #define PMU_CC1_IF_TYPE_MASK 0x00000030
909 #define PMU_CC1_IF_TYPE_RMII 0x00000000
910 #define PMU_CC1_IF_TYPE_MII 0x00000010
911 #define PMU_CC1_IF_TYPE_RGMII 0x00000020
913 #define PMU_CC1_SW_TYPE_MASK 0x000000c0
914 #define PMU_CC1_SW_TYPE_EPHY 0x00000000
915 #define PMU_CC1_SW_TYPE_EPHYMII 0x00000040
916 #define PMU_CC1_SW_TYPE_EPHYRMII 0x00000080
917 #define PMU_CC1_SW_TYPE_RGMII 0x000000c0
923 #define PMU0_PLL0_PLLCTL0 0
924 #define PMU0_PLL0_PC0_PDIV_MASK 1
925 #define PMU0_PLL0_PC0_PDIV_FREQ 25000
926 #define PMU0_PLL0_PC0_DIV_ARM_MASK 0x00000038
927 #define PMU0_PLL0_PC0_DIV_ARM_SHIFT 3
928 #define PMU0_PLL0_PC0_DIV_ARM_BASE 8
931 #define PMU0_PLL0_PC0_DIV_ARM_110MHZ 0
932 #define PMU0_PLL0_PC0_DIV_ARM_97_7MHZ 1
933 #define PMU0_PLL0_PC0_DIV_ARM_88MHZ 2
934 #define PMU0_PLL0_PC0_DIV_ARM_80MHZ 3
935 #define PMU0_PLL0_PC0_DIV_ARM_73_3MHZ 4
936 #define PMU0_PLL0_PC0_DIV_ARM_67_7MHZ 5
937 #define PMU0_PLL0_PC0_DIV_ARM_62_9MHZ 6
938 #define PMU0_PLL0_PC0_DIV_ARM_58_6MHZ 7
941 #define PMU0_PLL0_PLLCTL1 1
942 #define PMU0_PLL0_PC1_WILD_INT_MASK 0xf0000000
943 #define PMU0_PLL0_PC1_WILD_INT_SHIFT 28
944 #define PMU0_PLL0_PC1_WILD_FRAC_MASK 0x0fffff00
945 #define PMU0_PLL0_PC1_WILD_FRAC_SHIFT 8
946 #define PMU0_PLL0_PC1_STOP_MOD 0x00000040
949 #define PMU0_PLL0_PLLCTL2 2
950 #define PMU0_PLL0_PC2_WILD_INT_MASK 0xf
951 #define PMU0_PLL0_PC2_WILD_INT_SHIFT 4
955 #define PMU1_PLL0_PLLCTL0 0
956 #define PMU1_PLL0_PC0_P1DIV_MASK 0x00f00000
957 #define PMU1_PLL0_PC0_P1DIV_SHIFT 20
958 #define PMU1_PLL0_PC0_P2DIV_MASK 0x0f000000
959 #define PMU1_PLL0_PC0_P2DIV_SHIFT 24
962 #define PMU1_PLL0_PLLCTL1 1
963 #define PMU1_PLL0_PC1_M1DIV_MASK 0x000000ff
964 #define PMU1_PLL0_PC1_M1DIV_SHIFT 0
965 #define PMU1_PLL0_PC1_M2DIV_MASK 0x0000ff00
966 #define PMU1_PLL0_PC1_M2DIV_SHIFT 8
967 #define PMU1_PLL0_PC1_M3DIV_MASK 0x00ff0000
968 #define PMU1_PLL0_PC1_M3DIV_SHIFT 16
969 #define PMU1_PLL0_PC1_M4DIV_MASK 0xff000000
970 #define PMU1_PLL0_PC1_M4DIV_SHIFT 24
971 #define PMU1_PLL0_PC1_M4DIV_BY_9 9
972 #define PMU1_PLL0_PC1_M4DIV_BY_18 0x12
973 #define PMU1_PLL0_PC1_M4DIV_BY_36 0x24
975 #define DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT 8
976 #define DOT11MAC_880MHZ_CLK_DIVISOR_MASK (0xFF << DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT)
977 #define DOT11MAC_880MHZ_CLK_DIVISOR_VAL (0xE << DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT)
980 #define PMU1_PLL0_PLLCTL2 2
981 #define PMU1_PLL0_PC2_M5DIV_MASK 0x000000ff
982 #define PMU1_PLL0_PC2_M5DIV_SHIFT 0
983 #define PMU1_PLL0_PC2_M5DIV_BY_12 0xc
984 #define PMU1_PLL0_PC2_M5DIV_BY_18 0x12
985 #define PMU1_PLL0_PC2_M5DIV_BY_36 0x24
986 #define PMU1_PLL0_PC2_M6DIV_MASK 0x0000ff00
987 #define PMU1_PLL0_PC2_M6DIV_SHIFT 8
988 #define PMU1_PLL0_PC2_M6DIV_BY_18 0x12
989 #define PMU1_PLL0_PC2_M6DIV_BY_36 0x24
990 #define PMU1_PLL0_PC2_NDIV_MODE_MASK 0x000e0000
991 #define PMU1_PLL0_PC2_NDIV_MODE_SHIFT 17
992 #define PMU1_PLL0_PC2_NDIV_MODE_MASH 1
993 #define PMU1_PLL0_PC2_NDIV_MODE_MFB 2
994 #define PMU1_PLL0_PC2_NDIV_INT_MASK 0x1ff00000
995 #define PMU1_PLL0_PC2_NDIV_INT_SHIFT 20
998 #define PMU1_PLL0_PLLCTL3 3
999 #define PMU1_PLL0_PC3_NDIV_FRAC_MASK 0x00ffffff
1000 #define PMU1_PLL0_PC3_NDIV_FRAC_SHIFT 0
1003 #define PMU1_PLL0_PLLCTL4 4
1006 #define PMU1_PLL0_PLLCTL5 5
1007 #define PMU1_PLL0_PC5_CLK_DRV_MASK 0xffffff00
1008 #define PMU1_PLL0_PC5_CLK_DRV_SHIFT 8
1011 #define PMU2_PHY_PLL_PLLCTL 4
1012 #define PMU2_SI_PLL_PLLCTL 10
1017 #define PMU2_PLL_PLLCTL0 0
1018 #define PMU2_PLL_PC0_P1DIV_MASK 0x00f00000
1019 #define PMU2_PLL_PC0_P1DIV_SHIFT 20
1020 #define PMU2_PLL_PC0_P2DIV_MASK 0x0f000000
1021 #define PMU2_PLL_PC0_P2DIV_SHIFT 24
1024 #define PMU2_PLL_PLLCTL1 1
1025 #define PMU2_PLL_PC1_M1DIV_MASK 0x000000ff
1026 #define PMU2_PLL_PC1_M1DIV_SHIFT 0
1027 #define PMU2_PLL_PC1_M2DIV_MASK 0x0000ff00
1028 #define PMU2_PLL_PC1_M2DIV_SHIFT 8
1029 #define PMU2_PLL_PC1_M3DIV_MASK 0x00ff0000
1030 #define PMU2_PLL_PC1_M3DIV_SHIFT 16
1031 #define PMU2_PLL_PC1_M4DIV_MASK 0xff000000
1032 #define PMU2_PLL_PC1_M4DIV_SHIFT 24
1035 #define PMU2_PLL_PLLCTL2 2
1036 #define PMU2_PLL_PC2_M5DIV_MASK 0x000000ff
1037 #define PMU2_PLL_PC2_M5DIV_SHIFT 0
1038 #define PMU2_PLL_PC2_M6DIV_MASK 0x0000ff00
1039 #define PMU2_PLL_PC2_M6DIV_SHIFT 8
1040 #define PMU2_PLL_PC2_NDIV_MODE_MASK 0x000e0000
1041 #define PMU2_PLL_PC2_NDIV_MODE_SHIFT 17
1042 #define PMU2_PLL_PC2_NDIV_INT_MASK 0x1ff00000
1043 #define PMU2_PLL_PC2_NDIV_INT_SHIFT 20
1046 #define PMU2_PLL_PLLCTL3 3
1047 #define PMU2_PLL_PC3_NDIV_FRAC_MASK 0x00ffffff
1048 #define PMU2_PLL_PC3_NDIV_FRAC_SHIFT 0
1051 #define PMU2_PLL_PLLCTL4 4
1054 #define PMU2_PLL_PLLCTL5 5
1055 #define PMU2_PLL_PC5_CLKDRIVE_CH1_MASK 0x00000f00
1056 #define PMU2_PLL_PC5_CLKDRIVE_CH1_SHIFT 8
1057 #define PMU2_PLL_PC5_CLKDRIVE_CH2_MASK 0x0000f000
1058 #define PMU2_PLL_PC5_CLKDRIVE_CH2_SHIFT 12
1059 #define PMU2_PLL_PC5_CLKDRIVE_CH3_MASK 0x000f0000
1060 #define PMU2_PLL_PC5_CLKDRIVE_CH3_SHIFT 16
1061 #define PMU2_PLL_PC5_CLKDRIVE_CH4_MASK 0x00f00000
1062 #define PMU2_PLL_PC5_CLKDRIVE_CH4_SHIFT 20
1063 #define PMU2_PLL_PC5_CLKDRIVE_CH5_MASK 0x0f000000
1064 #define PMU2_PLL_PC5_CLKDRIVE_CH5_SHIFT 24
1065 #define PMU2_PLL_PC5_CLKDRIVE_CH6_MASK 0xf0000000
1066 #define PMU2_PLL_PC5_CLKDRIVE_CH6_SHIFT 28
1069 #define PMU5_PLL_P1P2_OFF 0
1070 #define PMU5_PLL_P1_MASK 0x0f000000
1071 #define PMU5_PLL_P1_SHIFT 24
1072 #define PMU5_PLL_P2_MASK 0x00f00000
1073 #define PMU5_PLL_P2_SHIFT 20
1074 #define PMU5_PLL_M14_OFF 1
1075 #define PMU5_PLL_MDIV_MASK 0x000000ff
1076 #define PMU5_PLL_MDIV_WIDTH 8
1077 #define PMU5_PLL_NM5_OFF 2
1078 #define PMU5_PLL_NDIV_MASK 0xfff00000
1079 #define PMU5_PLL_NDIV_SHIFT 20
1080 #define PMU5_PLL_NDIV_MODE_MASK 0x000e0000
1081 #define PMU5_PLL_NDIV_MODE_SHIFT 17
1082 #define PMU5_PLL_FMAB_OFF 3
1083 #define PMU5_PLL_MRAT_MASK 0xf0000000
1084 #define PMU5_PLL_MRAT_SHIFT 28
1085 #define PMU5_PLL_ABRAT_MASK 0x08000000
1086 #define PMU5_PLL_ABRAT_SHIFT 27
1087 #define PMU5_PLL_FDIV_MASK 0x07ffffff
1088 #define PMU5_PLL_PLLCTL_OFF 4
1089 #define PMU5_PLL_PCHI_OFF 5
1090 #define PMU5_PLL_PCHI_MASK 0x0000003f
1093 #define PMU_XTALFREQ_REG_ILPCTR_MASK 0x00001FFF
1094 #define PMU_XTALFREQ_REG_MEASURE_MASK 0x80000000
1095 #define PMU_XTALFREQ_REG_MEASURE_SHIFT 31
1098 #define PMU5_MAINPLL_CPU 1
1099 #define PMU5_MAINPLL_MEM 2
1100 #define PMU5_MAINPLL_SI 3
1102 #define PMU7_PLL_PLLCTL7 7
1103 #define PMU7_PLL_CTL7_M4DIV_MASK 0xff000000
1104 #define PMU7_PLL_CTL7_M4DIV_SHIFT 24
1105 #define PMU7_PLL_CTL7_M4DIV_BY_6 6
1106 #define PMU7_PLL_CTL7_M4DIV_BY_12 0xc
1107 #define PMU7_PLL_CTL7_M4DIV_BY_24 0x18
1108 #define PMU7_PLL_PLLCTL8 8
1109 #define PMU7_PLL_CTL8_M5DIV_MASK 0x000000ff
1110 #define PMU7_PLL_CTL8_M5DIV_SHIFT 0
1111 #define PMU7_PLL_CTL8_M5DIV_BY_8 8
1112 #define PMU7_PLL_CTL8_M5DIV_BY_12 0xc
1113 #define PMU7_PLL_CTL8_M5DIV_BY_24 0x18
1114 #define PMU7_PLL_CTL8_M6DIV_MASK 0x0000ff00
1115 #define PMU7_PLL_CTL8_M6DIV_SHIFT 8
1116 #define PMU7_PLL_CTL8_M6DIV_BY_12 0xc
1117 #define PMU7_PLL_CTL8_M6DIV_BY_24 0x18
1118 #define PMU7_PLL_PLLCTL11 11
1119 #define PMU7_PLL_PLLCTL11_MASK 0xffffff00
1120 #define PMU7_PLL_PLLCTL11_VAL 0x22222200
1123 #define PMU4716_MAINPLL_PLL0 12
1126 #define PMU5356_MAINPLL_PLL0 0
1127 #define PMU5357_MAINPLL_PLL0 0
1130 #define RES4716_PROC_PLL_ON 0x00000040
1131 #define RES4716_PROC_HT_AVAIL 0x00000080
1134 #define CCTRL_471X_I2S_PINS_ENABLE 0x0080
1138 #define CCTRL_5357_I2S_PINS_ENABLE 0x00040000
1139 #define CCTRL_5357_I2CSPI_PINS_ENABLE 0x00080000
1142 #define RES5354_EXT_SWITCHER_PWM 0
1143 #define RES5354_BB_SWITCHER_PWM 1
1144 #define RES5354_BB_SWITCHER_BURST 2
1145 #define RES5354_BB_EXT_SWITCHER_BURST 3
1146 #define RES5354_ILP_REQUEST 4
1147 #define RES5354_RADIO_SWITCHER_PWM 5
1148 #define RES5354_RADIO_SWITCHER_BURST 6
1149 #define RES5354_ROM_SWITCH 7
1150 #define RES5354_PA_REF_LDO 8
1151 #define RES5354_RADIO_LDO 9
1152 #define RES5354_AFE_LDO 10
1153 #define RES5354_PLL_LDO 11
1154 #define RES5354_BG_FILTBYP 12
1155 #define RES5354_TX_FILTBYP 13
1156 #define RES5354_RX_FILTBYP 14
1157 #define RES5354_XTAL_PU 15
1158 #define RES5354_XTAL_EN 16
1159 #define RES5354_BB_PLL_FILTBYP 17
1160 #define RES5354_RF_PLL_FILTBYP 18
1161 #define RES5354_BB_PLL_PU 19
1164 #define CCTRL5357_EXTPA (1<<14)
1165 #define CCTRL5357_ANT_MUX_2o3 (1<<15)
1168 #define RES4328_EXT_SWITCHER_PWM 0
1169 #define RES4328_BB_SWITCHER_PWM 1
1170 #define RES4328_BB_SWITCHER_BURST 2
1171 #define RES4328_BB_EXT_SWITCHER_BURST 3
1172 #define RES4328_ILP_REQUEST 4
1173 #define RES4328_RADIO_SWITCHER_PWM 5
1174 #define RES4328_RADIO_SWITCHER_BURST 6
1175 #define RES4328_ROM_SWITCH 7
1176 #define RES4328_PA_REF_LDO 8
1177 #define RES4328_RADIO_LDO 9
1178 #define RES4328_AFE_LDO 10
1179 #define RES4328_PLL_LDO 11
1180 #define RES4328_BG_FILTBYP 12
1181 #define RES4328_TX_FILTBYP 13
1182 #define RES4328_RX_FILTBYP 14
1183 #define RES4328_XTAL_PU 15
1184 #define RES4328_XTAL_EN 16
1185 #define RES4328_BB_PLL_FILTBYP 17
1186 #define RES4328_RF_PLL_FILTBYP 18
1187 #define RES4328_BB_PLL_PU 19
1190 #define RES4325_BUCK_BOOST_BURST 0
1191 #define RES4325_CBUCK_BURST 1
1192 #define RES4325_CBUCK_PWM 2
1193 #define RES4325_CLDO_CBUCK_BURST 3
1194 #define RES4325_CLDO_CBUCK_PWM 4
1195 #define RES4325_BUCK_BOOST_PWM 5
1196 #define RES4325_ILP_REQUEST 6
1197 #define RES4325_ABUCK_BURST 7
1198 #define RES4325_ABUCK_PWM 8
1199 #define RES4325_LNLDO1_PU 9
1200 #define RES4325_OTP_PU 10
1201 #define RES4325_LNLDO3_PU 11
1202 #define RES4325_LNLDO4_PU 12
1203 #define RES4325_XTAL_PU 13
1204 #define RES4325_ALP_AVAIL 14
1205 #define RES4325_RX_PWRSW_PU 15
1206 #define RES4325_TX_PWRSW_PU 16
1207 #define RES4325_RFPLL_PWRSW_PU 17
1208 #define RES4325_LOGEN_PWRSW_PU 18
1209 #define RES4325_AFE_PWRSW_PU 19
1210 #define RES4325_BBPLL_PWRSW_PU 20
1211 #define RES4325_HT_AVAIL 21
1214 #define RES4325B0_CBUCK_LPOM 1
1215 #define RES4325B0_CBUCK_BURST 2
1216 #define RES4325B0_CBUCK_PWM 3
1217 #define RES4325B0_CLDO_PU 4
1220 #define RES4325C1_LNLDO2_PU 12
1223 #define CST4325_SPROM_OTP_SEL_MASK 0x00000003
1224 #define CST4325_DEFCIS_SEL 0
1225 #define CST4325_SPROM_SEL 1
1226 #define CST4325_OTP_SEL 2
1227 #define CST4325_OTP_PWRDN 3
1228 #define CST4325_SDIO_USB_MODE_MASK 0x00000004
1229 #define CST4325_SDIO_USB_MODE_SHIFT 2
1230 #define CST4325_RCAL_VALID_MASK 0x00000008
1231 #define CST4325_RCAL_VALID_SHIFT 3
1232 #define CST4325_RCAL_VALUE_MASK 0x000001f0
1233 #define CST4325_RCAL_VALUE_SHIFT 4
1234 #define CST4325_PMUTOP_2B_MASK 0x00000200
1235 #define CST4325_PMUTOP_2B_SHIFT 9
1237 #define RES4329_RESERVED0 0
1238 #define RES4329_CBUCK_LPOM 1
1239 #define RES4329_CBUCK_BURST 2
1240 #define RES4329_CBUCK_PWM 3
1241 #define RES4329_CLDO_PU 4
1242 #define RES4329_PALDO_PU 5
1243 #define RES4329_ILP_REQUEST 6
1244 #define RES4329_RESERVED7 7
1245 #define RES4329_RESERVED8 8
1246 #define RES4329_LNLDO1_PU 9
1247 #define RES4329_OTP_PU 10
1248 #define RES4329_RESERVED11 11
1249 #define RES4329_LNLDO2_PU 12
1250 #define RES4329_XTAL_PU 13
1251 #define RES4329_ALP_AVAIL 14
1252 #define RES4329_RX_PWRSW_PU 15
1253 #define RES4329_TX_PWRSW_PU 16
1254 #define RES4329_RFPLL_PWRSW_PU 17
1255 #define RES4329_LOGEN_PWRSW_PU 18
1256 #define RES4329_AFE_PWRSW_PU 19
1257 #define RES4329_BBPLL_PWRSW_PU 20
1258 #define RES4329_HT_AVAIL 21
1260 #define CST4329_SPROM_OTP_SEL_MASK 0x00000003
1261 #define CST4329_DEFCIS_SEL 0
1262 #define CST4329_SPROM_SEL 1
1263 #define CST4329_OTP_SEL 2
1264 #define CST4329_OTP_PWRDN 3
1265 #define CST4329_SPI_SDIO_MODE_MASK 0x00000004
1266 #define CST4329_SPI_SDIO_MODE_SHIFT 2
1269 #define CST4312_SPROM_OTP_SEL_MASK 0x00000003
1270 #define CST4312_DEFCIS_SEL 0
1271 #define CST4312_SPROM_SEL 1
1272 #define CST4312_OTP_SEL 2
1273 #define CST4312_OTP_BAD 3
1276 #define RES4312_SWITCHER_BURST 0
1277 #define RES4312_SWITCHER_PWM 1
1278 #define RES4312_PA_REF_LDO 2
1279 #define RES4312_CORE_LDO_BURST 3
1280 #define RES4312_CORE_LDO_PWM 4
1281 #define RES4312_RADIO_LDO 5
1282 #define RES4312_ILP_REQUEST 6
1283 #define RES4312_BG_FILTBYP 7
1284 #define RES4312_TX_FILTBYP 8
1285 #define RES4312_RX_FILTBYP 9
1286 #define RES4312_XTAL_PU 10
1287 #define RES4312_ALP_AVAIL 11
1288 #define RES4312_BB_PLL_FILTBYP 12
1289 #define RES4312_RF_PLL_FILTBYP 13
1290 #define RES4312_HT_AVAIL 14
1293 #define RES4322_RF_LDO 0
1294 #define RES4322_ILP_REQUEST 1
1295 #define RES4322_XTAL_PU 2
1296 #define RES4322_ALP_AVAIL 3
1297 #define RES4322_SI_PLL_ON 4
1298 #define RES4322_HT_SI_AVAIL 5
1299 #define RES4322_PHY_PLL_ON 6
1300 #define RES4322_HT_PHY_AVAIL 7
1301 #define RES4322_OTP_PU 8
1304 #define CST4322_XTAL_FREQ_20_40MHZ 0x00000020
1305 #define CST4322_SPROM_OTP_SEL_MASK 0x000000c0
1306 #define CST4322_SPROM_OTP_SEL_SHIFT 6
1307 #define CST4322_NO_SPROM_OTP 0
1308 #define CST4322_SPROM_PRESENT 1
1309 #define CST4322_OTP_PRESENT 2
1310 #define CST4322_PCI_OR_USB 0x00000100
1311 #define CST4322_BOOT_MASK 0x00000600
1312 #define CST4322_BOOT_SHIFT 9
1313 #define CST4322_BOOT_FROM_SRAM 0
1314 #define CST4322_BOOT_FROM_ROM 1
1315 #define CST4322_BOOT_FROM_FLASH 2
1316 #define CST4322_BOOT_FROM_INVALID 3
1317 #define CST4322_ILP_DIV_EN 0x00000800
1318 #define CST4322_FLASH_TYPE_MASK 0x00001000
1319 #define CST4322_FLASH_TYPE_SHIFT 12
1320 #define CST4322_FLASH_TYPE_SHIFT_ST 0
1321 #define CST4322_FLASH_TYPE_SHIFT_ATMEL 1
1322 #define CST4322_ARM_TAP_SEL 0x00002000
1323 #define CST4322_RES_INIT_MODE_MASK 0x0000c000
1324 #define CST4322_RES_INIT_MODE_SHIFT 14
1325 #define CST4322_RES_INIT_MODE_ILPAVAIL 0
1326 #define CST4322_RES_INIT_MODE_ILPREQ 1
1327 #define CST4322_RES_INIT_MODE_ALPAVAIL 2
1328 #define CST4322_RES_INIT_MODE_HTAVAIL 3
1329 #define CST4322_PCIPLLCLK_GATING 0x00010000
1330 #define CST4322_CLK_SWITCH_PCI_TO_ALP 0x00020000
1331 #define CST4322_PCI_CARDBUS_MODE 0x00040000
1334 #define CCTRL43224_GPIO_TOGGLE 0x8000
1335 #define CCTRL_43224A0_12MA_LED_DRIVE 0x00F000F0
1336 #define CCTRL_43224B0_12MA_LED_DRIVE 0xF0
1339 #define RES43236_REGULATOR 0
1340 #define RES43236_ILP_REQUEST 1
1341 #define RES43236_XTAL_PU 2
1342 #define RES43236_ALP_AVAIL 3
1343 #define RES43236_SI_PLL_ON 4
1344 #define RES43236_HT_SI_AVAIL 5
1347 #define CCTRL43236_BT_COEXIST (1<<0)
1348 #define CCTRL43236_SECI (1<<1)
1349 #define CCTRL43236_EXT_LNA (1<<2)
1350 #define CCTRL43236_ANT_MUX_2o3 (1<<3)
1351 #define CCTRL43236_GSIO (1<<4)
1354 #define CST43236_SFLASH_MASK 0x00000040
1355 #define CST43236_OTP_SEL_MASK 0x00000080
1356 #define CST43236_OTP_SEL_SHIFT 7
1357 #define CST43236_HSIC_MASK 0x00000100
1358 #define CST43236_BP_CLK 0x00000200
1359 #define CST43236_BOOT_MASK 0x00001800
1360 #define CST43236_BOOT_SHIFT 11
1361 #define CST43236_BOOT_FROM_SRAM 0
1362 #define CST43236_BOOT_FROM_ROM 1
1363 #define CST43236_BOOT_FROM_FLASH 2
1364 #define CST43236_BOOT_FROM_INVALID 3
1367 #define RES43237_REGULATOR 0
1368 #define RES43237_ILP_REQUEST 1
1369 #define RES43237_XTAL_PU 2
1370 #define RES43237_ALP_AVAIL 3
1371 #define RES43237_SI_PLL_ON 4
1372 #define RES43237_HT_SI_AVAIL 5
1375 #define CCTRL43237_BT_COEXIST (1<<0)
1376 #define CCTRL43237_SECI (1<<1)
1377 #define CCTRL43237_EXT_LNA (1<<2)
1378 #define CCTRL43237_ANT_MUX_2o3 (1<<3)
1379 #define CCTRL43237_GSIO (1<<4)
1382 #define CST43237_SFLASH_MASK 0x00000040
1383 #define CST43237_OTP_SEL_MASK 0x00000080
1384 #define CST43237_OTP_SEL_SHIFT 7
1385 #define CST43237_HSIC_MASK 0x00000100
1386 #define CST43237_BP_CLK 0x00000200
1387 #define CST43237_BOOT_MASK 0x00001800
1388 #define CST43237_BOOT_SHIFT 11
1389 #define CST43237_BOOT_FROM_SRAM 0
1390 #define CST43237_BOOT_FROM_ROM 1
1391 #define CST43237_BOOT_FROM_FLASH 2
1392 #define CST43237_BOOT_FROM_INVALID 3
1395 #define RES43239_CBUCK_LPOM 0
1396 #define RES43239_CBUCK_BURST 1
1397 #define RES43239_CBUCK_LP_PWM 2
1398 #define RES43239_CBUCK_PWM 3
1399 #define RES43239_CLDO_PU 4
1400 #define RES43239_DIS_INT_RESET_PD 5
1401 #define RES43239_ILP_REQUEST 6
1402 #define RES43239_LNLDO_PU 7
1403 #define RES43239_LDO3P3_PU 8
1404 #define RES43239_OTP_PU 9
1405 #define RES43239_XTAL_PU 10
1406 #define RES43239_ALP_AVAIL 11
1407 #define RES43239_RADIO_PU 12
1408 #define RES43239_MACPHY_CLKAVAIL 23
1409 #define RES43239_HT_AVAIL 24
1410 #define RES43239_XOLDO_PU 25
1411 #define RES43239_WL_XTAL_CTL_SEL 26
1412 #define RES43239_SR_CLK_STABLE 27
1413 #define RES43239_SR_SAVE_RESTORE 28
1414 #define RES43239_SR_PHY_PIC 29
1415 #define RES43239_SR_PHY_PWR_SW 30
1418 #define CST43239_SPROM_MASK 0x00000002
1419 #define CST43239_SFLASH_MASK 0x00000004
1420 #define CST43239_RES_INIT_MODE_SHIFT 7
1421 #define CST43239_RES_INIT_MODE_MASK 0x000001f0
1422 #define CST43239_CHIPMODE_SDIOD(cs) ((cs) & (1 << 15))
1423 #define CST43239_CHIPMODE_USB20D(cs) (~(cs) & (1 << 15))
1424 #define CST43239_CHIPMODE_SDIO(cs) (((cs) & (1 << 0)) == 0)
1425 #define CST43239_CHIPMODE_GSPI(cs) (((cs) & (1 << 0)) == (1 << 0))
1428 #define CCTRL43239_XTAL_STRENGTH(ctl) ((ctl & 0x3F) << 12)
1431 #define RES4331_REGULATOR 0
1432 #define RES4331_ILP_REQUEST 1
1433 #define RES4331_XTAL_PU 2
1434 #define RES4331_ALP_AVAIL 3
1435 #define RES4331_SI_PLL_ON 4
1436 #define RES4331_HT_SI_AVAIL 5
1439 #define CCTRL4331_BT_COEXIST (1<<0)
1440 #define CCTRL4331_SECI (1<<1)
1441 #define CCTRL4331_EXT_LNA_G (1<<2)
1442 #define CCTRL4331_SPROM_GPIO13_15 (1<<3)
1443 #define CCTRL4331_EXTPA_EN (1<<4)
1444 #define CCTRL4331_GPIOCLK_ON_SPROMCS (1<<5)
1445 #define CCTRL4331_PCIE_MDIO_ON_SPROMCS (1<<6)
1446 #define CCTRL4331_EXTPA_ON_GPIO2_5 (1<<7)
1447 #define CCTRL4331_OVR_PIPEAUXCLKEN (1<<8)
1448 #define CCTRL4331_OVR_PIPEAUXPWRDOWN (1<<9)
1449 #define CCTRL4331_PCIE_AUXCLKEN (1<<10)
1450 #define CCTRL4331_PCIE_PIPE_PLLDOWN (1<<11)
1451 #define CCTRL4331_EXTPA_EN2 (1<<12)
1452 #define CCTRL4331_EXT_LNA_A (1<<13)
1453 #define CCTRL4331_BT_SHD0_ON_GPIO4 (1<<16)
1454 #define CCTRL4331_BT_SHD1_ON_GPIO5 (1<<17)
1455 #define CCTRL4331_EXTPA_ANA_EN (1<<24)
1458 #define CST4331_XTAL_FREQ 0x00000001
1459 #define CST4331_SPROM_OTP_SEL_MASK 0x00000006
1460 #define CST4331_SPROM_OTP_SEL_SHIFT 1
1461 #define CST4331_SPROM_PRESENT 0x00000002
1462 #define CST4331_OTP_PRESENT 0x00000004
1463 #define CST4331_LDO_RF 0x00000008
1464 #define CST4331_LDO_PAR 0x00000010
1467 #define RES4315_CBUCK_LPOM 1
1468 #define RES4315_CBUCK_BURST 2
1469 #define RES4315_CBUCK_PWM 3
1470 #define RES4315_CLDO_PU 4
1471 #define RES4315_PALDO_PU 5
1472 #define RES4315_ILP_REQUEST 6
1473 #define RES4315_LNLDO1_PU 9
1474 #define RES4315_OTP_PU 10
1475 #define RES4315_LNLDO2_PU 12
1476 #define RES4315_XTAL_PU 13
1477 #define RES4315_ALP_AVAIL 14
1478 #define RES4315_RX_PWRSW_PU 15
1479 #define RES4315_TX_PWRSW_PU 16
1480 #define RES4315_RFPLL_PWRSW_PU 17
1481 #define RES4315_LOGEN_PWRSW_PU 18
1482 #define RES4315_AFE_PWRSW_PU 19
1483 #define RES4315_BBPLL_PWRSW_PU 20
1484 #define RES4315_HT_AVAIL 21
1487 #define CST4315_SPROM_OTP_SEL_MASK 0x00000003
1488 #define CST4315_DEFCIS_SEL 0x00000000
1489 #define CST4315_SPROM_SEL 0x00000001
1490 #define CST4315_OTP_SEL 0x00000002
1491 #define CST4315_OTP_PWRDN 0x00000003
1492 #define CST4315_SDIO_MODE 0x00000004
1493 #define CST4315_RCAL_VALID 0x00000008
1494 #define CST4315_RCAL_VALUE_MASK 0x000001f0
1495 #define CST4315_RCAL_VALUE_SHIFT 4
1496 #define CST4315_PALDO_EXTPNP 0x00000200
1497 #define CST4315_CBUCK_MODE_MASK 0x00000c00
1498 #define CST4315_CBUCK_MODE_BURST 0x00000400
1499 #define CST4315_CBUCK_MODE_LPBURST 0x00000c00
1502 #define RES4319_CBUCK_LPOM 1
1503 #define RES4319_CBUCK_BURST 2
1504 #define RES4319_CBUCK_PWM 3
1505 #define RES4319_CLDO_PU 4
1506 #define RES4319_PALDO_PU 5
1507 #define RES4319_ILP_REQUEST 6
1508 #define RES4319_LNLDO1_PU 9
1509 #define RES4319_OTP_PU 10
1510 #define RES4319_LNLDO2_PU 12
1511 #define RES4319_XTAL_PU 13
1512 #define RES4319_ALP_AVAIL 14
1513 #define RES4319_RX_PWRSW_PU 15
1514 #define RES4319_TX_PWRSW_PU 16
1515 #define RES4319_RFPLL_PWRSW_PU 17
1516 #define RES4319_LOGEN_PWRSW_PU 18
1517 #define RES4319_AFE_PWRSW_PU 19
1518 #define RES4319_BBPLL_PWRSW_PU 20
1519 #define RES4319_HT_AVAIL 21
1522 #define CST4319_SPI_CPULESSUSB 0x00000001
1523 #define CST4319_SPI_CLK_POL 0x00000002
1524 #define CST4319_SPI_CLK_PH 0x00000008
1525 #define CST4319_SPROM_OTP_SEL_MASK 0x000000c0
1526 #define CST4319_SPROM_OTP_SEL_SHIFT 6
1527 #define CST4319_DEFCIS_SEL 0x00000000
1528 #define CST4319_SPROM_SEL 0x00000040
1529 #define CST4319_OTP_SEL 0x00000080
1530 #define CST4319_OTP_PWRDN 0x000000c0
1531 #define CST4319_SDIO_USB_MODE 0x00000100
1532 #define CST4319_REMAP_SEL_MASK 0x00000600
1533 #define CST4319_ILPDIV_EN 0x00000800
1534 #define CST4319_XTAL_PD_POL 0x00001000
1535 #define CST4319_LPO_SEL 0x00002000
1536 #define CST4319_RES_INIT_MODE 0x0000c000
1537 #define CST4319_PALDO_EXTPNP 0x00010000
1538 #define CST4319_CBUCK_MODE_MASK 0x00060000
1539 #define CST4319_CBUCK_MODE_BURST 0x00020000
1540 #define CST4319_CBUCK_MODE_LPBURST 0x00060000
1541 #define CST4319_RCAL_VALID 0x01000000
1542 #define CST4319_RCAL_VALUE_MASK 0x3e000000
1543 #define CST4319_RCAL_VALUE_SHIFT 25
1545 #define PMU1_PLL0_CHIPCTL0 0
1546 #define PMU1_PLL0_CHIPCTL1 1
1547 #define PMU1_PLL0_CHIPCTL2 2
1548 #define CCTL_4319USB_XTAL_SEL_MASK 0x00180000
1549 #define CCTL_4319USB_XTAL_SEL_SHIFT 19
1550 #define CCTL_4319USB_48MHZ_PLL_SEL 1
1551 #define CCTL_4319USB_24MHZ_PLL_SEL 2
1554 #define RES4336_CBUCK_LPOM 0
1555 #define RES4336_CBUCK_BURST 1
1556 #define RES4336_CBUCK_LP_PWM 2
1557 #define RES4336_CBUCK_PWM 3
1558 #define RES4336_CLDO_PU 4
1559 #define RES4336_DIS_INT_RESET_PD 5
1560 #define RES4336_ILP_REQUEST 6
1561 #define RES4336_LNLDO_PU 7
1562 #define RES4336_LDO3P3_PU 8
1563 #define RES4336_OTP_PU 9
1564 #define RES4336_XTAL_PU 10
1565 #define RES4336_ALP_AVAIL 11
1566 #define RES4336_RADIO_PU 12
1567 #define RES4336_BG_PU 13
1568 #define RES4336_VREG1p4_PU_PU 14
1569 #define RES4336_AFE_PWRSW_PU 15
1570 #define RES4336_RX_PWRSW_PU 16
1571 #define RES4336_TX_PWRSW_PU 17
1572 #define RES4336_BB_PWRSW_PU 18
1573 #define RES4336_SYNTH_PWRSW_PU 19
1574 #define RES4336_MISC_PWRSW_PU 20
1575 #define RES4336_LOGEN_PWRSW_PU 21
1576 #define RES4336_BBPLL_PWRSW_PU 22
1577 #define RES4336_MACPHY_CLKAVAIL 23
1578 #define RES4336_HT_AVAIL 24
1579 #define RES4336_RSVD 25
1582 #define CST4336_SPI_MODE_MASK 0x00000001
1583 #define CST4336_SPROM_PRESENT 0x00000002
1584 #define CST4336_OTP_PRESENT 0x00000004
1585 #define CST4336_ARMREMAP_0 0x00000008
1586 #define CST4336_ILPDIV_EN_MASK 0x00000010
1587 #define CST4336_ILPDIV_EN_SHIFT 4
1588 #define CST4336_XTAL_PD_POL_MASK 0x00000020
1589 #define CST4336_XTAL_PD_POL_SHIFT 5
1590 #define CST4336_LPO_SEL_MASK 0x00000040
1591 #define CST4336_LPO_SEL_SHIFT 6
1592 #define CST4336_RES_INIT_MODE_MASK 0x00000180
1593 #define CST4336_RES_INIT_MODE_SHIFT 7
1594 #define CST4336_CBUCK_MODE_MASK 0x00000600
1595 #define CST4336_CBUCK_MODE_SHIFT 9
1598 #define PCTL_4336_SERIAL_ENAB (1 << 24)
1601 #define RES4330_CBUCK_LPOM 0
1602 #define RES4330_CBUCK_BURST 1
1603 #define RES4330_CBUCK_LP_PWM 2
1604 #define RES4330_CBUCK_PWM 3
1605 #define RES4330_CLDO_PU 4
1606 #define RES4330_DIS_INT_RESET_PD 5
1607 #define RES4330_ILP_REQUEST 6
1608 #define RES4330_LNLDO_PU 7
1609 #define RES4330_LDO3P3_PU 8
1610 #define RES4330_OTP_PU 9
1611 #define RES4330_XTAL_PU 10
1612 #define RES4330_ALP_AVAIL 11
1613 #define RES4330_RADIO_PU 12
1614 #define RES4330_BG_PU 13
1615 #define RES4330_VREG1p4_PU_PU 14
1616 #define RES4330_AFE_PWRSW_PU 15
1617 #define RES4330_RX_PWRSW_PU 16
1618 #define RES4330_TX_PWRSW_PU 17
1619 #define RES4330_BB_PWRSW_PU 18
1620 #define RES4330_SYNTH_PWRSW_PU 19
1621 #define RES4330_MISC_PWRSW_PU 20
1622 #define RES4330_LOGEN_PWRSW_PU 21
1623 #define RES4330_BBPLL_PWRSW_PU 22
1624 #define RES4330_MACPHY_CLKAVAIL 23
1625 #define RES4330_HT_AVAIL 24
1626 #define RES4330_5gRX_PWRSW_PU 25
1627 #define RES4330_5gTX_PWRSW_PU 26
1628 #define RES4330_5g_LOGEN_PWRSW_PU 27
1631 #define CST4330_CHIPMODE_SDIOD(cs) (((cs) & 0x7) < 6)
1632 #define CST4330_CHIPMODE_USB20D(cs) (((cs) & 0x7) >= 6)
1633 #define CST4330_CHIPMODE_SDIO(cs) (((cs) & 0x4) == 0)
1634 #define CST4330_CHIPMODE_GSPI(cs) (((cs) & 0x6) == 4)
1635 #define CST4330_CHIPMODE_USB(cs) (((cs) & 0x7) == 6)
1636 #define CST4330_CHIPMODE_USBDA(cs) (((cs) & 0x7) == 7)
1637 #define CST4330_OTP_PRESENT 0x00000010
1638 #define CST4330_LPO_AUTODET_EN 0x00000020
1639 #define CST4330_ARMREMAP_0 0x00000040
1640 #define CST4330_SPROM_PRESENT 0x00000080
1641 #define CST4330_ILPDIV_EN 0x00000100
1642 #define CST4330_LPO_SEL 0x00000200
1643 #define CST4330_RES_INIT_MODE_SHIFT 10
1644 #define CST4330_RES_INIT_MODE_MASK 0x00000c00
1645 #define CST4330_CBUCK_MODE_SHIFT 12
1646 #define CST4330_CBUCK_MODE_MASK 0x00003000
1647 #define CST4330_CBUCK_POWER_OK 0x00004000
1648 #define CST4330_BB_PLL_LOCKED 0x00008000
1649 #define SOCDEVRAM_4330_BP_ADDR 0x1E000000
1650 #define SOCDEVRAM_4330_ARM_ADDR 0x00800000
1653 #define PCTL_4330_SERIAL_ENAB (1 << 24)
1656 #define CCTRL_4330_GPIO_SEL 0x00000001
1657 #define CCTRL_4330_ERCX_SEL 0x00000002
1658 #define CCTRL_4330_SDIO_HOST_WAKE 0x00000004
1659 #define CCTRL_4330_JTAG_DISABLE 0x00000008
1662 #define CCTRL_43239_GPIO_SEL 0x00000002
1663 #define CCTRL_43239_SDIO_HOST_WAKE 0x00000004
1665 #define RES4313_BB_PU_RSRC 0
1666 #define RES4313_ILP_REQ_RSRC 1
1667 #define RES4313_XTAL_PU_RSRC 2
1668 #define RES4313_ALP_AVAIL_RSRC 3
1669 #define RES4313_RADIO_PU_RSRC 4
1670 #define RES4313_BG_PU_RSRC 5
1671 #define RES4313_VREG1P4_PU_RSRC 6
1672 #define RES4313_AFE_PWRSW_RSRC 7
1673 #define RES4313_RX_PWRSW_RSRC 8
1674 #define RES4313_TX_PWRSW_RSRC 9
1675 #define RES4313_BB_PWRSW_RSRC 10
1676 #define RES4313_SYNTH_PWRSW_RSRC 11
1677 #define RES4313_MISC_PWRSW_RSRC 12
1678 #define RES4313_BB_PLL_PWRSW_RSRC 13
1679 #define RES4313_HT_AVAIL_RSRC 14
1680 #define RES4313_MACPHY_CLK_AVAIL_RSRC 15
1683 #define CST4313_SPROM_PRESENT 1
1684 #define CST4313_OTP_PRESENT 2
1685 #define CST4313_SPROM_OTP_SEL_MASK 0x00000002
1686 #define CST4313_SPROM_OTP_SEL_SHIFT 0
1689 #define CCTRL_4313_12MA_LED_DRIVE 0x00000007
1692 #define RES43228_NOT_USED 0
1693 #define RES43228_ILP_REQUEST 1
1694 #define RES43228_XTAL_PU 2
1695 #define RES43228_ALP_AVAIL 3
1696 #define RES43228_PLL_EN 4
1697 #define RES43228_HT_PHY_AVAIL 5
1700 #define CST43228_ILP_DIV_EN 0x1
1701 #define CST43228_OTP_PRESENT 0x2
1702 #define CST43228_SERDES_REFCLK_PADSEL 0x4
1703 #define CST43228_SDIO_MODE 0x8
1704 #define CST43228_SDIO_OTP_PRESENT 0x10
1705 #define CST43228_SDIO_RESET 0x20
1708 #define PMU_MAX_TRANSITION_DLY 15000
1711 #define PMURES_UP_TRANSITION 2
1715 #define SECI_MODE_UART 0x0
1716 #define SECI_MODE_SECI 0x1
1717 #define SECI_MODE_LEGACY_3WIRE_BT 0x2
1718 #define SECI_MODE_LEGACY_3WIRE_WLAN 0x3
1719 #define SECI_MODE_HALF_SECI 0x4
1721 #define SECI_RESET (1 << 0)
1722 #define SECI_RESET_BAR_UART (1 << 1)
1723 #define SECI_ENAB_SECI_ECI (1 << 2)
1724 #define SECI_ENAB_SECIOUT_DIS (1 << 3)
1725 #define SECI_MODE_MASK 0x7
1726 #define SECI_MODE_SHIFT 4
1727 #define SECI_UPD_SECI (1 << 7)
1729 #define SECI_SLIP_ESC_CHAR 0xDB
1730 #define SECI_SIGNOFF_0 SECI_SLIP_ESC_CHAR
1731 #define SECI_SIGNOFF_1 0
1732 #define SECI_REFRESH_REQ 0xDA
1735 #define CLKCTL_STS_SECI_CLK_REQ (1 << 8)
1736 #define CLKCTL_STS_SECI_CLK_AVAIL (1 << 24)
1738 #define SECI_UART_MSR_CTS_STATE (1 << 0)
1739 #define SECI_UART_MSR_RTS_STATE (1 << 1)
1740 #define SECI_UART_SECI_IN_STATE (1 << 2)
1741 #define SECI_UART_SECI_IN2_STATE (1 << 3)
1744 #define SECI_UART_LCR_STOP_BITS (1 << 0)
1745 #define SECI_UART_LCR_PARITY_EN (1 << 1)
1746 #define SECI_UART_LCR_PARITY (1 << 2)
1747 #define SECI_UART_LCR_RX_EN (1 << 3)
1748 #define SECI_UART_LCR_LBRK_CTRL (1 << 4)
1749 #define SECI_UART_LCR_TXO_EN (1 << 5)
1750 #define SECI_UART_LCR_RTSO_EN (1 << 6)
1751 #define SECI_UART_LCR_SLIPMODE_EN (1 << 7)
1752 #define SECI_UART_LCR_RXCRC_CHK (1 << 8)
1753 #define SECI_UART_LCR_TXCRC_INV (1 << 9)
1754 #define SECI_UART_LCR_TXCRC_LSBF (1 << 10)
1755 #define SECI_UART_LCR_TXCRC_EN (1 << 11)
1757 #define SECI_UART_MCR_TX_EN (1 << 0)
1758 #define SECI_UART_MCR_PRTS (1 << 1)
1759 #define SECI_UART_MCR_SWFLCTRL_EN (1 << 2)
1760 #define SECI_UART_MCR_HIGHRATE_EN (1 << 3)
1761 #define SECI_UART_MCR_LOOPBK_EN (1 << 4)
1762 #define SECI_UART_MCR_AUTO_RTS (1 << 5)
1763 #define SECI_UART_MCR_AUTO_TX_DIS (1 << 6)
1764 #define SECI_UART_MCR_BAUD_ADJ_EN (1 << 7)
1765 #define SECI_UART_MCR_XONOFF_RPT (1 << 9)
1770 #define ECI_BW_20 0x0
1771 #define ECI_BW_25 0x1
1772 #define ECI_BW_30 0x2
1773 #define ECI_BW_35 0x3
1774 #define ECI_BW_40 0x4
1775 #define ECI_BW_45 0x5
1776 #define ECI_BW_50 0x6
1777 #define ECI_BW_ALL 0x7
1780 #define WLAN_NUM_ANT1 TXANT_0
1781 #define WLAN_NUM_ANT2 TXANT_1
projects / firefly-linux-kernel-4.4.55.git / blob