2 * Broadcom device-specific manifest constants.
4 * Copyright (C) 1999-2011, Broadcom Corporation
6 * Unless you and Broadcom execute a separate written software license
7 * agreement governing use of this software, this software is licensed to you
8 * under the terms of the GNU General Public License version 2 (the "GPL"),
9 * available at http://www.broadcom.com/licenses/GPLv2.php, with the
10 * following added to such license:
12 * As a special exception, the copyright holders of this software give you
13 * permission to link this software with independent modules, and to copy and
14 * distribute the resulting executable under terms of your choice, provided that
15 * you also meet, for each linked independent module, the terms and conditions of
16 * the license of that module. An independent module is a module which is not
17 * derived from this software. The special exception does not apply to any
18 * modifications of the software.
20 * Notwithstanding the above, under no circumstances may you combine this
21 * software in any way with any other Broadcom software provided under a license
22 * other than the GPL, without Broadcom's express prior written consent.
24 * $Id: bcmdevs.h 332966 2012-05-11 22:40:21Z $
32 #define VENDOR_EPIGRAM 0xfeda
33 #define VENDOR_BROADCOM 0x14e4
34 #define VENDOR_3COM 0x10b7
35 #define VENDOR_NETGEAR 0x1385
36 #define VENDOR_DIAMOND 0x1092
37 #define VENDOR_INTEL 0x8086
38 #define VENDOR_DELL 0x1028
39 #define VENDOR_HP 0x103c
40 #define VENDOR_HP_COMPAQ 0x0e11
41 #define VENDOR_APPLE 0x106b
42 #define VENDOR_SI_IMAGE 0x1095
43 #define VENDOR_BUFFALO 0x1154
44 #define VENDOR_TI 0x104c
45 #define VENDOR_RICOH 0x1180
46 #define VENDOR_JMICRON 0x197b
50 #define VENDOR_BROADCOM_PCMCIA 0x02d0
53 #define VENDOR_BROADCOM_SDIO 0x00BF
56 #define BCM_DNGL_VID 0x0a5c
57 #define BCM_DNGL_BL_PID_4328 0xbd12
58 #define BCM_DNGL_BL_PID_4322 0xbd13
59 #define BCM_DNGL_BL_PID_4319 0xbd16
60 #define BCM_DNGL_BL_PID_43236 0xbd17
61 #define BCM_DNGL_BL_PID_4332 0xbd18
62 #define BCM_DNGL_BL_PID_4330 0xbd19
63 #define BCM_DNGL_BL_PID_43239 0xbd1b
64 #define BCM_DNGL_BDC_PID 0x0bdc
65 #define BCM_DNGL_JTAG_PID 0x4a44
66 #define BCM_DNGL_BL_PID_4324 0xbd1c
69 #define BCM_HWUSB_PID_43239 43239
72 #define BCM4210_DEVICE_ID 0x1072
73 #define BCM4230_DEVICE_ID 0x1086
74 #define BCM4401_ENET_ID 0x170c
75 #define BCM3352_DEVICE_ID 0x3352
76 #define BCM3360_DEVICE_ID 0x3360
77 #define BCM4211_DEVICE_ID 0x4211
78 #define BCM4231_DEVICE_ID 0x4231
79 #define BCM4303_D11B_ID 0x4303
80 #define BCM4311_D11G_ID 0x4311
81 #define BCM4311_D11DUAL_ID 0x4312
82 #define BCM4311_D11A_ID 0x4313
83 #define BCM4328_D11DUAL_ID 0x4314
84 #define BCM4328_D11G_ID 0x4315
85 #define BCM4328_D11A_ID 0x4316
86 #define BCM4318_D11G_ID 0x4318
87 #define BCM4318_D11DUAL_ID 0x4319
88 #define BCM4318_D11A_ID 0x431a
89 #define BCM4325_D11DUAL_ID 0x431b
90 #define BCM4325_D11G_ID 0x431c
91 #define BCM4325_D11A_ID 0x431d
92 #define BCM4306_D11G_ID 0x4320
93 #define BCM4306_D11A_ID 0x4321
94 #define BCM4306_UART_ID 0x4322
95 #define BCM4306_V90_ID 0x4323
96 #define BCM4306_D11DUAL_ID 0x4324
97 #define BCM4306_D11G_ID2 0x4325
98 #define BCM4321_D11N_ID 0x4328
99 #define BCM4321_D11N2G_ID 0x4329
100 #define BCM4321_D11N5G_ID 0x432a
101 #define BCM4322_D11N_ID 0x432b
102 #define BCM4322_D11N2G_ID 0x432c
103 #define BCM4322_D11N5G_ID 0x432d
104 #define BCM4329_D11N_ID 0x432e
105 #define BCM4329_D11N2G_ID 0x432f
106 #define BCM4329_D11N5G_ID 0x4330
107 #define BCM4315_D11DUAL_ID 0x4334
108 #define BCM4315_D11G_ID 0x4335
109 #define BCM4315_D11A_ID 0x4336
110 #define BCM4319_D11N_ID 0x4337
111 #define BCM4319_D11N2G_ID 0x4338
112 #define BCM4319_D11N5G_ID 0x4339
113 #define BCM43231_D11N2G_ID 0x4340
114 #define BCM43221_D11N2G_ID 0x4341
115 #define BCM43222_D11N_ID 0x4350
116 #define BCM43222_D11N2G_ID 0x4351
117 #define BCM43222_D11N5G_ID 0x4352
118 #define BCM43224_D11N_ID 0x4353
119 #define BCM43224_D11N_ID_VEN1 0x0576
120 #define BCM43226_D11N_ID 0x4354
121 #define BCM43236_D11N_ID 0x4346
122 #define BCM43236_D11N2G_ID 0x4347
123 #define BCM43236_D11N5G_ID 0x4348
124 #define BCM43225_D11N2G_ID 0x4357
125 #define BCM43421_D11N_ID 0xA99D
126 #define BCM4313_D11N2G_ID 0x4727
127 #define BCM4330_D11N_ID 0x4360
128 #define BCM4330_D11N2G_ID 0x4361
129 #define BCM4330_D11N5G_ID 0x4362
130 #define BCM4336_D11N_ID 0x4343
131 #define BCM6362_D11N_ID 0x435f
132 #define BCM4331_D11N_ID 0x4331
133 #define BCM4331_D11N2G_ID 0x4332
134 #define BCM4331_D11N5G_ID 0x4333
135 #define BCM43237_D11N_ID 0x4355
136 #define BCM43237_D11N5G_ID 0x4356
137 #define BCM43227_D11N2G_ID 0x4358
138 #define BCM43228_D11N_ID 0x4359
139 #define BCM43228_D11N5G_ID 0x435a
140 #define BCM43362_D11N_ID 0x4363
141 #define BCM43239_D11N_ID 0x4370
142 #define BCM4324_D11N_ID 0x4374
143 #define BCM43217_D11N2G_ID 0x43a9
144 #define BCM43131_D11N2G_ID 0x43aa
146 #define BCM4314_D11N2G_ID 0x4364
147 #define BCM43142_D11N2G_ID 0x4365
149 #define BCMGPRS_UART_ID 0x4333
150 #define BCMGPRS2_UART_ID 0x4344
151 #define FPGA_JTAGM_ID 0x43f0
152 #define BCM_JTAGM_ID 0x43f1
153 #define SDIOH_FPGA_ID 0x43f2
154 #define BCM_SDIOH_ID 0x43f3
155 #define SDIOD_FPGA_ID 0x43f4
156 #define SPIH_FPGA_ID 0x43f5
157 #define BCM_SPIH_ID 0x43f6
158 #define MIMO_FPGA_ID 0x43f8
159 #define BCM_JTAGM2_ID 0x43f9
160 #define SDHCI_FPGA_ID 0x43fa
161 #define BCM4402_ENET_ID 0x4402
162 #define BCM4402_V90_ID 0x4403
163 #define BCM4410_DEVICE_ID 0x4410
164 #define BCM4412_DEVICE_ID 0x4412
165 #define BCM4430_DEVICE_ID 0x4430
166 #define BCM4432_DEVICE_ID 0x4432
167 #define BCM4704_ENET_ID 0x4706
168 #define BCM4710_DEVICE_ID 0x4710
169 #define BCM47XX_AUDIO_ID 0x4711
170 #define BCM47XX_V90_ID 0x4712
171 #define BCM47XX_ENET_ID 0x4713
172 #define BCM47XX_EXT_ID 0x4714
173 #define BCM47XX_GMAC_ID 0x4715
174 #define BCM47XX_USBH_ID 0x4716
175 #define BCM47XX_USBD_ID 0x4717
176 #define BCM47XX_IPSEC_ID 0x4718
177 #define BCM47XX_ROBO_ID 0x4719
178 #define BCM47XX_USB20H_ID 0x471a
179 #define BCM47XX_USB20D_ID 0x471b
180 #define BCM47XX_ATA100_ID 0x471d
181 #define BCM47XX_SATAXOR_ID 0x471e
182 #define BCM47XX_GIGETH_ID 0x471f
183 #define BCM4712_MIPS_ID 0x4720
184 #define BCM4716_DEVICE_ID 0x4722
185 #define BCM47XX_SMBUS_EMU_ID 0x47fe
186 #define BCM47XX_XOR_EMU_ID 0x47ff
187 #define EPI41210_DEVICE_ID 0xa0fa
188 #define EPI41230_DEVICE_ID 0xa10e
189 #define JINVANI_SDIOH_ID 0x4743
190 #define BCM27XX_SDIOH_ID 0x2702
191 #define PCIXX21_FLASHMEDIA_ID 0x803b
192 #define PCIXX21_SDIOH_ID 0x803c
193 #define R5C822_SDIOH_ID 0x0822
194 #define JMICRON_SDIOH_ID 0x2381
197 #define BCM4306_CHIP_ID 0x4306
198 #define BCM4311_CHIP_ID 0x4311
199 #define BCM43111_CHIP_ID 43111
200 #define BCM43112_CHIP_ID 43112
201 #define BCM4312_CHIP_ID 0x4312
202 #define BCM4313_CHIP_ID 0x4313
203 #define BCM43131_CHIP_ID 43131
204 #define BCM4315_CHIP_ID 0x4315
205 #define BCM4318_CHIP_ID 0x4318
206 #define BCM4319_CHIP_ID 0x4319
207 #define BCM4320_CHIP_ID 0x4320
208 #define BCM4321_CHIP_ID 0x4321
209 #define BCM43217_CHIP_ID 43217
210 #define BCM4322_CHIP_ID 0x4322
211 #define BCM43221_CHIP_ID 43221
212 #define BCM43222_CHIP_ID 43222
213 #define BCM43224_CHIP_ID 43224
214 #define BCM43225_CHIP_ID 43225
215 #define BCM43227_CHIP_ID 43227
216 #define BCM43228_CHIP_ID 43228
217 #define BCM43226_CHIP_ID 43226
218 #define BCM43231_CHIP_ID 43231
219 #define BCM43234_CHIP_ID 43234
220 #define BCM43235_CHIP_ID 43235
221 #define BCM43236_CHIP_ID 43236
222 #define BCM43237_CHIP_ID 43237
223 #define BCM43238_CHIP_ID 43238
224 #define BCM43239_CHIP_ID 43239
225 #define BCM43420_CHIP_ID 43420
226 #define BCM43421_CHIP_ID 43421
227 #define BCM43428_CHIP_ID 43428
228 #define BCM43431_CHIP_ID 43431
229 #define BCM4325_CHIP_ID 0x4325
230 #define BCM4328_CHIP_ID 0x4328
231 #define BCM4329_CHIP_ID 0x4329
232 #define BCM4331_CHIP_ID 0x4331
233 #define BCM4336_CHIP_ID 0x4336
234 #define BCM43362_CHIP_ID 43362
235 #define BCM4330_CHIP_ID 0x4330
236 #define BCM6362_CHIP_ID 0x6362
237 #define BCM4314_CHIP_ID 0x4314
238 #define BCM43142_CHIP_ID 43142
239 #define BCM4324_CHIP_ID 0x4324
241 #define BCM4342_CHIP_ID 4342
242 #define BCM4402_CHIP_ID 0x4402
243 #define BCM4704_CHIP_ID 0x4704
244 #define BCM4710_CHIP_ID 0x4710
245 #define BCM4712_CHIP_ID 0x4712
246 #define BCM4716_CHIP_ID 0x4716
247 #define BCM47162_CHIP_ID 47162
248 #define BCM4748_CHIP_ID 0x4748
249 #define BCM4749_CHIP_ID 0x4749
250 #define BCM4785_CHIP_ID 0x4785
251 #define BCM5350_CHIP_ID 0x5350
252 #define BCM5352_CHIP_ID 0x5352
253 #define BCM5354_CHIP_ID 0x5354
254 #define BCM5365_CHIP_ID 0x5365
255 #define BCM5356_CHIP_ID 0x5356
256 #define BCM5357_CHIP_ID 0x5357
257 #define BCM53572_CHIP_ID 53572
260 #define BCM4303_PKG_ID 2
261 #define BCM4309_PKG_ID 1
262 #define BCM4712LARGE_PKG_ID 0
263 #define BCM4712SMALL_PKG_ID 1
264 #define BCM4712MID_PKG_ID 2
265 #define BCM4328USBD11G_PKG_ID 2
266 #define BCM4328USBDUAL_PKG_ID 3
267 #define BCM4328SDIOD11G_PKG_ID 4
268 #define BCM4328SDIODUAL_PKG_ID 5
269 #define BCM4329_289PIN_PKG_ID 0
270 #define BCM4329_182PIN_PKG_ID 1
271 #define BCM5354E_PKG_ID 1
272 #define BCM4716_PKG_ID 8
273 #define BCM4717_PKG_ID 9
274 #define BCM4718_PKG_ID 10
275 #define BCM5356_PKG_NONMODE 1
276 #define BCM5358U_PKG_ID 8
277 #define BCM5358_PKG_ID 9
278 #define BCM47186_PKG_ID 10
279 #define BCM5357_PKG_ID 11
280 #define BCM5356U_PKG_ID 12
281 #define BCM53572_PKG_ID 8
282 #define BCM47188_PKG_ID 9
283 #define BCM4331TT_PKG_ID 8
284 #define BCM4331TN_PKG_ID 9
285 #define BCM4331TNA0_PKG_ID 0xb
288 #define HDLSIM5350_PKG_ID 1
289 #define HDLSIM_PKG_ID 14
290 #define HWSIM_PKG_ID 15
291 #define BCM43224_FAB_CSM 0x8
292 #define BCM43224_FAB_SMIC 0xa
293 #define BCM4336_WLBGA_PKG_ID 0x8
294 #define BCM4330_WLBGA_PKG_ID 0x0
295 #define BCM4314PCIE_ARM_PKG_ID (8 | 0)
296 #define BCM4314SDIO_PKG_ID (8 | 1)
297 #define BCM4314PCIE_PKG_ID (8 | 2)
298 #define BCM4314SDIO_ARM_PKG_ID (8 | 3)
299 #define BCM4314SDIO_FPBGA_PKG_ID (8 | 4)
300 #define BCM4314DEV_PKG_ID (8 | 6)
302 #define PCIXX21_FLASHMEDIA0_ID 0x8033
303 #define PCIXX21_SDIOH0_ID 0x8034
306 #define BFL_BTC2WIRE 0x00000001
307 #define BFL_BTCOEX 0x00000001
308 #define BFL_PACTRL 0x00000002
309 #define BFL_AIRLINEMODE 0x00000004
310 #define BFL_ADCDIV 0x00000008
311 #define BFL_ENETROBO 0x00000010
312 #define BFL_NOPLLDOWN 0x00000020
313 #define BFL_CCKHIPWR 0x00000040
314 #define BFL_ENETADM 0x00000080
315 #define BFL_ENETVLAN 0x00000100
317 #define BFL_AFTERBURNER 0x00000200
319 #define BFL_NOPCI 0x00000400
320 #define BFL_FEM 0x00000800
321 #define BFL_EXTLNA 0x00001000
322 #define BFL_HGPA 0x00002000
323 #define BFL_BTC2WIRE_ALTGPIO 0x00004000
324 #define BFL_ALTIQ 0x00008000
325 #define BFL_NOPA 0x00010000
326 #define BFL_RSSIINV 0x00020000
327 #define BFL_PAREF 0x00040000
328 #define BFL_3TSWITCH 0x00080000
329 #define BFL_PHASESHIFT 0x00100000
330 #define BFL_BUCKBOOST 0x00200000
331 #define BFL_FEM_BT 0x00400000
332 #define BFL_NOCBUCK 0x00800000
333 #define BFL_CCKFAVOREVM 0x01000000
334 #define BFL_PALDO 0x02000000
335 #define BFL_LNLDO2_2P5 0x04000000
336 #define BFL_FASTPWR 0x08000000
337 #define BFL_UCPWRCTL_MININDX 0x08000000
338 #define BFL_EXTLNA_5GHz 0x10000000
339 #define BFL_TRSW_1by2 0x20000000
340 #define BFL_LO_TRSW_R_5GHz 0x40000000
341 #define BFL_ELNA_GAINDEF 0x80000000
342 #define BFL_EXTLNA_TX 0x20000000
345 #define BFL2_RXBB_INT_REG_DIS 0x00000001
346 #define BFL2_APLL_WAR 0x00000002
347 #define BFL2_TXPWRCTRL_EN 0x00000004
348 #define BFL2_2X4_DIV 0x00000008
349 #define BFL2_5G_PWRGAIN 0x00000010
350 #define BFL2_PCIEWAR_OVR 0x00000020
351 #define BFL2_CAESERS_BRD 0x00000040
352 #define BFL2_BTC3WIRE 0x00000080
353 #define BFL2_BTCLEGACY 0x00000080
354 #define BFL2_SKWRKFEM_BRD 0x00000100
355 #define BFL2_SPUR_WAR 0x00000200
356 #define BFL2_GPLL_WAR 0x00000400
357 #define BFL2_TRISTATE_LED 0x00000800
358 #define BFL2_SINGLEANT_CCK 0x00001000
359 #define BFL2_2G_SPUR_WAR 0x00002000
360 #define BFL2_BPHY_ALL_TXCORES 0x00004000
361 #define BFL2_FCC_BANDEDGE_WAR 0x00008000
362 #define BFL2_GPLL_WAR2 0x00010000
363 #define BFL2_IPALVLSHIFT_3P3 0x00020000
364 #define BFL2_INTERNDET_TXIQCAL 0x00040000
365 #define BFL2_XTALBUFOUTEN 0x00080000
366 #define BFL2_ANAPACTRL_2G 0x00100000
367 #define BFL2_ANAPACTRL_5G 0x00200000
368 #define BFL2_ELNACTRL_TRSW_2G 0x00400000
369 #define BFL2_BT_SHARE_ANT0 0x00800000
370 #define BFL2_TEMPSENSE_HIGHER 0x01000000
371 #define BFL2_BTC3WIREONLY 0x02000000
372 #define BFL2_PWR_NOMINAL 0x04000000
373 #define BFL2_EXTLNA_TX 0x08000000
375 #define BFL2_4313_RADIOREG 0x10000000
376 #define BFL2_SECI_LOPWR_DIS 0x20000000
380 #define BOARD_GPIO_BTC3W_IN 0x850
381 #define BOARD_GPIO_BTC3W_OUT 0x020
382 #define BOARD_GPIO_BTCMOD_IN 0x010
383 #define BOARD_GPIO_BTCMOD_OUT 0x020
384 #define BOARD_GPIO_BTC_IN 0x080
385 #define BOARD_GPIO_BTC_OUT 0x100
386 #define BOARD_GPIO_PACTRL 0x200
387 #define BOARD_GPIO_12 0x1000
388 #define BOARD_GPIO_13 0x2000
389 #define BOARD_GPIO_BTC4_IN 0x0800
390 #define BOARD_GPIO_BTC4_BT 0x2000
391 #define BOARD_GPIO_BTC4_STAT 0x4000
392 #define BOARD_GPIO_BTC4_WLAN 0x8000
393 #define BOARD_GPIO_1_WLAN_PWR 0x2
394 #define BOARD_GPIO_4_WLAN_PWR 0x10
396 #define GPIO_BTC4W_OUT_4312 0x010
397 #define GPIO_BTC4W_OUT_43224 0x020
398 #define GPIO_BTC4W_OUT_43224_SHARED 0x0e0
399 #define GPIO_BTC4W_OUT_43225 0x0e0
400 #define GPIO_BTC4W_OUT_43421 0x020
401 #define GPIO_BTC4W_OUT_4313 0x060
403 #define PCI_CFG_GPIO_SCS 0x10
404 #define PCI_CFG_GPIO_HWRAD 0x20
405 #define PCI_CFG_GPIO_XTAL 0x40
406 #define PCI_CFG_GPIO_PLL 0x80
409 #define PLL_DELAY 150
410 #define FREF_DELAY 200
411 #define MIN_SLOW_CLK 32
412 #define XTAL_ON_DELAY 1000
415 #define BU4710_BOARD 0x0400
416 #define VSIM4710_BOARD 0x0401
417 #define QT4710_BOARD 0x0402
419 #define BU4309_BOARD 0x040a
420 #define BCM94309CB_BOARD 0x040b
421 #define BCM94309MP_BOARD 0x040c
422 #define BCM4309AP_BOARD 0x040d
424 #define BCM94302MP_BOARD 0x040e
426 #define BU4306_BOARD 0x0416
427 #define BCM94306CB_BOARD 0x0417
428 #define BCM94306MP_BOARD 0x0418
430 #define BCM94710D_BOARD 0x041a
431 #define BCM94710R1_BOARD 0x041b
432 #define BCM94710R4_BOARD 0x041c
433 #define BCM94710AP_BOARD 0x041d
435 #define BU2050_BOARD 0x041f
437 #define BCM94306P50_BOARD 0x0420
439 #define BCM94309G_BOARD 0x0421
441 #define BU4704_BOARD 0x0423
442 #define BU4702_BOARD 0x0424
444 #define BCM94306PC_BOARD 0x0425
446 #define MPSG4306_BOARD 0x0427
448 #define BCM94702MN_BOARD 0x0428
451 #define BCM94702CPCI_BOARD 0x0429
454 #define BCM95380RR_BOARD 0x042a
457 #define BCM94306CBSG_BOARD 0x042b
460 #define PCSG94306_BOARD 0x042d
463 #define BU4704SD_BOARD 0x042e
466 #define BCM94704AGR_BOARD 0x042f
469 #define BCM94308MP_BOARD 0x0430
472 #define BCM94306GPRS_BOARD 0x0432
475 #define BU5365_FPGA_BOARD 0x0433
477 #define BU4712_BOARD 0x0444
478 #define BU4712SD_BOARD 0x045d
479 #define BU4712L_BOARD 0x045f
482 #define BCM94712AP_BOARD 0x0445
483 #define BCM94712P_BOARD 0x0446
486 #define BU4318_BOARD 0x0447
487 #define CB4318_BOARD 0x0448
488 #define MPG4318_BOARD 0x0449
489 #define MP4318_BOARD 0x044a
490 #define SD4318_BOARD 0x044b
493 #define BCM94313BU_BOARD 0x050f
494 #define BCM94313HM_BOARD 0x0510
495 #define BCM94313EPA_BOARD 0x0511
496 #define BCM94313HMG_BOARD 0x051C
499 #define BCM96338_BOARD 0x6338
500 #define BCM96348_BOARD 0x6348
501 #define BCM96358_BOARD 0x6358
502 #define BCM96368_BOARD 0x6368
505 #define BCM94306P_BOARD 0x044c
508 #define BCM94303MP_BOARD 0x044e
511 #define BCM94306MPSGH_BOARD 0x044f
514 #define BCM94306MPM 0x0450
515 #define BCM94306MPL 0x0453
518 #define BCM94712AGR_BOARD 0x0451
521 #define PC4303_BOARD 0x0454
524 #define BCM95350K_BOARD 0x0455
527 #define BCM95350R_BOARD 0x0456
530 #define BCM94306MPLNA_BOARD 0x0457
533 #define BU4320_BOARD 0x0458
534 #define BU4320S_BOARD 0x0459
535 #define BCM94320PH_BOARD 0x045a
538 #define BCM94306MPH_BOARD 0x045b
541 #define BCM94306PCIV_BOARD 0x045c
543 #define BU4712SD_BOARD 0x045d
545 #define BCM94320PFLSH_BOARD 0x045e
547 #define BU4712L_BOARD 0x045f
548 #define BCM94712LGR_BOARD 0x0460
549 #define BCM94320R_BOARD 0x0461
551 #define BU5352_BOARD 0x0462
553 #define BCM94318MPGH_BOARD 0x0463
555 #define BU4311_BOARD 0x0464
556 #define BCM94311MC_BOARD 0x0465
557 #define BCM94311MCAG_BOARD 0x0466
559 #define BCM95352GR_BOARD 0x0467
562 #define BCM95351AGR_BOARD 0x0470
565 #define BCM94704MPCB_BOARD 0x0472
568 #define BU4785_BOARD 0x0478
571 #define BU4321_BOARD 0x046b
572 #define BU4321E_BOARD 0x047c
573 #define MP4321_BOARD 0x046c
574 #define CB2_4321_BOARD 0x046d
575 #define CB2_4321_AG_BOARD 0x0066
576 #define MC4321_BOARD 0x046e
579 #define BU4328_BOARD 0x0481
580 #define BCM4328SDG_BOARD 0x0482
581 #define BCM4328SDAG_BOARD 0x0483
582 #define BCM4328UG_BOARD 0x0484
583 #define BCM4328UAG_BOARD 0x0485
584 #define BCM4328PC_BOARD 0x0486
585 #define BCM4328CF_BOARD 0x0487
588 #define BCM94325DEVBU_BOARD 0x0490
589 #define BCM94325BGABU_BOARD 0x0491
591 #define BCM94325SDGWB_BOARD 0x0492
593 #define BCM94325SDGMDL_BOARD 0x04aa
594 #define BCM94325SDGMDL2_BOARD 0x04c6
595 #define BCM94325SDGMDL3_BOARD 0x04c9
597 #define BCM94325SDABGWBA_BOARD 0x04e1
600 #define BCM94322MC_SSID 0x04a4
601 #define BCM94322USB_SSID 0x04a8
602 #define BCM94322HM_SSID 0x04b0
603 #define BCM94322USB2D_SSID 0x04bf
606 #define BCM4312MCGSG_BOARD 0x04b5
609 #define BCM94315DEVBU_SSID 0x04c2
610 #define BCM94315USBGP_SSID 0x04c7
611 #define BCM94315BGABU_SSID 0x04ca
612 #define BCM94315USBGP41_SSID 0x04cb
615 #define BCM94319DEVBU_SSID 0X04e5
616 #define BCM94319USB_SSID 0X04e6
617 #define BCM94319SD_SSID 0X04e7
620 #define BCM94716NR2_SSID 0x04cd
623 #define BCM94319DEVBU_SSID 0X04e5
624 #define BCM94319USBNP4L_SSID 0X04e6
625 #define BCM94319WLUSBN4L_SSID 0X04e7
626 #define BCM94319SDG_SSID 0X04ea
627 #define BCM94319LCUSBSDN4L_SSID 0X04eb
628 #define BCM94319USBB_SSID 0x04ee
629 #define BCM94319LCSDN4L_SSID 0X0507
630 #define BCM94319LSUSBN4L_SSID 0X0508
631 #define BCM94319SDNA4L_SSID 0X0517
632 #define BCM94319SDELNA4L_SSID 0X0518
633 #define BCM94319SDELNA6L_SSID 0X0539
634 #define BCM94319ARCADYAN_SSID 0X0546
635 #define BCM94319WINDSOR_SSID 0x0561
636 #define BCM94319MLAP_SSID 0x0562
637 #define BCM94319SDNA_SSID 0x058b
638 #define BCM94319BHEMU3_SSID 0x0563
639 #define BCM94319SDHMB_SSID 0x058c
640 #define BCM94319SDBREF_SSID 0x05a1
641 #define BCM94319USBSDB_SSID 0x05a2
645 #define BCM94329AGB_SSID 0X04b9
646 #define BCM94329TDKMDL1_SSID 0X04ba
647 #define BCM94329TDKMDL11_SSID 0X04fc
648 #define BCM94329OLYMPICN18_SSID 0X04fd
649 #define BCM94329OLYMPICN90_SSID 0X04fe
650 #define BCM94329OLYMPICN90U_SSID 0X050c
651 #define BCM94329OLYMPICN90M_SSID 0X050b
652 #define BCM94329AGBF_SSID 0X04ff
653 #define BCM94329OLYMPICX17_SSID 0X0504
654 #define BCM94329OLYMPICX17M_SSID 0X050a
655 #define BCM94329OLYMPICX17U_SSID 0X0509
656 #define BCM94329OLYMPICUNO_SSID 0X0564
657 #define BCM94329MOTOROLA_SSID 0X0565
658 #define BCM94329OLYMPICLOCO_SSID 0X0568
660 #define BCM94336SD_WLBGABU_SSID 0x0511
661 #define BCM94336SD_WLBGAREF_SSID 0x0519
662 #define BCM94336SDGP_SSID 0x0538
663 #define BCM94336SDG_SSID 0x0519
664 #define BCM94336SDGN_SSID 0x0538
665 #define BCM94336SDGFC_SSID 0x056B
668 #define BCM94330SDG_SSID 0x0528
669 #define BCM94330SD_FCBGABU_SSID 0x052e
670 #define BCM94330SD_WLBGABU_SSID 0x052f
671 #define BCM94330SD_FCBGA_SSID 0x0530
672 #define BCM94330FCSDAGB_SSID 0x0532
673 #define BCM94330OLYMPICAMG_SSID 0x0549
674 #define BCM94330OLYMPICAMGEPA_SSID 0x054F
675 #define BCM94330OLYMPICUNO3_SSID 0x0551
676 #define BCM94330WLSDAGB_SSID 0x0547
677 #define BCM94330CSPSDAGBB_SSID 0x054A
680 #define BCM943224X21 0x056e
681 #define BCM943224X21_FCC 0x00d1
684 #define BCM943228BU8_SSID 0x0540
685 #define BCM943228BU9_SSID 0x0541
686 #define BCM943228BU_SSID 0x0542
687 #define BCM943227HM4L_SSID 0x0543
688 #define BCM943227HMB_SSID 0x0544
689 #define BCM943228HM4L_SSID 0x0545
690 #define BCM943228SD_SSID 0x0573
693 #define BCM943239MOD_SSID 0x05ac
694 #define BCM943239REF_SSID 0x05aa
697 #define BCM94331X19 0x00D6
698 #define BCM94331PCIEBT3Ax_SSID 0x00E4
699 #define BCM94331X12_2G_SSID 0x00EC
700 #define BCM94331X12_5G_SSID 0x00ED
701 #define BCM94331X29B 0x00EF
702 #define BCM94331BU_SSID 0x0523
703 #define BCM94331S9BU_SSID 0x0524
704 #define BCM94331MC_SSID 0x0525
705 #define BCM94331MCI_SSID 0x0526
706 #define BCM94331PCIEBT4_SSID 0x0527
707 #define BCM94331HM_SSID 0x0574
708 #define BCM94331PCIEDUAL_SSID 0x059B
709 #define BCM94331MCH5_SSID 0x05A9
710 #define BCM94331PCIEDUALV2_SSID 0x05B7
711 #define BCM94331CS_SSID 0x05C6
712 #define BCM94331CSAX_SSID 0x00EF
715 #define BCM953572BU_SSID 0x058D
716 #define BCM953572NR2_SSID 0x058E
717 #define BCM947188NR2_SSID 0x058F
718 #define BCM953572SDRNR2_SSID 0x0590
721 #define BCM943236OLYMPICSULLEY_SSID 0x594
722 #define BCM943236PREPROTOBLU2O3_SSID 0x5b9
723 #define BCM943236USBELNA_SSID 0x5f8
726 #define GPIO_NUMPINS 32
729 #define RDL_RAM_BASE_4319 0x60000000
730 #define RDL_RAM_BASE_4329 0x60000000
731 #define RDL_RAM_SIZE_4319 0x48000
732 #define RDL_RAM_SIZE_4329 0x48000
733 #define RDL_RAM_SIZE_43236 0x70000
734 #define RDL_RAM_BASE_43236 0x60000000
735 #define RDL_RAM_SIZE_4328 0x60000
736 #define RDL_RAM_BASE_4328 0x80000000
737 #define RDL_RAM_SIZE_4322 0x60000
738 #define RDL_RAM_BASE_4322 0x60000000
741 #define MUXENAB_UART 0x00000001
742 #define MUXENAB_GPIO 0x00000002
743 #define MUXENAB_ERCX 0x00000004
744 #define MUXENAB_JTAG 0x00000008
745 #define MUXENAB_HOST_WAKE 0x00000010