2 * SPI device spec header file
4 * Copyright (C) 2010, Broadcom Corporation
7 * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
8 * the contents of this file may not be disclosed to third parties, copied
9 * or duplicated in any form, in whole or in part, without the prior
10 * written permission of Broadcom Corporation.
12 * $Id: spid.h,v 1.7.10.1.16.3 2009/04/09 19:23:14 Exp $
19 * Brcm SPI Device Register Map.
23 typedef volatile struct {
24 uint8 config; /* 0x00, len, endian, clock, speed, polarity, wakeup */
25 uint8 response_delay; /* 0x01, read response delay in bytes (corerev < 3) */
26 uint8 status_enable; /* 0x02, status-enable, intr with status, response_delay
27 * function selection, command/data error check
29 uint8 reset_bp; /* 0x03, reset on wlan/bt backplane reset (corerev >= 1) */
30 uint16 intr_reg; /* 0x04, Intr status register */
31 uint16 intr_en_reg; /* 0x06, Intr mask register */
32 uint32 status_reg; /* 0x08, RO, Status bits of last spi transfer */
33 uint16 f1_info_reg; /* 0x0c, RO, enabled, ready for data transfer, blocksize */
34 uint16 f2_info_reg; /* 0x0e, RO, enabled, ready for data transfer, blocksize */
35 uint16 f3_info_reg; /* 0x10, RO, enabled, ready for data transfer, blocksize */
36 uint32 test_read; /* 0x14, RO 0xfeedbead signature */
37 uint32 test_rw; /* 0x18, RW */
38 uint8 resp_delay_f0; /* 0x1c, read resp delay bytes for F0 (corerev >= 3) */
39 uint8 resp_delay_f1; /* 0x1d, read resp delay bytes for F1 (corerev >= 3) */
40 uint8 resp_delay_f2; /* 0x1e, read resp delay bytes for F2 (corerev >= 3) */
41 uint8 resp_delay_f3; /* 0x1f, read resp delay bytes for F3 (corerev >= 3) */
44 /* SPI device register offsets */
45 #define SPID_CONFIG 0x00
46 #define SPID_RESPONSE_DELAY 0x01
47 #define SPID_STATUS_ENABLE 0x02
48 #define SPID_RESET_BP 0x03 /* (corerev >= 1) */
49 #define SPID_INTR_REG 0x04 /* 16 bits - Interrupt status */
50 #define SPID_INTR_EN_REG 0x06 /* 16 bits - Interrupt mask */
51 #define SPID_STATUS_REG 0x08 /* 32 bits */
52 #define SPID_F1_INFO_REG 0x0C /* 16 bits */
53 #define SPID_F2_INFO_REG 0x0E /* 16 bits */
54 #define SPID_F3_INFO_REG 0x10 /* 16 bits */
55 #define SPID_TEST_READ 0x14 /* 32 bits */
56 #define SPID_TEST_RW 0x18 /* 32 bits */
57 #define SPID_RESP_DELAY_F0 0x1c /* 8 bits (corerev >= 3) */
58 #define SPID_RESP_DELAY_F1 0x1d /* 8 bits (corerev >= 3) */
59 #define SPID_RESP_DELAY_F2 0x1e /* 8 bits (corerev >= 3) */
60 #define SPID_RESP_DELAY_F3 0x1f /* 8 bits (corerev >= 3) */
62 /* Bit masks for SPID_CONFIG device register */
63 #define WORD_LENGTH_32 0x1 /* 0/1 16/32 bit word length */
64 #define ENDIAN_BIG 0x2 /* 0/1 Little/Big Endian */
65 #define CLOCK_PHASE 0x4 /* 0/1 clock phase delay */
66 #define CLOCK_POLARITY 0x8 /* 0/1 Idle state clock polarity is low/high */
67 #define HIGH_SPEED_MODE 0x10 /* 1/0 High Speed mode / Normal mode */
68 #define INTR_POLARITY 0x20 /* 1/0 Interrupt active polarity is high/low */
69 #define WAKE_UP 0x80 /* 0/1 Wake-up command from Host to WLAN */
71 /* Bit mask for SPID_RESPONSE_DELAY device register */
72 #define RESPONSE_DELAY_MASK 0xFF /* Configurable rd response delay in multiples of 8 bits */
74 /* Bit mask for SPID_STATUS_ENABLE device register */
75 #define STATUS_ENABLE 0x1 /* 1/0 Status sent/not sent to host after read/write */
76 #define INTR_WITH_STATUS 0x2 /* 0/1 Do-not / do-interrupt if status is sent */
77 #define RESP_DELAY_ALL 0x4 /* Applicability of resp delay to F1 or all func's read */
78 #define DWORD_PKT_LEN_EN 0x8 /* Packet len denoted in dwords instead of bytes */
79 #define CMD_ERR_CHK_EN 0x20 /* Command error check enable */
80 #define DATA_ERR_CHK_EN 0x40 /* Data error check enable */
82 /* Bit mask for SPID_RESET_BP device register */
83 #define RESET_ON_WLAN_BP_RESET 0x4 /* enable reset for WLAN backplane */
84 #define RESET_ON_BT_BP_RESET 0x8 /* enable reset for BT backplane */
85 #define RESET_SPI 0x80 /* reset the above enabled logic */
87 /* Bit mask for SPID_INTR_REG device register */
88 #define DATA_UNAVAILABLE 0x0001 /* Requested data not available; Clear by writing a "1" */
89 #define F2_F3_FIFO_RD_UNDERFLOW 0x0002
90 #define F2_F3_FIFO_WR_OVERFLOW 0x0004
91 #define COMMAND_ERROR 0x0008 /* Cleared by writing 1 */
92 #define DATA_ERROR 0x0010 /* Cleared by writing 1 */
93 #define F2_PACKET_AVAILABLE 0x0020
94 #define F3_PACKET_AVAILABLE 0x0040
95 #define F1_OVERFLOW 0x0080 /* Due to last write. Bkplane has pending write requests */
96 #define MISC_INTR0 0x0100
97 #define MISC_INTR1 0x0200
98 #define MISC_INTR2 0x0400
99 #define MISC_INTR3 0x0800
100 #define MISC_INTR4 0x1000
101 #define F1_INTR 0x2000
102 #define F2_INTR 0x4000
103 #define F3_INTR 0x8000
105 /* Bit mask for 32bit SPID_STATUS_REG device register */
106 #define STATUS_DATA_NOT_AVAILABLE 0x00000001
107 #define STATUS_UNDERFLOW 0x00000002
108 #define STATUS_OVERFLOW 0x00000004
109 #define STATUS_F2_INTR 0x00000008
110 #define STATUS_F3_INTR 0x00000010
111 #define STATUS_F2_RX_READY 0x00000020
112 #define STATUS_F3_RX_READY 0x00000040
113 #define STATUS_HOST_CMD_DATA_ERR 0x00000080
114 #define STATUS_F2_PKT_AVAILABLE 0x00000100
115 #define STATUS_F2_PKT_LEN_MASK 0x000FFE00
116 #define STATUS_F2_PKT_LEN_SHIFT 9
117 #define STATUS_F3_PKT_AVAILABLE 0x00100000
118 #define STATUS_F3_PKT_LEN_MASK 0xFFE00000
119 #define STATUS_F3_PKT_LEN_SHIFT 21
121 /* Bit mask for 16 bits SPID_F1_INFO_REG device register */
122 #define F1_ENABLED 0x0001
123 #define F1_RDY_FOR_DATA_TRANSFER 0x0002
124 #define F1_MAX_PKT_SIZE 0x01FC
126 /* Bit mask for 16 bits SPID_F2_INFO_REG device register */
127 #define F2_ENABLED 0x0001
128 #define F2_RDY_FOR_DATA_TRANSFER 0x0002
129 #define F2_MAX_PKT_SIZE 0x3FFC
131 /* Bit mask for 16 bits SPID_F3_INFO_REG device register */
132 #define F3_ENABLED 0x0001
133 #define F3_RDY_FOR_DATA_TRANSFER 0x0002
134 #define F3_MAX_PKT_SIZE 0x3FFC
136 /* Bit mask for 32 bits SPID_TEST_READ device register read in 16bit LE mode */
137 #define TEST_RO_DATA_32BIT_LE 0xFEEDBEAD
139 /* Maximum number of I/O funcs */
140 #define SPI_MAX_IOFUNCS 4
142 #define SPI_MAX_PKT_LEN (2048*4)
150 #define WAIT_F2RXFIFORDY 100
151 #define WAIT_F2RXFIFORDY_DELAY 20