2 * SDIO spec header file
3 * Protocol and standard (common) device definitions
5 * Copyright (C) 1999-2010, Broadcom Corporation
7 * Unless you and Broadcom execute a separate written software license
8 * agreement governing use of this software, this software is licensed to you
9 * under the terms of the GNU General Public License version 2 (the "GPL"),
10 * available at http://www.broadcom.com/licenses/GPLv2.php, with the
11 * following added to such license:
13 * As a special exception, the copyright holders of this software give you
14 * permission to link this software with independent modules, and to copy and
15 * distribute the resulting executable under terms of your choice, provided that
16 * you also meet, for each linked independent module, the terms and conditions of
17 * the license of that module. An independent module is a module which is not
18 * derived from this software. The special exception does not apply to any
19 * modifications of the software.
21 * Notwithstanding the above, under no circumstances may you combine this
22 * software in any way with any other Broadcom software provided under a license
23 * other than the GPL, without Broadcom's express prior written consent.
25 * $Id: sdio.h,v 13.24.4.1.4.1.16.1 2009/08/12 01:08:02 Exp $
32 /* CCCR structure for function 0 */
33 typedef volatile struct {
34 uint8 cccr_sdio_rev; /* RO, cccr and sdio revision */
35 uint8 sd_rev; /* RO, sd spec revision */
36 uint8 io_en; /* I/O enable */
37 uint8 io_rdy; /* I/O ready reg */
38 uint8 intr_ctl; /* Master and per function interrupt enable control */
39 uint8 intr_status; /* RO, interrupt pending status */
40 uint8 io_abort; /* read/write abort or reset all functions */
41 uint8 bus_inter; /* bus interface control */
42 uint8 capability; /* RO, card capability */
44 uint8 cis_base_low; /* 0x9 RO, common CIS base address, LSB */
46 uint8 cis_base_high; /* 0xB RO, common CIS base address, MSB */
48 /* suspend/resume registers */
49 uint8 bus_suspend; /* 0xC */
50 uint8 func_select; /* 0xD */
51 uint8 exec_flag; /* 0xE */
52 uint8 ready_flag; /* 0xF */
54 uint8 fn0_blk_size[2]; /* 0x10(LSB), 0x11(MSB) */
56 uint8 power_control; /* 0x12 (SDIO version 1.10) */
58 uint8 speed_control; /* 0x13 */
61 /* SDIO Device CCCR offsets */
62 #define SDIOD_CCCR_REV 0x00
63 #define SDIOD_CCCR_SDREV 0x01
64 #define SDIOD_CCCR_IOEN 0x02
65 #define SDIOD_CCCR_IORDY 0x03
66 #define SDIOD_CCCR_INTEN 0x04
67 #define SDIOD_CCCR_INTPEND 0x05
68 #define SDIOD_CCCR_IOABORT 0x06
69 #define SDIOD_CCCR_BICTRL 0x07
70 #define SDIOD_CCCR_CAPABLITIES 0x08
71 #define SDIOD_CCCR_CISPTR_0 0x09
72 #define SDIOD_CCCR_CISPTR_1 0x0A
73 #define SDIOD_CCCR_CISPTR_2 0x0B
74 #define SDIOD_CCCR_BUSSUSP 0x0C
75 #define SDIOD_CCCR_FUNCSEL 0x0D
76 #define SDIOD_CCCR_EXECFLAGS 0x0E
77 #define SDIOD_CCCR_RDYFLAGS 0x0F
78 #define SDIOD_CCCR_BLKSIZE_0 0x10
79 #define SDIOD_CCCR_BLKSIZE_1 0x11
80 #define SDIOD_CCCR_POWER_CONTROL 0x12
81 #define SDIOD_CCCR_SPEED_CONTROL 0x13
83 /* Broadcom extensions (corerev >= 1) */
84 #define SDIOD_CCCR_BRCM_SEPINT 0xf2
87 #define SDIO_REV_SDIOID_MASK 0xf0 /* SDIO spec revision number */
88 #define SDIO_REV_CCCRID_MASK 0x0f /* CCCR format version number */
91 #define SD_REV_PHY_MASK 0x0f /* SD format version number */
94 #define SDIO_FUNC_ENABLE_1 0x02 /* function 1 I/O enable */
95 #define SDIO_FUNC_ENABLE_2 0x04 /* function 2 I/O enable */
98 #define SDIO_FUNC_READY_1 0x02 /* function 1 I/O ready */
99 #define SDIO_FUNC_READY_2 0x04 /* function 2 I/O ready */
102 #define INTR_CTL_MASTER_EN 0x1 /* interrupt enable master */
103 #define INTR_CTL_FUNC1_EN 0x2 /* interrupt enable for function 1 */
104 #define INTR_CTL_FUNC2_EN 0x4 /* interrupt enable for function 2 */
107 #define INTR_STATUS_FUNC1 0x2 /* interrupt pending for function 1 */
108 #define INTR_STATUS_FUNC2 0x4 /* interrupt pending for function 2 */
111 #define IO_ABORT_RESET_ALL 0x08 /* I/O card reset */
112 #define IO_ABORT_FUNC_MASK 0x07 /* abort selction: function x */
115 #define BUS_CARD_DETECT_DIS 0x80 /* Card Detect disable */
116 #define BUS_SPI_CONT_INTR_CAP 0x40 /* support continuous SPI interrupt */
117 #define BUS_SPI_CONT_INTR_EN 0x20 /* continuous SPI interrupt enable */
118 #define BUS_SD_DATA_WIDTH_MASK 0x03 /* bus width mask */
119 #define BUS_SD_DATA_WIDTH_4BIT 0x02 /* bus width 4-bit mode */
120 #define BUS_SD_DATA_WIDTH_1BIT 0x00 /* bus width 1-bit mode */
123 #define SDIO_CAP_4BLS 0x80 /* 4-bit support for low speed card */
124 #define SDIO_CAP_LSC 0x40 /* low speed card */
125 #define SDIO_CAP_E4MI 0x20 /* enable interrupt between block of data in 4-bit mode */
126 #define SDIO_CAP_S4MI 0x10 /* support interrupt between block of data in 4-bit mode */
127 #define SDIO_CAP_SBS 0x08 /* support suspend/resume */
128 #define SDIO_CAP_SRW 0x04 /* support read wait */
129 #define SDIO_CAP_SMB 0x02 /* support multi-block transfer */
130 #define SDIO_CAP_SDC 0x01 /* Support Direct commands during multi-byte transfer */
133 #define SDIO_POWER_SMPC 0x01 /* supports master power control (RO) */
134 #define SDIO_POWER_EMPC 0x02 /* enable master power control (allow > 200mA) (RW) */
136 /* speed_control (control device entry into high-speed clocking mode) */
137 #define SDIO_SPEED_SHS 0x01 /* supports high-speed [clocking] mode (RO) */
138 #define SDIO_SPEED_EHS 0x02 /* enable high-speed [clocking] mode (RW) */
141 #define SDIO_SEPINT_MASK 0x01 /* route sdpcmdev intr onto separate pad (chip-specific) */
142 #define SDIO_SEPINT_OE 0x02 /* 1 asserts output enable for above pad */
143 #define SDIO_SEPINT_ACT_HI 0x04 /* use active high interrupt level instead of active low */
145 /* FBR structure for function 1-7, FBR addresses and register offsets */
146 typedef volatile struct {
147 uint8 devctr; /* device interface, CSA control */
148 uint8 ext_dev; /* extended standard I/O device type code */
149 uint8 pwr_sel; /* power selection support */
150 uint8 PAD[6]; /* reserved */
152 uint8 cis_low; /* CIS LSB */
154 uint8 cis_high; /* CIS MSB */
155 uint8 csa_low; /* code storage area, LSB */
157 uint8 csa_high; /* code storage area, MSB */
158 uint8 csa_dat_win; /* data access window to function */
160 uint8 fnx_blk_size[2]; /* block size, little endian */
163 /* Maximum number of I/O funcs */
164 #define SDIOD_MAX_IOFUNCS 7
166 /* SDIO Device FBR Start Address */
167 #define SDIOD_FBR_STARTADDR 0x100
169 /* SDIO Device FBR Size */
170 #define SDIOD_FBR_SIZE 0x100
172 /* Macro to calculate FBR register base */
173 #define SDIOD_FBR_BASE(n) ((n) * 0x100)
175 /* Function register offsets */
176 #define SDIOD_FBR_DEVCTR 0x00 /* basic info for function */
177 #define SDIOD_FBR_EXT_DEV 0x01 /* extended I/O device code */
178 #define SDIOD_FBR_PWR_SEL 0x02 /* power selection bits */
180 /* SDIO Function CIS ptr offset */
181 #define SDIOD_FBR_CISPTR_0 0x09
182 #define SDIOD_FBR_CISPTR_1 0x0A
183 #define SDIOD_FBR_CISPTR_2 0x0B
185 /* Code Storage Area pointer */
186 #define SDIOD_FBR_CSA_ADDR_0 0x0C
187 #define SDIOD_FBR_CSA_ADDR_1 0x0D
188 #define SDIOD_FBR_CSA_ADDR_2 0x0E
189 #define SDIOD_FBR_CSA_DATA 0x0F
191 /* SDIO Function I/O Block Size */
192 #define SDIOD_FBR_BLKSIZE_0 0x10
193 #define SDIOD_FBR_BLKSIZE_1 0x11
196 #define SDIOD_FBR_DEVCTR_DIC 0x0f /* device interface code */
197 #define SDIOD_FBR_DECVTR_CSA 0x40 /* CSA support flag */
198 #define SDIOD_FBR_DEVCTR_CSA_EN 0x80 /* CSA enabled */
199 /* interface codes */
200 #define SDIOD_DIC_NONE 0 /* SDIO standard interface is not supported */
201 #define SDIOD_DIC_UART 1
202 #define SDIOD_DIC_BLUETOOTH_A 2
203 #define SDIOD_DIC_BLUETOOTH_B 3
204 #define SDIOD_DIC_GPS 4
205 #define SDIOD_DIC_CAMERA 5
206 #define SDIOD_DIC_PHS 6
207 #define SDIOD_DIC_WLAN 7
208 #define SDIOD_DIC_EXT 0xf /* extended device interface, read ext_dev register */
211 #define SDIOD_PWR_SEL_SPS 0x01 /* supports power selection */
212 #define SDIOD_PWR_SEL_EPS 0x02 /* enable power selection (low-current mode) */
215 #define SDIO_FUNC_0 0
216 #define SDIO_FUNC_1 1
217 #define SDIO_FUNC_2 2
218 #define SDIO_FUNC_3 3
219 #define SDIO_FUNC_4 4
220 #define SDIO_FUNC_5 5
221 #define SDIO_FUNC_6 6
222 #define SDIO_FUNC_7 7
224 #define SD_CARD_TYPE_UNKNOWN 0 /* bad type or unrecognized */
225 #define SD_CARD_TYPE_IO 1 /* IO only card */
226 #define SD_CARD_TYPE_MEMORY 2 /* memory only card */
227 #define SD_CARD_TYPE_COMBO 3 /* IO and memory combo card */
229 #define SDIO_MAX_BLOCK_SIZE 2048 /* maximum block size for block mode operation */
230 #define SDIO_MIN_BLOCK_SIZE 1 /* minimum block size for block mode operation */
232 /* Card registers: status bit position */
233 #define CARDREG_STATUS_BIT_OUTOFRANGE 31
234 #define CARDREG_STATUS_BIT_COMCRCERROR 23
235 #define CARDREG_STATUS_BIT_ILLEGALCOMMAND 22
236 #define CARDREG_STATUS_BIT_ERROR 19
237 #define CARDREG_STATUS_BIT_IOCURRENTSTATE3 12
238 #define CARDREG_STATUS_BIT_IOCURRENTSTATE2 11
239 #define CARDREG_STATUS_BIT_IOCURRENTSTATE1 10
240 #define CARDREG_STATUS_BIT_IOCURRENTSTATE0 9
241 #define CARDREG_STATUS_BIT_FUN_NUM_ERROR 4
245 #define SD_CMD_GO_IDLE_STATE 0 /* mandatory for SDIO */
246 #define SD_CMD_SEND_OPCOND 1
247 #define SD_CMD_MMC_SET_RCA 3
248 #define SD_CMD_IO_SEND_OP_COND 5 /* mandatory for SDIO */
249 #define SD_CMD_SELECT_DESELECT_CARD 7
250 #define SD_CMD_SEND_CSD 9
251 #define SD_CMD_SEND_CID 10
252 #define SD_CMD_STOP_TRANSMISSION 12
253 #define SD_CMD_SEND_STATUS 13
254 #define SD_CMD_GO_INACTIVE_STATE 15
255 #define SD_CMD_SET_BLOCKLEN 16
256 #define SD_CMD_READ_SINGLE_BLOCK 17
257 #define SD_CMD_READ_MULTIPLE_BLOCK 18
258 #define SD_CMD_WRITE_BLOCK 24
259 #define SD_CMD_WRITE_MULTIPLE_BLOCK 25
260 #define SD_CMD_PROGRAM_CSD 27
261 #define SD_CMD_SET_WRITE_PROT 28
262 #define SD_CMD_CLR_WRITE_PROT 29
263 #define SD_CMD_SEND_WRITE_PROT 30
264 #define SD_CMD_ERASE_WR_BLK_START 32
265 #define SD_CMD_ERASE_WR_BLK_END 33
266 #define SD_CMD_ERASE 38
267 #define SD_CMD_LOCK_UNLOCK 42
268 #define SD_CMD_IO_RW_DIRECT 52 /* mandatory for SDIO */
269 #define SD_CMD_IO_RW_EXTENDED 53 /* mandatory for SDIO */
270 #define SD_CMD_APP_CMD 55
271 #define SD_CMD_GEN_CMD 56
272 #define SD_CMD_READ_OCR 58
273 #define SD_CMD_CRC_ON_OFF 59 /* mandatory for SDIO */
274 #define SD_ACMD_SD_STATUS 13
275 #define SD_ACMD_SEND_NUM_WR_BLOCKS 22
276 #define SD_ACMD_SET_WR_BLOCK_ERASE_CNT 23
277 #define SD_ACMD_SD_SEND_OP_COND 41
278 #define SD_ACMD_SET_CLR_CARD_DETECT 42
279 #define SD_ACMD_SEND_SCR 51
281 /* argument for SD_CMD_IO_RW_DIRECT and SD_CMD_IO_RW_EXTENDED */
282 #define SD_IO_OP_READ 0 /* Read_Write: Read */
283 #define SD_IO_OP_WRITE 1 /* Read_Write: Write */
284 #define SD_IO_RW_NORMAL 0 /* no RAW */
285 #define SD_IO_RW_RAW 1 /* RAW */
286 #define SD_IO_BYTE_MODE 0 /* Byte Mode */
287 #define SD_IO_BLOCK_MODE 1 /* BlockMode */
288 #define SD_IO_FIXED_ADDRESS 0 /* fix Address */
289 #define SD_IO_INCREMENT_ADDRESS 1 /* IncrementAddress */
291 /* build SD_CMD_IO_RW_DIRECT Argument */
292 #define SDIO_IO_RW_DIRECT_ARG(rw, raw, func, addr, data) \
293 ((((rw) & 1) << 31) | (((func) & 0x7) << 28) | (((raw) & 1) << 27) | \
294 (((addr) & 0x1FFFF) << 9) | ((data) & 0xFF))
296 /* build SD_CMD_IO_RW_EXTENDED Argument */
297 #define SDIO_IO_RW_EXTENDED_ARG(rw, blk, func, addr, inc_addr, count) \
298 ((((rw) & 1) << 31) | (((func) & 0x7) << 28) | (((blk) & 1) << 27) | \
299 (((inc_addr) & 1) << 26) | (((addr) & 0x1FFFF) << 9) | ((count) & 0x1FF))
301 /* SDIO response parameters */
302 #define SD_RSP_NO_NONE 0
303 #define SD_RSP_NO_1 1
304 #define SD_RSP_NO_2 2
305 #define SD_RSP_NO_3 3
306 #define SD_RSP_NO_4 4
307 #define SD_RSP_NO_5 5
308 #define SD_RSP_NO_6 6
310 /* Modified R6 response (to CMD3) */
311 #define SD_RSP_MR6_COM_CRC_ERROR 0x8000
312 #define SD_RSP_MR6_ILLEGAL_COMMAND 0x4000
313 #define SD_RSP_MR6_ERROR 0x2000
315 /* Modified R1 in R4 Response (to CMD5) */
316 #define SD_RSP_MR1_SBIT 0x80
317 #define SD_RSP_MR1_PARAMETER_ERROR 0x40
318 #define SD_RSP_MR1_RFU5 0x20
319 #define SD_RSP_MR1_FUNC_NUM_ERROR 0x10
320 #define SD_RSP_MR1_COM_CRC_ERROR 0x08
321 #define SD_RSP_MR1_ILLEGAL_COMMAND 0x04
322 #define SD_RSP_MR1_RFU1 0x02
323 #define SD_RSP_MR1_IDLE_STATE 0x01
325 /* R5 response (to CMD52 and CMD53) */
326 #define SD_RSP_R5_COM_CRC_ERROR 0x80
327 #define SD_RSP_R5_ILLEGAL_COMMAND 0x40
328 #define SD_RSP_R5_IO_CURRENTSTATE1 0x20
329 #define SD_RSP_R5_IO_CURRENTSTATE0 0x10
330 #define SD_RSP_R5_ERROR 0x08
331 #define SD_RSP_R5_RFU 0x04
332 #define SD_RSP_R5_FUNC_NUM_ERROR 0x02
333 #define SD_RSP_R5_OUT_OF_RANGE 0x01
335 #define SD_RSP_R5_ERRBITS 0xCB
338 /* ------------------------------------------------
339 * SDIO Commands and responses
341 * I/O only commands are:
342 * CMD0, CMD3, CMD5, CMD7, CMD15, CMD52, CMD53
343 * ------------------------------------------------
347 #define SDIOH_CMD_0 0
348 #define SDIOH_CMD_3 3
349 #define SDIOH_CMD_5 5
350 #define SDIOH_CMD_7 7
351 #define SDIOH_CMD_15 15
352 #define SDIOH_CMD_52 52
353 #define SDIOH_CMD_53 53
354 #define SDIOH_CMD_59 59
356 /* SDIO Command Responses */
357 #define SDIOH_RSP_NONE 0
358 #define SDIOH_RSP_R1 1
359 #define SDIOH_RSP_R2 2
360 #define SDIOH_RSP_R3 3
361 #define SDIOH_RSP_R4 4
362 #define SDIOH_RSP_R5 5
363 #define SDIOH_RSP_R6 6
366 * SDIO Response Error flags
368 #define SDIOH_RSP5_ERROR_FLAGS 0xCB
370 /* ------------------------------------------------
371 * SDIO Command structures. I/O only commands are:
373 * CMD0, CMD3, CMD5, CMD7, CMD15, CMD52, CMD53
374 * ------------------------------------------------
377 #define CMD5_OCR_M BITFIELD_MASK(24)
380 #define CMD7_RCA_M BITFIELD_MASK(16)
381 #define CMD7_RCA_S 16
383 #define CMD_15_RCA_M BITFIELD_MASK(16)
384 #define CMD_15_RCA_S 16
386 #define CMD52_DATA_M BITFIELD_MASK(8) /* Bits [7:0] - Write Data/Stuff bits of CMD52
388 #define CMD52_DATA_S 0
389 #define CMD52_REG_ADDR_M BITFIELD_MASK(17) /* Bits [25:9] - register address */
390 #define CMD52_REG_ADDR_S 9
391 #define CMD52_RAW_M BITFIELD_MASK(1) /* Bit 27 - Read after Write flag */
392 #define CMD52_RAW_S 27
393 #define CMD52_FUNCTION_M BITFIELD_MASK(3) /* Bits [30:28] - Function number */
394 #define CMD52_FUNCTION_S 28
395 #define CMD52_RW_FLAG_M BITFIELD_MASK(1) /* Bit 31 - R/W flag */
396 #define CMD52_RW_FLAG_S 31
399 #define CMD53_BYTE_BLK_CNT_M BITFIELD_MASK(9) /* Bits [8:0] - Byte/Block Count of CMD53 */
400 #define CMD53_BYTE_BLK_CNT_S 0
401 #define CMD53_REG_ADDR_M BITFIELD_MASK(17) /* Bits [25:9] - register address */
402 #define CMD53_REG_ADDR_S 9
403 #define CMD53_OP_CODE_M BITFIELD_MASK(1) /* Bit 26 - R/W Operation Code */
404 #define CMD53_OP_CODE_S 26
405 #define CMD53_BLK_MODE_M BITFIELD_MASK(1) /* Bit 27 - Block Mode */
406 #define CMD53_BLK_MODE_S 27
407 #define CMD53_FUNCTION_M BITFIELD_MASK(3) /* Bits [30:28] - Function number */
408 #define CMD53_FUNCTION_S 28
409 #define CMD53_RW_FLAG_M BITFIELD_MASK(1) /* Bit 31 - R/W flag */
410 #define CMD53_RW_FLAG_S 31
412 /* ------------------------------------------------------
413 * SDIO Command Response structures for SD1 and SD4 modes
414 * -----------------------------------------------------
416 #define RSP4_IO_OCR_M BITFIELD_MASK(24) /* Bits [23:0] - Card's OCR Bits [23:0] */
417 #define RSP4_IO_OCR_S 0
418 #define RSP4_STUFF_M BITFIELD_MASK(3) /* Bits [26:24] - Stuff bits */
419 #define RSP4_STUFF_S 24
420 #define RSP4_MEM_PRESENT_M BITFIELD_MASK(1) /* Bit 27 - Memory present */
421 #define RSP4_MEM_PRESENT_S 27
422 #define RSP4_NUM_FUNCS_M BITFIELD_MASK(3) /* Bits [30:28] - Number of I/O funcs */
423 #define RSP4_NUM_FUNCS_S 28
424 #define RSP4_CARD_READY_M BITFIELD_MASK(1) /* Bit 31 - SDIO card ready */
425 #define RSP4_CARD_READY_S 31
427 #define RSP6_STATUS_M BITFIELD_MASK(16) /* Bits [15:0] - Card status bits [19,22,23,12:0]
429 #define RSP6_STATUS_S 0
430 #define RSP6_IO_RCA_M BITFIELD_MASK(16) /* Bits [31:16] - RCA bits[31-16] */
431 #define RSP6_IO_RCA_S 16
433 #define RSP1_AKE_SEQ_ERROR_M BITFIELD_MASK(1) /* Bit 3 - Authentication seq error */
434 #define RSP1_AKE_SEQ_ERROR_S 3
435 #define RSP1_APP_CMD_M BITFIELD_MASK(1) /* Bit 5 - Card expects ACMD */
436 #define RSP1_APP_CMD_S 5
437 #define RSP1_READY_FOR_DATA_M BITFIELD_MASK(1) /* Bit 8 - Ready for data (buff empty) */
438 #define RSP1_READY_FOR_DATA_S 8
439 #define RSP1_CURR_STATE_M BITFIELD_MASK(4) /* Bits [12:9] - State of card
440 * when Cmd was received
442 #define RSP1_CURR_STATE_S 9
443 #define RSP1_EARSE_RESET_M BITFIELD_MASK(1) /* Bit 13 - Erase seq cleared */
444 #define RSP1_EARSE_RESET_S 13
445 #define RSP1_CARD_ECC_DISABLE_M BITFIELD_MASK(1) /* Bit 14 - Card ECC disabled */
446 #define RSP1_CARD_ECC_DISABLE_S 14
447 #define RSP1_WP_ERASE_SKIP_M BITFIELD_MASK(1) /* Bit 15 - Partial blocks erased due to W/P */
448 #define RSP1_WP_ERASE_SKIP_S 15
449 #define RSP1_CID_CSD_OVERW_M BITFIELD_MASK(1) /* Bit 16 - Illegal write to CID or R/O bits
452 #define RSP1_CID_CSD_OVERW_S 16
453 #define RSP1_ERROR_M BITFIELD_MASK(1) /* Bit 19 - General/Unknown error */
454 #define RSP1_ERROR_S 19
455 #define RSP1_CC_ERROR_M BITFIELD_MASK(1) /* Bit 20 - Internal Card Control error */
456 #define RSP1_CC_ERROR_S 20
457 #define RSP1_CARD_ECC_FAILED_M BITFIELD_MASK(1) /* Bit 21 - Card internal ECC failed
460 #define RSP1_CARD_ECC_FAILED_S 21
461 #define RSP1_ILLEGAL_CMD_M BITFIELD_MASK(1) /* Bit 22 - Cmd not legal for the card state */
462 #define RSP1_ILLEGAL_CMD_S 22
463 #define RSP1_COM_CRC_ERROR_M BITFIELD_MASK(1) /* Bit 23 - CRC check of previous command failed
465 #define RSP1_COM_CRC_ERROR_S 23
466 #define RSP1_LOCK_UNLOCK_FAIL_M BITFIELD_MASK(1) /* Bit 24 - Card lock-unlock Cmd Seq error */
467 #define RSP1_LOCK_UNLOCK_FAIL_S 24
468 #define RSP1_CARD_LOCKED_M BITFIELD_MASK(1) /* Bit 25 - Card locked by the host */
469 #define RSP1_CARD_LOCKED_S 25
470 #define RSP1_WP_VIOLATION_M BITFIELD_MASK(1) /* Bit 26 - Attempt to program
471 * write-protected blocks
473 #define RSP1_WP_VIOLATION_S 26
474 #define RSP1_ERASE_PARAM_M BITFIELD_MASK(1) /* Bit 27 - Invalid erase blocks */
475 #define RSP1_ERASE_PARAM_S 27
476 #define RSP1_ERASE_SEQ_ERR_M BITFIELD_MASK(1) /* Bit 28 - Erase Cmd seq error */
477 #define RSP1_ERASE_SEQ_ERR_S 28
478 #define RSP1_BLK_LEN_ERR_M BITFIELD_MASK(1) /* Bit 29 - Block length error */
479 #define RSP1_BLK_LEN_ERR_S 29
480 #define RSP1_ADDR_ERR_M BITFIELD_MASK(1) /* Bit 30 - Misaligned address */
481 #define RSP1_ADDR_ERR_S 30
482 #define RSP1_OUT_OF_RANGE_M BITFIELD_MASK(1) /* Bit 31 - Cmd arg was out of range */
483 #define RSP1_OUT_OF_RANGE_S 31
486 #define RSP5_DATA_M BITFIELD_MASK(8) /* Bits [0:7] - data */
487 #define RSP5_DATA_S 0
488 #define RSP5_FLAGS_M BITFIELD_MASK(8) /* Bit [15:8] - Rsp flags */
489 #define RSP5_FLAGS_S 8
490 #define RSP5_STUFF_M BITFIELD_MASK(16) /* Bits [31:16] - Stuff bits */
491 #define RSP5_STUFF_S 16
493 /* ----------------------------------------------
494 * SDIO Command Response structures for SPI mode
495 * ----------------------------------------------
497 #define SPIRSP4_IO_OCR_M BITFIELD_MASK(16) /* Bits [15:0] - Card's OCR Bits [23:8] */
498 #define SPIRSP4_IO_OCR_S 0
499 #define SPIRSP4_STUFF_M BITFIELD_MASK(3) /* Bits [18:16] - Stuff bits */
500 #define SPIRSP4_STUFF_S 16
501 #define SPIRSP4_MEM_PRESENT_M BITFIELD_MASK(1) /* Bit 19 - Memory present */
502 #define SPIRSP4_MEM_PRESENT_S 19
503 #define SPIRSP4_NUM_FUNCS_M BITFIELD_MASK(3) /* Bits [22:20] - Number of I/O funcs */
504 #define SPIRSP4_NUM_FUNCS_S 20
505 #define SPIRSP4_CARD_READY_M BITFIELD_MASK(1) /* Bit 23 - SDIO card ready */
506 #define SPIRSP4_CARD_READY_S 23
507 #define SPIRSP4_IDLE_STATE_M BITFIELD_MASK(1) /* Bit 24 - idle state */
508 #define SPIRSP4_IDLE_STATE_S 24
509 #define SPIRSP4_ILLEGAL_CMD_M BITFIELD_MASK(1) /* Bit 26 - Illegal Cmd error */
510 #define SPIRSP4_ILLEGAL_CMD_S 26
511 #define SPIRSP4_COM_CRC_ERROR_M BITFIELD_MASK(1) /* Bit 27 - COM CRC error */
512 #define SPIRSP4_COM_CRC_ERROR_S 27
513 #define SPIRSP4_FUNC_NUM_ERROR_M BITFIELD_MASK(1) /* Bit 28 - Function number error
515 #define SPIRSP4_FUNC_NUM_ERROR_S 28
516 #define SPIRSP4_PARAM_ERROR_M BITFIELD_MASK(1) /* Bit 30 - Parameter Error Bit */
517 #define SPIRSP4_PARAM_ERROR_S 30
518 #define SPIRSP4_START_BIT_M BITFIELD_MASK(1) /* Bit 31 - Start Bit */
519 #define SPIRSP4_START_BIT_S 31
521 #define SPIRSP5_DATA_M BITFIELD_MASK(8) /* Bits [23:16] - R/W Data */
522 #define SPIRSP5_DATA_S 16
523 #define SPIRSP5_IDLE_STATE_M BITFIELD_MASK(1) /* Bit 24 - Idle state */
524 #define SPIRSP5_IDLE_STATE_S 24
525 #define SPIRSP5_ILLEGAL_CMD_M BITFIELD_MASK(1) /* Bit 26 - Illegal Cmd error */
526 #define SPIRSP5_ILLEGAL_CMD_S 26
527 #define SPIRSP5_COM_CRC_ERROR_M BITFIELD_MASK(1) /* Bit 27 - COM CRC error */
528 #define SPIRSP5_COM_CRC_ERROR_S 27
529 #define SPIRSP5_FUNC_NUM_ERROR_M BITFIELD_MASK(1) /* Bit 28 - Function number error
531 #define SPIRSP5_FUNC_NUM_ERROR_S 28
532 #define SPIRSP5_PARAM_ERROR_M BITFIELD_MASK(1) /* Bit 30 - Parameter Error Bit */
533 #define SPIRSP5_PARAM_ERROR_S 30
534 #define SPIRSP5_START_BIT_M BITFIELD_MASK(1) /* Bit 31 - Start Bit */
535 #define SPIRSP5_START_BIT_S 31
537 /* RSP6 card status format; Pg 68 Physical Layer spec v 1.10 */
538 #define RSP6STAT_AKE_SEQ_ERROR_M BITFIELD_MASK(1) /* Bit 3 - Authentication seq error
540 #define RSP6STAT_AKE_SEQ_ERROR_S 3
541 #define RSP6STAT_APP_CMD_M BITFIELD_MASK(1) /* Bit 5 - Card expects ACMD */
542 #define RSP6STAT_APP_CMD_S 5
543 #define RSP6STAT_READY_FOR_DATA_M BITFIELD_MASK(1) /* Bit 8 - Ready for data
546 #define RSP6STAT_READY_FOR_DATA_S 8
547 #define RSP6STAT_CURR_STATE_M BITFIELD_MASK(4) /* Bits [12:9] - Card state at
550 #define RSP6STAT_CURR_STATE_S 9
551 #define RSP6STAT_ERROR_M BITFIELD_MASK(1) /* Bit 13 - General/Unknown error Bit 19
553 #define RSP6STAT_ERROR_S 13
554 #define RSP6STAT_ILLEGAL_CMD_M BITFIELD_MASK(1) /* Bit 14 - Illegal cmd for
557 #define RSP6STAT_ILLEGAL_CMD_S 14
558 #define RSP6STAT_COM_CRC_ERROR_M BITFIELD_MASK(1) /* Bit 15 - CRC previous command
561 #define RSP6STAT_COM_CRC_ERROR_S 15
563 #define SDIOH_XFER_TYPE_READ SD_IO_OP_READ
564 #define SDIOH_XFER_TYPE_WRITE SD_IO_OP_WRITE