2 * Misc utility routines for accessing chip-specific features
3 * of the SiliconBackplane-based Broadcom chips.
5 * Copyright (C) 1999-2010, Broadcom Corporation
7 * Unless you and Broadcom execute a separate written software license
8 * agreement governing use of this software, this software is licensed to you
9 * under the terms of the GNU General Public License version 2 (the "GPL"),
10 * available at http://www.broadcom.com/licenses/GPLv2.php, with the
11 * following added to such license:
13 * As a special exception, the copyright holders of this software give you
14 * permission to link this software with independent modules, and to copy and
15 * distribute the resulting executable under terms of your choice, provided that
16 * you also meet, for each linked independent module, the terms and conditions of
17 * the license of that module. An independent module is a module which is not
18 * derived from this software. The special exception does not apply to any
19 * modifications of the software.
21 * Notwithstanding the above, under no circumstances may you combine this
22 * software in any way with any other Broadcom software provided under a license
23 * other than the GPL, without Broadcom's express prior written consent.
25 * $Id: aiutils.c,v 1.6.4.7.4.6 2010/04/21 20:43:47 Exp $
37 #include "siutils_priv.h"
40 get_asd(si_t *sih, uint32 *eromptr, uint sp, uint ad, uint st,
41 uint32 *addrl, uint32 *addrh, uint32 *sizel, uint32 *sizeh);
47 get_erom_ent(si_t *sih, uint32 *eromptr, uint32 mask, uint32 match)
50 uint inv = 0, nom = 0;
53 ent = R_REG(si_osh(sih), (uint32 *)(uintptr)(*eromptr));
54 *eromptr += sizeof(uint32);
59 if ((ent & ER_VALID) == 0) {
64 if (ent == (ER_END | ER_VALID))
67 if ((ent & mask) == match)
73 SI_MSG(("%s: Returning ent 0x%08x\n", __FUNCTION__, ent));
75 SI_MSG((" after %d invalid and %d non-matching entries\n", inv, nom));
80 get_asd(si_t *sih, uint32 *eromptr, uint sp, uint ad, uint st,
81 uint32 *addrl, uint32 *addrh, uint32 *sizel, uint32 *sizeh)
85 asd = get_erom_ent(sih, eromptr, ER_VALID, ER_VALID);
86 if (((asd & ER_TAG1) != ER_ADD) ||
87 (((asd & AD_SP_MASK) >> AD_SP_SHIFT) != sp) ||
88 ((asd & AD_ST_MASK) != st)) {
89 /* This is not what we want, "push" it back */
90 *eromptr -= sizeof(uint32);
93 *addrl = asd & AD_ADDR_MASK;
95 *addrh = get_erom_ent(sih, eromptr, 0, 0);
99 sz = asd & AD_SZ_MASK;
100 if (sz == AD_SZ_SZD) {
101 szd = get_erom_ent(sih, eromptr, 0, 0);
102 *sizel = szd & SD_SZ_MASK;
104 *sizeh = get_erom_ent(sih, eromptr, 0, 0);
106 *sizel = AD_SZ_BASE << (sz >> AD_SZ_SHIFT);
108 SI_MSG((" SP %d, ad %d: st = %d, 0x%08x_0x%08x @ 0x%08x_0x%08x\n",
109 sp, ad, st, *sizeh, *sizel, *addrh, *addrl));
114 /* parse the enumeration rom to identify all cores */
116 ai_scan(si_t *sih, void *regs, uint devid)
118 si_info_t *sii = SI_INFO(sih);
119 chipcregs_t *cc = (chipcregs_t *)regs;
120 uint32 erombase, eromptr, eromlim;
122 erombase = R_REG(sii->osh, &cc->eromptr);
124 switch (BUSTYPE(sih->bustype)) {
126 eromptr = (uintptr)REG_MAP(erombase, SI_CORE_SIZE);
130 /* Set wrappers address */
131 sii->curwrap = (void *)((uintptr)regs + SI_CORE_SIZE);
133 /* Now point the window at the erom */
134 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN, 4, erombase);
135 eromptr = (uint32)(uintptr)regs;
145 SI_ERROR(("Don't know how to do AXI enumertion on bus %d\n", sih->bustype));
149 eromlim = eromptr + ER_REMAPCONTROL;
151 SI_MSG(("ai_scan: regs = 0x%p, erombase = 0x%08x, eromptr = 0x%08x, eromlim = 0x%08x\n",
152 regs, erombase, eromptr, eromlim));
153 while (eromptr < eromlim) {
154 uint32 cia, cib, base, cid, mfg, crev, nmw, nsw, nmp, nsp;
155 uint32 mpd, asd, addrl, addrh, sizel, sizeh;
161 /* Grok a component */
162 cia = get_erom_ent(sih, &eromptr, ER_TAG, ER_CI);
163 if (cia == (ER_END | ER_VALID)) {
164 SI_MSG(("Found END of erom after %d cores\n", sii->numcores));
167 base = eromptr - sizeof(uint32);
168 cib = get_erom_ent(sih, &eromptr, 0, 0);
170 if ((cib & ER_TAG) != ER_CI) {
171 SI_ERROR(("CIA not followed by CIB\n"));
175 cid = (cia & CIA_CID_MASK) >> CIA_CID_SHIFT;
176 mfg = (cia & CIA_MFG_MASK) >> CIA_MFG_SHIFT;
177 crev = (cib & CIB_REV_MASK) >> CIB_REV_SHIFT;
178 nmw = (cib & CIB_NMW_MASK) >> CIB_NMW_SHIFT;
179 nsw = (cib & CIB_NSW_MASK) >> CIB_NSW_SHIFT;
180 nmp = (cib & CIB_NMP_MASK) >> CIB_NMP_SHIFT;
181 nsp = (cib & CIB_NSP_MASK) >> CIB_NSP_SHIFT;
183 SI_MSG(("Found component 0x%04x/0x%4x rev %d at erom addr 0x%08x, with nmw = %d, "
184 "nsw = %d, nmp = %d & nsp = %d\n",
185 mfg, cid, crev, base, nmw, nsw, nmp, nsp));
187 if (((mfg == MFGID_ARM) && (cid == DEF_AI_COMP)) || (nsp == 0))
189 if ((nmw + nsw == 0)) {
190 /* A component which is not a core */
191 if (cid == OOB_ROUTER_CORE_ID) {
192 asd = get_asd(sih, &eromptr, 0, 0, AD_ST_SLAVE,
193 &addrl, &addrh, &sizel, &sizeh);
195 sii->common_info->oob_router = addrl;
202 /* sii->eromptr[idx] = base; */
203 sii->common_info->cia[idx] = cia;
204 sii->common_info->cib[idx] = cib;
205 sii->common_info->coreid[idx] = cid;
207 for (i = 0; i < nmp; i++) {
208 mpd = get_erom_ent(sih, &eromptr, ER_VALID, ER_VALID);
209 if ((mpd & ER_TAG) != ER_MP) {
210 SI_ERROR(("Not enough MP entries for component 0x%x\n", cid));
213 SI_MSG((" Master port %d, mp: %d id: %d\n", i,
214 (mpd & MPD_MP_MASK) >> MPD_MP_SHIFT,
215 (mpd & MPD_MUI_MASK) >> MPD_MUI_SHIFT));
218 /* First Slave Address Descriptor should be port 0:
219 * the main register space for the core
221 asd = get_asd(sih, &eromptr, 0, 0, AD_ST_SLAVE, &addrl, &addrh, &sizel, &sizeh);
223 /* Try again to see if it is a bridge */
224 asd = get_asd(sih, &eromptr, 0, 0, AD_ST_BRIDGE, &addrl, &addrh,
229 if ((addrh != 0) || (sizeh != 0) || (sizel != SI_CORE_SIZE)) {
230 SI_ERROR(("First Slave ASD for core 0x%04x malformed "
231 "(0x%08x)\n", cid, asd));
235 sii->common_info->coresba[idx] = addrl;
236 sii->common_info->coresba_size[idx] = sizel;
237 /* Get any more ASDs in port 0 */
240 asd = get_asd(sih, &eromptr, 0, j, AD_ST_SLAVE, &addrl, &addrh,
242 if ((asd != 0) && (j == 1) && (sizel == SI_CORE_SIZE))
243 sii->common_info->coresba2[idx] = addrl;
244 sii->common_info->coresba2_size[idx] = sizel;
248 /* Go through the ASDs for other slave ports */
249 for (i = 1; i < nsp; i++) {
252 asd = get_asd(sih, &eromptr, i, j++, AD_ST_SLAVE, &addrl, &addrh,
256 SI_ERROR((" SP %d has no address descriptors\n", i));
261 /* Now get master wrappers */
262 for (i = 0; i < nmw; i++) {
263 asd = get_asd(sih, &eromptr, i, 0, AD_ST_MWRAP, &addrl, &addrh,
266 SI_ERROR(("Missing descriptor for MW %d\n", i));
269 if ((sizeh != 0) || (sizel != SI_CORE_SIZE)) {
270 SI_ERROR(("Master wrapper %d is not 4KB\n", i));
274 sii->common_info->wrapba[idx] = addrl;
277 /* And finally slave wrappers */
278 for (i = 0; i < nsw; i++) {
279 uint fwp = (nsp == 1) ? 0 : 1;
280 asd = get_asd(sih, &eromptr, fwp + i, 0, AD_ST_SWRAP, &addrl, &addrh,
283 SI_ERROR(("Missing descriptor for SW %d\n", i));
286 if ((sizeh != 0) || (sizel != SI_CORE_SIZE)) {
287 SI_ERROR(("Slave wrapper %d is not 4KB\n", i));
290 if ((nmw == 0) && (i == 0))
291 sii->common_info->wrapba[idx] = addrl;
294 /* Don't record bridges */
302 SI_ERROR(("Reached end of erom without finding END"));
309 /* This function changes the logical "focus" to the indicated core.
310 * Return the current core's virtual address.
313 ai_setcoreidx(si_t *sih, uint coreidx)
315 si_info_t *sii = SI_INFO(sih);
316 uint32 addr = sii->common_info->coresba[coreidx];
317 uint32 wrap = sii->common_info->wrapba[coreidx];
320 if (coreidx >= sii->numcores)
324 * If the user has provided an interrupt mask enabled function,
325 * then assert interrupts are disabled before switching the core.
327 ASSERT((sii->intrsenabled_fn == NULL) || !(*(sii)->intrsenabled_fn)((sii)->intr_arg));
329 switch (BUSTYPE(sih->bustype)) {
332 if (!sii->common_info->regs[coreidx]) {
333 sii->common_info->regs[coreidx] = REG_MAP(addr, SI_CORE_SIZE);
334 ASSERT(GOODREGS(sii->common_info->regs[coreidx]));
336 sii->curmap = regs = sii->common_info->regs[coreidx];
337 if (!sii->common_info->wrappers[coreidx]) {
338 sii->common_info->wrappers[coreidx] = REG_MAP(wrap, SI_CORE_SIZE);
339 ASSERT(GOODREGS(sii->common_info->wrappers[coreidx]));
341 sii->curwrap = sii->common_info->wrappers[coreidx];
347 sii->curmap = regs = (void *)((uintptr)addr);
348 sii->curwrap = (void *)((uintptr)wrap);
359 sii->curidx = coreidx;
364 /* Return the number of address spaces in current core */
366 ai_numaddrspaces(si_t *sih)
371 /* Return the address of the nth address space in the current core */
373 ai_addrspace(si_t *sih, uint asidx)
382 return sii->common_info->coresba[cidx];
384 return sii->common_info->coresba2[cidx];
386 SI_ERROR(("%s: Need to parse the erom again to find addr space %d\n",
387 __FUNCTION__, asidx));
392 /* Return the size of the nth address space in the current core */
394 ai_addrspacesize(si_t *sih, uint asidx)
403 return sii->common_info->coresba_size[cidx];
405 return sii->common_info->coresba2_size[cidx];
407 SI_ERROR(("%s: Need to parse the erom again to find addr space %d\n",
408 __FUNCTION__, asidx));
422 return (R_REG(sii->osh, &ai->oobselouta30) & 0x1f);
426 ai_setint(si_t *sih, int siflag)
431 ai_write_wrap_reg(si_t *sih, uint32 offset, uint32 val)
433 si_info_t *sii = SI_INFO(sih);
434 aidmp_t *ai = sii->curwrap;
435 W_REG(sii->osh, (uint32 *)((uint8 *)ai+offset), val);
440 ai_corevendor(si_t *sih)
446 cia = sii->common_info->cia[sii->curidx];
447 return ((cia & CIA_MFG_MASK) >> CIA_MFG_SHIFT);
451 ai_corerev(si_t *sih)
457 cib = sii->common_info->cib[sii->curidx];
458 return ((cib & CIB_REV_MASK) >> CIB_REV_SHIFT);
462 ai_iscoreup(si_t *sih)
470 return (((R_REG(sii->osh, &ai->ioctrl) & (SICF_FGC | SICF_CLOCK_EN)) == SICF_CLOCK_EN) &&
471 ((R_REG(sii->osh, &ai->resetctrl) & AIRC_RESET) == 0));
475 * Switch to 'coreidx', issue a single arbitrary 32bit register mask&set operation,
476 * switch back to the original core, and return the new value.
478 * When using the silicon backplane, no fidleing with interrupts or core switches are needed.
480 * Also, when using pci/pcie, we can optimize away the core switching for pci registers
481 * and (on newer pci cores) chipcommon registers.
484 ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val)
495 ASSERT(GOODIDX(coreidx));
496 ASSERT(regoff < SI_CORE_SIZE);
497 ASSERT((val & ~mask) == 0);
499 if (coreidx >= SI_MAXCORES)
502 if (BUSTYPE(sih->bustype) == SI_BUS) {
503 /* If internal bus, we can always get at everything */
505 /* map if does not exist */
506 if (!sii->common_info->wrappers[coreidx]) {
507 sii->common_info->regs[coreidx] =
508 REG_MAP(sii->common_info->coresba[coreidx], SI_CORE_SIZE);
509 ASSERT(GOODREGS(sii->common_info->regs[coreidx]));
511 r = (uint32 *)((uchar *)sii->common_info->regs[coreidx] + regoff);
512 } else if (BUSTYPE(sih->bustype) == PCI_BUS) {
513 /* If pci/pcie, we can get at pci/pcie regs and on newer cores to chipc */
515 if ((sii->common_info->coreid[coreidx] == CC_CORE_ID) && SI_FAST(sii)) {
516 /* Chipc registers are mapped at 12KB */
519 r = (uint32 *)((char *)sii->curmap + PCI_16KB0_CCREGS_OFFSET + regoff);
520 } else if (sii->pub.buscoreidx == coreidx) {
521 /* pci registers are at either in the last 2KB of an 8KB window
522 * or, in pcie and pci rev 13 at 8KB
526 r = (uint32 *)((char *)sii->curmap +
527 PCI_16KB0_PCIREGS_OFFSET + regoff);
529 r = (uint32 *)((char *)sii->curmap +
530 ((regoff >= SBCONFIGOFF) ?
531 PCI_BAR0_PCISBR_OFFSET : PCI_BAR0_PCIREGS_OFFSET) +
537 INTR_OFF(sii, intr_val);
539 /* save current core index */
540 origidx = si_coreidx(&sii->pub);
543 r = (uint32*) ((uchar*) ai_setcoreidx(&sii->pub, coreidx) + regoff);
549 w = (R_REG(sii->osh, r) & ~mask) | val;
550 W_REG(sii->osh, r, w);
554 w = R_REG(sii->osh, r);
557 /* restore core index */
558 if (origidx != coreidx)
559 ai_setcoreidx(&sii->pub, origidx);
561 INTR_RESTORE(sii, intr_val);
568 ai_core_disable(si_t *sih, uint32 bits)
571 volatile uint32 dummy;
576 ASSERT(GOODREGS(sii->curwrap));
579 /* if core is already in reset, just return */
580 if (R_REG(sii->osh, &ai->resetctrl) & AIRC_RESET)
583 W_REG(sii->osh, &ai->ioctrl, bits);
584 dummy = R_REG(sii->osh, &ai->ioctrl);
587 W_REG(sii->osh, &ai->resetctrl, AIRC_RESET);
591 /* reset and re-enable a core
593 * bits - core specific bits that are set during and after reset sequence
594 * resetbits - core specific bits that are set only during reset sequence
597 ai_core_reset(si_t *sih, uint32 bits, uint32 resetbits)
601 volatile uint32 dummy;
604 ASSERT(GOODREGS(sii->curwrap));
608 * Must do the disable sequence first to work for arbitrary current core state.
610 ai_core_disable(sih, (bits | resetbits));
613 * Now do the initialization sequence.
615 W_REG(sii->osh, &ai->ioctrl, (bits | SICF_FGC | SICF_CLOCK_EN));
616 dummy = R_REG(sii->osh, &ai->ioctrl);
617 W_REG(sii->osh, &ai->resetctrl, 0);
620 W_REG(sii->osh, &ai->ioctrl, (bits | SICF_CLOCK_EN));
621 dummy = R_REG(sii->osh, &ai->ioctrl);
627 ai_core_cflags_wo(si_t *sih, uint32 mask, uint32 val)
634 ASSERT(GOODREGS(sii->curwrap));
637 ASSERT((val & ~mask) == 0);
640 w = ((R_REG(sii->osh, &ai->ioctrl) & ~mask) | val);
641 W_REG(sii->osh, &ai->ioctrl, w);
646 ai_core_cflags(si_t *sih, uint32 mask, uint32 val)
653 ASSERT(GOODREGS(sii->curwrap));
656 ASSERT((val & ~mask) == 0);
659 w = ((R_REG(sii->osh, &ai->ioctrl) & ~mask) | val);
660 W_REG(sii->osh, &ai->ioctrl, w);
663 return R_REG(sii->osh, &ai->ioctrl);
667 ai_core_sflags(si_t *sih, uint32 mask, uint32 val)
674 ASSERT(GOODREGS(sii->curwrap));
677 ASSERT((val & ~mask) == 0);
678 ASSERT((mask & ~SISF_CORE_BITS) == 0);
681 w = ((R_REG(sii->osh, &ai->iostatus) & ~mask) | val);
682 W_REG(sii->osh, &ai->iostatus, w);
685 return R_REG(sii->osh, &ai->iostatus);