2 * 'Standard' SDIO HOST CONTROLLER driver
4 * Copyright (C) 1999-2010, Broadcom Corporation
6 * Unless you and Broadcom execute a separate written software license
7 * agreement governing use of this software, this software is licensed to you
8 * under the terms of the GNU General Public License version 2 (the "GPL"),
9 * available at http://www.broadcom.com/licenses/GPLv2.php, with the
10 * following added to such license:
12 * As a special exception, the copyright holders of this software give you
13 * permission to link this software with independent modules, and to copy and
14 * distribute the resulting executable under terms of your choice, provided that
15 * you also meet, for each linked independent module, the terms and conditions of
16 * the license of that module. An independent module is a module which is not
17 * derived from this software. The special exception does not apply to any
18 * modifications of the software.
20 * Notwithstanding the above, under no circumstances may you combine this
21 * software in any way with any other Broadcom software provided under a license
22 * other than the GPL, without Broadcom's express prior written consent.
24 * $Id: bcmsdstd.c,v 1.64.4.1.4.4.2.18 2010/08/17 17:00:48 Exp $
30 #include <bcmendian.h>
34 #include <sdio.h> /* SDIO Device and Protocol Specs */
35 #include <sdioh.h> /* SDIO Host Controller Specification */
36 #include <bcmsdbus.h> /* bcmsdh to/from specific controller APIs */
37 #include <sdiovar.h> /* ioctl/iovars */
41 #define SD_PAGE_BITS 12
42 #define SD_PAGE (1 << SD_PAGE_BITS)
47 uint sd_msglevel = SDH_ERROR_VAL;
48 uint sd_hiok = TRUE; /* Use hi-speed mode if available? */
49 uint sd_sdmode = SDIOH_MODE_SD4; /* Use SD4 mode by default */
50 uint sd_f2_blocksize = 64; /* Default blocksize */
53 bool sd_yieldcpu = TRUE; /* Allow CPU yielding for buffer requests */
54 uint sd_minyield = 0; /* Minimum xfer size to allow CPU yield */
55 bool sd_forcerb = FALSE; /* Force sync readback in intrs_on/off */
58 uint sd_divisor = 2; /* Default 48MHz/2 = 24MHz */
60 uint sd_power = 1; /* Default to SD Slot powered ON */
61 uint sd_clock = 1; /* Default to SD Clock turned ON */
62 uint sd_pci_slot = 0xFFFFffff; /* Used to force selection of a particular PCI slot */
63 uint8 sd_dma_mode = DMA_MODE_SDMA; /* Default to SDMA for now */
67 static bool trap_errs = FALSE;
69 static const char *dma_mode_description[] = { "PIO", "SDMA", "ADMA1", "32b ADMA2", "64b ADMA2" };
72 static bool sdstd_start_clock(sdioh_info_t *sd, uint16 divisor);
73 static bool sdstd_start_power(sdioh_info_t *sd);
74 static bool sdstd_bus_width(sdioh_info_t *sd, int width);
75 static int sdstd_set_highspeed_mode(sdioh_info_t *sd, bool HSMode);
76 static int sdstd_set_dma_mode(sdioh_info_t *sd, int8 dma_mode);
77 static int sdstd_card_enablefuncs(sdioh_info_t *sd);
78 static void sdstd_cmd_getrsp(sdioh_info_t *sd, uint32 *rsp_buffer, int count);
79 static int sdstd_cmd_issue(sdioh_info_t *sd, bool use_dma, uint32 cmd, uint32 arg);
80 static int sdstd_card_regread(sdioh_info_t *sd, int func, uint32 regaddr,
81 int regsize, uint32 *data);
82 static int sdstd_card_regwrite(sdioh_info_t *sd, int func, uint32 regaddr,
83 int regsize, uint32 data);
84 static int sdstd_driver_init(sdioh_info_t *sd);
85 static bool sdstd_reset(sdioh_info_t *sd, bool host_reset, bool client_reset);
86 static int sdstd_card_buf(sdioh_info_t *sd, int rw, int func, bool fifo,
87 uint32 addr, int nbytes, uint32 *data);
88 static int sdstd_abort(sdioh_info_t *sd, uint func);
89 static int sdstd_check_errs(sdioh_info_t *sdioh_info, uint32 cmd, uint32 arg);
90 static int set_client_block_size(sdioh_info_t *sd, int func, int blocksize);
91 static void sd_map_dma(sdioh_info_t * sd);
92 static void sd_unmap_dma(sdioh_info_t * sd);
93 static void sd_clear_adma_dscr_buf(sdioh_info_t *sd);
94 static void sd_fill_dma_data_buf(sdioh_info_t *sd, uint8 data);
95 static void sd_create_adma_descriptor(sdioh_info_t *sd,
96 uint32 index, uint32 addr_phys,
97 uint16 length, uint16 flags);
98 static void sd_dump_adma_dscr(sdioh_info_t *sd);
99 static void sdstd_dumpregs(sdioh_info_t *sd);
103 * Private register access routines.
106 /* 16 bit PCI regs */
108 extern uint16 sdstd_rreg16(sdioh_info_t *sd, uint reg);
110 sdstd_rreg16(sdioh_info_t *sd, uint reg)
113 volatile uint16 data = *(volatile uint16 *)(sd->mem_space + reg);
114 sd_ctrl(("16: R Reg 0x%02x, Data 0x%x\n", reg, data));
118 extern void sdstd_wreg16(sdioh_info_t *sd, uint reg, uint16 data);
120 sdstd_wreg16(sdioh_info_t *sd, uint reg, uint16 data)
122 *(volatile uint16 *)(sd->mem_space + reg) = (uint16)data;
123 sd_ctrl(("16: W Reg 0x%02x, Data 0x%x\n", reg, data));
127 sdstd_or_reg16(sdioh_info_t *sd, uint reg, uint16 val)
129 volatile uint16 data = *(volatile uint16 *)(sd->mem_space + reg);
130 sd_ctrl(("16: OR Reg 0x%02x, Val 0x%x\n", reg, val));
132 *(volatile uint16 *)(sd->mem_space + reg) = (uint16)data;
136 sdstd_mod_reg16(sdioh_info_t *sd, uint reg, int16 mask, uint16 val)
139 volatile uint16 data = *(volatile uint16 *)(sd->mem_space + reg);
140 sd_ctrl(("16: MOD Reg 0x%02x, Mask 0x%x, Val 0x%x\n", reg, mask, val));
142 data |= (val & mask);
143 *(volatile uint16 *)(sd->mem_space + reg) = (uint16)data;
147 /* 32 bit PCI regs */
149 sdstd_rreg(sdioh_info_t *sd, uint reg)
151 volatile uint32 data = *(volatile uint32 *)(sd->mem_space + reg);
152 sd_ctrl(("32: R Reg 0x%02x, Data 0x%x\n", reg, data));
156 sdstd_wreg(sdioh_info_t *sd, uint reg, uint32 data)
158 *(volatile uint32 *)(sd->mem_space + reg) = (uint32)data;
159 sd_ctrl(("32: W Reg 0x%02x, Data 0x%x\n", reg, data));
165 sdstd_wreg8(sdioh_info_t *sd, uint reg, uint8 data)
167 *(volatile uint8 *)(sd->mem_space + reg) = (uint8)data;
168 sd_ctrl(("08: W Reg 0x%02x, Data 0x%x\n", reg, data));
171 sdstd_rreg8(sdioh_info_t *sd, uint reg)
173 volatile uint8 data = *(volatile uint8 *)(sd->mem_space + reg);
174 sd_ctrl(("08: R Reg 0x%02x, Data 0x%x\n", reg, data));
179 * Private work routines
182 sdioh_info_t *glob_sd;
185 * Public entry points & extern's
187 extern sdioh_info_t *
188 sdioh_attach(osl_t *osh, void *bar0, uint irq)
192 sd_trace(("%s\n", __FUNCTION__));
193 if ((sd = (sdioh_info_t *)MALLOC(osh, sizeof(sdioh_info_t))) == NULL) {
194 sd_err(("sdioh_attach: out of memory, malloced %d bytes\n", MALLOCED(osh)));
197 bzero((char *)sd, sizeof(sdioh_info_t));
200 if (sdstd_osinit(sd) != 0) {
201 sd_err(("%s:sdstd_osinit() failed\n", __FUNCTION__));
202 MFREE(sd->osh, sd, sizeof(sdioh_info_t));
205 sd->mem_space = (volatile char *)sdstd_reg_map(osh, (uintptr)bar0, SDIOH_REG_WINSZ);
208 if (sd->mem_space == NULL) {
209 sd_err(("%s:ioremap() failed\n", __FUNCTION__));
211 MFREE(sd->osh, sd, sizeof(sdioh_info_t));
214 sd_info(("%s:sd->mem_space = %p\n", __FUNCTION__, sd->mem_space));
215 sd->intr_handler = NULL;
216 sd->intr_handler_arg = NULL;
217 sd->intr_handler_valid = FALSE;
220 sd->sd_blockmode = TRUE;
221 sd->use_client_ints = TRUE;
222 sd->sd_dma_mode = sd_dma_mode;
224 if (!sd->sd_blockmode)
225 sd->sd_dma_mode = DMA_MODE_NONE;
227 if (sdstd_driver_init(sd) != SUCCESS) {
228 /* If host CPU was reset without resetting SD bus or
229 SD device, the device will still have its RCA but
230 driver no longer knows what it is (since driver has been restarted).
231 go through once to clear the RCA and a gain reassign it.
233 sd_info(("driver_init failed - Reset RCA and try again\n"));
234 if (sdstd_driver_init(sd) != SUCCESS) {
235 sd_err(("%s:driver_init() failed()\n", __FUNCTION__));
237 sdstd_reg_unmap(osh, (uintptr)sd->mem_space, SDIOH_REG_WINSZ);
238 sd->mem_space = NULL;
241 MFREE(sd->osh, sd, sizeof(sdioh_info_t));
246 OSL_DMADDRWIDTH(osh, 32);
248 /* Always map DMA buffers, so we can switch between DMA modes. */
251 if (sdstd_register_irq(sd, irq) != SUCCESS) {
252 sd_err(("%s: sdstd_register_irq() failed for irq = %d\n", __FUNCTION__, irq));
253 sdstd_free_irq(sd->irq, sd);
255 sdstd_reg_unmap(osh, (uintptr)sd->mem_space, SDIOH_REG_WINSZ);
256 sd->mem_space = NULL;
260 MFREE(sd->osh, sd, sizeof(sdioh_info_t));
264 sd_trace(("%s: Done\n", __FUNCTION__));
269 sdioh_detach(osl_t *osh, sdioh_info_t *sd)
271 sd_trace(("%s\n", __FUNCTION__));
274 sdstd_wreg16(sd, SD_IntrSignalEnable, 0);
275 sd_trace(("%s: freeing irq %d\n", __FUNCTION__, sd->irq));
276 sdstd_free_irq(sd->irq, sd);
277 if (sd->card_init_done)
278 sdstd_reset(sd, 1, 1);
280 sdstd_reg_unmap(osh, (uintptr)sd->mem_space, SDIOH_REG_WINSZ);
281 sd->mem_space = NULL;
285 MFREE(sd->osh, sd, sizeof(sdioh_info_t));
287 return SDIOH_API_RC_SUCCESS;
290 /* Configure callback to client when we receive client interrupt */
292 sdioh_interrupt_register(sdioh_info_t *sd, sdioh_cb_fn_t fn, void *argh)
294 sd_trace(("%s: Entering\n", __FUNCTION__));
295 sd->intr_handler = fn;
296 sd->intr_handler_arg = argh;
297 sd->intr_handler_valid = TRUE;
298 return SDIOH_API_RC_SUCCESS;
302 sdioh_interrupt_deregister(sdioh_info_t *sd)
304 sd_trace(("%s: Entering\n", __FUNCTION__));
305 sd->intr_handler_valid = FALSE;
306 sd->intr_handler = NULL;
307 sd->intr_handler_arg = NULL;
308 return SDIOH_API_RC_SUCCESS;
312 sdioh_interrupt_query(sdioh_info_t *sd, bool *onoff)
314 sd_trace(("%s: Entering\n", __FUNCTION__));
315 *onoff = sd->client_intr_enabled;
316 return SDIOH_API_RC_SUCCESS;
319 #if defined(DHD_DEBUG)
321 sdioh_interrupt_pending(sdioh_info_t *sd)
324 intrstatus = sdstd_rreg16(sd, SD_IntrStatus);
325 return !!(intrstatus & CLIENT_INTR);
330 sdioh_query_iofnum(sdioh_info_t *sd)
332 return sd->num_funcs;
357 const bcm_iovar_t sdioh_iovars[] = {
358 {"sd_msglevel", IOV_MSGLEVEL, 0, IOVT_UINT32, 0 },
359 {"sd_blockmode", IOV_BLOCKMODE, 0, IOVT_BOOL, 0 },
360 {"sd_blocksize", IOV_BLOCKSIZE, 0, IOVT_UINT32, 0 }, /* ((fn << 16) | size) */
361 {"sd_dma", IOV_DMA, 0, IOVT_UINT32, 0 },
363 {"sd_yieldcpu", IOV_YIELDCPU, 0, IOVT_BOOL, 0 },
364 {"sd_minyield", IOV_MINYIELD, 0, IOVT_UINT32, 0 },
365 {"sd_forcerb", IOV_FORCERB, 0, IOVT_BOOL, 0 },
367 {"sd_ints", IOV_USEINTS, 0, IOVT_BOOL, 0 },
368 {"sd_numints", IOV_NUMINTS, 0, IOVT_UINT32, 0 },
369 {"sd_numlocalints", IOV_NUMLOCALINTS, 0, IOVT_UINT32, 0 },
370 {"sd_hostreg", IOV_HOSTREG, 0, IOVT_BUFFER, sizeof(sdreg_t) },
371 {"sd_devreg", IOV_DEVREG, 0, IOVT_BUFFER, sizeof(sdreg_t) },
372 {"sd_divisor", IOV_DIVISOR, 0, IOVT_UINT32, 0 },
373 {"sd_power", IOV_POWER, 0, IOVT_UINT32, 0 },
374 {"sd_clock", IOV_CLOCK, 0, IOVT_UINT32, 0 },
375 {"sd_mode", IOV_SDMODE, 0, IOVT_UINT32, 100},
376 {"sd_highspeed", IOV_HISPEED, 0, IOVT_UINT32, 0},
381 sdioh_iovar_op(sdioh_info_t *si, const char *name,
382 void *params, int plen, void *arg, int len, bool set)
384 const bcm_iovar_t *vi = NULL;
394 /* Get must have return space; Set does not take qualifiers */
395 ASSERT(set || (arg && len));
396 ASSERT(!set || (!params && !plen));
398 sd_trace(("%s: Enter (%s %s)\n", __FUNCTION__, (set ? "set" : "get"), name));
400 if ((vi = bcm_iovar_lookup(sdioh_iovars, name)) == NULL) {
401 bcmerror = BCME_UNSUPPORTED;
405 if ((bcmerror = bcm_iovar_lencheck(vi, arg, len, set)) != 0)
408 /* Set up params so get and set can share the convenience variables */
409 if (params == NULL) {
414 if (vi->type == IOVT_VOID)
416 else if (vi->type == IOVT_BUFFER)
419 val_size = sizeof(int);
421 if (plen >= (int)sizeof(int_val))
422 bcopy(params, &int_val, sizeof(int_val));
424 bool_val = (int_val != 0) ? TRUE : FALSE;
426 actionid = set ? IOV_SVAL(vi->varid) : IOV_GVAL(vi->varid);
428 case IOV_GVAL(IOV_MSGLEVEL):
429 int_val = (int32)sd_msglevel;
430 bcopy(&int_val, arg, val_size);
433 case IOV_SVAL(IOV_MSGLEVEL):
434 sd_msglevel = int_val;
437 case IOV_GVAL(IOV_BLOCKMODE):
438 int_val = (int32)si->sd_blockmode;
439 bcopy(&int_val, arg, val_size);
442 case IOV_SVAL(IOV_BLOCKMODE):
443 si->sd_blockmode = (bool)int_val;
444 /* Haven't figured out how to make non-block mode with DMA */
445 if (!si->sd_blockmode)
446 si->sd_dma_mode = DMA_MODE_NONE;
450 case IOV_GVAL(IOV_YIELDCPU):
451 int_val = sd_yieldcpu;
452 bcopy(&int_val, arg, val_size);
455 case IOV_SVAL(IOV_YIELDCPU):
456 sd_yieldcpu = (bool)int_val;
459 case IOV_GVAL(IOV_MINYIELD):
460 int_val = sd_minyield;
461 bcopy(&int_val, arg, val_size);
464 case IOV_SVAL(IOV_MINYIELD):
465 sd_minyield = (bool)int_val;
468 case IOV_GVAL(IOV_FORCERB):
469 int_val = sd_forcerb;
470 bcopy(&int_val, arg, val_size);
473 case IOV_SVAL(IOV_FORCERB):
474 sd_forcerb = (bool)int_val;
476 #endif /* BCMSDYIELD */
478 case IOV_GVAL(IOV_BLOCKSIZE):
479 if ((uint32)int_val > si->num_funcs) {
480 bcmerror = BCME_BADARG;
483 int_val = (int32)si->client_block_size[int_val];
484 bcopy(&int_val, arg, val_size);
487 case IOV_SVAL(IOV_BLOCKSIZE):
489 uint func = ((uint32)int_val >> 16);
490 uint blksize = (uint16)int_val;
493 if (func > si->num_funcs) {
494 bcmerror = BCME_BADARG;
499 case 0: maxsize = 32; break;
500 case 1: maxsize = BLOCK_SIZE_4318; break;
501 case 2: maxsize = BLOCK_SIZE_4328; break;
502 default: maxsize = 0;
504 if (blksize > maxsize) {
505 bcmerror = BCME_BADARG;
514 bcmerror = set_client_block_size(si, func, blksize);
519 case IOV_GVAL(IOV_DMA):
520 int_val = (int32)si->sd_dma_mode;
521 bcopy(&int_val, arg, val_size);
524 case IOV_SVAL(IOV_DMA):
525 si->sd_dma_mode = (char)int_val;
526 sdstd_set_dma_mode(si, si->sd_dma_mode);
529 case IOV_GVAL(IOV_USEINTS):
530 int_val = (int32)si->use_client_ints;
531 bcopy(&int_val, arg, val_size);
534 case IOV_SVAL(IOV_USEINTS):
535 si->use_client_ints = (bool)int_val;
536 if (si->use_client_ints)
537 si->intmask |= CLIENT_INTR;
539 si->intmask &= ~CLIENT_INTR;
542 case IOV_GVAL(IOV_DIVISOR):
543 int_val = (uint32)sd_divisor;
544 bcopy(&int_val, arg, val_size);
547 case IOV_SVAL(IOV_DIVISOR):
548 sd_divisor = int_val;
549 if (!sdstd_start_clock(si, (uint16)sd_divisor)) {
550 sd_err(("set clock failed!\n"));
551 bcmerror = BCME_ERROR;
555 case IOV_GVAL(IOV_POWER):
556 int_val = (uint32)sd_power;
557 bcopy(&int_val, arg, val_size);
560 case IOV_SVAL(IOV_POWER):
563 if (sdstd_driver_init(si) != SUCCESS) {
564 sd_err(("set SD Slot power failed!\n"));
565 bcmerror = BCME_ERROR;
567 sd_err(("SD Slot Powered ON.\n"));
572 pwr = SFIELD(pwr, PWR_BUS_EN, 0);
573 sdstd_wreg8(si, SD_PwrCntrl, pwr); /* Set Voltage level */
574 sd_err(("SD Slot Powered OFF.\n"));
578 case IOV_GVAL(IOV_CLOCK):
579 int_val = (uint32)sd_clock;
580 bcopy(&int_val, arg, val_size);
583 case IOV_SVAL(IOV_CLOCK):
586 sd_info(("SD Clock turned ON.\n"));
587 if (!sdstd_start_clock(si, (uint16)sd_divisor)) {
588 sd_err(("sdstd_start_clock failed\n"));
589 bcmerror = BCME_ERROR;
592 /* turn off HC clock */
593 sdstd_wreg16(si, SD_ClockCntrl,
594 sdstd_rreg16(si, SD_ClockCntrl) & ~((uint16)0x4));
596 sd_info(("SD Clock turned OFF.\n"));
600 case IOV_GVAL(IOV_SDMODE):
601 int_val = (uint32)sd_sdmode;
602 bcopy(&int_val, arg, val_size);
605 case IOV_SVAL(IOV_SDMODE):
608 if (!sdstd_bus_width(si, sd_sdmode)) {
609 sd_err(("sdstd_bus_width failed\n"));
610 bcmerror = BCME_ERROR;
614 case IOV_GVAL(IOV_HISPEED):
615 int_val = (uint32)sd_hiok;
616 bcopy(&int_val, arg, val_size);
619 case IOV_SVAL(IOV_HISPEED):
621 bcmerror = sdstd_set_highspeed_mode(si, (bool)sd_hiok);
624 case IOV_GVAL(IOV_NUMINTS):
625 int_val = (int32)si->intrcount;
626 bcopy(&int_val, arg, val_size);
629 case IOV_GVAL(IOV_NUMLOCALINTS):
630 int_val = (int32)si->local_intrcount;
631 bcopy(&int_val, arg, val_size);
634 case IOV_GVAL(IOV_HOSTREG):
636 sdreg_t *sd_ptr = (sdreg_t *)params;
638 if (sd_ptr->offset < SD_SysAddr || sd_ptr->offset > SD_MaxCurCap) {
639 sd_err(("%s: bad offset 0x%x\n", __FUNCTION__, sd_ptr->offset));
640 bcmerror = BCME_BADARG;
644 sd_trace(("%s: rreg%d at offset %d\n", __FUNCTION__,
645 (sd_ptr->offset & 1) ? 8 : ((sd_ptr->offset & 2) ? 16 : 32),
647 if (sd_ptr->offset & 1)
648 int_val = sdstd_rreg8(si, sd_ptr->offset);
649 else if (sd_ptr->offset & 2)
650 int_val = sdstd_rreg16(si, sd_ptr->offset);
652 int_val = sdstd_rreg(si, sd_ptr->offset);
654 bcopy(&int_val, arg, sizeof(int_val));
658 case IOV_SVAL(IOV_HOSTREG):
660 sdreg_t *sd_ptr = (sdreg_t *)params;
662 if (sd_ptr->offset < SD_SysAddr || sd_ptr->offset > SD_MaxCurCap) {
663 sd_err(("%s: bad offset 0x%x\n", __FUNCTION__, sd_ptr->offset));
664 bcmerror = BCME_BADARG;
668 sd_trace(("%s: wreg%d value 0x%08x at offset %d\n", __FUNCTION__, sd_ptr->value,
669 (sd_ptr->offset & 1) ? 8 : ((sd_ptr->offset & 2) ? 16 : 32),
671 if (sd_ptr->offset & 1)
672 sdstd_wreg8(si, sd_ptr->offset, (uint8)sd_ptr->value);
673 else if (sd_ptr->offset & 2)
674 sdstd_wreg16(si, sd_ptr->offset, (uint16)sd_ptr->value);
676 sdstd_wreg(si, sd_ptr->offset, (uint32)sd_ptr->value);
681 case IOV_GVAL(IOV_DEVREG):
683 sdreg_t *sd_ptr = (sdreg_t *)params;
686 if (sdioh_cfg_read(si, sd_ptr->func, sd_ptr->offset, &data)) {
687 bcmerror = BCME_SDIO_ERROR;
692 bcopy(&int_val, arg, sizeof(int_val));
696 case IOV_SVAL(IOV_DEVREG):
698 sdreg_t *sd_ptr = (sdreg_t *)params;
699 uint8 data = (uint8)sd_ptr->value;
701 if (sdioh_cfg_write(si, sd_ptr->func, sd_ptr->offset, &data)) {
702 bcmerror = BCME_SDIO_ERROR;
710 bcmerror = BCME_UNSUPPORTED;
719 sdioh_cfg_read(sdioh_info_t *sd, uint fnc_num, uint32 addr, uint8 *data)
722 /* No lock needed since sdioh_request_byte does locking */
723 status = sdioh_request_byte(sd, SDIOH_READ, fnc_num, addr, data);
728 sdioh_cfg_write(sdioh_info_t *sd, uint fnc_num, uint32 addr, uint8 *data)
730 /* No lock needed since sdioh_request_byte does locking */
732 status = sdioh_request_byte(sd, SDIOH_WRITE, fnc_num, addr, data);
737 sdioh_cis_read(sdioh_info_t *sd, uint func, uint8 *cisd, uint32 length)
744 sd_trace(("%s: Func = %d\n", __FUNCTION__, func));
746 if (!sd->func_cis_ptr[func]) {
748 return SDIOH_API_RC_FAIL;
753 for (count = 0; count < length; count++) {
754 offset = sd->func_cis_ptr[func] + count;
755 if (sdstd_card_regread(sd, 0, offset, 1, &foo)) {
756 sd_err(("%s: regread failed: Can't read CIS\n", __FUNCTION__));
758 return SDIOH_API_RC_FAIL;
760 *cis = (uint8)(foo & 0xff);
764 return SDIOH_API_RC_SUCCESS;
768 sdioh_request_byte(sdioh_info_t *sd, uint rw, uint func, uint regaddr, uint8 *byte)
776 cmd_arg = SFIELD(cmd_arg, CMD52_FUNCTION, func);
777 cmd_arg = SFIELD(cmd_arg, CMD52_REG_ADDR, regaddr);
778 cmd_arg = SFIELD(cmd_arg, CMD52_RW_FLAG, rw == SDIOH_READ ? 0 : 1);
779 cmd_arg = SFIELD(cmd_arg, CMD52_RAW, 0);
780 cmd_arg = SFIELD(cmd_arg, CMD52_DATA, rw == SDIOH_READ ? 0 : *byte);
782 if ((status = sdstd_cmd_issue(sd, USE_DMA(sd), SDIOH_CMD_52, cmd_arg)) != SUCCESS) {
787 sdstd_cmd_getrsp(sd, &rsp5, 1);
788 if (sdstd_rreg16 (sd, SD_ErrorIntrStatus) != 0) {
789 sd_err(("%s: 1: ErrorintrStatus 0x%x\n",
790 __FUNCTION__, sdstd_rreg16(sd, SD_ErrorIntrStatus)));
792 if (GFIELD(rsp5, RSP5_FLAGS) != 0x10)
793 sd_err(("%s: rsp5 flags is 0x%x\t %d\n",
794 __FUNCTION__, GFIELD(rsp5, RSP5_FLAGS), func));
796 if (GFIELD(rsp5, RSP5_STUFF))
797 sd_err(("%s: rsp5 stuff is 0x%x: should be 0\n",
798 __FUNCTION__, GFIELD(rsp5, RSP5_STUFF)));
800 if (rw == SDIOH_READ)
801 *byte = GFIELD(rsp5, RSP5_DATA);
804 return SDIOH_API_RC_SUCCESS;
808 sdioh_request_word(sdioh_info_t *sd, uint cmd_type, uint rw, uint func, uint addr,
809 uint32 *word, uint nbytes)
816 if (rw == SDIOH_READ) {
817 status = sdstd_card_regread(sd, func, addr, nbytes, word);
819 *word = BCMSWAP32(*word);
822 *word = BCMSWAP32(*word);
823 status = sdstd_card_regwrite(sd, func, addr, nbytes, *word);
827 return (status == SUCCESS ? SDIOH_API_RC_SUCCESS : SDIOH_API_RC_FAIL);
831 sdioh_request_buffer(sdioh_info_t *sd, uint pio_dma, uint fix_inc, uint rw, uint func,
832 uint addr, uint reg_width, uint buflen_u, uint8 *buffer, void *pkt)
835 int buflen = (int)buflen_u;
836 bool fifo = (fix_inc == SDIOH_DATA_FIX);
837 uint8 *localbuf = NULL, *tmpbuf = NULL;
839 bool local_blockmode = sd->sd_blockmode;
843 ASSERT(reg_width == 4);
844 ASSERT(buflen_u < (1 << 30));
845 ASSERT(sd->client_block_size[func]);
847 sd_data(("%s: %c len %d r_cnt %d t_cnt %d, pkt @0x%p\n",
848 __FUNCTION__, rw == SDIOH_READ ? 'R' : 'W',
849 buflen_u, sd->r_cnt, sd->t_cnt, pkt));
851 /* Break buffer down into blocksize chunks:
852 * Bytemode: 1 block at a time.
853 * Blockmode: Multiples of blocksizes at a time w/ max of SD_PAGE.
854 * Both: leftovers are handled last (will be sent via bytemode).
857 if (local_blockmode) {
858 /* Max xfer is Page size */
859 len = MIN(SD_PAGE, buflen);
861 /* Round down to a block boundry */
862 if (buflen > sd->client_block_size[func])
863 len = (len/sd->client_block_size[func]) *
864 sd->client_block_size[func];
865 if ((func == SDIO_FUNC_1) && ((len % 4) == 3) && (rw == SDIOH_WRITE)) {
867 sd_err(("%s: Rounding up buffer to mod4 length.\n", __FUNCTION__));
870 if ((localbuf = (uint8 *)MALLOC(sd->osh, len)) == NULL) {
871 sd_err(("out of memory, malloced %d bytes\n",
874 return SDIOH_API_RC_FAIL;
876 bcopy(buffer, localbuf, len);
880 /* Byte mode: One block at a time */
881 len = MIN(sd->client_block_size[func], buflen);
884 if (sdstd_card_buf(sd, rw, func, fifo, addr, len, (uint32 *)buffer) != SUCCESS) {
886 return SDIOH_API_RC_FAIL;
889 if (local_blockmode) {
890 if ((func == SDIO_FUNC_1) && ((tmplen % 4) == 3) && (rw == SDIOH_WRITE)) {
892 MFREE(sd->osh, localbuf, len);
895 sd_err(("%s: Restoring back buffer ptr and len.\n", __FUNCTION__));
905 return SDIOH_API_RC_SUCCESS;
909 int sdstd_abort(sdioh_info_t *sd, uint func)
920 uint16 plain_intstatus;
922 /* Argument is write to F0 (CCCR) IOAbort with function number */
924 cmd_arg = SFIELD(cmd_arg, CMD52_FUNCTION, SDIO_FUNC_0);
925 cmd_arg = SFIELD(cmd_arg, CMD52_REG_ADDR, SDIOD_CCCR_IOABORT);
926 cmd_arg = SFIELD(cmd_arg, CMD52_RW_FLAG, SD_IO_OP_WRITE);
927 cmd_arg = SFIELD(cmd_arg, CMD52_RAW, 0);
928 cmd_arg = SFIELD(cmd_arg, CMD52_DATA, func);
930 /* Command is CMD52 write */
932 cmd_reg = SFIELD(cmd_reg, CMD_RESP_TYPE, RESP_TYPE_48_BUSY);
933 cmd_reg = SFIELD(cmd_reg, CMD_CRC_EN, 1);
934 cmd_reg = SFIELD(cmd_reg, CMD_INDEX_EN, 1);
935 cmd_reg = SFIELD(cmd_reg, CMD_DATA_EN, 0);
936 cmd_reg = SFIELD(cmd_reg, CMD_TYPE, CMD_TYPE_ABORT);
937 cmd_reg = SFIELD(cmd_reg, CMD_INDEX, SDIOH_CMD_52);
939 if (sd->sd_mode == SDIOH_MODE_SPI) {
940 cmd_reg = SFIELD(cmd_reg, CMD_CRC_EN, 0);
941 cmd_reg = SFIELD(cmd_reg, CMD_INDEX_EN, 0);
944 /* Wait for CMD_INHIBIT to go away as per spec section 3.6.1.1 */
945 retries = RETRIES_SMALL;
946 while (GFIELD(sdstd_rreg(sd, SD_PresentState), PRES_CMD_INHIBIT)) {
947 if (retries == RETRIES_SMALL)
948 sd_err(("%s: Waiting for Command Inhibit, state 0x%08x\n",
949 __FUNCTION__, sdstd_rreg(sd, SD_PresentState)));
951 sd_err(("%s: Command Inhibit timeout, state 0x%08x\n",
952 __FUNCTION__, sdstd_rreg(sd, SD_PresentState)));
955 err = BCME_SDIO_ERROR;
960 /* Clear errors from any previous commands */
961 if ((plain_intstatus = sdstd_rreg16(sd, SD_ErrorIntrStatus)) != 0) {
962 sd_err(("abort: clearing errstat 0x%04x\n", plain_intstatus));
963 sdstd_wreg16(sd, SD_ErrorIntrStatus, plain_intstatus);
965 plain_intstatus = sdstd_rreg16(sd, SD_IntrStatus);
966 if (plain_intstatus & ~(SFIELD(0, INTSTAT_CARD_INT, 1))) {
967 sd_err(("abort: intstatus 0x%04x\n", plain_intstatus));
968 if (GFIELD(plain_intstatus, INTSTAT_CMD_COMPLETE)) {
969 sd_err(("SDSTD_ABORT: CMD COMPLETE SET BEFORE COMMAND GIVEN!!!\n"));
971 if (GFIELD(plain_intstatus, INTSTAT_CARD_REMOVAL)) {
972 sd_err(("SDSTD_ABORT: INTSTAT_CARD_REMOVAL\n"));
978 /* Issue the command */
979 sdstd_wreg(sd, SD_Arg0, cmd_arg);
980 sdstd_wreg16(sd, SD_Command, cmd_reg);
982 /* In interrupt mode return, expect later CMD_COMPLETE interrupt */
983 if (!sd->polled_mode)
986 /* Otherwise, wait for the command to complete */
987 retries = RETRIES_LARGE;
989 int_reg = sdstd_rreg16(sd, SD_IntrStatus);
990 } while (--retries &&
991 (GFIELD(int_reg, INTSTAT_ERROR_INT) == 0) &&
992 (GFIELD(int_reg, INTSTAT_CMD_COMPLETE) == 0));
994 /* If command completion fails, do a cmd reset and note the error */
996 sd_err(("%s: CMD_COMPLETE timeout: intr 0x%04x err 0x%04x state 0x%08x\n",
997 __FUNCTION__, int_reg,
998 sdstd_rreg16(sd, SD_ErrorIntrStatus),
999 sdstd_rreg(sd, SD_PresentState)));
1001 sdstd_wreg8(sd, SD_SoftwareReset, SFIELD(0, SW_RESET_CMD, 1));
1002 retries = RETRIES_LARGE;
1004 sd_trace(("%s: waiting for CMD line reset\n", __FUNCTION__));
1005 } while ((GFIELD(sdstd_rreg8(sd, SD_SoftwareReset),
1006 SW_RESET_CMD)) && retries--);
1009 sd_err(("%s: Timeout waiting for CMD line reset\n", __FUNCTION__));
1015 err = BCME_SDIO_ERROR;
1018 /* Clear Command Complete interrupt */
1019 int_reg = SFIELD(0, INTSTAT_CMD_COMPLETE, 1);
1020 sdstd_wreg16(sd, SD_IntrStatus, int_reg);
1022 /* Check for Errors */
1023 if ((plain_intstatus = sdstd_rreg16 (sd, SD_ErrorIntrStatus)) != 0) {
1024 sd_err(("%s: ErrorintrStatus: 0x%x, "
1025 "(intrstatus = 0x%x, present state 0x%x) clearing\n",
1026 __FUNCTION__, plain_intstatus,
1027 sdstd_rreg16(sd, SD_IntrStatus),
1028 sdstd_rreg(sd, SD_PresentState)));
1030 sdstd_wreg16(sd, SD_ErrorIntrStatus, plain_intstatus);
1032 sdstd_wreg8(sd, SD_SoftwareReset, SFIELD(0, SW_RESET_DAT, 1));
1033 retries = RETRIES_LARGE;
1035 sd_trace(("%s: waiting for DAT line reset\n", __FUNCTION__));
1036 } while ((GFIELD(sdstd_rreg8(sd, SD_SoftwareReset),
1037 SW_RESET_DAT)) && retries--);
1040 sd_err(("%s: Timeout waiting for DAT line reset\n", __FUNCTION__));
1046 /* ABORT is dataless, only cmd errs count */
1047 if (plain_intstatus & ERRINT_CMD_ERRS)
1048 err = BCME_SDIO_ERROR;
1051 /* If command failed don't bother looking at response */
1055 /* Otherwise, check the response */
1056 sdstd_cmd_getrsp(sd, &rsp5, 1);
1057 rflags = GFIELD(rsp5, RSP5_FLAGS);
1059 if (rflags & SD_RSP_R5_ERRBITS) {
1060 sd_err(("%s: R5 flags include errbits: 0x%02x\n", __FUNCTION__, rflags));
1062 /* The CRC error flag applies to the previous command */
1063 if (rflags & (SD_RSP_R5_ERRBITS & ~SD_RSP_R5_COM_CRC_ERROR)) {
1064 err = BCME_SDIO_ERROR;
1069 if (((rflags & (SD_RSP_R5_IO_CURRENTSTATE0 | SD_RSP_R5_IO_CURRENTSTATE1)) != 0x10) &&
1070 ((rflags & (SD_RSP_R5_IO_CURRENTSTATE0 | SD_RSP_R5_IO_CURRENTSTATE1)) != 0x20)) {
1071 sd_err(("%s: R5 flags has bad state: 0x%02x\n", __FUNCTION__, rflags));
1072 err = BCME_SDIO_ERROR;
1076 if (GFIELD(rsp5, RSP5_STUFF)) {
1077 sd_err(("%s: rsp5 stuff is 0x%x: should be 0\n",
1078 __FUNCTION__, GFIELD(rsp5, RSP5_STUFF)));
1079 err = BCME_SDIO_ERROR;
1084 if (err == BCME_NODEVICE)
1087 sdstd_wreg8(sd, SD_SoftwareReset,
1088 SFIELD(SFIELD(0, SW_RESET_DAT, 1), SW_RESET_CMD, 1));
1090 retries = RETRIES_LARGE;
1092 rflags = sdstd_rreg8(sd, SD_SoftwareReset);
1093 if (!GFIELD(rflags, SW_RESET_DAT) && !GFIELD(rflags, SW_RESET_CMD))
1095 } while (--retries);
1098 sd_err(("%s: Timeout waiting for DAT/CMD reset: 0x%02x\n",
1099 __FUNCTION__, rflags));
1100 err = BCME_SDIO_ERROR;
1107 sdioh_abort(sdioh_info_t *sd, uint fnum)
1112 ret = sdstd_abort(sd, fnum);
1119 sdioh_start(sdioh_info_t *sd, int stage)
1125 sdioh_stop(sdioh_info_t *sd)
1131 sdstd_check_errs(sdioh_info_t *sdioh_info, uint32 cmd, uint32 arg)
1137 /* If no errors, we're done */
1138 if ((regval = sdstd_rreg16(sdioh_info, SD_ErrorIntrStatus)) == 0)
1141 sd_info(("%s: ErrorIntrStatus 0x%04x (clearing), IntrStatus 0x%04x PresentState 0x%08x\n",
1142 __FUNCTION__, regval, sdstd_rreg16(sdioh_info, SD_IntrStatus),
1143 sdstd_rreg(sdioh_info, SD_PresentState)));
1144 sdstd_wreg16(sdioh_info, SD_ErrorIntrStatus, regval);
1146 /* On command error, issue CMD reset */
1147 if (regval & ERRINT_CMD_ERRS) {
1148 sd_trace(("%s: issuing CMD reset\n", __FUNCTION__));
1149 sdstd_wreg8(sdioh_info, SD_SoftwareReset, SFIELD(0, SW_RESET_CMD, 1));
1150 for (retries = RETRIES_LARGE; retries; retries--)
1151 if (!(GFIELD(sdstd_rreg8(sdioh_info, SD_SoftwareReset), SW_RESET_CMD)))
1154 sd_err(("%s: Timeout waiting for CMD line reset\n", __FUNCTION__));
1158 /* On data error, issue DAT reset */
1159 if (regval & ERRINT_DATA_ERRS) {
1160 sd_trace(("%s: issuing DAT reset\n", __FUNCTION__));
1161 sdstd_wreg8(sdioh_info, SD_SoftwareReset, SFIELD(0, SW_RESET_DAT, 1));
1162 for (retries = RETRIES_LARGE; retries; retries--)
1163 if (!(GFIELD(sdstd_rreg8(sdioh_info, SD_SoftwareReset), SW_RESET_DAT)))
1166 sd_err(("%s: Timeout waiting for DAT line reset\n", __FUNCTION__));
1170 /* For an IO command (CMD52 or CMD53) issue an abort to the appropriate function */
1171 if (cmd == SDIOH_CMD_53)
1172 function = GFIELD(arg, CMD53_FUNCTION);
1173 else if (cmd == SDIOH_CMD_52)
1174 function = GFIELD(arg, CMD52_FUNCTION);
1176 sd_trace(("%s: requesting abort for function %d after cmd %d\n",
1177 __FUNCTION__, function, cmd));
1178 sdstd_abort(sdioh_info, function);
1190 * Private/Static work routines
1193 sdstd_reset(sdioh_info_t *sd, bool host_reset, bool client_reset)
1195 int retries = RETRIES_LARGE;
1202 /* Reset client card */
1203 if (client_reset && (sd->adapter_slot != -1)) {
1204 if (sdstd_card_regwrite(sd, 0, SDIOD_CCCR_IOABORT, 1, 0x8) != SUCCESS)
1205 sd_err(("%s: Cannot write to card reg 0x%x\n",
1206 __FUNCTION__, SDIOD_CCCR_IOABORT));
1211 /* Reset host controller */
1213 regval = SFIELD(0, SW_RESET_ALL, 1);
1214 sdstd_wreg8(sd, SD_SoftwareReset, regval);
1216 sd_trace(("%s: waiting for reset\n", __FUNCTION__));
1217 } while ((sdstd_rreg8(sd, SD_SoftwareReset) & regval) && retries--);
1220 sd_err(("%s: Timeout waiting for host reset\n", __FUNCTION__));
1225 /* A reset should reset bus back to 1 bit mode */
1226 sd->sd_mode = SDIOH_MODE_SD1;
1227 sdstd_set_dma_mode(sd, sd->sd_dma_mode);
1233 /* Disable device interrupt */
1235 sdstd_devintr_off(sdioh_info_t *sd)
1237 sd_trace(("%s: %d\n", __FUNCTION__, sd->use_client_ints));
1238 if (sd->use_client_ints) {
1239 sd->intmask &= ~CLIENT_INTR;
1240 sdstd_wreg16(sd, SD_IntrSignalEnable, sd->intmask);
1241 sdstd_rreg16(sd, SD_IntrSignalEnable); /* Sync readback */
1245 /* Enable device interrupt */
1247 sdstd_devintr_on(sdioh_info_t *sd)
1249 ASSERT(sd->lockcount == 0);
1250 sd_trace(("%s: %d\n", __FUNCTION__, sd->use_client_ints));
1251 if (sd->use_client_ints) {
1252 uint16 status = sdstd_rreg16(sd, SD_IntrStatusEnable);
1253 sdstd_wreg16(sd, SD_IntrStatusEnable, SFIELD(status, INTSTAT_CARD_INT, 0));
1254 sdstd_wreg16(sd, SD_IntrStatusEnable, status);
1256 sd->intmask |= CLIENT_INTR;
1257 sdstd_wreg16(sd, SD_IntrSignalEnable, sd->intmask);
1258 sdstd_rreg16(sd, SD_IntrSignalEnable); /* Sync readback */
1263 /* Enable/disable other interrupts */
1265 sdstd_intrs_on(sdioh_info_t *sd, uint16 norm, uint16 err)
1268 norm = SFIELD(norm, INTSTAT_ERROR_INT, 1);
1269 sdstd_wreg16(sd, SD_ErrorIntrSignalEnable, err);
1272 sd->intmask |= norm;
1273 sdstd_wreg16(sd, SD_IntrSignalEnable, sd->intmask);
1275 sdstd_rreg16(sd, SD_IntrSignalEnable); /* Sync readback */
1279 sdstd_intrs_off(sdioh_info_t *sd, uint16 norm, uint16 err)
1282 norm = SFIELD(norm, INTSTAT_ERROR_INT, 1);
1283 sdstd_wreg16(sd, SD_ErrorIntrSignalEnable, 0);
1286 sd->intmask &= ~norm;
1287 sdstd_wreg16(sd, SD_IntrSignalEnable, sd->intmask);
1289 sdstd_rreg16(sd, SD_IntrSignalEnable); /* Sync readback */
1291 #endif /* BCMSDYIELD */
1294 sdstd_host_init(sdioh_info_t *sd)
1296 int num_slots, full_slot;
1300 int slot, first_bar = 0;
1301 bool detect_slots = FALSE;
1304 /* Check for Arasan ID */
1305 if ((OSL_PCI_READ_CONFIG(sd->osh, PCI_CFG_VID, 4) & 0xFFFF) == VENDOR_SI_IMAGE) {
1306 sd_info(("%s: Found Arasan Standard SDIO Host Controller\n", __FUNCTION__));
1307 sd->controller_type = SDIOH_TYPE_ARASAN_HDK;
1308 detect_slots = TRUE;
1309 } else if ((OSL_PCI_READ_CONFIG(sd->osh, PCI_CFG_VID, 4) & 0xFFFF) == VENDOR_BROADCOM) {
1310 sd_info(("%s: Found Broadcom 27xx Standard SDIO Host Controller\n", __FUNCTION__));
1311 sd->controller_type = SDIOH_TYPE_BCM27XX;
1312 detect_slots = FALSE;
1313 } else if ((OSL_PCI_READ_CONFIG(sd->osh, PCI_CFG_VID, 4) & 0xFFFF) == VENDOR_TI) {
1314 sd_info(("%s: Found TI PCIxx21 Standard SDIO Host Controller\n", __FUNCTION__));
1315 sd->controller_type = SDIOH_TYPE_TI_PCIXX21;
1316 detect_slots = TRUE;
1317 } else if ((OSL_PCI_READ_CONFIG(sd->osh, PCI_CFG_VID, 4) & 0xFFFF) == VENDOR_RICOH) {
1318 sd_info(("%s: Ricoh Co Ltd R5C822 SD/SDIO/MMC/MS/MSPro Host Adapter\n",
1320 sd->controller_type = SDIOH_TYPE_RICOH_R5C822;
1321 detect_slots = TRUE;
1322 } else if ((OSL_PCI_READ_CONFIG(sd->osh, PCI_CFG_VID, 4) & 0xFFFF) == VENDOR_JMICRON) {
1323 sd_info(("%s: JMicron Standard SDIO Host Controller\n",
1325 sd->controller_type = SDIOH_TYPE_JMICRON;
1326 detect_slots = TRUE;
1332 * Determine num of slots
1336 first_bar = OSL_PCI_READ_CONFIG(sd->osh, SD_SlotInfo, 4) & 0x7;
1337 num_slots = (OSL_PCI_READ_CONFIG(sd->osh, SD_SlotInfo, 4) & 0xff) >> 4;
1339 num_slots++; /* map bits to num slots according to spec */
1341 if (OSL_PCI_READ_CONFIG(sd->osh, PCI_CFG_VID, 4) ==
1342 ((SDIOH_FPGA_ID << 16) | VENDOR_BROADCOM)) {
1343 sd_err(("%s: Found Broadcom Standard SDIO Host Controller FPGA\n", __FUNCTION__));
1344 /* Set BAR0 Window to SDIOSTH core */
1345 OSL_PCI_WRITE_CONFIG(sd->osh, PCI_BAR0_WIN, 4, 0x18001000);
1347 /* Set defaults particular to this controller. */
1348 detect_slots = TRUE;
1352 /* Controller supports ADMA2, so turn it on here. */
1353 sd->sd_dma_mode = DMA_MODE_ADMA2;
1356 /* Map in each slot on the board and query it to see if a
1357 * card is inserted. Use the first populated slot found.
1359 if (sd->mem_space) {
1360 sdstd_reg_unmap(sd->osh, (uintptr)sd->mem_space, SDIOH_REG_WINSZ);
1361 sd->mem_space = NULL;
1366 for (slot = 0; slot < num_slots; slot++) {
1367 bar = OSL_PCI_READ_CONFIG(sd->osh, PCI_CFG_BAR0 + (4*(slot + first_bar)), 4);
1368 sd->mem_space = (volatile char *)sdstd_reg_map(sd->osh,
1369 (uintptr)bar, SDIOH_REG_WINSZ);
1371 sd->adapter_slot = -1;
1374 card_ins = GFIELD(sdstd_rreg(sd, SD_PresentState), PRES_CARD_PRESENT);
1380 sd_info(("%s: SDIO slot %d: Full\n", __FUNCTION__, slot));
1384 sd_info(("%s: SDIO slot %d: Empty\n", __FUNCTION__, slot));
1387 if (sd->mem_space) {
1388 sdstd_reg_unmap(sd->osh, (uintptr)sd->mem_space, SDIOH_REG_WINSZ);
1389 sd->mem_space = NULL;
1393 if (full_slot < 0) {
1394 sd_err(("No slots on SDIO controller are populated\n"));
1398 bar = OSL_PCI_READ_CONFIG(sd->osh, PCI_CFG_BAR0 + (4*(full_slot + first_bar)), 4);
1399 sd->mem_space = (volatile char *)sdstd_reg_map(sd->osh, (uintptr)bar, SDIOH_REG_WINSZ);
1401 sd_err(("Using slot %d at BAR%d [0x%08x] mem_space 0x%p\n",
1403 (full_slot + first_bar),
1404 OSL_PCI_READ_CONFIG(sd->osh, PCI_CFG_BAR0 + (4*(full_slot + first_bar)), 4),
1408 sd->adapter_slot = full_slot;
1410 sd->version = sdstd_rreg16(sd, SD_HostControllerVersion) & 0xFF;
1411 switch (sd->version) {
1413 sd_err(("Host Controller version 1.0, Vendor Revision: 0x%02x\n",
1414 sdstd_rreg16(sd, SD_HostControllerVersion) >> 8));
1418 sd_err(("Host Controller version 2.0, Vendor Revision: 0x%02x\n",
1419 sdstd_rreg16(sd, SD_HostControllerVersion) >> 8));
1422 sd_err(("%s: Host Controller version 0x%02x not supported.\n",
1423 __FUNCTION__, sd->version));
1427 sd->caps = sdstd_rreg(sd, SD_Capabilities); /* Cache this for later use */
1428 sd->curr_caps = sdstd_rreg(sd, SD_MaxCurCap);
1430 sdstd_set_dma_mode(sd, sd->sd_dma_mode);
1433 sdstd_reset(sd, 1, 0);
1435 /* Read SD4/SD1 mode */
1436 if ((reg8 = sdstd_rreg8(sd, SD_HostCntrl))) {
1437 if (reg8 & SD4_MODE) {
1438 sd_err(("%s: Host cntrlr already in 4 bit mode: 0x%x\n",
1439 __FUNCTION__, reg8));
1443 /* Default power on mode is SD1 */
1444 sd->sd_mode = SDIOH_MODE_SD1;
1445 sd->polled_mode = TRUE;
1446 sd->host_init_done = TRUE;
1447 sd->card_init_done = FALSE;
1448 sd->adapter_slot = full_slot;
1452 #define CMD5_RETRIES 200
1454 get_ocr(sdioh_info_t *sd, uint32 *cmd_arg, uint32 *cmd_rsp)
1456 int retries, status;
1458 /* Get the Card's Operation Condition. Occasionally the board
1459 * takes a while to become ready
1461 retries = CMD5_RETRIES;
1464 if ((status = sdstd_cmd_issue(sd, USE_DMA(sd), SDIOH_CMD_5, *cmd_arg))
1466 sd_err(("%s: CMD5 failed\n", __FUNCTION__));
1469 sdstd_cmd_getrsp(sd, cmd_rsp, 1);
1470 if (!GFIELD(*cmd_rsp, RSP4_CARD_READY))
1471 sd_trace(("%s: Waiting for card to become ready\n", __FUNCTION__));
1472 } while ((!GFIELD(*cmd_rsp, RSP4_CARD_READY)) && --retries);
1480 sdstd_client_init(sdioh_info_t *sd)
1482 uint32 cmd_arg, cmd_rsp;
1487 sd_trace(("%s: Powering up slot %d\n", __FUNCTION__, sd->adapter_slot));
1489 /* Clear any pending ints */
1490 sdstd_wreg16(sd, SD_IntrStatus, 0x1ff);
1491 sdstd_wreg16(sd, SD_ErrorIntrStatus, 0x0fff);
1493 /* Enable both Normal and Error Status. This does not enable
1494 * interrupts, it only enables the status bits to
1497 sdstd_wreg16(sd, SD_IntrStatusEnable, 0x1ff);
1498 sdstd_wreg16(sd, SD_ErrorIntrStatusEnable, 0xffff);
1500 sdstd_wreg16(sd, SD_IntrSignalEnable, 0); /* Disable ints for now. */
1502 /* Start at ~400KHz clock rate for initialization */
1503 if (!sdstd_start_clock(sd, 128)) {
1504 sd_err(("sdstd_start_clock failed\n"));
1507 if (!sdstd_start_power(sd)) {
1508 sd_err(("sdstd_start_power failed\n"));
1512 if (sd->num_funcs == 0) {
1513 sd_err(("%s: No IO funcs!\n", __FUNCTION__));
1517 /* In SPI mode, issue CMD0 first */
1518 if (sd->sd_mode == SDIOH_MODE_SPI) {
1520 if ((status = sdstd_cmd_issue(sd, USE_DMA(sd), SDIOH_CMD_0, cmd_arg))
1522 sd_err(("BCMSDIOH: cardinit: CMD0 failed!\n"));
1527 if (sd->sd_mode != SDIOH_MODE_SPI) {
1530 /* Card is operational. Ask it to send an RCA */
1532 if ((status = sdstd_cmd_issue(sd, USE_DMA(sd), SDIOH_CMD_3, cmd_arg))
1534 sd_err(("%s: CMD3 failed!\n", __FUNCTION__));
1538 /* Verify the card status returned with the cmd response */
1539 sdstd_cmd_getrsp(sd, &cmd_rsp, 1);
1540 rsp6_status = GFIELD(cmd_rsp, RSP6_STATUS);
1541 if (GFIELD(rsp6_status, RSP6STAT_COM_CRC_ERROR) ||
1542 GFIELD(rsp6_status, RSP6STAT_ILLEGAL_CMD) ||
1543 GFIELD(rsp6_status, RSP6STAT_ERROR)) {
1544 sd_err(("%s: CMD3 response error. Response = 0x%x!\n",
1545 __FUNCTION__, rsp6_status));
1549 /* Save the Card's RCA */
1550 sd->card_rca = GFIELD(cmd_rsp, RSP6_IO_RCA);
1551 sd_info(("RCA is 0x%x\n", sd->card_rca));
1554 sd_err(("raw status is 0x%x\n", rsp6_status));
1556 /* Select the card */
1557 cmd_arg = SFIELD(0, CMD7_RCA, sd->card_rca);
1558 if ((status = sdstd_cmd_issue(sd, USE_DMA(sd), SDIOH_CMD_7, cmd_arg))
1560 sd_err(("%s: CMD7 failed!\n", __FUNCTION__));
1563 sdstd_cmd_getrsp(sd, &cmd_rsp, 1);
1564 if (cmd_rsp != SDIOH_CMD7_EXP_STATUS) {
1565 sd_err(("%s: CMD7 response error. Response = 0x%x!\n",
1566 __FUNCTION__, cmd_rsp));
1571 sdstd_card_enablefuncs(sd);
1573 if (!sdstd_bus_width(sd, sd_sdmode)) {
1574 sd_err(("sdstd_bus_width failed\n"));
1578 set_client_block_size(sd, 1, BLOCK_SIZE_4318);
1579 fn_ints = INTR_CTL_FUNC1_EN;
1581 if (sd->num_funcs >= 2) {
1582 set_client_block_size(sd, 2, sd_f2_blocksize /* BLOCK_SIZE_4328 */);
1583 fn_ints |= INTR_CTL_FUNC2_EN;
1586 /* Enable/Disable Client interrupts */
1587 /* Turn on here but disable at host controller? */
1588 if (sdstd_card_regwrite(sd, 0, SDIOD_CCCR_INTEN, 1,
1589 (fn_ints | INTR_CTL_MASTER_EN)) != SUCCESS) {
1590 sd_err(("%s: Could not enable ints in CCCR\n", __FUNCTION__));
1594 /* Switch to High-speed clocking mode if both host and device support it */
1595 sdstd_set_highspeed_mode(sd, (bool)sd_hiok);
1597 /* After configuring for High-Speed mode, set the desired clock rate. */
1598 if (!sdstd_start_clock(sd, (uint16)sd_divisor)) {
1599 sd_err(("sdstd_start_clock failed\n"));
1603 sd->card_init_done = TRUE;
1609 sdstd_set_highspeed_mode(sdioh_info_t *sd, bool HSMode)
1615 reg8 = sdstd_rreg8(sd, SD_HostCntrl);
1618 if (HSMode == TRUE) {
1619 if (sd_hiok && (GFIELD(sd->caps, CAP_HIGHSPEED)) == 0) {
1620 sd_err(("Host Controller does not support hi-speed mode.\n"));
1624 sd_info(("Attempting to enable High-Speed mode.\n"));
1626 if ((status = sdstd_card_regread(sd, 0, SDIOD_CCCR_SPEED_CONTROL,
1627 1, ®data)) != SUCCESS) {
1628 return BCME_SDIO_ERROR;
1630 if (regdata & SDIO_SPEED_SHS) {
1631 sd_info(("Device supports High-Speed mode.\n"));
1633 regdata |= SDIO_SPEED_EHS;
1635 sd_info(("Writing %08x to Card at %08x\n",
1636 regdata, SDIOD_CCCR_SPEED_CONTROL));
1637 if ((status = sdstd_card_regwrite(sd, 0, SDIOD_CCCR_SPEED_CONTROL,
1638 1, regdata)) != BCME_OK) {
1639 return BCME_SDIO_ERROR;
1642 if ((status = sdstd_card_regread(sd, 0, SDIOD_CCCR_SPEED_CONTROL,
1643 1, ®data)) != BCME_OK) {
1644 return BCME_SDIO_ERROR;
1647 sd_info(("Read %08x to Card at %08x\n", regdata, SDIOD_CCCR_SPEED_CONTROL));
1649 reg8 = SFIELD(reg8, HOST_HI_SPEED_EN, 1);
1651 sd_err(("High-speed clocking mode enabled.\n"));
1654 sd_err(("Device does not support High-Speed Mode.\n"));
1655 reg8 = SFIELD(reg8, HOST_HI_SPEED_EN, 0);
1658 /* Force off device bit */
1659 if ((status = sdstd_card_regread(sd, 0, SDIOD_CCCR_SPEED_CONTROL,
1660 1, ®data)) != BCME_OK) {
1663 if (regdata & SDIO_SPEED_EHS) {
1664 regdata &= ~SDIO_SPEED_EHS;
1665 if ((status = sdstd_card_regwrite(sd, 0, SDIOD_CCCR_SPEED_CONTROL,
1666 1, regdata)) != BCME_OK) {
1671 sd_err(("High-speed clocking mode disabled.\n"));
1672 reg8 = SFIELD(reg8, HOST_HI_SPEED_EN, 0);
1675 sdstd_wreg8(sd, SD_HostCntrl, reg8);
1681 * If dma_mode == DMA_MODE_AUTO, pick the "best" mode.
1682 * Otherwise, pick the selected mode if supported.
1683 * If not supported, use PIO mode.
1686 sdstd_set_dma_mode(sdioh_info_t *sd, int8 dma_mode)
1688 uint8 reg8, dma_sel_bits = SDIOH_SDMA_MODE;
1689 int8 prev_dma_mode = sd->sd_dma_mode;
1691 switch (prev_dma_mode) {
1693 sd_dma(("%s: Selecting best DMA mode supported by controller.\n",
1695 if (GFIELD(sd->caps, CAP_ADMA2)) {
1696 sd->sd_dma_mode = DMA_MODE_ADMA2;
1697 dma_sel_bits = SDIOH_ADMA2_MODE;
1698 } else if (GFIELD(sd->caps, CAP_ADMA1)) {
1699 sd->sd_dma_mode = DMA_MODE_ADMA1;
1700 dma_sel_bits = SDIOH_ADMA1_MODE;
1701 } else if (GFIELD(sd->caps, CAP_DMA)) {
1702 sd->sd_dma_mode = DMA_MODE_SDMA;
1704 sd->sd_dma_mode = DMA_MODE_NONE;
1708 sd->sd_dma_mode = DMA_MODE_NONE;
1711 if (GFIELD(sd->caps, CAP_DMA)) {
1712 sd->sd_dma_mode = DMA_MODE_SDMA;
1714 sd_err(("%s: SDMA not supported by controller.\n", __FUNCTION__));
1715 sd->sd_dma_mode = DMA_MODE_NONE;
1718 case DMA_MODE_ADMA1:
1719 if (GFIELD(sd->caps, CAP_ADMA1)) {
1720 sd->sd_dma_mode = DMA_MODE_ADMA1;
1721 dma_sel_bits = SDIOH_ADMA1_MODE;
1723 sd_err(("%s: ADMA1 not supported by controller.\n", __FUNCTION__));
1724 sd->sd_dma_mode = DMA_MODE_NONE;
1727 case DMA_MODE_ADMA2:
1728 if (GFIELD(sd->caps, CAP_ADMA2)) {
1729 sd->sd_dma_mode = DMA_MODE_ADMA2;
1730 dma_sel_bits = SDIOH_ADMA2_MODE;
1732 sd_err(("%s: ADMA2 not supported by controller.\n", __FUNCTION__));
1733 sd->sd_dma_mode = DMA_MODE_NONE;
1736 case DMA_MODE_ADMA2_64:
1737 sd_err(("%s: 64b ADMA2 not supported by driver.\n", __FUNCTION__));
1738 sd->sd_dma_mode = DMA_MODE_NONE;
1741 sd_err(("%s: Unsupported DMA Mode %d requested.\n", __FUNCTION__,
1743 sd->sd_dma_mode = DMA_MODE_NONE;
1747 /* clear SysAddr, only used for SDMA */
1748 sdstd_wreg(sd, SD_SysAddr, 0);
1750 sd_err(("%s: %s mode selected.\n", __FUNCTION__, dma_mode_description[sd->sd_dma_mode]));
1752 reg8 = sdstd_rreg8(sd, SD_HostCntrl);
1753 reg8 = SFIELD(reg8, HOST_DMA_SEL, dma_sel_bits);
1754 sdstd_wreg8(sd, SD_HostCntrl, reg8);
1755 sd_dma(("%s: SD_HostCntrl=0x%02x\n", __FUNCTION__, reg8));
1762 sdstd_start_clock(sdioh_info_t *sd, uint16 new_sd_divisor)
1767 /* turn off HC clock */
1768 sdstd_wreg16(sd, SD_ClockCntrl,
1769 sdstd_rreg16(sd, SD_ClockCntrl) & ~((uint16)0x4)); /* Disable the HC clock */
1773 divisor = (new_sd_divisor >> 1) << 8;
1775 sd_info(("Clock control is 0x%x\n", sdstd_rreg16(sd, SD_ClockCntrl)));
1776 sdstd_mod_reg16(sd, SD_ClockCntrl, 0xff00, divisor);
1777 sd_info(("%s: Using clock divisor of %d (regval 0x%04x)\n", __FUNCTION__,
1778 new_sd_divisor, divisor));
1780 sd_info(("Primary Clock Freq = %d MHz\n", GFIELD(sd->caps, CAP_TO_CLKFREQ)));
1782 if (GFIELD(sd->caps, CAP_TO_CLKFREQ) == 50) {
1783 sd_info(("%s: Resulting SDIO clock is %d %s\n", __FUNCTION__,
1784 ((50 % new_sd_divisor) ? (50000 / new_sd_divisor) : (50 / new_sd_divisor)),
1785 ((50 % new_sd_divisor) ? "KHz" : "MHz")));
1786 } else if (GFIELD(sd->caps, CAP_TO_CLKFREQ) == 48) {
1787 sd_info(("%s: Resulting SDIO clock is %d %s\n", __FUNCTION__,
1788 ((48 % new_sd_divisor) ? (48000 / new_sd_divisor) : (48 / new_sd_divisor)),
1789 ((48 % new_sd_divisor) ? "KHz" : "MHz")));
1790 } else if (GFIELD(sd->caps, CAP_TO_CLKFREQ) == 33) {
1791 sd_info(("%s: Resulting SDIO clock is %d %s\n", __FUNCTION__,
1792 ((33 % new_sd_divisor) ? (33000 / new_sd_divisor) : (33 / new_sd_divisor)),
1793 ((33 % new_sd_divisor) ? "KHz" : "MHz")));
1795 } else if (sd->controller_type == SDIOH_TYPE_BCM27XX) {
1797 sd_err(("Need to determine divisor for %d MHz clocks\n",
1798 GFIELD(sd->caps, CAP_TO_CLKFREQ)));
1799 sd_err(("Consult SD Host Controller Spec: Clock Control Register\n"));
1803 sdstd_or_reg16(sd, SD_ClockCntrl, 0x1); /* Enable the clock */
1805 /* Wait for clock to stabilize */
1806 rc = (sdstd_rreg16(sd, SD_ClockCntrl) & 2);
1810 sd_info(("Waiting for clock to become stable 0x%x\n", rc));
1811 rc = (sdstd_rreg16(sd, SD_ClockCntrl) & 2);
1813 if (count > 10000) {
1814 sd_err(("%s:Clocks failed to stabilize after %u attempts",
1815 __FUNCTION__, count));
1820 sdstd_or_reg16(sd, SD_ClockCntrl, 0x4);
1822 /* Set timeout control (adjust default value based on divisor).
1823 * Disabling timeout interrupts during setting is advised by host spec.
1830 divisor = new_sd_divisor;
1832 while (toval && !(divisor & 1)) {
1837 regdata = sdstd_rreg16(sd, SD_ErrorIntrStatusEnable);
1838 sdstd_wreg16(sd, SD_ErrorIntrStatusEnable, (regdata & ~ERRINT_DATA_TIMEOUT_BIT));
1839 sdstd_wreg8(sd, SD_TimeoutCntrl, (uint8)toval);
1840 sdstd_wreg16(sd, SD_ErrorIntrStatusEnable, regdata);
1845 sd_info(("Final Clock control is 0x%x\n", sdstd_rreg16(sd, SD_ClockCntrl)));
1851 sdstd_start_power(sdioh_info_t *sd)
1861 if (GFIELD(sd->caps, CAP_VOLT_1_8)) {
1865 if (GFIELD(sd->caps, CAP_VOLT_3_0)) {
1869 if (GFIELD(sd->caps, CAP_VOLT_3_3)) {
1874 pwr = SFIELD(pwr, PWR_VOLTS, volts);
1875 pwr = SFIELD(pwr, PWR_BUS_EN, 1);
1876 sdstd_wreg8(sd, SD_PwrCntrl, pwr); /* Set Voltage level */
1877 sd_info(("Setting Bus Power to %s Volts\n", s));
1879 /* Wait for power to stabilize, Dongle takes longer than NIC. */
1882 /* Get the Card's Operation Condition. Occasionally the board
1883 * takes a while to become ready
1887 if (get_ocr(sd, &cmd_arg, &cmd_rsp) != SUCCESS) {
1888 sd_err(("%s: Failed to get OCR bailing\n", __FUNCTION__));
1889 sdstd_reset(sd, 0, 1);
1893 sd_info(("mem_present = %d\n", GFIELD(cmd_rsp, RSP4_MEM_PRESENT)));
1894 sd_info(("num_funcs = %d\n", GFIELD(cmd_rsp, RSP4_NUM_FUNCS)));
1895 sd_info(("card_ready = %d\n", GFIELD(cmd_rsp, RSP4_CARD_READY)));
1896 sd_info(("OCR = 0x%x\n", GFIELD(cmd_rsp, RSP4_IO_OCR)));
1898 /* Verify that the card supports I/O mode */
1899 if (GFIELD(cmd_rsp, RSP4_NUM_FUNCS) == 0) {
1900 sd_err(("%s: Card does not support I/O\n", __FUNCTION__));
1903 sd->num_funcs = GFIELD(cmd_rsp, RSP4_NUM_FUNCS);
1905 /* Examine voltage: Arasan only supports 3.3 volts,
1906 * so look for 3.2-3.3 Volts and also 3.3-3.4 volts.
1909 if ((GFIELD(cmd_rsp, RSP4_IO_OCR) & (0x3 << 20)) == 0) {
1910 sd_err(("This client does not support 3.3 volts!\n"));
1913 sd_info(("Leaving bus power at 3.3 Volts\n"));
1915 cmd_arg = SFIELD(0, CMD5_OCR, 0xfff000);
1917 get_ocr(sd, &cmd_arg, &cmd_rsp);
1918 sd_info(("OCR = 0x%x\n", GFIELD(cmd_rsp, RSP4_IO_OCR)));
1923 sdstd_bus_width(sdioh_info_t *sd, int new_mode)
1929 sd_trace(("%s\n", __FUNCTION__));
1930 if (sd->sd_mode == new_mode) {
1931 sd_info(("%s: Already at width %d\n", __FUNCTION__, new_mode));
1932 /* Could exit, but continue just in case... */
1935 /* Set client side via reg 0x7 in CCCR */
1936 if ((status = sdstd_card_regread (sd, 0, SDIOD_CCCR_BICTRL, 1, ®data)) != SUCCESS)
1937 return (bool)status;
1938 regdata &= ~BUS_SD_DATA_WIDTH_MASK;
1939 if (new_mode == SDIOH_MODE_SD4) {
1940 sd_info(("Changing to SD4 Mode\n"));
1941 regdata |= SD4_MODE;
1942 } else if (new_mode == SDIOH_MODE_SD1) {
1943 sd_info(("Changing to SD1 Mode\n"));
1945 sd_err(("SPI Mode not supported by Standard Host Controller\n"));
1948 if ((status = sdstd_card_regwrite (sd, 0, SDIOD_CCCR_BICTRL, 1, regdata)) != SUCCESS)
1949 return (bool)status;
1951 /* Set host side via Host reg */
1952 reg8 = sdstd_rreg8(sd, SD_HostCntrl) & ~SD4_MODE;
1953 if (new_mode == SDIOH_MODE_SD4)
1955 sdstd_wreg8(sd, SD_HostCntrl, reg8);
1957 sd->sd_mode = new_mode;
1963 sdstd_driver_init(sdioh_info_t *sd)
1965 sd_trace(("%s\n", __FUNCTION__));
1966 if ((sdstd_host_init(sd)) != SUCCESS) {
1970 if (sdstd_client_init(sd) != SUCCESS) {
1978 sdstd_get_cisaddr(sdioh_info_t *sd, uint32 regaddr)
1980 /* read 24 bits and return valid 17 bit addr */
1982 uint32 scratch, regdata;
1983 uint8 *ptr = (uint8 *)&scratch;
1984 for (i = 0; i < 3; i++) {
1985 if ((sdstd_card_regread (sd, 0, regaddr, 1, ®data)) != SUCCESS)
1986 sd_err(("%s: Can't read!\n", __FUNCTION__));
1988 *ptr++ = (uint8) regdata;
1991 /* Only the lower 17-bits are valid */
1992 scratch = ltoh32(scratch);
1993 scratch &= 0x0001FFFF;
1998 sdstd_card_enablefuncs(sdioh_info_t *sd)
2005 sd_trace(("%s\n", __FUNCTION__));
2007 /* Get the Card's common CIS address */
2008 sd->com_cis_ptr = sdstd_get_cisaddr(sd, SDIOD_CCCR_CISPTR_0);
2009 sd->func_cis_ptr[0] = sd->com_cis_ptr;
2010 sd_info(("%s: Card's Common CIS Ptr = 0x%x\n", __FUNCTION__, sd->com_cis_ptr));
2012 /* Get the Card's function CIS (for each function) */
2013 for (fbraddr = SDIOD_FBR_STARTADDR, func = 1;
2014 func <= sd->num_funcs; func++, fbraddr += SDIOD_FBR_SIZE) {
2015 sd->func_cis_ptr[func] = sdstd_get_cisaddr(sd, SDIOD_FBR_CISPTR_0 + fbraddr);
2016 sd_info(("%s: Function %d CIS Ptr = 0x%x\n",
2017 __FUNCTION__, func, sd->func_cis_ptr[func]));
2020 /* Enable function 1 on the card */
2021 regdata = SDIO_FUNC_ENABLE_1;
2022 if ((status = sdstd_card_regwrite(sd, 0, SDIOD_CCCR_IOEN, 1, regdata)) != SUCCESS)
2028 /* Read client card reg */
2030 sdstd_card_regread(sdioh_info_t *sd, int func, uint32 regaddr, int regsize, uint32 *data)
2039 if ((func == 0) || (regsize == 1)) {
2040 cmd_arg = SFIELD(cmd_arg, CMD52_FUNCTION, func);
2041 cmd_arg = SFIELD(cmd_arg, CMD52_REG_ADDR, regaddr);
2042 cmd_arg = SFIELD(cmd_arg, CMD52_RW_FLAG, SDIOH_XFER_TYPE_READ);
2043 cmd_arg = SFIELD(cmd_arg, CMD52_RAW, 0);
2044 cmd_arg = SFIELD(cmd_arg, CMD52_DATA, 0);
2046 if ((status = sdstd_cmd_issue(sd, USE_DMA(sd), SDIOH_CMD_52, cmd_arg))
2050 sdstd_cmd_getrsp(sd, &rsp5, 1);
2051 if (sdstd_rreg16(sd, SD_ErrorIntrStatus) != 0) {
2052 sd_err(("%s: 1: ErrorintrStatus 0x%x\n",
2053 __FUNCTION__, sdstd_rreg16(sd, SD_ErrorIntrStatus)));
2056 if (GFIELD(rsp5, RSP5_FLAGS) != 0x10)
2057 sd_err(("%s: rsp5 flags is 0x%x\t %d\n",
2058 __FUNCTION__, GFIELD(rsp5, RSP5_FLAGS), func));
2060 if (GFIELD(rsp5, RSP5_STUFF))
2061 sd_err(("%s: rsp5 stuff is 0x%x: should be 0\n",
2062 __FUNCTION__, GFIELD(rsp5, RSP5_STUFF)));
2063 *data = GFIELD(rsp5, RSP5_DATA);
2065 cmd_arg = SFIELD(cmd_arg, CMD53_BYTE_BLK_CNT, regsize);
2066 cmd_arg = SFIELD(cmd_arg, CMD53_OP_CODE, 1);
2067 cmd_arg = SFIELD(cmd_arg, CMD53_BLK_MODE, 0);
2068 cmd_arg = SFIELD(cmd_arg, CMD53_FUNCTION, func);
2069 cmd_arg = SFIELD(cmd_arg, CMD53_REG_ADDR, regaddr);
2070 cmd_arg = SFIELD(cmd_arg, CMD53_RW_FLAG, SDIOH_XFER_TYPE_READ);
2072 sd->data_xfer_count = regsize;
2074 /* sdstd_cmd_issue() returns with the command complete bit
2075 * in the ISR already cleared
2077 if ((status = sdstd_cmd_issue(sd, USE_DMA(sd), SDIOH_CMD_53, cmd_arg))
2081 sdstd_cmd_getrsp(sd, &rsp5, 1);
2083 if (GFIELD(rsp5, RSP5_FLAGS) != 0x10)
2084 sd_err(("%s: rsp5 flags is 0x%x\t %d\n",
2085 __FUNCTION__, GFIELD(rsp5, RSP5_FLAGS), func));
2087 if (GFIELD(rsp5, RSP5_STUFF))
2088 sd_err(("%s: rsp5 stuff is 0x%x: should be 0\n",
2089 __FUNCTION__, GFIELD(rsp5, RSP5_STUFF)));
2091 if (sd->polled_mode) {
2092 volatile uint16 int_reg;
2093 int retries = RETRIES_LARGE;
2095 /* Wait for Read Buffer to become ready */
2097 int_reg = sdstd_rreg16(sd, SD_IntrStatus);
2098 } while (--retries && (GFIELD(int_reg, INTSTAT_BUF_READ_READY) == 0));
2101 sd_err(("%s: Timeout on Buf_Read_Ready: "
2102 "intStat: 0x%x errint: 0x%x PresentState 0x%x\n",
2103 __FUNCTION__, int_reg,
2104 sdstd_rreg16(sd, SD_ErrorIntrStatus),
2105 sdstd_rreg(sd, SD_PresentState)));
2106 sdstd_check_errs(sd, SDIOH_CMD_53, cmd_arg);
2110 /* Have Buffer Ready, so clear it and read the data */
2111 sdstd_wreg16(sd, SD_IntrStatus, SFIELD(0, INTSTAT_BUF_READ_READY, 1));
2113 *data = sdstd_rreg16(sd, SD_BufferDataPort0);
2115 *data = sdstd_rreg(sd, SD_BufferDataPort0);
2118 * After the data is read, the Transfer Complete bit should be on
2120 retries = RETRIES_LARGE;
2122 int_reg = sdstd_rreg16(sd, SD_IntrStatus);
2123 } while (--retries && (GFIELD(int_reg, INTSTAT_XFER_COMPLETE) == 0));
2125 /* Check for any errors from the data phase */
2126 if (sdstd_check_errs(sd, SDIOH_CMD_53, cmd_arg))
2130 sd_err(("%s: Timeout on xfer complete: "
2131 "intr 0x%04x err 0x%04x state 0x%08x\n",
2132 __FUNCTION__, int_reg,
2133 sdstd_rreg16(sd, SD_ErrorIntrStatus),
2134 sdstd_rreg(sd, SD_PresentState)));
2138 sdstd_wreg16(sd, SD_IntrStatus, SFIELD(0, INTSTAT_XFER_COMPLETE, 1));
2141 if (sd->polled_mode) {
2149 check_client_intr(sdioh_info_t *sd)
2151 uint16 raw_int, cur_int, old_int;
2153 raw_int = sdstd_rreg16(sd, SD_IntrStatus);
2154 cur_int = raw_int & sd->intmask;
2157 /* Not an error -- might share interrupts... */
2161 if (GFIELD(cur_int, INTSTAT_CARD_INT)) {
2162 old_int = sdstd_rreg16(sd, SD_IntrStatusEnable);
2163 sdstd_wreg16(sd, SD_IntrStatusEnable, SFIELD(old_int, INTSTAT_CARD_INT, 0));
2165 if (sd->client_intr_enabled && sd->use_client_ints) {
2167 ASSERT(sd->intr_handler);
2168 ASSERT(sd->intr_handler_arg);
2169 (sd->intr_handler)(sd->intr_handler_arg);
2171 sd_err(("%s: Not ready for intr: enabled %d, handler %p\n",
2172 __FUNCTION__, sd->client_intr_enabled, sd->intr_handler));
2174 sdstd_wreg16(sd, SD_IntrStatusEnable, old_int);
2176 /* Local interrupt: disable, set flag, and save intrstatus */
2177 sdstd_wreg16(sd, SD_IntrSignalEnable, 0);
2178 sdstd_wreg16(sd, SD_ErrorIntrSignalEnable, 0);
2179 sd->local_intrcount++;
2180 sd->got_hcint = TRUE;
2181 sd->last_intrstatus = cur_int;
2188 sdstd_spinbits(sdioh_info_t *sd, uint16 norm, uint16 err)
2190 uint16 int_reg, err_reg;
2191 int retries = RETRIES_LARGE;
2194 int_reg = sdstd_rreg16(sd, SD_IntrStatus);
2195 err_reg = sdstd_rreg16(sd, SD_ErrorIntrStatus);
2196 } while (--retries && !(int_reg & norm) && !(err_reg & err));
2198 norm |= sd->intmask;
2200 norm = SFIELD(norm, INTSTAT_ERROR_INT, 1);
2201 sd->last_intrstatus = int_reg & norm;
2204 /* write a client register */
2206 sdstd_card_regwrite(sdioh_info_t *sd, int func, uint32 regaddr, int regsize, uint32 data)
2209 uint32 cmd_arg, rsp5, flags;
2213 if ((func == 0) || (regsize == 1)) {
2214 cmd_arg = SFIELD(cmd_arg, CMD52_FUNCTION, func);
2215 cmd_arg = SFIELD(cmd_arg, CMD52_REG_ADDR, regaddr);
2216 cmd_arg = SFIELD(cmd_arg, CMD52_RW_FLAG, SDIOH_XFER_TYPE_WRITE);
2217 cmd_arg = SFIELD(cmd_arg, CMD52_RAW, 0);
2218 cmd_arg = SFIELD(cmd_arg, CMD52_DATA, data & 0xff);
2219 if ((status = sdstd_cmd_issue(sd, USE_DMA(sd), SDIOH_CMD_52, cmd_arg))
2223 sdstd_cmd_getrsp(sd, &rsp5, 1);
2224 flags = GFIELD(rsp5, RSP5_FLAGS);
2225 if (flags && (flags != 0x10))
2226 sd_err(("%s: rsp5.rsp5.flags = 0x%x, expecting 0x10\n",
2227 __FUNCTION__, flags));
2230 cmd_arg = SFIELD(cmd_arg, CMD53_BYTE_BLK_CNT, regsize);
2231 cmd_arg = SFIELD(cmd_arg, CMD53_OP_CODE, 1);
2232 cmd_arg = SFIELD(cmd_arg, CMD53_BLK_MODE, 0);
2233 cmd_arg = SFIELD(cmd_arg, CMD53_FUNCTION, func);
2234 cmd_arg = SFIELD(cmd_arg, CMD53_REG_ADDR, regaddr);
2235 cmd_arg = SFIELD(cmd_arg, CMD53_RW_FLAG, SDIOH_XFER_TYPE_WRITE);
2237 sd->data_xfer_count = regsize;
2239 /* sdstd_cmd_issue() returns with the command complete bit
2240 * in the ISR already cleared
2242 if ((status = sdstd_cmd_issue(sd, USE_DMA(sd), SDIOH_CMD_53, cmd_arg))
2246 sdstd_cmd_getrsp(sd, &rsp5, 1);
2248 if (GFIELD(rsp5, RSP5_FLAGS) != 0x10)
2249 sd_err(("%s: rsp5 flags = 0x%x, expecting 0x10\n",
2250 __FUNCTION__, GFIELD(rsp5, RSP5_FLAGS)));
2251 if (GFIELD(rsp5, RSP5_STUFF))
2252 sd_err(("%s: rsp5 stuff is 0x%x: expecting 0\n",
2253 __FUNCTION__, GFIELD(rsp5, RSP5_STUFF)));
2255 if (sd->polled_mode) {
2257 int retries = RETRIES_LARGE;
2259 /* Wait for Write Buffer to become ready */
2261 int_reg = sdstd_rreg16(sd, SD_IntrStatus);
2262 } while (--retries && (GFIELD(int_reg, INTSTAT_BUF_WRITE_READY) == 0));
2265 sd_err(("%s: Timeout on Buf_Write_Ready: intStat: 0x%x "
2266 "errint: 0x%x PresentState 0x%x\n",
2267 __FUNCTION__, int_reg,
2268 sdstd_rreg16(sd, SD_ErrorIntrStatus),
2269 sdstd_rreg(sd, SD_PresentState)));
2270 sdstd_check_errs(sd, SDIOH_CMD_53, cmd_arg);
2273 /* Clear Write Buf Ready bit */
2275 int_reg = SFIELD(int_reg, INTSTAT_BUF_WRITE_READY, 1);
2276 sdstd_wreg16(sd, SD_IntrStatus, int_reg);
2278 /* At this point we have Buffer Ready, so write the data */
2280 sdstd_wreg16(sd, SD_BufferDataPort0, (uint16) data);
2282 sdstd_wreg(sd, SD_BufferDataPort0, data);
2284 /* Wait for Transfer Complete */
2285 retries = RETRIES_LARGE;
2287 int_reg = sdstd_rreg16(sd, SD_IntrStatus);
2288 } while (--retries && (GFIELD(int_reg, INTSTAT_XFER_COMPLETE) == 0));
2290 /* Check for any errors from the data phase */
2291 if (sdstd_check_errs(sd, SDIOH_CMD_53, cmd_arg))
2295 sd_err(("%s: Timeout for xfer complete; State = 0x%x, "
2296 "intr state=0x%x, Errintstatus 0x%x rcnt %d, tcnt %d\n",
2297 __FUNCTION__, sdstd_rreg(sd, SD_PresentState),
2298 int_reg, sdstd_rreg16(sd, SD_ErrorIntrStatus),
2299 sd->r_cnt, sd->t_cnt));
2301 /* Clear the status bits */
2302 sdstd_wreg16(sd, SD_IntrStatus, SFIELD(int_reg, INTSTAT_CARD_INT, 0));
2309 sdstd_cmd_getrsp(sdioh_info_t *sd, uint32 *rsp_buffer, int count /* num 32 bit words */)
2312 int respaddr = SD_Response0;
2317 for (rsp_count = 0; rsp_count < count; rsp_count++) {
2318 *rsp_buffer++ = sdstd_rreg(sd, respaddr);
2324 sdstd_cmd_issue(sdioh_info_t *sdioh_info, bool use_dma, uint32 cmd, uint32 arg)
2329 uint16 xfer_reg = 0;
2332 if ((sdioh_info->sd_mode == SDIOH_MODE_SPI) &&
2333 ((cmd == SDIOH_CMD_3) || (cmd == SDIOH_CMD_7) || (cmd == SDIOH_CMD_15))) {
2334 sd_err(("%s: Cmd %d is not for SPI\n", __FUNCTION__, cmd));
2338 retries = RETRIES_SMALL;
2339 while ((GFIELD(sdstd_rreg(sdioh_info, SD_PresentState), PRES_CMD_INHIBIT)) && --retries) {
2340 if (retries == RETRIES_SMALL)
2341 sd_err(("%s: Waiting for Command Inhibit cmd = %d 0x%x\n",
2342 __FUNCTION__, cmd, sdstd_rreg(sdioh_info, SD_PresentState)));
2345 sd_err(("%s: Command Inhibit timeout\n", __FUNCTION__));
2354 case SDIOH_CMD_0: /* Set Card to Idle State - No Response */
2355 sd_data(("%s: CMD%d\n", __FUNCTION__, cmd));
2356 cmd_reg = SFIELD(cmd_reg, CMD_RESP_TYPE, RESP_TYPE_NONE);
2357 cmd_reg = SFIELD(cmd_reg, CMD_CRC_EN, 0);
2358 cmd_reg = SFIELD(cmd_reg, CMD_INDEX_EN, 0);
2359 cmd_reg = SFIELD(cmd_reg, CMD_DATA_EN, 0);
2360 cmd_reg = SFIELD(cmd_reg, CMD_TYPE, CMD_TYPE_NORMAL);
2361 cmd_reg = SFIELD(cmd_reg, CMD_INDEX, cmd);
2364 case SDIOH_CMD_3: /* Ask card to send RCA - Response R6 */
2365 sd_data(("%s: CMD%d\n", __FUNCTION__, cmd));
2366 cmd_reg = SFIELD(cmd_reg, CMD_RESP_TYPE, RESP_TYPE_48);
2367 cmd_reg = SFIELD(cmd_reg, CMD_CRC_EN, 0);
2368 cmd_reg = SFIELD(cmd_reg, CMD_INDEX_EN, 0);
2369 cmd_reg = SFIELD(cmd_reg, CMD_DATA_EN, 0);
2370 cmd_reg = SFIELD(cmd_reg, CMD_TYPE, CMD_TYPE_NORMAL);
2371 cmd_reg = SFIELD(cmd_reg, CMD_INDEX, cmd);
2374 case SDIOH_CMD_5: /* Send Operation condition - Response R4 */
2375 sd_data(("%s: CMD%d\n", __FUNCTION__, cmd));
2376 cmd_reg = SFIELD(cmd_reg, CMD_RESP_TYPE, RESP_TYPE_48);
2377 cmd_reg = SFIELD(cmd_reg, CMD_CRC_EN, 0);
2378 cmd_reg = SFIELD(cmd_reg, CMD_INDEX_EN, 0);
2379 cmd_reg = SFIELD(cmd_reg, CMD_DATA_EN, 0);
2380 cmd_reg = SFIELD(cmd_reg, CMD_TYPE, CMD_TYPE_NORMAL);
2381 cmd_reg = SFIELD(cmd_reg, CMD_INDEX, cmd);
2384 case SDIOH_CMD_7: /* Select card - Response R1 */
2385 sd_data(("%s: CMD%d\n", __FUNCTION__, cmd));
2386 cmd_reg = SFIELD(cmd_reg, CMD_RESP_TYPE, RESP_TYPE_48);
2387 cmd_reg = SFIELD(cmd_reg, CMD_CRC_EN, 1);
2388 cmd_reg = SFIELD(cmd_reg, CMD_INDEX_EN, 1);
2389 cmd_reg = SFIELD(cmd_reg, CMD_DATA_EN, 0);
2390 cmd_reg = SFIELD(cmd_reg, CMD_TYPE, CMD_TYPE_NORMAL);
2391 cmd_reg = SFIELD(cmd_reg, CMD_INDEX, cmd);
2394 case SDIOH_CMD_15: /* Set card to inactive state - Response None */
2395 sd_data(("%s: CMD%d\n", __FUNCTION__, cmd));
2396 cmd_reg = SFIELD(cmd_reg, CMD_RESP_TYPE, RESP_TYPE_NONE);
2397 cmd_reg = SFIELD(cmd_reg, CMD_CRC_EN, 0);
2398 cmd_reg = SFIELD(cmd_reg, CMD_INDEX_EN, 0);
2399 cmd_reg = SFIELD(cmd_reg, CMD_DATA_EN, 0);
2400 cmd_reg = SFIELD(cmd_reg, CMD_TYPE, CMD_TYPE_NORMAL);
2401 cmd_reg = SFIELD(cmd_reg, CMD_INDEX, cmd);
2404 case SDIOH_CMD_52: /* IO R/W Direct (single byte) - Response R5 */
2406 sd_data(("%s: CMD52 func(%d) addr(0x%x) %s data(0x%x)\n",
2408 GFIELD(arg, CMD52_FUNCTION),
2409 GFIELD(arg, CMD52_REG_ADDR),
2410 GFIELD(arg, CMD52_RW_FLAG) ? "W" : "R",
2411 GFIELD(arg, CMD52_DATA)));
2413 cmd_reg = SFIELD(cmd_reg, CMD_RESP_TYPE, RESP_TYPE_48);
2414 cmd_reg = SFIELD(cmd_reg, CMD_CRC_EN, 1);
2415 cmd_reg = SFIELD(cmd_reg, CMD_INDEX_EN, 1);
2416 cmd_reg = SFIELD(cmd_reg, CMD_DATA_EN, 0);
2417 cmd_reg = SFIELD(cmd_reg, CMD_TYPE, CMD_TYPE_NORMAL);
2418 cmd_reg = SFIELD(cmd_reg, CMD_INDEX, cmd);
2421 case SDIOH_CMD_53: /* IO R/W Extended (multiple bytes/blocks) */
2423 sd_data(("%s: CMD53 func(%d) addr(0x%x) %s mode(%s) cnt(%d), %s\n",
2425 GFIELD(arg, CMD53_FUNCTION),
2426 GFIELD(arg, CMD53_REG_ADDR),
2427 GFIELD(arg, CMD53_RW_FLAG) ? "W" : "R",
2428 GFIELD(arg, CMD53_BLK_MODE) ? "Block" : "Byte",
2429 GFIELD(arg, CMD53_BYTE_BLK_CNT),
2430 GFIELD(arg, CMD53_OP_CODE) ? "Incrementing addr" : "Single addr"));
2435 cmd_reg = SFIELD(cmd_reg, CMD_RESP_TYPE, RESP_TYPE_48);
2436 cmd_reg = SFIELD(cmd_reg, CMD_CRC_EN, 1);
2437 cmd_reg = SFIELD(cmd_reg, CMD_INDEX_EN, 1);
2438 cmd_reg = SFIELD(cmd_reg, CMD_DATA_EN, 1);
2439 cmd_reg = SFIELD(cmd_reg, CMD_TYPE, CMD_TYPE_NORMAL);
2440 cmd_reg = SFIELD(cmd_reg, CMD_INDEX, cmd);
2442 use_dma = USE_DMA(sdioh_info) && GFIELD(cmd_arg, CMD53_BLK_MODE);
2444 if (GFIELD(cmd_arg, CMD53_BLK_MODE)) {
2449 ASSERT(sdioh_info->sd_blockmode);
2451 func = GFIELD(cmd_arg, CMD53_FUNCTION);
2452 blocksize = MIN((int)sdioh_info->data_xfer_count,
2453 sdioh_info->client_block_size[func]);
2454 blockcount = GFIELD(cmd_arg, CMD53_BYTE_BLK_CNT);
2456 /* data_xfer_cnt is already setup so that for multiblock mode,
2457 * it is the entire buffer length. For non-block or single block,
2461 switch (sdioh_info->sd_dma_mode) {
2463 sd_dma(("%s: SDMA: SysAddr reg was 0x%x now 0x%x\n",
2464 __FUNCTION__, sdstd_rreg(sdioh_info, SD_SysAddr),
2465 (uint32)sdioh_info->dma_phys));
2466 sdstd_wreg(sdioh_info, SD_SysAddr, sdioh_info->dma_phys);
2468 case DMA_MODE_ADMA1:
2469 case DMA_MODE_ADMA2:
2470 sd_dma(("%s: ADMA: Using ADMA\n", __FUNCTION__));
2471 sd_create_adma_descriptor(sdioh_info, 0,
2472 sdioh_info->dma_phys, blockcount*blocksize,
2473 ADMA2_ATTRIBUTE_VALID | ADMA2_ATTRIBUTE_END |
2474 ADMA2_ATTRIBUTE_INT | ADMA2_ATTRIBUTE_ACT_TRAN);
2475 /* Dump descriptor if DMA debugging is enabled. */
2476 if (sd_msglevel & SDH_DMA_VAL) {
2477 sd_dump_adma_dscr(sdioh_info);
2480 sdstd_wreg(sdioh_info, SD_ADMA_SysAddr,
2481 sdioh_info->adma2_dscr_phys);
2484 sd_err(("%s: unsupported DMA mode %d.\n",
2485 __FUNCTION__, sdioh_info->sd_dma_mode));
2490 sd_trace(("%s: Setting block count %d, block size %d bytes\n",
2491 __FUNCTION__, blockcount, blocksize));
2492 sdstd_wreg16(sdioh_info, SD_BlockSize, blocksize);
2493 sdstd_wreg16(sdioh_info, SD_BlockCount, blockcount);
2495 xfer_reg = SFIELD(xfer_reg, XFER_DMA_ENABLE, use_dma);
2497 if (sdioh_info->client_block_size[func] != blocksize)
2498 set_client_block_size(sdioh_info, 1, blocksize);
2500 if (blockcount > 1) {
2501 xfer_reg = SFIELD(xfer_reg, XFER_MULTI_BLOCK, 1);
2502 xfer_reg = SFIELD(xfer_reg, XFER_BLK_COUNT_EN, 1);
2503 xfer_reg = SFIELD(xfer_reg, XFER_CMD_12_EN, 0);
2505 xfer_reg = SFIELD(xfer_reg, XFER_MULTI_BLOCK, 0);
2506 xfer_reg = SFIELD(xfer_reg, XFER_BLK_COUNT_EN, 0);
2507 xfer_reg = SFIELD(xfer_reg, XFER_CMD_12_EN, 0);
2510 if (GFIELD(cmd_arg, CMD53_RW_FLAG) == SDIOH_XFER_TYPE_READ)
2511 xfer_reg = SFIELD(xfer_reg, XFER_DATA_DIRECTION, 1);
2513 xfer_reg = SFIELD(xfer_reg, XFER_DATA_DIRECTION, 0);
2515 retries = RETRIES_SMALL;
2516 while (GFIELD(sdstd_rreg(sdioh_info, SD_PresentState),
2517 PRES_DAT_INHIBIT) && --retries)
2518 sd_err(("%s: Waiting for Data Inhibit cmd = %d\n",
2519 __FUNCTION__, cmd));
2521 sd_err(("%s: Data Inhibit timeout\n", __FUNCTION__));
2526 sdstd_wreg16(sdioh_info, SD_TransferMode, xfer_reg);
2528 } else { /* Non block mode */
2529 uint16 bytes = GFIELD(cmd_arg, CMD53_BYTE_BLK_CNT);
2530 /* The byte/block count field only has 9 bits,
2531 * so, to do a 512-byte bytemode transfer, this
2532 * field will contain 0, but we need to tell the
2533 * controller we're transferring 512 bytes.
2535 if (bytes == 0) bytes = 512;
2538 sdstd_wreg(sdioh_info, SD_SysAddr, sdioh_info->dma_phys);
2540 /* PCI: Transfer Mode register 0x0c */
2541 xfer_reg = SFIELD(xfer_reg, XFER_DMA_ENABLE, bytes <= 4 ? 0 : use_dma);
2542 xfer_reg = SFIELD(xfer_reg, XFER_CMD_12_EN, 0);
2543 if (GFIELD(cmd_arg, CMD53_RW_FLAG) == SDIOH_XFER_TYPE_READ)
2544 xfer_reg = SFIELD(xfer_reg, XFER_DATA_DIRECTION, 1);
2546 xfer_reg = SFIELD(xfer_reg, XFER_DATA_DIRECTION, 0);
2547 /* See table 2-8 Host Controller spec ver 1.00 */
2548 xfer_reg = SFIELD(xfer_reg, XFER_BLK_COUNT_EN, 0); /* Dont care */
2549 xfer_reg = SFIELD(xfer_reg, XFER_MULTI_BLOCK, 0);
2551 sdstd_wreg16(sdioh_info, SD_BlockSize, bytes);
2553 sdstd_wreg16(sdioh_info, SD_BlockCount, 1);
2555 retries = RETRIES_SMALL;
2556 while (GFIELD(sdstd_rreg(sdioh_info, SD_PresentState),
2557 PRES_DAT_INHIBIT) && --retries)
2558 sd_err(("%s: Waiting for Data Inhibit cmd = %d\n",
2559 __FUNCTION__, cmd));
2561 sd_err(("%s: Data Inhibit timeout\n", __FUNCTION__));
2566 sdstd_wreg16(sdioh_info, SD_TransferMode, xfer_reg);
2571 sd_err(("%s: Unknown command\n", __FUNCTION__));
2575 if (sdioh_info->sd_mode == SDIOH_MODE_SPI) {
2576 cmd_reg = SFIELD(cmd_reg, CMD_CRC_EN, 0);
2577 cmd_reg = SFIELD(cmd_reg, CMD_INDEX_EN, 0);
2580 /* Setup and issue the SDIO command */
2581 sdstd_wreg(sdioh_info, SD_Arg0, arg);
2582 sdstd_wreg16(sdioh_info, SD_Command, cmd_reg);
2584 /* If we are in polled mode, wait for the command to complete.
2585 * In interrupt mode, return immediately. The calling function will
2586 * know that the command has completed when the CMDATDONE interrupt
2589 if (sdioh_info->polled_mode) {
2591 int retries = RETRIES_LARGE;
2594 int_reg = sdstd_rreg16(sdioh_info, SD_IntrStatus);
2595 } while (--retries &&
2596 (GFIELD(int_reg, INTSTAT_ERROR_INT) == 0) &&
2597 (GFIELD(int_reg, INTSTAT_CMD_COMPLETE) == 0));
2600 sd_err(("%s: CMD_COMPLETE timeout: intrStatus: 0x%x "
2601 "error stat 0x%x state 0x%x\n",
2602 __FUNCTION__, int_reg,
2603 sdstd_rreg16(sdioh_info, SD_ErrorIntrStatus),
2604 sdstd_rreg(sdioh_info, SD_PresentState)));
2606 /* Attempt to reset CMD line when we get a CMD timeout */
2607 sdstd_wreg8(sdioh_info, SD_SoftwareReset, SFIELD(0, SW_RESET_CMD, 1));
2608 retries = RETRIES_LARGE;
2610 sd_trace(("%s: waiting for CMD line reset\n", __FUNCTION__));
2611 } while ((GFIELD(sdstd_rreg8(sdioh_info, SD_SoftwareReset),
2612 SW_RESET_CMD)) && retries--);
2615 sd_err(("%s: Timeout waiting for CMD line reset\n", __FUNCTION__));
2623 /* Clear Command Complete interrupt */
2624 int_reg = SFIELD(0, INTSTAT_CMD_COMPLETE, 1);
2625 sdstd_wreg16(sdioh_info, SD_IntrStatus, int_reg);
2627 /* Check for Errors */
2628 if (sdstd_check_errs(sdioh_info, cmd, arg)) {
2639 sdstd_card_buf(sdioh_info_t *sd, int rw, int func, bool fifo, uint32 addr, int nbytes, uint32 *data)
2644 uint16 int_reg, int_bit;
2646 int num_blocks, blocksize;
2647 bool local_blockmode, local_dma;
2648 bool read = rw == SDIOH_READ ? 1 : 0;
2655 sd_data(("%s: %s 53 addr 0x%x, len %d bytes, r_cnt %d t_cnt %d\n",
2656 __FUNCTION__, read ? "Rd" : "Wr", addr, nbytes, sd->r_cnt, sd->t_cnt));
2658 if (read) sd->r_cnt++; else sd->t_cnt++;
2660 local_blockmode = sd->sd_blockmode;
2661 local_dma = USE_DMA(sd);
2663 /* Don't bother with block mode on small xfers */
2664 if (nbytes < sd->client_block_size[func]) {
2665 sd_data(("setting local blockmode to false: nbytes (%d) != block_size (%d)\n",
2666 nbytes, sd->client_block_size[func]));
2667 local_blockmode = FALSE;
2671 if (local_blockmode) {
2672 blocksize = MIN(sd->client_block_size[func], nbytes);
2673 num_blocks = nbytes/blocksize;
2674 cmd_arg = SFIELD(cmd_arg, CMD53_BYTE_BLK_CNT, num_blocks);
2675 cmd_arg = SFIELD(cmd_arg, CMD53_BLK_MODE, 1);
2679 cmd_arg = SFIELD(cmd_arg, CMD53_BYTE_BLK_CNT, nbytes);
2680 cmd_arg = SFIELD(cmd_arg, CMD53_BLK_MODE, 0);
2683 if (local_dma && !read) {
2684 bcopy(data, sd->dma_buf, nbytes);
2685 sd_sync_dma(sd, read, nbytes);
2689 cmd_arg = SFIELD(cmd_arg, CMD53_OP_CODE, 0);
2691 cmd_arg = SFIELD(cmd_arg, CMD53_OP_CODE, 1);
2693 cmd_arg = SFIELD(cmd_arg, CMD53_FUNCTION, func);
2694 cmd_arg = SFIELD(cmd_arg, CMD53_REG_ADDR, addr);
2696 cmd_arg = SFIELD(cmd_arg, CMD53_RW_FLAG, SDIOH_XFER_TYPE_READ);
2698 cmd_arg = SFIELD(cmd_arg, CMD53_RW_FLAG, SDIOH_XFER_TYPE_WRITE);
2700 sd->data_xfer_count = nbytes;
2702 /* sdstd_cmd_issue() returns with the command complete bit
2703 * in the ISR already cleared
2705 if ((status = sdstd_cmd_issue(sd, local_dma, SDIOH_CMD_53, cmd_arg)) != SUCCESS) {
2706 sd_err(("%s: cmd_issue failed for %s\n", __FUNCTION__, (read ? "read" : "write")));
2710 sdstd_cmd_getrsp(sd, &rsp5, 1);
2712 if ((flags = GFIELD(rsp5, RSP5_FLAGS)) != 0x10) {
2713 sd_err(("%s: Rsp5: nbytes %d, dma %d blockmode %d, read %d "
2714 "numblocks %d, blocksize %d\n",
2715 __FUNCTION__, nbytes, local_dma, local_dma, read, num_blocks, blocksize));
2718 sd_err(("%s: rsp5: Command not accepted: arg out of range 0x%x, "
2719 "bytes %d dma %d\n",
2720 __FUNCTION__, flags, GFIELD(cmd_arg, CMD53_BYTE_BLK_CNT),
2721 GFIELD(cmd_arg, CMD53_BLK_MODE)));
2723 sd_err(("%s: Rsp5: General Error\n", __FUNCTION__));
2725 sd_err(("%s: rsp5 flags = 0x%x, expecting 0x10 returning error\n",
2726 __FUNCTION__, flags));
2732 if (GFIELD(rsp5, RSP5_STUFF))
2733 sd_err(("%s: rsp5 stuff is 0x%x: expecting 0\n",
2734 __FUNCTION__, GFIELD(rsp5, RSP5_STUFF)));
2737 yield = sd_yieldcpu && ((uint)nbytes >= sd_minyield);
2743 for (i = 0; i < num_blocks; i++) {
2746 /* Decide which status bit we're waiting for */
2748 int_bit = SFIELD(0, INTSTAT_BUF_READ_READY, 1);
2750 int_bit = SFIELD(0, INTSTAT_BUF_WRITE_READY, 1);
2752 /* If not on, wait for it (or for xfer error) */
2753 int_reg = sdstd_rreg16(sd, SD_IntrStatus);
2754 if (!(int_reg & int_bit))
2755 int_reg = sdstd_waitbits(sd, int_bit, ERRINT_TRANSFER_ERRS, yield);
2757 /* Confirm we got the bit w/o error */
2758 if (!(int_reg & int_bit) || GFIELD(int_reg, INTSTAT_ERROR_INT)) {
2759 sd_err(("%s: Error or timeout for Buf_%s_Ready: intStat: 0x%x "
2760 "errint: 0x%x PresentState 0x%x\n",
2761 __FUNCTION__, read ? "Read" : "Write", int_reg,
2762 sdstd_rreg16(sd, SD_ErrorIntrStatus),
2763 sdstd_rreg(sd, SD_PresentState)));
2765 sdstd_check_errs(sd, SDIOH_CMD_53, cmd_arg);
2769 /* Clear Buf Ready bit */
2770 sdstd_wreg16(sd, SD_IntrStatus, int_bit);
2772 /* At this point we have Buffer Ready, write the data 4 bytes at a time */
2773 for (words = blocksize/4; words; words--) {
2775 *data = sdstd_rreg(sd, SD_BufferDataPort0);
2777 sdstd_wreg(sd, SD_BufferDataPort0, *data);
2781 bytes = blocksize % 4;
2783 /* If no leftover bytes, go to next block */
2791 *(data++) = (uint32)(sdstd_rreg8(sd, SD_BufferDataPort0));
2793 sdstd_wreg8(sd, SD_BufferDataPort0,
2794 (uint8)(*(data++) & 0xff));
2799 *(data++) = (uint32)sdstd_rreg16(sd, SD_BufferDataPort0);
2801 sdstd_wreg16(sd, SD_BufferDataPort0, (uint16)(*(data++)));
2805 * SD_BufferDataPort0[0-15] | SD_BufferDataPort1[16-23]
2808 tmp = (uint32)sdstd_rreg16(sd, SD_BufferDataPort0);
2809 tmp |= ((uint32)(sdstd_rreg8(sd,
2810 SD_BufferDataPort1)) << 16);
2814 sdstd_wreg16(sd, SD_BufferDataPort0, (uint16)tmp & 0xffff);
2815 sdstd_wreg8(sd, SD_BufferDataPort1,
2816 (uint8)((tmp >> 16) & 0xff));
2820 sd_err(("%s: Unexpected bytes leftover %d\n",
2821 __FUNCTION__, bytes));
2826 } /* End PIO processing */
2828 /* Wait for Transfer Complete or Transfer Error */
2829 int_bit = SFIELD(0, INTSTAT_XFER_COMPLETE, 1);
2831 /* If not on, wait for it (or for xfer error) */
2832 int_reg = sdstd_rreg16(sd, SD_IntrStatus);
2833 if (!(int_reg & int_bit))
2834 int_reg = sdstd_waitbits(sd, int_bit, ERRINT_TRANSFER_ERRS, yield);
2836 /* Check for any errors from the data phase */
2837 if (sdstd_check_errs(sd, SDIOH_CMD_53, cmd_arg))
2840 /* May have gotten a software timeout if not blocking? */
2841 int_reg = sdstd_rreg16(sd, SD_IntrStatus);
2842 if (!(int_reg & int_bit)) {
2843 sd_err(("%s: Error or Timeout for xfer complete; %s, dma %d, State 0x%08x, "
2844 "intr 0x%04x, Err 0x%04x, len = %d, rcnt %d, tcnt %d\n",
2845 __FUNCTION__, read ? "R" : "W", local_dma,
2846 sdstd_rreg(sd, SD_PresentState), int_reg,
2847 sdstd_rreg16(sd, SD_ErrorIntrStatus), nbytes,
2848 sd->r_cnt, sd->t_cnt));
2853 /* Clear the status bits */
2857 /* Reads in particular don't have DMA_COMPLETE set */
2858 int_reg = SFIELD(int_reg, INTSTAT_DMA_INT, 1);
2860 sdstd_wreg16(sd, SD_IntrStatus, int_reg);
2863 if (local_dma && read) {
2864 sd_sync_dma(sd, read, nbytes);
2865 bcopy(sd->dma_buf, data, nbytes);
2871 set_client_block_size(sdioh_info_t *sd, int func, int block_size)
2877 sd_err(("%s: Setting block size %d, func %d\n", __FUNCTION__, block_size, func));
2878 sd->client_block_size[func] = block_size;
2880 /* Set the block size in the SDIO Card register */
2881 base = func * SDIOD_FBR_SIZE;
2882 err = sdstd_card_regwrite(sd, 0, base+SDIOD_CCCR_BLKSIZE_0, 1, block_size & 0xff);
2884 err = sdstd_card_regwrite(sd, 0, base+SDIOD_CCCR_BLKSIZE_1, 1,
2885 (block_size >> 8) & 0xff);
2888 /* Do not set the block size in the SDIO Host register, that
2889 * is func dependent and will get done on an individual
2893 return (err ? BCME_SDIO_ERROR : 0);
2896 /* Reset and re-initialize the device */
2898 sdioh_sdio_reset(sdioh_info_t *si)
2902 /* Reset the attached device (use slower clock for safety) */
2903 sdstd_start_clock(si, 128);
2904 sdstd_reset(si, 0, 1);
2906 /* Reset portions of the host state accordingly */
2907 hreg = sdstd_rreg8(si, SD_HostCntrl);
2908 hreg = SFIELD(hreg, HOST_HI_SPEED_EN, 0);
2909 hreg = SFIELD(hreg, HOST_DATA_WIDTH, 0);
2910 si->sd_mode = SDIOH_MODE_SD1;
2912 /* Reinitialize the card */
2913 si->card_init_done = FALSE;
2914 return sdstd_client_init(si);
2919 sd_map_dma(sdioh_info_t * sd)
2924 if ((va = DMA_ALLOC_CONSISTENT(sd->osh, SD_PAGE,
2925 &sd->dma_start_phys, 0x12, 12)) == NULL) {
2926 sd->sd_dma_mode = DMA_MODE_NONE;
2927 sd->dma_start_buf = 0;
2928 sd->dma_buf = (void *)0;
2930 sd->alloced_dma_size = SD_PAGE;
2931 sd_err(("%s: DMA_ALLOC failed. Disabling DMA support.\n", __FUNCTION__));
2933 sd->dma_start_buf = va;
2934 sd->dma_buf = (void *)ROUNDUP((uintptr)va, SD_PAGE);
2935 sd->dma_phys = ROUNDUP((sd->dma_start_phys), SD_PAGE);
2936 sd->alloced_dma_size = SD_PAGE;
2937 sd_err(("%s: Mapped DMA Buffer %dbytes @virt/phys: %p/0x%lx\n",
2938 __FUNCTION__, sd->alloced_dma_size, sd->dma_buf, sd->dma_phys));
2939 sd_fill_dma_data_buf(sd, 0xA5);
2942 if ((va = DMA_ALLOC_CONSISTENT(sd->osh, SD_PAGE,
2943 &sd->adma2_dscr_start_phys, 0x12, 12)) == NULL) {
2944 sd->sd_dma_mode = DMA_MODE_NONE;
2945 sd->adma2_dscr_start_buf = 0;
2946 sd->adma2_dscr_buf = (void *)0;
2947 sd->adma2_dscr_phys = 0;
2948 sd->alloced_adma2_dscr_size = 0;
2949 sd_err(("%s: DMA_ALLOC failed for descriptor buffer. "
2950 "Disabling DMA support.\n", __FUNCTION__));
2952 sd->adma2_dscr_start_buf = va;
2953 sd->adma2_dscr_buf = (void *)ROUNDUP((uintptr)va, SD_PAGE);
2954 sd->adma2_dscr_phys = ROUNDUP((sd->adma2_dscr_start_phys), SD_PAGE);
2955 sd->alloced_adma2_dscr_size = SD_PAGE;
2958 sd_err(("%s: Mapped ADMA2 Descriptor Buffer %dbytes @virt/phys: %p/0x%lx\n",
2959 __FUNCTION__, sd->alloced_adma2_dscr_size, sd->adma2_dscr_buf,
2960 sd->adma2_dscr_phys));
2961 sd_clear_adma_dscr_buf(sd);
2965 sd_unmap_dma(sdioh_info_t * sd)
2967 if (sd->dma_start_buf) {
2968 DMA_FREE_CONSISTENT(sd->osh, sd->dma_start_buf, sd->alloced_dma_size,
2969 sd->dma_start_phys, 0x12);
2972 if (sd->adma2_dscr_start_buf) {
2973 DMA_FREE_CONSISTENT(sd->osh, sd->adma2_dscr_start_buf, sd->alloced_adma2_dscr_size,
2974 sd->adma2_dscr_start_phys, 0x12);
2978 static void sd_clear_adma_dscr_buf(sdioh_info_t *sd)
2980 bzero((char *)sd->adma2_dscr_buf, SD_PAGE);
2981 sd_dump_adma_dscr(sd);
2984 static void sd_fill_dma_data_buf(sdioh_info_t *sd, uint8 data)
2986 memset((char *)sd->dma_buf, data, SD_PAGE);
2990 static void sd_create_adma_descriptor(sdioh_info_t *sd, uint32 index,
2991 uint32 addr_phys, uint16 length, uint16 flags)
2993 adma2_dscr_32b_t *adma2_dscr_table;
2994 adma1_dscr_t *adma1_dscr_table;
2996 adma2_dscr_table = sd->adma2_dscr_buf;
2997 adma1_dscr_table = sd->adma2_dscr_buf;
2999 switch (sd->sd_dma_mode) {
3000 case DMA_MODE_ADMA2:
3001 sd_dma(("%s: creating ADMA2 descriptor for index %d\n",
3002 __FUNCTION__, index));
3004 adma2_dscr_table[index].phys_addr = addr_phys;
3005 adma2_dscr_table[index].len_attr = length << 16;
3006 adma2_dscr_table[index].len_attr |= flags;
3008 case DMA_MODE_ADMA1:
3009 /* ADMA1 requires two descriptors, one for len
3010 * and the other for data transfer
3014 sd_dma(("%s: creating ADMA1 descriptor for index %d\n",
3015 __FUNCTION__, index));
3017 adma1_dscr_table[index].phys_addr_attr = length << 12;
3018 adma1_dscr_table[index].phys_addr_attr |= (ADMA1_ATTRIBUTE_ACT_SET |
3019 ADMA2_ATTRIBUTE_VALID);
3020 adma1_dscr_table[index+1].phys_addr_attr = addr_phys & 0xFFFFF000;
3021 adma1_dscr_table[index+1].phys_addr_attr |= (flags & 0x3f);
3024 sd_err(("%s: cannot create ADMA descriptor for DMA mode %d\n",
3025 __FUNCTION__, sd->sd_dma_mode));
3031 static void sd_dump_adma_dscr(sdioh_info_t *sd)
3033 adma2_dscr_32b_t *adma2_dscr_table;
3034 adma1_dscr_t *adma1_dscr_table;
3039 ASSERT(sd->adma2_dscr_buf != NULL);
3041 adma2_dscr_table = sd->adma2_dscr_buf;
3042 adma1_dscr_table = sd->adma2_dscr_buf;
3044 switch (sd->sd_dma_mode) {
3045 case DMA_MODE_ADMA2:
3046 sd_err(("ADMA2 Descriptor Table (%dbytes) @virt/phys: %p/0x%lx\n",
3047 SD_PAGE, sd->adma2_dscr_buf, sd->adma2_dscr_phys));
3048 sd_err((" #[Descr VA ] Buffer PA | Len | Flags (5:4 2 1 0)"
3050 while (adma2_dscr_table->len_attr & ADMA2_ATTRIBUTE_VALID) {
3051 flags = adma2_dscr_table->len_attr & 0xFFFF;
3052 sprintf(flags_str, "%s%s%s%s",
3053 ((flags & ADMA2_ATTRIBUTE_ACT_LINK) ==
3054 ADMA2_ATTRIBUTE_ACT_LINK) ? "LINK " :
3055 ((flags & ADMA2_ATTRIBUTE_ACT_LINK) ==
3056 ADMA2_ATTRIBUTE_ACT_TRAN) ? "TRAN " :
3057 ((flags & ADMA2_ATTRIBUTE_ACT_LINK) ==
3058 ADMA2_ATTRIBUTE_ACT_NOP) ? "NOP " : "RSV ",
3059 (flags & ADMA2_ATTRIBUTE_INT ? "INT " : " "),
3060 (flags & ADMA2_ATTRIBUTE_END ? "END " : " "),
3061 (flags & ADMA2_ATTRIBUTE_VALID ? "VALID" : ""));
3062 sd_err(("%2d[0x%p]: 0x%08x | 0x%04x | 0x%04x (%s) |\n",
3063 i, adma2_dscr_table, adma2_dscr_table->phys_addr,
3064 adma2_dscr_table->len_attr >> 16, flags, flags_str));
3067 /* Follow LINK descriptors or skip to next. */
3068 if ((flags & ADMA2_ATTRIBUTE_ACT_LINK) ==
3069 ADMA2_ATTRIBUTE_ACT_LINK) {
3070 adma2_dscr_table = phys_to_virt(
3071 adma2_dscr_table->phys_addr);
3078 case DMA_MODE_ADMA1:
3079 sd_err(("ADMA1 Descriptor Table (%dbytes) @virt/phys: %p/0x%lx\n",
3080 SD_PAGE, sd->adma2_dscr_buf, sd->adma2_dscr_phys));
3081 sd_err((" #[Descr VA ] Buffer PA | Flags (5:4 2 1 0) |\n"));
3083 for (i = 0; adma1_dscr_table->phys_addr_attr & ADMA2_ATTRIBUTE_VALID; i++) {
3084 flags = adma1_dscr_table->phys_addr_attr & 0x3F;
3085 sprintf(flags_str, "%s%s%s%s",
3086 ((flags & ADMA2_ATTRIBUTE_ACT_LINK) ==
3087 ADMA2_ATTRIBUTE_ACT_LINK) ? "LINK " :
3088 ((flags & ADMA2_ATTRIBUTE_ACT_LINK) ==
3089 ADMA2_ATTRIBUTE_ACT_TRAN) ? "TRAN " :
3090 ((flags & ADMA2_ATTRIBUTE_ACT_LINK) ==
3091 ADMA2_ATTRIBUTE_ACT_NOP) ? "NOP " : "SET ",
3092 (flags & ADMA2_ATTRIBUTE_INT ? "INT " : " "),
3093 (flags & ADMA2_ATTRIBUTE_END ? "END " : " "),
3094 (flags & ADMA2_ATTRIBUTE_VALID ? "VALID" : ""));
3095 sd_err(("%2d[0x%p]: 0x%08x | 0x%04x | (%s) |\n",
3096 i, adma1_dscr_table,
3097 adma1_dscr_table->phys_addr_attr & 0xFFFFF000,
3100 /* Follow LINK descriptors or skip to next. */
3101 if ((flags & ADMA2_ATTRIBUTE_ACT_LINK) ==
3102 ADMA2_ATTRIBUTE_ACT_LINK) {
3103 adma1_dscr_table = phys_to_virt(
3104 adma1_dscr_table->phys_addr_attr & 0xFFFFF000);
3111 sd_err(("Unknown DMA Descriptor Table Format.\n"));
3116 static void sdstd_dumpregs(sdioh_info_t *sd)
3118 sd_err(("IntrStatus: 0x%04x ErrorIntrStatus 0x%04x\n",
3119 sdstd_rreg16(sd, SD_IntrStatus),
3120 sdstd_rreg16(sd, SD_ErrorIntrStatus)));
3121 sd_err(("IntrStatusEnable: 0x%04x ErrorIntrStatusEnable 0x%04x\n",
3122 sdstd_rreg16(sd, SD_IntrStatusEnable),
3123 sdstd_rreg16(sd, SD_ErrorIntrStatusEnable)));
3124 sd_err(("IntrSignalEnable: 0x%04x ErrorIntrSignalEnable 0x%04x\n",
3125 sdstd_rreg16(sd, SD_IntrSignalEnable),
3126 sdstd_rreg16(sd, SD_ErrorIntrSignalEnable)));