3 Broadcom B43 wireless driver
4 IEEE 802.11n PHY support
6 Copyright (c) 2008 Michael Buesch <mb@bu3sch.de>
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING. If not, write to
20 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
21 Boston, MA 02110-1301, USA.
25 #include <linux/delay.h>
26 #include <linux/slab.h>
27 #include <linux/types.h>
31 #include "tables_nphy.h"
41 struct nphy_iqcal_params {
59 enum b43_nphy_rf_sequence {
63 B43_RFSEQ_UPDATE_GAINH,
64 B43_RFSEQ_UPDATE_GAINL,
65 B43_RFSEQ_UPDATE_GAINU,
68 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
69 u8 *events, u8 *delays, u8 length);
70 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
71 enum b43_nphy_rf_sequence seq);
72 static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
73 u16 value, u8 core, bool off);
74 static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
76 static int nphy_channel_switch(struct b43_wldev *dev, unsigned int channel);
78 static inline bool b43_empty_chanspec(struct b43_chanspec *chanspec)
80 return !chanspec->channel && !chanspec->sideband &&
81 !chanspec->b_width && !chanspec->b_freq;
84 static inline bool b43_eq_chanspecs(struct b43_chanspec *chanspec1,
85 struct b43_chanspec *chanspec2)
87 return (chanspec1->channel == chanspec2->channel &&
88 chanspec1->sideband == chanspec2->sideband &&
89 chanspec1->b_width == chanspec2->b_width &&
90 chanspec1->b_freq == chanspec2->b_freq);
93 void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
97 static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
101 static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
104 return B43_TXPWR_RES_DONE;
107 static void b43_chantab_radio_upload(struct b43_wldev *dev,
108 const struct b43_nphy_channeltab_entry_rev2 *e)
110 b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref);
111 b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
112 b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
113 b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
114 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
116 b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
117 b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
118 b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
119 b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
120 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
122 b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
123 b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
124 b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
125 b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
126 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
128 b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
129 b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
130 b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
131 b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
132 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
134 b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
135 b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
136 b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
137 b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
138 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
140 b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
141 b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
144 static void b43_chantab_phy_upload(struct b43_wldev *dev,
145 const struct b43_phy_n_sfo_cfg *e)
147 b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
148 b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
149 b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
150 b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
151 b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
152 b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
155 static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
161 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */
162 static void b43_radio_2055_setup(struct b43_wldev *dev,
163 const struct b43_nphy_channeltab_entry_rev2 *e)
165 B43_WARN_ON(dev->phy.rev >= 3);
167 b43_chantab_radio_upload(dev, e);
169 b43_radio_write(dev, B2055_VCO_CAL10, 0x05);
170 b43_radio_write(dev, B2055_VCO_CAL10, 0x45);
171 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
172 b43_radio_write(dev, B2055_VCO_CAL10, 0x65);
176 static void b43_radio_init2055_pre(struct b43_wldev *dev)
178 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
179 ~B43_NPHY_RFCTL_CMD_PORFORCE);
180 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
181 B43_NPHY_RFCTL_CMD_CHIP0PU |
182 B43_NPHY_RFCTL_CMD_OEPORFORCE);
183 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
184 B43_NPHY_RFCTL_CMD_PORFORCE);
187 static void b43_radio_init2055_post(struct b43_wldev *dev)
189 struct b43_phy_n *nphy = dev->phy.n;
190 struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
191 struct ssb_boardinfo *binfo = &(dev->dev->bus->boardinfo);
194 bool workaround = false;
196 if (sprom->revision < 4)
197 workaround = (binfo->vendor != PCI_VENDOR_ID_BROADCOM ||
198 binfo->type != 0x46D ||
201 workaround = ((sprom->boardflags_hi & B43_BFH_NOPA) == 0);
203 b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
205 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
206 b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F);
208 b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C);
209 b43_radio_write(dev, B2055_CAL_MISC, 0x3C);
210 b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
211 b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
212 b43_radio_set(dev, B2055_CAL_MISC, 0x1);
214 b43_radio_set(dev, B2055_CAL_MISC, 0x40);
215 for (i = 0; i < 200; i++) {
216 val = b43_radio_read(dev, B2055_CAL_COUT2);
224 b43err(dev->wl, "radio post init timeout\n");
225 b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
226 nphy_channel_switch(dev, dev->phy.channel);
227 b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9);
228 b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9);
229 b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
230 b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
231 b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6);
232 b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6);
233 if (!nphy->gain_boost) {
234 b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2);
235 b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2);
237 b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD);
238 b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD);
244 * Initialize a Broadcom 2055 N-radio
245 * http://bcm-v4.sipsolutions.net/802.11/Radio/2055/Init
247 static void b43_radio_init2055(struct b43_wldev *dev)
249 b43_radio_init2055_pre(dev);
250 if (b43_status(dev) < B43_STAT_INITIALIZED)
251 b2055_upload_inittab(dev, 0, 1);
253 b2055_upload_inittab(dev, 0/*FIXME on 5ghz band*/, 0);
254 b43_radio_init2055_post(dev);
258 * Initialize a Broadcom 2056 N-radio
259 * http://bcm-v4.sipsolutions.net/802.11/Radio/2056/Init
261 static void b43_radio_init2056(struct b43_wldev *dev)
268 * Upload the N-PHY tables.
269 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
271 static void b43_nphy_tables_init(struct b43_wldev *dev)
273 if (dev->phy.rev < 3)
274 b43_nphy_rev0_1_2_tables_init(dev);
276 b43_nphy_rev3plus_tables_init(dev);
279 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
280 static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
282 struct b43_phy_n *nphy = dev->phy.n;
283 enum ieee80211_band band;
287 nphy->rfctrl_intc1_save = b43_phy_read(dev,
288 B43_NPHY_RFCTL_INTC1);
289 nphy->rfctrl_intc2_save = b43_phy_read(dev,
290 B43_NPHY_RFCTL_INTC2);
291 band = b43_current_band(dev->wl);
292 if (dev->phy.rev >= 3) {
293 if (band == IEEE80211_BAND_5GHZ)
298 if (band == IEEE80211_BAND_5GHZ)
303 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
304 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
306 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
307 nphy->rfctrl_intc1_save);
308 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
309 nphy->rfctrl_intc2_save);
313 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */
314 static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
316 struct b43_phy_n *nphy = dev->phy.n;
318 enum ieee80211_band band = b43_current_band(dev->wl);
319 bool ipa = (nphy->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
320 (nphy->ipa5g_on && band == IEEE80211_BAND_5GHZ);
322 if (dev->phy.rev >= 3) {
325 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
326 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
330 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
331 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
335 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */
336 static void b43_nphy_bmac_clock_fgc(struct b43_wldev *dev, bool force)
340 if (dev->phy.type != B43_PHYTYPE_N)
343 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
345 tmslow |= SSB_TMSLOW_FGC;
347 tmslow &= ~SSB_TMSLOW_FGC;
348 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
351 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
352 static void b43_nphy_reset_cca(struct b43_wldev *dev)
356 b43_nphy_bmac_clock_fgc(dev, 1);
357 bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
358 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
360 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
361 b43_nphy_bmac_clock_fgc(dev, 0);
362 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
365 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
366 static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
368 u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
370 mimocfg |= B43_NPHY_MIMOCFG_AUTO;
372 mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
374 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
376 b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
379 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
380 static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
382 struct b43_phy_n *nphy = dev->phy.n;
384 bool override = false;
387 if (nphy->txrx_chain == 0) {
390 } else if (nphy->txrx_chain == 1) {
395 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
396 ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
400 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
401 B43_NPHY_RFSEQMODE_CAOVER);
403 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
404 ~B43_NPHY_RFSEQMODE_CAOVER);
407 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
408 static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
409 u16 samps, u8 time, bool wait)
414 b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
415 b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
417 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
419 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
421 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
423 for (i = 1000; i; i--) {
424 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
425 if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
426 est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
427 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
428 est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
429 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
430 est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
431 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
433 est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
434 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
435 est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
436 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
437 est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
438 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
443 memset(est, 0, sizeof(*est));
446 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
447 static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
448 struct b43_phy_n_iq_comp *pcomp)
451 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
452 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
453 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
454 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
456 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
457 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
458 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
459 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
463 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
464 static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
466 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
468 b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
470 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
471 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
473 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
474 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
476 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
477 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
478 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
479 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
480 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
481 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
482 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
483 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
486 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
487 static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
490 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
492 regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
494 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
495 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
497 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
498 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
500 regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
501 regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
502 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
503 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
504 regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
505 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
506 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
507 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
509 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
510 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
512 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, (u16)~B43_NPHY_RFSEQCA_RXDIS,
513 ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
514 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
515 ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
516 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
517 (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
518 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
519 (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
522 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
523 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
525 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
526 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
529 b43_nphy_rf_control_intc_override(dev, 2, 0, 3);
530 b43_nphy_rf_control_override(dev, 8, 0, 3, false);
531 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
540 b43_nphy_rf_control_intc_override(dev, 1, rxval, (core + 1));
541 b43_nphy_rf_control_intc_override(dev, 1, txval, (2 - core));
544 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
545 static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
551 int iq_nbits, qq_nbits;
555 struct nphy_iq_est est;
556 struct b43_phy_n_iq_comp old;
557 struct b43_phy_n_iq_comp new = { };
563 b43_nphy_rx_iq_coeffs(dev, false, &old);
564 b43_nphy_rx_iq_coeffs(dev, true, &new);
565 b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
568 for (i = 0; i < 2; i++) {
569 if (i == 0 && (mask & 1)) {
573 } else if (i == 1 && (mask & 2)) {
587 iq_nbits = fls(abs(iq));
590 arsh = iq_nbits - 20;
592 a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
595 a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
604 brsh = qq_nbits - 11;
606 b = (qq << (31 - qq_nbits));
609 b = (qq << (31 - qq_nbits));
616 b = int_sqrt(b / tmp - a * a) - (1 << 10);
618 if (i == 0 && (mask & 0x1)) {
619 if (dev->phy.rev >= 3) {
626 } else if (i == 1 && (mask & 0x2)) {
627 if (dev->phy.rev >= 3) {
640 b43_nphy_rx_iq_coeffs(dev, true, &new);
643 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
644 static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
649 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C50);
650 for (i = 0; i < 4; i++)
651 array[i] = b43_phy_read(dev, B43_NPHY_TABLE_DATALO);
653 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
654 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
655 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
656 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
659 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
660 static void b43_nphy_write_clip_detection(struct b43_wldev *dev, u16 *clip_st)
662 b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
663 b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
666 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
667 static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
669 clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
670 clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
673 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */
674 static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init)
676 if (dev->phy.rev >= 3) {
680 b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211);
681 b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222);
682 b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144);
683 b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188);
686 b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0);
687 b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0);
689 ssb_chipco_gpio_control(&dev->dev->bus->chipco, 0xFC00,
691 b43_write32(dev, B43_MMIO_MACCTL,
692 b43_read32(dev, B43_MMIO_MACCTL) &
693 ~B43_MACCTL_GPOUTSMSK);
694 b43_write16(dev, B43_MMIO_GPIO_MASK,
695 b43_read16(dev, B43_MMIO_GPIO_MASK) | 0xFC00);
696 b43_write16(dev, B43_MMIO_GPIO_CONTROL,
697 b43_read16(dev, B43_MMIO_GPIO_CONTROL) & ~0xFC00);
700 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
701 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
702 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
703 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
708 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
709 static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
713 if (dev->dev->id.revision == 16)
714 b43_mac_suspend(dev);
716 tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
717 tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
718 B43_NPHY_CLASSCTL_WAITEDEN);
721 b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
723 if (dev->dev->id.revision == 16)
729 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
730 static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
732 struct b43_phy *phy = &dev->phy;
733 struct b43_phy_n *nphy = phy->n;
736 u16 clip[] = { 0xFFFF, 0xFFFF };
737 if (nphy->deaf_count++ == 0) {
738 nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
739 b43_nphy_classifier(dev, 0x7, 0);
740 b43_nphy_read_clip_detection(dev, nphy->clip_state);
741 b43_nphy_write_clip_detection(dev, clip);
743 b43_nphy_reset_cca(dev);
745 if (--nphy->deaf_count == 0) {
746 b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
747 b43_nphy_write_clip_detection(dev, nphy->clip_state);
752 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
753 static void b43_nphy_stop_playback(struct b43_wldev *dev)
755 struct b43_phy_n *nphy = dev->phy.n;
758 if (nphy->hang_avoid)
759 b43_nphy_stay_in_carrier_search(dev, 1);
761 tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
763 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
765 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, (u16)~0x8000);
767 b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
769 if (nphy->bb_mult_save & 0x80000000) {
770 tmp = nphy->bb_mult_save & 0xFFFF;
771 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
772 nphy->bb_mult_save = 0;
775 if (nphy->hang_avoid)
776 b43_nphy_stay_in_carrier_search(dev, 0);
779 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */
780 static void b43_nphy_spur_workaround(struct b43_wldev *dev)
782 struct b43_phy_n *nphy = dev->phy.n;
784 u8 channel = nphy->radio_chanspec.channel;
785 int tone[2] = { 57, 58 };
786 u32 noise[2] = { 0x3FF, 0x3FF };
788 B43_WARN_ON(dev->phy.rev < 3);
790 if (nphy->hang_avoid)
791 b43_nphy_stay_in_carrier_search(dev, 1);
793 if (nphy->gband_spurwar_en) {
794 /* TODO: N PHY Adjust Analog Pfbw (7) */
795 if (channel == 11 && dev->phy.is_40mhz)
796 ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/
798 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
799 /* TODO: N PHY Adjust CRS Min Power (0x1E) */
802 if (nphy->aband_spurwar_en) {
806 } else if (channel == 38 || channel == 102 || channel == 118) {
814 } else if (channel == 134) {
817 } else if (channel == 151) {
820 } else if (channel == 153 || channel == 161) {
828 if (!tone[0] && !noise[0])
829 ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/
831 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
834 if (nphy->hang_avoid)
835 b43_nphy_stay_in_carrier_search(dev, 0);
838 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/AdjustLnaGainTbl */
839 static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev)
841 struct b43_phy_n *nphy = dev->phy.n;
848 u16 lna_gain[4] = { -2, 10, 19, 25 };
850 if (nphy->hang_avoid)
851 b43_nphy_stay_in_carrier_search(dev, 1);
853 if (nphy->gain_boost) {
854 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
858 tmp = 40370 - 315 * nphy->radio_chanspec.channel;
859 gain[0] = ((tmp >> 13) + ((tmp >> 12) & 1));
860 tmp = 23242 - 224 * nphy->radio_chanspec.channel;
861 gain[1] = ((tmp >> 13) + ((tmp >> 12) & 1));
868 for (i = 0; i < 2; i++) {
869 if (nphy->elna_gain_config) {
870 data[0] = 19 + gain[i];
871 data[1] = 25 + gain[i];
872 data[2] = 25 + gain[i];
873 data[3] = 25 + gain[i];
875 data[0] = lna_gain[0] + gain[i];
876 data[1] = lna_gain[1] + gain[i];
877 data[2] = lna_gain[2] + gain[i];
878 data[3] = lna_gain[3] + gain[i];
880 b43_ntab_write_bulk(dev, B43_NTAB16(10, 8), 4, data);
882 minmax[i] = 23 + gain[i];
885 b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN, ~B43_NPHY_C1_MINGAIN,
886 minmax[0] << B43_NPHY_C1_MINGAIN_SHIFT);
887 b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN, ~B43_NPHY_C2_MINGAIN,
888 minmax[1] << B43_NPHY_C2_MINGAIN_SHIFT);
890 if (nphy->hang_avoid)
891 b43_nphy_stay_in_carrier_search(dev, 0);
894 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */
895 static void b43_nphy_gain_crtl_workarounds(struct b43_wldev *dev)
897 struct b43_phy_n *nphy = dev->phy.n;
901 /* TODO: for PHY >= 3
902 s8 *lna1_gain, *lna2_gain;
903 u8 *gain_db, *gain_bits;
905 u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 };
906 u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 };
909 u8 rfseq_events[3] = { 6, 8, 7 };
910 u8 rfseq_delays[3] = { 10, 30, 1 };
912 if (dev->phy.rev >= 3) {
915 /* Set Clip 2 detect */
916 b43_phy_set(dev, B43_NPHY_C1_CGAINI,
917 B43_NPHY_C1_CGAINI_CL2DETECT);
918 b43_phy_set(dev, B43_NPHY_C2_CGAINI,
919 B43_NPHY_C2_CGAINI_CL2DETECT);
921 /* Set narrowband clip threshold */
922 b43_phy_set(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
923 b43_phy_set(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
925 if (!dev->phy.is_40mhz) {
926 /* Set dwell lengths */
927 b43_phy_set(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
928 b43_phy_set(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
929 b43_phy_set(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
930 b43_phy_set(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
933 /* Set wideband clip 2 threshold */
934 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
935 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2,
937 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
938 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2,
941 if (!dev->phy.is_40mhz) {
942 b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
943 ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1);
944 b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
945 ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1);
946 b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI,
947 ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1);
948 b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI,
949 ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1);
952 b43_phy_set(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
954 if (nphy->gain_boost) {
955 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ &&
961 code = dev->phy.is_40mhz ? 6 : 7;
964 /* Set HPVGA2 index */
965 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN,
966 ~B43_NPHY_C1_INITGAIN_HPVGA2,
967 code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
968 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN,
969 ~B43_NPHY_C2_INITGAIN_HPVGA2,
970 code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
972 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
973 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
975 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
978 b43_nphy_adjust_lna_gain_table(dev);
980 if (nphy->elna_gain_config) {
981 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808);
982 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
983 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
984 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
985 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
987 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08);
988 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
989 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
990 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
991 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
993 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
994 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
996 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1000 if (dev->phy.rev == 2) {
1001 for (i = 0; i < 4; i++) {
1002 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1003 (0x0400 * i) + 0x0020);
1004 for (j = 0; j < 21; j++)
1006 B43_NPHY_TABLE_DATALO, 3 * j);
1009 b43_nphy_set_rf_sequence(dev, 5,
1010 rfseq_events, rfseq_delays, 3);
1011 b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1,
1012 (u16)~B43_NPHY_OVER_DGAIN_CCKDGECV,
1013 0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT);
1015 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1016 b43_phy_maskset(dev, B43_PHY_N(0xC5D),
1022 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
1023 static void b43_nphy_workarounds(struct b43_wldev *dev)
1025 struct ssb_bus *bus = dev->dev->bus;
1026 struct b43_phy *phy = &dev->phy;
1027 struct b43_phy_n *nphy = phy->n;
1029 u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
1030 u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
1032 u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
1033 u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
1035 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1036 b43_nphy_classifier(dev, 1, 0);
1038 b43_nphy_classifier(dev, 1, 1);
1040 if (nphy->hang_avoid)
1041 b43_nphy_stay_in_carrier_search(dev, 1);
1043 b43_phy_set(dev, B43_NPHY_IQFLIP,
1044 B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
1046 if (dev->phy.rev >= 3) {
1049 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
1050 nphy->band5g_pwrgain) {
1051 b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
1052 b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
1054 b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
1055 b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
1058 /* TODO: convert to b43_ntab_write? */
1059 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2000);
1060 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x000A);
1061 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2010);
1062 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x000A);
1063 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2002);
1064 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0xCDAA);
1065 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2012);
1066 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0xCDAA);
1068 if (dev->phy.rev < 2) {
1069 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2008);
1070 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0000);
1071 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2018);
1072 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0000);
1073 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2007);
1074 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x7AAB);
1075 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2017);
1076 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x7AAB);
1077 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2006);
1078 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0800);
1079 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2016);
1080 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0800);
1083 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
1084 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
1085 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
1086 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
1088 if (bus->sprom.boardflags2_lo & 0x100 &&
1089 bus->boardinfo.type == 0x8B) {
1093 b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
1094 b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
1096 b43_nphy_gain_crtl_workarounds(dev);
1098 if (dev->phy.rev < 2) {
1099 if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
1100 ; /*TODO: b43_mhf(dev, 2, 0x0010, 0x0010, 3);*/
1101 } else if (dev->phy.rev == 2) {
1102 b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
1103 b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
1106 if (dev->phy.rev < 2)
1107 b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
1108 ~B43_NPHY_SCRAM_SIGCTL_SCM);
1110 /* Set phase track alpha and beta */
1111 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
1112 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
1113 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
1114 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
1115 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
1116 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
1118 b43_phy_mask(dev, B43_NPHY_PIL_DW1,
1119 (u16)~B43_NPHY_PIL_DW_64QAM);
1120 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
1121 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
1122 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
1124 if (dev->phy.rev == 2)
1125 b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
1126 B43_NPHY_FINERX2_CGC_DECGC);
1129 if (nphy->hang_avoid)
1130 b43_nphy_stay_in_carrier_search(dev, 0);
1133 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */
1134 static int b43_nphy_load_samples(struct b43_wldev *dev,
1135 struct b43_c32 *samples, u16 len) {
1136 struct b43_phy_n *nphy = dev->phy.n;
1140 data = kzalloc(len * sizeof(u32), GFP_KERNEL);
1142 b43err(dev->wl, "allocation for samples loading failed\n");
1145 if (nphy->hang_avoid)
1146 b43_nphy_stay_in_carrier_search(dev, 1);
1148 for (i = 0; i < len; i++) {
1149 data[i] = (samples[i].i & 0x3FF << 10);
1150 data[i] |= samples[i].q & 0x3FF;
1152 b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data);
1155 if (nphy->hang_avoid)
1156 b43_nphy_stay_in_carrier_search(dev, 0);
1160 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */
1161 static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
1165 u16 bw, len, rot, angle;
1166 struct b43_c32 *samples;
1169 bw = (dev->phy.is_40mhz) ? 40 : 20;
1173 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX)
1178 if (dev->phy.is_40mhz)
1184 samples = kzalloc(len * sizeof(struct b43_c32), GFP_KERNEL);
1186 b43err(dev->wl, "allocation for samples generation failed\n");
1189 rot = (((freq * 36) / bw) << 16) / 100;
1192 for (i = 0; i < len; i++) {
1193 samples[i] = b43_cordic(angle);
1195 samples[i].q = CORDIC_CONVERT(samples[i].q * max);
1196 samples[i].i = CORDIC_CONVERT(samples[i].i * max);
1199 i = b43_nphy_load_samples(dev, samples, len);
1201 return (i < 0) ? 0 : len;
1204 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */
1205 static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
1206 u16 wait, bool iqmode, bool dac_test)
1208 struct b43_phy_n *nphy = dev->phy.n;
1213 if (nphy->hang_avoid)
1214 b43_nphy_stay_in_carrier_search(dev, true);
1216 if ((nphy->bb_mult_save & 0x80000000) == 0) {
1217 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87));
1218 nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000;
1221 if (!dev->phy.is_40mhz)
1225 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
1227 if (nphy->hang_avoid)
1228 b43_nphy_stay_in_carrier_search(dev, false);
1230 b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1));
1232 if (loops != 0xFFFF)
1233 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1));
1235 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops);
1237 b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait);
1239 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1241 b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER);
1243 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1244 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000);
1247 b43_phy_write(dev, B43_NPHY_SAMP_CMD, 5);
1249 b43_phy_write(dev, B43_NPHY_SAMP_CMD, 1);
1251 for (i = 0; i < 100; i++) {
1252 if (b43_phy_read(dev, B43_NPHY_RFSEQST) & 1) {
1259 b43err(dev->wl, "run samples timeout\n");
1261 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1265 * Transmits a known value for LO calibration
1266 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone
1268 static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
1269 bool iqmode, bool dac_test)
1271 u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
1274 b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test);
1278 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
1279 static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
1281 struct b43_phy_n *nphy = dev->phy.n;
1284 u32 cur_real, cur_imag, real_part, imag_part;
1288 if (nphy->hang_avoid)
1289 b43_nphy_stay_in_carrier_search(dev, true);
1291 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
1293 for (i = 0; i < 2; i++) {
1294 tmp = ((buffer[i * 2] & 0x3FF) << 10) |
1295 (buffer[i * 2 + 1] & 0x3FF);
1296 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1297 (((i + 26) << 10) | 320));
1298 for (j = 0; j < 128; j++) {
1299 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
1300 ((tmp >> 16) & 0xFFFF));
1301 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1306 for (i = 0; i < 2; i++) {
1307 tmp = buffer[5 + i];
1308 real_part = (tmp >> 8) & 0xFF;
1309 imag_part = (tmp & 0xFF);
1310 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1311 (((i + 26) << 10) | 448));
1313 if (dev->phy.rev >= 3) {
1314 cur_real = real_part;
1315 cur_imag = imag_part;
1316 tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
1319 for (j = 0; j < 128; j++) {
1320 if (dev->phy.rev < 3) {
1321 cur_real = (real_part * loscale[j] + 128) >> 8;
1322 cur_imag = (imag_part * loscale[j] + 128) >> 8;
1323 tmp = ((cur_real & 0xFF) << 8) |
1326 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
1327 ((tmp >> 16) & 0xFFFF));
1328 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1333 if (dev->phy.rev >= 3) {
1334 b43_shm_write16(dev, B43_SHM_SHARED,
1335 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
1336 b43_shm_write16(dev, B43_SHM_SHARED,
1337 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
1340 if (nphy->hang_avoid)
1341 b43_nphy_stay_in_carrier_search(dev, false);
1344 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */
1345 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
1346 u8 *events, u8 *delays, u8 length)
1348 struct b43_phy_n *nphy = dev->phy.n;
1350 u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F;
1351 u16 offset1 = cmd << 4;
1352 u16 offset2 = offset1 + 0x80;
1354 if (nphy->hang_avoid)
1355 b43_nphy_stay_in_carrier_search(dev, true);
1357 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events);
1358 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays);
1360 for (i = length; i < 16; i++) {
1361 b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end);
1362 b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1);
1365 if (nphy->hang_avoid)
1366 b43_nphy_stay_in_carrier_search(dev, false);
1369 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
1370 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
1371 enum b43_nphy_rf_sequence seq)
1373 static const u16 trigger[] = {
1374 [B43_RFSEQ_RX2TX] = B43_NPHY_RFSEQTR_RX2TX,
1375 [B43_RFSEQ_TX2RX] = B43_NPHY_RFSEQTR_TX2RX,
1376 [B43_RFSEQ_RESET2RX] = B43_NPHY_RFSEQTR_RST2RX,
1377 [B43_RFSEQ_UPDATE_GAINH] = B43_NPHY_RFSEQTR_UPGH,
1378 [B43_RFSEQ_UPDATE_GAINL] = B43_NPHY_RFSEQTR_UPGL,
1379 [B43_RFSEQ_UPDATE_GAINU] = B43_NPHY_RFSEQTR_UPGU,
1382 u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1384 B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
1386 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
1387 B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
1388 b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
1389 for (i = 0; i < 200; i++) {
1390 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
1394 b43err(dev->wl, "RF sequence status timeout\n");
1396 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1399 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
1400 static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
1401 u16 value, u8 core, bool off)
1404 u8 index = fls(field);
1405 u8 addr, en_addr, val_addr;
1406 /* we expect only one bit set */
1407 B43_WARN_ON(field & (~(1 << (index - 1))));
1409 if (dev->phy.rev >= 3) {
1410 const struct nphy_rf_control_override_rev3 *rf_ctrl;
1411 for (i = 0; i < 2; i++) {
1412 if (index == 0 || index == 16) {
1414 "Unsupported RF Ctrl Override call\n");
1418 rf_ctrl = &tbl_rf_control_override_rev3[index - 1];
1419 en_addr = B43_PHY_N((i == 0) ?
1420 rf_ctrl->en_addr0 : rf_ctrl->en_addr1);
1421 val_addr = B43_PHY_N((i == 0) ?
1422 rf_ctrl->val_addr0 : rf_ctrl->val_addr1);
1425 b43_phy_mask(dev, en_addr, ~(field));
1426 b43_phy_mask(dev, val_addr,
1427 ~(rf_ctrl->val_mask));
1429 if (core == 0 || ((1 << core) & i) != 0) {
1430 b43_phy_set(dev, en_addr, field);
1431 b43_phy_maskset(dev, val_addr,
1432 ~(rf_ctrl->val_mask),
1433 (value << rf_ctrl->val_shift));
1438 const struct nphy_rf_control_override_rev2 *rf_ctrl;
1440 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field));
1443 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field);
1446 for (i = 0; i < 2; i++) {
1447 if (index <= 1 || index == 16) {
1449 "Unsupported RF Ctrl Override call\n");
1453 if (index == 2 || index == 10 ||
1454 (index >= 13 && index <= 15)) {
1458 rf_ctrl = &tbl_rf_control_override_rev2[index - 2];
1459 addr = B43_PHY_N((i == 0) ?
1460 rf_ctrl->addr0 : rf_ctrl->addr1);
1462 if ((core & (1 << i)) != 0)
1463 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask),
1464 (value << rf_ctrl->shift));
1466 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
1467 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1468 B43_NPHY_RFCTL_CMD_START);
1470 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE);
1475 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */
1476 static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
1482 B43_WARN_ON(dev->phy.rev < 3);
1483 B43_WARN_ON(field > 4);
1485 for (i = 0; i < 2; i++) {
1486 if ((core == 1 && i == 1) || (core == 2 && !i))
1490 B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
1491 b43_phy_mask(dev, reg, 0xFBFF);
1495 b43_phy_write(dev, reg, 0);
1496 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
1500 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1,
1501 0xFC3F, (value << 6));
1502 b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1,
1504 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1505 B43_NPHY_RFCTL_CMD_START);
1506 for (j = 0; j < 100; j++) {
1507 if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START) {
1515 "intc override timeout\n");
1516 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1,
1519 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2,
1520 0xFC3F, (value << 6));
1521 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1523 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1524 B43_NPHY_RFCTL_CMD_RXTX);
1525 for (j = 0; j < 100; j++) {
1526 if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX) {
1534 "intc override timeout\n");
1535 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
1540 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1547 b43_phy_maskset(dev, reg, ~tmp, val);
1550 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1557 b43_phy_maskset(dev, reg, ~tmp, val);
1560 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1567 b43_phy_maskset(dev, reg, ~tmp, val);
1573 static void b43_nphy_bphy_init(struct b43_wldev *dev)
1579 for (i = 0; i < 14; i++) {
1580 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
1584 for (i = 0; i < 16; i++) {
1585 b43_phy_write(dev, B43_PHY_N_BMODE(0x97 + i), val);
1588 b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
1591 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
1592 static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
1593 s8 offset, u8 core, u8 rail, u8 type)
1596 bool core1or5 = (core == 1) || (core == 5);
1597 bool core2or5 = (core == 2) || (core == 5);
1599 offset = clamp_val(offset, -32, 31);
1600 tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
1602 if (core1or5 && (rail == 0) && (type == 2))
1603 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
1604 if (core1or5 && (rail == 1) && (type == 2))
1605 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
1606 if (core2or5 && (rail == 0) && (type == 2))
1607 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
1608 if (core2or5 && (rail == 1) && (type == 2))
1609 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
1610 if (core1or5 && (rail == 0) && (type == 0))
1611 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
1612 if (core1or5 && (rail == 1) && (type == 0))
1613 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
1614 if (core2or5 && (rail == 0) && (type == 0))
1615 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
1616 if (core2or5 && (rail == 1) && (type == 0))
1617 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
1618 if (core1or5 && (rail == 0) && (type == 1))
1619 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
1620 if (core1or5 && (rail == 1) && (type == 1))
1621 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
1622 if (core2or5 && (rail == 0) && (type == 1))
1623 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
1624 if (core2or5 && (rail == 1) && (type == 1))
1625 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
1626 if (core1or5 && (rail == 0) && (type == 6))
1627 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
1628 if (core1or5 && (rail == 1) && (type == 6))
1629 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
1630 if (core2or5 && (rail == 0) && (type == 6))
1631 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
1632 if (core2or5 && (rail == 1) && (type == 6))
1633 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
1634 if (core1or5 && (rail == 0) && (type == 3))
1635 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
1636 if (core1or5 && (rail == 1) && (type == 3))
1637 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
1638 if (core2or5 && (rail == 0) && (type == 3))
1639 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
1640 if (core2or5 && (rail == 1) && (type == 3))
1641 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
1642 if (core1or5 && (type == 4))
1643 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
1644 if (core2or5 && (type == 4))
1645 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
1646 if (core1or5 && (type == 5))
1647 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
1648 if (core2or5 && (type == 5))
1649 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
1652 static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1665 val = (val << 12) | (val << 14);
1666 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
1667 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
1670 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
1672 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
1676 /* TODO use some definitions */
1678 b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF, 0);
1680 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFEC7, 0);
1681 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xEFDC, 0);
1682 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFFFE, 0);
1684 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xFFFE, 0);
1687 b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF,
1690 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1692 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1693 0xEFDC, (code << 1 | 0x1021));
1694 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFFFE, 0x1);
1696 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xFFFE, 0);
1701 static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1703 struct b43_phy_n *nphy = dev->phy.n;
1708 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF);
1709 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF);
1710 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF);
1711 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF);
1712 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF);
1713 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF);
1714 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
1715 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
1717 for (i = 0; i < 2; i++) {
1718 if ((code == 1 && i == 1) || (code == 2 && !i))
1722 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
1723 b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
1727 B43_NPHY_AFECTL_C1 :
1729 b43_phy_maskset(dev, reg, 0xFCFF, 0);
1732 B43_NPHY_RFCTL_LUT_TRSW_UP1 :
1733 B43_NPHY_RFCTL_LUT_TRSW_UP2;
1734 b43_phy_maskset(dev, reg, 0xFFC3, 0);
1737 val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
1742 b43_phy_set(dev, reg, val);
1745 B43_NPHY_TXF_40CO_B1S0 :
1746 B43_NPHY_TXF_40CO_B32S1;
1747 b43_phy_set(dev, reg, 0x0020);
1757 B43_NPHY_AFECTL_C1 :
1760 b43_phy_maskset(dev, reg, 0xFCFF, val);
1761 b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
1763 if (type != 3 && type != 6) {
1764 enum ieee80211_band band =
1765 b43_current_band(dev->wl);
1767 if ((nphy->ipa2g_on &&
1768 band == IEEE80211_BAND_2GHZ) ||
1770 band == IEEE80211_BAND_5GHZ))
1771 val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
1774 reg = (i == 0) ? 0x2000 : 0x3000;
1775 reg |= B2055_PADDRV;
1776 b43_radio_write16(dev, reg, val);
1779 B43_NPHY_AFECTL_OVER1 :
1780 B43_NPHY_AFECTL_OVER;
1781 b43_phy_set(dev, reg, 0x0200);
1788 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
1789 static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1791 if (dev->phy.rev >= 3)
1792 b43_nphy_rev3_rssi_select(dev, code, type);
1794 b43_nphy_rev2_rssi_select(dev, code, type);
1797 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
1798 static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf)
1801 for (i = 0; i < 2; i++) {
1804 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
1806 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1809 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
1811 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1812 0xFC, buf[2 * i + 1]);
1816 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1819 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1820 0xF3, buf[2 * i + 1] << 2);
1825 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
1826 static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
1831 u16 save_regs_phy[9];
1834 if (dev->phy.rev >= 3) {
1835 save_regs_phy[0] = b43_phy_read(dev,
1836 B43_NPHY_RFCTL_LUT_TRSW_UP1);
1837 save_regs_phy[1] = b43_phy_read(dev,
1838 B43_NPHY_RFCTL_LUT_TRSW_UP2);
1839 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1840 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1841 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
1842 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1843 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
1844 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
1847 b43_nphy_rssi_select(dev, 5, type);
1849 if (dev->phy.rev < 2) {
1850 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
1851 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
1854 for (i = 0; i < 4; i++)
1857 for (i = 0; i < nsamp; i++) {
1858 if (dev->phy.rev < 2) {
1859 s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
1860 s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
1862 s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
1863 s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
1866 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
1867 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
1868 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
1869 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
1871 out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
1872 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
1874 if (dev->phy.rev < 2)
1875 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
1877 if (dev->phy.rev >= 3) {
1878 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
1880 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
1882 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[2]);
1883 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[3]);
1884 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
1885 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
1886 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
1887 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
1893 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
1894 static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
1899 u16 class, override;
1900 u8 regs_save_radio[2];
1901 u16 regs_save_phy[2];
1905 u16 clip_off[2] = { 0xFFFF, 0xFFFF };
1906 s32 results_min[4] = { };
1907 u8 vcm_final[4] = { };
1908 s32 results[4][4] = { };
1909 s32 miniq[4][2] = { };
1914 } else if (type < 2) {
1922 class = b43_nphy_classifier(dev, 0, 0);
1923 b43_nphy_classifier(dev, 7, 4);
1924 b43_nphy_read_clip_detection(dev, clip_state);
1925 b43_nphy_write_clip_detection(dev, clip_off);
1927 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
1932 regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1933 regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX);
1934 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
1935 b43_radio_write16(dev, B2055_C1_PD_RXTX, val);
1937 regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1938 regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX);
1939 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
1940 b43_radio_write16(dev, B2055_C2_PD_RXTX, val);
1942 state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07;
1943 state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07;
1944 b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
1945 b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
1946 state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07;
1947 state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07;
1949 b43_nphy_rssi_select(dev, 5, type);
1950 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type);
1951 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type);
1953 for (i = 0; i < 4; i++) {
1955 for (j = 0; j < 4; j++)
1958 b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
1959 b43_nphy_poll_rssi(dev, type, results[i], 8);
1961 for (j = 0; j < 2; j++)
1962 miniq[i][j] = min(results[i][2 * j],
1963 results[i][2 * j + 1]);
1966 for (i = 0; i < 4; i++) {
1971 for (j = 0; j < 4; j++) {
1973 curr = abs(results[j][i]);
1975 curr = abs(miniq[j][i / 2] - code * 8);
1982 if (results[j][i] < minpoll)
1983 minpoll = results[j][i];
1985 results_min[i] = minpoll;
1986 vcm_final[i] = minvcm;
1990 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
1992 for (i = 0; i < 4; i++) {
1993 offset[i] = (code * 8) - results[vcm_final[i]][i];
1996 offset[i] = -((abs(offset[i]) + 4) / 8);
1998 offset[i] = (offset[i] + 4) / 8;
2000 if (results_min[i] == 248)
2001 offset[i] = code - 32;
2004 b43_nphy_scale_offset_rssi(dev, 0, offset[i], 1, 0,
2007 b43_nphy_scale_offset_rssi(dev, 0, offset[i], 2, 1,
2011 b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
2012 b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[1]);
2016 b43_nphy_rssi_select(dev, 1, 2);
2019 b43_nphy_rssi_select(dev, 1, 0);
2022 b43_nphy_rssi_select(dev, 1, 1);
2025 b43_nphy_rssi_select(dev, 1, 1);
2031 b43_nphy_rssi_select(dev, 2, 2);
2034 b43_nphy_rssi_select(dev, 2, 0);
2037 b43_nphy_rssi_select(dev, 2, 1);
2041 b43_nphy_rssi_select(dev, 0, type);
2043 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
2044 b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
2045 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
2046 b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
2048 b43_nphy_classifier(dev, 7, class);
2049 b43_nphy_write_clip_detection(dev, clip_state);
2052 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
2053 static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
2060 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
2062 static void b43_nphy_rssi_cal(struct b43_wldev *dev)
2064 if (dev->phy.rev >= 3) {
2065 b43_nphy_rev3_rssi_cal(dev);
2067 b43_nphy_rev2_rssi_cal(dev, 2);
2068 b43_nphy_rev2_rssi_cal(dev, 0);
2069 b43_nphy_rev2_rssi_cal(dev, 1);
2074 * Restore RSSI Calibration
2075 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
2077 static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
2079 struct b43_phy_n *nphy = dev->phy.n;
2081 u16 *rssical_radio_regs = NULL;
2082 u16 *rssical_phy_regs = NULL;
2084 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2085 if (b43_empty_chanspec(&nphy->rssical_chanspec_2G))
2087 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
2088 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
2090 if (b43_empty_chanspec(&nphy->rssical_chanspec_5G))
2092 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
2093 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
2096 /* TODO use some definitions */
2097 b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]);
2098 b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]);
2100 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
2101 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
2102 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
2103 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
2105 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
2106 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
2107 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
2108 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
2110 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
2111 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
2112 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
2113 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
2116 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */
2117 static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev)
2119 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2120 if (dev->phy.rev >= 6) {
2121 /* TODO If the chip is 47162
2122 return txpwrctrl_tx_gain_ipa_rev5 */
2123 return txpwrctrl_tx_gain_ipa_rev6;
2124 } else if (dev->phy.rev >= 5) {
2125 return txpwrctrl_tx_gain_ipa_rev5;
2127 return txpwrctrl_tx_gain_ipa;
2130 return txpwrctrl_tx_gain_ipa_5g;
2134 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
2135 static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
2137 struct b43_phy_n *nphy = dev->phy.n;
2138 u16 *save = nphy->tx_rx_cal_radio_saveregs;
2142 if (dev->phy.rev >= 3) {
2143 for (i = 0; i < 2; i++) {
2144 tmp = (i == 0) ? 0x2000 : 0x3000;
2147 save[offset + 0] = b43_radio_read16(dev, B2055_CAL_RVARCTL);
2148 save[offset + 1] = b43_radio_read16(dev, B2055_CAL_LPOCTL);
2149 save[offset + 2] = b43_radio_read16(dev, B2055_CAL_TS);
2150 save[offset + 3] = b43_radio_read16(dev, B2055_CAL_RCCALRTS);
2151 save[offset + 4] = b43_radio_read16(dev, B2055_CAL_RCALRTS);
2152 save[offset + 5] = b43_radio_read16(dev, B2055_PADDRV);
2153 save[offset + 6] = b43_radio_read16(dev, B2055_XOCTL1);
2154 save[offset + 7] = b43_radio_read16(dev, B2055_XOCTL2);
2155 save[offset + 8] = b43_radio_read16(dev, B2055_XOREGUL);
2156 save[offset + 9] = b43_radio_read16(dev, B2055_XOMISC);
2157 save[offset + 10] = b43_radio_read16(dev, B2055_PLL_LFC1);
2159 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2160 b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x0A);
2161 b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2162 b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2163 b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2164 b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2165 if (nphy->ipa5g_on) {
2166 b43_radio_write16(dev, tmp | B2055_PADDRV, 4);
2167 b43_radio_write16(dev, tmp | B2055_XOCTL1, 1);
2169 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2170 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0x2F);
2172 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2174 b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x06);
2175 b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2176 b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2177 b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2178 b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2179 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0);
2180 if (nphy->ipa2g_on) {
2181 b43_radio_write16(dev, tmp | B2055_PADDRV, 6);
2182 b43_radio_write16(dev, tmp | B2055_XOCTL2,
2183 (dev->phy.rev < 5) ? 0x11 : 0x01);
2185 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2186 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2189 b43_radio_write16(dev, tmp | B2055_XOREGUL, 0);
2190 b43_radio_write16(dev, tmp | B2055_XOMISC, 0);
2191 b43_radio_write16(dev, tmp | B2055_PLL_LFC1, 0);
2194 save[0] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL1);
2195 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
2197 save[1] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL2);
2198 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
2200 save[2] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL1);
2201 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
2203 save[3] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL2);
2204 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
2206 save[3] = b43_radio_read16(dev, B2055_C1_PWRDET_RXTX);
2207 save[4] = b43_radio_read16(dev, B2055_C2_PWRDET_RXTX);
2209 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
2210 B43_NPHY_BANDCTL_5GHZ)) {
2211 b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x04);
2212 b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x04);
2214 b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x20);
2215 b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x20);
2218 if (dev->phy.rev < 2) {
2219 b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
2220 b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
2222 b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
2223 b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
2228 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
2229 static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
2230 struct nphy_txgains target,
2231 struct nphy_iqcal_params *params)
2236 if (dev->phy.rev >= 3) {
2237 params->txgm = target.txgm[core];
2238 params->pga = target.pga[core];
2239 params->pad = target.pad[core];
2240 params->ipa = target.ipa[core];
2241 params->cal_gain = (params->txgm << 12) | (params->pga << 8) |
2242 (params->pad << 4) | (params->ipa);
2243 for (j = 0; j < 5; j++)
2244 params->ncorr[j] = 0x79;
2246 gain = (target.pad[core]) | (target.pga[core] << 4) |
2247 (target.txgm[core] << 8);
2249 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
2251 for (i = 0; i < 9; i++)
2252 if (tbl_iqcal_gainparams[indx][i][0] == gain)
2256 params->txgm = tbl_iqcal_gainparams[indx][i][1];
2257 params->pga = tbl_iqcal_gainparams[indx][i][2];
2258 params->pad = tbl_iqcal_gainparams[indx][i][3];
2259 params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
2261 for (j = 0; j < 4; j++)
2262 params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
2266 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
2267 static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
2269 struct b43_phy_n *nphy = dev->phy.n;
2273 u16 tmp = nphy->txcal_bbmult;
2278 for (i = 0; i < 18; i++) {
2279 scale = (ladder_lo[i].percent * tmp) / 100;
2280 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
2281 b43_ntab_write(dev, B43_NTAB16(15, i), entry);
2283 scale = (ladder_iq[i].percent * tmp) / 100;
2284 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
2285 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry);
2289 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */
2290 static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev)
2293 for (i = 0; i < 15; i++)
2294 b43_phy_write(dev, B43_PHY_N(0x2C5 + i),
2295 tbl_tx_filter_coef_rev4[2][i]);
2298 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */
2299 static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
2302 /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */
2303 u16 offset[] = { 0x186, 0x195, 0x2C5 };
2305 for (i = 0; i < 3; i++)
2306 for (j = 0; j < 15; j++)
2307 b43_phy_write(dev, B43_PHY_N(offset[i] + j),
2308 tbl_tx_filter_coef_rev4[i][j]);
2310 if (dev->phy.is_40mhz) {
2311 for (j = 0; j < 15; j++)
2312 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2313 tbl_tx_filter_coef_rev4[3][j]);
2314 } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2315 for (j = 0; j < 15; j++)
2316 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2317 tbl_tx_filter_coef_rev4[5][j]);
2320 if (dev->phy.channel == 14)
2321 for (j = 0; j < 15; j++)
2322 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2323 tbl_tx_filter_coef_rev4[6][j]);
2326 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
2327 static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
2329 struct b43_phy_n *nphy = dev->phy.n;
2332 struct nphy_txgains target;
2333 const u32 *table = NULL;
2335 if (nphy->txpwrctrl == 0) {
2338 if (nphy->hang_avoid)
2339 b43_nphy_stay_in_carrier_search(dev, true);
2340 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain);
2341 if (nphy->hang_avoid)
2342 b43_nphy_stay_in_carrier_search(dev, false);
2344 for (i = 0; i < 2; ++i) {
2345 if (dev->phy.rev >= 3) {
2346 target.ipa[i] = curr_gain[i] & 0x000F;
2347 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
2348 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
2349 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
2351 target.ipa[i] = curr_gain[i] & 0x0003;
2352 target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
2353 target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
2354 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
2360 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
2361 B43_NPHY_TXPCTL_STAT_BIDX) >>
2362 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
2363 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
2364 B43_NPHY_TXPCTL_STAT_BIDX) >>
2365 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
2367 for (i = 0; i < 2; ++i) {
2368 if (dev->phy.rev >= 3) {
2369 enum ieee80211_band band =
2370 b43_current_band(dev->wl);
2372 if ((nphy->ipa2g_on &&
2373 band == IEEE80211_BAND_2GHZ) ||
2375 band == IEEE80211_BAND_5GHZ)) {
2376 table = b43_nphy_get_ipa_gain_table(dev);
2378 if (band == IEEE80211_BAND_5GHZ) {
2379 if (dev->phy.rev == 3)
2380 table = b43_ntab_tx_gain_rev3_5ghz;
2381 else if (dev->phy.rev == 4)
2382 table = b43_ntab_tx_gain_rev4_5ghz;
2384 table = b43_ntab_tx_gain_rev5plus_5ghz;
2386 table = b43_ntab_tx_gain_rev3plus_2ghz;
2390 target.ipa[i] = (table[index[i]] >> 16) & 0xF;
2391 target.pad[i] = (table[index[i]] >> 20) & 0xF;
2392 target.pga[i] = (table[index[i]] >> 24) & 0xF;
2393 target.txgm[i] = (table[index[i]] >> 28) & 0xF;
2395 table = b43_ntab_tx_gain_rev0_1_2;
2397 target.ipa[i] = (table[index[i]] >> 16) & 0x3;
2398 target.pad[i] = (table[index[i]] >> 18) & 0x3;
2399 target.pga[i] = (table[index[i]] >> 20) & 0x7;
2400 target.txgm[i] = (table[index[i]] >> 23) & 0x7;
2408 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
2409 static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
2411 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2413 if (dev->phy.rev >= 3) {
2414 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
2415 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
2416 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
2417 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
2418 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
2419 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]);
2420 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]);
2421 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
2422 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
2423 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
2424 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
2425 b43_nphy_reset_cca(dev);
2427 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
2428 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
2429 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
2430 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]);
2431 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]);
2432 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
2433 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
2437 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
2438 static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
2440 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2443 regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2444 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2445 if (dev->phy.rev >= 3) {
2446 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
2447 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
2449 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
2451 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
2453 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2455 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
2457 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
2458 b43_phy_mask(dev, B43_NPHY_BBCFG, (u16)~B43_NPHY_BBCFG_RSTRX);
2460 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3));
2462 b43_ntab_write(dev, B43_NTAB16(8, 3), 0);
2464 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19));
2466 b43_ntab_write(dev, B43_NTAB16(8, 19), 0);
2467 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2468 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2470 b43_nphy_rf_control_intc_override(dev, 2, 1, 3);
2471 b43_nphy_rf_control_intc_override(dev, 1, 2, 1);
2472 b43_nphy_rf_control_intc_override(dev, 1, 8, 2);
2474 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
2475 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
2476 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
2477 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
2479 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
2480 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
2481 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2483 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
2484 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2));
2487 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp);
2488 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18));
2491 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp);
2492 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2493 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2494 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
2498 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
2499 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
2503 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */
2504 static void b43_nphy_save_cal(struct b43_wldev *dev)
2506 struct b43_phy_n *nphy = dev->phy.n;
2508 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
2509 u16 *txcal_radio_regs = NULL;
2510 struct b43_chanspec *iqcal_chanspec;
2513 if (nphy->hang_avoid)
2514 b43_nphy_stay_in_carrier_search(dev, 1);
2516 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2517 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
2518 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
2519 iqcal_chanspec = &nphy->iqcal_chanspec_2G;
2520 table = nphy->cal_cache.txcal_coeffs_2G;
2522 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
2523 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
2524 iqcal_chanspec = &nphy->iqcal_chanspec_5G;
2525 table = nphy->cal_cache.txcal_coeffs_5G;
2528 b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs);
2529 /* TODO use some definitions */
2530 if (dev->phy.rev >= 3) {
2531 txcal_radio_regs[0] = b43_radio_read(dev, 0x2021);
2532 txcal_radio_regs[1] = b43_radio_read(dev, 0x2022);
2533 txcal_radio_regs[2] = b43_radio_read(dev, 0x3021);
2534 txcal_radio_regs[3] = b43_radio_read(dev, 0x3022);
2535 txcal_radio_regs[4] = b43_radio_read(dev, 0x2023);
2536 txcal_radio_regs[5] = b43_radio_read(dev, 0x2024);
2537 txcal_radio_regs[6] = b43_radio_read(dev, 0x3023);
2538 txcal_radio_regs[7] = b43_radio_read(dev, 0x3024);
2540 txcal_radio_regs[0] = b43_radio_read(dev, 0x8B);
2541 txcal_radio_regs[1] = b43_radio_read(dev, 0xBA);
2542 txcal_radio_regs[2] = b43_radio_read(dev, 0x8D);
2543 txcal_radio_regs[3] = b43_radio_read(dev, 0xBC);
2545 *iqcal_chanspec = nphy->radio_chanspec;
2546 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 8, table);
2548 if (nphy->hang_avoid)
2549 b43_nphy_stay_in_carrier_search(dev, 0);
2552 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
2553 static void b43_nphy_restore_cal(struct b43_wldev *dev)
2555 struct b43_phy_n *nphy = dev->phy.n;
2562 u16 *txcal_radio_regs = NULL;
2563 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
2565 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2566 if (b43_empty_chanspec(&nphy->iqcal_chanspec_2G))
2568 table = nphy->cal_cache.txcal_coeffs_2G;
2569 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
2571 if (b43_empty_chanspec(&nphy->iqcal_chanspec_5G))
2573 table = nphy->cal_cache.txcal_coeffs_5G;
2574 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
2577 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table);
2579 for (i = 0; i < 4; i++) {
2580 if (dev->phy.rev >= 3)
2586 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef);
2587 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft);
2588 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft);
2590 if (dev->phy.rev < 2)
2591 b43_nphy_tx_iq_workaround(dev);
2593 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2594 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
2595 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
2597 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
2598 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
2601 /* TODO use some definitions */
2602 if (dev->phy.rev >= 3) {
2603 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
2604 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
2605 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
2606 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
2607 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
2608 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
2609 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
2610 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
2612 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
2613 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
2614 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
2615 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
2617 b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
2620 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
2621 static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
2622 struct nphy_txgains target,
2623 bool full, bool mphase)
2625 struct b43_phy_n *nphy = dev->phy.n;
2631 u16 tmp, core, type, count, max, numb, last, cmd;
2639 struct nphy_iqcal_params params[2];
2640 bool updated[2] = { };
2642 b43_nphy_stay_in_carrier_search(dev, true);
2644 if (dev->phy.rev >= 4) {
2645 avoid = nphy->hang_avoid;
2646 nphy->hang_avoid = 0;
2649 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
2651 for (i = 0; i < 2; i++) {
2652 b43_nphy_iq_cal_gain_params(dev, i, target, ¶ms[i]);
2653 gain[i] = params[i].cal_gain;
2656 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain);
2658 b43_nphy_tx_cal_radio_setup(dev);
2659 b43_nphy_tx_cal_phy_setup(dev);
2661 phy6or5x = dev->phy.rev >= 6 ||
2662 (dev->phy.rev == 5 && nphy->ipa2g_on &&
2663 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
2665 if (dev->phy.is_40mhz) {
2666 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
2667 tbl_tx_iqlo_cal_loft_ladder_40);
2668 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
2669 tbl_tx_iqlo_cal_iqimb_ladder_40);
2671 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
2672 tbl_tx_iqlo_cal_loft_ladder_20);
2673 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
2674 tbl_tx_iqlo_cal_iqimb_ladder_20);
2678 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
2680 if (!dev->phy.is_40mhz)
2685 if (nphy->mphase_cal_phase_id > 2)
2686 b43_nphy_run_samples(dev, (dev->phy.is_40mhz ? 40 : 20) * 8,
2687 0xFFFF, 0, true, false);
2689 error = b43_nphy_tx_tone(dev, freq, 250, true, false);
2692 if (nphy->mphase_cal_phase_id > 2) {
2693 table = nphy->mphase_txcal_bestcoeffs;
2695 if (dev->phy.rev < 3)
2698 if (!full && nphy->txiqlocal_coeffsvalid) {
2699 table = nphy->txiqlocal_bestc;
2701 if (dev->phy.rev < 3)
2705 if (dev->phy.rev >= 3) {
2706 table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
2707 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
2709 table = tbl_tx_iqlo_cal_startcoefs;
2710 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
2715 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table);
2718 if (dev->phy.rev >= 3)
2719 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
2721 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
2723 if (dev->phy.rev >= 3)
2724 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
2726 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
2730 count = nphy->mphase_txcal_cmdidx;
2732 (u16)(count + nphy->mphase_txcal_numcmds));
2738 for (; count < numb; count++) {
2740 if (dev->phy.rev >= 3)
2741 cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
2743 cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
2745 if (dev->phy.rev >= 3)
2746 cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
2748 cmd = tbl_tx_iqlo_cal_cmds_recal[count];
2751 core = (cmd & 0x3000) >> 12;
2752 type = (cmd & 0x0F00) >> 8;
2754 if (phy6or5x && updated[core] == 0) {
2755 b43_nphy_update_tx_cal_ladder(dev, core);
2759 tmp = (params[core].ncorr[type] << 8) | 0x66;
2760 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
2762 if (type == 1 || type == 3 || type == 4) {
2763 buffer[0] = b43_ntab_read(dev,
2764 B43_NTAB16(15, 69 + core));
2765 diq_start = buffer[0];
2767 b43_ntab_write(dev, B43_NTAB16(15, 69 + core),
2771 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
2772 for (i = 0; i < 2000; i++) {
2773 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
2779 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
2781 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length,
2784 if (type == 1 || type == 3 || type == 4)
2785 buffer[0] = diq_start;
2789 nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
2791 last = (dev->phy.rev < 3) ? 6 : 7;
2793 if (!mphase || nphy->mphase_cal_phase_id == last) {
2794 b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer);
2795 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer);
2796 if (dev->phy.rev < 3) {
2802 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
2804 b43_ntab_read_bulk(dev, B43_NTAB16(15, 101), 2,
2806 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
2808 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
2811 if (dev->phy.rev < 3)
2813 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
2814 nphy->txiqlocal_bestc);
2815 nphy->txiqlocal_coeffsvalid = true;
2816 nphy->txiqlocal_chanspec = nphy->radio_chanspec;
2819 if (dev->phy.rev < 3)
2821 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
2822 nphy->mphase_txcal_bestcoeffs);
2825 b43_nphy_stop_playback(dev);
2826 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
2829 b43_nphy_tx_cal_phy_cleanup(dev);
2830 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
2832 if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
2833 b43_nphy_tx_iq_workaround(dev);
2835 if (dev->phy.rev >= 4)
2836 nphy->hang_avoid = avoid;
2838 b43_nphy_stay_in_carrier_search(dev, false);
2843 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */
2844 static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev)
2846 struct b43_phy_n *nphy = dev->phy.n;
2851 if (!nphy->txiqlocal_coeffsvalid ||
2852 b43_eq_chanspecs(&nphy->txiqlocal_chanspec, &nphy->radio_chanspec))
2855 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
2856 for (i = 0; i < 4; i++) {
2857 if (buffer[i] != nphy->txiqlocal_bestc[i]) {
2864 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4,
2865 nphy->txiqlocal_bestc);
2866 for (i = 0; i < 4; i++)
2868 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
2870 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
2871 &nphy->txiqlocal_bestc[5]);
2872 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
2873 &nphy->txiqlocal_bestc[5]);
2877 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
2878 static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
2879 struct nphy_txgains target, u8 type, bool debug)
2881 struct b43_phy_n *nphy = dev->phy.n;
2886 u16 cur_hpf1, cur_hpf2, cur_lna;
2888 enum ieee80211_band band;
2892 u16 lna[3] = { 3, 3, 1 };
2893 u16 hpf1[3] = { 7, 2, 0 };
2894 u16 hpf2[3] = { 2, 0, 0 };
2898 struct nphy_iqcal_params cal_params[2];
2899 struct nphy_iq_est est;
2901 bool playtone = true;
2904 b43_nphy_stay_in_carrier_search(dev, 1);
2906 if (dev->phy.rev < 2)
2907 b43_nphy_reapply_tx_cal_coeffs(dev);
2908 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
2909 for (i = 0; i < 2; i++) {
2910 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
2911 cal_gain[i] = cal_params[i].cal_gain;
2913 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain);
2915 for (i = 0; i < 2; i++) {
2917 rfctl[0] = B43_NPHY_RFCTL_INTC1;
2918 rfctl[1] = B43_NPHY_RFCTL_INTC2;
2919 afectl_core = B43_NPHY_AFECTL_C1;
2921 rfctl[0] = B43_NPHY_RFCTL_INTC2;
2922 rfctl[1] = B43_NPHY_RFCTL_INTC1;
2923 afectl_core = B43_NPHY_AFECTL_C2;
2926 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
2927 tmp[2] = b43_phy_read(dev, afectl_core);
2928 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2929 tmp[4] = b43_phy_read(dev, rfctl[0]);
2930 tmp[5] = b43_phy_read(dev, rfctl[1]);
2932 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
2933 (u16)~B43_NPHY_RFSEQCA_RXDIS,
2934 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
2935 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
2937 b43_phy_set(dev, afectl_core, 0x0006);
2938 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
2940 band = b43_current_band(dev->wl);
2942 if (nphy->rxcalparams & 0xFF000000) {
2943 if (band == IEEE80211_BAND_5GHZ)
2944 b43_phy_write(dev, rfctl[0], 0x140);
2946 b43_phy_write(dev, rfctl[0], 0x110);
2948 if (band == IEEE80211_BAND_5GHZ)
2949 b43_phy_write(dev, rfctl[0], 0x180);
2951 b43_phy_write(dev, rfctl[0], 0x120);
2954 if (band == IEEE80211_BAND_5GHZ)
2955 b43_phy_write(dev, rfctl[1], 0x148);
2957 b43_phy_write(dev, rfctl[1], 0x114);
2959 if (nphy->rxcalparams & 0x10000) {
2960 b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
2962 b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
2966 for (j = 0; i < 4; j++) {
2972 if (power[1] > 10000) {
2977 if (power[0] > 10000) {
2987 cur_lna = lna[index];
2988 cur_hpf1 = hpf1[index];
2989 cur_hpf2 = hpf2[index];
2990 cur_hpf += desired - hweight32(power[index]);
2991 cur_hpf = clamp_val(cur_hpf, 0, 10);
2998 tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
3000 b43_nphy_rf_control_override(dev, 0x400, tmp[0], 3,
3002 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3003 b43_nphy_stop_playback(dev);
3006 ret = b43_nphy_tx_tone(dev, 4000,
3007 (nphy->rxcalparams & 0xFFFF),
3011 b43_nphy_run_samples(dev, 160, 0xFFFF, 0,
3017 b43_nphy_rx_iq_est(dev, &est, 1024, 32,
3026 power[i] = ((real + imag) / 1024) + 1;
3028 b43_nphy_calc_rx_iq_comp(dev, 1 << i);
3030 b43_nphy_stop_playback(dev);
3037 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
3038 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
3039 b43_phy_write(dev, rfctl[1], tmp[5]);
3040 b43_phy_write(dev, rfctl[0], tmp[4]);
3041 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
3042 b43_phy_write(dev, afectl_core, tmp[2]);
3043 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
3049 b43_nphy_rf_control_override(dev, 0x400, 0, 3, true);
3050 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3051 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
3053 b43_nphy_stay_in_carrier_search(dev, 0);
3058 static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
3059 struct nphy_txgains target, u8 type, bool debug)
3064 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
3065 static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
3066 struct nphy_txgains target, u8 type, bool debug)
3068 if (dev->phy.rev >= 3)
3069 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
3071 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
3076 * http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N
3078 int b43_phy_initn(struct b43_wldev *dev)
3080 struct ssb_bus *bus = dev->dev->bus;
3081 struct b43_phy *phy = &dev->phy;
3082 struct b43_phy_n *nphy = phy->n;
3084 struct nphy_txgains target;
3086 enum ieee80211_band tmp2;
3090 bool do_cal = false;
3092 if ((dev->phy.rev >= 3) &&
3093 (bus->sprom.boardflags_lo & B43_BFL_EXTLNA) &&
3094 (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
3095 chipco_set32(&dev->dev->bus->chipco, SSB_CHIPCO_CHIPCTL, 0x40);
3097 nphy->deaf_count = 0;
3098 b43_nphy_tables_init(dev);
3099 nphy->crsminpwr_adjusted = false;
3100 nphy->noisevars_adjusted = false;
3102 /* Clear all overrides */
3103 if (dev->phy.rev >= 3) {
3104 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
3105 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
3106 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
3107 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
3109 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
3111 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
3112 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
3113 if (dev->phy.rev < 6) {
3114 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
3115 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
3117 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
3118 ~(B43_NPHY_RFSEQMODE_CAOVER |
3119 B43_NPHY_RFSEQMODE_TROVER));
3120 if (dev->phy.rev >= 3)
3121 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
3122 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
3124 if (dev->phy.rev <= 2) {
3125 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
3126 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
3127 ~B43_NPHY_BPHY_CTL3_SCALE,
3128 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
3130 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
3131 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
3133 if (bus->sprom.boardflags2_lo & 0x100 ||
3134 (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
3135 bus->boardinfo.type == 0x8B))
3136 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
3138 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
3139 b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
3140 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
3141 b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
3143 b43_nphy_update_mimo_config(dev, nphy->preamble_override);
3144 b43_nphy_update_txrx_chain(dev);
3147 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
3148 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
3151 tmp2 = b43_current_band(dev->wl);
3152 if ((nphy->ipa2g_on && tmp2 == IEEE80211_BAND_2GHZ) ||
3153 (nphy->ipa5g_on && tmp2 == IEEE80211_BAND_5GHZ)) {
3154 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
3155 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
3156 nphy->papd_epsilon_offset[0] << 7);
3157 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
3158 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
3159 nphy->papd_epsilon_offset[1] << 7);
3160 b43_nphy_int_pa_set_tx_dig_filters(dev);
3161 } else if (phy->rev >= 5) {
3162 b43_nphy_ext_pa_set_tx_dig_filters(dev);
3165 b43_nphy_workarounds(dev);
3167 /* Reset CCA, in init code it differs a little from standard way */
3168 b43_nphy_bmac_clock_fgc(dev, 1);
3169 tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
3170 b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
3171 b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
3172 b43_nphy_bmac_clock_fgc(dev, 0);
3174 /* TODO N PHY MAC PHY Clock Set with argument 1 */
3176 b43_nphy_pa_override(dev, false);
3177 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
3178 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3179 b43_nphy_pa_override(dev, true);
3181 b43_nphy_classifier(dev, 0, 0);
3182 b43_nphy_read_clip_detection(dev, clip);
3183 tx_pwr_state = nphy->txpwrctrl;
3184 /* TODO N PHY TX power control with argument 0
3185 (turning off power control) */
3186 /* TODO Fix the TX Power Settings */
3187 /* TODO N PHY TX Power Control Idle TSSI */
3188 /* TODO N PHY TX Power Control Setup */
3190 if (phy->rev >= 3) {
3193 b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128,
3194 b43_ntab_tx_gain_rev0_1_2);
3195 b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128,
3196 b43_ntab_tx_gain_rev0_1_2);
3199 if (nphy->phyrxchain != 3)
3200 ;/* TODO N PHY RX Core Set State with phyrxchain as argument */
3201 if (nphy->mphase_cal_phase_id > 0)
3202 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
3204 do_rssi_cal = false;
3205 if (phy->rev >= 3) {
3206 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3208 b43_empty_chanspec(&nphy->rssical_chanspec_2G);
3211 b43_empty_chanspec(&nphy->rssical_chanspec_5G);
3214 b43_nphy_rssi_cal(dev);
3216 b43_nphy_restore_rssi_cal(dev);
3218 b43_nphy_rssi_cal(dev);
3221 if (!((nphy->measure_hold & 0x6) != 0)) {
3222 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3223 do_cal = b43_empty_chanspec(&nphy->iqcal_chanspec_2G);
3225 do_cal = b43_empty_chanspec(&nphy->iqcal_chanspec_5G);
3231 target = b43_nphy_get_tx_gains(dev);
3233 if (nphy->antsel_type == 2)
3234 b43_nphy_superswitch_init(dev, true);
3235 if (nphy->perical != 2) {
3236 b43_nphy_rssi_cal(dev);
3237 if (phy->rev >= 3) {
3238 nphy->cal_orig_pwr_idx[0] =
3239 nphy->txpwrindex[0].index_internal;
3240 nphy->cal_orig_pwr_idx[1] =
3241 nphy->txpwrindex[1].index_internal;
3242 /* TODO N PHY Pre Calibrate TX Gain */
3243 target = b43_nphy_get_tx_gains(dev);
3249 if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false)) {
3250 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
3251 b43_nphy_save_cal(dev);
3252 else if (nphy->mphase_cal_phase_id == 0)
3253 ;/* N PHY Periodic Calibration with argument 3 */
3255 b43_nphy_restore_cal(dev);
3258 b43_nphy_tx_pwr_ctrl_coef_setup(dev);
3259 /* TODO N PHY TX Power Control Enable with argument tx_pwr_state */
3260 b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
3261 b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
3262 if (phy->rev >= 3 && phy->rev <= 6)
3263 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
3264 b43_nphy_tx_lp_fbw(dev);
3266 b43_nphy_spur_workaround(dev);
3268 b43err(dev->wl, "IEEE 802.11n devices are not supported, yet.\n");
3272 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ChanspecSetup */
3273 static void b43_nphy_chanspec_setup(struct b43_wldev *dev,
3274 const struct b43_phy_n_sfo_cfg *e,
3275 struct b43_chanspec chanspec)
3277 struct b43_phy *phy = &dev->phy;
3278 struct b43_phy_n *nphy = dev->phy.n;
3283 tmp = b43_phy_read(dev, B43_NPHY_BANDCTL) & B43_NPHY_BANDCTL_5GHZ;
3284 if (chanspec.b_freq == 1 && tmp == 0) {
3285 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
3286 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
3287 b43_phy_set(dev, B43_PHY_B_BBCFG, 0xC000);
3288 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
3289 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
3290 } else if (chanspec.b_freq == 1) {
3291 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
3292 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
3293 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
3294 b43_phy_mask(dev, B43_PHY_B_BBCFG, (u16)~0xC000);
3295 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
3298 b43_chantab_phy_upload(dev, e);
3300 tmp = chanspec.channel;
3301 if (chanspec.b_freq == 1)
3303 if (chanspec.b_width == 3)
3305 b43_shm_write16(dev, B43_SHM_SHARED, 0xA0, tmp);
3307 if (nphy->radio_chanspec.channel == 14) {
3308 b43_nphy_classifier(dev, 2, 0);
3309 b43_phy_set(dev, B43_PHY_B_TEST, 0x0800);
3311 b43_nphy_classifier(dev, 2, 2);
3312 if (chanspec.b_freq == 2)
3313 b43_phy_mask(dev, B43_PHY_B_TEST, ~0x840);
3316 if (nphy->txpwrctrl)
3317 b43_nphy_tx_power_fix(dev);
3319 if (dev->phy.rev < 3)
3320 b43_nphy_adjust_lna_gain_table(dev);
3322 b43_nphy_tx_lp_fbw(dev);
3324 if (dev->phy.rev >= 3 && 0) {
3328 b43_phy_write(dev, B43_NPHY_NDATAT_DUP40, 0x3830);
3331 b43_nphy_spur_workaround(dev);
3334 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetChanspec */
3335 static int b43_nphy_set_chanspec(struct b43_wldev *dev,
3336 struct b43_chanspec chanspec)
3338 struct b43_phy_n *nphy = dev->phy.n;
3340 const struct b43_nphy_channeltab_entry_rev2 *tabent_r2;
3341 const struct b43_nphy_channeltab_entry_rev3 *tabent_r3;
3344 u8 channel = chanspec.channel;
3346 if (dev->phy.rev >= 3) {
3352 tabent_r2 = b43_nphy_get_chantabent_rev2(dev, channel);
3357 nphy->radio_chanspec = chanspec;
3359 if (chanspec.b_width != nphy->b_width)
3360 ; /* TODO: BMAC BW Set (chanspec.b_width) */
3362 /* TODO: use defines */
3363 if (chanspec.b_width == 3) {
3364 if (chanspec.sideband == 2)
3365 b43_phy_set(dev, B43_NPHY_RXCTL,
3366 B43_NPHY_RXCTL_BSELU20);
3368 b43_phy_mask(dev, B43_NPHY_RXCTL,
3369 ~B43_NPHY_RXCTL_BSELU20);
3372 if (dev->phy.rev >= 3) {
3373 tmp = (chanspec.b_freq == 1) ? 4 : 0;
3374 b43_radio_maskset(dev, 0x08, 0xFFFB, tmp);
3375 /* TODO: PHY Radio2056 Setup (dev, tabent_r3); */
3376 b43_nphy_chanspec_setup(dev, &(tabent_r3->phy_regs), chanspec);
3378 tmp = (chanspec.b_freq == 1) ? 0x0020 : 0x0050;
3379 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, tmp);
3380 b43_radio_2055_setup(dev, tabent_r2);
3381 b43_nphy_chanspec_setup(dev, &(tabent_r2->phy_regs), chanspec);
3387 /* Tune the hardware to a new channel */
3388 static int nphy_channel_switch(struct b43_wldev *dev, unsigned int channel)
3390 struct b43_phy_n *nphy = dev->phy.n;
3392 struct b43_chanspec chanspec;
3393 chanspec = nphy->radio_chanspec;
3394 chanspec.channel = channel;
3396 return b43_nphy_set_chanspec(dev, chanspec);
3399 static int b43_nphy_op_allocate(struct b43_wldev *dev)
3401 struct b43_phy_n *nphy;
3403 nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
3411 static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
3413 struct b43_phy *phy = &dev->phy;
3414 struct b43_phy_n *nphy = phy->n;
3416 memset(nphy, 0, sizeof(*nphy));
3418 //TODO init struct b43_phy_n
3421 static void b43_nphy_op_free(struct b43_wldev *dev)
3423 struct b43_phy *phy = &dev->phy;
3424 struct b43_phy_n *nphy = phy->n;
3430 static int b43_nphy_op_init(struct b43_wldev *dev)
3432 return b43_phy_initn(dev);
3435 static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
3438 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
3439 /* OFDM registers are onnly available on A/G-PHYs */
3440 b43err(dev->wl, "Invalid OFDM PHY access at "
3441 "0x%04X on N-PHY\n", offset);
3444 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
3445 /* Ext-G registers are only available on G-PHYs */
3446 b43err(dev->wl, "Invalid EXT-G PHY access at "
3447 "0x%04X on N-PHY\n", offset);
3450 #endif /* B43_DEBUG */
3453 static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
3455 check_phyreg(dev, reg);
3456 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
3457 return b43_read16(dev, B43_MMIO_PHY_DATA);
3460 static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
3462 check_phyreg(dev, reg);
3463 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
3464 b43_write16(dev, B43_MMIO_PHY_DATA, value);
3467 static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
3469 /* Register 1 is a 32-bit register. */
3470 B43_WARN_ON(reg == 1);
3471 /* N-PHY needs 0x100 for read access */
3474 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
3475 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
3478 static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
3480 /* Register 1 is a 32-bit register. */
3481 B43_WARN_ON(reg == 1);
3483 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
3484 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
3487 /* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
3488 static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
3491 struct b43_phy_n *nphy = dev->phy.n;
3493 if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
3494 b43err(dev->wl, "MAC not suspended\n");
3497 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
3498 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
3499 if (dev->phy.rev >= 3) {
3500 b43_radio_mask(dev, 0x09, ~0x2);
3502 b43_radio_write(dev, 0x204D, 0);
3503 b43_radio_write(dev, 0x2053, 0);
3504 b43_radio_write(dev, 0x2058, 0);
3505 b43_radio_write(dev, 0x205E, 0);
3506 b43_radio_mask(dev, 0x2062, ~0xF0);
3507 b43_radio_write(dev, 0x2064, 0);
3509 b43_radio_write(dev, 0x304D, 0);
3510 b43_radio_write(dev, 0x3053, 0);
3511 b43_radio_write(dev, 0x3058, 0);
3512 b43_radio_write(dev, 0x305E, 0);
3513 b43_radio_mask(dev, 0x3062, ~0xF0);
3514 b43_radio_write(dev, 0x3064, 0);
3517 if (dev->phy.rev >= 3) {
3518 b43_radio_init2056(dev);
3519 b43_nphy_set_chanspec(dev, nphy->radio_chanspec);
3521 b43_radio_init2055(dev);
3526 static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
3528 b43_phy_write(dev, B43_NPHY_AFECTL_OVER,
3532 static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
3533 unsigned int new_channel)
3535 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3536 if ((new_channel < 1) || (new_channel > 14))
3539 if (new_channel > 200)
3543 return nphy_channel_switch(dev, new_channel);
3546 static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
3548 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3553 const struct b43_phy_operations b43_phyops_n = {
3554 .allocate = b43_nphy_op_allocate,
3555 .free = b43_nphy_op_free,
3556 .prepare_structs = b43_nphy_op_prepare_structs,
3557 .init = b43_nphy_op_init,
3558 .phy_read = b43_nphy_op_read,
3559 .phy_write = b43_nphy_op_write,
3560 .radio_read = b43_nphy_op_radio_read,
3561 .radio_write = b43_nphy_op_radio_write,
3562 .software_rfkill = b43_nphy_op_software_rfkill,
3563 .switch_analog = b43_nphy_op_switch_analog,
3564 .switch_channel = b43_nphy_op_switch_channel,
3565 .get_default_chan = b43_nphy_op_get_default_chan,
3566 .recalc_txpower = b43_nphy_op_recalc_txpower,
3567 .adjust_txpower = b43_nphy_op_adjust_txpower,