3 Broadcom B43 wireless driver
6 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
7 Copyright (c) 2005-2007 Stefano Brivio <stefano.brivio@polimi.it>
8 Copyright (c) 2005-2008 Michael Buesch <m@bues.ch>
9 Copyright (c) 2005, 2006 Danny van Dyk <kugelfang@gentoo.org>
10 Copyright (c) 2005, 2006 Andreas Jaggi <andreas.jaggi@waterwave.ch>
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; see the file COPYING. If not, write to
24 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
25 Boston, MA 02110-1301, USA.
29 #include "phy_common.h"
38 int b43_phy_allocate(struct b43_wldev *dev)
40 struct b43_phy *phy = &(dev->phy);
47 phy->ops = &b43_phyops_a;
50 phy->ops = &b43_phyops_g;
53 #ifdef CONFIG_B43_PHY_N
54 phy->ops = &b43_phyops_n;
58 #ifdef CONFIG_B43_PHY_LP
59 phy->ops = &b43_phyops_lp;
63 if (B43_WARN_ON(!phy->ops))
66 err = phy->ops->allocate(dev);
73 void b43_phy_free(struct b43_wldev *dev)
75 dev->phy.ops->free(dev);
79 int b43_phy_init(struct b43_wldev *dev)
81 struct b43_phy *phy = &dev->phy;
82 const struct b43_phy_operations *ops = phy->ops;
85 phy->channel = ops->get_default_chan(dev);
87 ops->software_rfkill(dev, false);
90 b43err(dev->wl, "PHY init failed\n");
93 /* Make sure to switch hardware and firmware (SHM) to
94 * the default channel. */
95 err = b43_switch_channel(dev, ops->get_default_chan(dev));
97 b43err(dev->wl, "PHY init: Channel switch to default failed\n");
107 ops->software_rfkill(dev, true);
112 void b43_phy_exit(struct b43_wldev *dev)
114 const struct b43_phy_operations *ops = dev->phy.ops;
116 ops->software_rfkill(dev, true);
121 bool b43_has_hardware_pctl(struct b43_wldev *dev)
123 if (!dev->phy.hardware_power_control)
125 if (!dev->phy.ops->supports_hwpctl)
127 return dev->phy.ops->supports_hwpctl(dev);
130 void b43_radio_lock(struct b43_wldev *dev)
135 B43_WARN_ON(dev->phy.radio_locked);
136 dev->phy.radio_locked = 1;
139 macctl = b43_read32(dev, B43_MMIO_MACCTL);
140 macctl |= B43_MACCTL_RADIOLOCK;
141 b43_write32(dev, B43_MMIO_MACCTL, macctl);
142 /* Commit the write and wait for the firmware
143 * to finish any radio register access. */
144 b43_read32(dev, B43_MMIO_MACCTL);
148 void b43_radio_unlock(struct b43_wldev *dev)
153 B43_WARN_ON(!dev->phy.radio_locked);
154 dev->phy.radio_locked = 0;
157 /* Commit any write */
158 b43_read16(dev, B43_MMIO_PHY_VER);
160 macctl = b43_read32(dev, B43_MMIO_MACCTL);
161 macctl &= ~B43_MACCTL_RADIOLOCK;
162 b43_write32(dev, B43_MMIO_MACCTL, macctl);
165 void b43_phy_lock(struct b43_wldev *dev)
168 B43_WARN_ON(dev->phy.phy_locked);
169 dev->phy.phy_locked = 1;
171 B43_WARN_ON(dev->sdev->id.revision < 3);
173 if (!b43_is_mode(dev->wl, NL80211_IFTYPE_AP))
174 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
177 void b43_phy_unlock(struct b43_wldev *dev)
180 B43_WARN_ON(!dev->phy.phy_locked);
181 dev->phy.phy_locked = 0;
183 B43_WARN_ON(dev->sdev->id.revision < 3);
185 if (!b43_is_mode(dev->wl, NL80211_IFTYPE_AP))
186 b43_power_saving_ctl_bits(dev, 0);
189 static inline void assert_mac_suspended(struct b43_wldev *dev)
193 if ((b43_status(dev) >= B43_STAT_INITIALIZED) &&
194 (dev->mac_suspended <= 0)) {
195 b43dbg(dev->wl, "PHY/RADIO register access with "
201 u16 b43_radio_read(struct b43_wldev *dev, u16 reg)
203 assert_mac_suspended(dev);
204 return dev->phy.ops->radio_read(dev, reg);
207 void b43_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
209 assert_mac_suspended(dev);
210 dev->phy.ops->radio_write(dev, reg, value);
213 void b43_radio_mask(struct b43_wldev *dev, u16 offset, u16 mask)
215 b43_radio_write16(dev, offset,
216 b43_radio_read16(dev, offset) & mask);
219 void b43_radio_set(struct b43_wldev *dev, u16 offset, u16 set)
221 b43_radio_write16(dev, offset,
222 b43_radio_read16(dev, offset) | set);
225 void b43_radio_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set)
227 b43_radio_write16(dev, offset,
228 (b43_radio_read16(dev, offset) & mask) | set);
231 u16 b43_phy_read(struct b43_wldev *dev, u16 reg)
233 assert_mac_suspended(dev);
234 dev->phy.writes_counter = 0;
235 return dev->phy.ops->phy_read(dev, reg);
238 void b43_phy_write(struct b43_wldev *dev, u16 reg, u16 value)
240 assert_mac_suspended(dev);
241 dev->phy.ops->phy_write(dev, reg, value);
242 if (++dev->phy.writes_counter == B43_MAX_WRITES_IN_ROW) {
243 b43_read16(dev, B43_MMIO_PHY_VER);
244 dev->phy.writes_counter = 0;
248 void b43_phy_copy(struct b43_wldev *dev, u16 destreg, u16 srcreg)
250 assert_mac_suspended(dev);
251 dev->phy.ops->phy_write(dev, destreg,
252 dev->phy.ops->phy_read(dev, srcreg));
255 void b43_phy_mask(struct b43_wldev *dev, u16 offset, u16 mask)
257 if (dev->phy.ops->phy_maskset) {
258 assert_mac_suspended(dev);
259 dev->phy.ops->phy_maskset(dev, offset, mask, 0);
261 b43_phy_write(dev, offset,
262 b43_phy_read(dev, offset) & mask);
266 void b43_phy_set(struct b43_wldev *dev, u16 offset, u16 set)
268 if (dev->phy.ops->phy_maskset) {
269 assert_mac_suspended(dev);
270 dev->phy.ops->phy_maskset(dev, offset, 0xFFFF, set);
272 b43_phy_write(dev, offset,
273 b43_phy_read(dev, offset) | set);
277 void b43_phy_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set)
279 if (dev->phy.ops->phy_maskset) {
280 assert_mac_suspended(dev);
281 dev->phy.ops->phy_maskset(dev, offset, mask, set);
283 b43_phy_write(dev, offset,
284 (b43_phy_read(dev, offset) & mask) | set);
288 int b43_switch_channel(struct b43_wldev *dev, unsigned int new_channel)
290 struct b43_phy *phy = &(dev->phy);
291 u16 channelcookie, savedcookie;
294 if (new_channel == B43_DEFAULT_CHANNEL)
295 new_channel = phy->ops->get_default_chan(dev);
297 /* First we set the channel radio code to prevent the
298 * firmware from sending ghost packets.
300 channelcookie = new_channel;
301 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
302 channelcookie |= B43_SHM_SH_CHAN_5GHZ;
303 /* FIXME: set 40Mhz flag if required */
305 channelcookie |= B43_SHM_SH_CHAN_40MHZ;
306 savedcookie = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN);
307 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN, channelcookie);
309 /* Now try to switch the PHY hardware channel. */
310 err = phy->ops->switch_channel(dev, new_channel);
312 goto err_restore_cookie;
314 dev->phy.channel = new_channel;
315 /* Wait for the radio to tune to the channel and stabilize. */
321 b43_shm_write16(dev, B43_SHM_SHARED,
322 B43_SHM_SH_CHAN, savedcookie);
327 void b43_software_rfkill(struct b43_wldev *dev, bool blocked)
329 struct b43_phy *phy = &dev->phy;
331 b43_mac_suspend(dev);
332 phy->ops->software_rfkill(dev, blocked);
333 phy->radio_on = !blocked;
338 * b43_phy_txpower_adjust_work - TX power workqueue.
340 * Workqueue for updating the TX power parameters in hardware.
342 void b43_phy_txpower_adjust_work(struct work_struct *work)
344 struct b43_wl *wl = container_of(work, struct b43_wl,
345 txpower_adjust_work);
346 struct b43_wldev *dev;
348 mutex_lock(&wl->mutex);
349 dev = wl->current_dev;
351 if (likely(dev && (b43_status(dev) >= B43_STAT_STARTED)))
352 dev->phy.ops->adjust_txpower(dev);
354 mutex_unlock(&wl->mutex);
357 void b43_phy_txpower_check(struct b43_wldev *dev, unsigned int flags)
359 struct b43_phy *phy = &dev->phy;
360 unsigned long now = jiffies;
361 enum b43_txpwr_result result;
363 if (!(flags & B43_TXPWR_IGNORE_TIME)) {
364 /* Check if it's time for a TXpower check. */
365 if (time_before(now, phy->next_txpwr_check_time))
366 return; /* Not yet */
368 /* The next check will be needed in two seconds, or later. */
369 phy->next_txpwr_check_time = round_jiffies(now + (HZ * 2));
371 if ((dev->sdev->bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM) &&
372 (dev->sdev->bus->boardinfo.type == SSB_BOARD_BU4306))
373 return; /* No software txpower adjustment needed */
375 result = phy->ops->recalc_txpower(dev, !!(flags & B43_TXPWR_IGNORE_TSSI));
376 if (result == B43_TXPWR_RES_DONE)
377 return; /* We are done. */
378 B43_WARN_ON(result != B43_TXPWR_RES_NEED_ADJUST);
379 B43_WARN_ON(phy->ops->adjust_txpower == NULL);
381 /* We must adjust the transmission power in hardware.
382 * Schedule b43_phy_txpower_adjust_work(). */
383 ieee80211_queue_work(dev->wl->hw, &dev->wl->txpower_adjust_work);
386 int b43_phy_shm_tssi_read(struct b43_wldev *dev, u16 shm_offset)
388 const bool is_ofdm = (shm_offset != B43_SHM_SH_TSSI_CCK);
389 unsigned int a, b, c, d;
390 unsigned int average;
393 tmp = b43_shm_read32(dev, B43_SHM_SHARED, shm_offset);
395 b = (tmp >> 8) & 0xFF;
396 c = (tmp >> 16) & 0xFF;
397 d = (tmp >> 24) & 0xFF;
398 if (a == 0 || a == B43_TSSI_MAX ||
399 b == 0 || b == B43_TSSI_MAX ||
400 c == 0 || c == B43_TSSI_MAX ||
401 d == 0 || d == B43_TSSI_MAX)
403 /* The values are OK. Clear them. */
404 tmp = B43_TSSI_MAX | (B43_TSSI_MAX << 8) |
405 (B43_TSSI_MAX << 16) | (B43_TSSI_MAX << 24);
406 b43_shm_write32(dev, B43_SHM_SHARED, shm_offset, tmp);
415 /* Get the average of the values with 0.5 added to each value. */
416 average = (a + b + c + d + 2) / 4;
418 /* Adjust for CCK-boost */
419 if (b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO)
421 average = (average >= 13) ? (average - 13) : 0;
427 void b43_phyop_switch_analog_generic(struct b43_wldev *dev, bool on)
429 b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4);
433 bool b43_channel_type_is_40mhz(enum nl80211_channel_type channel_type)
435 return (channel_type == NL80211_CHAN_HT40MINUS ||
436 channel_type == NL80211_CHAN_HT40PLUS);
439 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Cordic */
440 struct b43_c32 b43_cordic(int theta)
442 static const u32 arctg[] = {
443 2949120, 1740967, 919879, 466945, 234379, 117304,
444 58666, 29335, 14668, 7334, 3667, 1833,
445 917, 458, 229, 115, 57, 29,
451 struct b43_c32 ret = { .i = 39797, .q = 0, };
453 while (theta > (180 << 16))
454 theta -= (360 << 16);
455 while (theta < -(180 << 16))
456 theta += (360 << 16);
458 if (theta > (90 << 16)) {
459 theta -= (180 << 16);
461 } else if (theta < -(90 << 16)) {
462 theta += (180 << 16);
466 for (i = 0; i <= 17; i++) {
468 tmp = ret.i - (ret.q >> i);
473 tmp = ret.i + (ret.q >> i);