3 Broadcom B43 wireless driver
6 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
7 Copyright (c) 2005-2007 Stefano Brivio <stefano.brivio@polimi.it>
8 Copyright (c) 2005-2008 Michael Buesch <mb@bu3sch.de>
9 Copyright (c) 2005, 2006 Danny van Dyk <kugelfang@gentoo.org>
10 Copyright (c) 2005, 2006 Andreas Jaggi <andreas.jaggi@waterwave.ch>
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; see the file COPYING. If not, write to
24 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
25 Boston, MA 02110-1301, USA.
29 #include "phy_common.h"
39 int b43_phy_allocate(struct b43_wldev *dev)
41 struct b43_phy *phy = &(dev->phy);
48 phy->ops = &b43_phyops_a;
51 phy->ops = &b43_phyops_g;
54 #ifdef CONFIG_B43_PHY_N
55 phy->ops = &b43_phyops_n;
59 #ifdef CONFIG_B43_PHY_LP
60 phy->ops = &b43_phyops_lp;
64 #ifdef CONFIG_B43_PHY_HT
65 phy->ops = &b43_phyops_ht;
69 if (B43_WARN_ON(!phy->ops))
72 err = phy->ops->allocate(dev);
79 void b43_phy_free(struct b43_wldev *dev)
81 dev->phy.ops->free(dev);
85 int b43_phy_init(struct b43_wldev *dev)
87 struct b43_phy *phy = &dev->phy;
88 const struct b43_phy_operations *ops = phy->ops;
91 phy->channel = ops->get_default_chan(dev);
93 ops->software_rfkill(dev, false);
96 b43err(dev->wl, "PHY init failed\n");
99 /* Make sure to switch hardware and firmware (SHM) to
100 * the default channel. */
101 err = b43_switch_channel(dev, ops->get_default_chan(dev));
103 b43err(dev->wl, "PHY init: Channel switch to default failed\n");
113 ops->software_rfkill(dev, true);
118 void b43_phy_exit(struct b43_wldev *dev)
120 const struct b43_phy_operations *ops = dev->phy.ops;
122 ops->software_rfkill(dev, true);
127 bool b43_has_hardware_pctl(struct b43_wldev *dev)
129 if (!dev->phy.hardware_power_control)
131 if (!dev->phy.ops->supports_hwpctl)
133 return dev->phy.ops->supports_hwpctl(dev);
136 void b43_radio_lock(struct b43_wldev *dev)
141 B43_WARN_ON(dev->phy.radio_locked);
142 dev->phy.radio_locked = 1;
145 macctl = b43_read32(dev, B43_MMIO_MACCTL);
146 macctl |= B43_MACCTL_RADIOLOCK;
147 b43_write32(dev, B43_MMIO_MACCTL, macctl);
148 /* Commit the write and wait for the firmware
149 * to finish any radio register access. */
150 b43_read32(dev, B43_MMIO_MACCTL);
154 void b43_radio_unlock(struct b43_wldev *dev)
159 B43_WARN_ON(!dev->phy.radio_locked);
160 dev->phy.radio_locked = 0;
163 /* Commit any write */
164 b43_read16(dev, B43_MMIO_PHY_VER);
166 macctl = b43_read32(dev, B43_MMIO_MACCTL);
167 macctl &= ~B43_MACCTL_RADIOLOCK;
168 b43_write32(dev, B43_MMIO_MACCTL, macctl);
171 void b43_phy_lock(struct b43_wldev *dev)
174 B43_WARN_ON(dev->phy.phy_locked);
175 dev->phy.phy_locked = 1;
177 B43_WARN_ON(dev->dev->core_rev < 3);
179 if (!b43_is_mode(dev->wl, NL80211_IFTYPE_AP))
180 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
183 void b43_phy_unlock(struct b43_wldev *dev)
186 B43_WARN_ON(!dev->phy.phy_locked);
187 dev->phy.phy_locked = 0;
189 B43_WARN_ON(dev->dev->core_rev < 3);
191 if (!b43_is_mode(dev->wl, NL80211_IFTYPE_AP))
192 b43_power_saving_ctl_bits(dev, 0);
195 static inline void assert_mac_suspended(struct b43_wldev *dev)
199 if ((b43_status(dev) >= B43_STAT_INITIALIZED) &&
200 (dev->mac_suspended <= 0)) {
201 b43dbg(dev->wl, "PHY/RADIO register access with "
207 u16 b43_radio_read(struct b43_wldev *dev, u16 reg)
209 assert_mac_suspended(dev);
210 return dev->phy.ops->radio_read(dev, reg);
213 void b43_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
215 assert_mac_suspended(dev);
216 dev->phy.ops->radio_write(dev, reg, value);
219 void b43_radio_mask(struct b43_wldev *dev, u16 offset, u16 mask)
221 b43_radio_write16(dev, offset,
222 b43_radio_read16(dev, offset) & mask);
225 void b43_radio_set(struct b43_wldev *dev, u16 offset, u16 set)
227 b43_radio_write16(dev, offset,
228 b43_radio_read16(dev, offset) | set);
231 void b43_radio_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set)
233 b43_radio_write16(dev, offset,
234 (b43_radio_read16(dev, offset) & mask) | set);
237 u16 b43_phy_read(struct b43_wldev *dev, u16 reg)
239 assert_mac_suspended(dev);
240 dev->phy.writes_counter = 0;
241 return dev->phy.ops->phy_read(dev, reg);
244 void b43_phy_write(struct b43_wldev *dev, u16 reg, u16 value)
246 assert_mac_suspended(dev);
247 dev->phy.ops->phy_write(dev, reg, value);
248 if (++dev->phy.writes_counter == B43_MAX_WRITES_IN_ROW) {
249 b43_read16(dev, B43_MMIO_PHY_VER);
250 dev->phy.writes_counter = 0;
254 void b43_phy_copy(struct b43_wldev *dev, u16 destreg, u16 srcreg)
256 assert_mac_suspended(dev);
257 dev->phy.ops->phy_write(dev, destreg,
258 dev->phy.ops->phy_read(dev, srcreg));
261 void b43_phy_mask(struct b43_wldev *dev, u16 offset, u16 mask)
263 if (dev->phy.ops->phy_maskset) {
264 assert_mac_suspended(dev);
265 dev->phy.ops->phy_maskset(dev, offset, mask, 0);
267 b43_phy_write(dev, offset,
268 b43_phy_read(dev, offset) & mask);
272 void b43_phy_set(struct b43_wldev *dev, u16 offset, u16 set)
274 if (dev->phy.ops->phy_maskset) {
275 assert_mac_suspended(dev);
276 dev->phy.ops->phy_maskset(dev, offset, 0xFFFF, set);
278 b43_phy_write(dev, offset,
279 b43_phy_read(dev, offset) | set);
283 void b43_phy_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set)
285 if (dev->phy.ops->phy_maskset) {
286 assert_mac_suspended(dev);
287 dev->phy.ops->phy_maskset(dev, offset, mask, set);
289 b43_phy_write(dev, offset,
290 (b43_phy_read(dev, offset) & mask) | set);
294 int b43_switch_channel(struct b43_wldev *dev, unsigned int new_channel)
296 struct b43_phy *phy = &(dev->phy);
297 u16 channelcookie, savedcookie;
300 if (new_channel == B43_DEFAULT_CHANNEL)
301 new_channel = phy->ops->get_default_chan(dev);
303 /* First we set the channel radio code to prevent the
304 * firmware from sending ghost packets.
306 channelcookie = new_channel;
307 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
308 channelcookie |= B43_SHM_SH_CHAN_5GHZ;
309 /* FIXME: set 40Mhz flag if required */
311 channelcookie |= B43_SHM_SH_CHAN_40MHZ;
312 savedcookie = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN);
313 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN, channelcookie);
315 /* Now try to switch the PHY hardware channel. */
316 err = phy->ops->switch_channel(dev, new_channel);
318 goto err_restore_cookie;
320 dev->phy.channel = new_channel;
321 /* Wait for the radio to tune to the channel and stabilize. */
327 b43_shm_write16(dev, B43_SHM_SHARED,
328 B43_SHM_SH_CHAN, savedcookie);
333 void b43_software_rfkill(struct b43_wldev *dev, bool blocked)
335 struct b43_phy *phy = &dev->phy;
337 b43_mac_suspend(dev);
338 phy->ops->software_rfkill(dev, blocked);
339 phy->radio_on = !blocked;
344 * b43_phy_txpower_adjust_work - TX power workqueue.
346 * Workqueue for updating the TX power parameters in hardware.
348 void b43_phy_txpower_adjust_work(struct work_struct *work)
350 struct b43_wl *wl = container_of(work, struct b43_wl,
351 txpower_adjust_work);
352 struct b43_wldev *dev;
354 mutex_lock(&wl->mutex);
355 dev = wl->current_dev;
357 if (likely(dev && (b43_status(dev) >= B43_STAT_STARTED)))
358 dev->phy.ops->adjust_txpower(dev);
360 mutex_unlock(&wl->mutex);
363 void b43_phy_txpower_check(struct b43_wldev *dev, unsigned int flags)
365 struct b43_phy *phy = &dev->phy;
366 unsigned long now = jiffies;
367 enum b43_txpwr_result result;
369 if (!(flags & B43_TXPWR_IGNORE_TIME)) {
370 /* Check if it's time for a TXpower check. */
371 if (time_before(now, phy->next_txpwr_check_time))
372 return; /* Not yet */
374 /* The next check will be needed in two seconds, or later. */
375 phy->next_txpwr_check_time = round_jiffies(now + (HZ * 2));
377 if ((dev->dev->board_vendor == SSB_BOARDVENDOR_BCM) &&
378 (dev->dev->board_type == SSB_BOARD_BU4306))
379 return; /* No software txpower adjustment needed */
381 result = phy->ops->recalc_txpower(dev, !!(flags & B43_TXPWR_IGNORE_TSSI));
382 if (result == B43_TXPWR_RES_DONE)
383 return; /* We are done. */
384 B43_WARN_ON(result != B43_TXPWR_RES_NEED_ADJUST);
385 B43_WARN_ON(phy->ops->adjust_txpower == NULL);
387 /* We must adjust the transmission power in hardware.
388 * Schedule b43_phy_txpower_adjust_work(). */
389 ieee80211_queue_work(dev->wl->hw, &dev->wl->txpower_adjust_work);
392 int b43_phy_shm_tssi_read(struct b43_wldev *dev, u16 shm_offset)
394 const bool is_ofdm = (shm_offset != B43_SHM_SH_TSSI_CCK);
395 unsigned int a, b, c, d;
396 unsigned int average;
399 tmp = b43_shm_read32(dev, B43_SHM_SHARED, shm_offset);
401 b = (tmp >> 8) & 0xFF;
402 c = (tmp >> 16) & 0xFF;
403 d = (tmp >> 24) & 0xFF;
404 if (a == 0 || a == B43_TSSI_MAX ||
405 b == 0 || b == B43_TSSI_MAX ||
406 c == 0 || c == B43_TSSI_MAX ||
407 d == 0 || d == B43_TSSI_MAX)
409 /* The values are OK. Clear them. */
410 tmp = B43_TSSI_MAX | (B43_TSSI_MAX << 8) |
411 (B43_TSSI_MAX << 16) | (B43_TSSI_MAX << 24);
412 b43_shm_write32(dev, B43_SHM_SHARED, shm_offset, tmp);
421 /* Get the average of the values with 0.5 added to each value. */
422 average = (a + b + c + d + 2) / 4;
424 /* Adjust for CCK-boost */
425 if (b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO)
427 average = (average >= 13) ? (average - 13) : 0;
433 void b43_phyop_switch_analog_generic(struct b43_wldev *dev, bool on)
435 b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4);
439 bool b43_channel_type_is_40mhz(enum nl80211_channel_type channel_type)
441 return (channel_type == NL80211_CHAN_HT40MINUS ||
442 channel_type == NL80211_CHAN_HT40PLUS);
445 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Cordic */
446 struct b43_c32 b43_cordic(int theta)
448 static const u32 arctg[] = {
449 2949120, 1740967, 919879, 466945, 234379, 117304,
450 58666, 29335, 14668, 7334, 3667, 1833,
451 917, 458, 229, 115, 57, 29,
457 struct b43_c32 ret = { .i = 39797, .q = 0, };
459 while (theta > (180 << 16))
460 theta -= (360 << 16);
461 while (theta < -(180 << 16))
462 theta += (360 << 16);
464 if (theta > (90 << 16)) {
465 theta -= (180 << 16);
467 } else if (theta < -(90 << 16)) {
468 theta += (180 << 16);
472 for (i = 0; i <= 17; i++) {
474 tmp = ret.i - (ret.q >> i);
479 tmp = ret.i + (ret.q >> i);