2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/dma-mapping.h>
19 #include "ar9003_mac.h"
21 #define BITS_PER_BYTE 8
22 #define OFDM_PLCP_BITS 22
23 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
29 #define HT_LTF(_ns) (4 * (_ns))
30 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
31 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
32 #define TIME_SYMBOLS(t) ((t) >> 2)
33 #define TIME_SYMBOLS_HALFGI(t) (((t) * 5 - 4) / 18)
34 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
35 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
38 static u16 bits_per_symbol[][2] = {
40 { 26, 54 }, /* 0: BPSK */
41 { 52, 108 }, /* 1: QPSK 1/2 */
42 { 78, 162 }, /* 2: QPSK 3/4 */
43 { 104, 216 }, /* 3: 16-QAM 1/2 */
44 { 156, 324 }, /* 4: 16-QAM 3/4 */
45 { 208, 432 }, /* 5: 64-QAM 2/3 */
46 { 234, 486 }, /* 6: 64-QAM 3/4 */
47 { 260, 540 }, /* 7: 64-QAM 5/6 */
50 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
51 struct ath_atx_tid *tid, struct sk_buff *skb);
52 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
53 int tx_flags, struct ath_txq *txq);
54 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
55 struct ath_txq *txq, struct list_head *bf_q,
56 struct ath_tx_status *ts, int txok);
57 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
58 struct list_head *head, bool internal);
59 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
60 struct ath_tx_status *ts, int nframes, int nbad,
62 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
64 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
66 struct ath_atx_tid *tid,
76 /*********************/
77 /* Aggregation logic */
78 /*********************/
80 void ath_txq_lock(struct ath_softc *sc, struct ath_txq *txq)
81 __acquires(&txq->axq_lock)
83 spin_lock_bh(&txq->axq_lock);
86 void ath_txq_unlock(struct ath_softc *sc, struct ath_txq *txq)
87 __releases(&txq->axq_lock)
89 spin_unlock_bh(&txq->axq_lock);
92 void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq)
93 __releases(&txq->axq_lock)
95 struct sk_buff_head q;
98 __skb_queue_head_init(&q);
99 skb_queue_splice_init(&txq->complete_q, &q);
100 spin_unlock_bh(&txq->axq_lock);
102 while ((skb = __skb_dequeue(&q)))
103 ieee80211_tx_status(sc->hw, skb);
106 static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
108 struct ath_atx_ac *ac = tid->ac;
117 list_add_tail(&tid->list, &ac->tid_q);
123 list_add_tail(&ac->list, &txq->axq_acq);
126 static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
128 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
129 BUILD_BUG_ON(sizeof(struct ath_frame_info) >
130 sizeof(tx_info->rate_driver_data));
131 return (struct ath_frame_info *) &tx_info->rate_driver_data[0];
134 static void ath_send_bar(struct ath_atx_tid *tid, u16 seqno)
139 ieee80211_send_bar(tid->an->vif, tid->an->sta->addr, tid->tidno,
140 seqno << IEEE80211_SEQ_SEQ_SHIFT);
143 static void ath_set_rates(struct ieee80211_vif *vif, struct ieee80211_sta *sta,
146 ieee80211_get_tx_rates(vif, sta, bf->bf_mpdu, bf->rates,
147 ARRAY_SIZE(bf->rates));
150 static void ath_txq_skb_done(struct ath_softc *sc, struct ath_txq *txq,
155 q = skb_get_queue_mapping(skb);
156 if (txq == sc->tx.uapsdq)
157 txq = sc->tx.txq_map[q];
159 if (txq != sc->tx.txq_map[q])
162 if (WARN_ON(--txq->pending_frames < 0))
163 txq->pending_frames = 0;
166 txq->pending_frames < sc->tx.txq_max_pending[q]) {
167 ieee80211_wake_queue(sc->hw, q);
168 txq->stopped = false;
172 static struct ath_atx_tid *
173 ath_get_skb_tid(struct ath_softc *sc, struct ath_node *an, struct sk_buff *skb)
175 u8 tidno = skb->priority & IEEE80211_QOS_CTL_TID_MASK;
176 return ATH_AN_2_TID(an, tidno);
179 static bool ath_tid_has_buffered(struct ath_atx_tid *tid)
181 return !skb_queue_empty(&tid->buf_q) || !skb_queue_empty(&tid->retry_q);
184 static struct sk_buff *ath_tid_dequeue(struct ath_atx_tid *tid)
188 skb = __skb_dequeue(&tid->retry_q);
190 skb = __skb_dequeue(&tid->buf_q);
196 * ath_tx_tid_change_state:
197 * - clears a-mpdu flag of previous session
198 * - force sequence number allocation to fix next BlockAck Window
201 ath_tx_tid_change_state(struct ath_softc *sc, struct ath_atx_tid *tid)
203 struct ath_txq *txq = tid->ac->txq;
204 struct ieee80211_tx_info *tx_info;
205 struct sk_buff *skb, *tskb;
207 struct ath_frame_info *fi;
209 skb_queue_walk_safe(&tid->buf_q, skb, tskb) {
210 fi = get_frame_info(skb);
213 tx_info = IEEE80211_SKB_CB(skb);
214 tx_info->flags &= ~IEEE80211_TX_CTL_AMPDU;
219 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
221 __skb_unlink(skb, &tid->buf_q);
222 ath_txq_skb_done(sc, txq, skb);
223 ieee80211_free_txskb(sc->hw, skb);
230 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
232 struct ath_txq *txq = tid->ac->txq;
235 struct list_head bf_head;
236 struct ath_tx_status ts;
237 struct ath_frame_info *fi;
238 bool sendbar = false;
240 INIT_LIST_HEAD(&bf_head);
242 memset(&ts, 0, sizeof(ts));
244 while ((skb = __skb_dequeue(&tid->retry_q))) {
245 fi = get_frame_info(skb);
248 ath_txq_skb_done(sc, txq, skb);
249 ieee80211_free_txskb(sc->hw, skb);
253 if (fi->baw_tracked) {
254 ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
258 list_add_tail(&bf->list, &bf_head);
259 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
263 ath_txq_unlock(sc, txq);
264 ath_send_bar(tid, tid->seq_start);
265 ath_txq_lock(sc, txq);
269 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
274 index = ATH_BA_INDEX(tid->seq_start, seqno);
275 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
277 __clear_bit(cindex, tid->tx_buf);
279 while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) {
280 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
281 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
282 if (tid->bar_index >= 0)
287 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
290 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
291 u16 seqno = bf->bf_state.seqno;
294 index = ATH_BA_INDEX(tid->seq_start, seqno);
295 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
296 __set_bit(cindex, tid->tx_buf);
299 if (index >= ((tid->baw_tail - tid->baw_head) &
300 (ATH_TID_MAX_BUFS - 1))) {
301 tid->baw_tail = cindex;
302 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
306 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
307 struct ath_atx_tid *tid)
312 struct list_head bf_head;
313 struct ath_tx_status ts;
314 struct ath_frame_info *fi;
316 memset(&ts, 0, sizeof(ts));
317 INIT_LIST_HEAD(&bf_head);
319 while ((skb = ath_tid_dequeue(tid))) {
320 fi = get_frame_info(skb);
324 ath_tx_complete(sc, skb, ATH_TX_ERROR, txq);
328 list_add_tail(&bf->list, &bf_head);
329 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
333 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
334 struct sk_buff *skb, int count)
336 struct ath_frame_info *fi = get_frame_info(skb);
337 struct ath_buf *bf = fi->bf;
338 struct ieee80211_hdr *hdr;
339 int prev = fi->retries;
341 TX_STAT_INC(txq->axq_qnum, a_retries);
342 fi->retries += count;
347 hdr = (struct ieee80211_hdr *)skb->data;
348 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
349 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
350 sizeof(*hdr), DMA_TO_DEVICE);
353 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
355 struct ath_buf *bf = NULL;
357 spin_lock_bh(&sc->tx.txbuflock);
359 if (unlikely(list_empty(&sc->tx.txbuf))) {
360 spin_unlock_bh(&sc->tx.txbuflock);
364 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
367 spin_unlock_bh(&sc->tx.txbuflock);
372 static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
374 spin_lock_bh(&sc->tx.txbuflock);
375 list_add_tail(&bf->list, &sc->tx.txbuf);
376 spin_unlock_bh(&sc->tx.txbuflock);
379 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
383 tbf = ath_tx_get_buffer(sc);
387 ATH_TXBUF_RESET(tbf);
389 tbf->bf_mpdu = bf->bf_mpdu;
390 tbf->bf_buf_addr = bf->bf_buf_addr;
391 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
392 tbf->bf_state = bf->bf_state;
393 tbf->bf_state.stale = false;
398 static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf,
399 struct ath_tx_status *ts, int txok,
400 int *nframes, int *nbad)
402 struct ath_frame_info *fi;
404 u32 ba[WME_BA_BMP_SIZE >> 5];
411 isaggr = bf_isaggr(bf);
413 seq_st = ts->ts_seqnum;
414 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
418 fi = get_frame_info(bf->bf_mpdu);
419 ba_index = ATH_BA_INDEX(seq_st, bf->bf_state.seqno);
422 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
430 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
431 struct ath_buf *bf, struct list_head *bf_q,
432 struct ath_tx_status *ts, int txok)
434 struct ath_node *an = NULL;
436 struct ieee80211_sta *sta;
437 struct ieee80211_hw *hw = sc->hw;
438 struct ieee80211_hdr *hdr;
439 struct ieee80211_tx_info *tx_info;
440 struct ath_atx_tid *tid = NULL;
441 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
442 struct list_head bf_head;
443 struct sk_buff_head bf_pending;
444 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0, seq_first;
445 u32 ba[WME_BA_BMP_SIZE >> 5];
446 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
447 bool rc_update = true, isba;
448 struct ieee80211_tx_rate rates[4];
449 struct ath_frame_info *fi;
451 bool flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
456 hdr = (struct ieee80211_hdr *)skb->data;
458 tx_info = IEEE80211_SKB_CB(skb);
460 memcpy(rates, bf->rates, sizeof(rates));
462 retries = ts->ts_longretry + 1;
463 for (i = 0; i < ts->ts_rateindex; i++)
464 retries += rates[i].count;
468 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2);
472 INIT_LIST_HEAD(&bf_head);
474 bf_next = bf->bf_next;
476 if (!bf->bf_state.stale || bf_next != NULL)
477 list_move_tail(&bf->list, &bf_head);
479 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts, 0);
486 an = (struct ath_node *)sta->drv_priv;
487 tid = ath_get_skb_tid(sc, an, skb);
488 seq_first = tid->seq_start;
489 isba = ts->ts_flags & ATH9K_TX_BA;
492 * The hardware occasionally sends a tx status for the wrong TID.
493 * In this case, the BA status cannot be considered valid and all
494 * subframes need to be retransmitted
496 * Only BlockAcks have a TID and therefore normal Acks cannot be
499 if (isba && tid->tidno != ts->tid)
502 isaggr = bf_isaggr(bf);
503 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
505 if (isaggr && txok) {
506 if (ts->ts_flags & ATH9K_TX_BA) {
507 seq_st = ts->ts_seqnum;
508 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
511 * AR5416 can become deaf/mute when BA
512 * issue happens. Chip needs to be reset.
513 * But AP code may have sychronization issues
514 * when perform internal reset in this routine.
515 * Only enable reset in STA mode for now.
517 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
522 __skb_queue_head_init(&bf_pending);
524 ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad);
526 u16 seqno = bf->bf_state.seqno;
528 txfail = txpending = sendbar = 0;
529 bf_next = bf->bf_next;
532 tx_info = IEEE80211_SKB_CB(skb);
533 fi = get_frame_info(skb);
535 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno) ||
538 * Outside of the current BlockAck window,
539 * maybe part of a previous session
542 } else if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) {
543 /* transmit completion, subframe is
544 * acked by block ack */
546 } else if (!isaggr && txok) {
547 /* transmit completion */
551 } else if (fi->retries < ATH_MAX_SW_RETRIES) {
552 if (txok || !an->sleeping)
553 ath_tx_set_retry(sc, txq, bf->bf_mpdu,
560 bar_index = max_t(int, bar_index,
561 ATH_BA_INDEX(seq_first, seqno));
565 * Make sure the last desc is reclaimed if it
566 * not a holding desc.
568 INIT_LIST_HEAD(&bf_head);
569 if (bf_next != NULL || !bf_last->bf_state.stale)
570 list_move_tail(&bf->list, &bf_head);
574 * complete the acked-ones/xretried ones; update
577 ath_tx_update_baw(sc, tid, seqno);
579 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
580 memcpy(tx_info->control.rates, rates, sizeof(rates));
581 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok);
585 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
588 if (tx_info->flags & IEEE80211_TX_STATUS_EOSP) {
589 tx_info->flags &= ~IEEE80211_TX_STATUS_EOSP;
590 ieee80211_sta_eosp(sta);
592 /* retry the un-acked ones */
593 if (bf->bf_next == NULL && bf_last->bf_state.stale) {
596 tbf = ath_clone_txbuf(sc, bf_last);
598 * Update tx baw and complete the
599 * frame with failed status if we
603 ath_tx_update_baw(sc, tid, seqno);
605 ath_tx_complete_buf(sc, bf, txq,
607 bar_index = max_t(int, bar_index,
608 ATH_BA_INDEX(seq_first, seqno));
616 * Put this buffer to the temporary pending
617 * queue to retain ordering
619 __skb_queue_tail(&bf_pending, skb);
625 /* prepend un-acked frames to the beginning of the pending frame queue */
626 if (!skb_queue_empty(&bf_pending)) {
628 ieee80211_sta_set_buffered(sta, tid->tidno, true);
630 skb_queue_splice_tail(&bf_pending, &tid->retry_q);
632 ath_tx_queue_tid(txq, tid);
634 if (ts->ts_status & (ATH9K_TXERR_FILT | ATH9K_TXERR_XRETRY))
635 tid->ac->clear_ps_filter = true;
639 if (bar_index >= 0) {
640 u16 bar_seq = ATH_BA_INDEX2SEQ(seq_first, bar_index);
642 if (BAW_WITHIN(tid->seq_start, tid->baw_size, bar_seq))
643 tid->bar_index = ATH_BA_INDEX(tid->seq_start, bar_seq);
645 ath_txq_unlock(sc, txq);
646 ath_send_bar(tid, ATH_BA_INDEX2SEQ(seq_first, bar_index + 1));
647 ath_txq_lock(sc, txq);
653 ath9k_queue_reset(sc, RESET_TYPE_TX_ERROR);
656 static bool bf_is_ampdu_not_probing(struct ath_buf *bf)
658 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu);
659 return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
662 static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq,
663 struct ath_tx_status *ts, struct ath_buf *bf,
664 struct list_head *bf_head)
666 struct ieee80211_tx_info *info;
669 txok = !(ts->ts_status & ATH9K_TXERR_MASK);
670 flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
671 txq->axq_tx_inprogress = false;
674 if (bf_is_ampdu_not_probing(bf))
675 txq->axq_ampdu_depth--;
677 if (!bf_isampdu(bf)) {
679 info = IEEE80211_SKB_CB(bf->bf_mpdu);
680 memcpy(info->control.rates, bf->rates,
681 sizeof(info->control.rates));
682 ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok);
684 ath_tx_complete_buf(sc, bf, txq, bf_head, ts, txok);
686 ath_tx_complete_aggr(sc, txq, bf, bf_head, ts, txok);
689 ath_txq_schedule(sc, txq);
692 static bool ath_lookup_legacy(struct ath_buf *bf)
695 struct ieee80211_tx_info *tx_info;
696 struct ieee80211_tx_rate *rates;
700 tx_info = IEEE80211_SKB_CB(skb);
701 rates = tx_info->control.rates;
703 for (i = 0; i < 4; i++) {
704 if (!rates[i].count || rates[i].idx < 0)
707 if (!(rates[i].flags & IEEE80211_TX_RC_MCS))
714 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
715 struct ath_atx_tid *tid)
718 struct ieee80211_tx_info *tx_info;
719 struct ieee80211_tx_rate *rates;
720 u32 max_4ms_framelen, frmlen;
721 u16 aggr_limit, bt_aggr_limit, legacy = 0;
722 int q = tid->ac->txq->mac80211_qnum;
726 tx_info = IEEE80211_SKB_CB(skb);
730 * Find the lowest frame length among the rate series that will have a
731 * 4ms (or TXOP limited) transmit duration.
733 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
735 for (i = 0; i < 4; i++) {
741 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
746 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
751 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
754 frmlen = sc->tx.max_aggr_framelen[q][modeidx][rates[i].idx];
755 max_4ms_framelen = min(max_4ms_framelen, frmlen);
759 * limit aggregate size by the minimum rate if rate selected is
760 * not a probe rate, if rate selected is a probe rate then
761 * avoid aggregation of this packet.
763 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
766 aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_MAX);
769 * Override the default aggregation limit for BTCOEX.
771 bt_aggr_limit = ath9k_btcoex_aggr_limit(sc, max_4ms_framelen);
773 aggr_limit = bt_aggr_limit;
775 if (tid->an->maxampdu)
776 aggr_limit = min(aggr_limit, tid->an->maxampdu);
782 * Returns the number of delimiters to be added to
783 * meet the minimum required mpdudensity.
785 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
786 struct ath_buf *bf, u16 frmlen,
789 #define FIRST_DESC_NDELIMS 60
790 u32 nsymbits, nsymbols;
793 int width, streams, half_gi, ndelim, mindelim;
794 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
796 /* Select standard number of delimiters based on frame length alone */
797 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
800 * If encryption enabled, hardware requires some more padding between
802 * TODO - this could be improved to be dependent on the rate.
803 * The hardware can keep up at lower rates, but not higher rates
805 if ((fi->keyix != ATH9K_TXKEYIX_INVALID) &&
806 !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))
807 ndelim += ATH_AGGR_ENCRYPTDELIM;
810 * Add delimiter when using RTS/CTS with aggregation
811 * and non enterprise AR9003 card
813 if (first_subfrm && !AR_SREV_9580_10_OR_LATER(sc->sc_ah) &&
814 (sc->sc_ah->ent_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE))
815 ndelim = max(ndelim, FIRST_DESC_NDELIMS);
818 * Convert desired mpdu density from microeconds to bytes based
819 * on highest rate in rate series (i.e. first rate) to determine
820 * required minimum length for subframe. Take into account
821 * whether high rate is 20 or 40Mhz and half or full GI.
823 * If there is no mpdu density restriction, no further calculation
827 if (tid->an->mpdudensity == 0)
830 rix = bf->rates[0].idx;
831 flags = bf->rates[0].flags;
832 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
833 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
836 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
838 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
843 streams = HT_RC_2_STREAMS(rix);
844 nsymbits = bits_per_symbol[rix % 8][width] * streams;
845 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
847 if (frmlen < minlen) {
848 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
849 ndelim = max(mindelim, ndelim);
855 static struct ath_buf *
856 ath_tx_get_tid_subframe(struct ath_softc *sc, struct ath_txq *txq,
857 struct ath_atx_tid *tid, struct sk_buff_head **q)
859 struct ieee80211_tx_info *tx_info;
860 struct ath_frame_info *fi;
867 if (skb_queue_empty(*q))
874 fi = get_frame_info(skb);
877 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
879 bf->bf_state.stale = false;
882 __skb_unlink(skb, *q);
883 ath_txq_skb_done(sc, txq, skb);
884 ieee80211_free_txskb(sc->hw, skb);
891 tx_info = IEEE80211_SKB_CB(skb);
892 tx_info->flags &= ~IEEE80211_TX_CTL_CLEAR_PS_FILT;
893 if (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU)) {
894 bf->bf_state.bf_type = 0;
898 bf->bf_state.bf_type = BUF_AMPDU | BUF_AGGR;
899 seqno = bf->bf_state.seqno;
901 /* do not step over block-ack window */
902 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno))
905 if (tid->bar_index > ATH_BA_INDEX(tid->seq_start, seqno)) {
906 struct ath_tx_status ts = {};
907 struct list_head bf_head;
909 INIT_LIST_HEAD(&bf_head);
910 list_add(&bf->list, &bf_head);
911 __skb_unlink(skb, *q);
912 ath_tx_update_baw(sc, tid, seqno);
913 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
924 ath_tx_form_aggr(struct ath_softc *sc, struct ath_txq *txq,
925 struct ath_atx_tid *tid, struct list_head *bf_q,
926 struct ath_buf *bf_first, struct sk_buff_head *tid_q,
929 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
930 struct ath_buf *bf = bf_first, *bf_prev = NULL;
931 int nframes = 0, ndelim;
932 u16 aggr_limit = 0, al = 0, bpad = 0,
933 al_delta, h_baw = tid->baw_size / 2;
934 struct ieee80211_tx_info *tx_info;
935 struct ath_frame_info *fi;
940 aggr_limit = ath_lookup_rate(sc, bf, tid);
944 fi = get_frame_info(skb);
946 /* do not exceed aggregation limit */
947 al_delta = ATH_AGGR_DELIM_SZ + fi->framelen;
949 if (aggr_limit < al + bpad + al_delta ||
950 ath_lookup_legacy(bf) || nframes >= h_baw)
953 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
954 if ((tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) ||
955 !(tx_info->flags & IEEE80211_TX_CTL_AMPDU))
959 /* add padding for previous frame to aggregation length */
960 al += bpad + al_delta;
963 * Get the delimiters needed to meet the MPDU
964 * density for this node.
966 ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen,
968 bpad = PADBYTES(al_delta) + (ndelim << 2);
973 /* link buffers of this frame to the aggregate */
974 if (!fi->baw_tracked)
975 ath_tx_addto_baw(sc, tid, bf);
976 bf->bf_state.ndelim = ndelim;
978 __skb_unlink(skb, tid_q);
979 list_add_tail(&bf->list, bf_q);
981 bf_prev->bf_next = bf;
985 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q);
990 } while (ath_tid_has_buffered(tid));
993 bf->bf_lastbf = bf_prev;
996 al = get_frame_info(bf->bf_mpdu)->framelen;
997 bf->bf_state.bf_type = BUF_AMPDU;
999 TX_STAT_INC(txq->axq_qnum, a_aggr);
1010 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1011 * width - 0 for 20 MHz, 1 for 40 MHz
1012 * half_gi - to use 4us v/s 3.6 us for symbol time
1014 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
1015 int width, int half_gi, bool shortPreamble)
1017 u32 nbits, nsymbits, duration, nsymbols;
1020 /* find number of symbols: PLCP + data */
1021 streams = HT_RC_2_STREAMS(rix);
1022 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
1023 nsymbits = bits_per_symbol[rix % 8][width] * streams;
1024 nsymbols = (nbits + nsymbits - 1) / nsymbits;
1027 duration = SYMBOL_TIME(nsymbols);
1029 duration = SYMBOL_TIME_HALFGI(nsymbols);
1031 /* addup duration for legacy/ht training and signal fields */
1032 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1037 static int ath_max_framelen(int usec, int mcs, bool ht40, bool sgi)
1039 int streams = HT_RC_2_STREAMS(mcs);
1043 symbols = sgi ? TIME_SYMBOLS_HALFGI(usec) : TIME_SYMBOLS(usec);
1044 bits = symbols * bits_per_symbol[mcs % 8][ht40] * streams;
1045 bits -= OFDM_PLCP_BITS;
1047 bytes -= L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1054 void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop)
1056 u16 *cur_ht20, *cur_ht20_sgi, *cur_ht40, *cur_ht40_sgi;
1059 /* 4ms is the default (and maximum) duration */
1060 if (!txop || txop > 4096)
1063 cur_ht20 = sc->tx.max_aggr_framelen[queue][MCS_HT20];
1064 cur_ht20_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT20_SGI];
1065 cur_ht40 = sc->tx.max_aggr_framelen[queue][MCS_HT40];
1066 cur_ht40_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT40_SGI];
1067 for (mcs = 0; mcs < 32; mcs++) {
1068 cur_ht20[mcs] = ath_max_framelen(txop, mcs, false, false);
1069 cur_ht20_sgi[mcs] = ath_max_framelen(txop, mcs, false, true);
1070 cur_ht40[mcs] = ath_max_framelen(txop, mcs, true, false);
1071 cur_ht40_sgi[mcs] = ath_max_framelen(txop, mcs, true, true);
1075 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf,
1076 struct ath_tx_info *info, int len, bool rts)
1078 struct ath_hw *ah = sc->sc_ah;
1079 struct sk_buff *skb;
1080 struct ieee80211_tx_info *tx_info;
1081 struct ieee80211_tx_rate *rates;
1082 const struct ieee80211_rate *rate;
1083 struct ieee80211_hdr *hdr;
1084 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
1085 u32 rts_thresh = sc->hw->wiphy->rts_threshold;
1090 tx_info = IEEE80211_SKB_CB(skb);
1092 hdr = (struct ieee80211_hdr *)skb->data;
1094 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1095 info->dur_update = !ieee80211_is_pspoll(hdr->frame_control);
1096 info->rtscts_rate = fi->rtscts_rate;
1098 for (i = 0; i < ARRAY_SIZE(bf->rates); i++) {
1099 bool is_40, is_sgi, is_sp;
1102 if (!rates[i].count || (rates[i].idx < 0))
1106 info->rates[i].Tries = rates[i].count;
1109 * Handle RTS threshold for unaggregated HT frames.
1111 if (bf_isampdu(bf) && !bf_isaggr(bf) &&
1112 (rates[i].flags & IEEE80211_TX_RC_MCS) &&
1113 unlikely(rts_thresh != (u32) -1)) {
1114 if (!rts_thresh || (len > rts_thresh))
1118 if (rts || rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1119 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1120 info->flags |= ATH9K_TXDESC_RTSENA;
1121 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1122 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1123 info->flags |= ATH9K_TXDESC_CTSENA;
1126 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1127 info->rates[i].RateFlags |= ATH9K_RATESERIES_2040;
1128 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
1129 info->rates[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
1131 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
1132 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
1133 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
1135 if (rates[i].flags & IEEE80211_TX_RC_MCS) {
1137 info->rates[i].Rate = rix | 0x80;
1138 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1139 ah->txchainmask, info->rates[i].Rate);
1140 info->rates[i].PktDuration = ath_pkt_duration(sc, rix, len,
1141 is_40, is_sgi, is_sp);
1142 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
1143 info->rates[i].RateFlags |= ATH9K_RATESERIES_STBC;
1148 rate = &sc->sbands[tx_info->band].bitrates[rates[i].idx];
1149 if ((tx_info->band == IEEE80211_BAND_2GHZ) &&
1150 !(rate->flags & IEEE80211_RATE_ERP_G))
1151 phy = WLAN_RC_PHY_CCK;
1153 phy = WLAN_RC_PHY_OFDM;
1155 info->rates[i].Rate = rate->hw_value;
1156 if (rate->hw_value_short) {
1157 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1158 info->rates[i].Rate |= rate->hw_value_short;
1163 if (bf->bf_state.bfs_paprd)
1164 info->rates[i].ChSel = ah->txchainmask;
1166 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1167 ah->txchainmask, info->rates[i].Rate);
1169 info->rates[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
1170 phy, rate->bitrate * 100, len, rix, is_sp);
1173 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1174 if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit))
1175 info->flags &= ~ATH9K_TXDESC_RTSENA;
1177 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
1178 if (info->flags & ATH9K_TXDESC_RTSENA)
1179 info->flags &= ~ATH9K_TXDESC_CTSENA;
1182 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1184 struct ieee80211_hdr *hdr;
1185 enum ath9k_pkt_type htype;
1188 hdr = (struct ieee80211_hdr *)skb->data;
1189 fc = hdr->frame_control;
1191 if (ieee80211_is_beacon(fc))
1192 htype = ATH9K_PKT_TYPE_BEACON;
1193 else if (ieee80211_is_probe_resp(fc))
1194 htype = ATH9K_PKT_TYPE_PROBE_RESP;
1195 else if (ieee80211_is_atim(fc))
1196 htype = ATH9K_PKT_TYPE_ATIM;
1197 else if (ieee80211_is_pspoll(fc))
1198 htype = ATH9K_PKT_TYPE_PSPOLL;
1200 htype = ATH9K_PKT_TYPE_NORMAL;
1205 static void ath_tx_fill_desc(struct ath_softc *sc, struct ath_buf *bf,
1206 struct ath_txq *txq, int len)
1208 struct ath_hw *ah = sc->sc_ah;
1209 struct ath_buf *bf_first = NULL;
1210 struct ath_tx_info info;
1211 u32 rts_thresh = sc->hw->wiphy->rts_threshold;
1214 memset(&info, 0, sizeof(info));
1215 info.is_first = true;
1216 info.is_last = true;
1217 info.txpower = MAX_RATE_POWER;
1218 info.qcu = txq->axq_qnum;
1221 struct sk_buff *skb = bf->bf_mpdu;
1222 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1223 struct ath_frame_info *fi = get_frame_info(skb);
1224 bool aggr = !!(bf->bf_state.bf_type & BUF_AGGR);
1226 info.type = get_hw_packet_type(skb);
1228 info.link = bf->bf_next->bf_daddr;
1230 info.link = (sc->tx99_state) ? bf->bf_daddr : 0;
1235 if (!sc->tx99_state)
1236 info.flags = ATH9K_TXDESC_INTREQ;
1237 if ((tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT) ||
1238 txq == sc->tx.uapsdq)
1239 info.flags |= ATH9K_TXDESC_CLRDMASK;
1241 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1242 info.flags |= ATH9K_TXDESC_NOACK;
1243 if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
1244 info.flags |= ATH9K_TXDESC_LDPC;
1246 if (bf->bf_state.bfs_paprd)
1247 info.flags |= (u32) bf->bf_state.bfs_paprd <<
1248 ATH9K_TXDESC_PAPRD_S;
1251 * mac80211 doesn't handle RTS threshold for HT because
1252 * the decision has to be taken based on AMPDU length
1253 * and aggregation is done entirely inside ath9k.
1254 * Set the RTS/CTS flag for the first subframe based
1257 if (aggr && (bf == bf_first) &&
1258 unlikely(rts_thresh != (u32) -1)) {
1260 * "len" is the size of the entire AMPDU.
1262 if (!rts_thresh || (len > rts_thresh))
1269 ath_buf_set_rate(sc, bf, &info, len, rts);
1272 info.buf_addr[0] = bf->bf_buf_addr;
1273 info.buf_len[0] = skb->len;
1274 info.pkt_len = fi->framelen;
1275 info.keyix = fi->keyix;
1276 info.keytype = fi->keytype;
1280 info.aggr = AGGR_BUF_FIRST;
1281 else if (bf == bf_first->bf_lastbf)
1282 info.aggr = AGGR_BUF_LAST;
1284 info.aggr = AGGR_BUF_MIDDLE;
1286 info.ndelim = bf->bf_state.ndelim;
1287 info.aggr_len = len;
1290 if (bf == bf_first->bf_lastbf)
1293 ath9k_hw_set_txdesc(ah, bf->bf_desc, &info);
1299 ath_tx_form_burst(struct ath_softc *sc, struct ath_txq *txq,
1300 struct ath_atx_tid *tid, struct list_head *bf_q,
1301 struct ath_buf *bf_first, struct sk_buff_head *tid_q)
1303 struct ath_buf *bf = bf_first, *bf_prev = NULL;
1304 struct sk_buff *skb;
1308 struct ieee80211_tx_info *tx_info;
1312 __skb_unlink(skb, tid_q);
1313 list_add_tail(&bf->list, bf_q);
1315 bf_prev->bf_next = bf;
1321 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q);
1325 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1326 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
1329 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1333 static bool ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
1334 struct ath_atx_tid *tid, bool *stop)
1337 struct ieee80211_tx_info *tx_info;
1338 struct sk_buff_head *tid_q;
1339 struct list_head bf_q;
1341 bool aggr, last = true;
1343 if (!ath_tid_has_buffered(tid))
1346 INIT_LIST_HEAD(&bf_q);
1348 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q);
1352 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1353 aggr = !!(tx_info->flags & IEEE80211_TX_CTL_AMPDU);
1354 if ((aggr && txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) ||
1355 (!aggr && txq->axq_depth >= ATH_NON_AGGR_MIN_QDEPTH)) {
1360 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1362 last = ath_tx_form_aggr(sc, txq, tid, &bf_q, bf,
1365 ath_tx_form_burst(sc, txq, tid, &bf_q, bf, tid_q);
1367 if (list_empty(&bf_q))
1370 if (tid->ac->clear_ps_filter || tid->an->no_ps_filter) {
1371 tid->ac->clear_ps_filter = false;
1372 tx_info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
1375 ath_tx_fill_desc(sc, bf, txq, aggr_len);
1376 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1380 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
1383 struct ath_atx_tid *txtid;
1384 struct ath_txq *txq;
1385 struct ath_node *an;
1388 an = (struct ath_node *)sta->drv_priv;
1389 txtid = ATH_AN_2_TID(an, tid);
1390 txq = txtid->ac->txq;
1392 ath_txq_lock(sc, txq);
1394 /* update ampdu factor/density, they may have changed. This may happen
1395 * in HT IBSS when a beacon with HT-info is received after the station
1396 * has already been added.
1398 if (sta->ht_cap.ht_supported) {
1399 an->maxampdu = (1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
1400 sta->ht_cap.ampdu_factor)) - 1;
1401 density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density);
1402 an->mpdudensity = density;
1405 /* force sequence number allocation for pending frames */
1406 ath_tx_tid_change_state(sc, txtid);
1408 txtid->active = true;
1409 txtid->paused = true;
1410 *ssn = txtid->seq_start = txtid->seq_next;
1411 txtid->bar_index = -1;
1413 memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf));
1414 txtid->baw_head = txtid->baw_tail = 0;
1416 ath_txq_unlock_complete(sc, txq);
1421 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
1423 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1424 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
1425 struct ath_txq *txq = txtid->ac->txq;
1427 ath_txq_lock(sc, txq);
1428 txtid->active = false;
1429 txtid->paused = false;
1430 ath_tx_flush_tid(sc, txtid);
1431 ath_tx_tid_change_state(sc, txtid);
1432 ath_txq_unlock_complete(sc, txq);
1435 void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc,
1436 struct ath_node *an)
1438 struct ath_atx_tid *tid;
1439 struct ath_atx_ac *ac;
1440 struct ath_txq *txq;
1444 for (tidno = 0, tid = &an->tid[tidno];
1445 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
1453 ath_txq_lock(sc, txq);
1455 buffered = ath_tid_has_buffered(tid);
1458 list_del(&tid->list);
1462 list_del(&ac->list);
1465 ath_txq_unlock(sc, txq);
1467 ieee80211_sta_set_buffered(sta, tidno, buffered);
1471 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an)
1473 struct ath_atx_tid *tid;
1474 struct ath_atx_ac *ac;
1475 struct ath_txq *txq;
1478 for (tidno = 0, tid = &an->tid[tidno];
1479 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
1484 ath_txq_lock(sc, txq);
1485 ac->clear_ps_filter = true;
1487 if (!tid->paused && ath_tid_has_buffered(tid)) {
1488 ath_tx_queue_tid(txq, tid);
1489 ath_txq_schedule(sc, txq);
1492 ath_txq_unlock_complete(sc, txq);
1496 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta,
1499 struct ath_atx_tid *tid;
1500 struct ath_node *an;
1501 struct ath_txq *txq;
1503 an = (struct ath_node *)sta->drv_priv;
1504 tid = ATH_AN_2_TID(an, tidno);
1507 ath_txq_lock(sc, txq);
1509 tid->baw_size = IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
1510 tid->paused = false;
1512 if (ath_tid_has_buffered(tid)) {
1513 ath_tx_queue_tid(txq, tid);
1514 ath_txq_schedule(sc, txq);
1517 ath_txq_unlock_complete(sc, txq);
1520 void ath9k_release_buffered_frames(struct ieee80211_hw *hw,
1521 struct ieee80211_sta *sta,
1522 u16 tids, int nframes,
1523 enum ieee80211_frame_release_type reason,
1526 struct ath_softc *sc = hw->priv;
1527 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1528 struct ath_txq *txq = sc->tx.uapsdq;
1529 struct ieee80211_tx_info *info;
1530 struct list_head bf_q;
1531 struct ath_buf *bf_tail = NULL, *bf;
1532 struct sk_buff_head *tid_q;
1536 INIT_LIST_HEAD(&bf_q);
1537 for (i = 0; tids && nframes; i++, tids >>= 1) {
1538 struct ath_atx_tid *tid;
1543 tid = ATH_AN_2_TID(an, i);
1547 ath_txq_lock(sc, tid->ac->txq);
1548 while (nframes > 0) {
1549 bf = ath_tx_get_tid_subframe(sc, sc->tx.uapsdq, tid, &tid_q);
1553 __skb_unlink(bf->bf_mpdu, tid_q);
1554 list_add_tail(&bf->list, &bf_q);
1555 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1556 if (bf_isampdu(bf)) {
1557 ath_tx_addto_baw(sc, tid, bf);
1558 bf->bf_state.bf_type &= ~BUF_AGGR;
1561 bf_tail->bf_next = bf;
1566 TX_STAT_INC(txq->axq_qnum, a_queued_hw);
1568 if (an->sta && !ath_tid_has_buffered(tid))
1569 ieee80211_sta_set_buffered(an->sta, i, false);
1571 ath_txq_unlock_complete(sc, tid->ac->txq);
1574 if (list_empty(&bf_q))
1577 info = IEEE80211_SKB_CB(bf_tail->bf_mpdu);
1578 info->flags |= IEEE80211_TX_STATUS_EOSP;
1580 bf = list_first_entry(&bf_q, struct ath_buf, list);
1581 ath_txq_lock(sc, txq);
1582 ath_tx_fill_desc(sc, bf, txq, 0);
1583 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1584 ath_txq_unlock(sc, txq);
1587 /********************/
1588 /* Queue Management */
1589 /********************/
1591 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
1593 struct ath_hw *ah = sc->sc_ah;
1594 struct ath9k_tx_queue_info qi;
1595 static const int subtype_txq_to_hwq[] = {
1596 [IEEE80211_AC_BE] = ATH_TXQ_AC_BE,
1597 [IEEE80211_AC_BK] = ATH_TXQ_AC_BK,
1598 [IEEE80211_AC_VI] = ATH_TXQ_AC_VI,
1599 [IEEE80211_AC_VO] = ATH_TXQ_AC_VO,
1603 memset(&qi, 0, sizeof(qi));
1604 qi.tqi_subtype = subtype_txq_to_hwq[subtype];
1605 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
1606 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
1607 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
1608 qi.tqi_physCompBuf = 0;
1611 * Enable interrupts only for EOL and DESC conditions.
1612 * We mark tx descriptors to receive a DESC interrupt
1613 * when a tx queue gets deep; otherwise waiting for the
1614 * EOL to reap descriptors. Note that this is done to
1615 * reduce interrupt load and this only defers reaping
1616 * descriptors, never transmitting frames. Aside from
1617 * reducing interrupts this also permits more concurrency.
1618 * The only potential downside is if the tx queue backs
1619 * up in which case the top half of the kernel may backup
1620 * due to a lack of tx descriptors.
1622 * The UAPSD queue is an exception, since we take a desc-
1623 * based intr on the EOSP frames.
1625 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1626 qi.tqi_qflags = TXQ_FLAG_TXINT_ENABLE;
1628 if (qtype == ATH9K_TX_QUEUE_UAPSD)
1629 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
1631 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
1632 TXQ_FLAG_TXDESCINT_ENABLE;
1634 axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
1635 if (axq_qnum == -1) {
1637 * NB: don't print a message, this happens
1638 * normally on parts with too few tx queues
1642 if (!ATH_TXQ_SETUP(sc, axq_qnum)) {
1643 struct ath_txq *txq = &sc->tx.txq[axq_qnum];
1645 txq->axq_qnum = axq_qnum;
1646 txq->mac80211_qnum = -1;
1647 txq->axq_link = NULL;
1648 __skb_queue_head_init(&txq->complete_q);
1649 INIT_LIST_HEAD(&txq->axq_q);
1650 INIT_LIST_HEAD(&txq->axq_acq);
1651 spin_lock_init(&txq->axq_lock);
1653 txq->axq_ampdu_depth = 0;
1654 txq->axq_tx_inprogress = false;
1655 sc->tx.txqsetup |= 1<<axq_qnum;
1657 txq->txq_headidx = txq->txq_tailidx = 0;
1658 for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
1659 INIT_LIST_HEAD(&txq->txq_fifo[i]);
1661 return &sc->tx.txq[axq_qnum];
1664 int ath_txq_update(struct ath_softc *sc, int qnum,
1665 struct ath9k_tx_queue_info *qinfo)
1667 struct ath_hw *ah = sc->sc_ah;
1669 struct ath9k_tx_queue_info qi;
1671 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
1673 ath9k_hw_get_txq_props(ah, qnum, &qi);
1674 qi.tqi_aifs = qinfo->tqi_aifs;
1675 qi.tqi_cwmin = qinfo->tqi_cwmin;
1676 qi.tqi_cwmax = qinfo->tqi_cwmax;
1677 qi.tqi_burstTime = qinfo->tqi_burstTime;
1678 qi.tqi_readyTime = qinfo->tqi_readyTime;
1680 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
1681 ath_err(ath9k_hw_common(sc->sc_ah),
1682 "Unable to update hardware queue %u!\n", qnum);
1685 ath9k_hw_resettxqueue(ah, qnum);
1691 int ath_cabq_update(struct ath_softc *sc)
1693 struct ath9k_tx_queue_info qi;
1694 struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
1695 int qnum = sc->beacon.cabq->axq_qnum;
1697 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
1699 qi.tqi_readyTime = (cur_conf->beacon_interval *
1700 ATH_CABQ_READY_TIME) / 100;
1701 ath_txq_update(sc, qnum, &qi);
1706 static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq,
1707 struct list_head *list)
1709 struct ath_buf *bf, *lastbf;
1710 struct list_head bf_head;
1711 struct ath_tx_status ts;
1713 memset(&ts, 0, sizeof(ts));
1714 ts.ts_status = ATH9K_TX_FLUSH;
1715 INIT_LIST_HEAD(&bf_head);
1717 while (!list_empty(list)) {
1718 bf = list_first_entry(list, struct ath_buf, list);
1720 if (bf->bf_state.stale) {
1721 list_del(&bf->list);
1723 ath_tx_return_buffer(sc, bf);
1727 lastbf = bf->bf_lastbf;
1728 list_cut_position(&bf_head, list, &lastbf->list);
1729 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
1734 * Drain a given TX queue (could be Beacon or Data)
1736 * This assumes output has been stopped and
1737 * we do not need to block ath_tx_tasklet.
1739 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq)
1741 ath_txq_lock(sc, txq);
1743 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1744 int idx = txq->txq_tailidx;
1746 while (!list_empty(&txq->txq_fifo[idx])) {
1747 ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx]);
1749 INCR(idx, ATH_TXFIFO_DEPTH);
1751 txq->txq_tailidx = idx;
1754 txq->axq_link = NULL;
1755 txq->axq_tx_inprogress = false;
1756 ath_drain_txq_list(sc, txq, &txq->axq_q);
1758 ath_txq_unlock_complete(sc, txq);
1761 bool ath_drain_all_txq(struct ath_softc *sc)
1763 struct ath_hw *ah = sc->sc_ah;
1764 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1765 struct ath_txq *txq;
1769 if (test_bit(SC_OP_INVALID, &sc->sc_flags))
1772 ath9k_hw_abort_tx_dma(ah);
1774 /* Check if any queue remains active */
1775 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1776 if (!ATH_TXQ_SETUP(sc, i))
1779 if (!sc->tx.txq[i].axq_depth)
1782 if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum))
1787 ath_err(common, "Failed to stop TX DMA, queues=0x%03x!\n", npend);
1789 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1790 if (!ATH_TXQ_SETUP(sc, i))
1794 * The caller will resume queues with ieee80211_wake_queues.
1795 * Mark the queue as not stopped to prevent ath_tx_complete
1796 * from waking the queue too early.
1798 txq = &sc->tx.txq[i];
1799 txq->stopped = false;
1800 ath_draintxq(sc, txq);
1806 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1808 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1809 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1812 /* For each axq_acq entry, for each tid, try to schedule packets
1813 * for transmit until ampdu_depth has reached min Q depth.
1815 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1817 struct ath_atx_ac *ac, *last_ac;
1818 struct ath_atx_tid *tid, *last_tid;
1821 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags) ||
1822 list_empty(&txq->axq_acq))
1827 last_ac = list_entry(txq->axq_acq.prev, struct ath_atx_ac, list);
1828 while (!list_empty(&txq->axq_acq)) {
1831 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
1832 last_tid = list_entry(ac->tid_q.prev, struct ath_atx_tid, list);
1833 list_del(&ac->list);
1836 while (!list_empty(&ac->tid_q)) {
1838 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid,
1840 list_del(&tid->list);
1846 if (ath_tx_sched_aggr(sc, txq, tid, &stop))
1850 * add tid to round-robin queue if more frames
1851 * are pending for the tid
1853 if (ath_tid_has_buffered(tid))
1854 ath_tx_queue_tid(txq, tid);
1856 if (stop || tid == last_tid)
1860 if (!list_empty(&ac->tid_q) && !ac->sched) {
1862 list_add_tail(&ac->list, &txq->axq_acq);
1868 if (ac == last_ac) {
1873 last_ac = list_entry(txq->axq_acq.prev,
1874 struct ath_atx_ac, list);
1886 * Insert a chain of ath_buf (descriptors) on a txq and
1887 * assume the descriptors are already chained together by caller.
1889 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1890 struct list_head *head, bool internal)
1892 struct ath_hw *ah = sc->sc_ah;
1893 struct ath_common *common = ath9k_hw_common(ah);
1894 struct ath_buf *bf, *bf_last;
1895 bool puttxbuf = false;
1899 * Insert the frame on the outbound list and
1900 * pass it on to the hardware.
1903 if (list_empty(head))
1906 edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1907 bf = list_first_entry(head, struct ath_buf, list);
1908 bf_last = list_entry(head->prev, struct ath_buf, list);
1910 ath_dbg(common, QUEUE, "qnum: %d, txq depth: %d\n",
1911 txq->axq_qnum, txq->axq_depth);
1913 if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) {
1914 list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]);
1915 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
1918 list_splice_tail_init(head, &txq->axq_q);
1920 if (txq->axq_link) {
1921 ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr);
1922 ath_dbg(common, XMIT, "link[%u] (%p)=%llx (%p)\n",
1923 txq->axq_qnum, txq->axq_link,
1924 ito64(bf->bf_daddr), bf->bf_desc);
1928 txq->axq_link = bf_last->bf_desc;
1932 TX_STAT_INC(txq->axq_qnum, puttxbuf);
1933 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1934 ath_dbg(common, XMIT, "TXDP[%u] = %llx (%p)\n",
1935 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1938 if (!edma || sc->tx99_state) {
1939 TX_STAT_INC(txq->axq_qnum, txstart);
1940 ath9k_hw_txstart(ah, txq->axq_qnum);
1946 if (bf_is_ampdu_not_probing(bf))
1947 txq->axq_ampdu_depth++;
1949 bf_last = bf->bf_lastbf;
1950 bf = bf_last->bf_next;
1951 bf_last->bf_next = NULL;
1956 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
1957 struct ath_atx_tid *tid, struct sk_buff *skb)
1959 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1960 struct ath_frame_info *fi = get_frame_info(skb);
1961 struct list_head bf_head;
1962 struct ath_buf *bf = fi->bf;
1964 INIT_LIST_HEAD(&bf_head);
1965 list_add_tail(&bf->list, &bf_head);
1966 bf->bf_state.bf_type = 0;
1967 if (tid && (tx_info->flags & IEEE80211_TX_CTL_AMPDU)) {
1968 bf->bf_state.bf_type = BUF_AMPDU;
1969 ath_tx_addto_baw(sc, tid, bf);
1974 ath_tx_fill_desc(sc, bf, txq, fi->framelen);
1975 ath_tx_txqaddbuf(sc, txq, &bf_head, false);
1976 TX_STAT_INC(txq->axq_qnum, queued);
1979 static void setup_frame_info(struct ieee80211_hw *hw,
1980 struct ieee80211_sta *sta,
1981 struct sk_buff *skb,
1984 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1985 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
1986 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1987 const struct ieee80211_rate *rate;
1988 struct ath_frame_info *fi = get_frame_info(skb);
1989 struct ath_node *an = NULL;
1990 enum ath9k_key_type keytype;
1991 bool short_preamble = false;
1994 * We check if Short Preamble is needed for the CTS rate by
1995 * checking the BSS's global flag.
1996 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
1998 if (tx_info->control.vif &&
1999 tx_info->control.vif->bss_conf.use_short_preamble)
2000 short_preamble = true;
2002 rate = ieee80211_get_rts_cts_rate(hw, tx_info);
2003 keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
2006 an = (struct ath_node *) sta->drv_priv;
2008 memset(fi, 0, sizeof(*fi));
2010 fi->keyix = hw_key->hw_key_idx;
2011 else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0)
2012 fi->keyix = an->ps_key;
2014 fi->keyix = ATH9K_TXKEYIX_INVALID;
2015 fi->keytype = keytype;
2016 fi->framelen = framelen;
2020 fi->rtscts_rate = rate->hw_value;
2022 fi->rtscts_rate |= rate->hw_value_short;
2025 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
2027 struct ath_hw *ah = sc->sc_ah;
2028 struct ath9k_channel *curchan = ah->curchan;
2030 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && IS_CHAN_5GHZ(curchan) &&
2031 (chainmask == 0x7) && (rate < 0x90))
2033 else if (AR_SREV_9462(ah) && ath9k_hw_btcoex_is_enabled(ah) &&
2041 * Assign a descriptor (and sequence number if necessary,
2042 * and map buffer for DMA. Frees skb on error
2044 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
2045 struct ath_txq *txq,
2046 struct ath_atx_tid *tid,
2047 struct sk_buff *skb)
2049 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2050 struct ath_frame_info *fi = get_frame_info(skb);
2051 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2056 bf = ath_tx_get_buffer(sc);
2058 ath_dbg(common, XMIT, "TX buffers are full\n");
2062 ATH_TXBUF_RESET(bf);
2065 fragno = le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG;
2066 seqno = tid->seq_next;
2067 hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
2070 hdr->seq_ctrl |= cpu_to_le16(fragno);
2072 if (!ieee80211_has_morefrags(hdr->frame_control))
2073 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
2075 bf->bf_state.seqno = seqno;
2080 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
2081 skb->len, DMA_TO_DEVICE);
2082 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
2084 bf->bf_buf_addr = 0;
2085 ath_err(ath9k_hw_common(sc->sc_ah),
2086 "dma_mapping_error() on TX\n");
2087 ath_tx_return_buffer(sc, bf);
2096 static int ath_tx_prepare(struct ieee80211_hw *hw, struct sk_buff *skb,
2097 struct ath_tx_control *txctl)
2099 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2100 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2101 struct ieee80211_sta *sta = txctl->sta;
2102 struct ieee80211_vif *vif = info->control.vif;
2103 struct ath_vif *avp;
2104 struct ath_softc *sc = hw->priv;
2105 int frmlen = skb->len + FCS_LEN;
2106 int padpos, padsize;
2108 /* NOTE: sta can be NULL according to net/mac80211.h */
2110 txctl->an = (struct ath_node *)sta->drv_priv;
2111 else if (vif && ieee80211_is_data(hdr->frame_control)) {
2112 avp = (void *)vif->drv_priv;
2113 txctl->an = &avp->mcast_node;
2116 if (info->control.hw_key)
2117 frmlen += info->control.hw_key->icv_len;
2120 * As a temporary workaround, assign seq# here; this will likely need
2121 * to be cleaned up to work better with Beacon transmission and virtual
2124 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2125 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2126 sc->tx.seq_no += 0x10;
2127 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2128 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
2131 if ((vif && vif->type != NL80211_IFTYPE_AP &&
2132 vif->type != NL80211_IFTYPE_AP_VLAN) ||
2133 !ieee80211_is_data(hdr->frame_control))
2134 info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
2136 /* Add the padding after the header if this is not already done */
2137 padpos = ieee80211_hdrlen(hdr->frame_control);
2138 padsize = padpos & 3;
2139 if (padsize && skb->len > padpos) {
2140 if (skb_headroom(skb) < padsize)
2143 skb_push(skb, padsize);
2144 memmove(skb->data, skb->data + padsize, padpos);
2147 setup_frame_info(hw, sta, skb, frmlen);
2152 /* Upon failure caller should free skb */
2153 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
2154 struct ath_tx_control *txctl)
2156 struct ieee80211_hdr *hdr;
2157 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2158 struct ieee80211_sta *sta = txctl->sta;
2159 struct ieee80211_vif *vif = info->control.vif;
2160 struct ath_softc *sc = hw->priv;
2161 struct ath_txq *txq = txctl->txq;
2162 struct ath_atx_tid *tid = NULL;
2167 ret = ath_tx_prepare(hw, skb, txctl);
2171 hdr = (struct ieee80211_hdr *) skb->data;
2173 * At this point, the vif, hw_key and sta pointers in the tx control
2174 * info are no longer valid (overwritten by the ath_frame_info data.
2177 q = skb_get_queue_mapping(skb);
2179 ath_txq_lock(sc, txq);
2180 if (txq == sc->tx.txq_map[q] &&
2181 ++txq->pending_frames > sc->tx.txq_max_pending[q] &&
2183 ieee80211_stop_queue(sc->hw, q);
2184 txq->stopped = true;
2187 if (info->flags & IEEE80211_TX_CTL_PS_RESPONSE) {
2188 ath_txq_unlock(sc, txq);
2189 txq = sc->tx.uapsdq;
2190 ath_txq_lock(sc, txq);
2191 } else if (txctl->an &&
2192 ieee80211_is_data_present(hdr->frame_control)) {
2193 tid = ath_get_skb_tid(sc, txctl->an, skb);
2195 WARN_ON(tid->ac->txq != txctl->txq);
2197 if (info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT)
2198 tid->ac->clear_ps_filter = true;
2201 * Add this frame to software queue for scheduling later
2204 TX_STAT_INC(txq->axq_qnum, a_queued_sw);
2205 __skb_queue_tail(&tid->buf_q, skb);
2206 if (!txctl->an->sleeping)
2207 ath_tx_queue_tid(txq, tid);
2209 ath_txq_schedule(sc, txq);
2213 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
2215 ath_txq_skb_done(sc, txq, skb);
2217 dev_kfree_skb_any(skb);
2219 ieee80211_free_txskb(sc->hw, skb);
2223 bf->bf_state.bfs_paprd = txctl->paprd;
2226 bf->bf_state.bfs_paprd_timestamp = jiffies;
2228 ath_set_rates(vif, sta, bf);
2229 ath_tx_send_normal(sc, txq, tid, skb);
2232 ath_txq_unlock(sc, txq);
2237 void ath_tx_cabq(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2238 struct sk_buff *skb)
2240 struct ath_softc *sc = hw->priv;
2241 struct ath_tx_control txctl = {
2242 .txq = sc->beacon.cabq
2244 struct ath_tx_info info = {};
2245 struct ieee80211_hdr *hdr;
2246 struct ath_buf *bf_tail = NULL;
2253 sc->cur_beacon_conf.beacon_interval * 1000 *
2254 sc->cur_beacon_conf.dtim_period / ATH_BCBUF;
2257 struct ath_frame_info *fi = get_frame_info(skb);
2259 if (ath_tx_prepare(hw, skb, &txctl))
2262 bf = ath_tx_setup_buffer(sc, txctl.txq, NULL, skb);
2267 ath_set_rates(vif, NULL, bf);
2268 ath_buf_set_rate(sc, bf, &info, fi->framelen, false);
2269 duration += info.rates[0].PktDuration;
2271 bf_tail->bf_next = bf;
2273 list_add_tail(&bf->list, &bf_q);
2277 if (duration > max_duration)
2280 skb = ieee80211_get_buffered_bc(hw, vif);
2284 ieee80211_free_txskb(hw, skb);
2286 if (list_empty(&bf_q))
2289 bf = list_first_entry(&bf_q, struct ath_buf, list);
2290 hdr = (struct ieee80211_hdr *) bf->bf_mpdu->data;
2292 if (hdr->frame_control & IEEE80211_FCTL_MOREDATA) {
2293 hdr->frame_control &= ~IEEE80211_FCTL_MOREDATA;
2294 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
2295 sizeof(*hdr), DMA_TO_DEVICE);
2298 ath_txq_lock(sc, txctl.txq);
2299 ath_tx_fill_desc(sc, bf, txctl.txq, 0);
2300 ath_tx_txqaddbuf(sc, txctl.txq, &bf_q, false);
2301 TX_STAT_INC(txctl.txq->axq_qnum, queued);
2302 ath_txq_unlock(sc, txctl.txq);
2309 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
2310 int tx_flags, struct ath_txq *txq)
2312 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2313 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2314 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
2315 int padpos, padsize;
2316 unsigned long flags;
2318 ath_dbg(common, XMIT, "TX complete: skb: %p\n", skb);
2320 if (sc->sc_ah->caldata)
2321 set_bit(PAPRD_PACKET_SENT, &sc->sc_ah->caldata->cal_flags);
2323 if (!(tx_flags & ATH_TX_ERROR))
2324 /* Frame was ACKed */
2325 tx_info->flags |= IEEE80211_TX_STAT_ACK;
2327 padpos = ieee80211_hdrlen(hdr->frame_control);
2328 padsize = padpos & 3;
2329 if (padsize && skb->len>padpos+padsize) {
2331 * Remove MAC header padding before giving the frame back to
2334 memmove(skb->data + padsize, skb->data, padpos);
2335 skb_pull(skb, padsize);
2338 spin_lock_irqsave(&sc->sc_pm_lock, flags);
2339 if ((sc->ps_flags & PS_WAIT_FOR_TX_ACK) && !txq->axq_depth) {
2340 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
2342 "Going back to sleep after having received TX status (0x%lx)\n",
2343 sc->ps_flags & (PS_WAIT_FOR_BEACON |
2345 PS_WAIT_FOR_PSPOLL_DATA |
2346 PS_WAIT_FOR_TX_ACK));
2348 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
2350 __skb_queue_tail(&txq->complete_q, skb);
2351 ath_txq_skb_done(sc, txq, skb);
2354 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
2355 struct ath_txq *txq, struct list_head *bf_q,
2356 struct ath_tx_status *ts, int txok)
2358 struct sk_buff *skb = bf->bf_mpdu;
2359 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2360 unsigned long flags;
2364 tx_flags |= ATH_TX_ERROR;
2366 if (ts->ts_status & ATH9K_TXERR_FILT)
2367 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
2369 dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE);
2370 bf->bf_buf_addr = 0;
2372 goto skip_tx_complete;
2374 if (bf->bf_state.bfs_paprd) {
2375 if (time_after(jiffies,
2376 bf->bf_state.bfs_paprd_timestamp +
2377 msecs_to_jiffies(ATH_PAPRD_TIMEOUT)))
2378 dev_kfree_skb_any(skb);
2380 complete(&sc->paprd_complete);
2382 ath_debug_stat_tx(sc, bf, ts, txq, tx_flags);
2383 ath_tx_complete(sc, skb, tx_flags, txq);
2386 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
2387 * accidentally reference it later.
2392 * Return the list of ath_buf of this mpdu to free queue
2394 spin_lock_irqsave(&sc->tx.txbuflock, flags);
2395 list_splice_tail_init(bf_q, &sc->tx.txbuf);
2396 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
2399 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
2400 struct ath_tx_status *ts, int nframes, int nbad,
2403 struct sk_buff *skb = bf->bf_mpdu;
2404 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2405 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2406 struct ieee80211_hw *hw = sc->hw;
2407 struct ath_hw *ah = sc->sc_ah;
2411 tx_info->status.ack_signal = ts->ts_rssi;
2413 tx_rateindex = ts->ts_rateindex;
2414 WARN_ON(tx_rateindex >= hw->max_rates);
2416 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
2417 tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
2419 BUG_ON(nbad > nframes);
2421 tx_info->status.ampdu_len = nframes;
2422 tx_info->status.ampdu_ack_len = nframes - nbad;
2424 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
2425 (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) == 0) {
2427 * If an underrun error is seen assume it as an excessive
2428 * retry only if max frame trigger level has been reached
2429 * (2 KB for single stream, and 4 KB for dual stream).
2430 * Adjust the long retry as if the frame was tried
2431 * hw->max_rate_tries times to affect how rate control updates
2432 * PER for the failed rate.
2433 * In case of congestion on the bus penalizing this type of
2434 * underruns should help hardware actually transmit new frames
2435 * successfully by eventually preferring slower rates.
2436 * This itself should also alleviate congestion on the bus.
2438 if (unlikely(ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
2439 ATH9K_TX_DELIM_UNDERRUN)) &&
2440 ieee80211_is_data(hdr->frame_control) &&
2441 ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level)
2442 tx_info->status.rates[tx_rateindex].count =
2446 for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
2447 tx_info->status.rates[i].count = 0;
2448 tx_info->status.rates[i].idx = -1;
2451 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
2454 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
2456 struct ath_hw *ah = sc->sc_ah;
2457 struct ath_common *common = ath9k_hw_common(ah);
2458 struct ath_buf *bf, *lastbf, *bf_held = NULL;
2459 struct list_head bf_head;
2460 struct ath_desc *ds;
2461 struct ath_tx_status ts;
2464 ath_dbg(common, QUEUE, "tx queue %d (%x), link %p\n",
2465 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
2468 ath_txq_lock(sc, txq);
2470 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags))
2473 if (list_empty(&txq->axq_q)) {
2474 txq->axq_link = NULL;
2475 ath_txq_schedule(sc, txq);
2478 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2481 * There is a race condition that a BH gets scheduled
2482 * after sw writes TxE and before hw re-load the last
2483 * descriptor to get the newly chained one.
2484 * Software must keep the last DONE descriptor as a
2485 * holding descriptor - software does so by marking
2486 * it with the STALE flag.
2489 if (bf->bf_state.stale) {
2491 if (list_is_last(&bf_held->list, &txq->axq_q))
2494 bf = list_entry(bf_held->list.next, struct ath_buf,
2498 lastbf = bf->bf_lastbf;
2499 ds = lastbf->bf_desc;
2501 memset(&ts, 0, sizeof(ts));
2502 status = ath9k_hw_txprocdesc(ah, ds, &ts);
2503 if (status == -EINPROGRESS)
2506 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2509 * Remove ath_buf's of the same transmit unit from txq,
2510 * however leave the last descriptor back as the holding
2511 * descriptor for hw.
2513 lastbf->bf_state.stale = true;
2514 INIT_LIST_HEAD(&bf_head);
2515 if (!list_is_singular(&lastbf->list))
2516 list_cut_position(&bf_head,
2517 &txq->axq_q, lastbf->list.prev);
2520 list_del(&bf_held->list);
2521 ath_tx_return_buffer(sc, bf_held);
2524 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2526 ath_txq_unlock_complete(sc, txq);
2529 void ath_tx_tasklet(struct ath_softc *sc)
2531 struct ath_hw *ah = sc->sc_ah;
2532 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1) & ah->intr_txqs;
2535 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2536 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2537 ath_tx_processq(sc, &sc->tx.txq[i]);
2541 void ath_tx_edma_tasklet(struct ath_softc *sc)
2543 struct ath_tx_status ts;
2544 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2545 struct ath_hw *ah = sc->sc_ah;
2546 struct ath_txq *txq;
2547 struct ath_buf *bf, *lastbf;
2548 struct list_head bf_head;
2549 struct list_head *fifo_list;
2553 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags))
2556 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts);
2557 if (status == -EINPROGRESS)
2559 if (status == -EIO) {
2560 ath_dbg(common, XMIT, "Error processing tx status\n");
2564 /* Process beacon completions separately */
2565 if (ts.qid == sc->beacon.beaconq) {
2566 sc->beacon.tx_processed = true;
2567 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2569 ath9k_csa_is_finished(sc);
2573 txq = &sc->tx.txq[ts.qid];
2575 ath_txq_lock(sc, txq);
2577 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2579 fifo_list = &txq->txq_fifo[txq->txq_tailidx];
2580 if (list_empty(fifo_list)) {
2581 ath_txq_unlock(sc, txq);
2585 bf = list_first_entry(fifo_list, struct ath_buf, list);
2586 if (bf->bf_state.stale) {
2587 list_del(&bf->list);
2588 ath_tx_return_buffer(sc, bf);
2589 bf = list_first_entry(fifo_list, struct ath_buf, list);
2592 lastbf = bf->bf_lastbf;
2594 INIT_LIST_HEAD(&bf_head);
2595 if (list_is_last(&lastbf->list, fifo_list)) {
2596 list_splice_tail_init(fifo_list, &bf_head);
2597 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
2599 if (!list_empty(&txq->axq_q)) {
2600 struct list_head bf_q;
2602 INIT_LIST_HEAD(&bf_q);
2603 txq->axq_link = NULL;
2604 list_splice_tail_init(&txq->axq_q, &bf_q);
2605 ath_tx_txqaddbuf(sc, txq, &bf_q, true);
2608 lastbf->bf_state.stale = true;
2610 list_cut_position(&bf_head, fifo_list,
2614 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2615 ath_txq_unlock_complete(sc, txq);
2623 static int ath_txstatus_setup(struct ath_softc *sc, int size)
2625 struct ath_descdma *dd = &sc->txsdma;
2626 u8 txs_len = sc->sc_ah->caps.txs_len;
2628 dd->dd_desc_len = size * txs_len;
2629 dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len,
2630 &dd->dd_desc_paddr, GFP_KERNEL);
2637 static int ath_tx_edma_init(struct ath_softc *sc)
2641 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
2643 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
2644 sc->txsdma.dd_desc_paddr,
2645 ATH_TXSTATUS_RING_SIZE);
2650 int ath_tx_init(struct ath_softc *sc, int nbufs)
2652 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2655 spin_lock_init(&sc->tx.txbuflock);
2657 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2661 "Failed to allocate tx descriptors: %d\n", error);
2665 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2666 "beacon", ATH_BCBUF, 1, 1);
2669 "Failed to allocate beacon descriptors: %d\n", error);
2673 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
2675 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
2676 error = ath_tx_edma_init(sc);
2681 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2683 struct ath_atx_tid *tid;
2684 struct ath_atx_ac *ac;
2687 for (tidno = 0, tid = &an->tid[tidno];
2688 tidno < IEEE80211_NUM_TIDS;
2692 tid->seq_start = tid->seq_next = 0;
2693 tid->baw_size = WME_MAX_BA;
2694 tid->baw_head = tid->baw_tail = 0;
2696 tid->paused = false;
2697 tid->active = false;
2698 __skb_queue_head_init(&tid->buf_q);
2699 __skb_queue_head_init(&tid->retry_q);
2700 acno = TID_TO_WME_AC(tidno);
2701 tid->ac = &an->ac[acno];
2704 for (acno = 0, ac = &an->ac[acno];
2705 acno < IEEE80211_NUM_ACS; acno++, ac++) {
2707 ac->clear_ps_filter = true;
2708 ac->txq = sc->tx.txq_map[acno];
2709 INIT_LIST_HEAD(&ac->tid_q);
2713 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2715 struct ath_atx_ac *ac;
2716 struct ath_atx_tid *tid;
2717 struct ath_txq *txq;
2720 for (tidno = 0, tid = &an->tid[tidno];
2721 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
2726 ath_txq_lock(sc, txq);
2729 list_del(&tid->list);
2734 list_del(&ac->list);
2735 tid->ac->sched = false;
2738 ath_tid_drain(sc, txq, tid);
2739 tid->active = false;
2741 ath_txq_unlock(sc, txq);
2745 #ifdef CONFIG_ATH9K_TX99
2747 int ath9k_tx99_send(struct ath_softc *sc, struct sk_buff *skb,
2748 struct ath_tx_control *txctl)
2750 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2751 struct ath_frame_info *fi = get_frame_info(skb);
2752 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2754 int padpos, padsize;
2756 padpos = ieee80211_hdrlen(hdr->frame_control);
2757 padsize = padpos & 3;
2759 if (padsize && skb->len > padpos) {
2760 if (skb_headroom(skb) < padsize) {
2761 ath_dbg(common, XMIT,
2762 "tx99 padding failed\n");
2766 skb_push(skb, padsize);
2767 memmove(skb->data, skb->data + padsize, padpos);
2770 fi->keyix = ATH9K_TXKEYIX_INVALID;
2771 fi->framelen = skb->len + FCS_LEN;
2772 fi->keytype = ATH9K_KEY_TYPE_CLEAR;
2774 bf = ath_tx_setup_buffer(sc, txctl->txq, NULL, skb);
2776 ath_dbg(common, XMIT, "tx99 buffer setup failed\n");
2780 ath_set_rates(sc->tx99_vif, NULL, bf);
2782 ath9k_hw_set_desc_link(sc->sc_ah, bf->bf_desc, bf->bf_daddr);
2783 ath9k_hw_tx99_start(sc->sc_ah, txctl->txq->axq_qnum);
2785 ath_tx_send_normal(sc, txctl->txq, NULL, skb);
2790 #endif /* CONFIG_ATH9K_TX99 */