2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/dma-mapping.h>
18 #include <linux/relay.h>
20 #include "ar9003_mac.h"
22 #define SKB_CB_ATHBUF(__skb) (*((struct ath_rxbuf **)__skb->cb))
24 static inline bool ath9k_check_auto_sleep(struct ath_softc *sc)
26 return sc->ps_enabled &&
27 (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP);
31 * Setup and link descriptors.
33 * 11N: we can no longer afford to self link the last descriptor.
34 * MAC acknowledges BA status as long as it copies frames to host
35 * buffer (or rx fifo). This can incorrectly acknowledge packets
36 * to a sender if last desc is self-linked.
38 static void ath_rx_buf_link(struct ath_softc *sc, struct ath_rxbuf *bf)
40 struct ath_hw *ah = sc->sc_ah;
41 struct ath_common *common = ath9k_hw_common(ah);
46 ds->ds_link = 0; /* link to null */
47 ds->ds_data = bf->bf_buf_addr;
49 /* virtual addr of the beginning of the buffer. */
52 ds->ds_vdata = skb->data;
55 * setup rx descriptors. The rx_bufsize here tells the hardware
56 * how much data it can DMA to us and that we are prepared
59 ath9k_hw_setuprxdesc(ah, ds,
63 if (sc->rx.rxlink == NULL)
64 ath9k_hw_putrxbuf(ah, bf->bf_daddr);
66 *sc->rx.rxlink = bf->bf_daddr;
68 sc->rx.rxlink = &ds->ds_link;
71 static void ath_rx_buf_relink(struct ath_softc *sc, struct ath_rxbuf *bf)
74 ath_rx_buf_link(sc, sc->rx.buf_hold);
79 static void ath_setdefantenna(struct ath_softc *sc, u32 antenna)
81 /* XXX block beacon interrupts */
82 ath9k_hw_setantenna(sc->sc_ah, antenna);
83 sc->rx.defant = antenna;
84 sc->rx.rxotherant = 0;
87 static void ath_opmode_init(struct ath_softc *sc)
89 struct ath_hw *ah = sc->sc_ah;
90 struct ath_common *common = ath9k_hw_common(ah);
94 /* configure rx filter */
95 rfilt = ath_calcrxfilter(sc);
96 ath9k_hw_setrxfilter(ah, rfilt);
98 /* configure bssid mask */
99 ath_hw_setbssidmask(common);
101 /* configure operational mode */
102 ath9k_hw_setopmode(ah);
104 /* calculate and install multicast filter */
105 mfilt[0] = mfilt[1] = ~0;
106 ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]);
109 static bool ath_rx_edma_buf_link(struct ath_softc *sc,
110 enum ath9k_rx_qtype qtype)
112 struct ath_hw *ah = sc->sc_ah;
113 struct ath_rx_edma *rx_edma;
115 struct ath_rxbuf *bf;
117 rx_edma = &sc->rx.rx_edma[qtype];
118 if (skb_queue_len(&rx_edma->rx_fifo) >= rx_edma->rx_fifo_hwsize)
121 bf = list_first_entry(&sc->rx.rxbuf, struct ath_rxbuf, list);
122 list_del_init(&bf->list);
126 memset(skb->data, 0, ah->caps.rx_status_len);
127 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
128 ah->caps.rx_status_len, DMA_TO_DEVICE);
130 SKB_CB_ATHBUF(skb) = bf;
131 ath9k_hw_addrxbuf_edma(ah, bf->bf_buf_addr, qtype);
132 __skb_queue_tail(&rx_edma->rx_fifo, skb);
137 static void ath_rx_addbuffer_edma(struct ath_softc *sc,
138 enum ath9k_rx_qtype qtype)
140 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
141 struct ath_rxbuf *bf, *tbf;
143 if (list_empty(&sc->rx.rxbuf)) {
144 ath_dbg(common, QUEUE, "No free rx buf available\n");
148 list_for_each_entry_safe(bf, tbf, &sc->rx.rxbuf, list)
149 if (!ath_rx_edma_buf_link(sc, qtype))
154 static void ath_rx_remove_buffer(struct ath_softc *sc,
155 enum ath9k_rx_qtype qtype)
157 struct ath_rxbuf *bf;
158 struct ath_rx_edma *rx_edma;
161 rx_edma = &sc->rx.rx_edma[qtype];
163 while ((skb = __skb_dequeue(&rx_edma->rx_fifo)) != NULL) {
164 bf = SKB_CB_ATHBUF(skb);
166 list_add_tail(&bf->list, &sc->rx.rxbuf);
170 static void ath_rx_edma_cleanup(struct ath_softc *sc)
172 struct ath_hw *ah = sc->sc_ah;
173 struct ath_common *common = ath9k_hw_common(ah);
174 struct ath_rxbuf *bf;
176 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP);
177 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP);
179 list_for_each_entry(bf, &sc->rx.rxbuf, list) {
181 dma_unmap_single(sc->dev, bf->bf_buf_addr,
184 dev_kfree_skb_any(bf->bf_mpdu);
191 static void ath_rx_edma_init_queue(struct ath_rx_edma *rx_edma, int size)
193 __skb_queue_head_init(&rx_edma->rx_fifo);
194 rx_edma->rx_fifo_hwsize = size;
197 static int ath_rx_edma_init(struct ath_softc *sc, int nbufs)
199 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
200 struct ath_hw *ah = sc->sc_ah;
202 struct ath_rxbuf *bf;
206 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
207 ah->caps.rx_status_len);
209 ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_LP],
210 ah->caps.rx_lp_qdepth);
211 ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_HP],
212 ah->caps.rx_hp_qdepth);
214 size = sizeof(struct ath_rxbuf) * nbufs;
215 bf = devm_kzalloc(sc->dev, size, GFP_KERNEL);
219 INIT_LIST_HEAD(&sc->rx.rxbuf);
221 for (i = 0; i < nbufs; i++, bf++) {
222 skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_KERNEL);
228 memset(skb->data, 0, common->rx_bufsize);
231 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
234 if (unlikely(dma_mapping_error(sc->dev,
236 dev_kfree_skb_any(skb);
240 "dma_mapping_error() on RX init\n");
245 list_add_tail(&bf->list, &sc->rx.rxbuf);
251 ath_rx_edma_cleanup(sc);
255 static void ath_edma_start_recv(struct ath_softc *sc)
257 ath9k_hw_rxena(sc->sc_ah);
258 ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_HP);
259 ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_LP);
261 ath9k_hw_startpcureceive(sc->sc_ah, !!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL));
264 static void ath_edma_stop_recv(struct ath_softc *sc)
266 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP);
267 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP);
270 int ath_rx_init(struct ath_softc *sc, int nbufs)
272 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
274 struct ath_rxbuf *bf;
277 spin_lock_init(&sc->sc_pcu_lock);
279 common->rx_bufsize = IEEE80211_MAX_MPDU_LEN / 2 +
280 sc->sc_ah->caps.rx_status_len;
282 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
283 return ath_rx_edma_init(sc, nbufs);
285 ath_dbg(common, CONFIG, "cachelsz %u rxbufsize %u\n",
286 common->cachelsz, common->rx_bufsize);
288 /* Initialize rx descriptors */
290 error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf,
294 "failed to allocate rx descriptors: %d\n",
299 list_for_each_entry(bf, &sc->rx.rxbuf, list) {
300 skb = ath_rxbuf_alloc(common, common->rx_bufsize,
308 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
311 if (unlikely(dma_mapping_error(sc->dev,
313 dev_kfree_skb_any(skb);
317 "dma_mapping_error() on RX init\n");
322 sc->rx.rxlink = NULL;
330 void ath_rx_cleanup(struct ath_softc *sc)
332 struct ath_hw *ah = sc->sc_ah;
333 struct ath_common *common = ath9k_hw_common(ah);
335 struct ath_rxbuf *bf;
337 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
338 ath_rx_edma_cleanup(sc);
342 list_for_each_entry(bf, &sc->rx.rxbuf, list) {
345 dma_unmap_single(sc->dev, bf->bf_buf_addr,
356 * Calculate the receive filter according to the
357 * operating mode and state:
359 * o always accept unicast, broadcast, and multicast traffic
360 * o maintain current state of phy error reception (the hal
361 * may enable phy error frames for noise immunity work)
362 * o probe request frames are accepted only when operating in
363 * hostap, adhoc, or monitor modes
364 * o enable promiscuous mode according to the interface state
366 * - when operating in adhoc mode so the 802.11 layer creates
367 * node table entries for peers,
368 * - when operating in station mode for collecting rssi data when
369 * the station is otherwise quiet, or
370 * - when operating as a repeater so we see repeater-sta beacons
374 u32 ath_calcrxfilter(struct ath_softc *sc)
378 if (config_enabled(CONFIG_ATH9K_TX99))
381 rfilt = ATH9K_RX_FILTER_UCAST | ATH9K_RX_FILTER_BCAST
382 | ATH9K_RX_FILTER_MCAST;
384 /* if operating on a DFS channel, enable radar pulse detection */
385 if (sc->hw->conf.radar_enabled)
386 rfilt |= ATH9K_RX_FILTER_PHYRADAR | ATH9K_RX_FILTER_PHYERR;
388 if (sc->rx.rxfilter & FIF_PROBE_REQ)
389 rfilt |= ATH9K_RX_FILTER_PROBEREQ;
392 * Set promiscuous mode when FIF_PROMISC_IN_BSS is enabled for station
393 * mode interface or when in monitor mode. AP mode does not need this
394 * since it receives all in-BSS frames anyway.
396 if (sc->sc_ah->is_monitoring)
397 rfilt |= ATH9K_RX_FILTER_PROM;
399 if (sc->rx.rxfilter & FIF_CONTROL)
400 rfilt |= ATH9K_RX_FILTER_CONTROL;
402 if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) &&
404 !(sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC))
405 rfilt |= ATH9K_RX_FILTER_MYBEACON;
407 rfilt |= ATH9K_RX_FILTER_BEACON;
409 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
410 (sc->rx.rxfilter & FIF_PSPOLL))
411 rfilt |= ATH9K_RX_FILTER_PSPOLL;
413 if (conf_is_ht(&sc->hw->conf))
414 rfilt |= ATH9K_RX_FILTER_COMP_BAR;
416 if (sc->nvifs > 1 || (sc->rx.rxfilter & FIF_OTHER_BSS)) {
417 /* This is needed for older chips */
418 if (sc->sc_ah->hw_version.macVersion <= AR_SREV_VERSION_9160)
419 rfilt |= ATH9K_RX_FILTER_PROM;
420 rfilt |= ATH9K_RX_FILTER_MCAST_BCAST_ALL;
423 if (AR_SREV_9550(sc->sc_ah))
424 rfilt |= ATH9K_RX_FILTER_4ADDRESS;
430 int ath_startrecv(struct ath_softc *sc)
432 struct ath_hw *ah = sc->sc_ah;
433 struct ath_rxbuf *bf, *tbf;
435 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
436 ath_edma_start_recv(sc);
440 if (list_empty(&sc->rx.rxbuf))
443 sc->rx.buf_hold = NULL;
444 sc->rx.rxlink = NULL;
445 list_for_each_entry_safe(bf, tbf, &sc->rx.rxbuf, list) {
446 ath_rx_buf_link(sc, bf);
449 /* We could have deleted elements so the list may be empty now */
450 if (list_empty(&sc->rx.rxbuf))
453 bf = list_first_entry(&sc->rx.rxbuf, struct ath_rxbuf, list);
454 ath9k_hw_putrxbuf(ah, bf->bf_daddr);
459 ath9k_hw_startpcureceive(ah, !!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL));
464 static void ath_flushrecv(struct ath_softc *sc)
466 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
467 ath_rx_tasklet(sc, 1, true);
468 ath_rx_tasklet(sc, 1, false);
471 bool ath_stoprecv(struct ath_softc *sc)
473 struct ath_hw *ah = sc->sc_ah;
474 bool stopped, reset = false;
476 ath9k_hw_abortpcurecv(ah);
477 ath9k_hw_setrxfilter(ah, 0);
478 stopped = ath9k_hw_stopdmarecv(ah, &reset);
482 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
483 ath_edma_stop_recv(sc);
485 sc->rx.rxlink = NULL;
487 if (!(ah->ah_flags & AH_UNPLUGGED) &&
488 unlikely(!stopped)) {
489 ath_err(ath9k_hw_common(sc->sc_ah),
490 "Could not stop RX, we could be "
491 "confusing the DMA engine when we start RX up\n");
492 ATH_DBG_WARN_ON_ONCE(!stopped);
494 return stopped && !reset;
497 static bool ath_beacon_dtim_pending_cab(struct sk_buff *skb)
499 /* Check whether the Beacon frame has DTIM indicating buffered bc/mc */
500 struct ieee80211_mgmt *mgmt;
501 u8 *pos, *end, id, elen;
502 struct ieee80211_tim_ie *tim;
504 mgmt = (struct ieee80211_mgmt *)skb->data;
505 pos = mgmt->u.beacon.variable;
506 end = skb->data + skb->len;
508 while (pos + 2 < end) {
511 if (pos + elen > end)
514 if (id == WLAN_EID_TIM) {
515 if (elen < sizeof(*tim))
517 tim = (struct ieee80211_tim_ie *) pos;
518 if (tim->dtim_count != 0)
520 return tim->bitmap_ctrl & 0x01;
529 static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb)
531 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
533 if (skb->len < 24 + 8 + 2 + 2)
536 sc->ps_flags &= ~PS_WAIT_FOR_BEACON;
538 if (sc->ps_flags & PS_BEACON_SYNC) {
539 sc->ps_flags &= ~PS_BEACON_SYNC;
541 "Reconfigure beacon timers based on synchronized timestamp\n");
542 ath9k_set_beacon(sc);
545 if (ath_beacon_dtim_pending_cab(skb)) {
547 * Remain awake waiting for buffered broadcast/multicast
548 * frames. If the last broadcast/multicast frame is not
549 * received properly, the next beacon frame will work as
550 * a backup trigger for returning into NETWORK SLEEP state,
551 * so we are waiting for it as well.
554 "Received DTIM beacon indicating buffered broadcast/multicast frame(s)\n");
555 sc->ps_flags |= PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON;
559 if (sc->ps_flags & PS_WAIT_FOR_CAB) {
561 * This can happen if a broadcast frame is dropped or the AP
562 * fails to send a frame indicating that all CAB frames have
565 sc->ps_flags &= ~PS_WAIT_FOR_CAB;
566 ath_dbg(common, PS, "PS wait for CAB frames timed out\n");
570 static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb, bool mybeacon)
572 struct ieee80211_hdr *hdr;
573 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
575 hdr = (struct ieee80211_hdr *)skb->data;
577 /* Process Beacon and CAB receive in PS state */
578 if (((sc->ps_flags & PS_WAIT_FOR_BEACON) || ath9k_check_auto_sleep(sc))
580 ath_rx_ps_beacon(sc, skb);
581 } else if ((sc->ps_flags & PS_WAIT_FOR_CAB) &&
582 (ieee80211_is_data(hdr->frame_control) ||
583 ieee80211_is_action(hdr->frame_control)) &&
584 is_multicast_ether_addr(hdr->addr1) &&
585 !ieee80211_has_moredata(hdr->frame_control)) {
587 * No more broadcast/multicast frames to be received at this
590 sc->ps_flags &= ~(PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON);
592 "All PS CAB frames received, back to sleep\n");
593 } else if ((sc->ps_flags & PS_WAIT_FOR_PSPOLL_DATA) &&
594 !is_multicast_ether_addr(hdr->addr1) &&
595 !ieee80211_has_morefrags(hdr->frame_control)) {
596 sc->ps_flags &= ~PS_WAIT_FOR_PSPOLL_DATA;
598 "Going back to sleep after having received PS-Poll data (0x%lx)\n",
599 sc->ps_flags & (PS_WAIT_FOR_BEACON |
601 PS_WAIT_FOR_PSPOLL_DATA |
602 PS_WAIT_FOR_TX_ACK));
606 static bool ath_edma_get_buffers(struct ath_softc *sc,
607 enum ath9k_rx_qtype qtype,
608 struct ath_rx_status *rs,
609 struct ath_rxbuf **dest)
611 struct ath_rx_edma *rx_edma = &sc->rx.rx_edma[qtype];
612 struct ath_hw *ah = sc->sc_ah;
613 struct ath_common *common = ath9k_hw_common(ah);
615 struct ath_rxbuf *bf;
618 skb = skb_peek(&rx_edma->rx_fifo);
622 bf = SKB_CB_ATHBUF(skb);
625 dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr,
626 common->rx_bufsize, DMA_FROM_DEVICE);
628 ret = ath9k_hw_process_rxdesc_edma(ah, rs, skb->data);
629 if (ret == -EINPROGRESS) {
630 /*let device gain the buffer again*/
631 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
632 common->rx_bufsize, DMA_FROM_DEVICE);
636 __skb_unlink(skb, &rx_edma->rx_fifo);
637 if (ret == -EINVAL) {
638 /* corrupt descriptor, skip this one and the following one */
639 list_add_tail(&bf->list, &sc->rx.rxbuf);
640 ath_rx_edma_buf_link(sc, qtype);
642 skb = skb_peek(&rx_edma->rx_fifo);
644 bf = SKB_CB_ATHBUF(skb);
647 __skb_unlink(skb, &rx_edma->rx_fifo);
648 list_add_tail(&bf->list, &sc->rx.rxbuf);
649 ath_rx_edma_buf_link(sc, qtype);
659 static struct ath_rxbuf *ath_edma_get_next_rx_buf(struct ath_softc *sc,
660 struct ath_rx_status *rs,
661 enum ath9k_rx_qtype qtype)
663 struct ath_rxbuf *bf = NULL;
665 while (ath_edma_get_buffers(sc, qtype, rs, &bf)) {
674 static struct ath_rxbuf *ath_get_next_rx_buf(struct ath_softc *sc,
675 struct ath_rx_status *rs)
677 struct ath_hw *ah = sc->sc_ah;
678 struct ath_common *common = ath9k_hw_common(ah);
680 struct ath_rxbuf *bf;
683 if (list_empty(&sc->rx.rxbuf)) {
684 sc->rx.rxlink = NULL;
688 bf = list_first_entry(&sc->rx.rxbuf, struct ath_rxbuf, list);
689 if (bf == sc->rx.buf_hold)
695 * Must provide the virtual address of the current
696 * descriptor, the physical address, and the virtual
697 * address of the next descriptor in the h/w chain.
698 * This allows the HAL to look ahead to see if the
699 * hardware is done with a descriptor by checking the
700 * done bit in the following descriptor and the address
701 * of the current descriptor the DMA engine is working
702 * on. All this is necessary because of our use of
703 * a self-linked list to avoid rx overruns.
705 ret = ath9k_hw_rxprocdesc(ah, ds, rs);
706 if (ret == -EINPROGRESS) {
707 struct ath_rx_status trs;
708 struct ath_rxbuf *tbf;
709 struct ath_desc *tds;
711 memset(&trs, 0, sizeof(trs));
712 if (list_is_last(&bf->list, &sc->rx.rxbuf)) {
713 sc->rx.rxlink = NULL;
717 tbf = list_entry(bf->list.next, struct ath_rxbuf, list);
720 * On some hardware the descriptor status words could
721 * get corrupted, including the done bit. Because of
722 * this, check if the next descriptor's done bit is
725 * If the next descriptor's done bit is set, the current
726 * descriptor has been corrupted. Force s/w to discard
727 * this descriptor and continue...
731 ret = ath9k_hw_rxprocdesc(ah, tds, &trs);
732 if (ret == -EINPROGRESS)
736 * mark descriptor as zero-length and set the 'more'
737 * flag to ensure that both buffers get discarded
748 * Synchronize the DMA transfer with CPU before
749 * 1. accessing the frame
750 * 2. requeueing the same buffer to h/w
752 dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr,
759 /* Assumes you've already done the endian to CPU conversion */
760 static bool ath9k_rx_accept(struct ath_common *common,
761 struct ieee80211_hdr *hdr,
762 struct ieee80211_rx_status *rxs,
763 struct ath_rx_status *rx_stats,
766 struct ath_softc *sc = (struct ath_softc *) common->priv;
767 bool is_mc, is_valid_tkip, strip_mic, mic_error;
768 struct ath_hw *ah = common->ah;
771 fc = hdr->frame_control;
773 is_mc = !!is_multicast_ether_addr(hdr->addr1);
774 is_valid_tkip = rx_stats->rs_keyix != ATH9K_RXKEYIX_INVALID &&
775 test_bit(rx_stats->rs_keyix, common->tkip_keymap);
776 strip_mic = is_valid_tkip && ieee80211_is_data(fc) &&
777 ieee80211_has_protected(fc) &&
778 !(rx_stats->rs_status &
779 (ATH9K_RXERR_DECRYPT | ATH9K_RXERR_CRC | ATH9K_RXERR_MIC |
780 ATH9K_RXERR_KEYMISS));
783 * Key miss events are only relevant for pairwise keys where the
784 * descriptor does contain a valid key index. This has been observed
785 * mostly with CCMP encryption.
787 if (rx_stats->rs_keyix == ATH9K_RXKEYIX_INVALID ||
788 !test_bit(rx_stats->rs_keyix, common->ccmp_keymap))
789 rx_stats->rs_status &= ~ATH9K_RXERR_KEYMISS;
791 mic_error = is_valid_tkip && !ieee80211_is_ctl(fc) &&
792 !ieee80211_has_morefrags(fc) &&
793 !(le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG) &&
794 (rx_stats->rs_status & ATH9K_RXERR_MIC);
797 * The rx_stats->rs_status will not be set until the end of the
798 * chained descriptors so it can be ignored if rs_more is set. The
799 * rs_more will be false at the last element of the chained
802 if (rx_stats->rs_status != 0) {
805 if (rx_stats->rs_status & ATH9K_RXERR_CRC) {
806 rxs->flag |= RX_FLAG_FAILED_FCS_CRC;
810 if ((rx_stats->rs_status & ATH9K_RXERR_DECRYPT) ||
811 (!is_mc && (rx_stats->rs_status & ATH9K_RXERR_KEYMISS))) {
812 *decrypt_error = true;
817 * Reject error frames with the exception of
818 * decryption and MIC failures. For monitor mode,
819 * we also ignore the CRC error.
821 status_mask = ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC |
824 if (ah->is_monitoring && (sc->rx.rxfilter & FIF_FCSFAIL))
825 status_mask |= ATH9K_RXERR_CRC;
827 if (rx_stats->rs_status & ~status_mask)
832 * For unicast frames the MIC error bit can have false positives,
833 * so all MIC error reports need to be validated in software.
834 * False negatives are not common, so skip software verification
835 * if the hardware considers the MIC valid.
838 rxs->flag |= RX_FLAG_MMIC_STRIPPED;
839 else if (is_mc && mic_error)
840 rxs->flag |= RX_FLAG_MMIC_ERROR;
845 static int ath9k_process_rate(struct ath_common *common,
846 struct ieee80211_hw *hw,
847 struct ath_rx_status *rx_stats,
848 struct ieee80211_rx_status *rxs)
850 struct ieee80211_supported_band *sband;
851 enum ieee80211_band band;
853 struct ath_softc __maybe_unused *sc = common->priv;
855 band = hw->conf.chandef.chan->band;
856 sband = hw->wiphy->bands[band];
858 switch (hw->conf.chandef.width) {
859 case NL80211_CHAN_WIDTH_5:
860 rxs->flag |= RX_FLAG_5MHZ;
862 case NL80211_CHAN_WIDTH_10:
863 rxs->flag |= RX_FLAG_10MHZ;
869 if (rx_stats->rs_rate & 0x80) {
871 rxs->flag |= RX_FLAG_HT;
872 rxs->flag |= rx_stats->flag;
873 rxs->rate_idx = rx_stats->rs_rate & 0x7f;
877 for (i = 0; i < sband->n_bitrates; i++) {
878 if (sband->bitrates[i].hw_value == rx_stats->rs_rate) {
882 if (sband->bitrates[i].hw_value_short == rx_stats->rs_rate) {
883 rxs->flag |= RX_FLAG_SHORTPRE;
890 * No valid hardware bitrate found -- we should not get here
891 * because hardware has already validated this frame as OK.
894 "unsupported hw bitrate detected 0x%02x using 1 Mbit\n",
896 RX_STAT_INC(rx_rate_err);
900 static void ath9k_process_rssi(struct ath_common *common,
901 struct ieee80211_hw *hw,
902 struct ath_rx_status *rx_stats,
903 struct ieee80211_rx_status *rxs)
905 struct ath_softc *sc = hw->priv;
906 struct ath_hw *ah = common->ah;
908 int rssi = rx_stats->rs_rssi;
911 * RSSI is not available for subframes in an A-MPDU.
913 if (rx_stats->rs_moreaggr) {
914 rxs->flag |= RX_FLAG_NO_SIGNAL_VAL;
919 * Check if the RSSI for the last subframe in an A-MPDU
920 * or an unaggregated frame is valid.
922 if (rx_stats->rs_rssi == ATH9K_RSSI_BAD) {
923 rxs->flag |= RX_FLAG_NO_SIGNAL_VAL;
928 * Update Beacon RSSI, this is used by ANI.
930 if (rx_stats->is_mybeacon &&
931 ((ah->opmode == NL80211_IFTYPE_STATION) ||
932 (ah->opmode == NL80211_IFTYPE_ADHOC))) {
933 ATH_RSSI_LPF(sc->last_rssi, rx_stats->rs_rssi);
934 last_rssi = sc->last_rssi;
936 if (likely(last_rssi != ATH_RSSI_DUMMY_MARKER))
937 rssi = ATH_EP_RND(last_rssi, ATH_RSSI_EP_MULTIPLIER);
941 ah->stats.avgbrssi = rssi;
944 rxs->signal = ah->noise + rx_stats->rs_rssi;
947 static void ath9k_process_tsf(struct ath_rx_status *rs,
948 struct ieee80211_rx_status *rxs,
951 u32 tsf_lower = tsf & 0xffffffff;
953 rxs->mactime = (tsf & ~0xffffffffULL) | rs->rs_tstamp;
954 if (rs->rs_tstamp > tsf_lower &&
955 unlikely(rs->rs_tstamp - tsf_lower > 0x10000000))
956 rxs->mactime -= 0x100000000ULL;
958 if (rs->rs_tstamp < tsf_lower &&
959 unlikely(tsf_lower - rs->rs_tstamp > 0x10000000))
960 rxs->mactime += 0x100000000ULL;
963 #ifdef CONFIG_ATH9K_DEBUGFS
964 static s8 fix_rssi_inv_only(u8 rssi_val)
968 return (s8) rssi_val;
972 /* returns 1 if this was a spectral frame, even if not handled. */
973 static int ath_process_fft(struct ath_softc *sc, struct ieee80211_hdr *hdr,
974 struct ath_rx_status *rs, u64 tsf)
976 #ifdef CONFIG_ATH9K_DEBUGFS
977 struct ath_hw *ah = sc->sc_ah;
978 u8 num_bins, *bins, *vdata = (u8 *)hdr;
979 struct fft_sample_ht20 fft_sample_20;
980 struct fft_sample_ht20_40 fft_sample_40;
981 struct fft_sample_tlv *tlv;
982 struct ath_radar_info *radar_info;
983 int len = rs->rs_datalen;
985 u16 fft_len, length, freq = ah->curchan->chan->center_freq;
986 enum nl80211_channel_type chan_type;
988 /* AR9280 and before report via ATH9K_PHYERR_RADAR, AR93xx and newer
989 * via ATH9K_PHYERR_SPECTRAL. Haven't seen ATH9K_PHYERR_FALSE_RADAR_EXT
990 * yet, but this is supposed to be possible as well.
992 if (rs->rs_phyerr != ATH9K_PHYERR_RADAR &&
993 rs->rs_phyerr != ATH9K_PHYERR_FALSE_RADAR_EXT &&
994 rs->rs_phyerr != ATH9K_PHYERR_SPECTRAL)
997 /* check if spectral scan bit is set. This does not have to be checked
998 * if received through a SPECTRAL phy error, but shouldn't hurt.
1000 radar_info = ((struct ath_radar_info *)&vdata[len]) - 1;
1001 if (!(radar_info->pulse_bw_info & SPECTRAL_SCAN_BITMASK))
1004 chan_type = cfg80211_get_chandef_type(&sc->hw->conf.chandef);
1005 if ((chan_type == NL80211_CHAN_HT40MINUS) ||
1006 (chan_type == NL80211_CHAN_HT40PLUS)) {
1007 fft_len = SPECTRAL_HT20_40_TOTAL_DATA_LEN;
1008 num_bins = SPECTRAL_HT20_40_NUM_BINS;
1009 bins = (u8 *)fft_sample_40.data;
1011 fft_len = SPECTRAL_HT20_TOTAL_DATA_LEN;
1012 num_bins = SPECTRAL_HT20_NUM_BINS;
1013 bins = (u8 *)fft_sample_20.data;
1016 /* Variation in the data length is possible and will be fixed later */
1017 if ((len > fft_len + 2) || (len < fft_len - 1))
1020 switch (len - fft_len) {
1022 /* length correct, nothing to do. */
1023 memcpy(bins, vdata, num_bins);
1026 /* first byte missing, duplicate it. */
1027 memcpy(&bins[1], vdata, num_bins - 1);
1031 /* MAC added 2 extra bytes at bin 30 and 32, remove them. */
1032 memcpy(bins, vdata, 30);
1033 bins[30] = vdata[31];
1034 memcpy(&bins[31], &vdata[33], num_bins - 31);
1037 /* MAC added 2 extra bytes AND first byte is missing. */
1039 memcpy(&bins[1], vdata, 30);
1040 bins[31] = vdata[31];
1041 memcpy(&bins[32], &vdata[33], num_bins - 32);
1047 /* DC value (value in the middle) is the blind spot of the spectral
1048 * sample and invalid, interpolate it.
1050 dc_pos = num_bins / 2;
1051 bins[dc_pos] = (bins[dc_pos + 1] + bins[dc_pos - 1]) / 2;
1053 if ((chan_type == NL80211_CHAN_HT40MINUS) ||
1054 (chan_type == NL80211_CHAN_HT40PLUS)) {
1055 s8 lower_rssi, upper_rssi;
1057 u8 lower_max_index, upper_max_index;
1058 u8 lower_bitmap_w, upper_bitmap_w;
1059 u16 lower_mag, upper_mag;
1060 struct ath9k_hw_cal_data *caldata = ah->caldata;
1061 struct ath_ht20_40_mag_info *mag_info;
1064 ext_nf = ath9k_hw_getchan_noise(ah, ah->curchan,
1065 caldata->nfCalHist[3].privNF);
1067 ext_nf = ATH_DEFAULT_NOISE_FLOOR;
1069 length = sizeof(fft_sample_40) - sizeof(struct fft_sample_tlv);
1070 fft_sample_40.tlv.type = ATH_FFT_SAMPLE_HT20_40;
1071 fft_sample_40.tlv.length = __cpu_to_be16(length);
1072 fft_sample_40.freq = __cpu_to_be16(freq);
1073 fft_sample_40.channel_type = chan_type;
1075 if (chan_type == NL80211_CHAN_HT40PLUS) {
1076 lower_rssi = fix_rssi_inv_only(rs->rs_rssi_ctl0);
1077 upper_rssi = fix_rssi_inv_only(rs->rs_rssi_ext0);
1079 fft_sample_40.lower_noise = ah->noise;
1080 fft_sample_40.upper_noise = ext_nf;
1082 lower_rssi = fix_rssi_inv_only(rs->rs_rssi_ext0);
1083 upper_rssi = fix_rssi_inv_only(rs->rs_rssi_ctl0);
1085 fft_sample_40.lower_noise = ext_nf;
1086 fft_sample_40.upper_noise = ah->noise;
1088 fft_sample_40.lower_rssi = lower_rssi;
1089 fft_sample_40.upper_rssi = upper_rssi;
1091 mag_info = ((struct ath_ht20_40_mag_info *)radar_info) - 1;
1092 lower_mag = spectral_max_magnitude(mag_info->lower_bins);
1093 upper_mag = spectral_max_magnitude(mag_info->upper_bins);
1094 fft_sample_40.lower_max_magnitude = __cpu_to_be16(lower_mag);
1095 fft_sample_40.upper_max_magnitude = __cpu_to_be16(upper_mag);
1096 lower_max_index = spectral_max_index(mag_info->lower_bins);
1097 upper_max_index = spectral_max_index(mag_info->upper_bins);
1098 fft_sample_40.lower_max_index = lower_max_index;
1099 fft_sample_40.upper_max_index = upper_max_index;
1100 lower_bitmap_w = spectral_bitmap_weight(mag_info->lower_bins);
1101 upper_bitmap_w = spectral_bitmap_weight(mag_info->upper_bins);
1102 fft_sample_40.lower_bitmap_weight = lower_bitmap_w;
1103 fft_sample_40.upper_bitmap_weight = upper_bitmap_w;
1104 fft_sample_40.max_exp = mag_info->max_exp & 0xf;
1106 fft_sample_40.tsf = __cpu_to_be64(tsf);
1108 tlv = (struct fft_sample_tlv *)&fft_sample_40;
1110 u8 max_index, bitmap_w;
1112 struct ath_ht20_mag_info *mag_info;
1114 length = sizeof(fft_sample_20) - sizeof(struct fft_sample_tlv);
1115 fft_sample_20.tlv.type = ATH_FFT_SAMPLE_HT20;
1116 fft_sample_20.tlv.length = __cpu_to_be16(length);
1117 fft_sample_20.freq = __cpu_to_be16(freq);
1119 fft_sample_20.rssi = fix_rssi_inv_only(rs->rs_rssi_ctl0);
1120 fft_sample_20.noise = ah->noise;
1122 mag_info = ((struct ath_ht20_mag_info *)radar_info) - 1;
1123 magnitude = spectral_max_magnitude(mag_info->all_bins);
1124 fft_sample_20.max_magnitude = __cpu_to_be16(magnitude);
1125 max_index = spectral_max_index(mag_info->all_bins);
1126 fft_sample_20.max_index = max_index;
1127 bitmap_w = spectral_bitmap_weight(mag_info->all_bins);
1128 fft_sample_20.bitmap_weight = bitmap_w;
1129 fft_sample_20.max_exp = mag_info->max_exp & 0xf;
1131 fft_sample_20.tsf = __cpu_to_be64(tsf);
1133 tlv = (struct fft_sample_tlv *)&fft_sample_20;
1136 ath_debug_send_fft_sample(sc, tlv);
1143 static bool ath9k_is_mybeacon(struct ath_softc *sc, struct ieee80211_hdr *hdr)
1145 struct ath_hw *ah = sc->sc_ah;
1146 struct ath_common *common = ath9k_hw_common(ah);
1148 if (ieee80211_is_beacon(hdr->frame_control)) {
1149 RX_STAT_INC(rx_beacons);
1150 if (!is_zero_ether_addr(common->curbssid) &&
1151 ether_addr_equal(hdr->addr3, common->curbssid))
1159 * For Decrypt or Demic errors, we only mark packet status here and always push
1160 * up the frame up to let mac80211 handle the actual error case, be it no
1161 * decryption key or real decryption error. This let us keep statistics there.
1163 static int ath9k_rx_skb_preprocess(struct ath_softc *sc,
1164 struct sk_buff *skb,
1165 struct ath_rx_status *rx_stats,
1166 struct ieee80211_rx_status *rx_status,
1167 bool *decrypt_error, u64 tsf)
1169 struct ieee80211_hw *hw = sc->hw;
1170 struct ath_hw *ah = sc->sc_ah;
1171 struct ath_common *common = ath9k_hw_common(ah);
1172 struct ieee80211_hdr *hdr;
1173 bool discard_current = sc->rx.discard_next;
1177 * Discard corrupt descriptors which are marked in
1178 * ath_get_next_rx_buf().
1180 sc->rx.discard_next = rx_stats->rs_more;
1181 if (discard_current)
1185 * Discard zero-length packets.
1187 if (!rx_stats->rs_datalen) {
1188 RX_STAT_INC(rx_len_err);
1193 * rs_status follows rs_datalen so if rs_datalen is too large
1194 * we can take a hint that hardware corrupted it, so ignore
1197 if (rx_stats->rs_datalen > (common->rx_bufsize - ah->caps.rx_status_len)) {
1198 RX_STAT_INC(rx_len_err);
1202 /* Only use status info from the last fragment */
1203 if (rx_stats->rs_more)
1207 * Return immediately if the RX descriptor has been marked
1208 * as corrupt based on the various error bits.
1210 * This is different from the other corrupt descriptor
1211 * condition handled above.
1213 if (rx_stats->rs_status & ATH9K_RXERR_CORRUPT_DESC) {
1218 hdr = (struct ieee80211_hdr *) (skb->data + ah->caps.rx_status_len);
1220 ath9k_process_tsf(rx_stats, rx_status, tsf);
1221 ath_debug_stat_rx(sc, rx_stats);
1224 * Process PHY errors and return so that the packet
1227 if (rx_stats->rs_status & ATH9K_RXERR_PHY) {
1228 ath9k_dfs_process_phyerr(sc, hdr, rx_stats, rx_status->mactime);
1229 if (ath_process_fft(sc, hdr, rx_stats, rx_status->mactime))
1230 RX_STAT_INC(rx_spectral);
1237 * everything but the rate is checked here, the rate check is done
1238 * separately to avoid doing two lookups for a rate for each frame.
1240 if (!ath9k_rx_accept(common, hdr, rx_status, rx_stats, decrypt_error)) {
1245 rx_stats->is_mybeacon = ath9k_is_mybeacon(sc, hdr);
1246 if (rx_stats->is_mybeacon) {
1247 sc->hw_busy_count = 0;
1248 ath_start_rx_poll(sc, 3);
1251 if (ath9k_process_rate(common, hw, rx_stats, rx_status)) {
1256 ath9k_process_rssi(common, hw, rx_stats, rx_status);
1258 rx_status->band = hw->conf.chandef.chan->band;
1259 rx_status->freq = hw->conf.chandef.chan->center_freq;
1260 rx_status->antenna = rx_stats->rs_antenna;
1261 rx_status->flag |= RX_FLAG_MACTIME_END;
1263 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
1264 if (ieee80211_is_data_present(hdr->frame_control) &&
1265 !ieee80211_is_qos_nullfunc(hdr->frame_control))
1270 sc->rx.discard_next = false;
1274 static void ath9k_rx_skb_postprocess(struct ath_common *common,
1275 struct sk_buff *skb,
1276 struct ath_rx_status *rx_stats,
1277 struct ieee80211_rx_status *rxs,
1280 struct ath_hw *ah = common->ah;
1281 struct ieee80211_hdr *hdr;
1282 int hdrlen, padpos, padsize;
1286 /* see if any padding is done by the hw and remove it */
1287 hdr = (struct ieee80211_hdr *) skb->data;
1288 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1289 fc = hdr->frame_control;
1290 padpos = ieee80211_hdrlen(fc);
1292 /* The MAC header is padded to have 32-bit boundary if the
1293 * packet payload is non-zero. The general calculation for
1294 * padsize would take into account odd header lengths:
1295 * padsize = (4 - padpos % 4) % 4; However, since only
1296 * even-length headers are used, padding can only be 0 or 2
1297 * bytes and we can optimize this a bit. In addition, we must
1298 * not try to remove padding from short control frames that do
1299 * not have payload. */
1300 padsize = padpos & 3;
1301 if (padsize && skb->len>=padpos+padsize+FCS_LEN) {
1302 memmove(skb->data + padsize, skb->data, padpos);
1303 skb_pull(skb, padsize);
1306 keyix = rx_stats->rs_keyix;
1308 if (!(keyix == ATH9K_RXKEYIX_INVALID) && !decrypt_error &&
1309 ieee80211_has_protected(fc)) {
1310 rxs->flag |= RX_FLAG_DECRYPTED;
1311 } else if (ieee80211_has_protected(fc)
1312 && !decrypt_error && skb->len >= hdrlen + 4) {
1313 keyix = skb->data[hdrlen + 3] >> 6;
1315 if (test_bit(keyix, common->keymap))
1316 rxs->flag |= RX_FLAG_DECRYPTED;
1318 if (ah->sw_mgmt_crypto &&
1319 (rxs->flag & RX_FLAG_DECRYPTED) &&
1320 ieee80211_is_mgmt(fc))
1321 /* Use software decrypt for management frames. */
1322 rxs->flag &= ~RX_FLAG_DECRYPTED;
1326 * Run the LNA combining algorithm only in these cases:
1328 * Standalone WLAN cards with both LNA/Antenna diversity
1329 * enabled in the EEPROM.
1331 * WLAN+BT cards which are in the supported card list
1332 * in ath_pci_id_table and the user has loaded the
1333 * driver with "bt_ant_diversity" set to true.
1335 static void ath9k_antenna_check(struct ath_softc *sc,
1336 struct ath_rx_status *rs)
1338 struct ath_hw *ah = sc->sc_ah;
1339 struct ath9k_hw_capabilities *pCap = &ah->caps;
1340 struct ath_common *common = ath9k_hw_common(ah);
1342 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB))
1346 * Change the default rx antenna if rx diversity
1347 * chooses the other antenna 3 times in a row.
1349 if (sc->rx.defant != rs->rs_antenna) {
1350 if (++sc->rx.rxotherant >= 3)
1351 ath_setdefantenna(sc, rs->rs_antenna);
1353 sc->rx.rxotherant = 0;
1356 if (pCap->hw_caps & ATH9K_HW_CAP_BT_ANT_DIV) {
1357 if (common->bt_ant_diversity)
1358 ath_ant_comb_scan(sc, rs);
1360 ath_ant_comb_scan(sc, rs);
1364 static void ath9k_apply_ampdu_details(struct ath_softc *sc,
1365 struct ath_rx_status *rs, struct ieee80211_rx_status *rxs)
1367 if (rs->rs_isaggr) {
1368 rxs->flag |= RX_FLAG_AMPDU_DETAILS | RX_FLAG_AMPDU_LAST_KNOWN;
1370 rxs->ampdu_reference = sc->rx.ampdu_ref;
1372 if (!rs->rs_moreaggr) {
1373 rxs->flag |= RX_FLAG_AMPDU_IS_LAST;
1377 if (rs->rs_flags & ATH9K_RX_DELIM_CRC_PRE)
1378 rxs->flag |= RX_FLAG_AMPDU_DELIM_CRC_ERROR;
1382 int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp)
1384 struct ath_rxbuf *bf;
1385 struct sk_buff *skb = NULL, *requeue_skb, *hdr_skb;
1386 struct ieee80211_rx_status *rxs;
1387 struct ath_hw *ah = sc->sc_ah;
1388 struct ath_common *common = ath9k_hw_common(ah);
1389 struct ieee80211_hw *hw = sc->hw;
1391 struct ath_rx_status rs;
1392 enum ath9k_rx_qtype qtype;
1393 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1396 unsigned long flags;
1397 dma_addr_t new_buf_addr;
1400 dma_type = DMA_BIDIRECTIONAL;
1402 dma_type = DMA_FROM_DEVICE;
1404 qtype = hp ? ATH9K_RX_QUEUE_HP : ATH9K_RX_QUEUE_LP;
1406 tsf = ath9k_hw_gettsf64(ah);
1409 bool decrypt_error = false;
1411 memset(&rs, 0, sizeof(rs));
1413 bf = ath_edma_get_next_rx_buf(sc, &rs, qtype);
1415 bf = ath_get_next_rx_buf(sc, &rs);
1425 * Take frame header from the first fragment and RX status from
1429 hdr_skb = sc->rx.frag;
1433 rxs = IEEE80211_SKB_RXCB(hdr_skb);
1434 memset(rxs, 0, sizeof(struct ieee80211_rx_status));
1436 retval = ath9k_rx_skb_preprocess(sc, hdr_skb, &rs, rxs,
1437 &decrypt_error, tsf);
1439 goto requeue_drop_frag;
1441 /* Ensure we always have an skb to requeue once we are done
1442 * processing the current buffer's skb */
1443 requeue_skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_ATOMIC);
1445 /* If there is no memory we ignore the current RX'd frame,
1446 * tell hardware it can give us a new frame using the old
1447 * skb and put it at the tail of the sc->rx.rxbuf list for
1450 RX_STAT_INC(rx_oom_err);
1451 goto requeue_drop_frag;
1454 /* We will now give hardware our shiny new allocated skb */
1455 new_buf_addr = dma_map_single(sc->dev, requeue_skb->data,
1456 common->rx_bufsize, dma_type);
1457 if (unlikely(dma_mapping_error(sc->dev, new_buf_addr))) {
1458 dev_kfree_skb_any(requeue_skb);
1459 goto requeue_drop_frag;
1462 /* Unmap the frame */
1463 dma_unmap_single(sc->dev, bf->bf_buf_addr,
1464 common->rx_bufsize, dma_type);
1466 bf->bf_mpdu = requeue_skb;
1467 bf->bf_buf_addr = new_buf_addr;
1469 skb_put(skb, rs.rs_datalen + ah->caps.rx_status_len);
1470 if (ah->caps.rx_status_len)
1471 skb_pull(skb, ah->caps.rx_status_len);
1474 ath9k_rx_skb_postprocess(common, hdr_skb, &rs,
1475 rxs, decrypt_error);
1478 RX_STAT_INC(rx_frags);
1480 * rs_more indicates chained descriptors which can be
1481 * used to link buffers together for a sort of
1482 * scatter-gather operation.
1485 /* too many fragments - cannot handle frame */
1486 dev_kfree_skb_any(sc->rx.frag);
1487 dev_kfree_skb_any(skb);
1488 RX_STAT_INC(rx_too_many_frags_err);
1496 int space = skb->len - skb_tailroom(hdr_skb);
1498 if (pskb_expand_head(hdr_skb, 0, space, GFP_ATOMIC) < 0) {
1500 RX_STAT_INC(rx_oom_err);
1501 goto requeue_drop_frag;
1506 skb_copy_from_linear_data(skb, skb_put(hdr_skb, skb->len),
1508 dev_kfree_skb_any(skb);
1512 if (rxs->flag & RX_FLAG_MMIC_STRIPPED)
1513 skb_trim(skb, skb->len - 8);
1515 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1516 if ((sc->ps_flags & (PS_WAIT_FOR_BEACON |
1518 PS_WAIT_FOR_PSPOLL_DATA)) ||
1519 ath9k_check_auto_sleep(sc))
1520 ath_rx_ps(sc, skb, rs.is_mybeacon);
1521 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1523 ath9k_antenna_check(sc, &rs);
1525 ath9k_apply_ampdu_details(sc, &rs, rxs);
1527 ieee80211_rx(hw, skb);
1531 dev_kfree_skb_any(sc->rx.frag);
1535 list_add_tail(&bf->list, &sc->rx.rxbuf);
1540 ath_rx_edma_buf_link(sc, qtype);
1542 ath_rx_buf_relink(sc, bf);
1547 if (!(ah->imask & ATH9K_INT_RXEOL)) {
1548 ah->imask |= (ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
1549 ath9k_hw_set_interrupts(ah);