2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/nl80211.h>
18 #include <linux/pci.h>
21 static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = {
22 { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */
23 { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
24 { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */
25 { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */
26 { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
27 { PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */
28 { PCI_VDEVICE(ATHEROS, 0x002C) }, /* PCI-E 802.11n bonded out */
29 { PCI_VDEVICE(ATHEROS, 0x002D) }, /* PCI */
30 { PCI_VDEVICE(ATHEROS, 0x002E) }, /* PCI-E */
34 /* return bus cachesize in 4B word units */
35 static void ath_pci_read_cachesize(struct ath_common *common, int *csz)
37 struct ath_softc *sc = (struct ath_softc *) common->priv;
40 pci_read_config_byte(to_pci_dev(sc->dev), PCI_CACHE_LINE_SIZE, &u8tmp);
44 * This check was put in to avoid "unplesant" consequences if
45 * the bootrom has not fully initialized all PCI devices.
46 * Sometimes the cache line size register is not set
50 *csz = DEFAULT_CACHELINE >> 2; /* Use the default size */
53 static bool ath_pci_eeprom_read(struct ath_common *common, u32 off, u16 *data)
55 struct ath_hw *ah = (struct ath_hw *) common->ah;
57 common->ops->read(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S));
59 if (!ath9k_hw_wait(ah,
60 AR_EEPROM_STATUS_DATA,
61 AR_EEPROM_STATUS_DATA_BUSY |
62 AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0,
67 *data = MS(common->ops->read(ah, AR_EEPROM_STATUS_DATA),
68 AR_EEPROM_STATUS_DATA_VAL);
74 * Bluetooth coexistance requires disabling ASPM.
76 static void ath_pci_bt_coex_prep(struct ath_common *common)
78 struct ath_softc *sc = (struct ath_softc *) common->priv;
79 struct pci_dev *pdev = to_pci_dev(sc->dev);
85 pci_read_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, &aspm);
86 aspm &= ~(ATH_PCIE_CAP_LINK_L0S | ATH_PCIE_CAP_LINK_L1);
87 pci_write_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, aspm);
90 static const struct ath_bus_ops ath_pci_bus_ops = {
91 .read_cachesize = ath_pci_read_cachesize,
92 .eeprom_read = ath_pci_eeprom_read,
93 .bt_coex_prep = ath_pci_bt_coex_prep,
96 static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
99 struct ath_wiphy *aphy;
100 struct ath_softc *sc;
101 struct ieee80211_hw *hw;
108 if (pci_enable_device(pdev))
111 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
113 printk(KERN_ERR "ath9k: 32-bit DMA not available\n");
117 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
119 printk(KERN_ERR "ath9k: 32-bit DMA consistent "
120 "DMA enable failed\n");
125 * Cache line size is used to size and align various
126 * structures used to communicate with the hardware.
128 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
131 * Linux 2.4.18 (at least) writes the cache line size
132 * register as a 16-bit wide register which is wrong.
133 * We must have this setup properly for rx buffer
134 * DMA to work so force a reasonable value here if it
137 csz = L1_CACHE_BYTES / sizeof(u32);
138 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
141 * The default setting of latency timer yields poor results,
142 * set it to the value used by other systems. It may be worth
143 * tweaking this setting more.
145 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
147 pci_set_master(pdev);
150 * Disable the RETRY_TIMEOUT register (0x41) to keep
151 * PCI Tx retries from interfering with C3 CPU state.
153 pci_read_config_dword(pdev, 0x40, &val);
154 if ((val & 0x0000ff00) != 0)
155 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
157 ret = pci_request_region(pdev, 0, "ath9k");
159 dev_err(&pdev->dev, "PCI memory region reserve error\n");
164 mem = pci_iomap(pdev, 0, 0);
166 printk(KERN_ERR "PCI memory map error\n") ;
171 hw = ieee80211_alloc_hw(sizeof(struct ath_wiphy) +
172 sizeof(struct ath_softc), &ath9k_ops);
174 dev_err(&pdev->dev, "No memory for ieee80211_hw\n");
179 SET_IEEE80211_DEV(hw, &pdev->dev);
180 pci_set_drvdata(pdev, hw);
183 sc = (struct ath_softc *) (aphy + 1);
186 sc->pri_wiphy = aphy;
188 sc->dev = &pdev->dev;
191 /* Will be cleared in ath9k_start() */
192 sc->sc_flags |= SC_OP_INVALID;
194 ret = request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath9k", sc);
196 dev_err(&pdev->dev, "request_irq failed\n");
202 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &subsysid);
203 ret = ath9k_init_device(id->device, sc, subsysid, &ath_pci_bus_ops);
205 dev_err(&pdev->dev, "Failed to initialize device\n");
209 ath9k_hw_name(sc->sc_ah, hw_name, sizeof(hw_name));
211 "%s: %s mem=0x%lx, irq=%d\n",
212 wiphy_name(hw->wiphy),
214 (unsigned long)mem, pdev->irq);
219 free_irq(sc->irq, sc);
221 ieee80211_free_hw(hw);
223 pci_iounmap(pdev, mem);
225 pci_release_region(pdev, 0);
229 pci_disable_device(pdev);
233 static void ath_pci_remove(struct pci_dev *pdev)
235 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
236 struct ath_wiphy *aphy = hw->priv;
237 struct ath_softc *sc = aphy->sc;
238 void __iomem *mem = sc->mem;
240 ath9k_deinit_device(sc);
241 free_irq(sc->irq, sc);
242 ieee80211_free_hw(sc->hw);
244 pci_iounmap(pdev, mem);
245 pci_disable_device(pdev);
246 pci_release_region(pdev, 0);
251 static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state)
253 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
254 struct ath_wiphy *aphy = hw->priv;
255 struct ath_softc *sc = aphy->sc;
257 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
259 pci_save_state(pdev);
260 pci_disable_device(pdev);
261 pci_set_power_state(pdev, PCI_D3hot);
266 static int ath_pci_resume(struct pci_dev *pdev)
268 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
269 struct ath_wiphy *aphy = hw->priv;
270 struct ath_softc *sc = aphy->sc;
274 pci_restore_state(pdev);
276 err = pci_enable_device(pdev);
281 * Suspend/Resume resets the PCI configuration space, so we have to
282 * re-disable the RETRY_TIMEOUT register (0x41) to keep
283 * PCI Tx retries from interfering with C3 CPU state
285 pci_read_config_dword(pdev, 0x40, &val);
286 if ((val & 0x0000ff00) != 0)
287 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
290 ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin,
291 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
292 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
297 #endif /* CONFIG_PM */
299 MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
301 static struct pci_driver ath_pci_driver = {
303 .id_table = ath_pci_id_table,
304 .probe = ath_pci_probe,
305 .remove = ath_pci_remove,
307 .suspend = ath_pci_suspend,
308 .resume = ath_pci_resume,
309 #endif /* CONFIG_PM */
312 int ath_pci_init(void)
314 return pci_register_driver(&ath_pci_driver);
317 void ath_pci_exit(void)
319 pci_unregister_driver(&ath_pci_driver);