2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19 #include <linux/dma-mapping.h>
20 #include <linux/slab.h>
21 #include <linux/ath9k_platform.h>
22 #include <linux/module.h>
23 #include <linux/relay.h>
24 #include <net/ieee80211_radiotap.h>
28 struct ath9k_eeprom_ctx {
29 struct completion complete;
33 static char *dev_info = "ath9k";
35 MODULE_AUTHOR("Atheros Communications");
36 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
37 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
38 MODULE_LICENSE("Dual BSD/GPL");
40 static unsigned int ath9k_debug = ATH_DBG_DEFAULT;
41 module_param_named(debug, ath9k_debug, uint, 0);
42 MODULE_PARM_DESC(debug, "Debugging mask");
44 int ath9k_modparam_nohwcrypt;
45 module_param_named(nohwcrypt, ath9k_modparam_nohwcrypt, int, 0444);
46 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
49 module_param_named(blink, led_blink, int, 0444);
50 MODULE_PARM_DESC(blink, "Enable LED blink on activity");
52 static int ath9k_btcoex_enable;
53 module_param_named(btcoex_enable, ath9k_btcoex_enable, int, 0444);
54 MODULE_PARM_DESC(btcoex_enable, "Enable wifi-BT coexistence");
56 static int ath9k_bt_ant_diversity;
57 module_param_named(bt_ant_diversity, ath9k_bt_ant_diversity, int, 0444);
58 MODULE_PARM_DESC(bt_ant_diversity, "Enable WLAN/BT RX antenna diversity");
60 static int ath9k_ps_enable;
61 module_param_named(ps_enable, ath9k_ps_enable, int, 0444);
62 MODULE_PARM_DESC(ps_enable, "Enable WLAN PowerSave");
64 bool is_ath9k_unloaded;
66 #ifdef CONFIG_MAC80211_LEDS
67 static const struct ieee80211_tpt_blink ath9k_tpt_blink[] = {
68 { .throughput = 0 * 1024, .blink_time = 334 },
69 { .throughput = 1 * 1024, .blink_time = 260 },
70 { .throughput = 5 * 1024, .blink_time = 220 },
71 { .throughput = 10 * 1024, .blink_time = 190 },
72 { .throughput = 20 * 1024, .blink_time = 170 },
73 { .throughput = 50 * 1024, .blink_time = 150 },
74 { .throughput = 70 * 1024, .blink_time = 130 },
75 { .throughput = 100 * 1024, .blink_time = 110 },
76 { .throughput = 200 * 1024, .blink_time = 80 },
77 { .throughput = 300 * 1024, .blink_time = 50 },
81 static void ath9k_deinit_softc(struct ath_softc *sc);
84 * Read and write, they both share the same lock. We do this to serialize
85 * reads and writes on Atheros 802.11n PCI devices only. This is required
86 * as the FIFO on these devices can only accept sanely 2 requests.
89 static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
91 struct ath_hw *ah = (struct ath_hw *) hw_priv;
92 struct ath_common *common = ath9k_hw_common(ah);
93 struct ath_softc *sc = (struct ath_softc *) common->priv;
95 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) {
97 spin_lock_irqsave(&sc->sc_serial_rw, flags);
98 iowrite32(val, sc->mem + reg_offset);
99 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
101 iowrite32(val, sc->mem + reg_offset);
104 static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset)
106 struct ath_hw *ah = (struct ath_hw *) hw_priv;
107 struct ath_common *common = ath9k_hw_common(ah);
108 struct ath_softc *sc = (struct ath_softc *) common->priv;
111 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) {
113 spin_lock_irqsave(&sc->sc_serial_rw, flags);
114 val = ioread32(sc->mem + reg_offset);
115 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
117 val = ioread32(sc->mem + reg_offset);
121 static unsigned int __ath9k_reg_rmw(struct ath_softc *sc, u32 reg_offset,
126 val = ioread32(sc->mem + reg_offset);
129 iowrite32(val, sc->mem + reg_offset);
134 static unsigned int ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr)
136 struct ath_hw *ah = (struct ath_hw *) hw_priv;
137 struct ath_common *common = ath9k_hw_common(ah);
138 struct ath_softc *sc = (struct ath_softc *) common->priv;
139 unsigned long uninitialized_var(flags);
142 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) {
143 spin_lock_irqsave(&sc->sc_serial_rw, flags);
144 val = __ath9k_reg_rmw(sc, reg_offset, set, clr);
145 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
147 val = __ath9k_reg_rmw(sc, reg_offset, set, clr);
152 /**************************/
154 /**************************/
156 static void ath9k_reg_notifier(struct wiphy *wiphy,
157 struct regulatory_request *request)
159 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
160 struct ath_softc *sc = hw->priv;
161 struct ath_hw *ah = sc->sc_ah;
162 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
164 ath_reg_notifier_apply(wiphy, request, reg);
168 sc->config.txpowlimit = 2 * ah->curchan->chan->max_power;
170 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit, false);
171 sc->curtxpow = ath9k_hw_regulatory(ah)->power_limit;
172 /* synchronize DFS detector if regulatory domain changed */
173 if (sc->dfs_detector != NULL)
174 sc->dfs_detector->set_dfs_domain(sc->dfs_detector,
175 request->dfs_region);
176 ath9k_ps_restore(sc);
181 * This function will allocate both the DMA descriptor structure, and the
182 * buffers it contains. These are used to contain the descriptors used
185 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
186 struct list_head *head, const char *name,
187 int nbuf, int ndesc, bool is_tx)
189 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
191 int i, bsize, desc_len;
193 ath_dbg(common, CONFIG, "%s DMA: %u buffers %u desc/buf\n",
196 INIT_LIST_HEAD(head);
199 desc_len = sc->sc_ah->caps.tx_desc_len;
201 desc_len = sizeof(struct ath_desc);
203 /* ath_desc must be a multiple of DWORDs */
204 if ((desc_len % 4) != 0) {
205 ath_err(common, "ath_desc not DWORD aligned\n");
206 BUG_ON((desc_len % 4) != 0);
210 dd->dd_desc_len = desc_len * nbuf * ndesc;
213 * Need additional DMA memory because we can't use
214 * descriptors that cross the 4K page boundary. Assume
215 * one skipped descriptor per 4K page.
217 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
219 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
222 while (ndesc_skipped) {
223 dma_len = ndesc_skipped * desc_len;
224 dd->dd_desc_len += dma_len;
226 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
230 /* allocate descriptors */
231 dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len,
232 &dd->dd_desc_paddr, GFP_KERNEL);
236 ds = (u8 *) dd->dd_desc;
237 ath_dbg(common, CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
238 name, ds, (u32) dd->dd_desc_len,
239 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
241 /* allocate buffers */
245 bsize = sizeof(struct ath_buf) * nbuf;
246 bf = devm_kzalloc(sc->dev, bsize, GFP_KERNEL);
250 for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) {
252 bf->bf_daddr = DS2PHYS(dd, ds);
254 if (!(sc->sc_ah->caps.hw_caps &
255 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
257 * Skip descriptor addresses which can cause 4KB
258 * boundary crossing (addr + length) with a 32 dword
261 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
262 BUG_ON((caddr_t) bf->bf_desc >=
263 ((caddr_t) dd->dd_desc +
266 ds += (desc_len * ndesc);
268 bf->bf_daddr = DS2PHYS(dd, ds);
271 list_add_tail(&bf->list, head);
274 struct ath_rxbuf *bf;
276 bsize = sizeof(struct ath_rxbuf) * nbuf;
277 bf = devm_kzalloc(sc->dev, bsize, GFP_KERNEL);
281 for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) {
283 bf->bf_daddr = DS2PHYS(dd, ds);
285 if (!(sc->sc_ah->caps.hw_caps &
286 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
288 * Skip descriptor addresses which can cause 4KB
289 * boundary crossing (addr + length) with a 32 dword
292 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
293 BUG_ON((caddr_t) bf->bf_desc >=
294 ((caddr_t) dd->dd_desc +
297 ds += (desc_len * ndesc);
299 bf->bf_daddr = DS2PHYS(dd, ds);
302 list_add_tail(&bf->list, head);
308 static int ath9k_init_queues(struct ath_softc *sc)
312 sc->beacon.beaconq = ath9k_hw_beaconq_setup(sc->sc_ah);
313 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
316 sc->tx.uapsdq = ath_txq_setup(sc, ATH9K_TX_QUEUE_UAPSD, 0);
318 for (i = 0; i < IEEE80211_NUM_ACS; i++) {
319 sc->tx.txq_map[i] = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, i);
320 sc->tx.txq_map[i]->mac80211_qnum = i;
321 sc->tx.txq_max_pending[i] = ATH_MAX_QDEPTH;
326 static void ath9k_init_misc(struct ath_softc *sc)
328 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
331 setup_timer(&common->ani.timer, ath_ani_calibrate, (unsigned long)sc);
333 common->last_rssi = ATH_RSSI_DUMMY_MARKER;
334 sc->config.txpowlimit = ATH_TXPOWER_MAX;
335 memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
336 sc->beacon.slottime = ATH9K_SLOT_TIME_9;
338 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++)
339 sc->beacon.bslot[i] = NULL;
341 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)
342 sc->ant_comb.count = ATH_ANT_DIV_COMB_INIT_COUNT;
344 sc->spec_config.enabled = 0;
345 sc->spec_config.short_repeat = true;
346 sc->spec_config.count = 8;
347 sc->spec_config.endless = false;
348 sc->spec_config.period = 0xFF;
349 sc->spec_config.fft_period = 0xF;
352 static void ath9k_init_pcoem_platform(struct ath_softc *sc)
354 struct ath_hw *ah = sc->sc_ah;
355 struct ath9k_hw_capabilities *pCap = &ah->caps;
356 struct ath_common *common = ath9k_hw_common(ah);
358 if (common->bus_ops->ath_bus_type != ATH_PCI)
361 if (sc->driver_data & (ATH9K_PCI_CUS198 |
363 ah->config.xlna_gpio = 9;
364 ah->config.xatten_margin_cfg = true;
365 ah->config.alt_mingainidx = true;
366 ah->config.ant_ctrl_comm2g_switch_enable = 0x000BBB88;
367 sc->ant_comb.low_rssi_thresh = 20;
368 sc->ant_comb.fast_div_bias = 3;
370 ath_info(common, "Set parameters for %s\n",
371 (sc->driver_data & ATH9K_PCI_CUS198) ?
372 "CUS198" : "CUS230");
375 if (sc->driver_data & ATH9K_PCI_CUS217)
376 ath_info(common, "CUS217 card detected\n");
378 if (sc->driver_data & ATH9K_PCI_CUS252)
379 ath_info(common, "CUS252 card detected\n");
381 if (sc->driver_data & ATH9K_PCI_AR9565_1ANT)
382 ath_info(common, "WB335 1-ANT card detected\n");
384 if (sc->driver_data & ATH9K_PCI_AR9565_2ANT)
385 ath_info(common, "WB335 2-ANT card detected\n");
387 if (sc->driver_data & ATH9K_PCI_KILLER)
388 ath_info(common, "Killer Wireless card detected\n");
391 * Some WB335 cards do not support antenna diversity. Since
392 * we use a hardcoded value for AR9565 instead of using the
393 * EEPROM/OTP data, remove the combining feature from
394 * the HW capabilities bitmap.
396 if (sc->driver_data & (ATH9K_PCI_AR9565_1ANT | ATH9K_PCI_AR9565_2ANT)) {
397 if (!(sc->driver_data & ATH9K_PCI_BT_ANT_DIV))
398 pCap->hw_caps &= ~ATH9K_HW_CAP_ANT_DIV_COMB;
401 if (sc->driver_data & ATH9K_PCI_BT_ANT_DIV) {
402 pCap->hw_caps |= ATH9K_HW_CAP_BT_ANT_DIV;
403 ath_info(common, "Set BT/WLAN RX diversity capability\n");
406 if (sc->driver_data & ATH9K_PCI_D3_L1_WAR) {
407 ah->config.pcie_waen = 0x0040473b;
408 ath_info(common, "Enable WAR for ASPM D3/L1\n");
411 if (sc->driver_data & ATH9K_PCI_NO_PLL_PWRSAVE) {
412 ah->config.no_pll_pwrsave = true;
413 ath_info(common, "Disable PLL PowerSave\n");
417 static void ath9k_eeprom_request_cb(const struct firmware *eeprom_blob,
420 struct ath9k_eeprom_ctx *ec = ctx;
423 ec->ah->eeprom_blob = eeprom_blob;
425 complete(&ec->complete);
428 static int ath9k_eeprom_request(struct ath_softc *sc, const char *name)
430 struct ath9k_eeprom_ctx ec;
431 struct ath_hw *ah = ah = sc->sc_ah;
434 /* try to load the EEPROM content asynchronously */
435 init_completion(&ec.complete);
438 err = request_firmware_nowait(THIS_MODULE, 1, name, sc->dev, GFP_KERNEL,
439 &ec, ath9k_eeprom_request_cb);
441 ath_err(ath9k_hw_common(ah),
442 "EEPROM request failed\n");
446 wait_for_completion(&ec.complete);
448 if (!ah->eeprom_blob) {
449 ath_err(ath9k_hw_common(ah),
450 "Unable to load EEPROM file %s\n", name);
457 static void ath9k_eeprom_release(struct ath_softc *sc)
459 release_firmware(sc->sc_ah->eeprom_blob);
462 static int ath9k_init_soc_platform(struct ath_softc *sc)
464 struct ath9k_platform_data *pdata = sc->dev->platform_data;
465 struct ath_hw *ah = sc->sc_ah;
471 if (pdata->eeprom_name) {
472 ret = ath9k_eeprom_request(sc, pdata->eeprom_name);
477 if (pdata->tx_gain_buffalo)
478 ah->config.tx_gain_buffalo = true;
483 static int ath9k_init_softc(u16 devid, struct ath_softc *sc,
484 const struct ath_bus_ops *bus_ops)
486 struct ath9k_platform_data *pdata = sc->dev->platform_data;
487 struct ath_hw *ah = NULL;
488 struct ath9k_hw_capabilities *pCap;
489 struct ath_common *common;
493 ah = devm_kzalloc(sc->dev, sizeof(struct ath_hw), GFP_KERNEL);
499 ah->hw_version.devid = devid;
500 ah->reg_ops.read = ath9k_ioread32;
501 ah->reg_ops.write = ath9k_iowrite32;
502 ah->reg_ops.rmw = ath9k_reg_rmw;
506 common = ath9k_hw_common(ah);
507 sc->dfs_detector = dfs_pattern_detector_init(common, NL80211_DFS_UNSET);
508 sc->tx99_power = MAX_RATE_POWER + 1;
509 init_waitqueue_head(&sc->tx_wait);
512 ah->ah_flags |= AH_USE_EEPROM;
513 sc->sc_ah->led_pin = -1;
515 sc->sc_ah->gpio_mask = pdata->gpio_mask;
516 sc->sc_ah->gpio_val = pdata->gpio_val;
517 sc->sc_ah->led_pin = pdata->led_pin;
518 ah->is_clk_25mhz = pdata->is_clk_25mhz;
519 ah->get_mac_revision = pdata->get_mac_revision;
520 ah->external_reset = pdata->external_reset;
523 common->ops = &ah->reg_ops;
524 common->bus_ops = bus_ops;
528 common->debug_mask = ath9k_debug;
529 common->btcoex_enabled = ath9k_btcoex_enable == 1;
530 common->disable_ani = false;
535 ath9k_init_pcoem_platform(sc);
537 ret = ath9k_init_soc_platform(sc);
542 * Enable WLAN/BT RX Antenna diversity only when:
544 * - BTCOEX is disabled.
545 * - the user manually requests the feature.
546 * - the HW cap is set using the platform data.
548 if (!common->btcoex_enabled && ath9k_bt_ant_diversity &&
549 (pCap->hw_caps & ATH9K_HW_CAP_BT_ANT_DIV))
550 common->bt_ant_diversity = 1;
552 spin_lock_init(&common->cc_lock);
553 spin_lock_init(&sc->sc_serial_rw);
554 spin_lock_init(&sc->sc_pm_lock);
555 mutex_init(&sc->mutex);
556 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
557 tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
560 setup_timer(&sc->sleep_timer, ath_ps_full_sleep, (unsigned long)sc);
561 INIT_WORK(&sc->hw_reset_work, ath_reset_work);
562 INIT_WORK(&sc->paprd_work, ath_paprd_calibrate);
563 INIT_DELAYED_WORK(&sc->hw_pll_work, ath_hw_pll_work);
566 * Cache line size is used to size and align various
567 * structures used to communicate with the hardware.
569 ath_read_cachesize(common, &csz);
570 common->cachelsz = csz << 2; /* convert to bytes */
572 /* Initializes the hardware for all supported chipsets */
573 ret = ath9k_hw_init(ah);
577 if (pdata && pdata->macaddr)
578 memcpy(common->macaddr, pdata->macaddr, ETH_ALEN);
580 ret = ath9k_init_queues(sc);
584 ret = ath9k_init_btcoex(sc);
588 ret = ath9k_cmn_init_channels_rates(common);
592 ath9k_cmn_init_crypto(sc->sc_ah);
594 ath_fill_led_pin(sc);
596 if (common->bus_ops->aspm_init)
597 common->bus_ops->aspm_init(common);
602 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
603 if (ATH_TXQ_SETUP(sc, i))
604 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
608 ath9k_eeprom_release(sc);
609 dev_kfree_skb_any(sc->tx99_skb);
613 static void ath9k_init_band_txpower(struct ath_softc *sc, int band)
615 struct ieee80211_supported_band *sband;
616 struct ieee80211_channel *chan;
617 struct ath_hw *ah = sc->sc_ah;
618 struct ath_common *common = ath9k_hw_common(ah);
619 struct cfg80211_chan_def chandef;
622 sband = &common->sbands[band];
623 for (i = 0; i < sband->n_channels; i++) {
624 chan = &sband->channels[i];
625 ah->curchan = &ah->channels[chan->hw_value];
626 cfg80211_chandef_create(&chandef, chan, NL80211_CHAN_HT20);
627 ath9k_cmn_get_channel(sc->hw, ah, &chandef);
628 ath9k_hw_set_txpowerlimit(ah, MAX_RATE_POWER, true);
632 static void ath9k_init_txpower_limits(struct ath_softc *sc)
634 struct ath_hw *ah = sc->sc_ah;
635 struct ath9k_channel *curchan = ah->curchan;
637 if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
638 ath9k_init_band_txpower(sc, IEEE80211_BAND_2GHZ);
639 if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
640 ath9k_init_band_txpower(sc, IEEE80211_BAND_5GHZ);
642 ah->curchan = curchan;
645 static const struct ieee80211_iface_limit if_limits[] = {
646 { .max = 2048, .types = BIT(NL80211_IFTYPE_STATION) |
647 BIT(NL80211_IFTYPE_P2P_CLIENT) |
648 BIT(NL80211_IFTYPE_WDS) },
650 #ifdef CONFIG_MAC80211_MESH
651 BIT(NL80211_IFTYPE_MESH_POINT) |
653 BIT(NL80211_IFTYPE_AP) |
654 BIT(NL80211_IFTYPE_P2P_GO) },
657 static const struct ieee80211_iface_limit if_dfs_limits[] = {
658 { .max = 1, .types = BIT(NL80211_IFTYPE_AP) |
659 #ifdef CONFIG_MAC80211_MESH
660 BIT(NL80211_IFTYPE_MESH_POINT) |
662 BIT(NL80211_IFTYPE_ADHOC) },
665 static const struct ieee80211_iface_combination if_comb[] = {
668 .n_limits = ARRAY_SIZE(if_limits),
669 .max_interfaces = 2048,
670 .num_different_channels = 1,
671 .beacon_int_infra_match = true,
673 #ifdef CONFIG_ATH9K_DFS_CERTIFIED
675 .limits = if_dfs_limits,
676 .n_limits = ARRAY_SIZE(if_dfs_limits),
678 .num_different_channels = 1,
679 .beacon_int_infra_match = true,
680 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) |
681 BIT(NL80211_CHAN_WIDTH_20),
686 static void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
688 struct ath_hw *ah = sc->sc_ah;
689 struct ath_common *common = ath9k_hw_common(ah);
691 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
692 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
693 IEEE80211_HW_SIGNAL_DBM |
694 IEEE80211_HW_PS_NULLFUNC_STACK |
695 IEEE80211_HW_SPECTRUM_MGMT |
696 IEEE80211_HW_REPORTS_TX_ACK_STATUS |
697 IEEE80211_HW_SUPPORTS_RC_TABLE |
698 IEEE80211_HW_SUPPORTS_HT_CCK_RATES;
701 hw->flags |= IEEE80211_HW_SUPPORTS_PS;
703 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
704 hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION;
706 if (AR_SREV_9280_20_OR_LATER(ah))
707 hw->radiotap_mcs_details |=
708 IEEE80211_RADIOTAP_MCS_HAVE_STBC;
711 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || ath9k_modparam_nohwcrypt)
712 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
714 hw->wiphy->features |= NL80211_FEATURE_ACTIVE_MONITOR;
716 if (!config_enabled(CONFIG_ATH9K_TX99)) {
717 hw->wiphy->interface_modes =
718 BIT(NL80211_IFTYPE_P2P_GO) |
719 BIT(NL80211_IFTYPE_P2P_CLIENT) |
720 BIT(NL80211_IFTYPE_AP) |
721 BIT(NL80211_IFTYPE_WDS) |
722 BIT(NL80211_IFTYPE_STATION) |
723 BIT(NL80211_IFTYPE_ADHOC) |
724 BIT(NL80211_IFTYPE_MESH_POINT);
725 hw->wiphy->iface_combinations = if_comb;
726 hw->wiphy->n_iface_combinations = ARRAY_SIZE(if_comb);
729 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
731 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
732 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS;
733 hw->wiphy->flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL;
734 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_5_10_MHZ;
735 hw->wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH;
736 hw->wiphy->flags |= WIPHY_FLAG_AP_UAPSD;
740 hw->max_listen_interval = 1;
741 hw->max_rate_tries = 10;
742 hw->sta_data_size = sizeof(struct ath_node);
743 hw->vif_data_size = sizeof(struct ath_vif);
745 hw->wiphy->available_antennas_rx = BIT(ah->caps.max_rxchains) - 1;
746 hw->wiphy->available_antennas_tx = BIT(ah->caps.max_txchains) - 1;
748 /* single chain devices with rx diversity */
749 if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)
750 hw->wiphy->available_antennas_rx = BIT(0) | BIT(1);
752 sc->ant_rx = hw->wiphy->available_antennas_rx;
753 sc->ant_tx = hw->wiphy->available_antennas_tx;
755 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
756 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
757 &common->sbands[IEEE80211_BAND_2GHZ];
758 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
759 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
760 &common->sbands[IEEE80211_BAND_5GHZ];
763 ath9k_cmn_reload_chainmask(ah);
765 SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
768 int ath9k_init_device(u16 devid, struct ath_softc *sc,
769 const struct ath_bus_ops *bus_ops)
771 struct ieee80211_hw *hw = sc->hw;
772 struct ath_common *common;
775 struct ath_regulatory *reg;
777 /* Bring up device */
778 error = ath9k_init_softc(devid, sc, bus_ops);
783 common = ath9k_hw_common(ah);
784 ath9k_set_hw_capab(sc, hw);
786 /* Will be cleared in ath9k_start() */
787 set_bit(ATH_OP_INVALID, &common->op_flags);
789 /* Initialize regulatory */
790 error = ath_regd_init(&common->regulatory, sc->hw->wiphy,
795 reg = &common->regulatory;
798 error = ath_tx_init(sc, ATH_TXBUF);
803 error = ath_rx_init(sc, ATH_RXBUF);
807 ath9k_init_txpower_limits(sc);
809 #ifdef CONFIG_MAC80211_LEDS
810 /* must be initialized before ieee80211_register_hw */
811 sc->led_cdev.default_trigger = ieee80211_create_tpt_led_trigger(sc->hw,
812 IEEE80211_TPT_LEDTRIG_FL_RADIO, ath9k_tpt_blink,
813 ARRAY_SIZE(ath9k_tpt_blink));
816 /* Register with mac80211 */
817 error = ieee80211_register_hw(hw);
821 error = ath9k_init_debug(ah);
823 ath_err(common, "Unable to create debugfs files\n");
827 /* Handle world regulatory */
828 if (!ath_is_world_regd(reg)) {
829 error = regulatory_hint(hw->wiphy, reg->alpha2);
835 ath_start_rfkill_poll(sc);
840 ath9k_deinit_debug(sc);
842 ieee80211_unregister_hw(hw);
846 ath9k_deinit_softc(sc);
850 /*****************************/
851 /* De-Initialization */
852 /*****************************/
854 static void ath9k_deinit_softc(struct ath_softc *sc)
858 ath9k_deinit_btcoex(sc);
860 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
861 if (ATH_TXQ_SETUP(sc, i))
862 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
864 del_timer_sync(&sc->sleep_timer);
865 ath9k_hw_deinit(sc->sc_ah);
866 if (sc->dfs_detector != NULL)
867 sc->dfs_detector->exit(sc->dfs_detector);
869 ath9k_eeprom_release(sc);
872 void ath9k_deinit_device(struct ath_softc *sc)
874 struct ieee80211_hw *hw = sc->hw;
878 wiphy_rfkill_stop_polling(sc->hw->wiphy);
881 ath9k_ps_restore(sc);
883 ath9k_deinit_debug(sc);
884 ieee80211_unregister_hw(hw);
886 ath9k_deinit_softc(sc);
889 /************************/
891 /************************/
893 static int __init ath9k_init(void)
897 error = ath_pci_init();
899 pr_err("No PCI devices found, driver not installed\n");
904 error = ath_ahb_init();
917 module_init(ath9k_init);
919 static void __exit ath9k_exit(void)
921 is_ath9k_unloaded = true;
924 pr_info("%s: Driver unloaded\n", dev_info);
926 module_exit(ath9k_exit);