2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include <asm/unaligned.h>
25 #define ATH9K_CLOCK_RATE_CCK 22
26 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
27 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
29 static void ar9002_hw_attach_ops(struct ath_hw *ah);
31 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
33 MODULE_AUTHOR("Atheros Communications");
34 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
35 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
36 MODULE_LICENSE("Dual BSD/GPL");
38 static int __init ath9k_init(void)
42 module_init(ath9k_init);
44 static void __exit ath9k_exit(void)
48 module_exit(ath9k_exit);
50 /* Private hardware callbacks */
52 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
54 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
57 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
59 ath9k_hw_private_ops(ah)->init_mode_regs(ah);
62 static bool ath9k_hw_macversion_supported(struct ath_hw *ah)
64 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
66 return priv_ops->macversion_supported(ah->hw_version.macVersion);
69 /********************/
70 /* Helper Functions */
71 /********************/
73 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
75 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
77 if (!ah->curchan) /* should really check for CCK instead */
78 return usecs *ATH9K_CLOCK_RATE_CCK;
79 if (conf->channel->band == IEEE80211_BAND_2GHZ)
80 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
81 return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
84 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
86 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
88 if (conf_is_ht40(conf))
89 return ath9k_hw_mac_clks(ah, usecs) * 2;
91 return ath9k_hw_mac_clks(ah, usecs);
94 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
98 BUG_ON(timeout < AH_TIME_QUANTUM);
100 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
101 if ((REG_READ(ah, reg) & mask) == val)
104 udelay(AH_TIME_QUANTUM);
107 ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
108 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
109 timeout, reg, REG_READ(ah, reg), mask, val);
113 EXPORT_SYMBOL(ath9k_hw_wait);
115 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
120 for (i = 0, retval = 0; i < n; i++) {
121 retval = (retval << 1) | (val & 1);
127 bool ath9k_get_channel_edges(struct ath_hw *ah,
131 struct ath9k_hw_capabilities *pCap = &ah->caps;
133 if (flags & CHANNEL_5GHZ) {
134 *low = pCap->low_5ghz_chan;
135 *high = pCap->high_5ghz_chan;
138 if ((flags & CHANNEL_2GHZ)) {
139 *low = pCap->low_2ghz_chan;
140 *high = pCap->high_2ghz_chan;
146 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
148 u32 frameLen, u16 rateix,
151 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
157 case WLAN_RC_PHY_CCK:
158 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
161 numBits = frameLen << 3;
162 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
164 case WLAN_RC_PHY_OFDM:
165 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
166 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
167 numBits = OFDM_PLCP_BITS + (frameLen << 3);
168 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
169 txTime = OFDM_SIFS_TIME_QUARTER
170 + OFDM_PREAMBLE_TIME_QUARTER
171 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
172 } else if (ah->curchan &&
173 IS_CHAN_HALF_RATE(ah->curchan)) {
174 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
175 numBits = OFDM_PLCP_BITS + (frameLen << 3);
176 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
177 txTime = OFDM_SIFS_TIME_HALF +
178 OFDM_PREAMBLE_TIME_HALF
179 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
181 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
182 numBits = OFDM_PLCP_BITS + (frameLen << 3);
183 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
184 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
185 + (numSymbols * OFDM_SYMBOL_TIME);
189 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
190 "Unknown phy %u (rate ix %u)\n", phy, rateix);
197 EXPORT_SYMBOL(ath9k_hw_computetxtime);
199 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
200 struct ath9k_channel *chan,
201 struct chan_centers *centers)
205 if (!IS_CHAN_HT40(chan)) {
206 centers->ctl_center = centers->ext_center =
207 centers->synth_center = chan->channel;
211 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
212 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
213 centers->synth_center =
214 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
217 centers->synth_center =
218 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
222 centers->ctl_center =
223 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
224 /* 25 MHz spacing is supported by hw but not on upper layers */
225 centers->ext_center =
226 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
233 static void ath9k_hw_read_revisions(struct ath_hw *ah)
237 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
240 val = REG_READ(ah, AR_SREV);
241 ah->hw_version.macVersion =
242 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
243 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
244 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
246 if (!AR_SREV_9100(ah))
247 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
249 ah->hw_version.macRev = val & AR_SREV_REVISION;
251 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
252 ah->is_pciexpress = true;
256 static int ath9k_hw_get_radiorev(struct ath_hw *ah)
261 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
263 for (i = 0; i < 8; i++)
264 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
265 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
266 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
268 return ath9k_hw_reverse_bits(val, 8);
271 /************************************/
272 /* HW Attach, Detach, Init Routines */
273 /************************************/
275 static void ath9k_hw_disablepcie(struct ath_hw *ah)
277 if (AR_SREV_9100(ah))
280 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
281 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
282 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
283 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
284 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
285 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
286 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
287 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
288 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
290 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
293 static bool ath9k_hw_chip_test(struct ath_hw *ah)
295 struct ath_common *common = ath9k_hw_common(ah);
296 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
298 u32 patternData[4] = { 0x55555555,
304 for (i = 0; i < 2; i++) {
305 u32 addr = regAddr[i];
308 regHold[i] = REG_READ(ah, addr);
309 for (j = 0; j < 0x100; j++) {
310 wrData = (j << 16) | j;
311 REG_WRITE(ah, addr, wrData);
312 rdData = REG_READ(ah, addr);
313 if (rdData != wrData) {
314 ath_print(common, ATH_DBG_FATAL,
315 "address test failed "
316 "addr: 0x%08x - wr:0x%08x != "
318 addr, wrData, rdData);
322 for (j = 0; j < 4; j++) {
323 wrData = patternData[j];
324 REG_WRITE(ah, addr, wrData);
325 rdData = REG_READ(ah, addr);
326 if (wrData != rdData) {
327 ath_print(common, ATH_DBG_FATAL,
328 "address test failed "
329 "addr: 0x%08x - wr:0x%08x != "
331 addr, wrData, rdData);
335 REG_WRITE(ah, regAddr[i], regHold[i]);
342 static void ath9k_hw_init_config(struct ath_hw *ah)
346 ah->config.dma_beacon_response_time = 2;
347 ah->config.sw_beacon_response_time = 10;
348 ah->config.additional_swba_backoff = 0;
349 ah->config.ack_6mb = 0x0;
350 ah->config.cwm_ignore_extcca = 0;
351 ah->config.pcie_powersave_enable = 0;
352 ah->config.pcie_clock_req = 0;
353 ah->config.pcie_waen = 0;
354 ah->config.analog_shiftreg = 1;
355 ah->config.ofdm_trig_low = 200;
356 ah->config.ofdm_trig_high = 500;
357 ah->config.cck_trig_high = 200;
358 ah->config.cck_trig_low = 100;
359 ah->config.enable_ani = 1;
361 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
362 ah->config.spurchans[i][0] = AR_NO_SPUR;
363 ah->config.spurchans[i][1] = AR_NO_SPUR;
366 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
367 ah->config.ht_enable = 1;
369 ah->config.ht_enable = 0;
371 ah->config.rx_intr_mitigation = true;
374 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
375 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
376 * This means we use it for all AR5416 devices, and the few
377 * minor PCI AR9280 devices out there.
379 * Serialization is required because these devices do not handle
380 * well the case of two concurrent reads/writes due to the latency
381 * involved. During one read/write another read/write can be issued
382 * on another CPU while the previous read/write may still be working
383 * on our hardware, if we hit this case the hardware poops in a loop.
384 * We prevent this by serializing reads and writes.
386 * This issue is not present on PCI-Express devices or pre-AR5416
387 * devices (legacy, 802.11abg).
389 if (num_possible_cpus() > 1)
390 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
393 static void ath9k_hw_init_defaults(struct ath_hw *ah)
395 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
397 regulatory->country_code = CTRY_DEFAULT;
398 regulatory->power_limit = MAX_RATE_POWER;
399 regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
401 ah->hw_version.magic = AR5416_MAGIC;
402 ah->hw_version.subvendorid = 0;
405 if (ah->hw_version.devid == AR5416_AR9100_DEVID)
406 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
407 if (!AR_SREV_9100(ah))
408 ah->ah_flags = AH_USE_EEPROM;
411 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
412 ah->beacon_interval = 100;
413 ah->enable_32kHz_clock = DONT_USE_32KHZ;
414 ah->slottime = (u32) -1;
415 ah->globaltxtimeout = (u32) -1;
416 ah->power_mode = ATH9K_PM_UNDEFINED;
419 static int ath9k_hw_rf_claim(struct ath_hw *ah)
423 REG_WRITE(ah, AR_PHY(0), 0x00000007);
425 val = ath9k_hw_get_radiorev(ah);
426 switch (val & AR_RADIO_SREV_MAJOR) {
428 val = AR_RAD5133_SREV_MAJOR;
430 case AR_RAD5133_SREV_MAJOR:
431 case AR_RAD5122_SREV_MAJOR:
432 case AR_RAD2133_SREV_MAJOR:
433 case AR_RAD2122_SREV_MAJOR:
436 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
437 "Radio Chip Rev 0x%02X not supported\n",
438 val & AR_RADIO_SREV_MAJOR);
442 ah->hw_version.analog5GhzRev = val;
447 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
449 struct ath_common *common = ath9k_hw_common(ah);
455 for (i = 0; i < 3; i++) {
456 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
458 common->macaddr[2 * i] = eeval >> 8;
459 common->macaddr[2 * i + 1] = eeval & 0xff;
461 if (sum == 0 || sum == 0xffff * 3)
462 return -EADDRNOTAVAIL;
467 static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
471 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
472 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
474 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
475 INIT_INI_ARRAY(&ah->iniModesRxGain,
476 ar9280Modes_backoff_13db_rxgain_9280_2,
477 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
478 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
479 INIT_INI_ARRAY(&ah->iniModesRxGain,
480 ar9280Modes_backoff_23db_rxgain_9280_2,
481 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
483 INIT_INI_ARRAY(&ah->iniModesRxGain,
484 ar9280Modes_original_rxgain_9280_2,
485 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
487 INIT_INI_ARRAY(&ah->iniModesRxGain,
488 ar9280Modes_original_rxgain_9280_2,
489 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
493 static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
497 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
498 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
500 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
501 INIT_INI_ARRAY(&ah->iniModesTxGain,
502 ar9280Modes_high_power_tx_gain_9280_2,
503 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
505 INIT_INI_ARRAY(&ah->iniModesTxGain,
506 ar9280Modes_original_tx_gain_9280_2,
507 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
509 INIT_INI_ARRAY(&ah->iniModesTxGain,
510 ar9280Modes_original_tx_gain_9280_2,
511 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
515 static int ath9k_hw_post_init(struct ath_hw *ah)
519 if (!AR_SREV_9271(ah)) {
520 if (!ath9k_hw_chip_test(ah))
524 ecode = ath9k_hw_rf_claim(ah);
528 ecode = ath9k_hw_eeprom_init(ah);
532 ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
533 "Eeprom VER: %d, REV: %d\n",
534 ah->eep_ops->get_eeprom_ver(ah),
535 ah->eep_ops->get_eeprom_rev(ah));
537 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
539 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
540 "Failed allocating banks for "
545 if (!AR_SREV_9100(ah)) {
546 ath9k_hw_ani_setup(ah);
547 ath9k_hw_ani_init(ah);
553 static bool ar9002_hw_macversion_supported(u32 macversion)
555 switch (macversion) {
556 case AR_SREV_VERSION_5416_PCI:
557 case AR_SREV_VERSION_5416_PCIE:
558 case AR_SREV_VERSION_9160:
559 case AR_SREV_VERSION_9100:
560 case AR_SREV_VERSION_9280:
561 case AR_SREV_VERSION_9285:
562 case AR_SREV_VERSION_9287:
563 case AR_SREV_VERSION_9271:
571 static void ar9002_hw_init_cal_settings(struct ath_hw *ah)
573 if (AR_SREV_9160_10_OR_LATER(ah)) {
574 if (AR_SREV_9280_10_OR_LATER(ah)) {
575 ah->iq_caldata.calData = &iq_cal_single_sample;
576 ah->adcgain_caldata.calData =
577 &adc_gain_cal_single_sample;
578 ah->adcdc_caldata.calData =
579 &adc_dc_cal_single_sample;
580 ah->adcdc_calinitdata.calData =
583 ah->iq_caldata.calData = &iq_cal_multi_sample;
584 ah->adcgain_caldata.calData =
585 &adc_gain_cal_multi_sample;
586 ah->adcdc_caldata.calData =
587 &adc_dc_cal_multi_sample;
588 ah->adcdc_calinitdata.calData =
591 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
595 static void ar9002_hw_init_mode_regs(struct ath_hw *ah)
597 if (AR_SREV_9271(ah)) {
598 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271,
599 ARRAY_SIZE(ar9271Modes_9271), 6);
600 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271,
601 ARRAY_SIZE(ar9271Common_9271), 2);
602 INIT_INI_ARRAY(&ah->iniCommon_normal_cck_fir_coeff_9271,
603 ar9271Common_normal_cck_fir_coeff_9271,
604 ARRAY_SIZE(ar9271Common_normal_cck_fir_coeff_9271), 2);
605 INIT_INI_ARRAY(&ah->iniCommon_japan_2484_cck_fir_coeff_9271,
606 ar9271Common_japan_2484_cck_fir_coeff_9271,
607 ARRAY_SIZE(ar9271Common_japan_2484_cck_fir_coeff_9271), 2);
608 INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only,
609 ar9271Modes_9271_1_0_only,
610 ARRAY_SIZE(ar9271Modes_9271_1_0_only), 6);
611 INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg,
612 ARRAY_SIZE(ar9271Modes_9271_ANI_reg), 6);
613 INIT_INI_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
614 ar9271Modes_high_power_tx_gain_9271,
615 ARRAY_SIZE(ar9271Modes_high_power_tx_gain_9271), 6);
616 INIT_INI_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
617 ar9271Modes_normal_power_tx_gain_9271,
618 ARRAY_SIZE(ar9271Modes_normal_power_tx_gain_9271), 6);
622 if (AR_SREV_9287_11_OR_LATER(ah)) {
623 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
624 ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
625 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
626 ARRAY_SIZE(ar9287Common_9287_1_1), 2);
627 if (ah->config.pcie_clock_req)
628 INIT_INI_ARRAY(&ah->iniPcieSerdes,
629 ar9287PciePhy_clkreq_off_L1_9287_1_1,
630 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
632 INIT_INI_ARRAY(&ah->iniPcieSerdes,
633 ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
634 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
636 } else if (AR_SREV_9287_10_OR_LATER(ah)) {
637 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
638 ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
639 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
640 ARRAY_SIZE(ar9287Common_9287_1_0), 2);
642 if (ah->config.pcie_clock_req)
643 INIT_INI_ARRAY(&ah->iniPcieSerdes,
644 ar9287PciePhy_clkreq_off_L1_9287_1_0,
645 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
647 INIT_INI_ARRAY(&ah->iniPcieSerdes,
648 ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
649 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
651 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
654 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
655 ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
656 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
657 ARRAY_SIZE(ar9285Common_9285_1_2), 2);
659 if (ah->config.pcie_clock_req) {
660 INIT_INI_ARRAY(&ah->iniPcieSerdes,
661 ar9285PciePhy_clkreq_off_L1_9285_1_2,
662 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
664 INIT_INI_ARRAY(&ah->iniPcieSerdes,
665 ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
666 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
669 } else if (AR_SREV_9285_10_OR_LATER(ah)) {
670 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
671 ARRAY_SIZE(ar9285Modes_9285), 6);
672 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
673 ARRAY_SIZE(ar9285Common_9285), 2);
675 if (ah->config.pcie_clock_req) {
676 INIT_INI_ARRAY(&ah->iniPcieSerdes,
677 ar9285PciePhy_clkreq_off_L1_9285,
678 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
680 INIT_INI_ARRAY(&ah->iniPcieSerdes,
681 ar9285PciePhy_clkreq_always_on_L1_9285,
682 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
684 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
685 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
686 ARRAY_SIZE(ar9280Modes_9280_2), 6);
687 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
688 ARRAY_SIZE(ar9280Common_9280_2), 2);
690 if (ah->config.pcie_clock_req) {
691 INIT_INI_ARRAY(&ah->iniPcieSerdes,
692 ar9280PciePhy_clkreq_off_L1_9280,
693 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
695 INIT_INI_ARRAY(&ah->iniPcieSerdes,
696 ar9280PciePhy_clkreq_always_on_L1_9280,
697 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
699 INIT_INI_ARRAY(&ah->iniModesAdditional,
700 ar9280Modes_fast_clock_9280_2,
701 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
702 } else if (AR_SREV_9280_10_OR_LATER(ah)) {
703 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
704 ARRAY_SIZE(ar9280Modes_9280), 6);
705 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
706 ARRAY_SIZE(ar9280Common_9280), 2);
707 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
708 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
709 ARRAY_SIZE(ar5416Modes_9160), 6);
710 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
711 ARRAY_SIZE(ar5416Common_9160), 2);
712 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
713 ARRAY_SIZE(ar5416Bank0_9160), 2);
714 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
715 ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
716 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
717 ARRAY_SIZE(ar5416Bank1_9160), 2);
718 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
719 ARRAY_SIZE(ar5416Bank2_9160), 2);
720 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
721 ARRAY_SIZE(ar5416Bank3_9160), 3);
722 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
723 ARRAY_SIZE(ar5416Bank6_9160), 3);
724 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
725 ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
726 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
727 ARRAY_SIZE(ar5416Bank7_9160), 2);
728 if (AR_SREV_9160_11(ah)) {
729 INIT_INI_ARRAY(&ah->iniAddac,
731 ARRAY_SIZE(ar5416Addac_91601_1), 2);
733 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
734 ARRAY_SIZE(ar5416Addac_9160), 2);
736 } else if (AR_SREV_9100_OR_LATER(ah)) {
737 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
738 ARRAY_SIZE(ar5416Modes_9100), 6);
739 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
740 ARRAY_SIZE(ar5416Common_9100), 2);
741 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
742 ARRAY_SIZE(ar5416Bank0_9100), 2);
743 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
744 ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
745 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
746 ARRAY_SIZE(ar5416Bank1_9100), 2);
747 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
748 ARRAY_SIZE(ar5416Bank2_9100), 2);
749 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
750 ARRAY_SIZE(ar5416Bank3_9100), 3);
751 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
752 ARRAY_SIZE(ar5416Bank6_9100), 3);
753 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
754 ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
755 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
756 ARRAY_SIZE(ar5416Bank7_9100), 2);
757 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
758 ARRAY_SIZE(ar5416Addac_9100), 2);
760 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
761 ARRAY_SIZE(ar5416Modes), 6);
762 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
763 ARRAY_SIZE(ar5416Common), 2);
764 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
765 ARRAY_SIZE(ar5416Bank0), 2);
766 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
767 ARRAY_SIZE(ar5416BB_RfGain), 3);
768 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
769 ARRAY_SIZE(ar5416Bank1), 2);
770 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
771 ARRAY_SIZE(ar5416Bank2), 2);
772 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
773 ARRAY_SIZE(ar5416Bank3), 3);
774 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
775 ARRAY_SIZE(ar5416Bank6), 3);
776 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
777 ARRAY_SIZE(ar5416Bank6TPC), 3);
778 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
779 ARRAY_SIZE(ar5416Bank7), 2);
780 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
781 ARRAY_SIZE(ar5416Addac), 2);
785 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
787 if (AR_SREV_9287_11_OR_LATER(ah))
788 INIT_INI_ARRAY(&ah->iniModesRxGain,
789 ar9287Modes_rx_gain_9287_1_1,
790 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
791 else if (AR_SREV_9287_10(ah))
792 INIT_INI_ARRAY(&ah->iniModesRxGain,
793 ar9287Modes_rx_gain_9287_1_0,
794 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
795 else if (AR_SREV_9280_20(ah))
796 ath9k_hw_init_rxgain_ini(ah);
798 if (AR_SREV_9287_11_OR_LATER(ah)) {
799 INIT_INI_ARRAY(&ah->iniModesTxGain,
800 ar9287Modes_tx_gain_9287_1_1,
801 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
802 } else if (AR_SREV_9287_10(ah)) {
803 INIT_INI_ARRAY(&ah->iniModesTxGain,
804 ar9287Modes_tx_gain_9287_1_0,
805 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
806 } else if (AR_SREV_9280_20(ah)) {
807 ath9k_hw_init_txgain_ini(ah);
808 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
809 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
812 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
813 if (AR_SREV_9285E_20(ah)) {
814 INIT_INI_ARRAY(&ah->iniModesTxGain,
815 ar9285Modes_XE2_0_high_power,
817 ar9285Modes_XE2_0_high_power), 6);
819 INIT_INI_ARRAY(&ah->iniModesTxGain,
820 ar9285Modes_high_power_tx_gain_9285_1_2,
822 ar9285Modes_high_power_tx_gain_9285_1_2), 6);
825 if (AR_SREV_9285E_20(ah)) {
826 INIT_INI_ARRAY(&ah->iniModesTxGain,
827 ar9285Modes_XE2_0_normal_power,
829 ar9285Modes_XE2_0_normal_power), 6);
831 INIT_INI_ARRAY(&ah->iniModesTxGain,
832 ar9285Modes_original_tx_gain_9285_1_2,
834 ar9285Modes_original_tx_gain_9285_1_2), 6);
840 static void ath9k_hw_init_eeprom_fix(struct ath_hw *ah)
842 struct base_eep_header *pBase = &(ah->eeprom.def.baseEepHeader);
843 struct ath_common *common = ath9k_hw_common(ah);
845 ah->need_an_top2_fixup = (ah->hw_version.devid == AR9280_DEVID_PCI) &&
846 (ah->eep_map != EEP_MAP_4KBITS) &&
847 ((pBase->version & 0xff) > 0x0a) &&
848 (pBase->pwdclkind == 0);
850 if (ah->need_an_top2_fixup)
851 ath_print(common, ATH_DBG_EEPROM,
852 "needs fixup for AR_AN_TOP2 register\n");
855 /* Called for all hardware families */
856 static int __ath9k_hw_init(struct ath_hw *ah)
858 struct ath_common *common = ath9k_hw_common(ah);
861 ath9k_hw_init_defaults(ah);
862 ath9k_hw_init_config(ah);
864 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
865 ath_print(common, ATH_DBG_FATAL,
866 "Couldn't reset chip\n");
870 ar9002_hw_attach_ops(ah);
872 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
873 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
877 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
878 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
879 (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
880 ah->config.serialize_regmode =
883 ah->config.serialize_regmode =
888 ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
889 ah->config.serialize_regmode);
891 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
892 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
894 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
896 if (!ath9k_hw_macversion_supported(ah)) {
897 ath_print(common, ATH_DBG_FATAL,
898 "Mac Chip Rev 0x%02x.%x is not supported by "
899 "this driver\n", ah->hw_version.macVersion,
900 ah->hw_version.macRev);
904 if (AR_SREV_9100(ah)) {
905 ah->iq_caldata.calData = &iq_cal_multi_sample;
906 ah->supp_cals = IQ_MISMATCH_CAL;
907 ah->is_pciexpress = false;
910 if (AR_SREV_9271(ah))
911 ah->is_pciexpress = false;
913 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
914 ath9k_hw_init_cal_settings(ah);
916 ah->ani_function = ATH9K_ANI_ALL;
917 if (AR_SREV_9280_10_OR_LATER(ah))
918 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
920 ath9k_hw_init_mode_regs(ah);
922 if (ah->is_pciexpress)
923 ath9k_hw_configpcipowersave(ah, 0, 0);
925 ath9k_hw_disablepcie(ah);
927 /* Support for Japan ch.14 (2484) spread */
928 if (AR_SREV_9287_11_OR_LATER(ah)) {
929 INIT_INI_ARRAY(&ah->iniCckfirNormal,
930 ar9287Common_normal_cck_fir_coeff_92871_1,
931 ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1), 2);
932 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
933 ar9287Common_japan_2484_cck_fir_coeff_92871_1,
934 ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1), 2);
937 r = ath9k_hw_post_init(ah);
941 ath9k_hw_init_mode_gain_regs(ah);
942 r = ath9k_hw_fill_cap_info(ah);
946 ath9k_hw_init_eeprom_fix(ah);
948 r = ath9k_hw_init_macaddr(ah);
950 ath_print(common, ATH_DBG_FATAL,
951 "Failed to initialize MAC address\n");
955 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
956 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
958 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
960 ath9k_init_nfcal_hist_buffer(ah);
962 common->state = ATH_HW_INITIALIZED;
967 int ath9k_hw_init(struct ath_hw *ah)
970 struct ath_common *common = ath9k_hw_common(ah);
972 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
973 switch (ah->hw_version.devid) {
974 case AR5416_DEVID_PCI:
975 case AR5416_DEVID_PCIE:
976 case AR5416_AR9100_DEVID:
977 case AR9160_DEVID_PCI:
978 case AR9280_DEVID_PCI:
979 case AR9280_DEVID_PCIE:
980 case AR9285_DEVID_PCIE:
981 case AR5416_DEVID_AR9287_PCI:
982 case AR5416_DEVID_AR9287_PCIE:
983 case AR2427_DEVID_PCIE:
986 if (common->bus_ops->ath_bus_type == ATH_USB)
988 ath_print(common, ATH_DBG_FATAL,
989 "Hardware device ID 0x%04x not supported\n",
990 ah->hw_version.devid);
994 ret = __ath9k_hw_init(ah);
996 ath_print(common, ATH_DBG_FATAL,
997 "Unable to initialize hardware; "
998 "initialization status: %d\n", ret);
1004 EXPORT_SYMBOL(ath9k_hw_init);
1006 static void ath9k_hw_init_qos(struct ath_hw *ah)
1008 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
1009 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
1011 REG_WRITE(ah, AR_QOS_NO_ACK,
1012 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
1013 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
1014 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
1016 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
1017 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
1018 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
1019 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
1020 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
1023 static void ath9k_hw_init_pll(struct ath_hw *ah,
1024 struct ath9k_channel *chan)
1028 if (AR_SREV_9100(ah)) {
1029 if (chan && IS_CHAN_5GHZ(chan))
1034 if (AR_SREV_9280_10_OR_LATER(ah)) {
1035 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1037 if (chan && IS_CHAN_HALF_RATE(chan))
1038 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1039 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1040 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1042 if (chan && IS_CHAN_5GHZ(chan)) {
1043 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
1046 if (AR_SREV_9280_20(ah)) {
1047 if (((chan->channel % 20) == 0)
1048 || ((chan->channel % 10) == 0))
1054 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
1057 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1059 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1061 if (chan && IS_CHAN_HALF_RATE(chan))
1062 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1063 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1064 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1066 if (chan && IS_CHAN_5GHZ(chan))
1067 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1069 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1071 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1073 if (chan && IS_CHAN_HALF_RATE(chan))
1074 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1075 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1076 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1078 if (chan && IS_CHAN_5GHZ(chan))
1079 pll |= SM(0xa, AR_RTC_PLL_DIV);
1081 pll |= SM(0xb, AR_RTC_PLL_DIV);
1084 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
1086 /* Switch the core clock for ar9271 to 117Mhz */
1087 if (AR_SREV_9271(ah)) {
1089 REG_WRITE(ah, 0x50040, 0x304);
1092 udelay(RTC_PLL_SETTLE_DELAY);
1094 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1097 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1098 enum nl80211_iftype opmode)
1100 u32 imr_reg = AR_IMR_TXERR |
1106 if (ah->config.rx_intr_mitigation)
1107 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1109 imr_reg |= AR_IMR_RXOK;
1111 imr_reg |= AR_IMR_TXOK;
1113 if (opmode == NL80211_IFTYPE_AP)
1114 imr_reg |= AR_IMR_MIB;
1116 REG_WRITE(ah, AR_IMR, imr_reg);
1117 ah->imrs2_reg |= AR_IMR_S2_GTT;
1118 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
1120 if (!AR_SREV_9100(ah)) {
1121 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1122 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1123 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1127 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
1129 u32 val = ath9k_hw_mac_to_clks(ah, us);
1130 val = min(val, (u32) 0xFFFF);
1131 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
1134 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1136 u32 val = ath9k_hw_mac_to_clks(ah, us);
1137 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
1138 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
1141 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1143 u32 val = ath9k_hw_mac_to_clks(ah, us);
1144 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
1145 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
1148 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1151 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
1152 "bad global tx timeout %u\n", tu);
1153 ah->globaltxtimeout = (u32) -1;
1156 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1157 ah->globaltxtimeout = tu;
1162 void ath9k_hw_init_global_settings(struct ath_hw *ah)
1164 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
1169 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1172 if (ah->misc_mode != 0)
1173 REG_WRITE(ah, AR_PCU_MISC,
1174 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1176 if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
1181 /* As defined by IEEE 802.11-2007 17.3.8.6 */
1182 slottime = ah->slottime + 3 * ah->coverage_class;
1183 acktimeout = slottime + sifstime;
1186 * Workaround for early ACK timeouts, add an offset to match the
1187 * initval's 64us ack timeout value.
1188 * This was initially only meant to work around an issue with delayed
1189 * BA frames in some implementations, but it has been found to fix ACK
1190 * timeout issues in other cases as well.
1192 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
1193 acktimeout += 64 - sifstime - ah->slottime;
1195 ath9k_hw_setslottime(ah, slottime);
1196 ath9k_hw_set_ack_timeout(ah, acktimeout);
1197 ath9k_hw_set_cts_timeout(ah, acktimeout);
1198 if (ah->globaltxtimeout != (u32) -1)
1199 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1201 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
1203 void ath9k_hw_deinit(struct ath_hw *ah)
1205 struct ath_common *common = ath9k_hw_common(ah);
1207 if (common->state < ATH_HW_INITIALIZED)
1210 if (!AR_SREV_9100(ah))
1211 ath9k_hw_ani_disable(ah);
1213 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1216 ath9k_hw_rf_free_ext_banks(ah);
1218 EXPORT_SYMBOL(ath9k_hw_deinit);
1224 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
1226 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1228 if (IS_CHAN_B(chan))
1230 else if (IS_CHAN_G(chan))
1238 /****************************************/
1239 /* Reset and Channel Switching Routines */
1240 /****************************************/
1242 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1247 * set AHB_MODE not to do cacheline prefetches
1249 regval = REG_READ(ah, AR_AHB_MODE);
1250 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1253 * let mac dma reads be in 128 byte chunks
1255 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1256 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1259 * Restore TX Trigger Level to its pre-reset value.
1260 * The initial value depends on whether aggregation is enabled, and is
1261 * adjusted whenever underruns are detected.
1263 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1266 * let mac dma writes be in 128 byte chunks
1268 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1269 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1272 * Setup receive FIFO threshold to hold off TX activities
1274 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1277 * reduce the number of usable entries in PCU TXBUF to avoid
1278 * wrap around issues.
1280 if (AR_SREV_9285(ah)) {
1281 /* For AR9285 the number of Fifos are reduced to half.
1282 * So set the usable tx buf size also to half to
1283 * avoid data/delimiter underruns
1285 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1286 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1287 } else if (!AR_SREV_9271(ah)) {
1288 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1289 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1293 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1297 val = REG_READ(ah, AR_STA_ID1);
1298 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1300 case NL80211_IFTYPE_AP:
1301 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1302 | AR_STA_ID1_KSRCH_MODE);
1303 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1305 case NL80211_IFTYPE_ADHOC:
1306 case NL80211_IFTYPE_MESH_POINT:
1307 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1308 | AR_STA_ID1_KSRCH_MODE);
1309 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1311 case NL80211_IFTYPE_STATION:
1312 case NL80211_IFTYPE_MONITOR:
1313 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1318 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1319 u32 *coef_mantissa, u32 *coef_exponent)
1321 u32 coef_exp, coef_man;
1323 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1324 if ((coef_scaled >> coef_exp) & 0x1)
1327 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1329 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1331 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1332 *coef_exponent = coef_exp - 16;
1335 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1340 if (AR_SREV_9100(ah)) {
1341 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1342 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1343 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1344 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1345 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1348 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1349 AR_RTC_FORCE_WAKE_ON_INT);
1351 if (AR_SREV_9100(ah)) {
1352 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1353 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1355 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1357 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1358 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1360 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1363 if (!AR_SREV_9300_20_OR_LATER(ah))
1365 REG_WRITE(ah, AR_RC, val);
1367 } else if (!AR_SREV_9300_20_OR_LATER(ah))
1368 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1370 rst_flags = AR_RTC_RC_MAC_WARM;
1371 if (type == ATH9K_RESET_COLD)
1372 rst_flags |= AR_RTC_RC_MAC_COLD;
1375 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1378 REG_WRITE(ah, AR_RTC_RC, 0);
1379 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1380 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1381 "RTC stuck in MAC reset\n");
1385 if (!AR_SREV_9100(ah))
1386 REG_WRITE(ah, AR_RC, 0);
1388 if (AR_SREV_9100(ah))
1394 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1396 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1397 AR_RTC_FORCE_WAKE_ON_INT);
1399 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1400 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1402 REG_WRITE(ah, AR_RTC_RESET, 0);
1405 if (!AR_SREV_9100(ah))
1406 REG_WRITE(ah, AR_RC, 0);
1408 REG_WRITE(ah, AR_RTC_RESET, 1);
1410 if (!ath9k_hw_wait(ah,
1415 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1416 "RTC not waking up\n");
1420 ath9k_hw_read_revisions(ah);
1422 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1425 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1427 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1428 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1431 case ATH9K_RESET_POWER_ON:
1432 return ath9k_hw_set_reset_power_on(ah);
1433 case ATH9K_RESET_WARM:
1434 case ATH9K_RESET_COLD:
1435 return ath9k_hw_set_reset(ah, type);
1441 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1442 struct ath9k_channel *chan)
1444 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1445 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1447 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1450 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1453 ah->chip_fullsleep = false;
1454 ath9k_hw_init_pll(ah, chan);
1455 ath9k_hw_set_rfmode(ah, chan);
1460 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1461 struct ath9k_channel *chan)
1463 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1464 struct ath_common *common = ath9k_hw_common(ah);
1465 struct ieee80211_channel *channel = chan->chan;
1469 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1470 if (ath9k_hw_numtxpending(ah, qnum)) {
1471 ath_print(common, ATH_DBG_QUEUE,
1472 "Transmit frames pending on "
1473 "queue %d\n", qnum);
1478 if (!ath9k_hw_rfbus_req(ah)) {
1479 ath_print(common, ATH_DBG_FATAL,
1480 "Could not kill baseband RX\n");
1484 ath9k_hw_set_channel_regs(ah, chan);
1486 r = ath9k_hw_rf_set_freq(ah, chan);
1488 ath_print(common, ATH_DBG_FATAL,
1489 "Failed to set channel\n");
1493 ah->eep_ops->set_txpower(ah, chan,
1494 ath9k_regd_get_ctl(regulatory, chan),
1495 channel->max_antenna_gain * 2,
1496 channel->max_power * 2,
1497 min((u32) MAX_RATE_POWER,
1498 (u32) regulatory->power_limit));
1500 ath9k_hw_rfbus_done(ah);
1502 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1503 ath9k_hw_set_delta_slope(ah, chan);
1505 ath9k_hw_spur_mitigate_freq(ah, chan);
1507 if (!chan->oneTimeCalsDone)
1508 chan->oneTimeCalsDone = true;
1513 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1514 bool bChannelChange)
1516 struct ath_common *common = ath9k_hw_common(ah);
1518 struct ath9k_channel *curchan = ah->curchan;
1524 ah->txchainmask = common->tx_chainmask;
1525 ah->rxchainmask = common->rx_chainmask;
1527 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1530 if (curchan && !ah->chip_fullsleep)
1531 ath9k_hw_getnf(ah, curchan);
1533 if (bChannelChange &&
1534 (ah->chip_fullsleep != true) &&
1535 (ah->curchan != NULL) &&
1536 (chan->channel != ah->curchan->channel) &&
1537 ((chan->channelFlags & CHANNEL_ALL) ==
1538 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
1539 !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) ||
1540 IS_CHAN_A_5MHZ_SPACED(ah->curchan))) {
1542 if (ath9k_hw_channel_change(ah, chan)) {
1543 ath9k_hw_loadnf(ah, ah->curchan);
1544 ath9k_hw_start_nfcal(ah);
1549 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1550 if (saveDefAntenna == 0)
1553 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1555 /* For chips on which RTC reset is done, save TSF before it gets cleared */
1556 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1557 tsf = ath9k_hw_gettsf64(ah);
1559 saveLedState = REG_READ(ah, AR_CFG_LED) &
1560 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1561 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1563 ath9k_hw_mark_phy_inactive(ah);
1565 /* Only required on the first reset */
1566 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1568 AR9271_RESET_POWER_DOWN_CONTROL,
1569 AR9271_RADIO_RF_RST);
1573 if (!ath9k_hw_chip_reset(ah, chan)) {
1574 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
1578 /* Only required on the first reset */
1579 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1580 ah->htc_reset_init = false;
1582 AR9271_RESET_POWER_DOWN_CONTROL,
1583 AR9271_GATE_MAC_CTL);
1588 if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1589 ath9k_hw_settsf64(ah, tsf);
1591 if (AR_SREV_9280_10_OR_LATER(ah))
1592 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1594 r = ath9k_hw_process_ini(ah, chan);
1598 /* Setup MFP options for CCMP */
1599 if (AR_SREV_9280_20_OR_LATER(ah)) {
1600 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1601 * frames when constructing CCMP AAD. */
1602 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1604 ah->sw_mgmt_crypto = false;
1605 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1606 /* Disable hardware crypto for management frames */
1607 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1608 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1609 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1610 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1611 ah->sw_mgmt_crypto = true;
1613 ah->sw_mgmt_crypto = true;
1615 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1616 ath9k_hw_set_delta_slope(ah, chan);
1618 ath9k_hw_spur_mitigate_freq(ah, chan);
1619 ah->eep_ops->set_board_values(ah, chan);
1621 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1622 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
1624 | AR_STA_ID1_RTS_USE_DEF
1626 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
1627 | ah->sta_id1_defaults);
1628 ath9k_hw_set_operating_mode(ah, ah->opmode);
1630 ath_hw_setbssidmask(common);
1632 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1634 ath9k_hw_write_associd(ah);
1636 REG_WRITE(ah, AR_ISR, ~0);
1638 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1640 r = ath9k_hw_rf_set_freq(ah, chan);
1644 for (i = 0; i < AR_NUM_DCU; i++)
1645 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1648 for (i = 0; i < ah->caps.total_queues; i++)
1649 ath9k_hw_resettxqueue(ah, i);
1651 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
1652 ath9k_hw_init_qos(ah);
1654 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1655 ath9k_enable_rfkill(ah);
1657 ath9k_hw_init_global_settings(ah);
1659 if (AR_SREV_9287_12_OR_LATER(ah)) {
1660 REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
1661 AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
1662 REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
1663 AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
1664 REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
1665 AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
1667 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
1668 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
1670 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
1671 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
1672 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
1673 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
1675 if (AR_SREV_9287_12_OR_LATER(ah)) {
1676 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1677 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
1680 REG_WRITE(ah, AR_STA_ID1,
1681 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
1683 ath9k_hw_set_dma(ah);
1685 REG_WRITE(ah, AR_OBS, 8);
1687 if (ah->config.rx_intr_mitigation) {
1688 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1689 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1692 ath9k_hw_init_bb(ah, chan);
1694 if (!ath9k_hw_init_cal(ah, chan))
1697 ath9k_hw_restore_chainmask(ah);
1698 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1701 * For big endian systems turn on swapping for descriptors
1703 if (AR_SREV_9100(ah)) {
1705 mask = REG_READ(ah, AR_CFG);
1706 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1707 ath_print(common, ATH_DBG_RESET,
1708 "CFG Byte Swap Set 0x%x\n", mask);
1711 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1712 REG_WRITE(ah, AR_CFG, mask);
1713 ath_print(common, ATH_DBG_RESET,
1714 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
1717 /* Configure AR9271 target WLAN */
1718 if (AR_SREV_9271(ah))
1719 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1722 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1726 if (ah->btcoex_hw.enabled)
1727 ath9k_hw_btcoex_enable(ah);
1731 EXPORT_SYMBOL(ath9k_hw_reset);
1733 /************************/
1734 /* Key Cache Management */
1735 /************************/
1737 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
1741 if (entry >= ah->caps.keycache_size) {
1742 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1743 "keychache entry %u out of range\n", entry);
1747 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
1749 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
1750 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
1751 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
1752 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
1753 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
1754 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
1755 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
1756 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
1758 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
1759 u16 micentry = entry + 64;
1761 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
1762 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
1763 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
1764 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
1770 EXPORT_SYMBOL(ath9k_hw_keyreset);
1772 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
1776 if (entry >= ah->caps.keycache_size) {
1777 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1778 "keychache entry %u out of range\n", entry);
1783 macHi = (mac[5] << 8) | mac[4];
1784 macLo = (mac[3] << 24) |
1789 macLo |= (macHi & 1) << 31;
1794 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
1795 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
1799 EXPORT_SYMBOL(ath9k_hw_keysetmac);
1801 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
1802 const struct ath9k_keyval *k,
1805 const struct ath9k_hw_capabilities *pCap = &ah->caps;
1806 struct ath_common *common = ath9k_hw_common(ah);
1807 u32 key0, key1, key2, key3, key4;
1810 if (entry >= pCap->keycache_size) {
1811 ath_print(common, ATH_DBG_FATAL,
1812 "keycache entry %u out of range\n", entry);
1816 switch (k->kv_type) {
1817 case ATH9K_CIPHER_AES_OCB:
1818 keyType = AR_KEYTABLE_TYPE_AES;
1820 case ATH9K_CIPHER_AES_CCM:
1821 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
1822 ath_print(common, ATH_DBG_ANY,
1823 "AES-CCM not supported by mac rev 0x%x\n",
1824 ah->hw_version.macRev);
1827 keyType = AR_KEYTABLE_TYPE_CCM;
1829 case ATH9K_CIPHER_TKIP:
1830 keyType = AR_KEYTABLE_TYPE_TKIP;
1831 if (ATH9K_IS_MIC_ENABLED(ah)
1832 && entry + 64 >= pCap->keycache_size) {
1833 ath_print(common, ATH_DBG_ANY,
1834 "entry %u inappropriate for TKIP\n", entry);
1838 case ATH9K_CIPHER_WEP:
1839 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
1840 ath_print(common, ATH_DBG_ANY,
1841 "WEP key length %u too small\n", k->kv_len);
1844 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
1845 keyType = AR_KEYTABLE_TYPE_40;
1846 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
1847 keyType = AR_KEYTABLE_TYPE_104;
1849 keyType = AR_KEYTABLE_TYPE_128;
1851 case ATH9K_CIPHER_CLR:
1852 keyType = AR_KEYTABLE_TYPE_CLR;
1855 ath_print(common, ATH_DBG_FATAL,
1856 "cipher %u not supported\n", k->kv_type);
1860 key0 = get_unaligned_le32(k->kv_val + 0);
1861 key1 = get_unaligned_le16(k->kv_val + 4);
1862 key2 = get_unaligned_le32(k->kv_val + 6);
1863 key3 = get_unaligned_le16(k->kv_val + 10);
1864 key4 = get_unaligned_le32(k->kv_val + 12);
1865 if (k->kv_len <= WLAN_KEY_LEN_WEP104)
1869 * Note: Key cache registers access special memory area that requires
1870 * two 32-bit writes to actually update the values in the internal
1871 * memory. Consequently, the exact order and pairs used here must be
1875 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
1876 u16 micentry = entry + 64;
1879 * Write inverted key[47:0] first to avoid Michael MIC errors
1880 * on frames that could be sent or received at the same time.
1881 * The correct key will be written in the end once everything
1884 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
1885 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
1887 /* Write key[95:48] */
1888 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
1889 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
1891 /* Write key[127:96] and key type */
1892 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
1893 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
1895 /* Write MAC address for the entry */
1896 (void) ath9k_hw_keysetmac(ah, entry, mac);
1898 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
1900 * TKIP uses two key cache entries:
1901 * Michael MIC TX/RX keys in the same key cache entry
1902 * (idx = main index + 64):
1903 * key0 [31:0] = RX key [31:0]
1904 * key1 [15:0] = TX key [31:16]
1905 * key1 [31:16] = reserved
1906 * key2 [31:0] = RX key [63:32]
1907 * key3 [15:0] = TX key [15:0]
1908 * key3 [31:16] = reserved
1909 * key4 [31:0] = TX key [63:32]
1911 u32 mic0, mic1, mic2, mic3, mic4;
1913 mic0 = get_unaligned_le32(k->kv_mic + 0);
1914 mic2 = get_unaligned_le32(k->kv_mic + 4);
1915 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
1916 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
1917 mic4 = get_unaligned_le32(k->kv_txmic + 4);
1919 /* Write RX[31:0] and TX[31:16] */
1920 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
1921 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
1923 /* Write RX[63:32] and TX[15:0] */
1924 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
1925 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
1927 /* Write TX[63:32] and keyType(reserved) */
1928 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
1929 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
1930 AR_KEYTABLE_TYPE_CLR);
1934 * TKIP uses four key cache entries (two for group
1936 * Michael MIC TX/RX keys are in different key cache
1937 * entries (idx = main index + 64 for TX and
1938 * main index + 32 + 96 for RX):
1939 * key0 [31:0] = TX/RX MIC key [31:0]
1940 * key1 [31:0] = reserved
1941 * key2 [31:0] = TX/RX MIC key [63:32]
1942 * key3 [31:0] = reserved
1943 * key4 [31:0] = reserved
1945 * Upper layer code will call this function separately
1946 * for TX and RX keys when these registers offsets are
1951 mic0 = get_unaligned_le32(k->kv_mic + 0);
1952 mic2 = get_unaligned_le32(k->kv_mic + 4);
1954 /* Write MIC key[31:0] */
1955 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
1956 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
1958 /* Write MIC key[63:32] */
1959 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
1960 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
1962 /* Write TX[63:32] and keyType(reserved) */
1963 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
1964 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
1965 AR_KEYTABLE_TYPE_CLR);
1968 /* MAC address registers are reserved for the MIC entry */
1969 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
1970 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
1973 * Write the correct (un-inverted) key[47:0] last to enable
1974 * TKIP now that all other registers are set with correct
1977 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
1978 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
1980 /* Write key[47:0] */
1981 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
1982 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
1984 /* Write key[95:48] */
1985 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
1986 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
1988 /* Write key[127:96] and key type */
1989 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
1990 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
1992 /* Write MAC address for the entry */
1993 (void) ath9k_hw_keysetmac(ah, entry, mac);
1998 EXPORT_SYMBOL(ath9k_hw_set_keycache_entry);
2000 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
2002 if (entry < ah->caps.keycache_size) {
2003 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2004 if (val & AR_KEYTABLE_VALID)
2009 EXPORT_SYMBOL(ath9k_hw_keyisvalid);
2011 /******************************/
2012 /* Power Management (Chipset) */
2013 /******************************/
2016 * Notify Power Mgt is disabled in self-generated frames.
2017 * If requested, force chip to sleep.
2019 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2021 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2024 * Clear the RTC force wake bit to allow the
2025 * mac to go to sleep.
2027 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2028 AR_RTC_FORCE_WAKE_EN);
2029 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
2030 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2032 /* Shutdown chip. Active low */
2033 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
2034 REG_CLR_BIT(ah, (AR_RTC_RESET),
2039 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2041 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2043 struct ath9k_hw_capabilities *pCap = &ah->caps;
2045 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2046 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2047 AR_RTC_FORCE_WAKE_ON_INT);
2049 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2050 AR_RTC_FORCE_WAKE_EN);
2055 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2061 if ((REG_READ(ah, AR_RTC_STATUS) &
2062 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2063 if (ath9k_hw_set_reset_reg(ah,
2064 ATH9K_RESET_POWER_ON) != true) {
2067 if (!AR_SREV_9300_20_OR_LATER(ah))
2068 ath9k_hw_init_pll(ah, NULL);
2070 if (AR_SREV_9100(ah))
2071 REG_SET_BIT(ah, AR_RTC_RESET,
2074 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2075 AR_RTC_FORCE_WAKE_EN);
2078 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2079 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2080 if (val == AR_RTC_STATUS_ON)
2083 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2084 AR_RTC_FORCE_WAKE_EN);
2087 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2088 "Failed to wakeup in %uus\n",
2089 POWER_UP_TIME / 20);
2094 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2099 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2101 struct ath_common *common = ath9k_hw_common(ah);
2102 int status = true, setChip = true;
2103 static const char *modes[] = {
2110 if (ah->power_mode == mode)
2113 ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
2114 modes[ah->power_mode], modes[mode]);
2117 case ATH9K_PM_AWAKE:
2118 status = ath9k_hw_set_power_awake(ah, setChip);
2120 case ATH9K_PM_FULL_SLEEP:
2121 ath9k_set_power_sleep(ah, setChip);
2122 ah->chip_fullsleep = true;
2124 case ATH9K_PM_NETWORK_SLEEP:
2125 ath9k_set_power_network_sleep(ah, setChip);
2128 ath_print(common, ATH_DBG_FATAL,
2129 "Unknown power mode %u\n", mode);
2132 ah->power_mode = mode;
2136 EXPORT_SYMBOL(ath9k_hw_setpower);
2139 * Helper for ASPM support.
2141 * Disable PLL when in L0s as well as receiver clock when in L1.
2142 * This power saving option must be enabled through the SerDes.
2144 * Programming the SerDes must go through the same 288 bit serial shift
2145 * register as the other analog registers. Hence the 9 writes.
2147 static void ar9002_hw_configpcipowersave(struct ath_hw *ah,
2154 if (ah->is_pciexpress != true)
2157 /* Do not touch SerDes registers */
2158 if (ah->config.pcie_powersave_enable == 2)
2161 /* Nothing to do on restore for 11N */
2163 if (AR_SREV_9280_20_OR_LATER(ah)) {
2165 * AR9280 2.0 or later chips use SerDes values from the
2166 * initvals.h initialized depending on chipset during
2169 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
2170 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
2171 INI_RA(&ah->iniPcieSerdes, i, 1));
2173 } else if (AR_SREV_9280(ah) &&
2174 (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
2175 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2176 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2178 /* RX shut off when elecidle is asserted */
2179 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2180 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2181 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2183 /* Shut off CLKREQ active in L1 */
2184 if (ah->config.pcie_clock_req)
2185 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2187 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2189 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2190 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2191 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2193 /* Load the new settings */
2194 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2197 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2198 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2200 /* RX shut off when elecidle is asserted */
2201 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2202 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2203 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2206 * Ignore ah->ah_config.pcie_clock_req setting for
2209 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2211 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2212 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2213 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2215 /* Load the new settings */
2216 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2221 /* set bit 19 to allow forcing of pcie core into L1 state */
2222 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2224 /* Several PCIe massages to ensure proper behaviour */
2225 if (ah->config.pcie_waen) {
2226 val = ah->config.pcie_waen;
2228 val &= (~AR_WA_D3_L1_DISABLE);
2230 if (AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
2232 val = AR9285_WA_DEFAULT;
2234 val &= (~AR_WA_D3_L1_DISABLE);
2235 } else if (AR_SREV_9280(ah)) {
2237 * On AR9280 chips bit 22 of 0x4004 needs to be
2238 * set otherwise card may disappear.
2240 val = AR9280_WA_DEFAULT;
2242 val &= (~AR_WA_D3_L1_DISABLE);
2244 val = AR_WA_DEFAULT;
2247 REG_WRITE(ah, AR_WA, val);
2252 * Set PCIe workaround bits
2253 * bit 14 in WA register (disable L1) should only
2254 * be set when device enters D3 and be cleared
2255 * when device comes back to D0.
2257 if (ah->config.pcie_waen) {
2258 if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
2259 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
2261 if (((AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
2262 AR_SREV_9287(ah)) &&
2263 (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||
2264 (AR_SREV_9280(ah) &&
2265 (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {
2266 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
2272 /**********************/
2273 /* Interrupt Handling */
2274 /**********************/
2276 bool ath9k_hw_intrpend(struct ath_hw *ah)
2280 if (AR_SREV_9100(ah))
2283 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
2284 if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
2287 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
2288 if ((host_isr & AR_INTR_SYNC_DEFAULT)
2289 && (host_isr != AR_INTR_SPURIOUS))
2294 EXPORT_SYMBOL(ath9k_hw_intrpend);
2296 bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
2300 struct ath9k_hw_capabilities *pCap = &ah->caps;
2302 bool fatal_int = false;
2303 struct ath_common *common = ath9k_hw_common(ah);
2305 if (!AR_SREV_9100(ah)) {
2306 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
2307 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
2308 == AR_RTC_STATUS_ON) {
2309 isr = REG_READ(ah, AR_ISR);
2313 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
2314 AR_INTR_SYNC_DEFAULT;
2318 if (!isr && !sync_cause)
2322 isr = REG_READ(ah, AR_ISR);
2326 if (isr & AR_ISR_BCNMISC) {
2328 isr2 = REG_READ(ah, AR_ISR_S2);
2329 if (isr2 & AR_ISR_S2_TIM)
2330 mask2 |= ATH9K_INT_TIM;
2331 if (isr2 & AR_ISR_S2_DTIM)
2332 mask2 |= ATH9K_INT_DTIM;
2333 if (isr2 & AR_ISR_S2_DTIMSYNC)
2334 mask2 |= ATH9K_INT_DTIMSYNC;
2335 if (isr2 & (AR_ISR_S2_CABEND))
2336 mask2 |= ATH9K_INT_CABEND;
2337 if (isr2 & AR_ISR_S2_GTT)
2338 mask2 |= ATH9K_INT_GTT;
2339 if (isr2 & AR_ISR_S2_CST)
2340 mask2 |= ATH9K_INT_CST;
2341 if (isr2 & AR_ISR_S2_TSFOOR)
2342 mask2 |= ATH9K_INT_TSFOOR;
2345 isr = REG_READ(ah, AR_ISR_RAC);
2346 if (isr == 0xffffffff) {
2351 *masked = isr & ATH9K_INT_COMMON;
2353 if (ah->config.rx_intr_mitigation) {
2354 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2355 *masked |= ATH9K_INT_RX;
2358 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
2359 *masked |= ATH9K_INT_RX;
2361 (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
2365 *masked |= ATH9K_INT_TX;
2367 s0_s = REG_READ(ah, AR_ISR_S0_S);
2368 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2369 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
2371 s1_s = REG_READ(ah, AR_ISR_S1_S);
2372 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2373 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
2376 if (isr & AR_ISR_RXORN) {
2377 ath_print(common, ATH_DBG_INTERRUPT,
2378 "receive FIFO overrun interrupt\n");
2381 if (!AR_SREV_9100(ah)) {
2382 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2383 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
2384 if (isr5 & AR_ISR_S5_TIM_TIMER)
2385 *masked |= ATH9K_INT_TIM_TIMER;
2392 if (AR_SREV_9100(ah))
2395 if (isr & AR_ISR_GENTMR) {
2398 s5_s = REG_READ(ah, AR_ISR_S5_S);
2399 if (isr & AR_ISR_GENTMR) {
2400 ah->intr_gen_timer_trigger =
2401 MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
2403 ah->intr_gen_timer_thresh =
2404 MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
2406 if (ah->intr_gen_timer_trigger)
2407 *masked |= ATH9K_INT_GENTIMER;
2415 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
2419 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
2420 ath_print(common, ATH_DBG_ANY,
2421 "received PCI FATAL interrupt\n");
2423 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
2424 ath_print(common, ATH_DBG_ANY,
2425 "received PCI PERR interrupt\n");
2427 *masked |= ATH9K_INT_FATAL;
2429 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
2430 ath_print(common, ATH_DBG_INTERRUPT,
2431 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
2432 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
2433 REG_WRITE(ah, AR_RC, 0);
2434 *masked |= ATH9K_INT_FATAL;
2436 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
2437 ath_print(common, ATH_DBG_INTERRUPT,
2438 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
2441 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
2442 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
2447 EXPORT_SYMBOL(ath9k_hw_getisr);
2449 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
2451 enum ath9k_int omask = ah->imask;
2453 struct ath9k_hw_capabilities *pCap = &ah->caps;
2454 struct ath_common *common = ath9k_hw_common(ah);
2456 ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
2458 if (omask & ATH9K_INT_GLOBAL) {
2459 ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n");
2460 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
2461 (void) REG_READ(ah, AR_IER);
2462 if (!AR_SREV_9100(ah)) {
2463 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
2464 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
2466 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
2467 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
2471 mask = ints & ATH9K_INT_COMMON;
2474 if (ints & ATH9K_INT_TX) {
2475 if (ah->txok_interrupt_mask)
2476 mask |= AR_IMR_TXOK;
2477 if (ah->txdesc_interrupt_mask)
2478 mask |= AR_IMR_TXDESC;
2479 if (ah->txerr_interrupt_mask)
2480 mask |= AR_IMR_TXERR;
2481 if (ah->txeol_interrupt_mask)
2482 mask |= AR_IMR_TXEOL;
2484 if (ints & ATH9K_INT_RX) {
2485 mask |= AR_IMR_RXERR;
2486 if (ah->config.rx_intr_mitigation)
2487 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
2489 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
2490 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
2491 mask |= AR_IMR_GENTMR;
2494 if (ints & (ATH9K_INT_BMISC)) {
2495 mask |= AR_IMR_BCNMISC;
2496 if (ints & ATH9K_INT_TIM)
2497 mask2 |= AR_IMR_S2_TIM;
2498 if (ints & ATH9K_INT_DTIM)
2499 mask2 |= AR_IMR_S2_DTIM;
2500 if (ints & ATH9K_INT_DTIMSYNC)
2501 mask2 |= AR_IMR_S2_DTIMSYNC;
2502 if (ints & ATH9K_INT_CABEND)
2503 mask2 |= AR_IMR_S2_CABEND;
2504 if (ints & ATH9K_INT_TSFOOR)
2505 mask2 |= AR_IMR_S2_TSFOOR;
2508 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
2509 mask |= AR_IMR_BCNMISC;
2510 if (ints & ATH9K_INT_GTT)
2511 mask2 |= AR_IMR_S2_GTT;
2512 if (ints & ATH9K_INT_CST)
2513 mask2 |= AR_IMR_S2_CST;
2516 ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
2517 REG_WRITE(ah, AR_IMR, mask);
2518 ah->imrs2_reg &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC |
2519 AR_IMR_S2_CABEND | AR_IMR_S2_CABTO |
2520 AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST);
2521 ah->imrs2_reg |= mask2;
2522 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
2524 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2525 if (ints & ATH9K_INT_TIM_TIMER)
2526 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2528 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2531 if (ints & ATH9K_INT_GLOBAL) {
2532 ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n");
2533 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
2534 if (!AR_SREV_9100(ah)) {
2535 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
2537 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
2540 REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
2541 AR_INTR_SYNC_DEFAULT);
2542 REG_WRITE(ah, AR_INTR_SYNC_MASK,
2543 AR_INTR_SYNC_DEFAULT);
2545 ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
2546 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
2551 EXPORT_SYMBOL(ath9k_hw_set_interrupts);
2553 /*******************/
2554 /* Beacon Handling */
2555 /*******************/
2557 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
2561 ah->beacon_interval = beacon_period;
2563 switch (ah->opmode) {
2564 case NL80211_IFTYPE_STATION:
2565 case NL80211_IFTYPE_MONITOR:
2566 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
2567 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
2568 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
2569 flags |= AR_TBTT_TIMER_EN;
2571 case NL80211_IFTYPE_ADHOC:
2572 case NL80211_IFTYPE_MESH_POINT:
2573 REG_SET_BIT(ah, AR_TXCFG,
2574 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
2575 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
2576 TU_TO_USEC(next_beacon +
2577 (ah->atim_window ? ah->
2579 flags |= AR_NDP_TIMER_EN;
2580 case NL80211_IFTYPE_AP:
2581 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
2582 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
2583 TU_TO_USEC(next_beacon -
2585 dma_beacon_response_time));
2586 REG_WRITE(ah, AR_NEXT_SWBA,
2587 TU_TO_USEC(next_beacon -
2589 sw_beacon_response_time));
2591 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
2594 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
2595 "%s: unsupported opmode: %d\n",
2596 __func__, ah->opmode);
2601 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
2602 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
2603 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
2604 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
2606 beacon_period &= ~ATH9K_BEACON_ENA;
2607 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
2608 ath9k_hw_reset_tsf(ah);
2611 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
2613 EXPORT_SYMBOL(ath9k_hw_beaconinit);
2615 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
2616 const struct ath9k_beacon_state *bs)
2618 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2619 struct ath9k_hw_capabilities *pCap = &ah->caps;
2620 struct ath_common *common = ath9k_hw_common(ah);
2622 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
2624 REG_WRITE(ah, AR_BEACON_PERIOD,
2625 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
2626 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
2627 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
2629 REG_RMW_FIELD(ah, AR_RSSI_THR,
2630 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
2632 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
2634 if (bs->bs_sleepduration > beaconintval)
2635 beaconintval = bs->bs_sleepduration;
2637 dtimperiod = bs->bs_dtimperiod;
2638 if (bs->bs_sleepduration > dtimperiod)
2639 dtimperiod = bs->bs_sleepduration;
2641 if (beaconintval == dtimperiod)
2642 nextTbtt = bs->bs_nextdtim;
2644 nextTbtt = bs->bs_nexttbtt;
2646 ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
2647 ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
2648 ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
2649 ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
2651 REG_WRITE(ah, AR_NEXT_DTIM,
2652 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
2653 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
2655 REG_WRITE(ah, AR_SLEEP1,
2656 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
2657 | AR_SLEEP1_ASSUME_DTIM);
2659 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
2660 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
2662 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
2664 REG_WRITE(ah, AR_SLEEP2,
2665 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
2667 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
2668 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
2670 REG_SET_BIT(ah, AR_TIMER_MODE,
2671 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
2674 /* TSF Out of Range Threshold */
2675 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
2677 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
2679 /*******************/
2680 /* HW Capabilities */
2681 /*******************/
2683 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
2685 struct ath9k_hw_capabilities *pCap = &ah->caps;
2686 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2687 struct ath_common *common = ath9k_hw_common(ah);
2688 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
2690 u16 capField = 0, eeval;
2692 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
2693 regulatory->current_rd = eeval;
2695 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
2696 if (AR_SREV_9285_10_OR_LATER(ah))
2697 eeval |= AR9285_RDEXT_DEFAULT;
2698 regulatory->current_rd_ext = eeval;
2700 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
2702 if (ah->opmode != NL80211_IFTYPE_AP &&
2703 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
2704 if (regulatory->current_rd == 0x64 ||
2705 regulatory->current_rd == 0x65)
2706 regulatory->current_rd += 5;
2707 else if (regulatory->current_rd == 0x41)
2708 regulatory->current_rd = 0x43;
2709 ath_print(common, ATH_DBG_REGULATORY,
2710 "regdomain mapped to 0x%x\n", regulatory->current_rd);
2713 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
2714 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
2715 ath_print(common, ATH_DBG_FATAL,
2716 "no band has been marked as supported in EEPROM.\n");
2720 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
2722 if (eeval & AR5416_OPFLAGS_11A) {
2723 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
2724 if (ah->config.ht_enable) {
2725 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
2726 set_bit(ATH9K_MODE_11NA_HT20,
2727 pCap->wireless_modes);
2728 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
2729 set_bit(ATH9K_MODE_11NA_HT40PLUS,
2730 pCap->wireless_modes);
2731 set_bit(ATH9K_MODE_11NA_HT40MINUS,
2732 pCap->wireless_modes);
2737 if (eeval & AR5416_OPFLAGS_11G) {
2738 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
2739 if (ah->config.ht_enable) {
2740 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
2741 set_bit(ATH9K_MODE_11NG_HT20,
2742 pCap->wireless_modes);
2743 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
2744 set_bit(ATH9K_MODE_11NG_HT40PLUS,
2745 pCap->wireless_modes);
2746 set_bit(ATH9K_MODE_11NG_HT40MINUS,
2747 pCap->wireless_modes);
2752 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
2754 * For AR9271 we will temporarilly uses the rx chainmax as read from
2757 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
2758 !(eeval & AR5416_OPFLAGS_11A) &&
2759 !(AR_SREV_9271(ah)))
2760 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
2761 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
2763 /* Use rx_chainmask from EEPROM. */
2764 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
2766 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
2767 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
2769 pCap->low_2ghz_chan = 2312;
2770 pCap->high_2ghz_chan = 2732;
2772 pCap->low_5ghz_chan = 4920;
2773 pCap->high_5ghz_chan = 6100;
2775 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
2776 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
2777 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
2779 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
2780 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
2781 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
2783 if (ah->config.ht_enable)
2784 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2786 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
2788 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
2789 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
2790 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
2791 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
2793 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
2794 pCap->total_queues =
2795 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
2797 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
2799 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
2800 pCap->keycache_size =
2801 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
2803 pCap->keycache_size = AR_KEYTABLE_SIZE;
2805 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
2807 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2808 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
2810 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
2812 if (AR_SREV_9271(ah))
2813 pCap->num_gpio_pins = AR9271_NUM_GPIO;
2814 else if (AR_SREV_9285_10_OR_LATER(ah))
2815 pCap->num_gpio_pins = AR9285_NUM_GPIO;
2816 else if (AR_SREV_9280_10_OR_LATER(ah))
2817 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2819 pCap->num_gpio_pins = AR_NUM_GPIO;
2821 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
2822 pCap->hw_caps |= ATH9K_HW_CAP_CST;
2823 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
2825 pCap->rts_aggr_limit = (8 * 1024);
2828 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
2830 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2831 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2832 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2834 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2835 ah->rfkill_polarity =
2836 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
2838 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
2841 if (AR_SREV_9271(ah))
2842 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2844 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
2846 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
2847 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2849 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
2851 if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
2853 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
2854 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
2855 AR_EEPROM_EEREGCAP_EN_KK_U2 |
2856 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
2859 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
2860 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
2863 /* Advertise midband for AR5416 with FCC midband set in eeprom */
2864 if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
2866 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
2868 pCap->num_antcfg_5ghz =
2869 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
2870 pCap->num_antcfg_2ghz =
2871 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
2873 if (AR_SREV_9280_10_OR_LATER(ah) &&
2874 ath9k_hw_btcoex_supported(ah)) {
2875 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
2876 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
2878 if (AR_SREV_9285(ah)) {
2879 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
2880 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
2882 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
2885 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
2891 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
2892 u32 capability, u32 *result)
2894 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2896 case ATH9K_CAP_CIPHER:
2897 switch (capability) {
2898 case ATH9K_CIPHER_AES_CCM:
2899 case ATH9K_CIPHER_AES_OCB:
2900 case ATH9K_CIPHER_TKIP:
2901 case ATH9K_CIPHER_WEP:
2902 case ATH9K_CIPHER_MIC:
2903 case ATH9K_CIPHER_CLR:
2908 case ATH9K_CAP_TKIP_MIC:
2909 switch (capability) {
2913 return (ah->sta_id1_defaults &
2914 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
2917 case ATH9K_CAP_TKIP_SPLIT:
2918 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
2920 case ATH9K_CAP_MCAST_KEYSRCH:
2921 switch (capability) {
2925 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
2928 return (ah->sta_id1_defaults &
2929 AR_STA_ID1_MCAST_KSRCH) ? true :
2934 case ATH9K_CAP_TXPOW:
2935 switch (capability) {
2939 *result = regulatory->power_limit;
2942 *result = regulatory->max_power_level;
2945 *result = regulatory->tp_scale;
2950 return (AR_SREV_9280_20_OR_LATER(ah) &&
2951 (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
2957 EXPORT_SYMBOL(ath9k_hw_getcapability);
2959 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
2960 u32 capability, u32 setting, int *status)
2963 case ATH9K_CAP_TKIP_MIC:
2965 ah->sta_id1_defaults |=
2966 AR_STA_ID1_CRPT_MIC_ENABLE;
2968 ah->sta_id1_defaults &=
2969 ~AR_STA_ID1_CRPT_MIC_ENABLE;
2971 case ATH9K_CAP_MCAST_KEYSRCH:
2973 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
2975 ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
2981 EXPORT_SYMBOL(ath9k_hw_setcapability);
2983 /****************************/
2984 /* GPIO / RFKILL / Antennae */
2985 /****************************/
2987 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
2991 u32 gpio_shift, tmp;
2994 addr = AR_GPIO_OUTPUT_MUX3;
2996 addr = AR_GPIO_OUTPUT_MUX2;
2998 addr = AR_GPIO_OUTPUT_MUX1;
3000 gpio_shift = (gpio % 6) * 5;
3002 if (AR_SREV_9280_20_OR_LATER(ah)
3003 || (addr != AR_GPIO_OUTPUT_MUX1)) {
3004 REG_RMW(ah, addr, (type << gpio_shift),
3005 (0x1f << gpio_shift));
3007 tmp = REG_READ(ah, addr);
3008 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3009 tmp &= ~(0x1f << gpio_shift);
3010 tmp |= (type << gpio_shift);
3011 REG_WRITE(ah, addr, tmp);
3015 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
3019 BUG_ON(gpio >= ah->caps.num_gpio_pins);
3021 gpio_shift = gpio << 1;
3025 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3026 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3028 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
3030 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3032 #define MS_REG_READ(x, y) \
3033 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3035 if (gpio >= ah->caps.num_gpio_pins)
3038 if (AR_SREV_9300_20_OR_LATER(ah))
3039 return MS_REG_READ(AR9300, gpio) != 0;
3040 else if (AR_SREV_9271(ah))
3041 return MS_REG_READ(AR9271, gpio) != 0;
3042 else if (AR_SREV_9287_10_OR_LATER(ah))
3043 return MS_REG_READ(AR9287, gpio) != 0;
3044 else if (AR_SREV_9285_10_OR_LATER(ah))
3045 return MS_REG_READ(AR9285, gpio) != 0;
3046 else if (AR_SREV_9280_10_OR_LATER(ah))
3047 return MS_REG_READ(AR928X, gpio) != 0;
3049 return MS_REG_READ(AR, gpio) != 0;
3051 EXPORT_SYMBOL(ath9k_hw_gpio_get);
3053 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
3058 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3060 gpio_shift = 2 * gpio;
3064 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3065 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3067 EXPORT_SYMBOL(ath9k_hw_cfg_output);
3069 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
3071 if (AR_SREV_9271(ah))
3074 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3077 EXPORT_SYMBOL(ath9k_hw_set_gpio);
3079 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
3081 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3083 EXPORT_SYMBOL(ath9k_hw_getdefantenna);
3085 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
3087 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3089 EXPORT_SYMBOL(ath9k_hw_setantenna);
3091 /*********************/
3092 /* General Operation */
3093 /*********************/
3095 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
3097 u32 bits = REG_READ(ah, AR_RX_FILTER);
3098 u32 phybits = REG_READ(ah, AR_PHY_ERR);
3100 if (phybits & AR_PHY_ERR_RADAR)
3101 bits |= ATH9K_RX_FILTER_PHYRADAR;
3102 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3103 bits |= ATH9K_RX_FILTER_PHYERR;
3107 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
3109 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
3113 REG_WRITE(ah, AR_RX_FILTER, bits);
3116 if (bits & ATH9K_RX_FILTER_PHYRADAR)
3117 phybits |= AR_PHY_ERR_RADAR;
3118 if (bits & ATH9K_RX_FILTER_PHYERR)
3119 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3120 REG_WRITE(ah, AR_PHY_ERR, phybits);
3123 REG_WRITE(ah, AR_RXCFG,
3124 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3126 REG_WRITE(ah, AR_RXCFG,
3127 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3129 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
3131 bool ath9k_hw_phy_disable(struct ath_hw *ah)
3133 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
3136 ath9k_hw_init_pll(ah, NULL);
3139 EXPORT_SYMBOL(ath9k_hw_phy_disable);
3141 bool ath9k_hw_disable(struct ath_hw *ah)
3143 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3146 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
3149 ath9k_hw_init_pll(ah, NULL);
3152 EXPORT_SYMBOL(ath9k_hw_disable);
3154 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
3156 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3157 struct ath9k_channel *chan = ah->curchan;
3158 struct ieee80211_channel *channel = chan->chan;
3160 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
3162 ah->eep_ops->set_txpower(ah, chan,
3163 ath9k_regd_get_ctl(regulatory, chan),
3164 channel->max_antenna_gain * 2,
3165 channel->max_power * 2,
3166 min((u32) MAX_RATE_POWER,
3167 (u32) regulatory->power_limit));
3169 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
3171 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
3173 memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN);
3175 EXPORT_SYMBOL(ath9k_hw_setmac);
3177 void ath9k_hw_setopmode(struct ath_hw *ah)
3179 ath9k_hw_set_operating_mode(ah, ah->opmode);
3181 EXPORT_SYMBOL(ath9k_hw_setopmode);
3183 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
3185 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3186 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3188 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
3190 void ath9k_hw_write_associd(struct ath_hw *ah)
3192 struct ath_common *common = ath9k_hw_common(ah);
3194 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
3195 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
3196 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
3198 EXPORT_SYMBOL(ath9k_hw_write_associd);
3200 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
3204 tsf = REG_READ(ah, AR_TSF_U32);
3205 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
3209 EXPORT_SYMBOL(ath9k_hw_gettsf64);
3211 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
3213 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
3214 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
3216 EXPORT_SYMBOL(ath9k_hw_settsf64);
3218 void ath9k_hw_reset_tsf(struct ath_hw *ah)
3220 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
3221 AH_TSF_WRITE_TIMEOUT))
3222 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
3223 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3225 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3227 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
3229 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
3232 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
3234 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
3236 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
3239 * Extend 15-bit time stamp from rx descriptor to
3240 * a full 64-bit TSF using the current h/w TSF.
3242 u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp)
3246 tsf = ath9k_hw_gettsf64(ah);
3247 if ((tsf & 0x7fff) < rstamp)
3249 return (tsf & ~0x7fff) | rstamp;
3251 EXPORT_SYMBOL(ath9k_hw_extend_tsf);
3253 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
3255 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
3258 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
3259 macmode = AR_2040_JOINED_RX_CLEAR;
3263 REG_WRITE(ah, AR_2040_MODE, macmode);
3266 /* HW Generic timers configuration */
3268 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
3270 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3271 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3272 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3273 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3274 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3275 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3276 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3277 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3278 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
3279 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
3280 AR_NDP2_TIMER_MODE, 0x0002},
3281 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
3282 AR_NDP2_TIMER_MODE, 0x0004},
3283 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
3284 AR_NDP2_TIMER_MODE, 0x0008},
3285 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
3286 AR_NDP2_TIMER_MODE, 0x0010},
3287 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
3288 AR_NDP2_TIMER_MODE, 0x0020},
3289 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
3290 AR_NDP2_TIMER_MODE, 0x0040},
3291 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
3292 AR_NDP2_TIMER_MODE, 0x0080}
3295 /* HW generic timer primitives */
3297 /* compute and clear index of rightmost 1 */
3298 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
3308 return timer_table->gen_timer_index[b];
3311 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
3313 return REG_READ(ah, AR_TSF_L32);
3315 EXPORT_SYMBOL(ath9k_hw_gettsf32);
3317 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
3318 void (*trigger)(void *),
3319 void (*overflow)(void *),
3323 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3324 struct ath_gen_timer *timer;
3326 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
3328 if (timer == NULL) {
3329 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
3330 "Failed to allocate memory"
3331 "for hw timer[%d]\n", timer_index);
3335 /* allocate a hardware generic timer slot */
3336 timer_table->timers[timer_index] = timer;
3337 timer->index = timer_index;
3338 timer->trigger = trigger;
3339 timer->overflow = overflow;
3344 EXPORT_SYMBOL(ath_gen_timer_alloc);
3346 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
3347 struct ath_gen_timer *timer,
3351 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3354 BUG_ON(!timer_period);
3356 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
3358 tsf = ath9k_hw_gettsf32(ah);
3360 ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
3361 "curent tsf %x period %x"
3362 "timer_next %x\n", tsf, timer_period, timer_next);
3365 * Pull timer_next forward if the current TSF already passed it
3366 * because of software latency
3368 if (timer_next < tsf)
3369 timer_next = tsf + timer_period;
3372 * Program generic timer registers
3374 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
3376 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
3378 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3379 gen_tmr_configuration[timer->index].mode_mask);
3381 /* Enable both trigger and thresh interrupt masks */
3382 REG_SET_BIT(ah, AR_IMR_S5,
3383 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3384 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3386 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
3388 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
3390 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3392 if ((timer->index < AR_FIRST_NDP_TIMER) ||
3393 (timer->index >= ATH_MAX_GEN_TIMER)) {
3397 /* Clear generic timer enable bits. */
3398 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3399 gen_tmr_configuration[timer->index].mode_mask);
3401 /* Disable both trigger and thresh interrupt masks */
3402 REG_CLR_BIT(ah, AR_IMR_S5,
3403 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3404 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3406 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
3408 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
3410 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
3412 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3414 /* free the hardware generic timer slot */
3415 timer_table->timers[timer->index] = NULL;
3418 EXPORT_SYMBOL(ath_gen_timer_free);
3421 * Generic Timer Interrupts handling
3423 void ath_gen_timer_isr(struct ath_hw *ah)
3425 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3426 struct ath_gen_timer *timer;
3427 struct ath_common *common = ath9k_hw_common(ah);
3428 u32 trigger_mask, thresh_mask, index;
3430 /* get hardware generic timer interrupt status */
3431 trigger_mask = ah->intr_gen_timer_trigger;
3432 thresh_mask = ah->intr_gen_timer_thresh;
3433 trigger_mask &= timer_table->timer_mask.val;
3434 thresh_mask &= timer_table->timer_mask.val;
3436 trigger_mask &= ~thresh_mask;
3438 while (thresh_mask) {
3439 index = rightmost_index(timer_table, &thresh_mask);
3440 timer = timer_table->timers[index];
3442 ath_print(common, ATH_DBG_HWTIMER,
3443 "TSF overflow for Gen timer %d\n", index);
3444 timer->overflow(timer->arg);
3447 while (trigger_mask) {
3448 index = rightmost_index(timer_table, &trigger_mask);
3449 timer = timer_table->timers[index];
3451 ath_print(common, ATH_DBG_HWTIMER,
3452 "Gen timer[%d] trigger\n", index);
3453 timer->trigger(timer->arg);
3456 EXPORT_SYMBOL(ath_gen_timer_isr);
3462 void ath9k_hw_htc_resetinit(struct ath_hw *ah)
3464 ah->htc_reset_init = true;
3466 EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
3471 } ath_mac_bb_names[] = {
3472 /* Devices with external radios */
3473 { AR_SREV_VERSION_5416_PCI, "5416" },
3474 { AR_SREV_VERSION_5416_PCIE, "5418" },
3475 { AR_SREV_VERSION_9100, "9100" },
3476 { AR_SREV_VERSION_9160, "9160" },
3477 /* Single-chip solutions */
3478 { AR_SREV_VERSION_9280, "9280" },
3479 { AR_SREV_VERSION_9285, "9285" },
3480 { AR_SREV_VERSION_9287, "9287" },
3481 { AR_SREV_VERSION_9271, "9271" },
3484 /* For devices with external radios */
3488 } ath_rf_names[] = {
3490 { AR_RAD5133_SREV_MAJOR, "5133" },
3491 { AR_RAD5122_SREV_MAJOR, "5122" },
3492 { AR_RAD2133_SREV_MAJOR, "2133" },
3493 { AR_RAD2122_SREV_MAJOR, "2122" }
3497 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3499 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
3503 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3504 if (ath_mac_bb_names[i].version == mac_bb_version) {
3505 return ath_mac_bb_names[i].name;
3513 * Return the RF name. "????" is returned if the RF is unknown.
3514 * Used for devices with external radios.
3516 static const char *ath9k_hw_rf_name(u16 rf_version)
3520 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3521 if (ath_rf_names[i].version == rf_version) {
3522 return ath_rf_names[i].name;
3529 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3533 /* chipsets >= AR9280 are single-chip */
3534 if (AR_SREV_9280_10_OR_LATER(ah)) {
3535 used = snprintf(hw_name, len,
3536 "Atheros AR%s Rev:%x",
3537 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3538 ah->hw_version.macRev);
3541 used = snprintf(hw_name, len,
3542 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3543 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3544 ah->hw_version.macRev,
3545 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
3546 AR_RADIO_SREV_MAJOR)),
3547 ah->hw_version.phyRev);
3550 hw_name[used] = '\0';
3552 EXPORT_SYMBOL(ath9k_hw_name);
3554 /* Sets up the AR5008/AR9001/AR9002 hardware familiy callbacks */
3555 static void ar9002_hw_attach_ops(struct ath_hw *ah)
3557 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
3558 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
3560 priv_ops->init_cal_settings = ar9002_hw_init_cal_settings;
3561 priv_ops->init_mode_regs = ar9002_hw_init_mode_regs;
3562 priv_ops->macversion_supported = ar9002_hw_macversion_supported;
3564 ops->config_pci_powersave = ar9002_hw_configpcipowersave;
3566 if (AR_SREV_9280_10_OR_LATER(ah))
3567 ar9002_hw_attach_phy_ops(ah);
3569 ar5008_hw_attach_phy_ops(ah);