drivers/net/wireless/ath/ath9k/hw.c

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/io.h>
  18 #include <asm/unaligned.h>
  19
  20 #include "hw.h"
  21 #include "hw-ops.h"
  22 #include "rc.h"
  23 #include "ar5008_initvals.h"
  24 #include "ar9001_initvals.h"
  25 #include "ar9002_initvals.h"
  26 #include "ar9003_initvals.h"
  27
  28 #define ATH9K_CLOCK_RATE_CCK            22
  29 #define ATH9K_CLOCK_RATE_5GHZ_OFDM      40
  30 #define ATH9K_CLOCK_RATE_2GHZ_OFDM      44
  31
  32 static void ar9002_hw_attach_ops(struct ath_hw *ah);
  33 static void ar9003_hw_attach_ops(struct ath_hw *ah);
  34
  35 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
  36
  37 MODULE_AUTHOR("Atheros Communications");
  38 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  39 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  40 MODULE_LICENSE("Dual BSD/GPL");
  41
  42 static int __init ath9k_init(void)
  43 {
  44         return 0;
  45 }
  46 module_init(ath9k_init);
  47
  48 static void __exit ath9k_exit(void)
  49 {
  50         return;
  51 }
  52 module_exit(ath9k_exit);
  53
  54 /* Private hardware callbacks */
  55
  56 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
  57 {
  58         ath9k_hw_private_ops(ah)->init_cal_settings(ah);
  59 }
  60
  61 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
  62 {
  63         ath9k_hw_private_ops(ah)->init_mode_regs(ah);
  64 }
  65
  66 static bool ath9k_hw_macversion_supported(struct ath_hw *ah)
  67 {
  68         struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
  69
  70         return priv_ops->macversion_supported(ah->hw_version.macVersion);
  71 }
  72
  73 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
  74                                         struct ath9k_channel *chan)
  75 {
  76         return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
  77 }
  78
  79 /********************/
  80 /* Helper Functions */
  81 /********************/
  82
  83 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
  84 {
  85         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
  86
  87         if (!ah->curchan) /* should really check for CCK instead */
  88                 return usecs *ATH9K_CLOCK_RATE_CCK;
  89         if (conf->channel->band == IEEE80211_BAND_2GHZ)
  90                 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
  91         return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
  92 }
  93
  94 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
  95 {
  96         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
  97
  98         if (conf_is_ht40(conf))
  99                 return ath9k_hw_mac_clks(ah, usecs) * 2;
 100         else
 101                 return ath9k_hw_mac_clks(ah, usecs);
 102 }
 103
 104 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
 105 {
 106         int i;
 107
 108         BUG_ON(timeout < AH_TIME_QUANTUM);
 109
 110         for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
 111                 if ((REG_READ(ah, reg) & mask) == val)
 112                         return true;
 113
 114                 udelay(AH_TIME_QUANTUM);
 115         }
 116
 117         ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
 118                   "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
 119                   timeout, reg, REG_READ(ah, reg), mask, val);
 120
 121         return false;
 122 }
 123 EXPORT_SYMBOL(ath9k_hw_wait);
 124
 125 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
 126 {
 127         u32 retval;
 128         int i;
 129
 130         for (i = 0, retval = 0; i < n; i++) {
 131                 retval = (retval << 1) | (val & 1);
 132                 val >>= 1;
 133         }
 134         return retval;
 135 }
 136
 137 bool ath9k_get_channel_edges(struct ath_hw *ah,
 138                              u16 flags, u16 *low,
 139                              u16 *high)
 140 {
 141         struct ath9k_hw_capabilities *pCap = &ah->caps;
 142
 143         if (flags & CHANNEL_5GHZ) {
 144                 *low = pCap->low_5ghz_chan;
 145                 *high = pCap->high_5ghz_chan;
 146                 return true;
 147         }
 148         if ((flags & CHANNEL_2GHZ)) {
 149                 *low = pCap->low_2ghz_chan;
 150                 *high = pCap->high_2ghz_chan;
 151                 return true;
 152         }
 153         return false;
 154 }
 155
 156 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
 157                            u8 phy, int kbps,
 158                            u32 frameLen, u16 rateix,
 159                            bool shortPreamble)
 160 {
 161         u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
 162
 163         if (kbps == 0)
 164                 return 0;
 165
 166         switch (phy) {
 167         case WLAN_RC_PHY_CCK:
 168                 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
 169                 if (shortPreamble)
 170                         phyTime >>= 1;
 171                 numBits = frameLen << 3;
 172                 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
 173                 break;
 174         case WLAN_RC_PHY_OFDM:
 175                 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
 176                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
 177                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 178                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 179                         txTime = OFDM_SIFS_TIME_QUARTER
 180                                 + OFDM_PREAMBLE_TIME_QUARTER
 181                                 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
 182                 } else if (ah->curchan &&
 183                            IS_CHAN_HALF_RATE(ah->curchan)) {
 184                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
 185                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 186                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 187                         txTime = OFDM_SIFS_TIME_HALF +
 188                                 OFDM_PREAMBLE_TIME_HALF
 189                                 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
 190                 } else {
 191                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
 192                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 193                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 194                         txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
 195                                 + (numSymbols * OFDM_SYMBOL_TIME);
 196                 }
 197                 break;
 198         default:
 199                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
 200                           "Unknown phy %u (rate ix %u)\n", phy, rateix);
 201                 txTime = 0;
 202                 break;
 203         }
 204
 205         return txTime;
 206 }
 207 EXPORT_SYMBOL(ath9k_hw_computetxtime);
 208
 209 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
 210                                   struct ath9k_channel *chan,
 211                                   struct chan_centers *centers)
 212 {
 213         int8_t extoff;
 214
 215         if (!IS_CHAN_HT40(chan)) {
 216                 centers->ctl_center = centers->ext_center =
 217                         centers->synth_center = chan->channel;
 218                 return;
 219         }
 220
 221         if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
 222             (chan->chanmode == CHANNEL_G_HT40PLUS)) {
 223                 centers->synth_center =
 224                         chan->channel + HT40_CHANNEL_CENTER_SHIFT;
 225                 extoff = 1;
 226         } else {
 227                 centers->synth_center =
 228                         chan->channel - HT40_CHANNEL_CENTER_SHIFT;
 229                 extoff = -1;
 230         }
 231
 232         centers->ctl_center =
 233                 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
 234         /* 25 MHz spacing is supported by hw but not on upper layers */
 235         centers->ext_center =
 236                 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
 237 }
 238
 239 /******************/
 240 /* Chip Revisions */
 241 /******************/
 242
 243 static void ath9k_hw_read_revisions(struct ath_hw *ah)
 244 {
 245         u32 val;
 246
 247         val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
 248
 249         if (val == 0xFF) {
 250                 val = REG_READ(ah, AR_SREV);
 251                 ah->hw_version.macVersion =
 252                         (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
 253                 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
 254                 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
 255         } else {
 256                 if (!AR_SREV_9100(ah))
 257                         ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
 258
 259                 ah->hw_version.macRev = val & AR_SREV_REVISION;
 260
 261                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
 262                         ah->is_pciexpress = true;
 263         }
 264 }
 265
 266 static int ath9k_hw_get_radiorev(struct ath_hw *ah)
 267 {
 268         u32 val;
 269         int i;
 270
 271         REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
 272
 273         for (i = 0; i < 8; i++)
 274                 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
 275         val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
 276         val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
 277
 278         return ath9k_hw_reverse_bits(val, 8);
 279 }
 280
 281 /************************************/
 282 /* HW Attach, Detach, Init Routines */
 283 /************************************/
 284
 285 static void ath9k_hw_disablepcie(struct ath_hw *ah)
 286 {
 287         if (AR_SREV_9100(ah))
 288                 return;
 289
 290         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
 291         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
 292         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
 293         REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
 294         REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
 295         REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
 296         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
 297         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
 298         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
 299
 300         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
 301 }
 302
 303 /* This should work for all families including legacy */
 304 static bool ath9k_hw_chip_test(struct ath_hw *ah)
 305 {
 306         struct ath_common *common = ath9k_hw_common(ah);
 307         u32 regAddr[2] = { AR_STA_ID0 };
 308         u32 regHold[2];
 309         u32 patternData[4] = { 0x55555555,
 310                                0xaaaaaaaa,
 311                                0x66666666,
 312                                0x99999999 };
 313         int i, j, loop_max;
 314
 315         if (!AR_SREV_9300_20_OR_LATER(ah)) {
 316                 loop_max = 2;
 317                 regAddr[1] = AR_PHY_BASE + (8 << 2);
 318         } else
 319                 loop_max = 1;
 320
 321         for (i = 0; i < loop_max; i++) {
 322                 u32 addr = regAddr[i];
 323                 u32 wrData, rdData;
 324
 325                 regHold[i] = REG_READ(ah, addr);
 326                 for (j = 0; j < 0x100; j++) {
 327                         wrData = (j << 16) | j;
 328                         REG_WRITE(ah, addr, wrData);
 329                         rdData = REG_READ(ah, addr);
 330                         if (rdData != wrData) {
 331                                 ath_print(common, ATH_DBG_FATAL,
 332                                           "address test failed "
 333                                           "addr: 0x%08x - wr:0x%08x != "
 334                                           "rd:0x%08x\n",
 335                                           addr, wrData, rdData);
 336                                 return false;
 337                         }
 338                 }
 339                 for (j = 0; j < 4; j++) {
 340                         wrData = patternData[j];
 341                         REG_WRITE(ah, addr, wrData);
 342                         rdData = REG_READ(ah, addr);
 343                         if (wrData != rdData) {
 344                                 ath_print(common, ATH_DBG_FATAL,
 345                                           "address test failed "
 346                                           "addr: 0x%08x - wr:0x%08x != "
 347                                           "rd:0x%08x\n",
 348                                           addr, wrData, rdData);
 349                                 return false;
 350                         }
 351                 }
 352                 REG_WRITE(ah, regAddr[i], regHold[i]);
 353         }
 354         udelay(100);
 355
 356         return true;
 357 }
 358
 359 static void ath9k_hw_init_config(struct ath_hw *ah)
 360 {
 361         int i;
 362
 363         ah->config.dma_beacon_response_time = 2;
 364         ah->config.sw_beacon_response_time = 10;
 365         ah->config.additional_swba_backoff = 0;
 366         ah->config.ack_6mb = 0x0;
 367         ah->config.cwm_ignore_extcca = 0;
 368         ah->config.pcie_powersave_enable = 0;
 369         ah->config.pcie_clock_req = 0;
 370         ah->config.pcie_waen = 0;
 371         ah->config.analog_shiftreg = 1;
 372         ah->config.ofdm_trig_low = 200;
 373         ah->config.ofdm_trig_high = 500;
 374         ah->config.cck_trig_high = 200;
 375         ah->config.cck_trig_low = 100;
 376
 377         /*
 378          * For now ANI is disabled for AR9003, it is still
 379          * being tested.
 380          */
 381         if (!AR_SREV_9300_20_OR_LATER(ah))
 382                 ah->config.enable_ani = 1;
 383
 384         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
 385                 ah->config.spurchans[i][0] = AR_NO_SPUR;
 386                 ah->config.spurchans[i][1] = AR_NO_SPUR;
 387         }
 388
 389         if (ah->hw_version.devid != AR2427_DEVID_PCIE)
 390                 ah->config.ht_enable = 1;
 391         else
 392                 ah->config.ht_enable = 0;
 393
 394         ah->config.rx_intr_mitigation = true;
 395
 396         /*
 397          * We need this for PCI devices only (Cardbus, PCI, miniPCI)
 398          * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
 399          * This means we use it for all AR5416 devices, and the few
 400          * minor PCI AR9280 devices out there.
 401          *
 402          * Serialization is required because these devices do not handle
 403          * well the case of two concurrent reads/writes due to the latency
 404          * involved. During one read/write another read/write can be issued
 405          * on another CPU while the previous read/write may still be working
 406          * on our hardware, if we hit this case the hardware poops in a loop.
 407          * We prevent this by serializing reads and writes.
 408          *
 409          * This issue is not present on PCI-Express devices or pre-AR5416
 410          * devices (legacy, 802.11abg).
 411          */
 412         if (num_possible_cpus() > 1)
 413                 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
 414 }
 415
 416 static void ath9k_hw_init_defaults(struct ath_hw *ah)
 417 {
 418         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
 419
 420         regulatory->country_code = CTRY_DEFAULT;
 421         regulatory->power_limit = MAX_RATE_POWER;
 422         regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
 423
 424         ah->hw_version.magic = AR5416_MAGIC;
 425         ah->hw_version.subvendorid = 0;
 426
 427         ah->ah_flags = 0;
 428         if (!AR_SREV_9100(ah))
 429                 ah->ah_flags = AH_USE_EEPROM;
 430
 431         ah->atim_window = 0;
 432         ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
 433         ah->beacon_interval = 100;
 434         ah->enable_32kHz_clock = DONT_USE_32KHZ;
 435         ah->slottime = (u32) -1;
 436         ah->globaltxtimeout = (u32) -1;
 437         ah->power_mode = ATH9K_PM_UNDEFINED;
 438 }
 439
 440 static int ath9k_hw_rf_claim(struct ath_hw *ah)
 441 {
 442         u32 val;
 443
 444         REG_WRITE(ah, AR_PHY(0), 0x00000007);
 445
 446         val = ath9k_hw_get_radiorev(ah);
 447         switch (val & AR_RADIO_SREV_MAJOR) {
 448         case 0:
 449                 val = AR_RAD5133_SREV_MAJOR;
 450                 break;
 451         case AR_RAD5133_SREV_MAJOR:
 452         case AR_RAD5122_SREV_MAJOR:
 453         case AR_RAD2133_SREV_MAJOR:
 454         case AR_RAD2122_SREV_MAJOR:
 455                 break;
 456         default:
 457                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
 458                           "Radio Chip Rev 0x%02X not supported\n",
 459                           val & AR_RADIO_SREV_MAJOR);
 460                 return -EOPNOTSUPP;
 461         }
 462
 463         ah->hw_version.analog5GhzRev = val;
 464
 465         return 0;
 466 }
 467
 468 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
 469 {
 470         struct ath_common *common = ath9k_hw_common(ah);
 471         u32 sum;
 472         int i;
 473         u16 eeval;
 474
 475         sum = 0;
 476         for (i = 0; i < 3; i++) {
 477                 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
 478                 sum += eeval;
 479                 common->macaddr[2 * i] = eeval >> 8;
 480                 common->macaddr[2 * i + 1] = eeval & 0xff;
 481         }
 482         if (sum == 0 || sum == 0xffff * 3)
 483                 return -EADDRNOTAVAIL;
 484
 485         return 0;
 486 }
 487
 488 static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
 489 {
 490         u32 rxgain_type;
 491
 492         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
 493                 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
 494
 495                 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
 496                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 497                         ar9280Modes_backoff_13db_rxgain_9280_2,
 498                         ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
 499                 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
 500                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 501                         ar9280Modes_backoff_23db_rxgain_9280_2,
 502                         ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
 503                 else
 504                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 505                         ar9280Modes_original_rxgain_9280_2,
 506                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 507         } else {
 508                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 509                         ar9280Modes_original_rxgain_9280_2,
 510                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 511         }
 512 }
 513
 514 static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
 515 {
 516         u32 txgain_type;
 517
 518         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
 519                 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
 520
 521                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
 522                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 523                         ar9280Modes_high_power_tx_gain_9280_2,
 524                         ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
 525                 else
 526                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 527                         ar9280Modes_original_tx_gain_9280_2,
 528                         ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 529         } else {
 530                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 531                 ar9280Modes_original_tx_gain_9280_2,
 532                 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 533         }
 534 }
 535
 536 static int ath9k_hw_post_init(struct ath_hw *ah)
 537 {
 538         int ecode;
 539
 540         if (!AR_SREV_9271(ah)) {
 541                 if (!ath9k_hw_chip_test(ah))
 542                         return -ENODEV;
 543         }
 544
 545         ecode = ath9k_hw_rf_claim(ah);
 546         if (ecode != 0)
 547                 return ecode;
 548
 549         ecode = ath9k_hw_eeprom_init(ah);
 550         if (ecode != 0)
 551                 return ecode;
 552
 553         ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
 554                   "Eeprom VER: %d, REV: %d\n",
 555                   ah->eep_ops->get_eeprom_ver(ah),
 556                   ah->eep_ops->get_eeprom_rev(ah));
 557
 558         ecode = ath9k_hw_rf_alloc_ext_banks(ah);
 559         if (ecode) {
 560                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
 561                           "Failed allocating banks for "
 562                           "external radio\n");
 563                 return ecode;
 564         }
 565
 566         if (!AR_SREV_9100(ah)) {
 567                 ath9k_hw_ani_setup(ah);
 568                 ath9k_hw_ani_init(ah);
 569         }
 570
 571         return 0;
 572 }
 573
 574 static bool ar9002_hw_macversion_supported(u32 macversion)
 575 {
 576         switch (macversion) {
 577         case AR_SREV_VERSION_5416_PCI:
 578         case AR_SREV_VERSION_5416_PCIE:
 579         case AR_SREV_VERSION_9160:
 580         case AR_SREV_VERSION_9100:
 581         case AR_SREV_VERSION_9280:
 582         case AR_SREV_VERSION_9285:
 583         case AR_SREV_VERSION_9287:
 584         case AR_SREV_VERSION_9271:
 585                 return true;
 586         default:
 587                 break;
 588         }
 589         return false;
 590 }
 591
 592 static bool ar9003_hw_macversion_supported(u32 macversion)
 593 {
 594         switch (macversion) {
 595         case AR_SREV_VERSION_9300:
 596                 return true;
 597         default:
 598                 break;
 599         }
 600         return false;
 601 }
 602
 603 static void ar9002_hw_init_mode_regs(struct ath_hw *ah)
 604 {
 605         if (AR_SREV_9271(ah)) {
 606                 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271,
 607                                ARRAY_SIZE(ar9271Modes_9271), 6);
 608                 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271,
 609                                ARRAY_SIZE(ar9271Common_9271), 2);
 610                 INIT_INI_ARRAY(&ah->iniCommon_normal_cck_fir_coeff_9271,
 611                                ar9271Common_normal_cck_fir_coeff_9271,
 612                                ARRAY_SIZE(ar9271Common_normal_cck_fir_coeff_9271), 2);
 613                 INIT_INI_ARRAY(&ah->iniCommon_japan_2484_cck_fir_coeff_9271,
 614                                ar9271Common_japan_2484_cck_fir_coeff_9271,
 615                                ARRAY_SIZE(ar9271Common_japan_2484_cck_fir_coeff_9271), 2);
 616                 INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only,
 617                                ar9271Modes_9271_1_0_only,
 618                                ARRAY_SIZE(ar9271Modes_9271_1_0_only), 6);
 619                 INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg,
 620                                ARRAY_SIZE(ar9271Modes_9271_ANI_reg), 6);
 621                 INIT_INI_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
 622                                ar9271Modes_high_power_tx_gain_9271,
 623                                ARRAY_SIZE(ar9271Modes_high_power_tx_gain_9271), 6);
 624                 INIT_INI_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
 625                                ar9271Modes_normal_power_tx_gain_9271,
 626                                ARRAY_SIZE(ar9271Modes_normal_power_tx_gain_9271), 6);
 627                 return;
 628         }
 629
 630         if (AR_SREV_9287_11_OR_LATER(ah)) {
 631                 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
 632                                 ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
 633                 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
 634                                 ARRAY_SIZE(ar9287Common_9287_1_1), 2);
 635                 if (ah->config.pcie_clock_req)
 636                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 637                         ar9287PciePhy_clkreq_off_L1_9287_1_1,
 638                         ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
 639                 else
 640                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 641                         ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
 642                         ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
 643                                         2);
 644         } else if (AR_SREV_9287_10_OR_LATER(ah)) {
 645                 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
 646                                 ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
 647                 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
 648                                 ARRAY_SIZE(ar9287Common_9287_1_0), 2);
 649
 650                 if (ah->config.pcie_clock_req)
 651                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 652                         ar9287PciePhy_clkreq_off_L1_9287_1_0,
 653                         ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
 654                 else
 655                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 656                         ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
 657                         ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
 658                                   2);
 659         } else if (AR_SREV_9285_12_OR_LATER(ah)) {
 660
 661
 662                 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
 663                                ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
 664                 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
 665                                ARRAY_SIZE(ar9285Common_9285_1_2), 2);
 666
 667                 if (ah->config.pcie_clock_req) {
 668                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 669                         ar9285PciePhy_clkreq_off_L1_9285_1_2,
 670                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
 671                 } else {
 672                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 673                         ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
 674                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
 675                                   2);
 676                 }
 677         } else if (AR_SREV_9285_10_OR_LATER(ah)) {
 678                 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
 679                                ARRAY_SIZE(ar9285Modes_9285), 6);
 680                 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
 681                                ARRAY_SIZE(ar9285Common_9285), 2);
 682
 683                 if (ah->config.pcie_clock_req) {
 684                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 685                         ar9285PciePhy_clkreq_off_L1_9285,
 686                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
 687                 } else {
 688                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 689                         ar9285PciePhy_clkreq_always_on_L1_9285,
 690                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
 691                 }
 692         } else if (AR_SREV_9280_20_OR_LATER(ah)) {
 693                 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
 694                                ARRAY_SIZE(ar9280Modes_9280_2), 6);
 695                 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
 696                                ARRAY_SIZE(ar9280Common_9280_2), 2);
 697
 698                 if (ah->config.pcie_clock_req) {
 699                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 700                                ar9280PciePhy_clkreq_off_L1_9280,
 701                                ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
 702                 } else {
 703                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 704                                ar9280PciePhy_clkreq_always_on_L1_9280,
 705                                ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
 706                 }
 707                 INIT_INI_ARRAY(&ah->iniModesAdditional,
 708                                ar9280Modes_fast_clock_9280_2,
 709                                ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
 710         } else if (AR_SREV_9280_10_OR_LATER(ah)) {
 711                 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
 712                                ARRAY_SIZE(ar9280Modes_9280), 6);
 713                 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
 714                                ARRAY_SIZE(ar9280Common_9280), 2);
 715         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
 716                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
 717                                ARRAY_SIZE(ar5416Modes_9160), 6);
 718                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
 719                                ARRAY_SIZE(ar5416Common_9160), 2);
 720                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
 721                                ARRAY_SIZE(ar5416Bank0_9160), 2);
 722                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
 723                                ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
 724                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
 725                                ARRAY_SIZE(ar5416Bank1_9160), 2);
 726                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
 727                                ARRAY_SIZE(ar5416Bank2_9160), 2);
 728                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
 729                                ARRAY_SIZE(ar5416Bank3_9160), 3);
 730                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
 731                                ARRAY_SIZE(ar5416Bank6_9160), 3);
 732                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
 733                                ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
 734                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
 735                                ARRAY_SIZE(ar5416Bank7_9160), 2);
 736                 if (AR_SREV_9160_11(ah)) {
 737                         INIT_INI_ARRAY(&ah->iniAddac,
 738                                        ar5416Addac_91601_1,
 739                                        ARRAY_SIZE(ar5416Addac_91601_1), 2);
 740                 } else {
 741                         INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
 742                                        ARRAY_SIZE(ar5416Addac_9160), 2);
 743                 }
 744         } else if (AR_SREV_9100_OR_LATER(ah)) {
 745                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
 746                                ARRAY_SIZE(ar5416Modes_9100), 6);
 747                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
 748                                ARRAY_SIZE(ar5416Common_9100), 2);
 749                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
 750                                ARRAY_SIZE(ar5416Bank0_9100), 2);
 751                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
 752                                ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
 753                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
 754                                ARRAY_SIZE(ar5416Bank1_9100), 2);
 755                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
 756                                ARRAY_SIZE(ar5416Bank2_9100), 2);
 757                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
 758                                ARRAY_SIZE(ar5416Bank3_9100), 3);
 759                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
 760                                ARRAY_SIZE(ar5416Bank6_9100), 3);
 761                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
 762                                ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
 763                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
 764                                ARRAY_SIZE(ar5416Bank7_9100), 2);
 765                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
 766                                ARRAY_SIZE(ar5416Addac_9100), 2);
 767         } else {
 768                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
 769                                ARRAY_SIZE(ar5416Modes), 6);
 770                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
 771                                ARRAY_SIZE(ar5416Common), 2);
 772                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
 773                                ARRAY_SIZE(ar5416Bank0), 2);
 774                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
 775                                ARRAY_SIZE(ar5416BB_RfGain), 3);
 776                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
 777                                ARRAY_SIZE(ar5416Bank1), 2);
 778                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
 779                                ARRAY_SIZE(ar5416Bank2), 2);
 780                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
 781                                ARRAY_SIZE(ar5416Bank3), 3);
 782                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
 783                                ARRAY_SIZE(ar5416Bank6), 3);
 784                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
 785                                ARRAY_SIZE(ar5416Bank6TPC), 3);
 786                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
 787                                ARRAY_SIZE(ar5416Bank7), 2);
 788                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
 789                                ARRAY_SIZE(ar5416Addac), 2);
 790         }
 791 }
 792
 793 /* AR9003 2.0 - new INI format (pre, core, post arrays per subsystem) */
 794 static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
 795 {
 796         /* mac */
 797         INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
 798         INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 799                        ar9300_2p0_mac_core,
 800                        ARRAY_SIZE(ar9300_2p0_mac_core), 2);
 801         INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 802                        ar9300_2p0_mac_postamble,
 803                        ARRAY_SIZE(ar9300_2p0_mac_postamble), 5);
 804
 805         /* bb */
 806         INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
 807         INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 808                        ar9300_2p0_baseband_core,
 809                        ARRAY_SIZE(ar9300_2p0_baseband_core), 2);
 810         INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 811                        ar9300_2p0_baseband_postamble,
 812                        ARRAY_SIZE(ar9300_2p0_baseband_postamble), 5);
 813
 814         /* radio */
 815         INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
 816         INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 817                        ar9300_2p0_radio_core,
 818                        ARRAY_SIZE(ar9300_2p0_radio_core), 2);
 819         INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 820                        ar9300_2p0_radio_postamble,
 821                        ARRAY_SIZE(ar9300_2p0_radio_postamble), 5);
 822
 823         /* soc */
 824         INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 825                        ar9300_2p0_soc_preamble,
 826                        ARRAY_SIZE(ar9300_2p0_soc_preamble), 2);
 827         INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
 828         INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 829                        ar9300_2p0_soc_postamble,
 830                        ARRAY_SIZE(ar9300_2p0_soc_postamble), 5);
 831
 832         /* rx/tx gain */
 833         INIT_INI_ARRAY(&ah->iniModesRxGain,
 834                        ar9300Common_rx_gain_table_2p0,
 835                        ARRAY_SIZE(ar9300Common_rx_gain_table_2p0), 2);
 836         INIT_INI_ARRAY(&ah->iniModesTxGain,
 837                        ar9300Modes_lowest_ob_db_tx_gain_table_2p0,
 838                        ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p0),
 839                        5);
 840
 841         /* Load PCIE SERDES settings from INI */
 842
 843         /* Awake Setting */
 844
 845         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 846                        ar9300PciePhy_pll_on_clkreq_disable_L1_2p0,
 847                        ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p0),
 848                        2);
 849
 850         /* Sleep Setting */
 851
 852         INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 853                        ar9300PciePhy_clkreq_enable_L1_2p0,
 854                        ARRAY_SIZE(ar9300PciePhy_clkreq_enable_L1_2p0),
 855                        2);
 856
 857         /* Fast clock modal settings */
 858         INIT_INI_ARRAY(&ah->iniModesAdditional,
 859                        ar9300Modes_fast_clock_2p0,
 860                        ARRAY_SIZE(ar9300Modes_fast_clock_2p0),
 861                        3);
 862 }
 863
 864 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
 865 {
 866         if (AR_SREV_9287_11_OR_LATER(ah))
 867                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 868                 ar9287Modes_rx_gain_9287_1_1,
 869                 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
 870         else if (AR_SREV_9287_10(ah))
 871                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 872                 ar9287Modes_rx_gain_9287_1_0,
 873                 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
 874         else if (AR_SREV_9280_20(ah))
 875                 ath9k_hw_init_rxgain_ini(ah);
 876
 877         if (AR_SREV_9287_11_OR_LATER(ah)) {
 878                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 879                 ar9287Modes_tx_gain_9287_1_1,
 880                 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
 881         } else if (AR_SREV_9287_10(ah)) {
 882                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 883                 ar9287Modes_tx_gain_9287_1_0,
 884                 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
 885         } else if (AR_SREV_9280_20(ah)) {
 886                 ath9k_hw_init_txgain_ini(ah);
 887         } else if (AR_SREV_9285_12_OR_LATER(ah)) {
 888                 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
 889
 890                 /* txgain table */
 891                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
 892                         if (AR_SREV_9285E_20(ah)) {
 893                                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 894                                 ar9285Modes_XE2_0_high_power,
 895                                 ARRAY_SIZE(
 896                                   ar9285Modes_XE2_0_high_power), 6);
 897                         } else {
 898                                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 899                                 ar9285Modes_high_power_tx_gain_9285_1_2,
 900                                 ARRAY_SIZE(
 901                                   ar9285Modes_high_power_tx_gain_9285_1_2), 6);
 902                         }
 903                 } else {
 904                         if (AR_SREV_9285E_20(ah)) {
 905                                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 906                                 ar9285Modes_XE2_0_normal_power,
 907                                 ARRAY_SIZE(
 908                                   ar9285Modes_XE2_0_normal_power), 6);
 909                         } else {
 910                                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 911                                 ar9285Modes_original_tx_gain_9285_1_2,
 912                                 ARRAY_SIZE(
 913                                   ar9285Modes_original_tx_gain_9285_1_2), 6);
 914                         }
 915                 }
 916         }
 917 }
 918
 919 static void ath9k_hw_init_eeprom_fix(struct ath_hw *ah)
 920 {
 921         struct base_eep_header *pBase = &(ah->eeprom.def.baseEepHeader);
 922         struct ath_common *common = ath9k_hw_common(ah);
 923
 924         ah->need_an_top2_fixup = (ah->hw_version.devid == AR9280_DEVID_PCI) &&
 925                                  !AR_SREV_9285(ah) && !AR_SREV_9271(ah) &&
 926                                  ((pBase->version & 0xff) > 0x0a) &&
 927                                  (pBase->pwdclkind == 0);
 928
 929         if (ah->need_an_top2_fixup)
 930                 ath_print(common, ATH_DBG_EEPROM,
 931                           "needs fixup for AR_AN_TOP2 register\n");
 932 }
 933
 934 static void ath9k_hw_attach_ops(struct ath_hw *ah)
 935 {
 936         if (AR_SREV_9300_20_OR_LATER(ah))
 937                 ar9003_hw_attach_ops(ah);
 938         else
 939                 ar9002_hw_attach_ops(ah);
 940 }
 941
 942 /* Called for all hardware families */
 943 static int __ath9k_hw_init(struct ath_hw *ah)
 944 {
 945         struct ath_common *common = ath9k_hw_common(ah);
 946         int r = 0;
 947
 948         if (ah->hw_version.devid == AR5416_AR9100_DEVID)
 949                 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
 950
 951         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
 952                 ath_print(common, ATH_DBG_FATAL,
 953                           "Couldn't reset chip\n");
 954                 return -EIO;
 955         }
 956
 957         ath9k_hw_init_defaults(ah);
 958         ath9k_hw_init_config(ah);
 959
 960         ath9k_hw_attach_ops(ah);
 961
 962         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
 963                 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
 964                 return -EIO;
 965         }
 966
 967         if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
 968                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
 969                     (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
 970                         ah->config.serialize_regmode =
 971                                 SER_REG_MODE_ON;
 972                 } else {
 973                         ah->config.serialize_regmode =
 974                                 SER_REG_MODE_OFF;
 975                 }
 976         }
 977
 978         ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
 979                 ah->config.serialize_regmode);
 980
 981         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
 982                 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
 983         else
 984                 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
 985
 986         if (!ath9k_hw_macversion_supported(ah)) {
 987                 ath_print(common, ATH_DBG_FATAL,
 988                           "Mac Chip Rev 0x%02x.%x is not supported by "
 989                           "this driver\n", ah->hw_version.macVersion,
 990                           ah->hw_version.macRev);
 991                 return -EOPNOTSUPP;
 992         }
 993
 994         if (AR_SREV_9271(ah) || AR_SREV_9100(ah))
 995                 ah->is_pciexpress = false;
 996
 997         ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
 998         ath9k_hw_init_cal_settings(ah);
 999
1000         ah->ani_function = ATH9K_ANI_ALL;
1001         if (AR_SREV_9280_10_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1002                 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
1003
1004         ath9k_hw_init_mode_regs(ah);
1005
1006         if (ah->is_pciexpress)
1007                 ath9k_hw_configpcipowersave(ah, 0, 0);
1008         else
1009                 ath9k_hw_disablepcie(ah);
1010
1011         /* Support for Japan ch.14 (2484) spread */
1012         if (AR_SREV_9287_11_OR_LATER(ah)) {
1013                 INIT_INI_ARRAY(&ah->iniCckfirNormal,
1014                        ar9287Common_normal_cck_fir_coeff_92871_1,
1015                        ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1), 2);
1016                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
1017                        ar9287Common_japan_2484_cck_fir_coeff_92871_1,
1018                        ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1), 2);
1019         }
1020
1021         r = ath9k_hw_post_init(ah);
1022         if (r)
1023                 return r;
1024
1025         ath9k_hw_init_mode_gain_regs(ah);
1026         r = ath9k_hw_fill_cap_info(ah);
1027         if (r)
1028                 return r;
1029
1030         ath9k_hw_init_eeprom_fix(ah);
1031
1032         r = ath9k_hw_init_macaddr(ah);
1033         if (r) {
1034                 ath_print(common, ATH_DBG_FATAL,
1035                           "Failed to initialize MAC address\n");
1036                 return r;
1037         }
1038
1039         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
1040                 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
1041         else
1042                 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
1043
1044         if (AR_SREV_9300_20_OR_LATER(ah))
1045                 ar9003_hw_set_nf_limits(ah);
1046
1047         ath9k_init_nfcal_hist_buffer(ah);
1048
1049         common->state = ATH_HW_INITIALIZED;
1050
1051         return 0;
1052 }
1053
1054 int ath9k_hw_init(struct ath_hw *ah)
1055 {
1056         int ret;
1057         struct ath_common *common = ath9k_hw_common(ah);
1058
1059         /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
1060         switch (ah->hw_version.devid) {
1061         case AR5416_DEVID_PCI:
1062         case AR5416_DEVID_PCIE:
1063         case AR5416_AR9100_DEVID:
1064         case AR9160_DEVID_PCI:
1065         case AR9280_DEVID_PCI:
1066         case AR9280_DEVID_PCIE:
1067         case AR9285_DEVID_PCIE:
1068         case AR9287_DEVID_PCI:
1069         case AR9287_DEVID_PCIE:
1070         case AR2427_DEVID_PCIE:
1071         case AR9300_DEVID_PCIE:
1072                 break;
1073         default:
1074                 if (common->bus_ops->ath_bus_type == ATH_USB)
1075                         break;
1076                 ath_print(common, ATH_DBG_FATAL,
1077                           "Hardware device ID 0x%04x not supported\n",
1078                           ah->hw_version.devid);
1079                 return -EOPNOTSUPP;
1080         }
1081
1082         ret = __ath9k_hw_init(ah);
1083         if (ret) {
1084                 ath_print(common, ATH_DBG_FATAL,
1085                           "Unable to initialize hardware; "
1086                           "initialization status: %d\n", ret);
1087                 return ret;
1088         }
1089
1090         return 0;
1091 }
1092 EXPORT_SYMBOL(ath9k_hw_init);
1093
1094 static void ath9k_hw_init_qos(struct ath_hw *ah)
1095 {
1096         REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
1097         REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
1098
1099         REG_WRITE(ah, AR_QOS_NO_ACK,
1100                   SM(2, AR_QOS_NO_ACK_TWO_BIT) |
1101                   SM(5, AR_QOS_NO_ACK_BIT_OFF) |
1102                   SM(0, AR_QOS_NO_ACK_BYTE_OFF));
1103
1104         REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
1105         REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
1106         REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
1107         REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
1108         REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
1109 }
1110
1111 static void ath9k_hw_init_pll(struct ath_hw *ah,
1112                               struct ath9k_channel *chan)
1113 {
1114         u32 pll = ath9k_hw_compute_pll_control(ah, chan);
1115
1116         REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
1117
1118         /* Switch the core clock for ar9271 to 117Mhz */
1119         if (AR_SREV_9271(ah)) {
1120                 udelay(500);
1121                 REG_WRITE(ah, 0x50040, 0x304);
1122         }
1123
1124         udelay(RTC_PLL_SETTLE_DELAY);
1125
1126         REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1127 }
1128
1129 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1130                                           enum nl80211_iftype opmode)
1131 {
1132         u32 imr_reg = AR_IMR_TXERR |
1133                 AR_IMR_TXURN |
1134                 AR_IMR_RXERR |
1135                 AR_IMR_RXORN |
1136                 AR_IMR_BCNMISC;
1137
1138         if (ah->config.rx_intr_mitigation)
1139                 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1140         else
1141                 imr_reg |= AR_IMR_RXOK;
1142
1143         imr_reg |= AR_IMR_TXOK;
1144
1145         if (opmode == NL80211_IFTYPE_AP)
1146                 imr_reg |= AR_IMR_MIB;
1147
1148         REG_WRITE(ah, AR_IMR, imr_reg);
1149         ah->imrs2_reg |= AR_IMR_S2_GTT;
1150         REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
1151
1152         if (!AR_SREV_9100(ah)) {
1153                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1154                 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1155                 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1156         }
1157 }
1158
1159 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
1160 {
1161         u32 val = ath9k_hw_mac_to_clks(ah, us);
1162         val = min(val, (u32) 0xFFFF);
1163         REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
1164 }
1165
1166 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1167 {
1168         u32 val = ath9k_hw_mac_to_clks(ah, us);
1169         val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
1170         REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
1171 }
1172
1173 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1174 {
1175         u32 val = ath9k_hw_mac_to_clks(ah, us);
1176         val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
1177         REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
1178 }
1179
1180 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1181 {
1182         if (tu > 0xFFFF) {
1183                 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
1184                           "bad global tx timeout %u\n", tu);
1185                 ah->globaltxtimeout = (u32) -1;
1186                 return false;
1187         } else {
1188                 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1189                 ah->globaltxtimeout = tu;
1190                 return true;
1191         }
1192 }
1193
1194 void ath9k_hw_init_global_settings(struct ath_hw *ah)
1195 {
1196         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
1197         int acktimeout;
1198         int slottime;
1199         int sifstime;
1200
1201         ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1202                   ah->misc_mode);
1203
1204         if (ah->misc_mode != 0)
1205                 REG_WRITE(ah, AR_PCU_MISC,
1206                           REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1207
1208         if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
1209                 sifstime = 16;
1210         else
1211                 sifstime = 10;
1212
1213         /* As defined by IEEE 802.11-2007 17.3.8.6 */
1214         slottime = ah->slottime + 3 * ah->coverage_class;
1215         acktimeout = slottime + sifstime;
1216
1217         /*
1218          * Workaround for early ACK timeouts, add an offset to match the
1219          * initval's 64us ack timeout value.
1220          * This was initially only meant to work around an issue with delayed
1221          * BA frames in some implementations, but it has been found to fix ACK
1222          * timeout issues in other cases as well.
1223          */
1224         if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
1225                 acktimeout += 64 - sifstime - ah->slottime;
1226
1227         ath9k_hw_setslottime(ah, slottime);
1228         ath9k_hw_set_ack_timeout(ah, acktimeout);
1229         ath9k_hw_set_cts_timeout(ah, acktimeout);
1230         if (ah->globaltxtimeout != (u32) -1)
1231                 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1232 }
1233 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
1234
1235 void ath9k_hw_deinit(struct ath_hw *ah)
1236 {
1237         struct ath_common *common = ath9k_hw_common(ah);
1238
1239         if (common->state < ATH_HW_INITIALIZED)
1240                 goto free_hw;
1241
1242         if (!AR_SREV_9100(ah))
1243                 ath9k_hw_ani_disable(ah);
1244
1245         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1246
1247 free_hw:
1248         ath9k_hw_rf_free_ext_banks(ah);
1249 }
1250 EXPORT_SYMBOL(ath9k_hw_deinit);
1251
1252 /*******/
1253 /* INI */
1254 /*******/
1255
1256 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
1257 {
1258         u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1259
1260         if (IS_CHAN_B(chan))
1261                 ctl |= CTL_11B;
1262         else if (IS_CHAN_G(chan))
1263                 ctl |= CTL_11G;
1264         else
1265                 ctl |= CTL_11A;
1266
1267         return ctl;
1268 }
1269
1270 /****************************************/
1271 /* Reset and Channel Switching Routines */
1272 /****************************************/
1273
1274 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1275 {
1276         u32 regval;
1277
1278         /*
1279          * set AHB_MODE not to do cacheline prefetches
1280         */
1281         regval = REG_READ(ah, AR_AHB_MODE);
1282         REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1283
1284         /*
1285          * let mac dma reads be in 128 byte chunks
1286          */
1287         regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1288         REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1289
1290         /*
1291          * Restore TX Trigger Level to its pre-reset value.
1292          * The initial value depends on whether aggregation is enabled, and is
1293          * adjusted whenever underruns are detected.
1294          */
1295         REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1296
1297         /*
1298          * let mac dma writes be in 128 byte chunks
1299          */
1300         regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1301         REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1302
1303         /*
1304          * Setup receive FIFO threshold to hold off TX activities
1305          */
1306         REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1307
1308         /*
1309          * reduce the number of usable entries in PCU TXBUF to avoid
1310          * wrap around issues.
1311          */
1312         if (AR_SREV_9285(ah)) {
1313                 /* For AR9285 the number of Fifos are reduced to half.
1314                  * So set the usable tx buf size also to half to
1315                  * avoid data/delimiter underruns
1316                  */
1317                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1318                           AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1319         } else if (!AR_SREV_9271(ah)) {
1320                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1321                           AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1322         }
1323 }
1324
1325 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1326 {
1327         u32 val;
1328
1329         val = REG_READ(ah, AR_STA_ID1);
1330         val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1331         switch (opmode) {
1332         case NL80211_IFTYPE_AP:
1333                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1334                           | AR_STA_ID1_KSRCH_MODE);
1335                 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1336                 break;
1337         case NL80211_IFTYPE_ADHOC:
1338         case NL80211_IFTYPE_MESH_POINT:
1339                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1340                           | AR_STA_ID1_KSRCH_MODE);
1341                 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1342                 break;
1343         case NL80211_IFTYPE_STATION:
1344         case NL80211_IFTYPE_MONITOR:
1345                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1346                 break;
1347         }
1348 }
1349
1350 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1351                                    u32 *coef_mantissa, u32 *coef_exponent)
1352 {
1353         u32 coef_exp, coef_man;
1354
1355         for (coef_exp = 31; coef_exp > 0; coef_exp--)
1356                 if ((coef_scaled >> coef_exp) & 0x1)
1357                         break;
1358
1359         coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1360
1361         coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1362
1363         *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1364         *coef_exponent = coef_exp - 16;
1365 }
1366
1367 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1368 {
1369         u32 rst_flags;
1370         u32 tmpReg;
1371
1372         if (AR_SREV_9100(ah)) {
1373                 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1374                 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1375                 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1376                 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1377                 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1378         }
1379
1380         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1381                   AR_RTC_FORCE_WAKE_ON_INT);
1382
1383         if (AR_SREV_9100(ah)) {
1384                 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1385                         AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1386         } else {
1387                 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1388                 if (tmpReg &
1389                     (AR_INTR_SYNC_LOCAL_TIMEOUT |
1390                      AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1391                         u32 val;
1392                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1393
1394                         val = AR_RC_HOSTIF;
1395                         if (!AR_SREV_9300_20_OR_LATER(ah))
1396                                 val |= AR_RC_AHB;
1397                         REG_WRITE(ah, AR_RC, val);
1398
1399                 } else if (!AR_SREV_9300_20_OR_LATER(ah))
1400                         REG_WRITE(ah, AR_RC, AR_RC_AHB);
1401
1402                 rst_flags = AR_RTC_RC_MAC_WARM;
1403                 if (type == ATH9K_RESET_COLD)
1404                         rst_flags |= AR_RTC_RC_MAC_COLD;
1405         }
1406
1407         REG_WRITE(ah, AR_RTC_RC, rst_flags);
1408         udelay(50);
1409
1410         REG_WRITE(ah, AR_RTC_RC, 0);
1411         if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1412                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1413                           "RTC stuck in MAC reset\n");
1414                 return false;
1415         }
1416
1417         if (!AR_SREV_9100(ah))
1418                 REG_WRITE(ah, AR_RC, 0);
1419
1420         if (AR_SREV_9100(ah))
1421                 udelay(50);
1422
1423         return true;
1424 }
1425
1426 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1427 {
1428         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1429                   AR_RTC_FORCE_WAKE_ON_INT);
1430
1431         if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1432                 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1433
1434         REG_WRITE(ah, AR_RTC_RESET, 0);
1435
1436         if (!AR_SREV_9300_20_OR_LATER(ah))
1437                 udelay(2);
1438
1439         if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1440                 REG_WRITE(ah, AR_RC, 0);
1441
1442         REG_WRITE(ah, AR_RTC_RESET, 1);
1443
1444         if (!ath9k_hw_wait(ah,
1445                            AR_RTC_STATUS,
1446                            AR_RTC_STATUS_M,
1447                            AR_RTC_STATUS_ON,
1448                            AH_WAIT_TIMEOUT)) {
1449                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1450                           "RTC not waking up\n");
1451                 return false;
1452         }
1453
1454         ath9k_hw_read_revisions(ah);
1455
1456         return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1457 }
1458
1459 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1460 {
1461         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1462                   AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1463
1464         switch (type) {
1465         case ATH9K_RESET_POWER_ON:
1466                 return ath9k_hw_set_reset_power_on(ah);
1467         case ATH9K_RESET_WARM:
1468         case ATH9K_RESET_COLD:
1469                 return ath9k_hw_set_reset(ah, type);
1470         default:
1471                 return false;
1472         }
1473 }
1474
1475 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1476                                 struct ath9k_channel *chan)
1477 {
1478         if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1479                 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1480                         return false;
1481         } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1482                 return false;
1483
1484         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1485                 return false;
1486
1487         ah->chip_fullsleep = false;
1488         ath9k_hw_init_pll(ah, chan);
1489         ath9k_hw_set_rfmode(ah, chan);
1490
1491         return true;
1492 }
1493
1494 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1495                                     struct ath9k_channel *chan)
1496 {
1497         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1498         struct ath_common *common = ath9k_hw_common(ah);
1499         struct ieee80211_channel *channel = chan->chan;
1500         u32 qnum;
1501         int r;
1502
1503         for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1504                 if (ath9k_hw_numtxpending(ah, qnum)) {
1505                         ath_print(common, ATH_DBG_QUEUE,
1506                                   "Transmit frames pending on "
1507                                   "queue %d\n", qnum);
1508                         return false;
1509                 }
1510         }
1511
1512         if (!ath9k_hw_rfbus_req(ah)) {
1513                 ath_print(common, ATH_DBG_FATAL,
1514                           "Could not kill baseband RX\n");
1515                 return false;
1516         }
1517
1518         ath9k_hw_set_channel_regs(ah, chan);
1519
1520         r = ath9k_hw_rf_set_freq(ah, chan);
1521         if (r) {
1522                 ath_print(common, ATH_DBG_FATAL,
1523                           "Failed to set channel\n");
1524                 return false;
1525         }
1526
1527         ah->eep_ops->set_txpower(ah, chan,
1528                              ath9k_regd_get_ctl(regulatory, chan),
1529                              channel->max_antenna_gain * 2,
1530                              channel->max_power * 2,
1531                              min((u32) MAX_RATE_POWER,
1532                              (u32) regulatory->power_limit));
1533
1534         ath9k_hw_rfbus_done(ah);
1535
1536         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1537                 ath9k_hw_set_delta_slope(ah, chan);
1538
1539         ath9k_hw_spur_mitigate_freq(ah, chan);
1540
1541         if (!chan->oneTimeCalsDone)
1542                 chan->oneTimeCalsDone = true;
1543
1544         return true;
1545 }
1546
1547 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1548                     bool bChannelChange)
1549 {
1550         struct ath_common *common = ath9k_hw_common(ah);
1551         u32 saveLedState;
1552         struct ath9k_channel *curchan = ah->curchan;
1553         u32 saveDefAntenna;
1554         u32 macStaId1;
1555         u64 tsf = 0;
1556         int i, r;
1557
1558         ah->txchainmask = common->tx_chainmask;
1559         ah->rxchainmask = common->rx_chainmask;
1560
1561         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1562                 return -EIO;
1563
1564         if (curchan && !ah->chip_fullsleep)
1565                 ath9k_hw_getnf(ah, curchan);
1566
1567         if (bChannelChange &&
1568             (ah->chip_fullsleep != true) &&
1569             (ah->curchan != NULL) &&
1570             (chan->channel != ah->curchan->channel) &&
1571             ((chan->channelFlags & CHANNEL_ALL) ==
1572              (ah->curchan->channelFlags & CHANNEL_ALL)) &&
1573              !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) ||
1574              IS_CHAN_A_5MHZ_SPACED(ah->curchan))) {
1575
1576                 if (ath9k_hw_channel_change(ah, chan)) {
1577                         ath9k_hw_loadnf(ah, ah->curchan);
1578                         ath9k_hw_start_nfcal(ah);
1579                         return 0;
1580                 }
1581         }
1582
1583         saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1584         if (saveDefAntenna == 0)
1585                 saveDefAntenna = 1;
1586
1587         macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1588
1589         /* For chips on which RTC reset is done, save TSF before it gets cleared */
1590         if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1591                 tsf = ath9k_hw_gettsf64(ah);
1592
1593         saveLedState = REG_READ(ah, AR_CFG_LED) &
1594                 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1595                  AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1596
1597         ath9k_hw_mark_phy_inactive(ah);
1598
1599         /* Only required on the first reset */
1600         if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1601                 REG_WRITE(ah,
1602                           AR9271_RESET_POWER_DOWN_CONTROL,
1603                           AR9271_RADIO_RF_RST);
1604                 udelay(50);
1605         }
1606
1607         if (!ath9k_hw_chip_reset(ah, chan)) {
1608                 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
1609                 return -EINVAL;
1610         }
1611
1612         /* Only required on the first reset */
1613         if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1614                 ah->htc_reset_init = false;
1615                 REG_WRITE(ah,
1616                           AR9271_RESET_POWER_DOWN_CONTROL,
1617                           AR9271_GATE_MAC_CTL);
1618                 udelay(50);
1619         }
1620
1621         /* Restore TSF */
1622         if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1623                 ath9k_hw_settsf64(ah, tsf);
1624
1625         if (AR_SREV_9280_10_OR_LATER(ah))
1626                 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1627
1628         r = ath9k_hw_process_ini(ah, chan);
1629         if (r)
1630                 return r;
1631
1632         /* Setup MFP options for CCMP */
1633         if (AR_SREV_9280_20_OR_LATER(ah)) {
1634                 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1635                  * frames when constructing CCMP AAD. */
1636                 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1637                               0xc7ff);
1638                 ah->sw_mgmt_crypto = false;
1639         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1640                 /* Disable hardware crypto for management frames */
1641                 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1642                             AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1643                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1644                             AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1645                 ah->sw_mgmt_crypto = true;
1646         } else
1647                 ah->sw_mgmt_crypto = true;
1648
1649         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1650                 ath9k_hw_set_delta_slope(ah, chan);
1651
1652         ath9k_hw_spur_mitigate_freq(ah, chan);
1653         ah->eep_ops->set_board_values(ah, chan);
1654
1655         REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1656         REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
1657                   | macStaId1
1658                   | AR_STA_ID1_RTS_USE_DEF
1659                   | (ah->config.
1660                      ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
1661                   | ah->sta_id1_defaults);
1662         ath9k_hw_set_operating_mode(ah, ah->opmode);
1663
1664         ath_hw_setbssidmask(common);
1665
1666         REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1667
1668         ath9k_hw_write_associd(ah);
1669
1670         REG_WRITE(ah, AR_ISR, ~0);
1671
1672         REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1673
1674         r = ath9k_hw_rf_set_freq(ah, chan);
1675         if (r)
1676                 return r;
1677
1678         for (i = 0; i < AR_NUM_DCU; i++)
1679                 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1680
1681         ah->intr_txqs = 0;
1682         for (i = 0; i < ah->caps.total_queues; i++)
1683                 ath9k_hw_resettxqueue(ah, i);
1684
1685         ath9k_hw_init_interrupt_masks(ah, ah->opmode);
1686         ath9k_hw_init_qos(ah);
1687
1688         if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1689                 ath9k_enable_rfkill(ah);
1690
1691         ath9k_hw_init_global_settings(ah);
1692
1693         if (AR_SREV_9287_12_OR_LATER(ah)) {
1694                 REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
1695                           AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
1696                 REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
1697                           AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
1698                 REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
1699                           AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
1700
1701                 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
1702                 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
1703
1704                 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
1705                             AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
1706                 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
1707                               AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
1708         }
1709         if (AR_SREV_9287_12_OR_LATER(ah)) {
1710                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1711                                 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
1712         }
1713
1714         REG_WRITE(ah, AR_STA_ID1,
1715                   REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
1716
1717         ath9k_hw_set_dma(ah);
1718
1719         REG_WRITE(ah, AR_OBS, 8);
1720
1721         if (ah->config.rx_intr_mitigation) {
1722                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1723                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1724         }
1725
1726         ath9k_hw_init_bb(ah, chan);
1727
1728         if (!ath9k_hw_init_cal(ah, chan))
1729                 return -EIO;
1730
1731         ath9k_hw_restore_chainmask(ah);
1732         REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1733
1734         /*
1735          * For big endian systems turn on swapping for descriptors
1736          */
1737         if (AR_SREV_9100(ah)) {
1738                 u32 mask;
1739                 mask = REG_READ(ah, AR_CFG);
1740                 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1741                         ath_print(common, ATH_DBG_RESET,
1742                                 "CFG Byte Swap Set 0x%x\n", mask);
1743                 } else {
1744                         mask =
1745                                 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1746                         REG_WRITE(ah, AR_CFG, mask);
1747                         ath_print(common, ATH_DBG_RESET,
1748                                 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
1749                 }
1750         } else {
1751                 /* Configure AR9271 target WLAN */
1752                 if (AR_SREV_9271(ah))
1753                         REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1754 #ifdef __BIG_ENDIAN
1755                 else
1756                         REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1757 #endif
1758         }
1759
1760         if (ah->btcoex_hw.enabled)
1761                 ath9k_hw_btcoex_enable(ah);
1762
1763         return 0;
1764 }
1765 EXPORT_SYMBOL(ath9k_hw_reset);
1766
1767 /************************/
1768 /* Key Cache Management */
1769 /************************/
1770
1771 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
1772 {
1773         u32 keyType;
1774
1775         if (entry >= ah->caps.keycache_size) {
1776                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1777                           "keychache entry %u out of range\n", entry);
1778                 return false;
1779         }
1780
1781         keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
1782
1783         REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
1784         REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
1785         REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
1786         REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
1787         REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
1788         REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
1789         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
1790         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
1791
1792         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
1793                 u16 micentry = entry + 64;
1794
1795                 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
1796                 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
1797                 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
1798                 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
1799
1800         }
1801
1802         return true;
1803 }
1804 EXPORT_SYMBOL(ath9k_hw_keyreset);
1805
1806 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
1807 {
1808         u32 macHi, macLo;
1809
1810         if (entry >= ah->caps.keycache_size) {
1811                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1812                           "keychache entry %u out of range\n", entry);
1813                 return false;
1814         }
1815
1816         if (mac != NULL) {
1817                 macHi = (mac[5] << 8) | mac[4];
1818                 macLo = (mac[3] << 24) |
1819                         (mac[2] << 16) |
1820                         (mac[1] << 8) |
1821                         mac[0];
1822                 macLo >>= 1;
1823                 macLo |= (macHi & 1) << 31;
1824                 macHi >>= 1;
1825         } else {
1826                 macLo = macHi = 0;
1827         }
1828         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
1829         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
1830
1831         return true;
1832 }
1833 EXPORT_SYMBOL(ath9k_hw_keysetmac);
1834
1835 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
1836                                  const struct ath9k_keyval *k,
1837                                  const u8 *mac)
1838 {
1839         const struct ath9k_hw_capabilities *pCap = &ah->caps;
1840         struct ath_common *common = ath9k_hw_common(ah);
1841         u32 key0, key1, key2, key3, key4;
1842         u32 keyType;
1843
1844         if (entry >= pCap->keycache_size) {
1845                 ath_print(common, ATH_DBG_FATAL,
1846                           "keycache entry %u out of range\n", entry);
1847                 return false;
1848         }
1849
1850         switch (k->kv_type) {
1851         case ATH9K_CIPHER_AES_OCB:
1852                 keyType = AR_KEYTABLE_TYPE_AES;
1853                 break;
1854         case ATH9K_CIPHER_AES_CCM:
1855                 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
1856                         ath_print(common, ATH_DBG_ANY,
1857                                   "AES-CCM not supported by mac rev 0x%x\n",
1858                                   ah->hw_version.macRev);
1859                         return false;
1860                 }
1861                 keyType = AR_KEYTABLE_TYPE_CCM;
1862                 break;
1863         case ATH9K_CIPHER_TKIP:
1864                 keyType = AR_KEYTABLE_TYPE_TKIP;
1865                 if (ATH9K_IS_MIC_ENABLED(ah)
1866                     && entry + 64 >= pCap->keycache_size) {
1867                         ath_print(common, ATH_DBG_ANY,
1868                                   "entry %u inappropriate for TKIP\n", entry);
1869                         return false;
1870                 }
1871                 break;
1872         case ATH9K_CIPHER_WEP:
1873                 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
1874                         ath_print(common, ATH_DBG_ANY,
1875                                   "WEP key length %u too small\n", k->kv_len);
1876                         return false;
1877                 }
1878                 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
1879                         keyType = AR_KEYTABLE_TYPE_40;
1880                 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
1881                         keyType = AR_KEYTABLE_TYPE_104;
1882                 else
1883                         keyType = AR_KEYTABLE_TYPE_128;
1884                 break;
1885         case ATH9K_CIPHER_CLR:
1886                 keyType = AR_KEYTABLE_TYPE_CLR;
1887                 break;
1888         default:
1889                 ath_print(common, ATH_DBG_FATAL,
1890                           "cipher %u not supported\n", k->kv_type);
1891                 return false;
1892         }
1893
1894         key0 = get_unaligned_le32(k->kv_val + 0);
1895         key1 = get_unaligned_le16(k->kv_val + 4);
1896         key2 = get_unaligned_le32(k->kv_val + 6);
1897         key3 = get_unaligned_le16(k->kv_val + 10);
1898         key4 = get_unaligned_le32(k->kv_val + 12);
1899         if (k->kv_len <= WLAN_KEY_LEN_WEP104)
1900                 key4 &= 0xff;
1901
1902         /*
1903          * Note: Key cache registers access special memory area that requires
1904          * two 32-bit writes to actually update the values in the internal
1905          * memory. Consequently, the exact order and pairs used here must be
1906          * maintained.
1907          */
1908
1909         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
1910                 u16 micentry = entry + 64;
1911
1912                 /*
1913                  * Write inverted key[47:0] first to avoid Michael MIC errors
1914                  * on frames that could be sent or received at the same time.
1915                  * The correct key will be written in the end once everything
1916                  * else is ready.
1917                  */
1918                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
1919                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
1920
1921                 /* Write key[95:48] */
1922                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
1923                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
1924
1925                 /* Write key[127:96] and key type */
1926                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
1927                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
1928
1929                 /* Write MAC address for the entry */
1930                 (void) ath9k_hw_keysetmac(ah, entry, mac);
1931
1932                 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
1933                         /*
1934                          * TKIP uses two key cache entries:
1935                          * Michael MIC TX/RX keys in the same key cache entry
1936                          * (idx = main index + 64):
1937                          * key0 [31:0] = RX key [31:0]
1938                          * key1 [15:0] = TX key [31:16]
1939                          * key1 [31:16] = reserved
1940                          * key2 [31:0] = RX key [63:32]
1941                          * key3 [15:0] = TX key [15:0]
1942                          * key3 [31:16] = reserved
1943                          * key4 [31:0] = TX key [63:32]
1944                          */
1945                         u32 mic0, mic1, mic2, mic3, mic4;
1946
1947                         mic0 = get_unaligned_le32(k->kv_mic + 0);
1948                         mic2 = get_unaligned_le32(k->kv_mic + 4);
1949                         mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
1950                         mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
1951                         mic4 = get_unaligned_le32(k->kv_txmic + 4);
1952
1953                         /* Write RX[31:0] and TX[31:16] */
1954                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
1955                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
1956
1957                         /* Write RX[63:32] and TX[15:0] */
1958                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
1959                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
1960
1961                         /* Write TX[63:32] and keyType(reserved) */
1962                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
1963                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
1964                                   AR_KEYTABLE_TYPE_CLR);
1965
1966                 } else {
1967                         /*
1968                          * TKIP uses four key cache entries (two for group
1969                          * keys):
1970                          * Michael MIC TX/RX keys are in different key cache
1971                          * entries (idx = main index + 64 for TX and
1972                          * main index + 32 + 96 for RX):
1973                          * key0 [31:0] = TX/RX MIC key [31:0]
1974                          * key1 [31:0] = reserved
1975                          * key2 [31:0] = TX/RX MIC key [63:32]
1976                          * key3 [31:0] = reserved
1977                          * key4 [31:0] = reserved
1978                          *
1979                          * Upper layer code will call this function separately
1980                          * for TX and RX keys when these registers offsets are
1981                          * used.
1982                          */
1983                         u32 mic0, mic2;
1984
1985                         mic0 = get_unaligned_le32(k->kv_mic + 0);
1986                         mic2 = get_unaligned_le32(k->kv_mic + 4);
1987
1988                         /* Write MIC key[31:0] */
1989                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
1990                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
1991
1992                         /* Write MIC key[63:32] */
1993                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
1994                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
1995
1996                         /* Write TX[63:32] and keyType(reserved) */
1997                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
1998                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
1999                                   AR_KEYTABLE_TYPE_CLR);
2000                 }
2001
2002                 /* MAC address registers are reserved for the MIC entry */
2003                 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2004                 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2005
2006                 /*
2007                  * Write the correct (un-inverted) key[47:0] last to enable
2008                  * TKIP now that all other registers are set with correct
2009                  * values.
2010                  */
2011                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2012                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2013         } else {
2014                 /* Write key[47:0] */
2015                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2016                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2017
2018                 /* Write key[95:48] */
2019                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2020                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2021
2022                 /* Write key[127:96] and key type */
2023                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2024                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2025
2026                 /* Write MAC address for the entry */
2027                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2028         }
2029
2030         return true;
2031 }
2032 EXPORT_SYMBOL(ath9k_hw_set_keycache_entry);
2033
2034 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
2035 {
2036         if (entry < ah->caps.keycache_size) {
2037                 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2038                 if (val & AR_KEYTABLE_VALID)
2039                         return true;
2040         }
2041         return false;
2042 }
2043 EXPORT_SYMBOL(ath9k_hw_keyisvalid);
2044
2045 /******************************/
2046 /* Power Management (Chipset) */
2047 /******************************/
2048
2049 /*
2050  * Notify Power Mgt is disabled in self-generated frames.
2051  * If requested, force chip to sleep.
2052  */
2053 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2054 {
2055         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2056         if (setChip) {
2057                 /*
2058                  * Clear the RTC force wake bit to allow the
2059                  * mac to go to sleep.
2060                  */
2061                 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2062                             AR_RTC_FORCE_WAKE_EN);
2063                 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
2064                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2065
2066                 /* Shutdown chip. Active low */
2067                 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
2068                         REG_CLR_BIT(ah, (AR_RTC_RESET),
2069                                     AR_RTC_RESET_EN);
2070         }
2071 }
2072
2073 /*
2074  * Notify Power Management is enabled in self-generating
2075  * frames. If request, set power mode of chip to
2076  * auto/normal.  Duration in units of 128us (1/8 TU).
2077  */
2078 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2079 {
2080         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2081         if (setChip) {
2082                 struct ath9k_hw_capabilities *pCap = &ah->caps;
2083
2084                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2085                         /* Set WakeOnInterrupt bit; clear ForceWake bit */
2086                         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2087                                   AR_RTC_FORCE_WAKE_ON_INT);
2088                 } else {
2089                         /*
2090                          * Clear the RTC force wake bit to allow the
2091                          * mac to go to sleep.
2092                          */
2093                         REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2094                                     AR_RTC_FORCE_WAKE_EN);
2095                 }
2096         }
2097 }
2098
2099 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2100 {
2101         u32 val;
2102         int i;
2103
2104         if (setChip) {
2105                 if ((REG_READ(ah, AR_RTC_STATUS) &
2106                      AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2107                         if (ath9k_hw_set_reset_reg(ah,
2108                                            ATH9K_RESET_POWER_ON) != true) {
2109                                 return false;
2110                         }
2111                         if (!AR_SREV_9300_20_OR_LATER(ah))
2112                                 ath9k_hw_init_pll(ah, NULL);
2113                 }
2114                 if (AR_SREV_9100(ah))
2115                         REG_SET_BIT(ah, AR_RTC_RESET,
2116                                     AR_RTC_RESET_EN);
2117
2118                 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2119                             AR_RTC_FORCE_WAKE_EN);
2120                 udelay(50);
2121
2122                 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2123                         val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2124                         if (val == AR_RTC_STATUS_ON)
2125                                 break;
2126                         udelay(50);
2127                         REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2128                                     AR_RTC_FORCE_WAKE_EN);
2129                 }
2130                 if (i == 0) {
2131                         ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2132                                   "Failed to wakeup in %uus\n",
2133                                   POWER_UP_TIME / 20);
2134                         return false;
2135                 }
2136         }
2137
2138         REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2139
2140         return true;
2141 }
2142
2143 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2144 {
2145         struct ath_common *common = ath9k_hw_common(ah);
2146         int status = true, setChip = true;
2147         static const char *modes[] = {
2148                 "AWAKE",
2149                 "FULL-SLEEP",
2150                 "NETWORK SLEEP",
2151                 "UNDEFINED"
2152         };
2153
2154         if (ah->power_mode == mode)
2155                 return status;
2156
2157         ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
2158                   modes[ah->power_mode], modes[mode]);
2159
2160         switch (mode) {
2161         case ATH9K_PM_AWAKE:
2162                 status = ath9k_hw_set_power_awake(ah, setChip);
2163                 break;
2164         case ATH9K_PM_FULL_SLEEP:
2165                 ath9k_set_power_sleep(ah, setChip);
2166                 ah->chip_fullsleep = true;
2167                 break;
2168         case ATH9K_PM_NETWORK_SLEEP:
2169                 ath9k_set_power_network_sleep(ah, setChip);
2170                 break;
2171         default:
2172                 ath_print(common, ATH_DBG_FATAL,
2173                           "Unknown power mode %u\n", mode);
2174                 return false;
2175         }
2176         ah->power_mode = mode;
2177
2178         return status;
2179 }
2180 EXPORT_SYMBOL(ath9k_hw_setpower);
2181
2182 /*
2183  * Helper for ASPM support.
2184  *
2185  * Disable PLL when in L0s as well as receiver clock when in L1.
2186  * This power saving option must be enabled through the SerDes.
2187  *
2188  * Programming the SerDes must go through the same 288 bit serial shift
2189  * register as the other analog registers.  Hence the 9 writes.
2190  */
2191 static void ar9002_hw_configpcipowersave(struct ath_hw *ah,
2192                                          int restore,
2193                                          int power_off)
2194 {
2195         u8 i;
2196         u32 val;
2197
2198         if (ah->is_pciexpress != true)
2199                 return;
2200
2201         /* Do not touch SerDes registers */
2202         if (ah->config.pcie_powersave_enable == 2)
2203                 return;
2204
2205         /* Nothing to do on restore for 11N */
2206         if (!restore) {
2207                 if (AR_SREV_9280_20_OR_LATER(ah)) {
2208                         /*
2209                          * AR9280 2.0 or later chips use SerDes values from the
2210                          * initvals.h initialized depending on chipset during
2211                          * __ath9k_hw_init()
2212                          */
2213                         for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
2214                                 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
2215                                           INI_RA(&ah->iniPcieSerdes, i, 1));
2216                         }
2217                 } else if (AR_SREV_9280(ah) &&
2218                            (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
2219                         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2220                         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2221
2222                         /* RX shut off when elecidle is asserted */
2223                         REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2224                         REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2225                         REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2226
2227                         /* Shut off CLKREQ active in L1 */
2228                         if (ah->config.pcie_clock_req)
2229                                 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2230                         else
2231                                 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2232
2233                         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2234                         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2235                         REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2236
2237                         /* Load the new settings */
2238                         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2239
2240                 } else {
2241                         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2242                         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2243
2244                         /* RX shut off when elecidle is asserted */
2245                         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2246                         REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2247                         REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2248
2249                         /*
2250                          * Ignore ah->ah_config.pcie_clock_req setting for
2251                          * pre-AR9280 11n
2252                          */
2253                         REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2254
2255                         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2256                         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2257                         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2258
2259                         /* Load the new settings */
2260                         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2261                 }
2262
2263                 udelay(1000);
2264
2265                 /* set bit 19 to allow forcing of pcie core into L1 state */
2266                 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2267
2268                 /* Several PCIe massages to ensure proper behaviour */
2269                 if (ah->config.pcie_waen) {
2270                         val = ah->config.pcie_waen;
2271                         if (!power_off)
2272                                 val &= (~AR_WA_D3_L1_DISABLE);
2273                 } else {
2274                         if (AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
2275                             AR_SREV_9287(ah)) {
2276                                 val = AR9285_WA_DEFAULT;
2277                                 if (!power_off)
2278                                         val &= (~AR_WA_D3_L1_DISABLE);
2279                         } else if (AR_SREV_9280(ah)) {
2280                                 /*
2281                                  * On AR9280 chips bit 22 of 0x4004 needs to be
2282                                  * set otherwise card may disappear.
2283                                  */
2284                                 val = AR9280_WA_DEFAULT;
2285                                 if (!power_off)
2286                                         val &= (~AR_WA_D3_L1_DISABLE);
2287                         } else
2288                                 val = AR_WA_DEFAULT;
2289                 }
2290
2291                 REG_WRITE(ah, AR_WA, val);
2292         }
2293
2294         if (power_off) {
2295                 /*
2296                  * Set PCIe workaround bits
2297                  * bit 14 in WA register (disable L1) should only
2298                  * be set when device enters D3 and be cleared
2299                  * when device comes back to D0.
2300                  */
2301                 if (ah->config.pcie_waen) {
2302                         if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
2303                                 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
2304                 } else {
2305                         if (((AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
2306                               AR_SREV_9287(ah)) &&
2307                              (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||
2308                             (AR_SREV_9280(ah) &&
2309                              (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {
2310                                 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
2311                         }
2312                 }
2313         }
2314 }
2315
2316 /**********************/
2317 /* Interrupt Handling */
2318 /**********************/
2319
2320 bool ath9k_hw_intrpend(struct ath_hw *ah)
2321 {
2322         u32 host_isr;
2323
2324         if (AR_SREV_9100(ah))
2325                 return true;
2326
2327         host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
2328         if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
2329                 return true;
2330
2331         host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
2332         if ((host_isr & AR_INTR_SYNC_DEFAULT)
2333             && (host_isr != AR_INTR_SPURIOUS))
2334                 return true;
2335
2336         return false;
2337 }
2338 EXPORT_SYMBOL(ath9k_hw_intrpend);
2339
2340 bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
2341 {
2342         u32 isr = 0;
2343         u32 mask2 = 0;
2344         struct ath9k_hw_capabilities *pCap = &ah->caps;
2345         u32 sync_cause = 0;
2346         bool fatal_int = false;
2347         struct ath_common *common = ath9k_hw_common(ah);
2348
2349         if (!AR_SREV_9100(ah)) {
2350                 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
2351                         if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
2352                             == AR_RTC_STATUS_ON) {
2353                                 isr = REG_READ(ah, AR_ISR);
2354                         }
2355                 }
2356
2357                 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
2358                         AR_INTR_SYNC_DEFAULT;
2359
2360                 *masked = 0;
2361
2362                 if (!isr && !sync_cause)
2363                         return false;
2364         } else {
2365                 *masked = 0;
2366                 isr = REG_READ(ah, AR_ISR);
2367         }
2368
2369         if (isr) {
2370                 if (isr & AR_ISR_BCNMISC) {
2371                         u32 isr2;
2372                         isr2 = REG_READ(ah, AR_ISR_S2);
2373                         if (isr2 & AR_ISR_S2_TIM)
2374                                 mask2 |= ATH9K_INT_TIM;
2375                         if (isr2 & AR_ISR_S2_DTIM)
2376                                 mask2 |= ATH9K_INT_DTIM;
2377                         if (isr2 & AR_ISR_S2_DTIMSYNC)
2378                                 mask2 |= ATH9K_INT_DTIMSYNC;
2379                         if (isr2 & (AR_ISR_S2_CABEND))
2380                                 mask2 |= ATH9K_INT_CABEND;
2381                         if (isr2 & AR_ISR_S2_GTT)
2382                                 mask2 |= ATH9K_INT_GTT;
2383                         if (isr2 & AR_ISR_S2_CST)
2384                                 mask2 |= ATH9K_INT_CST;
2385                         if (isr2 & AR_ISR_S2_TSFOOR)
2386                                 mask2 |= ATH9K_INT_TSFOOR;
2387                 }
2388
2389                 isr = REG_READ(ah, AR_ISR_RAC);
2390                 if (isr == 0xffffffff) {
2391                         *masked = 0;
2392                         return false;
2393                 }
2394
2395                 *masked = isr & ATH9K_INT_COMMON;
2396
2397                 if (ah->config.rx_intr_mitigation) {
2398                         if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2399                                 *masked |= ATH9K_INT_RX;
2400                 }
2401
2402                 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
2403                         *masked |= ATH9K_INT_RX;
2404                 if (isr &
2405                     (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
2406                      AR_ISR_TXEOL)) {
2407                         u32 s0_s, s1_s;
2408
2409                         *masked |= ATH9K_INT_TX;
2410
2411                         s0_s = REG_READ(ah, AR_ISR_S0_S);
2412                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2413                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
2414
2415                         s1_s = REG_READ(ah, AR_ISR_S1_S);
2416                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2417                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
2418                 }
2419
2420                 if (isr & AR_ISR_RXORN) {
2421                         ath_print(common, ATH_DBG_INTERRUPT,
2422                                   "receive FIFO overrun interrupt\n");
2423                 }
2424
2425                 if (!AR_SREV_9100(ah)) {
2426                         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2427                                 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
2428                                 if (isr5 & AR_ISR_S5_TIM_TIMER)
2429                                         *masked |= ATH9K_INT_TIM_TIMER;
2430                         }
2431                 }
2432
2433                 *masked |= mask2;
2434         }
2435
2436         if (AR_SREV_9100(ah))
2437                 return true;
2438
2439         if (isr & AR_ISR_GENTMR) {
2440                 u32 s5_s;
2441
2442                 s5_s = REG_READ(ah, AR_ISR_S5_S);
2443                 if (isr & AR_ISR_GENTMR) {
2444                         ah->intr_gen_timer_trigger =
2445                                 MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
2446
2447                         ah->intr_gen_timer_thresh =
2448                                 MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
2449
2450                         if (ah->intr_gen_timer_trigger)
2451                                 *masked |= ATH9K_INT_GENTIMER;
2452
2453                 }
2454         }
2455
2456         if (sync_cause) {
2457                 fatal_int =
2458                         (sync_cause &
2459                          (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
2460                         ? true : false;
2461
2462                 if (fatal_int) {
2463                         if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
2464                                 ath_print(common, ATH_DBG_ANY,
2465                                           "received PCI FATAL interrupt\n");
2466                         }
2467                         if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
2468                                 ath_print(common, ATH_DBG_ANY,
2469                                           "received PCI PERR interrupt\n");
2470                         }
2471                         *masked |= ATH9K_INT_FATAL;
2472                 }
2473                 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
2474                         ath_print(common, ATH_DBG_INTERRUPT,
2475                                   "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
2476                         REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
2477                         REG_WRITE(ah, AR_RC, 0);
2478                         *masked |= ATH9K_INT_FATAL;
2479                 }
2480                 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
2481                         ath_print(common, ATH_DBG_INTERRUPT,
2482                                   "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
2483                 }
2484
2485                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
2486                 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
2487         }
2488
2489         return true;
2490 }
2491 EXPORT_SYMBOL(ath9k_hw_getisr);
2492
2493 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
2494 {
2495         enum ath9k_int omask = ah->imask;
2496         u32 mask, mask2;
2497         struct ath9k_hw_capabilities *pCap = &ah->caps;
2498         struct ath_common *common = ath9k_hw_common(ah);
2499
2500         ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
2501
2502         if (omask & ATH9K_INT_GLOBAL) {
2503                 ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n");
2504                 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
2505                 (void) REG_READ(ah, AR_IER);
2506                 if (!AR_SREV_9100(ah)) {
2507                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
2508                         (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
2509
2510                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
2511                         (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
2512                 }
2513         }
2514
2515         mask = ints & ATH9K_INT_COMMON;
2516         mask2 = 0;
2517
2518         if (ints & ATH9K_INT_TX) {
2519                 if (ah->txok_interrupt_mask)
2520                         mask |= AR_IMR_TXOK;
2521                 if (ah->txdesc_interrupt_mask)
2522                         mask |= AR_IMR_TXDESC;
2523                 if (ah->txerr_interrupt_mask)
2524                         mask |= AR_IMR_TXERR;
2525                 if (ah->txeol_interrupt_mask)
2526                         mask |= AR_IMR_TXEOL;
2527         }
2528         if (ints & ATH9K_INT_RX) {
2529                 mask |= AR_IMR_RXERR;
2530                 if (ah->config.rx_intr_mitigation)
2531                         mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
2532                 else
2533                         mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
2534                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
2535                         mask |= AR_IMR_GENTMR;
2536         }
2537
2538         if (ints & (ATH9K_INT_BMISC)) {
2539                 mask |= AR_IMR_BCNMISC;
2540                 if (ints & ATH9K_INT_TIM)
2541                         mask2 |= AR_IMR_S2_TIM;
2542                 if (ints & ATH9K_INT_DTIM)
2543                         mask2 |= AR_IMR_S2_DTIM;
2544                 if (ints & ATH9K_INT_DTIMSYNC)
2545                         mask2 |= AR_IMR_S2_DTIMSYNC;
2546                 if (ints & ATH9K_INT_CABEND)
2547                         mask2 |= AR_IMR_S2_CABEND;
2548                 if (ints & ATH9K_INT_TSFOOR)
2549                         mask2 |= AR_IMR_S2_TSFOOR;
2550         }
2551
2552         if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
2553                 mask |= AR_IMR_BCNMISC;
2554                 if (ints & ATH9K_INT_GTT)
2555                         mask2 |= AR_IMR_S2_GTT;
2556                 if (ints & ATH9K_INT_CST)
2557                         mask2 |= AR_IMR_S2_CST;
2558         }
2559
2560         ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
2561         REG_WRITE(ah, AR_IMR, mask);
2562         ah->imrs2_reg &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC |
2563                            AR_IMR_S2_CABEND | AR_IMR_S2_CABTO |
2564                            AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST);
2565         ah->imrs2_reg |= mask2;
2566         REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
2567
2568         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2569                 if (ints & ATH9K_INT_TIM_TIMER)
2570                         REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2571                 else
2572                         REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2573         }
2574
2575         if (ints & ATH9K_INT_GLOBAL) {
2576                 ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n");
2577                 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
2578                 if (!AR_SREV_9100(ah)) {
2579                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
2580                                   AR_INTR_MAC_IRQ);
2581                         REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
2582
2583
2584                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
2585                                   AR_INTR_SYNC_DEFAULT);
2586                         REG_WRITE(ah, AR_INTR_SYNC_MASK,
2587                                   AR_INTR_SYNC_DEFAULT);
2588                 }
2589                 ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
2590                           REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
2591         }
2592
2593         return omask;
2594 }
2595 EXPORT_SYMBOL(ath9k_hw_set_interrupts);
2596
2597 /*
2598  * Helper for ASPM support.
2599  *
2600  * Disable PLL when in L0s as well as receiver clock when in L1.
2601  * This power saving option must be enabled through the SerDes.
2602  *
2603  * Programming the SerDes must go through the same 288 bit serial shift
2604  * register as the other analog registers.  Hence the 9 writes.
2605  */
2606 static void ar9003_hw_configpcipowersave(struct ath_hw *ah,
2607                                          int restore,
2608                                          int power_off)
2609 {
2610         if (ah->is_pciexpress != true)
2611                 return;
2612
2613         /* Do not touch SerDes registers */
2614         if (ah->config.pcie_powersave_enable == 2)
2615                 return;
2616
2617         /* Nothing to do on restore for 11N */
2618         if (!restore) {
2619                 /* set bit 19 to allow forcing of pcie core into L1 state */
2620                 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2621
2622                 /* Several PCIe massages to ensure proper behaviour */
2623                 if (ah->config.pcie_waen)
2624                         REG_WRITE(ah, AR_WA, ah->config.pcie_waen);
2625         }
2626 }
2627
2628 /*******************/
2629 /* Beacon Handling */
2630 /*******************/
2631
2632 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
2633 {
2634         int flags = 0;
2635
2636         ah->beacon_interval = beacon_period;
2637
2638         switch (ah->opmode) {
2639         case NL80211_IFTYPE_STATION:
2640         case NL80211_IFTYPE_MONITOR:
2641                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
2642                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
2643                 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
2644                 flags |= AR_TBTT_TIMER_EN;
2645                 break;
2646         case NL80211_IFTYPE_ADHOC:
2647         case NL80211_IFTYPE_MESH_POINT:
2648                 REG_SET_BIT(ah, AR_TXCFG,
2649                             AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
2650                 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
2651                           TU_TO_USEC(next_beacon +
2652                                      (ah->atim_window ? ah->
2653                                       atim_window : 1)));
2654                 flags |= AR_NDP_TIMER_EN;
2655         case NL80211_IFTYPE_AP:
2656                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
2657                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
2658                           TU_TO_USEC(next_beacon -
2659                                      ah->config.
2660                                      dma_beacon_response_time));
2661                 REG_WRITE(ah, AR_NEXT_SWBA,
2662                           TU_TO_USEC(next_beacon -
2663                                      ah->config.
2664                                      sw_beacon_response_time));
2665                 flags |=
2666                         AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
2667                 break;
2668         default:
2669                 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
2670                           "%s: unsupported opmode: %d\n",
2671                           __func__, ah->opmode);
2672                 return;
2673                 break;
2674         }
2675
2676         REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
2677         REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
2678         REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
2679         REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
2680
2681         beacon_period &= ~ATH9K_BEACON_ENA;
2682         if (beacon_period & ATH9K_BEACON_RESET_TSF) {
2683                 ath9k_hw_reset_tsf(ah);
2684         }
2685
2686         REG_SET_BIT(ah, AR_TIMER_MODE, flags);
2687 }
2688 EXPORT_SYMBOL(ath9k_hw_beaconinit);
2689
2690 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
2691                                     const struct ath9k_beacon_state *bs)
2692 {
2693         u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2694         struct ath9k_hw_capabilities *pCap = &ah->caps;
2695         struct ath_common *common = ath9k_hw_common(ah);
2696
2697         REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
2698
2699         REG_WRITE(ah, AR_BEACON_PERIOD,
2700                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
2701         REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
2702                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
2703
2704         REG_RMW_FIELD(ah, AR_RSSI_THR,
2705                       AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
2706
2707         beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
2708
2709         if (bs->bs_sleepduration > beaconintval)
2710                 beaconintval = bs->bs_sleepduration;
2711
2712         dtimperiod = bs->bs_dtimperiod;
2713         if (bs->bs_sleepduration > dtimperiod)
2714                 dtimperiod = bs->bs_sleepduration;
2715
2716         if (beaconintval == dtimperiod)
2717                 nextTbtt = bs->bs_nextdtim;
2718         else
2719                 nextTbtt = bs->bs_nexttbtt;
2720
2721         ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
2722         ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
2723         ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
2724         ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
2725
2726         REG_WRITE(ah, AR_NEXT_DTIM,
2727                   TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
2728         REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
2729
2730         REG_WRITE(ah, AR_SLEEP1,
2731                   SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
2732                   | AR_SLEEP1_ASSUME_DTIM);
2733
2734         if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
2735                 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
2736         else
2737                 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
2738
2739         REG_WRITE(ah, AR_SLEEP2,
2740                   SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
2741
2742         REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
2743         REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
2744
2745         REG_SET_BIT(ah, AR_TIMER_MODE,
2746                     AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
2747                     AR_DTIM_TIMER_EN);
2748
2749         /* TSF Out of Range Threshold */
2750         REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
2751 }
2752 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
2753
2754 /*******************/
2755 /* HW Capabilities */
2756 /*******************/
2757
2758 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
2759 {
2760         struct ath9k_hw_capabilities *pCap = &ah->caps;
2761         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2762         struct ath_common *common = ath9k_hw_common(ah);
2763         struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
2764
2765         u16 capField = 0, eeval;
2766
2767         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
2768         regulatory->current_rd = eeval;
2769
2770         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
2771         if (AR_SREV_9285_10_OR_LATER(ah))
2772                 eeval |= AR9285_RDEXT_DEFAULT;
2773         regulatory->current_rd_ext = eeval;
2774
2775         capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
2776
2777         if (ah->opmode != NL80211_IFTYPE_AP &&
2778             ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
2779                 if (regulatory->current_rd == 0x64 ||
2780                     regulatory->current_rd == 0x65)
2781                         regulatory->current_rd += 5;
2782                 else if (regulatory->current_rd == 0x41)
2783                         regulatory->current_rd = 0x43;
2784                 ath_print(common, ATH_DBG_REGULATORY,
2785                           "regdomain mapped to 0x%x\n", regulatory->current_rd);
2786         }
2787
2788         eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
2789         if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
2790                 ath_print(common, ATH_DBG_FATAL,
2791                           "no band has been marked as supported in EEPROM.\n");
2792                 return -EINVAL;
2793         }
2794
2795         bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
2796
2797         if (eeval & AR5416_OPFLAGS_11A) {
2798                 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
2799                 if (ah->config.ht_enable) {
2800                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
2801                                 set_bit(ATH9K_MODE_11NA_HT20,
2802                                         pCap->wireless_modes);
2803                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
2804                                 set_bit(ATH9K_MODE_11NA_HT40PLUS,
2805                                         pCap->wireless_modes);
2806                                 set_bit(ATH9K_MODE_11NA_HT40MINUS,
2807                                         pCap->wireless_modes);
2808                         }
2809                 }
2810         }
2811
2812         if (eeval & AR5416_OPFLAGS_11G) {
2813                 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
2814                 if (ah->config.ht_enable) {
2815                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
2816                                 set_bit(ATH9K_MODE_11NG_HT20,
2817                                         pCap->wireless_modes);
2818                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
2819                                 set_bit(ATH9K_MODE_11NG_HT40PLUS,
2820                                         pCap->wireless_modes);
2821                                 set_bit(ATH9K_MODE_11NG_HT40MINUS,
2822                                         pCap->wireless_modes);
2823                         }
2824                 }
2825         }
2826
2827         pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
2828         /*
2829          * For AR9271 we will temporarilly uses the rx chainmax as read from
2830          * the EEPROM.
2831          */
2832         if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
2833             !(eeval & AR5416_OPFLAGS_11A) &&
2834             !(AR_SREV_9271(ah)))
2835                 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
2836                 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
2837         else
2838                 /* Use rx_chainmask from EEPROM. */
2839                 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
2840
2841         if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
2842                 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
2843
2844         pCap->low_2ghz_chan = 2312;
2845         pCap->high_2ghz_chan = 2732;
2846
2847         pCap->low_5ghz_chan = 4920;
2848         pCap->high_5ghz_chan = 6100;
2849
2850         pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
2851         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
2852         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
2853
2854         pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
2855         pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
2856         pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
2857
2858         if (ah->config.ht_enable)
2859                 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2860         else
2861                 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
2862
2863         pCap->hw_caps |= ATH9K_HW_CAP_GTT;
2864         pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
2865         pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
2866         pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
2867
2868         if (capField & AR_EEPROM_EEPCAP_MAXQCU)
2869                 pCap->total_queues =
2870                         MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
2871         else
2872                 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
2873
2874         if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
2875                 pCap->keycache_size =
2876                         1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
2877         else
2878                 pCap->keycache_size = AR_KEYTABLE_SIZE;
2879
2880         pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
2881
2882         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2883                 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
2884         else
2885                 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
2886
2887         if (AR_SREV_9271(ah))
2888                 pCap->num_gpio_pins = AR9271_NUM_GPIO;
2889         else if (AR_SREV_9285_10_OR_LATER(ah))
2890                 pCap->num_gpio_pins = AR9285_NUM_GPIO;
2891         else if (AR_SREV_9280_10_OR_LATER(ah))
2892                 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2893         else
2894                 pCap->num_gpio_pins = AR_NUM_GPIO;
2895
2896         if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
2897                 pCap->hw_caps |= ATH9K_HW_CAP_CST;
2898                 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
2899         } else {
2900                 pCap->rts_aggr_limit = (8 * 1024);
2901         }
2902
2903         pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
2904
2905 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2906         ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2907         if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2908                 ah->rfkill_gpio =
2909                         MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2910                 ah->rfkill_polarity =
2911                         MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
2912
2913                 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
2914         }
2915 #endif
2916         if (AR_SREV_9271(ah))
2917                 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2918         else
2919                 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
2920
2921         if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
2922                 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2923         else
2924                 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
2925
2926         if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
2927                 pCap->reg_cap =
2928                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
2929                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
2930                         AR_EEPROM_EEREGCAP_EN_KK_U2 |
2931                         AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
2932         } else {
2933                 pCap->reg_cap =
2934                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
2935                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
2936         }
2937
2938         /* Advertise midband for AR5416 with FCC midband set in eeprom */
2939         if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
2940             AR_SREV_5416(ah))
2941                 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
2942
2943         pCap->num_antcfg_5ghz =
2944                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
2945         pCap->num_antcfg_2ghz =
2946                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
2947
2948         if (AR_SREV_9280_10_OR_LATER(ah) &&
2949             ath9k_hw_btcoex_supported(ah)) {
2950                 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
2951                 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
2952
2953                 if (AR_SREV_9285(ah)) {
2954                         btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
2955                         btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
2956                 } else {
2957                         btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
2958                 }
2959         } else {
2960                 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
2961         }
2962
2963         if (AR_SREV_9300_20_OR_LATER(ah)) {
2964                 pCap->hw_caps |= ATH9K_HW_CAP_EDMA;
2965                 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2966                 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2967                 pCap->rx_status_len = sizeof(struct ar9003_rxs);
2968                 pCap->tx_desc_len = sizeof(struct ar9003_txc);
2969         } else {
2970                 pCap->tx_desc_len = sizeof(struct ath_desc);
2971         }
2972
2973         return 0;
2974 }
2975
2976 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
2977                             u32 capability, u32 *result)
2978 {
2979         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2980         switch (type) {
2981         case ATH9K_CAP_CIPHER:
2982                 switch (capability) {
2983                 case ATH9K_CIPHER_AES_CCM:
2984                 case ATH9K_CIPHER_AES_OCB:
2985                 case ATH9K_CIPHER_TKIP:
2986                 case ATH9K_CIPHER_WEP:
2987                 case ATH9K_CIPHER_MIC:
2988                 case ATH9K_CIPHER_CLR:
2989                         return true;
2990                 default:
2991                         return false;
2992                 }
2993         case ATH9K_CAP_TKIP_MIC:
2994                 switch (capability) {
2995                 case 0:
2996                         return true;
2997                 case 1:
2998                         return (ah->sta_id1_defaults &
2999                                 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3000                         false;
3001                 }
3002         case ATH9K_CAP_TKIP_SPLIT:
3003                 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
3004                         false : true;
3005         case ATH9K_CAP_MCAST_KEYSRCH:
3006                 switch (capability) {
3007                 case 0:
3008                         return true;
3009                 case 1:
3010                         if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3011                                 return false;
3012                         } else {
3013                                 return (ah->sta_id1_defaults &
3014                                         AR_STA_ID1_MCAST_KSRCH) ? true :
3015                                         false;
3016                         }
3017                 }
3018                 return false;
3019         case ATH9K_CAP_TXPOW:
3020                 switch (capability) {
3021                 case 0:
3022                         return 0;
3023                 case 1:
3024                         *result = regulatory->power_limit;
3025                         return 0;
3026                 case 2:
3027                         *result = regulatory->max_power_level;
3028                         return 0;
3029                 case 3:
3030                         *result = regulatory->tp_scale;
3031                         return 0;
3032                 }
3033                 return false;
3034         case ATH9K_CAP_DS:
3035                 return (AR_SREV_9280_20_OR_LATER(ah) &&
3036                         (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
3037                         ? false : true;
3038         default:
3039                 return false;
3040         }
3041 }
3042 EXPORT_SYMBOL(ath9k_hw_getcapability);
3043
3044 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3045                             u32 capability, u32 setting, int *status)
3046 {
3047         switch (type) {
3048         case ATH9K_CAP_TKIP_MIC:
3049                 if (setting)
3050                         ah->sta_id1_defaults |=
3051                                 AR_STA_ID1_CRPT_MIC_ENABLE;
3052                 else
3053                         ah->sta_id1_defaults &=
3054                                 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3055                 return true;
3056         case ATH9K_CAP_MCAST_KEYSRCH:
3057                 if (setting)
3058                         ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
3059                 else
3060                         ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3061                 return true;
3062         default:
3063                 return false;
3064         }
3065 }
3066 EXPORT_SYMBOL(ath9k_hw_setcapability);
3067
3068 /****************************/
3069 /* GPIO / RFKILL / Antennae */
3070 /****************************/
3071
3072 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
3073                                          u32 gpio, u32 type)
3074 {
3075         int addr;
3076         u32 gpio_shift, tmp;
3077
3078         if (gpio > 11)
3079                 addr = AR_GPIO_OUTPUT_MUX3;
3080         else if (gpio > 5)
3081                 addr = AR_GPIO_OUTPUT_MUX2;
3082         else
3083                 addr = AR_GPIO_OUTPUT_MUX1;
3084
3085         gpio_shift = (gpio % 6) * 5;
3086
3087         if (AR_SREV_9280_20_OR_LATER(ah)
3088             || (addr != AR_GPIO_OUTPUT_MUX1)) {
3089                 REG_RMW(ah, addr, (type << gpio_shift),
3090                         (0x1f << gpio_shift));
3091         } else {
3092                 tmp = REG_READ(ah, addr);
3093                 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3094                 tmp &= ~(0x1f << gpio_shift);
3095                 tmp |= (type << gpio_shift);
3096                 REG_WRITE(ah, addr, tmp);
3097         }
3098 }
3099
3100 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
3101 {
3102         u32 gpio_shift;
3103
3104         BUG_ON(gpio >= ah->caps.num_gpio_pins);
3105
3106         gpio_shift = gpio << 1;
3107
3108         REG_RMW(ah,
3109                 AR_GPIO_OE_OUT,
3110                 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3111                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3112 }
3113 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
3114
3115 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3116 {
3117 #define MS_REG_READ(x, y) \
3118         (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3119
3120         if (gpio >= ah->caps.num_gpio_pins)
3121                 return 0xffffffff;
3122
3123         if (AR_SREV_9300_20_OR_LATER(ah))
3124                 return MS_REG_READ(AR9300, gpio) != 0;
3125         else if (AR_SREV_9271(ah))
3126                 return MS_REG_READ(AR9271, gpio) != 0;
3127         else if (AR_SREV_9287_10_OR_LATER(ah))
3128                 return MS_REG_READ(AR9287, gpio) != 0;
3129         else if (AR_SREV_9285_10_OR_LATER(ah))
3130                 return MS_REG_READ(AR9285, gpio) != 0;
3131         else if (AR_SREV_9280_10_OR_LATER(ah))
3132                 return MS_REG_READ(AR928X, gpio) != 0;
3133         else
3134                 return MS_REG_READ(AR, gpio) != 0;
3135 }
3136 EXPORT_SYMBOL(ath9k_hw_gpio_get);
3137
3138 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
3139                          u32 ah_signal_type)
3140 {
3141         u32 gpio_shift;
3142
3143         ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3144
3145         gpio_shift = 2 * gpio;
3146
3147         REG_RMW(ah,
3148                 AR_GPIO_OE_OUT,
3149                 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3150                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3151 }
3152 EXPORT_SYMBOL(ath9k_hw_cfg_output);
3153
3154 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
3155 {
3156         if (AR_SREV_9271(ah))
3157                 val = ~val;
3158
3159         REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3160                 AR_GPIO_BIT(gpio));
3161 }
3162 EXPORT_SYMBOL(ath9k_hw_set_gpio);
3163
3164 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
3165 {
3166         return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3167 }
3168 EXPORT_SYMBOL(ath9k_hw_getdefantenna);
3169
3170 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
3171 {
3172         REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3173 }
3174 EXPORT_SYMBOL(ath9k_hw_setantenna);
3175
3176 /*********************/
3177 /* General Operation */
3178 /*********************/
3179
3180 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
3181 {
3182         u32 bits = REG_READ(ah, AR_RX_FILTER);
3183         u32 phybits = REG_READ(ah, AR_PHY_ERR);
3184
3185         if (phybits & AR_PHY_ERR_RADAR)
3186                 bits |= ATH9K_RX_FILTER_PHYRADAR;
3187         if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3188                 bits |= ATH9K_RX_FILTER_PHYERR;
3189
3190         return bits;
3191 }
3192 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
3193
3194 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
3195 {
3196         u32 phybits;
3197
3198         REG_WRITE(ah, AR_RX_FILTER, bits);
3199
3200         phybits = 0;
3201         if (bits & ATH9K_RX_FILTER_PHYRADAR)
3202                 phybits |= AR_PHY_ERR_RADAR;
3203         if (bits & ATH9K_RX_FILTER_PHYERR)
3204                 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3205         REG_WRITE(ah, AR_PHY_ERR, phybits);
3206
3207         if (phybits)
3208                 REG_WRITE(ah, AR_RXCFG,
3209                           REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3210         else
3211                 REG_WRITE(ah, AR_RXCFG,
3212                           REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3213 }
3214 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
3215
3216 bool ath9k_hw_phy_disable(struct ath_hw *ah)
3217 {
3218         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
3219                 return false;
3220
3221         ath9k_hw_init_pll(ah, NULL);
3222         return true;
3223 }
3224 EXPORT_SYMBOL(ath9k_hw_phy_disable);
3225
3226 bool ath9k_hw_disable(struct ath_hw *ah)
3227 {
3228         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3229                 return false;
3230
3231         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
3232                 return false;
3233
3234         ath9k_hw_init_pll(ah, NULL);
3235         return true;
3236 }
3237 EXPORT_SYMBOL(ath9k_hw_disable);
3238
3239 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
3240 {
3241         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3242         struct ath9k_channel *chan = ah->curchan;
3243         struct ieee80211_channel *channel = chan->chan;
3244
3245         regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
3246
3247         ah->eep_ops->set_txpower(ah, chan,
3248                                  ath9k_regd_get_ctl(regulatory, chan),
3249                                  channel->max_antenna_gain * 2,
3250                                  channel->max_power * 2,
3251                                  min((u32) MAX_RATE_POWER,
3252                                  (u32) regulatory->power_limit));
3253 }
3254 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
3255
3256 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
3257 {
3258         memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN);
3259 }
3260 EXPORT_SYMBOL(ath9k_hw_setmac);
3261
3262 void ath9k_hw_setopmode(struct ath_hw *ah)
3263 {
3264         ath9k_hw_set_operating_mode(ah, ah->opmode);
3265 }
3266 EXPORT_SYMBOL(ath9k_hw_setopmode);
3267
3268 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
3269 {
3270         REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3271         REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3272 }
3273 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
3274
3275 void ath9k_hw_write_associd(struct ath_hw *ah)
3276 {
3277         struct ath_common *common = ath9k_hw_common(ah);
3278
3279         REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
3280         REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
3281                   ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
3282 }
3283 EXPORT_SYMBOL(ath9k_hw_write_associd);
3284
3285 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
3286 {
3287         u64 tsf;
3288
3289         tsf = REG_READ(ah, AR_TSF_U32);
3290         tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
3291
3292         return tsf;
3293 }
3294 EXPORT_SYMBOL(ath9k_hw_gettsf64);
3295
3296 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
3297 {
3298         REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
3299         REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
3300 }
3301 EXPORT_SYMBOL(ath9k_hw_settsf64);
3302
3303 void ath9k_hw_reset_tsf(struct ath_hw *ah)
3304 {
3305         if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
3306                            AH_TSF_WRITE_TIMEOUT))
3307                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
3308                           "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3309
3310         REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3311 }
3312 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
3313
3314 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
3315 {
3316         if (setting)
3317                 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
3318         else
3319                 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
3320 }
3321 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
3322
3323 /*
3324  *  Extend 15-bit time stamp from rx descriptor to
3325  *  a full 64-bit TSF using the current h/w TSF.
3326 */
3327 u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp)
3328 {
3329         u64 tsf;
3330
3331         tsf = ath9k_hw_gettsf64(ah);
3332         if ((tsf & 0x7fff) < rstamp)
3333                 tsf -= 0x8000;
3334         return (tsf & ~0x7fff) | rstamp;
3335 }
3336 EXPORT_SYMBOL(ath9k_hw_extend_tsf);
3337
3338 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
3339 {
3340         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
3341         u32 macmode;
3342
3343         if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
3344                 macmode = AR_2040_JOINED_RX_CLEAR;
3345         else
3346                 macmode = 0;
3347
3348         REG_WRITE(ah, AR_2040_MODE, macmode);
3349 }
3350
3351 /* HW Generic timers configuration */
3352
3353 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
3354 {
3355         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3356         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3357         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3358         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3359         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3360         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3361         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3362         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3363         {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
3364         {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
3365                                 AR_NDP2_TIMER_MODE, 0x0002},
3366         {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
3367                                 AR_NDP2_TIMER_MODE, 0x0004},
3368         {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
3369                                 AR_NDP2_TIMER_MODE, 0x0008},
3370         {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
3371                                 AR_NDP2_TIMER_MODE, 0x0010},
3372         {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
3373                                 AR_NDP2_TIMER_MODE, 0x0020},
3374         {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
3375                                 AR_NDP2_TIMER_MODE, 0x0040},
3376         {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
3377                                 AR_NDP2_TIMER_MODE, 0x0080}
3378 };
3379
3380 /* HW generic timer primitives */
3381
3382 /* compute and clear index of rightmost 1 */
3383 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
3384 {
3385         u32 b;
3386
3387         b = *mask;
3388         b &= (0-b);
3389         *mask &= ~b;
3390         b *= debruijn32;
3391         b >>= 27;
3392
3393         return timer_table->gen_timer_index[b];
3394 }
3395
3396 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
3397 {
3398         return REG_READ(ah, AR_TSF_L32);
3399 }
3400 EXPORT_SYMBOL(ath9k_hw_gettsf32);
3401
3402 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
3403                                           void (*trigger)(void *),
3404                                           void (*overflow)(void *),
3405                                           void *arg,
3406                                           u8 timer_index)
3407 {
3408         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3409         struct ath_gen_timer *timer;
3410
3411         timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
3412
3413         if (timer == NULL) {
3414                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
3415                           "Failed to allocate memory"
3416                           "for hw timer[%d]\n", timer_index);
3417                 return NULL;
3418         }
3419
3420         /* allocate a hardware generic timer slot */
3421         timer_table->timers[timer_index] = timer;
3422         timer->index = timer_index;
3423         timer->trigger = trigger;
3424         timer->overflow = overflow;
3425         timer->arg = arg;
3426
3427         return timer;
3428 }
3429 EXPORT_SYMBOL(ath_gen_timer_alloc);
3430
3431 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
3432                               struct ath_gen_timer *timer,
3433                               u32 timer_next,
3434                               u32 timer_period)
3435 {
3436         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3437         u32 tsf;
3438
3439         BUG_ON(!timer_period);
3440
3441         set_bit(timer->index, &timer_table->timer_mask.timer_bits);
3442
3443         tsf = ath9k_hw_gettsf32(ah);
3444
3445         ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
3446                   "curent tsf %x period %x"
3447                   "timer_next %x\n", tsf, timer_period, timer_next);
3448
3449         /*
3450          * Pull timer_next forward if the current TSF already passed it
3451          * because of software latency
3452          */
3453         if (timer_next < tsf)
3454                 timer_next = tsf + timer_period;
3455
3456         /*
3457          * Program generic timer registers
3458          */
3459         REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
3460                  timer_next);
3461         REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
3462                   timer_period);
3463         REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3464                     gen_tmr_configuration[timer->index].mode_mask);
3465
3466         /* Enable both trigger and thresh interrupt masks */
3467         REG_SET_BIT(ah, AR_IMR_S5,
3468                 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3469                 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3470 }
3471 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
3472
3473 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
3474 {
3475         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3476
3477         if ((timer->index < AR_FIRST_NDP_TIMER) ||
3478                 (timer->index >= ATH_MAX_GEN_TIMER)) {
3479                 return;
3480         }
3481
3482         /* Clear generic timer enable bits. */
3483         REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3484                         gen_tmr_configuration[timer->index].mode_mask);
3485
3486         /* Disable both trigger and thresh interrupt masks */
3487         REG_CLR_BIT(ah, AR_IMR_S5,
3488                 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3489                 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3490
3491         clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
3492 }
3493 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
3494
3495 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
3496 {
3497         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3498
3499         /* free the hardware generic timer slot */
3500         timer_table->timers[timer->index] = NULL;
3501         kfree(timer);
3502 }
3503 EXPORT_SYMBOL(ath_gen_timer_free);
3504
3505 /*
3506  * Generic Timer Interrupts handling
3507  */
3508 void ath_gen_timer_isr(struct ath_hw *ah)
3509 {
3510         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3511         struct ath_gen_timer *timer;
3512         struct ath_common *common = ath9k_hw_common(ah);
3513         u32 trigger_mask, thresh_mask, index;
3514
3515         /* get hardware generic timer interrupt status */
3516         trigger_mask = ah->intr_gen_timer_trigger;
3517         thresh_mask = ah->intr_gen_timer_thresh;
3518         trigger_mask &= timer_table->timer_mask.val;
3519         thresh_mask &= timer_table->timer_mask.val;
3520
3521         trigger_mask &= ~thresh_mask;
3522
3523         while (thresh_mask) {
3524                 index = rightmost_index(timer_table, &thresh_mask);
3525                 timer = timer_table->timers[index];
3526                 BUG_ON(!timer);
3527                 ath_print(common, ATH_DBG_HWTIMER,
3528                           "TSF overflow for Gen timer %d\n", index);
3529                 timer->overflow(timer->arg);
3530         }
3531
3532         while (trigger_mask) {
3533                 index = rightmost_index(timer_table, &trigger_mask);
3534                 timer = timer_table->timers[index];
3535                 BUG_ON(!timer);
3536                 ath_print(common, ATH_DBG_HWTIMER,
3537                           "Gen timer[%d] trigger\n", index);
3538                 timer->trigger(timer->arg);
3539         }
3540 }
3541 EXPORT_SYMBOL(ath_gen_timer_isr);
3542
3543 /********/
3544 /* HTC  */
3545 /********/
3546
3547 void ath9k_hw_htc_resetinit(struct ath_hw *ah)
3548 {
3549         ah->htc_reset_init = true;
3550 }
3551 EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
3552
3553 static struct {
3554         u32 version;
3555         const char * name;
3556 } ath_mac_bb_names[] = {
3557         /* Devices with external radios */
3558         { AR_SREV_VERSION_5416_PCI,     "5416" },
3559         { AR_SREV_VERSION_5416_PCIE,    "5418" },
3560         { AR_SREV_VERSION_9100,         "9100" },
3561         { AR_SREV_VERSION_9160,         "9160" },
3562         /* Single-chip solutions */
3563         { AR_SREV_VERSION_9280,         "9280" },
3564         { AR_SREV_VERSION_9285,         "9285" },
3565         { AR_SREV_VERSION_9287,         "9287" },
3566         { AR_SREV_VERSION_9271,         "9271" },
3567 };
3568
3569 /* For devices with external radios */
3570 static struct {
3571         u16 version;
3572         const char * name;
3573 } ath_rf_names[] = {
3574         { 0,                            "5133" },
3575         { AR_RAD5133_SREV_MAJOR,        "5133" },
3576         { AR_RAD5122_SREV_MAJOR,        "5122" },
3577         { AR_RAD2133_SREV_MAJOR,        "2133" },
3578         { AR_RAD2122_SREV_MAJOR,        "2122" }
3579 };
3580
3581 /*
3582  * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3583  */
3584 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
3585 {
3586         int i;
3587
3588         for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3589                 if (ath_mac_bb_names[i].version == mac_bb_version) {
3590                         return ath_mac_bb_names[i].name;
3591                 }
3592         }
3593
3594         return "????";
3595 }
3596
3597 /*
3598  * Return the RF name. "????" is returned if the RF is unknown.
3599  * Used for devices with external radios.
3600  */
3601 static const char *ath9k_hw_rf_name(u16 rf_version)
3602 {
3603         int i;
3604
3605         for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3606                 if (ath_rf_names[i].version == rf_version) {
3607                         return ath_rf_names[i].name;
3608                 }
3609         }
3610
3611         return "????";
3612 }
3613
3614 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3615 {
3616         int used;
3617
3618         /* chipsets >= AR9280 are single-chip */
3619         if (AR_SREV_9280_10_OR_LATER(ah)) {
3620                 used = snprintf(hw_name, len,
3621                                "Atheros AR%s Rev:%x",
3622                                ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3623                                ah->hw_version.macRev);
3624         }
3625         else {
3626                 used = snprintf(hw_name, len,
3627                                "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3628                                ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3629                                ah->hw_version.macRev,
3630                                ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
3631                                                 AR_RADIO_SREV_MAJOR)),
3632                                ah->hw_version.phyRev);
3633         }
3634
3635         hw_name[used] = '\0';
3636 }
3637 EXPORT_SYMBOL(ath9k_hw_name);
3638
3639 /* Sets up the AR5008/AR9001/AR9002 hardware familiy callbacks */
3640 static void ar9002_hw_attach_ops(struct ath_hw *ah)
3641 {
3642         struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
3643         struct ath_hw_ops *ops = ath9k_hw_ops(ah);
3644
3645         priv_ops->init_mode_regs = ar9002_hw_init_mode_regs;
3646         priv_ops->macversion_supported = ar9002_hw_macversion_supported;
3647
3648         ops->config_pci_powersave = ar9002_hw_configpcipowersave;
3649
3650         ar5008_hw_attach_phy_ops(ah);
3651         if (AR_SREV_9280_10_OR_LATER(ah))
3652                 ar9002_hw_attach_phy_ops(ah);
3653
3654         ar9002_hw_attach_calib_ops(ah);
3655         ar9002_hw_attach_mac_ops(ah);
3656 }
3657
3658 /* Sets up the AR9003 hardware familiy callbacks */
3659 static void ar9003_hw_attach_ops(struct ath_hw *ah)
3660 {
3661         struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
3662         struct ath_hw_ops *ops = ath9k_hw_ops(ah);
3663
3664         priv_ops->init_mode_regs = ar9003_hw_init_mode_regs;
3665         priv_ops->macversion_supported = ar9003_hw_macversion_supported;
3666
3667         ops->config_pci_powersave = ar9003_hw_configpcipowersave;
3668
3669         ar9003_hw_attach_phy_ops(ah);
3670         ar9003_hw_attach_calib_ops(ah);
3671         ar9003_hw_attach_mac_ops(ah);
3672 }