2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include <linux/slab.h>
19 #include <linux/module.h>
20 #include <asm/unaligned.h>
25 #include "ar9003_mac.h"
27 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
29 MODULE_AUTHOR("Atheros Communications");
30 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
31 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
32 MODULE_LICENSE("Dual BSD/GPL");
34 static int __init ath9k_init(void)
38 module_init(ath9k_init);
40 static void __exit ath9k_exit(void)
44 module_exit(ath9k_exit);
46 /* Private hardware callbacks */
48 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
50 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
53 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
55 ath9k_hw_private_ops(ah)->init_mode_regs(ah);
58 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
59 struct ath9k_channel *chan)
61 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
64 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
66 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
69 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
72 static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah)
74 /* You will not have this callback if using the old ANI */
75 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs)
78 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah);
81 /********************/
82 /* Helper Functions */
83 /********************/
85 static void ath9k_hw_set_clockrate(struct ath_hw *ah)
87 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
88 struct ath_common *common = ath9k_hw_common(ah);
89 unsigned int clockrate;
91 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */
92 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah))
94 else if (!ah->curchan) /* should really check for CCK instead */
95 clockrate = ATH9K_CLOCK_RATE_CCK;
96 else if (conf->channel->band == IEEE80211_BAND_2GHZ)
97 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
98 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
99 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
101 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
103 if (conf_is_ht40(conf))
107 if (IS_CHAN_HALF_RATE(ah->curchan))
109 if (IS_CHAN_QUARTER_RATE(ah->curchan))
113 common->clockrate = clockrate;
116 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
118 struct ath_common *common = ath9k_hw_common(ah);
120 return usecs * common->clockrate;
123 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
127 BUG_ON(timeout < AH_TIME_QUANTUM);
129 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
130 if ((REG_READ(ah, reg) & mask) == val)
133 udelay(AH_TIME_QUANTUM);
136 ath_dbg(ath9k_hw_common(ah), ATH_DBG_ANY,
137 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
138 timeout, reg, REG_READ(ah, reg), mask, val);
142 EXPORT_SYMBOL(ath9k_hw_wait);
144 void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array,
145 int column, unsigned int *writecnt)
149 ENABLE_REGWRITE_BUFFER(ah);
150 for (r = 0; r < array->ia_rows; r++) {
151 REG_WRITE(ah, INI_RA(array, r, 0),
152 INI_RA(array, r, column));
155 REGWRITE_BUFFER_FLUSH(ah);
158 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
163 for (i = 0, retval = 0; i < n; i++) {
164 retval = (retval << 1) | (val & 1);
170 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
172 u32 frameLen, u16 rateix,
175 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
181 case WLAN_RC_PHY_CCK:
182 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
185 numBits = frameLen << 3;
186 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
188 case WLAN_RC_PHY_OFDM:
189 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
190 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
191 numBits = OFDM_PLCP_BITS + (frameLen << 3);
192 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
193 txTime = OFDM_SIFS_TIME_QUARTER
194 + OFDM_PREAMBLE_TIME_QUARTER
195 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
196 } else if (ah->curchan &&
197 IS_CHAN_HALF_RATE(ah->curchan)) {
198 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
199 numBits = OFDM_PLCP_BITS + (frameLen << 3);
200 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
201 txTime = OFDM_SIFS_TIME_HALF +
202 OFDM_PREAMBLE_TIME_HALF
203 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
205 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
206 numBits = OFDM_PLCP_BITS + (frameLen << 3);
207 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
208 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
209 + (numSymbols * OFDM_SYMBOL_TIME);
213 ath_err(ath9k_hw_common(ah),
214 "Unknown phy %u (rate ix %u)\n", phy, rateix);
221 EXPORT_SYMBOL(ath9k_hw_computetxtime);
223 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
224 struct ath9k_channel *chan,
225 struct chan_centers *centers)
229 if (!IS_CHAN_HT40(chan)) {
230 centers->ctl_center = centers->ext_center =
231 centers->synth_center = chan->channel;
235 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
236 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
237 centers->synth_center =
238 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
241 centers->synth_center =
242 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
246 centers->ctl_center =
247 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
248 /* 25 MHz spacing is supported by hw but not on upper layers */
249 centers->ext_center =
250 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
257 static void ath9k_hw_read_revisions(struct ath_hw *ah)
261 switch (ah->hw_version.devid) {
262 case AR5416_AR9100_DEVID:
263 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
265 case AR9300_DEVID_AR9330:
266 ah->hw_version.macVersion = AR_SREV_VERSION_9330;
267 if (ah->get_mac_revision) {
268 ah->hw_version.macRev = ah->get_mac_revision();
270 val = REG_READ(ah, AR_SREV);
271 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
274 case AR9300_DEVID_AR9340:
275 ah->hw_version.macVersion = AR_SREV_VERSION_9340;
276 val = REG_READ(ah, AR_SREV);
277 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
281 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
284 val = REG_READ(ah, AR_SREV);
285 ah->hw_version.macVersion =
286 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
287 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
289 if (AR_SREV_9462(ah))
290 ah->is_pciexpress = true;
292 ah->is_pciexpress = (val &
293 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
295 if (!AR_SREV_9100(ah))
296 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
298 ah->hw_version.macRev = val & AR_SREV_REVISION;
300 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
301 ah->is_pciexpress = true;
305 /************************************/
306 /* HW Attach, Detach, Init Routines */
307 /************************************/
309 static void ath9k_hw_disablepcie(struct ath_hw *ah)
311 if (!AR_SREV_5416(ah))
314 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
315 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
316 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
317 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
318 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
319 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
320 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
321 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
322 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
324 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
327 static void ath9k_hw_aspm_init(struct ath_hw *ah)
329 struct ath_common *common = ath9k_hw_common(ah);
331 if (common->bus_ops->aspm_init)
332 common->bus_ops->aspm_init(common);
335 /* This should work for all families including legacy */
336 static bool ath9k_hw_chip_test(struct ath_hw *ah)
338 struct ath_common *common = ath9k_hw_common(ah);
339 u32 regAddr[2] = { AR_STA_ID0 };
341 static const u32 patternData[4] = {
342 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
346 if (!AR_SREV_9300_20_OR_LATER(ah)) {
348 regAddr[1] = AR_PHY_BASE + (8 << 2);
352 for (i = 0; i < loop_max; i++) {
353 u32 addr = regAddr[i];
356 regHold[i] = REG_READ(ah, addr);
357 for (j = 0; j < 0x100; j++) {
358 wrData = (j << 16) | j;
359 REG_WRITE(ah, addr, wrData);
360 rdData = REG_READ(ah, addr);
361 if (rdData != wrData) {
363 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
364 addr, wrData, rdData);
368 for (j = 0; j < 4; j++) {
369 wrData = patternData[j];
370 REG_WRITE(ah, addr, wrData);
371 rdData = REG_READ(ah, addr);
372 if (wrData != rdData) {
374 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
375 addr, wrData, rdData);
379 REG_WRITE(ah, regAddr[i], regHold[i]);
386 static void ath9k_hw_init_config(struct ath_hw *ah)
390 ah->config.dma_beacon_response_time = 2;
391 ah->config.sw_beacon_response_time = 10;
392 ah->config.additional_swba_backoff = 0;
393 ah->config.ack_6mb = 0x0;
394 ah->config.cwm_ignore_extcca = 0;
395 ah->config.pcie_clock_req = 0;
396 ah->config.pcie_waen = 0;
397 ah->config.analog_shiftreg = 1;
398 ah->config.enable_ani = true;
400 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
401 ah->config.spurchans[i][0] = AR_NO_SPUR;
402 ah->config.spurchans[i][1] = AR_NO_SPUR;
405 /* PAPRD needs some more work to be enabled */
406 ah->config.paprd_disable = 1;
408 ah->config.rx_intr_mitigation = true;
409 ah->config.pcieSerDesWrite = true;
412 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
413 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
414 * This means we use it for all AR5416 devices, and the few
415 * minor PCI AR9280 devices out there.
417 * Serialization is required because these devices do not handle
418 * well the case of two concurrent reads/writes due to the latency
419 * involved. During one read/write another read/write can be issued
420 * on another CPU while the previous read/write may still be working
421 * on our hardware, if we hit this case the hardware poops in a loop.
422 * We prevent this by serializing reads and writes.
424 * This issue is not present on PCI-Express devices or pre-AR5416
425 * devices (legacy, 802.11abg).
427 if (num_possible_cpus() > 1)
428 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
431 static void ath9k_hw_init_defaults(struct ath_hw *ah)
433 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
435 regulatory->country_code = CTRY_DEFAULT;
436 regulatory->power_limit = MAX_RATE_POWER;
438 ah->hw_version.magic = AR5416_MAGIC;
439 ah->hw_version.subvendorid = 0;
442 ah->sta_id1_defaults =
443 AR_STA_ID1_CRPT_MIC_ENABLE |
444 AR_STA_ID1_MCAST_KSRCH;
445 if (AR_SREV_9100(ah))
446 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
447 ah->enable_32kHz_clock = DONT_USE_32KHZ;
448 ah->slottime = ATH9K_SLOT_TIME_9;
449 ah->globaltxtimeout = (u32) -1;
450 ah->power_mode = ATH9K_PM_UNDEFINED;
453 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
455 struct ath_common *common = ath9k_hw_common(ah);
459 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
462 for (i = 0; i < 3; i++) {
463 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
465 common->macaddr[2 * i] = eeval >> 8;
466 common->macaddr[2 * i + 1] = eeval & 0xff;
468 if (sum == 0 || sum == 0xffff * 3)
469 return -EADDRNOTAVAIL;
474 static int ath9k_hw_post_init(struct ath_hw *ah)
476 struct ath_common *common = ath9k_hw_common(ah);
479 if (common->bus_ops->ath_bus_type != ATH_USB) {
480 if (!ath9k_hw_chip_test(ah))
484 if (!AR_SREV_9300_20_OR_LATER(ah)) {
485 ecode = ar9002_hw_rf_claim(ah);
490 ecode = ath9k_hw_eeprom_init(ah);
494 ath_dbg(ath9k_hw_common(ah), ATH_DBG_CONFIG,
495 "Eeprom VER: %d, REV: %d\n",
496 ah->eep_ops->get_eeprom_ver(ah),
497 ah->eep_ops->get_eeprom_rev(ah));
499 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
501 ath_err(ath9k_hw_common(ah),
502 "Failed allocating banks for external radio\n");
503 ath9k_hw_rf_free_ext_banks(ah);
507 if (!AR_SREV_9100(ah) && !AR_SREV_9340(ah)) {
508 ath9k_hw_ani_setup(ah);
509 ath9k_hw_ani_init(ah);
515 static void ath9k_hw_attach_ops(struct ath_hw *ah)
517 if (AR_SREV_9300_20_OR_LATER(ah))
518 ar9003_hw_attach_ops(ah);
520 ar9002_hw_attach_ops(ah);
523 /* Called for all hardware families */
524 static int __ath9k_hw_init(struct ath_hw *ah)
526 struct ath_common *common = ath9k_hw_common(ah);
529 ath9k_hw_read_revisions(ah);
532 * Read back AR_WA into a permanent copy and set bits 14 and 17.
533 * We need to do this to avoid RMW of this register. We cannot
534 * read the reg when chip is asleep.
536 ah->WARegVal = REG_READ(ah, AR_WA);
537 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
538 AR_WA_ASPM_TIMER_BASED_DISABLE);
540 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
541 ath_err(common, "Couldn't reset chip\n");
545 if (AR_SREV_9462(ah))
546 ah->WARegVal &= ~AR_WA_D3_L1_DISABLE;
548 ath9k_hw_init_defaults(ah);
549 ath9k_hw_init_config(ah);
551 ath9k_hw_attach_ops(ah);
553 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
554 ath_err(common, "Couldn't wakeup chip\n");
558 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
559 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
560 ((AR_SREV_9160(ah) || AR_SREV_9280(ah)) &&
561 !ah->is_pciexpress)) {
562 ah->config.serialize_regmode =
565 ah->config.serialize_regmode =
570 ath_dbg(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
571 ah->config.serialize_regmode);
573 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
574 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
576 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
578 switch (ah->hw_version.macVersion) {
579 case AR_SREV_VERSION_5416_PCI:
580 case AR_SREV_VERSION_5416_PCIE:
581 case AR_SREV_VERSION_9160:
582 case AR_SREV_VERSION_9100:
583 case AR_SREV_VERSION_9280:
584 case AR_SREV_VERSION_9285:
585 case AR_SREV_VERSION_9287:
586 case AR_SREV_VERSION_9271:
587 case AR_SREV_VERSION_9300:
588 case AR_SREV_VERSION_9330:
589 case AR_SREV_VERSION_9485:
590 case AR_SREV_VERSION_9340:
591 case AR_SREV_VERSION_9462:
595 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
596 ah->hw_version.macVersion, ah->hw_version.macRev);
600 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) ||
602 ah->is_pciexpress = false;
604 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
605 ath9k_hw_init_cal_settings(ah);
607 ah->ani_function = ATH9K_ANI_ALL;
608 if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
609 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
610 if (!AR_SREV_9300_20_OR_LATER(ah))
611 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
613 ath9k_hw_init_mode_regs(ah);
615 if (!ah->is_pciexpress)
616 ath9k_hw_disablepcie(ah);
618 if (!AR_SREV_9300_20_OR_LATER(ah))
619 ar9002_hw_cck_chan14_spread(ah);
621 r = ath9k_hw_post_init(ah);
625 ath9k_hw_init_mode_gain_regs(ah);
626 r = ath9k_hw_fill_cap_info(ah);
630 if (ah->is_pciexpress)
631 ath9k_hw_aspm_init(ah);
633 r = ath9k_hw_init_macaddr(ah);
635 ath_err(common, "Failed to initialize MAC address\n");
639 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
640 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
642 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
644 if (AR_SREV_9330(ah))
645 ah->bb_watchdog_timeout_ms = 85;
647 ah->bb_watchdog_timeout_ms = 25;
649 common->state = ATH_HW_INITIALIZED;
654 int ath9k_hw_init(struct ath_hw *ah)
657 struct ath_common *common = ath9k_hw_common(ah);
659 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
660 switch (ah->hw_version.devid) {
661 case AR5416_DEVID_PCI:
662 case AR5416_DEVID_PCIE:
663 case AR5416_AR9100_DEVID:
664 case AR9160_DEVID_PCI:
665 case AR9280_DEVID_PCI:
666 case AR9280_DEVID_PCIE:
667 case AR9285_DEVID_PCIE:
668 case AR9287_DEVID_PCI:
669 case AR9287_DEVID_PCIE:
670 case AR2427_DEVID_PCIE:
671 case AR9300_DEVID_PCIE:
672 case AR9300_DEVID_AR9485_PCIE:
673 case AR9300_DEVID_AR9330:
674 case AR9300_DEVID_AR9340:
675 case AR9300_DEVID_AR9580:
676 case AR9300_DEVID_AR9462:
679 if (common->bus_ops->ath_bus_type == ATH_USB)
681 ath_err(common, "Hardware device ID 0x%04x not supported\n",
682 ah->hw_version.devid);
686 ret = __ath9k_hw_init(ah);
689 "Unable to initialize hardware; initialization status: %d\n",
696 EXPORT_SYMBOL(ath9k_hw_init);
698 static void ath9k_hw_init_qos(struct ath_hw *ah)
700 ENABLE_REGWRITE_BUFFER(ah);
702 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
703 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
705 REG_WRITE(ah, AR_QOS_NO_ACK,
706 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
707 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
708 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
710 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
711 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
712 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
713 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
714 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
716 REGWRITE_BUFFER_FLUSH(ah);
719 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
721 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
723 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
725 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0)
728 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
730 EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
732 static void ath9k_hw_init_pll(struct ath_hw *ah,
733 struct ath9k_channel *chan)
737 if (AR_SREV_9485(ah)) {
739 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
740 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
741 AR_CH0_BB_DPLL2_PLL_PWD, 0x1);
742 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
743 AR_CH0_DPLL2_KD, 0x40);
744 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
745 AR_CH0_DPLL2_KI, 0x4);
747 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
748 AR_CH0_BB_DPLL1_REFDIV, 0x5);
749 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
750 AR_CH0_BB_DPLL1_NINI, 0x58);
751 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
752 AR_CH0_BB_DPLL1_NFRAC, 0x0);
754 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
755 AR_CH0_BB_DPLL2_OUTDIV, 0x1);
756 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
757 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1);
758 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
759 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1);
761 /* program BB PLL phase_shift to 0x6 */
762 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
763 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6);
765 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
766 AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
768 } else if (AR_SREV_9330(ah)) {
769 u32 ddr_dpll2, pll_control2, kd;
771 if (ah->is_clk_25mhz) {
772 ddr_dpll2 = 0x18e82f01;
773 pll_control2 = 0xe04a3d;
776 ddr_dpll2 = 0x19e82f01;
777 pll_control2 = 0x886666;
781 /* program DDR PLL ki and kd value */
782 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2);
784 /* program DDR PLL phase_shift */
785 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
786 AR_CH0_DPLL3_PHASE_SHIFT, 0x1);
788 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
791 /* program refdiv, nint, frac to RTC register */
792 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2);
794 /* program BB PLL kd and ki value */
795 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd);
796 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06);
798 /* program BB PLL phase_shift */
799 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
800 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1);
801 } else if (AR_SREV_9340(ah)) {
802 u32 regval, pll2_divint, pll2_divfrac, refdiv;
804 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
807 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
810 if (ah->is_clk_25mhz) {
812 pll2_divfrac = 0x1eb85;
820 regval = REG_READ(ah, AR_PHY_PLL_MODE);
821 regval |= (0x1 << 16);
822 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
825 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) |
826 (pll2_divint << 18) | pll2_divfrac);
829 regval = REG_READ(ah, AR_PHY_PLL_MODE);
830 regval = (regval & 0x80071fff) | (0x1 << 30) | (0x1 << 13) |
831 (0x4 << 26) | (0x18 << 19);
832 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
833 REG_WRITE(ah, AR_PHY_PLL_MODE,
834 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
838 pll = ath9k_hw_compute_pll_control(ah, chan);
840 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
842 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah))
845 /* Switch the core clock for ar9271 to 117Mhz */
846 if (AR_SREV_9271(ah)) {
848 REG_WRITE(ah, 0x50040, 0x304);
851 udelay(RTC_PLL_SETTLE_DELAY);
853 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
855 if (AR_SREV_9340(ah)) {
856 if (ah->is_clk_25mhz) {
857 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
858 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
859 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
861 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
862 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
863 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
869 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
870 enum nl80211_iftype opmode)
872 u32 sync_default = AR_INTR_SYNC_DEFAULT;
873 u32 imr_reg = AR_IMR_TXERR |
879 if (AR_SREV_9340(ah))
880 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
882 if (AR_SREV_9300_20_OR_LATER(ah)) {
883 imr_reg |= AR_IMR_RXOK_HP;
884 if (ah->config.rx_intr_mitigation)
885 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
887 imr_reg |= AR_IMR_RXOK_LP;
890 if (ah->config.rx_intr_mitigation)
891 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
893 imr_reg |= AR_IMR_RXOK;
896 if (ah->config.tx_intr_mitigation)
897 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
899 imr_reg |= AR_IMR_TXOK;
901 if (opmode == NL80211_IFTYPE_AP)
902 imr_reg |= AR_IMR_MIB;
904 ENABLE_REGWRITE_BUFFER(ah);
906 REG_WRITE(ah, AR_IMR, imr_reg);
907 ah->imrs2_reg |= AR_IMR_S2_GTT;
908 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
910 if (!AR_SREV_9100(ah)) {
911 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
912 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
913 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
916 REGWRITE_BUFFER_FLUSH(ah);
918 if (AR_SREV_9300_20_OR_LATER(ah)) {
919 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
920 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
921 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
922 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
926 static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us)
928 u32 val = ath9k_hw_mac_to_clks(ah, us - 2);
929 val = min(val, (u32) 0xFFFF);
930 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val);
933 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
935 u32 val = ath9k_hw_mac_to_clks(ah, us);
936 val = min(val, (u32) 0xFFFF);
937 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
940 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
942 u32 val = ath9k_hw_mac_to_clks(ah, us);
943 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
944 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
947 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
949 u32 val = ath9k_hw_mac_to_clks(ah, us);
950 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
951 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
954 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
957 ath_dbg(ath9k_hw_common(ah), ATH_DBG_XMIT,
958 "bad global tx timeout %u\n", tu);
959 ah->globaltxtimeout = (u32) -1;
962 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
963 ah->globaltxtimeout = tu;
968 void ath9k_hw_init_global_settings(struct ath_hw *ah)
970 struct ath_common *common = ath9k_hw_common(ah);
971 struct ieee80211_conf *conf = &common->hw->conf;
972 const struct ath9k_channel *chan = ah->curchan;
973 int acktimeout, ctstimeout;
976 int rx_lat = 0, tx_lat = 0, eifs = 0;
979 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
985 if (ah->misc_mode != 0)
986 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
988 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
994 if (IS_CHAN_HALF_RATE(chan)) {
998 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1003 } else if (IS_CHAN_QUARTER_RATE(chan)) {
1005 rx_lat = (rx_lat * 4) - 1;
1007 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1013 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1014 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO;
1015 reg = AR_USEC_ASYNC_FIFO;
1017 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/
1019 reg = REG_READ(ah, AR_USEC);
1021 rx_lat = MS(reg, AR_USEC_RX_LAT);
1022 tx_lat = MS(reg, AR_USEC_TX_LAT);
1024 slottime = ah->slottime;
1025 if (IS_CHAN_5GHZ(chan))
1031 /* As defined by IEEE 802.11-2007 17.3.8.6 */
1032 acktimeout = slottime + sifstime + 3 * ah->coverage_class;
1033 ctstimeout = acktimeout;
1036 * Workaround for early ACK timeouts, add an offset to match the
1037 * initval's 64us ack timeout value.
1038 * This was initially only meant to work around an issue with delayed
1039 * BA frames in some implementations, but it has been found to fix ACK
1040 * timeout issues in other cases as well.
1042 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
1043 acktimeout += 64 - sifstime - ah->slottime;
1045 ath9k_hw_set_sifs_time(ah, sifstime);
1046 ath9k_hw_setslottime(ah, slottime);
1047 ath9k_hw_set_ack_timeout(ah, acktimeout);
1048 ath9k_hw_set_cts_timeout(ah, ctstimeout);
1049 if (ah->globaltxtimeout != (u32) -1)
1050 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1052 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs));
1053 REG_RMW(ah, AR_USEC,
1054 (common->clockrate - 1) |
1055 SM(rx_lat, AR_USEC_RX_LAT) |
1056 SM(tx_lat, AR_USEC_TX_LAT),
1057 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC);
1060 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
1062 void ath9k_hw_deinit(struct ath_hw *ah)
1064 struct ath_common *common = ath9k_hw_common(ah);
1066 if (common->state < ATH_HW_INITIALIZED)
1069 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1072 ath9k_hw_rf_free_ext_banks(ah);
1074 EXPORT_SYMBOL(ath9k_hw_deinit);
1080 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
1082 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1084 if (IS_CHAN_B(chan))
1086 else if (IS_CHAN_G(chan))
1094 /****************************************/
1095 /* Reset and Channel Switching Routines */
1096 /****************************************/
1098 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1100 struct ath_common *common = ath9k_hw_common(ah);
1102 ENABLE_REGWRITE_BUFFER(ah);
1105 * set AHB_MODE not to do cacheline prefetches
1107 if (!AR_SREV_9300_20_OR_LATER(ah))
1108 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
1111 * let mac dma reads be in 128 byte chunks
1113 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
1115 REGWRITE_BUFFER_FLUSH(ah);
1118 * Restore TX Trigger Level to its pre-reset value.
1119 * The initial value depends on whether aggregation is enabled, and is
1120 * adjusted whenever underruns are detected.
1122 if (!AR_SREV_9300_20_OR_LATER(ah))
1123 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1125 ENABLE_REGWRITE_BUFFER(ah);
1128 * let mac dma writes be in 128 byte chunks
1130 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
1133 * Setup receive FIFO threshold to hold off TX activities
1135 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1137 if (AR_SREV_9300_20_OR_LATER(ah)) {
1138 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
1139 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
1141 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
1142 ah->caps.rx_status_len);
1146 * reduce the number of usable entries in PCU TXBUF to avoid
1147 * wrap around issues.
1149 if (AR_SREV_9285(ah)) {
1150 /* For AR9285 the number of Fifos are reduced to half.
1151 * So set the usable tx buf size also to half to
1152 * avoid data/delimiter underruns
1154 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1155 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1156 } else if (!AR_SREV_9271(ah)) {
1157 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1158 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1161 REGWRITE_BUFFER_FLUSH(ah);
1163 if (AR_SREV_9300_20_OR_LATER(ah))
1164 ath9k_hw_reset_txstatus_ring(ah);
1167 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1169 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
1170 u32 set = AR_STA_ID1_KSRCH_MODE;
1173 case NL80211_IFTYPE_ADHOC:
1174 case NL80211_IFTYPE_MESH_POINT:
1175 set |= AR_STA_ID1_ADHOC;
1176 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1178 case NL80211_IFTYPE_AP:
1179 set |= AR_STA_ID1_STA_AP;
1181 case NL80211_IFTYPE_STATION:
1182 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1185 if (!ah->is_monitoring)
1189 REG_RMW(ah, AR_STA_ID1, set, mask);
1192 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1193 u32 *coef_mantissa, u32 *coef_exponent)
1195 u32 coef_exp, coef_man;
1197 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1198 if ((coef_scaled >> coef_exp) & 0x1)
1201 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1203 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1205 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1206 *coef_exponent = coef_exp - 16;
1209 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1214 if (AR_SREV_9100(ah)) {
1215 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK,
1216 AR_RTC_DERIVED_CLK_PERIOD, 1);
1217 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1220 ENABLE_REGWRITE_BUFFER(ah);
1222 if (AR_SREV_9300_20_OR_LATER(ah)) {
1223 REG_WRITE(ah, AR_WA, ah->WARegVal);
1227 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1228 AR_RTC_FORCE_WAKE_ON_INT);
1230 if (AR_SREV_9100(ah)) {
1231 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1232 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1234 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1236 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1237 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1239 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1242 if (!AR_SREV_9300_20_OR_LATER(ah))
1244 REG_WRITE(ah, AR_RC, val);
1246 } else if (!AR_SREV_9300_20_OR_LATER(ah))
1247 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1249 rst_flags = AR_RTC_RC_MAC_WARM;
1250 if (type == ATH9K_RESET_COLD)
1251 rst_flags |= AR_RTC_RC_MAC_COLD;
1254 if (AR_SREV_9330(ah)) {
1259 * call external reset function to reset WMAC if:
1260 * - doing a cold reset
1261 * - we have pending frames in the TX queues
1264 for (i = 0; i < AR_NUM_QCU; i++) {
1265 npend = ath9k_hw_numtxpending(ah, i);
1270 if (ah->external_reset &&
1271 (npend || type == ATH9K_RESET_COLD)) {
1274 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
1275 "reset MAC via external reset\n");
1277 reset_err = ah->external_reset();
1279 ath_err(ath9k_hw_common(ah),
1280 "External reset failed, err=%d\n",
1285 REG_WRITE(ah, AR_RTC_RESET, 1);
1289 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1291 REGWRITE_BUFFER_FLUSH(ah);
1295 REG_WRITE(ah, AR_RTC_RC, 0);
1296 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1297 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
1298 "RTC stuck in MAC reset\n");
1302 if (!AR_SREV_9100(ah))
1303 REG_WRITE(ah, AR_RC, 0);
1305 if (AR_SREV_9100(ah))
1311 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1313 ENABLE_REGWRITE_BUFFER(ah);
1315 if (AR_SREV_9300_20_OR_LATER(ah)) {
1316 REG_WRITE(ah, AR_WA, ah->WARegVal);
1320 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1321 AR_RTC_FORCE_WAKE_ON_INT);
1323 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1324 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1326 REG_WRITE(ah, AR_RTC_RESET, 0);
1328 REGWRITE_BUFFER_FLUSH(ah);
1330 if (!AR_SREV_9300_20_OR_LATER(ah))
1333 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1334 REG_WRITE(ah, AR_RC, 0);
1336 REG_WRITE(ah, AR_RTC_RESET, 1);
1338 if (!ath9k_hw_wait(ah,
1343 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
1344 "RTC not waking up\n");
1348 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1351 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1354 if (AR_SREV_9300_20_OR_LATER(ah)) {
1355 REG_WRITE(ah, AR_WA, ah->WARegVal);
1359 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1360 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1363 case ATH9K_RESET_POWER_ON:
1364 return ath9k_hw_set_reset_power_on(ah);
1365 case ATH9K_RESET_WARM:
1366 case ATH9K_RESET_COLD:
1367 return ath9k_hw_set_reset(ah, type);
1373 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1374 struct ath9k_channel *chan)
1376 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1377 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1379 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1382 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1385 ah->chip_fullsleep = false;
1386 ath9k_hw_init_pll(ah, chan);
1387 ath9k_hw_set_rfmode(ah, chan);
1392 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1393 struct ath9k_channel *chan)
1395 struct ath_common *common = ath9k_hw_common(ah);
1398 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1399 bool band_switch, mode_diff;
1402 band_switch = (chan->channelFlags & (CHANNEL_2GHZ | CHANNEL_5GHZ)) !=
1403 (ah->curchan->channelFlags & (CHANNEL_2GHZ |
1405 mode_diff = (chan->chanmode != ah->curchan->chanmode);
1407 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1408 if (ath9k_hw_numtxpending(ah, qnum)) {
1409 ath_dbg(common, ATH_DBG_QUEUE,
1410 "Transmit frames pending on queue %d\n", qnum);
1415 if (!ath9k_hw_rfbus_req(ah)) {
1416 ath_err(common, "Could not kill baseband RX\n");
1420 if (edma && (band_switch || mode_diff)) {
1421 ath9k_hw_mark_phy_inactive(ah);
1424 ath9k_hw_init_pll(ah, NULL);
1426 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) {
1427 ath_err(common, "Failed to do fast channel change\n");
1432 ath9k_hw_set_channel_regs(ah, chan);
1434 r = ath9k_hw_rf_set_freq(ah, chan);
1436 ath_err(common, "Failed to set channel\n");
1439 ath9k_hw_set_clockrate(ah);
1440 ath9k_hw_apply_txpower(ah, chan);
1441 ath9k_hw_rfbus_done(ah);
1443 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1444 ath9k_hw_set_delta_slope(ah, chan);
1446 ath9k_hw_spur_mitigate_freq(ah, chan);
1448 if (edma && (band_switch || mode_diff)) {
1449 ah->ah_flags |= AH_FASTCC;
1450 if (band_switch || ini_reloaded)
1451 ah->eep_ops->set_board_values(ah, chan);
1453 ath9k_hw_init_bb(ah, chan);
1455 if (band_switch || ini_reloaded)
1456 ath9k_hw_init_cal(ah, chan);
1457 ah->ah_flags &= ~AH_FASTCC;
1463 static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
1465 u32 gpio_mask = ah->gpio_mask;
1468 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {
1469 if (!(gpio_mask & 1))
1472 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1473 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
1477 bool ath9k_hw_check_alive(struct ath_hw *ah)
1482 if (AR_SREV_9285_12_OR_LATER(ah))
1486 reg = REG_READ(ah, AR_OBS_BUS_1);
1488 if ((reg & 0x7E7FFFEF) == 0x00702400)
1491 switch (reg & 0x7E000B00) {
1499 } while (count-- > 0);
1503 EXPORT_SYMBOL(ath9k_hw_check_alive);
1505 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1506 struct ath9k_hw_cal_data *caldata, bool bChannelChange)
1508 struct ath_common *common = ath9k_hw_common(ah);
1510 struct ath9k_channel *curchan = ah->curchan;
1515 bool allow_fbs = false;
1517 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1520 if (curchan && !ah->chip_fullsleep)
1521 ath9k_hw_getnf(ah, curchan);
1523 ah->caldata = caldata;
1525 (chan->channel != caldata->channel ||
1526 (chan->channelFlags & ~CHANNEL_CW_INT) !=
1527 (caldata->channelFlags & ~CHANNEL_CW_INT))) {
1528 /* Operating channel changed, reset channel calibration data */
1529 memset(caldata, 0, sizeof(*caldata));
1530 ath9k_init_nfcal_hist_buffer(ah, chan);
1532 ah->noise = ath9k_hw_getchan_noise(ah, chan);
1534 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI)
1535 bChannelChange = false;
1538 caldata->done_txiqcal_once &&
1539 caldata->done_txclcal_once &&
1540 caldata->rtt_hist.num_readings)
1543 if (bChannelChange &&
1544 (ah->chip_fullsleep != true) &&
1545 (ah->curchan != NULL) &&
1546 (chan->channel != ah->curchan->channel) &&
1548 ((chan->channelFlags & CHANNEL_ALL) ==
1549 (ah->curchan->channelFlags & CHANNEL_ALL)))) {
1550 if (ath9k_hw_channel_change(ah, chan)) {
1551 ath9k_hw_loadnf(ah, ah->curchan);
1552 ath9k_hw_start_nfcal(ah, true);
1553 if (AR_SREV_9271(ah))
1554 ar9002_hw_load_ani_reg(ah, chan);
1559 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1560 if (saveDefAntenna == 0)
1563 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1565 /* For chips on which RTC reset is done, save TSF before it gets cleared */
1566 if (AR_SREV_9100(ah) ||
1567 (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)))
1568 tsf = ath9k_hw_gettsf64(ah);
1570 saveLedState = REG_READ(ah, AR_CFG_LED) &
1571 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1572 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1574 ath9k_hw_mark_phy_inactive(ah);
1576 ah->paprd_table_write_done = false;
1578 /* Only required on the first reset */
1579 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1581 AR9271_RESET_POWER_DOWN_CONTROL,
1582 AR9271_RADIO_RF_RST);
1586 if (!ath9k_hw_chip_reset(ah, chan)) {
1587 ath_err(common, "Chip reset failed\n");
1591 /* Only required on the first reset */
1592 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1593 ah->htc_reset_init = false;
1595 AR9271_RESET_POWER_DOWN_CONTROL,
1596 AR9271_GATE_MAC_CTL);
1602 ath9k_hw_settsf64(ah, tsf);
1604 if (AR_SREV_9280_20_OR_LATER(ah))
1605 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1607 if (!AR_SREV_9300_20_OR_LATER(ah))
1608 ar9002_hw_enable_async_fifo(ah);
1610 r = ath9k_hw_process_ini(ah, chan);
1615 * Some AR91xx SoC devices frequently fail to accept TSF writes
1616 * right after the chip reset. When that happens, write a new
1617 * value after the initvals have been applied, with an offset
1618 * based on measured time difference
1620 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
1622 ath9k_hw_settsf64(ah, tsf);
1625 /* Setup MFP options for CCMP */
1626 if (AR_SREV_9280_20_OR_LATER(ah)) {
1627 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1628 * frames when constructing CCMP AAD. */
1629 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1631 ah->sw_mgmt_crypto = false;
1632 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1633 /* Disable hardware crypto for management frames */
1634 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1635 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1636 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1637 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1638 ah->sw_mgmt_crypto = true;
1640 ah->sw_mgmt_crypto = true;
1642 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1643 ath9k_hw_set_delta_slope(ah, chan);
1645 ath9k_hw_spur_mitigate_freq(ah, chan);
1646 ah->eep_ops->set_board_values(ah, chan);
1648 ENABLE_REGWRITE_BUFFER(ah);
1650 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1651 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
1653 | AR_STA_ID1_RTS_USE_DEF
1655 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
1656 | ah->sta_id1_defaults);
1657 ath_hw_setbssidmask(common);
1658 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1659 ath9k_hw_write_associd(ah);
1660 REG_WRITE(ah, AR_ISR, ~0);
1661 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1663 REGWRITE_BUFFER_FLUSH(ah);
1665 ath9k_hw_set_operating_mode(ah, ah->opmode);
1667 r = ath9k_hw_rf_set_freq(ah, chan);
1671 ath9k_hw_set_clockrate(ah);
1673 ENABLE_REGWRITE_BUFFER(ah);
1675 for (i = 0; i < AR_NUM_DCU; i++)
1676 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1678 REGWRITE_BUFFER_FLUSH(ah);
1681 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1682 ath9k_hw_resettxqueue(ah, i);
1684 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
1685 ath9k_hw_ani_cache_ini_regs(ah);
1686 ath9k_hw_init_qos(ah);
1688 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1689 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
1691 ath9k_hw_init_global_settings(ah);
1693 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1694 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
1695 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
1696 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
1697 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
1698 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1699 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
1702 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
1704 ath9k_hw_set_dma(ah);
1706 REG_WRITE(ah, AR_OBS, 8);
1708 if (ah->config.rx_intr_mitigation) {
1709 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1710 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1713 if (ah->config.tx_intr_mitigation) {
1714 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1715 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1718 ath9k_hw_init_bb(ah, chan);
1721 caldata->done_txiqcal_once = false;
1722 caldata->done_txclcal_once = false;
1723 caldata->rtt_hist.num_readings = 0;
1725 if (!ath9k_hw_init_cal(ah, chan))
1728 ath9k_hw_loadnf(ah, chan);
1729 ath9k_hw_start_nfcal(ah, true);
1731 ENABLE_REGWRITE_BUFFER(ah);
1733 ath9k_hw_restore_chainmask(ah);
1734 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1736 REGWRITE_BUFFER_FLUSH(ah);
1739 * For big endian systems turn on swapping for descriptors
1741 if (AR_SREV_9100(ah)) {
1743 mask = REG_READ(ah, AR_CFG);
1744 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1745 ath_dbg(common, ATH_DBG_RESET,
1746 "CFG Byte Swap Set 0x%x\n", mask);
1749 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1750 REG_WRITE(ah, AR_CFG, mask);
1751 ath_dbg(common, ATH_DBG_RESET,
1752 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
1755 if (common->bus_ops->ath_bus_type == ATH_USB) {
1756 /* Configure AR9271 target WLAN */
1757 if (AR_SREV_9271(ah))
1758 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1760 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1763 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah))
1764 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
1766 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1770 if (ah->btcoex_hw.enabled)
1771 ath9k_hw_btcoex_enable(ah);
1773 if (AR_SREV_9300_20_OR_LATER(ah)) {
1774 ar9003_hw_bb_watchdog_config(ah);
1776 ar9003_hw_disable_phy_restart(ah);
1779 ath9k_hw_apply_gpio_override(ah);
1783 EXPORT_SYMBOL(ath9k_hw_reset);
1785 /******************************/
1786 /* Power Management (Chipset) */
1787 /******************************/
1790 * Notify Power Mgt is disabled in self-generated frames.
1791 * If requested, force chip to sleep.
1793 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
1795 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1797 if (AR_SREV_9462(ah)) {
1798 REG_WRITE(ah, AR_TIMER_MODE,
1799 REG_READ(ah, AR_TIMER_MODE) & 0xFFFFFF00);
1800 REG_WRITE(ah, AR_NDP2_TIMER_MODE, REG_READ(ah,
1801 AR_NDP2_TIMER_MODE) & 0xFFFFFF00);
1802 REG_WRITE(ah, AR_SLP32_INC,
1803 REG_READ(ah, AR_SLP32_INC) & 0xFFF00000);
1804 /* xxx Required for WLAN only case ? */
1805 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0);
1810 * Clear the RTC force wake bit to allow the
1811 * mac to go to sleep.
1813 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
1815 if (AR_SREV_9462(ah))
1818 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1819 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1821 /* Shutdown chip. Active low */
1822 if (!AR_SREV_5416(ah) &&
1823 !AR_SREV_9271(ah) && !AR_SREV_9462_10(ah)) {
1824 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN);
1829 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
1830 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
1834 * Notify Power Management is enabled in self-generating
1835 * frames. If request, set power mode of chip to
1836 * auto/normal. Duration in units of 128us (1/8 TU).
1838 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
1842 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1844 struct ath9k_hw_capabilities *pCap = &ah->caps;
1846 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1847 /* Set WakeOnInterrupt bit; clear ForceWake bit */
1848 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1849 AR_RTC_FORCE_WAKE_ON_INT);
1852 /* When chip goes into network sleep, it could be waken
1853 * up by MCI_INT interrupt caused by BT's HW messages
1854 * (LNA_xxx, CONT_xxx) which chould be in a very fast
1855 * rate (~100us). This will cause chip to leave and
1856 * re-enter network sleep mode frequently, which in
1857 * consequence will have WLAN MCI HW to generate lots of
1858 * SYS_WAKING and SYS_SLEEPING messages which will make
1859 * BT CPU to busy to process.
1861 if (AR_SREV_9462(ah)) {
1862 val = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_EN) &
1863 ~AR_MCI_INTERRUPT_RX_HW_MSG_MASK;
1864 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, val);
1867 * Clear the RTC force wake bit to allow the
1868 * mac to go to sleep.
1870 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1871 AR_RTC_FORCE_WAKE_EN);
1873 if (AR_SREV_9462(ah))
1878 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
1879 if (AR_SREV_9300_20_OR_LATER(ah))
1880 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
1883 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
1888 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
1889 if (AR_SREV_9300_20_OR_LATER(ah)) {
1890 REG_WRITE(ah, AR_WA, ah->WARegVal);
1895 if ((REG_READ(ah, AR_RTC_STATUS) &
1896 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
1897 if (ath9k_hw_set_reset_reg(ah,
1898 ATH9K_RESET_POWER_ON) != true) {
1901 if (!AR_SREV_9300_20_OR_LATER(ah))
1902 ath9k_hw_init_pll(ah, NULL);
1904 if (AR_SREV_9100(ah))
1905 REG_SET_BIT(ah, AR_RTC_RESET,
1908 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1909 AR_RTC_FORCE_WAKE_EN);
1912 for (i = POWER_UP_TIME / 50; i > 0; i--) {
1913 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
1914 if (val == AR_RTC_STATUS_ON)
1917 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1918 AR_RTC_FORCE_WAKE_EN);
1921 ath_err(ath9k_hw_common(ah),
1922 "Failed to wakeup in %uus\n",
1923 POWER_UP_TIME / 20);
1928 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1933 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
1935 struct ath_common *common = ath9k_hw_common(ah);
1936 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
1937 int status = true, setChip = true;
1938 static const char *modes[] = {
1945 if (ah->power_mode == mode)
1948 ath_dbg(common, ATH_DBG_RESET, "%s -> %s\n",
1949 modes[ah->power_mode], modes[mode]);
1952 case ATH9K_PM_AWAKE:
1953 status = ath9k_hw_set_power_awake(ah, setChip);
1955 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
1956 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
1959 case ATH9K_PM_FULL_SLEEP:
1961 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI) {
1962 if (ar9003_mci_state(ah, MCI_STATE_ENABLE, NULL) &&
1963 (mci->bt_state != MCI_BT_SLEEP) &&
1964 !mci->halted_bt_gpm) {
1965 ath_dbg(common, ATH_DBG_MCI, "MCI halt BT GPM"
1967 ar9003_mci_send_coex_halt_bt_gpm(ah,
1972 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
1975 ath9k_set_power_sleep(ah, setChip);
1976 ah->chip_fullsleep = true;
1978 case ATH9K_PM_NETWORK_SLEEP:
1980 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
1981 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
1983 ath9k_set_power_network_sleep(ah, setChip);
1986 ath_err(common, "Unknown power mode %u\n", mode);
1989 ah->power_mode = mode;
1992 * XXX: If this warning never comes up after a while then
1993 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
1994 * ath9k_hw_setpower() return type void.
1997 if (!(ah->ah_flags & AH_UNPLUGGED))
1998 ATH_DBG_WARN_ON_ONCE(!status);
2002 EXPORT_SYMBOL(ath9k_hw_setpower);
2004 /*******************/
2005 /* Beacon Handling */
2006 /*******************/
2008 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
2012 ENABLE_REGWRITE_BUFFER(ah);
2014 switch (ah->opmode) {
2015 case NL80211_IFTYPE_ADHOC:
2016 case NL80211_IFTYPE_MESH_POINT:
2017 REG_SET_BIT(ah, AR_TXCFG,
2018 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
2019 REG_WRITE(ah, AR_NEXT_NDP_TIMER, next_beacon +
2020 TU_TO_USEC(ah->atim_window ? ah->atim_window : 1));
2021 flags |= AR_NDP_TIMER_EN;
2022 case NL80211_IFTYPE_AP:
2023 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
2024 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -
2025 TU_TO_USEC(ah->config.dma_beacon_response_time));
2026 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -
2027 TU_TO_USEC(ah->config.sw_beacon_response_time));
2029 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
2032 ath_dbg(ath9k_hw_common(ah), ATH_DBG_BEACON,
2033 "%s: unsupported opmode: %d\n",
2034 __func__, ah->opmode);
2039 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
2040 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
2041 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
2042 REG_WRITE(ah, AR_NDP_PERIOD, beacon_period);
2044 REGWRITE_BUFFER_FLUSH(ah);
2046 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
2048 EXPORT_SYMBOL(ath9k_hw_beaconinit);
2050 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
2051 const struct ath9k_beacon_state *bs)
2053 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2054 struct ath9k_hw_capabilities *pCap = &ah->caps;
2055 struct ath_common *common = ath9k_hw_common(ah);
2057 ENABLE_REGWRITE_BUFFER(ah);
2059 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
2061 REG_WRITE(ah, AR_BEACON_PERIOD,
2062 TU_TO_USEC(bs->bs_intval));
2063 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
2064 TU_TO_USEC(bs->bs_intval));
2066 REGWRITE_BUFFER_FLUSH(ah);
2068 REG_RMW_FIELD(ah, AR_RSSI_THR,
2069 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
2071 beaconintval = bs->bs_intval;
2073 if (bs->bs_sleepduration > beaconintval)
2074 beaconintval = bs->bs_sleepduration;
2076 dtimperiod = bs->bs_dtimperiod;
2077 if (bs->bs_sleepduration > dtimperiod)
2078 dtimperiod = bs->bs_sleepduration;
2080 if (beaconintval == dtimperiod)
2081 nextTbtt = bs->bs_nextdtim;
2083 nextTbtt = bs->bs_nexttbtt;
2085 ath_dbg(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
2086 ath_dbg(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
2087 ath_dbg(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
2088 ath_dbg(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
2090 ENABLE_REGWRITE_BUFFER(ah);
2092 REG_WRITE(ah, AR_NEXT_DTIM,
2093 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
2094 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
2096 REG_WRITE(ah, AR_SLEEP1,
2097 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
2098 | AR_SLEEP1_ASSUME_DTIM);
2100 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
2101 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
2103 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
2105 REG_WRITE(ah, AR_SLEEP2,
2106 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
2108 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
2109 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
2111 REGWRITE_BUFFER_FLUSH(ah);
2113 REG_SET_BIT(ah, AR_TIMER_MODE,
2114 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
2117 /* TSF Out of Range Threshold */
2118 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
2120 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
2122 /*******************/
2123 /* HW Capabilities */
2124 /*******************/
2126 static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask)
2128 eeprom_chainmask &= chip_chainmask;
2129 if (eeprom_chainmask)
2130 return eeprom_chainmask;
2132 return chip_chainmask;
2135 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
2137 struct ath9k_hw_capabilities *pCap = &ah->caps;
2138 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2139 struct ath_common *common = ath9k_hw_common(ah);
2140 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
2141 unsigned int chip_chainmask;
2144 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
2146 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
2147 regulatory->current_rd = eeval;
2149 if (ah->opmode != NL80211_IFTYPE_AP &&
2150 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
2151 if (regulatory->current_rd == 0x64 ||
2152 regulatory->current_rd == 0x65)
2153 regulatory->current_rd += 5;
2154 else if (regulatory->current_rd == 0x41)
2155 regulatory->current_rd = 0x43;
2156 ath_dbg(common, ATH_DBG_REGULATORY,
2157 "regdomain mapped to 0x%x\n", regulatory->current_rd);
2160 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
2161 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
2163 "no band has been marked as supported in EEPROM\n");
2167 if (eeval & AR5416_OPFLAGS_11A)
2168 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
2170 if (eeval & AR5416_OPFLAGS_11G)
2171 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
2173 if (AR_SREV_9485(ah) || AR_SREV_9285(ah) || AR_SREV_9330(ah))
2175 else if (!AR_SREV_9280_20_OR_LATER(ah))
2177 else if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9340(ah))
2182 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
2184 * For AR9271 we will temporarilly uses the rx chainmax as read from
2187 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
2188 !(eeval & AR5416_OPFLAGS_11A) &&
2189 !(AR_SREV_9271(ah)))
2190 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
2191 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
2192 else if (AR_SREV_9100(ah))
2193 pCap->rx_chainmask = 0x7;
2195 /* Use rx_chainmask from EEPROM. */
2196 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
2198 pCap->tx_chainmask = fixup_chainmask(chip_chainmask, pCap->tx_chainmask);
2199 pCap->rx_chainmask = fixup_chainmask(chip_chainmask, pCap->rx_chainmask);
2200 ah->txchainmask = pCap->tx_chainmask;
2201 ah->rxchainmask = pCap->rx_chainmask;
2203 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
2205 /* enable key search for every frame in an aggregate */
2206 if (AR_SREV_9300_20_OR_LATER(ah))
2207 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
2209 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
2211 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
2212 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2214 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
2216 if (AR_SREV_9271(ah))
2217 pCap->num_gpio_pins = AR9271_NUM_GPIO;
2218 else if (AR_DEVID_7010(ah))
2219 pCap->num_gpio_pins = AR7010_NUM_GPIO;
2220 else if (AR_SREV_9300_20_OR_LATER(ah))
2221 pCap->num_gpio_pins = AR9300_NUM_GPIO;
2222 else if (AR_SREV_9287_11_OR_LATER(ah))
2223 pCap->num_gpio_pins = AR9287_NUM_GPIO;
2224 else if (AR_SREV_9285_12_OR_LATER(ah))
2225 pCap->num_gpio_pins = AR9285_NUM_GPIO;
2226 else if (AR_SREV_9280_20_OR_LATER(ah))
2227 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2229 pCap->num_gpio_pins = AR_NUM_GPIO;
2231 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
2232 pCap->hw_caps |= ATH9K_HW_CAP_CST;
2233 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
2235 pCap->rts_aggr_limit = (8 * 1024);
2238 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2239 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2240 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2242 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2243 ah->rfkill_polarity =
2244 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
2246 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
2249 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
2250 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2252 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
2254 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
2255 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2257 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
2259 if (common->btcoex_enabled) {
2260 if (AR_SREV_9300_20_OR_LATER(ah)) {
2261 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
2262 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO_9300;
2263 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO_9300;
2264 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO_9300;
2265 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
2266 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO_9280;
2267 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO_9280;
2269 if (AR_SREV_9285(ah)) {
2270 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
2271 btcoex_hw->btpriority_gpio =
2272 ATH_BTPRIORITY_GPIO_9285;
2274 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
2278 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
2281 if (AR_SREV_9300_20_OR_LATER(ah)) {
2282 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
2283 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah))
2284 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
2286 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2287 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2288 pCap->rx_status_len = sizeof(struct ar9003_rxs);
2289 pCap->tx_desc_len = sizeof(struct ar9003_txc);
2290 pCap->txs_len = sizeof(struct ar9003_txs);
2291 if (!ah->config.paprd_disable &&
2292 ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
2293 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
2295 pCap->tx_desc_len = sizeof(struct ath_desc);
2296 if (AR_SREV_9280_20(ah))
2297 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
2300 if (AR_SREV_9300_20_OR_LATER(ah))
2301 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2303 if (AR_SREV_9300_20_OR_LATER(ah))
2304 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
2306 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
2307 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2309 if (AR_SREV_9285(ah))
2310 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
2312 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2313 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1))
2314 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2316 if (AR_SREV_9300_20_OR_LATER(ah)) {
2317 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
2318 pCap->hw_caps |= ATH9K_HW_CAP_APM;
2322 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
2323 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2325 * enable the diversity-combining algorithm only when
2326 * both enable_lna_div and enable_fast_div are set
2327 * Table for Diversity
2328 * ant_div_alt_lnaconf bit 0-1
2329 * ant_div_main_lnaconf bit 2-3
2330 * ant_div_alt_gaintb bit 4
2331 * ant_div_main_gaintb bit 5
2332 * enable_ant_div_lnadiv bit 6
2333 * enable_ant_fast_div bit 7
2335 if ((ant_div_ctl1 >> 0x6) == 0x3)
2336 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2339 if (AR_SREV_9485_10(ah)) {
2340 pCap->pcie_lcr_extsync_en = true;
2341 pCap->pcie_lcr_offset = 0x80;
2344 tx_chainmask = pCap->tx_chainmask;
2345 rx_chainmask = pCap->rx_chainmask;
2346 while (tx_chainmask || rx_chainmask) {
2347 if (tx_chainmask & BIT(0))
2348 pCap->max_txchains++;
2349 if (rx_chainmask & BIT(0))
2350 pCap->max_rxchains++;
2356 if (AR_SREV_9300_20_OR_LATER(ah)) {
2357 ah->enabled_cals |= TX_IQ_CAL;
2358 if (!AR_SREV_9330(ah))
2359 ah->enabled_cals |= TX_IQ_ON_AGC_CAL;
2361 if (AR_SREV_9462(ah))
2362 pCap->hw_caps |= ATH9K_HW_CAP_RTT | ATH9K_HW_CAP_MCI;
2367 /****************************/
2368 /* GPIO / RFKILL / Antennae */
2369 /****************************/
2371 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
2375 u32 gpio_shift, tmp;
2378 addr = AR_GPIO_OUTPUT_MUX3;
2380 addr = AR_GPIO_OUTPUT_MUX2;
2382 addr = AR_GPIO_OUTPUT_MUX1;
2384 gpio_shift = (gpio % 6) * 5;
2386 if (AR_SREV_9280_20_OR_LATER(ah)
2387 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2388 REG_RMW(ah, addr, (type << gpio_shift),
2389 (0x1f << gpio_shift));
2391 tmp = REG_READ(ah, addr);
2392 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2393 tmp &= ~(0x1f << gpio_shift);
2394 tmp |= (type << gpio_shift);
2395 REG_WRITE(ah, addr, tmp);
2399 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
2403 BUG_ON(gpio >= ah->caps.num_gpio_pins);
2405 if (AR_DEVID_7010(ah)) {
2407 REG_RMW(ah, AR7010_GPIO_OE,
2408 (AR7010_GPIO_OE_AS_INPUT << gpio_shift),
2409 (AR7010_GPIO_OE_MASK << gpio_shift));
2413 gpio_shift = gpio << 1;
2416 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2417 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2419 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
2421 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
2423 #define MS_REG_READ(x, y) \
2424 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2426 if (gpio >= ah->caps.num_gpio_pins)
2429 if (AR_DEVID_7010(ah)) {
2431 val = REG_READ(ah, AR7010_GPIO_IN);
2432 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
2433 } else if (AR_SREV_9300_20_OR_LATER(ah))
2434 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) &
2435 AR_GPIO_BIT(gpio)) != 0;
2436 else if (AR_SREV_9271(ah))
2437 return MS_REG_READ(AR9271, gpio) != 0;
2438 else if (AR_SREV_9287_11_OR_LATER(ah))
2439 return MS_REG_READ(AR9287, gpio) != 0;
2440 else if (AR_SREV_9285_12_OR_LATER(ah))
2441 return MS_REG_READ(AR9285, gpio) != 0;
2442 else if (AR_SREV_9280_20_OR_LATER(ah))
2443 return MS_REG_READ(AR928X, gpio) != 0;
2445 return MS_REG_READ(AR, gpio) != 0;
2447 EXPORT_SYMBOL(ath9k_hw_gpio_get);
2449 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
2454 if (AR_DEVID_7010(ah)) {
2456 REG_RMW(ah, AR7010_GPIO_OE,
2457 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
2458 (AR7010_GPIO_OE_MASK << gpio_shift));
2462 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2463 gpio_shift = 2 * gpio;
2466 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2467 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2469 EXPORT_SYMBOL(ath9k_hw_cfg_output);
2471 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
2473 if (AR_DEVID_7010(ah)) {
2475 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
2480 if (AR_SREV_9271(ah))
2483 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2486 EXPORT_SYMBOL(ath9k_hw_set_gpio);
2488 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
2490 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
2492 EXPORT_SYMBOL(ath9k_hw_getdefantenna);
2494 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
2496 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
2498 EXPORT_SYMBOL(ath9k_hw_setantenna);
2500 /*********************/
2501 /* General Operation */
2502 /*********************/
2504 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
2506 u32 bits = REG_READ(ah, AR_RX_FILTER);
2507 u32 phybits = REG_READ(ah, AR_PHY_ERR);
2509 if (phybits & AR_PHY_ERR_RADAR)
2510 bits |= ATH9K_RX_FILTER_PHYRADAR;
2511 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2512 bits |= ATH9K_RX_FILTER_PHYERR;
2516 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
2518 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
2522 ENABLE_REGWRITE_BUFFER(ah);
2524 if (AR_SREV_9462(ah))
2525 bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER;
2527 REG_WRITE(ah, AR_RX_FILTER, bits);
2530 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2531 phybits |= AR_PHY_ERR_RADAR;
2532 if (bits & ATH9K_RX_FILTER_PHYERR)
2533 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2534 REG_WRITE(ah, AR_PHY_ERR, phybits);
2537 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2539 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2541 REGWRITE_BUFFER_FLUSH(ah);
2543 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
2545 bool ath9k_hw_phy_disable(struct ath_hw *ah)
2547 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2550 ath9k_hw_init_pll(ah, NULL);
2553 EXPORT_SYMBOL(ath9k_hw_phy_disable);
2555 bool ath9k_hw_disable(struct ath_hw *ah)
2557 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2560 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2563 ath9k_hw_init_pll(ah, NULL);
2566 EXPORT_SYMBOL(ath9k_hw_disable);
2568 static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan)
2570 enum eeprom_param gain_param;
2572 if (IS_CHAN_2GHZ(chan))
2573 gain_param = EEP_ANTENNA_GAIN_2G;
2575 gain_param = EEP_ANTENNA_GAIN_5G;
2577 return ah->eep_ops->get_eeprom(ah, gain_param);
2580 void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan)
2582 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2583 struct ieee80211_channel *channel;
2584 int chan_pwr, new_pwr, max_gain;
2585 int ant_gain, ant_reduction = 0;
2590 channel = chan->chan;
2591 chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER);
2592 new_pwr = min_t(int, chan_pwr, reg->power_limit);
2593 max_gain = chan_pwr - new_pwr + channel->max_antenna_gain * 2;
2595 ant_gain = get_antenna_gain(ah, chan);
2596 if (ant_gain > max_gain)
2597 ant_reduction = ant_gain - max_gain;
2599 ah->eep_ops->set_txpower(ah, chan,
2600 ath9k_regd_get_ctl(reg, chan),
2601 ant_reduction, new_pwr, false);
2604 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
2606 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2607 struct ath9k_channel *chan = ah->curchan;
2608 struct ieee80211_channel *channel = chan->chan;
2610 reg->power_limit = min_t(u32, limit, MAX_RATE_POWER);
2612 channel->max_power = MAX_RATE_POWER / 2;
2614 ath9k_hw_apply_txpower(ah, chan);
2617 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2);
2619 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
2621 void ath9k_hw_setopmode(struct ath_hw *ah)
2623 ath9k_hw_set_operating_mode(ah, ah->opmode);
2625 EXPORT_SYMBOL(ath9k_hw_setopmode);
2627 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
2629 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2630 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
2632 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
2634 void ath9k_hw_write_associd(struct ath_hw *ah)
2636 struct ath_common *common = ath9k_hw_common(ah);
2638 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2639 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2640 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2642 EXPORT_SYMBOL(ath9k_hw_write_associd);
2644 #define ATH9K_MAX_TSF_READ 10
2646 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
2648 u32 tsf_lower, tsf_upper1, tsf_upper2;
2651 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2652 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2653 tsf_lower = REG_READ(ah, AR_TSF_L32);
2654 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2655 if (tsf_upper2 == tsf_upper1)
2657 tsf_upper1 = tsf_upper2;
2660 WARN_ON( i == ATH9K_MAX_TSF_READ );
2662 return (((u64)tsf_upper1 << 32) | tsf_lower);
2664 EXPORT_SYMBOL(ath9k_hw_gettsf64);
2666 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
2668 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
2669 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
2671 EXPORT_SYMBOL(ath9k_hw_settsf64);
2673 void ath9k_hw_reset_tsf(struct ath_hw *ah)
2675 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2676 AH_TSF_WRITE_TIMEOUT))
2677 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
2678 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
2680 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2682 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
2684 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
2687 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
2689 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
2691 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
2693 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
2695 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
2698 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
2699 macmode = AR_2040_JOINED_RX_CLEAR;
2703 REG_WRITE(ah, AR_2040_MODE, macmode);
2706 /* HW Generic timers configuration */
2708 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2710 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2711 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2712 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2713 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2714 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2715 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2716 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2717 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2718 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2719 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2720 AR_NDP2_TIMER_MODE, 0x0002},
2721 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2722 AR_NDP2_TIMER_MODE, 0x0004},
2723 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2724 AR_NDP2_TIMER_MODE, 0x0008},
2725 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2726 AR_NDP2_TIMER_MODE, 0x0010},
2727 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2728 AR_NDP2_TIMER_MODE, 0x0020},
2729 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2730 AR_NDP2_TIMER_MODE, 0x0040},
2731 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2732 AR_NDP2_TIMER_MODE, 0x0080}
2735 /* HW generic timer primitives */
2737 /* compute and clear index of rightmost 1 */
2738 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2748 return timer_table->gen_timer_index[b];
2751 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
2753 return REG_READ(ah, AR_TSF_L32);
2755 EXPORT_SYMBOL(ath9k_hw_gettsf32);
2757 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2758 void (*trigger)(void *),
2759 void (*overflow)(void *),
2763 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2764 struct ath_gen_timer *timer;
2766 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2768 if (timer == NULL) {
2769 ath_err(ath9k_hw_common(ah),
2770 "Failed to allocate memory for hw timer[%d]\n",
2775 /* allocate a hardware generic timer slot */
2776 timer_table->timers[timer_index] = timer;
2777 timer->index = timer_index;
2778 timer->trigger = trigger;
2779 timer->overflow = overflow;
2784 EXPORT_SYMBOL(ath_gen_timer_alloc);
2786 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2787 struct ath_gen_timer *timer,
2791 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2792 u32 tsf, timer_next;
2794 BUG_ON(!timer_period);
2796 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
2798 tsf = ath9k_hw_gettsf32(ah);
2800 timer_next = tsf + trig_timeout;
2802 ath_dbg(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
2803 "current tsf %x period %x timer_next %x\n",
2804 tsf, timer_period, timer_next);
2807 * Program generic timer registers
2809 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2811 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
2813 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2814 gen_tmr_configuration[timer->index].mode_mask);
2816 if (AR_SREV_9462(ah)) {
2818 * Starting from AR9462, each generic timer can select which tsf
2819 * to use. But we still follow the old rule, 0 - 7 use tsf and
2822 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN))
2823 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
2824 (1 << timer->index));
2826 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
2827 (1 << timer->index));
2830 /* Enable both trigger and thresh interrupt masks */
2831 REG_SET_BIT(ah, AR_IMR_S5,
2832 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2833 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2835 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
2837 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
2839 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2841 if ((timer->index < AR_FIRST_NDP_TIMER) ||
2842 (timer->index >= ATH_MAX_GEN_TIMER)) {
2846 /* Clear generic timer enable bits. */
2847 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2848 gen_tmr_configuration[timer->index].mode_mask);
2850 /* Disable both trigger and thresh interrupt masks */
2851 REG_CLR_BIT(ah, AR_IMR_S5,
2852 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2853 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2855 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
2857 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
2859 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
2861 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2863 /* free the hardware generic timer slot */
2864 timer_table->timers[timer->index] = NULL;
2867 EXPORT_SYMBOL(ath_gen_timer_free);
2870 * Generic Timer Interrupts handling
2872 void ath_gen_timer_isr(struct ath_hw *ah)
2874 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2875 struct ath_gen_timer *timer;
2876 struct ath_common *common = ath9k_hw_common(ah);
2877 u32 trigger_mask, thresh_mask, index;
2879 /* get hardware generic timer interrupt status */
2880 trigger_mask = ah->intr_gen_timer_trigger;
2881 thresh_mask = ah->intr_gen_timer_thresh;
2882 trigger_mask &= timer_table->timer_mask.val;
2883 thresh_mask &= timer_table->timer_mask.val;
2885 trigger_mask &= ~thresh_mask;
2887 while (thresh_mask) {
2888 index = rightmost_index(timer_table, &thresh_mask);
2889 timer = timer_table->timers[index];
2891 ath_dbg(common, ATH_DBG_HWTIMER,
2892 "TSF overflow for Gen timer %d\n", index);
2893 timer->overflow(timer->arg);
2896 while (trigger_mask) {
2897 index = rightmost_index(timer_table, &trigger_mask);
2898 timer = timer_table->timers[index];
2900 ath_dbg(common, ATH_DBG_HWTIMER,
2901 "Gen timer[%d] trigger\n", index);
2902 timer->trigger(timer->arg);
2905 EXPORT_SYMBOL(ath_gen_timer_isr);
2911 void ath9k_hw_htc_resetinit(struct ath_hw *ah)
2913 ah->htc_reset_init = true;
2915 EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
2920 } ath_mac_bb_names[] = {
2921 /* Devices with external radios */
2922 { AR_SREV_VERSION_5416_PCI, "5416" },
2923 { AR_SREV_VERSION_5416_PCIE, "5418" },
2924 { AR_SREV_VERSION_9100, "9100" },
2925 { AR_SREV_VERSION_9160, "9160" },
2926 /* Single-chip solutions */
2927 { AR_SREV_VERSION_9280, "9280" },
2928 { AR_SREV_VERSION_9285, "9285" },
2929 { AR_SREV_VERSION_9287, "9287" },
2930 { AR_SREV_VERSION_9271, "9271" },
2931 { AR_SREV_VERSION_9300, "9300" },
2932 { AR_SREV_VERSION_9330, "9330" },
2933 { AR_SREV_VERSION_9340, "9340" },
2934 { AR_SREV_VERSION_9485, "9485" },
2935 { AR_SREV_VERSION_9462, "9462" },
2938 /* For devices with external radios */
2942 } ath_rf_names[] = {
2944 { AR_RAD5133_SREV_MAJOR, "5133" },
2945 { AR_RAD5122_SREV_MAJOR, "5122" },
2946 { AR_RAD2133_SREV_MAJOR, "2133" },
2947 { AR_RAD2122_SREV_MAJOR, "2122" }
2951 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2953 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2957 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2958 if (ath_mac_bb_names[i].version == mac_bb_version) {
2959 return ath_mac_bb_names[i].name;
2967 * Return the RF name. "????" is returned if the RF is unknown.
2968 * Used for devices with external radios.
2970 static const char *ath9k_hw_rf_name(u16 rf_version)
2974 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2975 if (ath_rf_names[i].version == rf_version) {
2976 return ath_rf_names[i].name;
2983 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
2987 /* chipsets >= AR9280 are single-chip */
2988 if (AR_SREV_9280_20_OR_LATER(ah)) {
2989 used = snprintf(hw_name, len,
2990 "Atheros AR%s Rev:%x",
2991 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2992 ah->hw_version.macRev);
2995 used = snprintf(hw_name, len,
2996 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
2997 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2998 ah->hw_version.macRev,
2999 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
3000 AR_RADIO_SREV_MAJOR)),
3001 ah->hw_version.phyRev);
3004 hw_name[used] = '\0';
3006 EXPORT_SYMBOL(ath9k_hw_name);