2 * Copyright (c) 2010-2011 Atheros Communications, Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21 * Channel Register Map
23 #define AR_CHAN_BASE 0x9800
25 #define AR_PHY_TIMING1 (AR_CHAN_BASE + 0x0)
26 #define AR_PHY_TIMING2 (AR_CHAN_BASE + 0x4)
27 #define AR_PHY_TIMING3 (AR_CHAN_BASE + 0x8)
28 #define AR_PHY_TIMING4 (AR_CHAN_BASE + 0xc)
29 #define AR_PHY_TIMING5 (AR_CHAN_BASE + 0x10)
30 #define AR_PHY_TIMING6 (AR_CHAN_BASE + 0x14)
31 #define AR_PHY_TIMING11 (AR_CHAN_BASE + 0x18)
32 #define AR_PHY_SPUR_REG (AR_CHAN_BASE + 0x1c)
33 #define AR_PHY_RX_IQCAL_CORR_B0 (AR_CHAN_BASE + 0xdc)
34 #define AR_PHY_TX_IQCAL_CONTROL_3 (AR_CHAN_BASE + 0xb0)
35 #define AR_PHY_TIMING_CONTROL4_DO_GAIN_DC_IQ_CAL_SHIFT 16
37 #define AR_PHY_TIMING11_SPUR_FREQ_SD 0x3FF00000
38 #define AR_PHY_TIMING11_SPUR_FREQ_SD_S 20
40 #define AR_PHY_TIMING11_SPUR_DELTA_PHASE 0x000FFFFF
41 #define AR_PHY_TIMING11_SPUR_DELTA_PHASE_S 0
43 #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC 0x40000000
44 #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC_S 30
46 #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR 0x80000000
47 #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR_S 31
49 #define AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT 0x4000000
50 #define AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT_S 26
52 #define AR_PHY_SPUR_REG_ENABLE_MASK_PPM 0x20000 /* bins move with freq offset */
53 #define AR_PHY_SPUR_REG_ENABLE_MASK_PPM_S 17
54 #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH 0x000000FF
55 #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0
56 #define AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI 0x00000100
57 #define AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI_S 8
58 #define AR_PHY_SPUR_REG_MASK_RATE_CNTL 0x03FC0000
59 #define AR_PHY_SPUR_REG_MASK_RATE_CNTL_S 18
61 #define AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN 0x20000000
62 #define AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN_S 29
64 #define AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN 0x80000000
65 #define AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN_S 31
67 #define AR_PHY_FIND_SIG_LOW (AR_CHAN_BASE + 0x20)
69 #define AR_PHY_SFCORR (AR_CHAN_BASE + 0x24)
70 #define AR_PHY_SFCORR_LOW (AR_CHAN_BASE + 0x28)
71 #define AR_PHY_SFCORR_EXT (AR_CHAN_BASE + 0x2c)
73 #define AR_PHY_EXT_CCA (AR_CHAN_BASE + 0x30)
74 #define AR_PHY_RADAR_0 (AR_CHAN_BASE + 0x34)
75 #define AR_PHY_RADAR_1 (AR_CHAN_BASE + 0x38)
76 #define AR_PHY_RADAR_EXT (AR_CHAN_BASE + 0x3c)
77 #define AR_PHY_MULTICHAIN_CTRL (AR_CHAN_BASE + 0x80)
78 #define AR_PHY_PERCHAIN_CSD (AR_CHAN_BASE + 0x84)
80 #define AR_PHY_TX_PHASE_RAMP_0 (AR_CHAN_BASE + 0xd0)
81 #define AR_PHY_ADC_GAIN_DC_CORR_0 (AR_CHAN_BASE + 0xd4)
82 #define AR_PHY_IQ_ADC_MEAS_0_B0 (AR_CHAN_BASE + 0xc0)
83 #define AR_PHY_IQ_ADC_MEAS_1_B0 (AR_CHAN_BASE + 0xc4)
84 #define AR_PHY_IQ_ADC_MEAS_2_B0 (AR_CHAN_BASE + 0xc8)
85 #define AR_PHY_IQ_ADC_MEAS_3_B0 (AR_CHAN_BASE + 0xcc)
87 /* The following registers changed position from AR9300 1.0 to AR9300 2.0 */
88 #define AR_PHY_TX_PHASE_RAMP_0_9300_10 (AR_CHAN_BASE + 0xd0 - 0x10)
89 #define AR_PHY_ADC_GAIN_DC_CORR_0_9300_10 (AR_CHAN_BASE + 0xd4 - 0x10)
90 #define AR_PHY_IQ_ADC_MEAS_0_B0_9300_10 (AR_CHAN_BASE + 0xc0 + 0x8)
91 #define AR_PHY_IQ_ADC_MEAS_1_B0_9300_10 (AR_CHAN_BASE + 0xc4 + 0x8)
92 #define AR_PHY_IQ_ADC_MEAS_2_B0_9300_10 (AR_CHAN_BASE + 0xc8 + 0x8)
93 #define AR_PHY_IQ_ADC_MEAS_3_B0_9300_10 (AR_CHAN_BASE + 0xcc + 0x8)
95 #define AR_PHY_TX_CRC (AR_CHAN_BASE + 0xa0)
96 #define AR_PHY_TST_DAC_CONST (AR_CHAN_BASE + 0xa4)
97 #define AR_PHY_SPUR_REPORT_0 (AR_CHAN_BASE + 0xa8)
98 #define AR_PHY_CHAN_INFO_TAB_0 (AR_CHAN_BASE + 0x300)
101 * Channel Field Definitions
103 #define AR_PHY_TIMING2_USE_FORCE_PPM 0x00001000
104 #define AR_PHY_TIMING2_FORCE_PPM_VAL 0x00000fff
105 #define AR_PHY_TIMING3_DSC_MAN 0xFFFE0000
106 #define AR_PHY_TIMING3_DSC_MAN_S 17
107 #define AR_PHY_TIMING3_DSC_EXP 0x0001E000
108 #define AR_PHY_TIMING3_DSC_EXP_S 13
109 #define AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX 0xF000
110 #define AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX_S 12
111 #define AR_PHY_TIMING4_DO_CAL 0x10000
113 #define AR_PHY_TIMING4_ENABLE_PILOT_MASK 0x10000000
114 #define AR_PHY_TIMING4_ENABLE_PILOT_MASK_S 28
115 #define AR_PHY_TIMING4_ENABLE_CHAN_MASK 0x20000000
116 #define AR_PHY_TIMING4_ENABLE_CHAN_MASK_S 29
118 #define AR_PHY_TIMING4_ENABLE_SPUR_FILTER 0x40000000
119 #define AR_PHY_TIMING4_ENABLE_SPUR_FILTER_S 30
120 #define AR_PHY_TIMING4_ENABLE_SPUR_RSSI 0x80000000
121 #define AR_PHY_TIMING4_ENABLE_SPUR_RSSI_S 31
123 #define AR_PHY_NEW_ADC_GAIN_CORR_ENABLE 0x40000000
124 #define AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE 0x80000000
125 #define AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW 0x00000001
126 #define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW 0x00003F00
127 #define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S 8
128 #define AR_PHY_SFCORR_LOW_M1_THRESH_LOW 0x001FC000
129 #define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_S 14
130 #define AR_PHY_SFCORR_LOW_M2_THRESH_LOW 0x0FE00000
131 #define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_S 21
132 #define AR_PHY_SFCORR_M2COUNT_THR 0x0000001F
133 #define AR_PHY_SFCORR_M2COUNT_THR_S 0
134 #define AR_PHY_SFCORR_M1_THRESH 0x00FE0000
135 #define AR_PHY_SFCORR_M1_THRESH_S 17
136 #define AR_PHY_SFCORR_M2_THRESH 0x7F000000
137 #define AR_PHY_SFCORR_M2_THRESH_S 24
138 #define AR_PHY_SFCORR_EXT_M1_THRESH 0x0000007F
139 #define AR_PHY_SFCORR_EXT_M1_THRESH_S 0
140 #define AR_PHY_SFCORR_EXT_M2_THRESH 0x00003F80
141 #define AR_PHY_SFCORR_EXT_M2_THRESH_S 7
142 #define AR_PHY_SFCORR_EXT_M1_THRESH_LOW 0x001FC000
143 #define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_S 14
144 #define AR_PHY_SFCORR_EXT_M2_THRESH_LOW 0x0FE00000
145 #define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_S 21
146 #define AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD 0x10000000
147 #define AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD_S 28
148 #define AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S 28
149 #define AR_PHY_EXT_CCA_THRESH62 0x007F0000
150 #define AR_PHY_EXT_CCA_THRESH62_S 16
151 #define AR_PHY_EXTCHN_PWRTHR1_ANT_DIV_ALT_ANT_MINGAINIDX 0x0000FF00
152 #define AR_PHY_EXTCHN_PWRTHR1_ANT_DIV_ALT_ANT_MINGAINIDX_S 8
153 #define AR_PHY_EXT_MINCCA_PWR 0x01FF0000
154 #define AR_PHY_EXT_MINCCA_PWR_S 16
155 #define AR_PHY_EXT_CYCPWR_THR1 0x0000FE00L
156 #define AR_PHY_EXT_CYCPWR_THR1_S 9
157 #define AR_PHY_TIMING5_CYCPWR_THR1 0x000000FE
158 #define AR_PHY_TIMING5_CYCPWR_THR1_S 1
159 #define AR_PHY_TIMING5_CYCPWR_THR1_ENABLE 0x00000001
160 #define AR_PHY_TIMING5_CYCPWR_THR1_ENABLE_S 0
161 #define AR_PHY_TIMING5_CYCPWR_THR1A 0x007F0000
162 #define AR_PHY_TIMING5_CYCPWR_THR1A_S 16
163 #define AR_PHY_TIMING5_RSSI_THR1A (0x7F << 16)
164 #define AR_PHY_TIMING5_RSSI_THR1A_S 16
165 #define AR_PHY_TIMING5_RSSI_THR1A_ENA (0x1 << 15)
166 #define AR_PHY_RADAR_0_ENA 0x00000001
167 #define AR_PHY_RADAR_0_FFT_ENA 0x80000000
168 #define AR_PHY_RADAR_0_INBAND 0x0000003e
169 #define AR_PHY_RADAR_0_INBAND_S 1
170 #define AR_PHY_RADAR_0_PRSSI 0x00000FC0
171 #define AR_PHY_RADAR_0_PRSSI_S 6
172 #define AR_PHY_RADAR_0_HEIGHT 0x0003F000
173 #define AR_PHY_RADAR_0_HEIGHT_S 12
174 #define AR_PHY_RADAR_0_RRSSI 0x00FC0000
175 #define AR_PHY_RADAR_0_RRSSI_S 18
176 #define AR_PHY_RADAR_0_FIRPWR 0x7F000000
177 #define AR_PHY_RADAR_0_FIRPWR_S 24
178 #define AR_PHY_RADAR_1_RELPWR_ENA 0x00800000
179 #define AR_PHY_RADAR_1_USE_FIR128 0x00400000
180 #define AR_PHY_RADAR_1_RELPWR_THRESH 0x003F0000
181 #define AR_PHY_RADAR_1_RELPWR_THRESH_S 16
182 #define AR_PHY_RADAR_1_BLOCK_CHECK 0x00008000
183 #define AR_PHY_RADAR_1_MAX_RRSSI 0x00004000
184 #define AR_PHY_RADAR_1_RELSTEP_CHECK 0x00002000
185 #define AR_PHY_RADAR_1_RELSTEP_THRESH 0x00001F00
186 #define AR_PHY_RADAR_1_RELSTEP_THRESH_S 8
187 #define AR_PHY_RADAR_1_MAXLEN 0x000000FF
188 #define AR_PHY_RADAR_1_MAXLEN_S 0
189 #define AR_PHY_RADAR_EXT_ENA 0x00004000
190 #define AR_PHY_RADAR_DC_PWR_THRESH 0x007f8000
191 #define AR_PHY_RADAR_DC_PWR_THRESH_S 15
192 #define AR_PHY_RADAR_LB_DC_CAP 0x7f800000
193 #define AR_PHY_RADAR_LB_DC_CAP_S 23
194 #define AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW (0x3f << 6)
195 #define AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW_S 6
196 #define AR_PHY_FIND_SIG_LOW_FIRPWR (0x7f << 12)
197 #define AR_PHY_FIND_SIG_LOW_FIRPWR_S 12
198 #define AR_PHY_FIND_SIG_LOW_FIRPWR_SIGN_BIT 19
199 #define AR_PHY_FIND_SIG_LOW_RELSTEP 0x1f
200 #define AR_PHY_FIND_SIG_LOW_RELSTEP_S 0
201 #define AR_PHY_FIND_SIG_LOW_RELSTEP_SIGN_BIT 5
202 #define AR_PHY_CHAN_INFO_TAB_S2_READ 0x00000008
203 #define AR_PHY_CHAN_INFO_TAB_S2_READ_S 3
204 #define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF 0x0000007F
205 #define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF_S 0
206 #define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF 0x00003F80
207 #define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF_S 7
208 #define AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE 0x00004000
209 #define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF 0x003f8000
210 #define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF_S 15
211 #define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF 0x1fc00000
212 #define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF_S 22
217 #define AR_MRC_BASE 0x9c00
219 #define AR_PHY_TIMING_3A (AR_MRC_BASE + 0x0)
220 #define AR_PHY_LDPC_CNTL1 (AR_MRC_BASE + 0x4)
221 #define AR_PHY_LDPC_CNTL2 (AR_MRC_BASE + 0x8)
222 #define AR_PHY_PILOT_SPUR_MASK (AR_MRC_BASE + 0xc)
223 #define AR_PHY_CHAN_SPUR_MASK (AR_MRC_BASE + 0x10)
224 #define AR_PHY_SGI_DELTA (AR_MRC_BASE + 0x14)
225 #define AR_PHY_ML_CNTL_1 (AR_MRC_BASE + 0x18)
226 #define AR_PHY_ML_CNTL_2 (AR_MRC_BASE + 0x1c)
227 #define AR_PHY_TST_ADC (AR_MRC_BASE + 0x20)
229 #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A 0x00000FE0
230 #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_S 5
231 #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A 0x1F
232 #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A_S 0
233 #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B 0x00FE0000
234 #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B_S 17
235 #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_B 0x0001F000
236 #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_B_S 12
238 #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A 0x00000FE0
239 #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_S 5
240 #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A 0x1F
241 #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A_S 0
242 #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B 0x00FE0000
243 #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B_S 17
244 #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_B 0x0001F000
245 #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_B_S 12
249 * MRC Feild Definitions
251 #define AR_PHY_SGI_DSC_MAN 0x0007FFF0
252 #define AR_PHY_SGI_DSC_MAN_S 4
253 #define AR_PHY_SGI_DSC_EXP 0x0000000F
254 #define AR_PHY_SGI_DSC_EXP_S 0
258 #define AR_BBB_BASE 0x9d00
263 #define AR_AGC_BASE 0x9e00
265 #define AR_PHY_SETTLING (AR_AGC_BASE + 0x0)
266 #define AR_PHY_FORCEMAX_GAINS_0 (AR_AGC_BASE + 0x4)
267 #define AR_PHY_GAINS_MINOFF0 (AR_AGC_BASE + 0x8)
268 #define AR_PHY_DESIRED_SZ (AR_AGC_BASE + 0xc)
269 #define AR_PHY_FIND_SIG (AR_AGC_BASE + 0x10)
270 #define AR_PHY_AGC (AR_AGC_BASE + 0x14)
271 #define AR_PHY_EXT_ATTEN_CTL_0 (AR_AGC_BASE + 0x18)
272 #define AR_PHY_CCA_0 (AR_AGC_BASE + 0x1c)
273 #define AR_PHY_CCA_CTRL_0 (AR_AGC_BASE + 0x20)
274 #define AR_PHY_RESTART (AR_AGC_BASE + 0x24)
277 * Antenna Diversity settings
279 #define AR_PHY_MC_GAIN_CTRL (AR_AGC_BASE + 0x28)
280 #define AR_ANT_DIV_CTRL_ALL 0x7e000000
281 #define AR_ANT_DIV_CTRL_ALL_S 25
282 #define AR_ANT_DIV_ENABLE 0x1000000
283 #define AR_ANT_DIV_ENABLE_S 24
286 #define AR_PHY_ANT_FAST_DIV_BIAS 0x00007e00
287 #define AR_PHY_ANT_FAST_DIV_BIAS_S 9
288 #define AR_PHY_ANT_SW_RX_PROT 0x00800000
289 #define AR_PHY_ANT_SW_RX_PROT_S 23
290 #define AR_PHY_ANT_DIV_LNADIV 0x01000000
291 #define AR_PHY_ANT_DIV_LNADIV_S 24
292 #define AR_PHY_ANT_DIV_ALT_LNACONF 0x06000000
293 #define AR_PHY_ANT_DIV_ALT_LNACONF_S 25
294 #define AR_PHY_ANT_DIV_MAIN_LNACONF 0x18000000
295 #define AR_PHY_ANT_DIV_MAIN_LNACONF_S 27
296 #define AR_PHY_ANT_DIV_ALT_GAINTB 0x20000000
297 #define AR_PHY_ANT_DIV_ALT_GAINTB_S 29
298 #define AR_PHY_ANT_DIV_MAIN_GAINTB 0x40000000
299 #define AR_PHY_ANT_DIV_MAIN_GAINTB_S 30
301 #define AR_PHY_EXTCHN_PWRTHR1 (AR_AGC_BASE + 0x2c)
302 #define AR_PHY_EXT_CHN_WIN (AR_AGC_BASE + 0x30)
303 #define AR_PHY_20_40_DET_THR (AR_AGC_BASE + 0x34)
304 #define AR_PHY_RIFS_SRCH (AR_AGC_BASE + 0x38)
305 #define AR_PHY_PEAK_DET_CTRL_1 (AR_AGC_BASE + 0x3c)
306 #define AR_PHY_PEAK_DET_CTRL_2 (AR_AGC_BASE + 0x40)
307 #define AR_PHY_RX_GAIN_BOUNDS_1 (AR_AGC_BASE + 0x44)
308 #define AR_PHY_RX_GAIN_BOUNDS_2 (AR_AGC_BASE + 0x48)
309 #define AR_PHY_RSSI_0 (AR_AGC_BASE + 0x180)
310 #define AR_PHY_SPUR_CCK_REP0 (AR_AGC_BASE + 0x184)
312 #define AR_PHY_CCK_DETECT (AR_AGC_BASE + 0x1c0)
313 #define AR_FAST_DIV_ENABLE 0x2000
314 #define AR_FAST_DIV_ENABLE_S 13
316 #define AR_PHY_DAG_CTRLCCK (AR_AGC_BASE + 0x1c4)
317 #define AR_PHY_IQCORR_CTRL_CCK (AR_AGC_BASE + 0x1c8)
319 #define AR_PHY_CCK_SPUR_MIT (AR_AGC_BASE + 0x1cc)
320 #define AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR 0x000001fe
321 #define AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR_S 1
322 #define AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE 0x60000000
323 #define AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE_S 29
324 #define AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT 0x00000001
325 #define AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT_S 0
326 #define AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ 0x1ffffe00
327 #define AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ_S 9
329 #define AR_PHY_MRC_CCK_CTRL (AR_AGC_BASE + 0x1d0)
330 #define AR_PHY_MRC_CCK_ENABLE 0x00000001
331 #define AR_PHY_MRC_CCK_ENABLE_S 0
332 #define AR_PHY_MRC_CCK_MUX_REG 0x00000002
333 #define AR_PHY_MRC_CCK_MUX_REG_S 1
335 #define AR_PHY_RX_OCGAIN (AR_AGC_BASE + 0x200)
337 #define AR_PHY_CCA_NOM_VAL_9300_2GHZ -110
338 #define AR_PHY_CCA_NOM_VAL_9300_5GHZ -115
339 #define AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ -125
340 #define AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ -125
341 #define AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ -95
342 #define AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ -100
344 #define AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_2GHZ -95
345 #define AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_5GHZ -100
347 #define AR_PHY_CCA_NOM_VAL_9462_2GHZ -127
348 #define AR_PHY_CCA_MIN_GOOD_VAL_9462_2GHZ -127
349 #define AR_PHY_CCA_MAX_GOOD_VAL_9462_2GHZ -60
350 #define AR_PHY_CCA_NOM_VAL_9462_5GHZ -127
351 #define AR_PHY_CCA_MIN_GOOD_VAL_9462_5GHZ -127
352 #define AR_PHY_CCA_MAX_GOOD_VAL_9462_5GHZ -60
354 #define AR_PHY_CCA_NOM_VAL_9330_2GHZ -118
356 #define AR9300_EXT_LNA_CTL_GPIO_AR9485 9
359 * AGC Field Definitions
361 #define AR_PHY_EXT_ATTEN_CTL_RXTX_MARGIN 0x00FC0000
362 #define AR_PHY_EXT_ATTEN_CTL_RXTX_MARGIN_S 18
363 #define AR_PHY_EXT_ATTEN_CTL_BSW_MARGIN 0x00003C00
364 #define AR_PHY_EXT_ATTEN_CTL_BSW_MARGIN_S 10
365 #define AR_PHY_EXT_ATTEN_CTL_BSW_ATTEN 0x0000001F
366 #define AR_PHY_EXT_ATTEN_CTL_BSW_ATTEN_S 0
367 #define AR_PHY_EXT_ATTEN_CTL_XATTEN2_MARGIN 0x003E0000
368 #define AR_PHY_EXT_ATTEN_CTL_XATTEN2_MARGIN_S 17
369 #define AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN 0x0001F000
370 #define AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN_S 12
371 #define AR_PHY_EXT_ATTEN_CTL_XATTEN2_DB 0x00000FC0
372 #define AR_PHY_EXT_ATTEN_CTL_XATTEN2_DB_S 6
373 #define AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB 0x0000003F
374 #define AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB_S 0
375 #define AR_PHY_RXGAIN_TXRX_ATTEN 0x0003F000
376 #define AR_PHY_RXGAIN_TXRX_ATTEN_S 12
377 #define AR_PHY_RXGAIN_TXRX_RF_MAX 0x007C0000
378 #define AR_PHY_RXGAIN_TXRX_RF_MAX_S 18
379 #define AR9280_PHY_RXGAIN_TXRX_ATTEN 0x00003F80
380 #define AR9280_PHY_RXGAIN_TXRX_ATTEN_S 7
381 #define AR9280_PHY_RXGAIN_TXRX_MARGIN 0x001FC000
382 #define AR9280_PHY_RXGAIN_TXRX_MARGIN_S 14
383 #define AR_PHY_SETTLING_SWITCH 0x00003F80
384 #define AR_PHY_SETTLING_SWITCH_S 7
385 #define AR_PHY_DESIRED_SZ_ADC 0x000000FF
386 #define AR_PHY_DESIRED_SZ_ADC_S 0
387 #define AR_PHY_DESIRED_SZ_PGA 0x0000FF00
388 #define AR_PHY_DESIRED_SZ_PGA_S 8
389 #define AR_PHY_DESIRED_SZ_TOT_DES 0x0FF00000
390 #define AR_PHY_DESIRED_SZ_TOT_DES_S 20
391 #define AR_PHY_MINCCA_PWR 0x1FF00000
392 #define AR_PHY_MINCCA_PWR_S 20
393 #define AR_PHY_CCA_THRESH62 0x0007F000
394 #define AR_PHY_CCA_THRESH62_S 12
395 #define AR9280_PHY_MINCCA_PWR 0x1FF00000
396 #define AR9280_PHY_MINCCA_PWR_S 20
397 #define AR9280_PHY_CCA_THRESH62 0x000FF000
398 #define AR9280_PHY_CCA_THRESH62_S 12
399 #define AR_PHY_EXT_CCA0_THRESH62 0x000000FF
400 #define AR_PHY_EXT_CCA0_THRESH62_S 0
401 #define AR_PHY_EXT_CCA0_THRESH62_1 0x000001FF
402 #define AR_PHY_EXT_CCA0_THRESH62_1_S 0
403 #define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK 0x0000003F
404 #define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S 0
405 #define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME 0x00001FC0
406 #define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_S 6
407 #define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV 0x2000
409 #define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR 0x00000200
410 #define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR_S 9
411 #define AR_PHY_DAG_CTRLCCK_RSSI_THR 0x0001FC00
412 #define AR_PHY_DAG_CTRLCCK_RSSI_THR_S 10
414 #define AR_PHY_RIFS_INIT_DELAY 0x3ff0000
415 #define AR_PHY_AGC_QUICK_DROP 0x03c00000
416 #define AR_PHY_AGC_QUICK_DROP_S 22
417 #define AR_PHY_AGC_COARSE_LOW 0x00007F80
418 #define AR_PHY_AGC_COARSE_LOW_S 7
419 #define AR_PHY_AGC_COARSE_HIGH 0x003F8000
420 #define AR_PHY_AGC_COARSE_HIGH_S 15
421 #define AR_PHY_AGC_COARSE_PWR_CONST 0x0000007F
422 #define AR_PHY_AGC_COARSE_PWR_CONST_S 0
423 #define AR_PHY_FIND_SIG_FIRSTEP 0x0003F000
424 #define AR_PHY_FIND_SIG_FIRSTEP_S 12
425 #define AR_PHY_FIND_SIG_FIRPWR 0x03FC0000
426 #define AR_PHY_FIND_SIG_FIRPWR_S 18
427 #define AR_PHY_FIND_SIG_FIRPWR_SIGN_BIT 25
428 #define AR_PHY_FIND_SIG_RELPWR (0x1f << 6)
429 #define AR_PHY_FIND_SIG_RELPWR_S 6
430 #define AR_PHY_FIND_SIG_RELPWR_SIGN_BIT 11
431 #define AR_PHY_FIND_SIG_RELSTEP 0x1f
432 #define AR_PHY_FIND_SIG_RELSTEP_S 0
433 #define AR_PHY_FIND_SIG_RELSTEP_SIGN_BIT 5
434 #define AR_PHY_RESTART_ENABLE_DIV_M2FLAG 0x00200000
435 #define AR_PHY_RESTART_ENABLE_DIV_M2FLAG_S 21
436 #define AR_PHY_RESTART_DIV_GC 0x001C0000
437 #define AR_PHY_RESTART_DIV_GC_S 18
438 #define AR_PHY_RESTART_ENA 0x01
439 #define AR_PHY_DC_RESTART_DIS 0x40000000
441 #define AR_PHY_TPC_OLPC_GAIN_DELTA_PAL_ON 0xFF000000
442 #define AR_PHY_TPC_OLPC_GAIN_DELTA_PAL_ON_S 24
443 #define AR_PHY_TPC_OLPC_GAIN_DELTA 0x00FF0000
444 #define AR_PHY_TPC_OLPC_GAIN_DELTA_S 16
446 #define AR_PHY_TPC_6_ERROR_EST_MODE 0x03000000
447 #define AR_PHY_TPC_6_ERROR_EST_MODE_S 24
452 #define AR_SM_BASE 0xa200
454 #define AR_PHY_D2_CHIP_ID (AR_SM_BASE + 0x0)
455 #define AR_PHY_GEN_CTRL (AR_SM_BASE + 0x4)
456 #define AR_PHY_MODE (AR_SM_BASE + 0x8)
457 #define AR_PHY_ACTIVE (AR_SM_BASE + 0xc)
458 #define AR_PHY_SPUR_MASK_A (AR_SM_BASE + 0x20)
459 #define AR_PHY_SPUR_MASK_B (AR_SM_BASE + 0x24)
460 #define AR_PHY_SPECTRAL_SCAN (AR_SM_BASE + 0x28)
461 #define AR_PHY_RADAR_BW_FILTER (AR_SM_BASE + 0x2c)
462 #define AR_PHY_SEARCH_START_DELAY (AR_SM_BASE + 0x30)
463 #define AR_PHY_MAX_RX_LEN (AR_SM_BASE + 0x34)
464 #define AR_PHY_FRAME_CTL (AR_SM_BASE + 0x38)
465 #define AR_PHY_RFBUS_REQ (AR_SM_BASE + 0x3c)
466 #define AR_PHY_RFBUS_GRANT (AR_SM_BASE + 0x40)
467 #define AR_PHY_RIFS (AR_SM_BASE + 0x44)
468 #define AR_PHY_RX_CLR_DELAY (AR_SM_BASE + 0x50)
469 #define AR_PHY_RX_DELAY (AR_SM_BASE + 0x54)
471 #define AR_PHY_XPA_TIMING_CTL (AR_SM_BASE + 0x64)
472 #define AR_PHY_MISC_PA_CTL (AR_SM_BASE + 0x80)
473 #define AR_PHY_SWITCH_CHAIN_0 (AR_SM_BASE + 0x84)
474 #define AR_PHY_SWITCH_COM (AR_SM_BASE + 0x88)
475 #define AR_PHY_SWITCH_COM_2 (AR_SM_BASE + 0x8c)
476 #define AR_PHY_RX_CHAINMASK (AR_SM_BASE + 0xa0)
477 #define AR_PHY_CAL_CHAINMASK (AR_SM_BASE + 0xc0)
478 #define AR_PHY_CALMODE (AR_SM_BASE + 0xc8)
479 #define AR_PHY_FCAL_1 (AR_SM_BASE + 0xcc)
480 #define AR_PHY_FCAL_2_0 (AR_SM_BASE + 0xd0)
481 #define AR_PHY_DFT_TONE_CTL_0 (AR_SM_BASE + 0xd4)
482 #define AR_PHY_CL_CAL_CTL (AR_SM_BASE + 0xd8)
483 #define AR_PHY_CL_TAB_0 (AR_SM_BASE + 0x100)
484 #define AR_PHY_SYNTH_CONTROL (AR_SM_BASE + 0x140)
485 #define AR_PHY_ADDAC_CLK_SEL (AR_SM_BASE + 0x144)
486 #define AR_PHY_PLL_CTL (AR_SM_BASE + 0x148)
487 #define AR_PHY_ANALOG_SWAP (AR_SM_BASE + 0x14c)
488 #define AR_PHY_ADDAC_PARA_CTL (AR_SM_BASE + 0x150)
489 #define AR_PHY_XPA_CFG (AR_SM_BASE + 0x158)
491 #define AR_PHY_FRAME_CTL_CF_OVERLAP_WINDOW 3
492 #define AR_PHY_FRAME_CTL_CF_OVERLAP_WINDOW_S 0
494 #define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A 0x0001FC00
495 #define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_S 10
496 #define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A 0x3FF
497 #define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A_S 0
499 #define AR_PHY_TEST (AR_SM_BASE + 0x160)
501 #define AR_PHY_TEST_BBB_OBS_SEL 0x780000
502 #define AR_PHY_TEST_BBB_OBS_SEL_S 19
504 #define AR_PHY_TEST_RX_OBS_SEL_BIT5_S 23
505 #define AR_PHY_TEST_RX_OBS_SEL_BIT5 (1 << AR_PHY_TEST_RX_OBS_SEL_BIT5_S)
507 #define AR_PHY_TEST_CHAIN_SEL 0xC0000000
508 #define AR_PHY_TEST_CHAIN_SEL_S 30
510 #define AR_PHY_TEST_CTL_STATUS (AR_SM_BASE + 0x164)
511 #define AR_PHY_TEST_CTL_TSTDAC_EN 0x1
512 #define AR_PHY_TEST_CTL_TSTDAC_EN_S 0
513 #define AR_PHY_TEST_CTL_TX_OBS_SEL 0x1C
514 #define AR_PHY_TEST_CTL_TX_OBS_SEL_S 2
515 #define AR_PHY_TEST_CTL_TX_OBS_MUX_SEL 0x60
516 #define AR_PHY_TEST_CTL_TX_OBS_MUX_SEL_S 5
517 #define AR_PHY_TEST_CTL_TSTADC_EN 0x100
518 #define AR_PHY_TEST_CTL_TSTADC_EN_S 8
519 #define AR_PHY_TEST_CTL_RX_OBS_SEL 0x3C00
520 #define AR_PHY_TEST_CTL_RX_OBS_SEL_S 10
521 #define AR_PHY_TEST_CTL_DEBUGPORT_SEL 0xe0000000
522 #define AR_PHY_TEST_CTL_DEBUGPORT_SEL_S 29
525 #define AR_PHY_TSTDAC (AR_SM_BASE + 0x168)
527 #define AR_PHY_CHAN_STATUS (AR_SM_BASE + 0x16c)
529 #define AR_PHY_CHAN_INFO_MEMORY (AR_SM_BASE + 0x170)
530 #define AR_PHY_CHAN_INFO_MEMORY_CHANINFOMEM_S2_READ 0x00000008
531 #define AR_PHY_CHAN_INFO_MEMORY_CHANINFOMEM_S2_READ_S 3
533 #define AR_PHY_CHNINFO_NOISEPWR (AR_SM_BASE + 0x174)
534 #define AR_PHY_CHNINFO_GAINDIFF (AR_SM_BASE + 0x178)
535 #define AR_PHY_CHNINFO_FINETIM (AR_SM_BASE + 0x17c)
536 #define AR_PHY_CHAN_INFO_GAIN_0 (AR_SM_BASE + 0x180)
537 #define AR_PHY_SCRAMBLER_SEED (AR_SM_BASE + 0x190)
538 #define AR_PHY_CCK_TX_CTRL (AR_SM_BASE + 0x194)
540 #define AR_PHY_HEAVYCLIP_CTL (AR_SM_BASE + 0x1a4)
541 #define AR_PHY_HEAVYCLIP_20 (AR_SM_BASE + 0x1a8)
542 #define AR_PHY_HEAVYCLIP_40 (AR_SM_BASE + 0x1ac)
543 #define AR_PHY_ILLEGAL_TXRATE (AR_SM_BASE + 0x1b0)
545 #define AR_PHY_POWER_TX_RATE(_d) (AR_SM_BASE + 0x1c0 + ((_d) << 2))
547 #define AR_PHY_PWRTX_MAX (AR_SM_BASE + 0x1f0)
548 #define AR_PHY_POWER_TX_SUB (AR_SM_BASE + 0x1f4)
550 #define AR_PHY_TPC_1 (AR_SM_BASE + 0x1f8)
551 #define AR_PHY_TPC_1_FORCED_DAC_GAIN 0x0000003e
552 #define AR_PHY_TPC_1_FORCED_DAC_GAIN_S 1
553 #define AR_PHY_TPC_1_FORCE_DAC_GAIN 0x00000001
554 #define AR_PHY_TPC_1_FORCE_DAC_GAIN_S 0
556 #define AR_PHY_TPC_4_B0 (AR_SM_BASE + 0x204)
557 #define AR_PHY_TPC_5_B0 (AR_SM_BASE + 0x208)
558 #define AR_PHY_TPC_6_B0 (AR_SM_BASE + 0x20c)
560 #define AR_PHY_TPC_11_B0 (AR_SM_BASE + 0x220)
561 #define AR_PHY_TPC_11_B1 (AR_SM1_BASE + 0x220)
562 #define AR_PHY_TPC_11_B2 (AR_SM2_BASE + 0x220)
563 #define AR_PHY_TPC_11_OLPC_GAIN_DELTA 0x00ff0000
564 #define AR_PHY_TPC_11_OLPC_GAIN_DELTA_S 16
566 #define AR_PHY_TPC_12 (AR_SM_BASE + 0x224)
567 #define AR_PHY_TPC_12_DESIRED_SCALE_HT40_5 0x3e000000
568 #define AR_PHY_TPC_12_DESIRED_SCALE_HT40_5_S 25
570 #define AR_PHY_TPC_18 (AR_SM_BASE + 0x23c)
571 #define AR_PHY_TPC_18_THERM_CAL_VALUE 0x000000ff
572 #define AR_PHY_TPC_18_THERM_CAL_VALUE_S 0
573 #define AR_PHY_TPC_18_VOLT_CAL_VALUE 0x0000ff00
574 #define AR_PHY_TPC_18_VOLT_CAL_VALUE_S 8
576 #define AR_PHY_TPC_19 (AR_SM_BASE + 0x240)
577 #define AR_PHY_TPC_19_ALPHA_VOLT 0x001f0000
578 #define AR_PHY_TPC_19_ALPHA_VOLT_S 16
579 #define AR_PHY_TPC_19_ALPHA_THERM 0xff
580 #define AR_PHY_TPC_19_ALPHA_THERM_S 0
582 #define AR_PHY_TX_FORCED_GAIN (AR_SM_BASE + 0x258)
583 #define AR_PHY_TX_FORCED_GAIN_FORCE_TX_GAIN 0x00000001
584 #define AR_PHY_TX_FORCED_GAIN_FORCE_TX_GAIN_S 0
585 #define AR_PHY_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN 0x0000000e
586 #define AR_PHY_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN_S 1
587 #define AR_PHY_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN 0x00000030
588 #define AR_PHY_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN_S 4
589 #define AR_PHY_TX_FORCED_GAIN_FORCED_TXMXRGAIN 0x000003c0
590 #define AR_PHY_TX_FORCED_GAIN_FORCED_TXMXRGAIN_S 6
591 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNA 0x00003c00
592 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNA_S 10
593 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNB 0x0003c000
594 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNB_S 14
595 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNC 0x003c0000
596 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNC_S 18
597 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGND 0x00c00000
598 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGND_S 22
599 #define AR_PHY_TX_FORCED_GAIN_FORCED_ENABLE_PAL 0x01000000
600 #define AR_PHY_TX_FORCED_GAIN_FORCED_ENABLE_PAL_S 24
603 #define AR_PHY_PDADC_TAB_0 (AR_SM_BASE + 0x280)
605 #define AR_PHY_TXGAIN_TABLE (AR_SM_BASE + 0x300)
607 #define AR_PHY_TX_IQCAL_CONTROL_0 (AR_SM_BASE + (AR_SREV_9485(ah) ? \
609 #define AR_PHY_TX_IQCAL_CONTROL_1 (AR_SM_BASE + (AR_SREV_9485(ah) ? \
611 #define AR_PHY_TX_IQCAL_START (AR_SM_BASE + (AR_SREV_9485(ah) ? \
613 #define AR_PHY_TX_IQCAL_STATUS_B0 (AR_SM_BASE + (AR_SREV_9485(ah) ? \
615 #define AR_PHY_TX_IQCAL_CORR_COEFF_B0(_i) (AR_SM_BASE + \
616 (AR_SREV_9485(ah) ? \
617 0x3d0 : 0x450) + ((_i) << 2))
618 #define AR_PHY_RTT_CTRL (AR_SM_BASE + 0x380)
620 #define AR_PHY_WATCHDOG_STATUS (AR_SM_BASE + 0x5c0)
621 #define AR_PHY_WATCHDOG_CTL_1 (AR_SM_BASE + 0x5c4)
622 #define AR_PHY_WATCHDOG_CTL_2 (AR_SM_BASE + 0x5c8)
623 #define AR_PHY_WATCHDOG_CTL (AR_SM_BASE + 0x5cc)
624 #define AR_PHY_ONLY_WARMRESET (AR_SM_BASE + 0x5d0)
625 #define AR_PHY_ONLY_CTL (AR_SM_BASE + 0x5d4)
626 #define AR_PHY_ECO_CTRL (AR_SM_BASE + 0x5dc)
628 #define AR_PHY_BB_THERM_ADC_1 (AR_SM_BASE + 0x248)
629 #define AR_PHY_BB_THERM_ADC_1_INIT_THERM 0x000000ff
630 #define AR_PHY_BB_THERM_ADC_1_INIT_THERM_S 0
632 #define AR_PHY_BB_THERM_ADC_3 (AR_SM_BASE + 0x250)
633 #define AR_PHY_BB_THERM_ADC_3_THERM_ADC_SCALE_GAIN 0x0001ff00
634 #define AR_PHY_BB_THERM_ADC_3_THERM_ADC_SCALE_GAIN_S 8
635 #define AR_PHY_BB_THERM_ADC_3_THERM_ADC_OFFSET 0x000000ff
636 #define AR_PHY_BB_THERM_ADC_3_THERM_ADC_OFFSET_S 0
638 #define AR_PHY_BB_THERM_ADC_4 (AR_SM_BASE + 0x254)
639 #define AR_PHY_BB_THERM_ADC_4_LATEST_THERM_VALUE 0x000000ff
640 #define AR_PHY_BB_THERM_ADC_4_LATEST_THERM_VALUE_S 0
641 #define AR_PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE 0x0000ff00
642 #define AR_PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE_S 8
645 #define AR_PHY_AIC_CTRL_0_B0 (AR_SM_BASE + 0x4b0)
646 #define AR_PHY_AIC_CTRL_1_B0 (AR_SM_BASE + 0x4b4)
647 #define AR_PHY_AIC_CTRL_2_B0 (AR_SM_BASE + 0x4b8)
648 #define AR_PHY_AIC_CTRL_3_B0 (AR_SM_BASE + 0x4bc)
649 #define AR_PHY_AIC_STAT_0_B0 (AR_SM_BASE + 0x4c4))
650 #define AR_PHY_AIC_STAT_1_B0 (AR_SM_BASE + 0x4c8))
651 #define AR_PHY_AIC_CTRL_4_B0 (AR_SM_BASE + 0x4c0)
652 #define AR_PHY_AIC_STAT_2_B0 (AR_SM_BASE + 0x4cc)
654 #define AR_PHY_65NM_CH0_TXRF3 0x16048
655 #define AR_PHY_65NM_CH0_TXRF3_CAPDIV2G 0x0000001e
656 #define AR_PHY_65NM_CH0_TXRF3_CAPDIV2G_S 1
658 #define AR_PHY_65NM_CH0_SYNTH4 0x1608c
659 #define AR_PHY_SYNTH4_LONG_SHIFT_SELECT ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x00000001 : 0x00000002)
660 #define AR_PHY_SYNTH4_LONG_SHIFT_SELECT_S ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0 : 1)
661 #define AR_PHY_65NM_CH0_SYNTH7 0x16098
662 #define AR_PHY_65NM_CH0_SYNTH12 0x160ac
663 #define AR_PHY_65NM_CH0_BIAS1 0x160c0
664 #define AR_PHY_65NM_CH0_BIAS2 0x160c4
665 #define AR_PHY_65NM_CH0_BIAS4 0x160cc
666 #define AR_PHY_65NM_CH0_RXTX2 0x16104
667 #define AR_PHY_65NM_CH1_RXTX2 0x16504
668 #define AR_PHY_65NM_CH2_RXTX2 0x16904
669 #define AR_PHY_65NM_CH0_RXTX4 0x1610c
670 #define AR_PHY_65NM_CH1_RXTX4 0x1650c
671 #define AR_PHY_65NM_CH2_RXTX4 0x1690c
673 #define AR_PHY_65NM_CH0_SYNTH12_VREFMUL3 0x00780000
674 #define AR_PHY_65NM_CH0_SYNTH12_VREFMUL3_S 19
675 #define AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK 0x00000004
676 #define AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S 2
677 #define AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK 0x00000008
678 #define AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S 3
680 #define AR_CH0_TOP (AR_SREV_9300(ah) ? 0x16288 : \
681 (((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x1628c : 0x16280)))
682 #define AR_CH0_TOP_XPABIASLVL (AR_SREV_9550(ah) ? 0x3c0 : 0x300)
683 #define AR_CH0_TOP_XPABIASLVL_S (AR_SREV_9550(ah) ? 6 : 8)
685 #define AR_CH0_THERM (AR_SREV_9300(ah) ? 0x16290 : \
686 ((AR_SREV_9485(ah) ? 0x1628c : 0x16294)))
687 #define AR_CH0_THERM_XPABIASLVL_MSB 0x3
688 #define AR_CH0_THERM_XPABIASLVL_MSB_S 0
689 #define AR_CH0_THERM_XPASHORT2GND 0x4
690 #define AR_CH0_THERM_XPASHORT2GND_S 2
692 #define AR_SWITCH_TABLE_COM_ALL (0xffff)
693 #define AR_SWITCH_TABLE_COM_ALL_S (0)
694 #define AR_SWITCH_TABLE_COM_AR9462_ALL (0xffffff)
695 #define AR_SWITCH_TABLE_COM_AR9462_ALL_S (0)
696 #define AR_SWITCH_TABLE_COM_AR9550_ALL (0xffffff)
697 #define AR_SWITCH_TABLE_COM_AR9550_ALL_S (0)
698 #define AR_SWITCH_TABLE_COM_SPDT (0x00f00000)
699 #define AR_SWITCH_TABLE_COM_SPDT_ALL (0x0000fff0)
700 #define AR_SWITCH_TABLE_COM_SPDT_ALL_S (4)
702 #define AR_SWITCH_TABLE_COM2_ALL (0xffffff)
703 #define AR_SWITCH_TABLE_COM2_ALL_S (0)
705 #define AR_SWITCH_TABLE_ALL (0xfff)
706 #define AR_SWITCH_TABLE_ALL_S (0)
708 #define AR_PHY_65NM_CH0_THERM (AR_SREV_9300(ah) ? 0x16290 :\
709 ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x16294 : 0x1628c))
711 #define AR_PHY_65NM_CH0_THERM_LOCAL 0x80000000
712 #define AR_PHY_65NM_CH0_THERM_LOCAL_S 31
713 #define AR_PHY_65NM_CH0_THERM_START 0x20000000
714 #define AR_PHY_65NM_CH0_THERM_START_S 29
715 #define AR_PHY_65NM_CH0_THERM_SAR_ADC_OUT 0x0000ff00
716 #define AR_PHY_65NM_CH0_THERM_SAR_ADC_OUT_S 8
718 #define AR_CH0_TOP2 (AR_SREV_9300(ah) ? 0x1628c : \
719 (AR_SREV_9462(ah) ? 0x16290 : 0x16284))
720 #define AR_CH0_TOP2_XPABIASLVL 0xf000
721 #define AR_CH0_TOP2_XPABIASLVL_S 12
723 #define AR_CH0_XTAL (AR_SREV_9300(ah) ? 0x16294 : \
724 ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x16298 : 0x16290))
725 #define AR_CH0_XTAL_CAPINDAC 0x7f000000
726 #define AR_CH0_XTAL_CAPINDAC_S 24
727 #define AR_CH0_XTAL_CAPOUTDAC 0x00fe0000
728 #define AR_CH0_XTAL_CAPOUTDAC_S 17
730 #define AR_PHY_PMU1 ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x16340 : 0x16c40)
731 #define AR_PHY_PMU1_PWD 0x1
732 #define AR_PHY_PMU1_PWD_S 0
734 #define AR_PHY_PMU2 ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x16344 : 0x16c44)
735 #define AR_PHY_PMU2_PGM 0x00200000
736 #define AR_PHY_PMU2_PGM_S 21
738 #define AR_PHY_RX1DB_BIQUAD_LONG_SHIFT 0x00380000
739 #define AR_PHY_RX1DB_BIQUAD_LONG_SHIFT_S 19
740 #define AR_PHY_RX6DB_BIQUAD_LONG_SHIFT 0x00c00000
741 #define AR_PHY_RX6DB_BIQUAD_LONG_SHIFT_S 22
742 #define AR_PHY_LNAGAIN_LONG_SHIFT 0xe0000000
743 #define AR_PHY_LNAGAIN_LONG_SHIFT_S 29
744 #define AR_PHY_MXRGAIN_LONG_SHIFT 0x03000000
745 #define AR_PHY_MXRGAIN_LONG_SHIFT_S 24
746 #define AR_PHY_VGAGAIN_LONG_SHIFT 0x1c000000
747 #define AR_PHY_VGAGAIN_LONG_SHIFT_S 26
748 #define AR_PHY_SCFIR_GAIN_LONG_SHIFT 0x00000001
749 #define AR_PHY_SCFIR_GAIN_LONG_SHIFT_S 0
750 #define AR_PHY_MANRXGAIN_LONG_SHIFT 0x00000002
751 #define AR_PHY_MANRXGAIN_LONG_SHIFT_S 1
754 * SM Field Definitions
756 #define AR_PHY_CL_CAL_ENABLE 0x00000002
757 #define AR_PHY_PARALLEL_CAL_ENABLE 0x00000001
758 #define AR_PHY_TPCRG1_PD_CAL_ENABLE 0x00400000
759 #define AR_PHY_TPCRG1_PD_CAL_ENABLE_S 22
761 #define AR_PHY_ADDAC_PARACTL_OFF_PWDADC 0x00008000
763 #define AR_PHY_FCAL20_CAP_STATUS_0 0x01f00000
764 #define AR_PHY_FCAL20_CAP_STATUS_0_S 20
766 #define AR_PHY_RFBUS_REQ_EN 0x00000001 /* request for RF bus */
767 #define AR_PHY_RFBUS_GRANT_EN 0x00000001 /* RF bus granted */
768 #define AR_PHY_GC_TURBO_MODE 0x00000001 /* set turbo mode bits */
769 #define AR_PHY_GC_TURBO_SHORT 0x00000002 /* set short symbols to turbo mode setting */
770 #define AR_PHY_GC_DYN2040_EN 0x00000004 /* enable dyn 20/40 mode */
771 #define AR_PHY_GC_DYN2040_PRI_ONLY 0x00000008 /* dyn 20/40 - primary only */
772 #define AR_PHY_GC_DYN2040_PRI_CH 0x00000010 /* dyn 20/40 - primary ch offset (0=+10MHz, 1=-10MHz)*/
773 #define AR_PHY_GC_DYN2040_PRI_CH_S 4
774 #define AR_PHY_GC_DYN2040_EXT_CH 0x00000020 /* dyn 20/40 - ext ch spacing (0=20MHz/ 1=25MHz) */
775 #define AR_PHY_GC_HT_EN 0x00000040 /* ht enable */
776 #define AR_PHY_GC_SHORT_GI_40 0x00000080 /* allow short GI for HT 40 */
777 #define AR_PHY_GC_WALSH 0x00000100 /* walsh spatial spreading for 2 chains,2 streams TX */
778 #define AR_PHY_GC_SINGLE_HT_LTF1 0x00000200 /* single length (4us) 1st HT long training symbol */
779 #define AR_PHY_GC_GF_DETECT_EN 0x00000400 /* enable Green Field detection. Only affects rx, not tx */
780 #define AR_PHY_GC_ENABLE_DAC_FIFO 0x00000800 /* fifo between bb and dac */
781 #define AR_PHY_RX_DELAY_DELAY 0x00003FFF /* delay from wakeup to rx ena */
783 #define AR_PHY_CALMODE_IQ 0x00000000
784 #define AR_PHY_CALMODE_ADC_GAIN 0x00000001
785 #define AR_PHY_CALMODE_ADC_DC_PER 0x00000002
786 #define AR_PHY_CALMODE_ADC_DC_INIT 0x00000003
787 #define AR_PHY_SWAP_ALT_CHAIN 0x00000040
788 #define AR_PHY_MODE_OFDM 0x00000000
789 #define AR_PHY_MODE_CCK 0x00000001
790 #define AR_PHY_MODE_DYNAMIC 0x00000004
791 #define AR_PHY_MODE_DYNAMIC_S 2
792 #define AR_PHY_MODE_HALF 0x00000020
793 #define AR_PHY_MODE_QUARTER 0x00000040
794 #define AR_PHY_MAC_CLK_MODE 0x00000080
795 #define AR_PHY_MODE_DYN_CCK_DISABLE 0x00000100
796 #define AR_PHY_MODE_SVD_HALF 0x00000200
797 #define AR_PHY_ACTIVE_EN 0x00000001
798 #define AR_PHY_ACTIVE_DIS 0x00000000
799 #define AR_PHY_FORCE_XPA_CFG 0x000000001
800 #define AR_PHY_FORCE_XPA_CFG_S 0
801 #define AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF 0xFF000000
802 #define AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF_S 24
803 #define AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF 0x00FF0000
804 #define AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF_S 16
805 #define AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON 0x0000FF00
806 #define AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON_S 8
807 #define AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON 0x000000FF
808 #define AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON_S 0
809 #define AR_PHY_TX_END_TO_A2_RX_ON 0x00FF0000
810 #define AR_PHY_TX_END_TO_A2_RX_ON_S 16
811 #define AR_PHY_TX_END_DATA_START 0x000000FF
812 #define AR_PHY_TX_END_DATA_START_S 0
813 #define AR_PHY_TX_END_PA_ON 0x0000FF00
814 #define AR_PHY_TX_END_PA_ON_S 8
815 #define AR_PHY_TPCRG5_PD_GAIN_OVERLAP 0x0000000F
816 #define AR_PHY_TPCRG5_PD_GAIN_OVERLAP_S 0
817 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1 0x000003F0
818 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_S 4
819 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2 0x0000FC00
820 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_S 10
821 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3 0x003F0000
822 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_S 16
823 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4 0x0FC00000
824 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_S 22
825 #define AR_PHY_TPCRG1_NUM_PD_GAIN 0x0000c000
826 #define AR_PHY_TPCRG1_NUM_PD_GAIN_S 14
827 #define AR_PHY_TPCRG1_PD_GAIN_1 0x00030000
828 #define AR_PHY_TPCRG1_PD_GAIN_1_S 16
829 #define AR_PHY_TPCRG1_PD_GAIN_2 0x000C0000
830 #define AR_PHY_TPCRG1_PD_GAIN_2_S 18
831 #define AR_PHY_TPCRG1_PD_GAIN_3 0x00300000
832 #define AR_PHY_TPCRG1_PD_GAIN_3_S 20
833 #define AR_PHY_TPCGR1_FORCED_DAC_GAIN 0x0000003e
834 #define AR_PHY_TPCGR1_FORCED_DAC_GAIN_S 1
835 #define AR_PHY_TPCGR1_FORCE_DAC_GAIN 0x00000001
836 #define AR_PHY_TXGAIN_FORCE 0x00000001
837 #define AR_PHY_TXGAIN_FORCE_S 0
838 #define AR_PHY_TXGAIN_FORCED_PADVGNRA 0x00003c00
839 #define AR_PHY_TXGAIN_FORCED_PADVGNRA_S 10
840 #define AR_PHY_TXGAIN_FORCED_PADVGNRB 0x0003c000
841 #define AR_PHY_TXGAIN_FORCED_PADVGNRB_S 14
842 #define AR_PHY_TXGAIN_FORCED_PADVGNRD 0x00c00000
843 #define AR_PHY_TXGAIN_FORCED_PADVGNRD_S 22
844 #define AR_PHY_TXGAIN_FORCED_TXMXRGAIN 0x000003c0
845 #define AR_PHY_TXGAIN_FORCED_TXMXRGAIN_S 6
846 #define AR_PHY_TXGAIN_FORCED_TXBB1DBGAIN 0x0000000e
847 #define AR_PHY_TXGAIN_FORCED_TXBB1DBGAIN_S 1
849 #define AR_PHY_POWER_TX_RATE1 0x9934
850 #define AR_PHY_POWER_TX_RATE2 0x9938
851 #define AR_PHY_POWER_TX_RATE_MAX 0x993c
852 #define AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE 0x00000040
853 #define PHY_AGC_CLR 0x10000000
854 #define RFSILENT_BB 0x00002000
855 #define AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK 0xFFF
856 #define AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_SIGNED_BIT 0x800
857 #define AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT 320
858 #define AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK 0x0001
859 #define AR_PHY_RX_DELAY_DELAY 0x00003FFF
860 #define AR_PHY_CCK_TX_CTRL_JAPAN 0x00000010
862 #define AR_PHY_SPECTRAL_SCAN_ENABLE 0x00000001
863 #define AR_PHY_SPECTRAL_SCAN_ENABLE_S 0
864 #define AR_PHY_SPECTRAL_SCAN_ACTIVE 0x00000002
865 #define AR_PHY_SPECTRAL_SCAN_ACTIVE_S 1
866 #define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD 0x000000F0
867 #define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD_S 4
868 #define AR_PHY_SPECTRAL_SCAN_PERIOD 0x0000FF00
869 #define AR_PHY_SPECTRAL_SCAN_PERIOD_S 8
870 #define AR_PHY_SPECTRAL_SCAN_COUNT 0x0FFF0000
871 #define AR_PHY_SPECTRAL_SCAN_COUNT_S 16
872 #define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT 0x10000000
873 #define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT_S 28
874 #define AR_PHY_SPECTRAL_SCAN_PRIORITY 0x20000000
875 #define AR_PHY_SPECTRAL_SCAN_PRIORITY_S 29
876 #define AR_PHY_SPECTRAL_SCAN_USE_ERR5 0x40000000
877 #define AR_PHY_SPECTRAL_SCAN_USE_ERR5_S 30
878 #define AR_PHY_SPECTRAL_SCAN_COMPRESSED_RPT 0x80000000
879 #define AR_PHY_SPECTRAL_SCAN_COMPRESSED_RPT_S 31
881 #define AR_PHY_CHANNEL_STATUS_RX_CLEAR 0x00000004
882 #define AR_PHY_RTT_CTRL_ENA_RADIO_RETENTION 0x00000001
883 #define AR_PHY_RTT_CTRL_ENA_RADIO_RETENTION_S 0
884 #define AR_PHY_RTT_CTRL_RESTORE_MASK 0x0000007E
885 #define AR_PHY_RTT_CTRL_RESTORE_MASK_S 1
886 #define AR_PHY_RTT_CTRL_FORCE_RADIO_RESTORE 0x00000080
887 #define AR_PHY_RTT_CTRL_FORCE_RADIO_RESTORE_S 7
888 #define AR_PHY_RTT_SW_RTT_TABLE_ACCESS 0x00000001
889 #define AR_PHY_RTT_SW_RTT_TABLE_ACCESS_S 0
890 #define AR_PHY_RTT_SW_RTT_TABLE_WRITE 0x00000002
891 #define AR_PHY_RTT_SW_RTT_TABLE_WRITE_S 1
892 #define AR_PHY_RTT_SW_RTT_TABLE_ADDR 0x0000001C
893 #define AR_PHY_RTT_SW_RTT_TABLE_ADDR_S 2
894 #define AR_PHY_RTT_SW_RTT_TABLE_DATA 0xFFFFFFF0
895 #define AR_PHY_RTT_SW_RTT_TABLE_DATA_S 4
896 #define AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL 0x80000000
897 #define AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL_S 31
898 #define AR_PHY_TX_IQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT 0x01fc0000
899 #define AR_PHY_TX_IQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_S 18
900 #define AR_PHY_TX_IQCAL_START_DO_CAL 0x00000001
901 #define AR_PHY_TX_IQCAL_START_DO_CAL_S 0
903 #define AR_PHY_TX_IQCAL_STATUS_FAILED 0x00000001
904 #define AR_PHY_CALIBRATED_GAINS_0 0x3e
905 #define AR_PHY_CALIBRATED_GAINS_0_S 1
907 #define AR_PHY_TX_IQCAL_CORR_COEFF_00_COEFF_TABLE 0x00003fff
908 #define AR_PHY_TX_IQCAL_CORR_COEFF_00_COEFF_TABLE_S 0
909 #define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE 0x0fffc000
910 #define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE_S 14
912 #define AR_PHY_65NM_CH0_RXTX4_THERM_ON 0x10000000
913 #define AR_PHY_65NM_CH0_RXTX4_THERM_ON_S 28
914 #define AR_PHY_65NM_CH0_RXTX4_THERM_ON_OVR 0x20000000
915 #define AR_PHY_65NM_CH0_RXTX4_THERM_ON_OVR_S 29
917 #define AR_PHY_65NM_RXTX4_XLNA_BIAS 0xC0000000
918 #define AR_PHY_65NM_RXTX4_XLNA_BIAS_S 30
921 * Channel 1 Register Map
923 #define AR_CHAN1_BASE 0xa800
925 #define AR_PHY_EXT_CCA_1 (AR_CHAN1_BASE + 0x30)
926 #define AR_PHY_TX_PHASE_RAMP_1 (AR_CHAN1_BASE + 0xd0)
927 #define AR_PHY_ADC_GAIN_DC_CORR_1 (AR_CHAN1_BASE + 0xd4)
929 #define AR_PHY_SPUR_REPORT_1 (AR_CHAN1_BASE + 0xa8)
930 #define AR_PHY_CHAN_INFO_TAB_1 (AR_CHAN1_BASE + 0x300)
931 #define AR_PHY_RX_IQCAL_CORR_B1 (AR_CHAN1_BASE + 0xdc)
934 * Channel 1 Field Definitions
936 #define AR_PHY_CH1_EXT_MINCCA_PWR 0x01FF0000
937 #define AR_PHY_CH1_EXT_MINCCA_PWR_S 16
942 #define AR_AGC1_BASE 0xae00
944 #define AR_PHY_FORCEMAX_GAINS_1 (AR_AGC1_BASE + 0x4)
945 #define AR_PHY_EXT_ATTEN_CTL_1 (AR_AGC1_BASE + 0x18)
946 #define AR_PHY_CCA_1 (AR_AGC1_BASE + 0x1c)
947 #define AR_PHY_CCA_CTRL_1 (AR_AGC1_BASE + 0x20)
948 #define AR_PHY_RSSI_1 (AR_AGC1_BASE + 0x180)
949 #define AR_PHY_SPUR_CCK_REP_1 (AR_AGC1_BASE + 0x184)
950 #define AR_PHY_RX_OCGAIN_2 (AR_AGC1_BASE + 0x200)
953 * AGC 1 Field Definitions
955 #define AR_PHY_CH1_MINCCA_PWR 0x1FF00000
956 #define AR_PHY_CH1_MINCCA_PWR_S 20
961 #define AR_SM1_BASE 0xb200
963 #define AR_PHY_SWITCH_CHAIN_1 (AR_SM1_BASE + 0x84)
964 #define AR_PHY_FCAL_2_1 (AR_SM1_BASE + 0xd0)
965 #define AR_PHY_DFT_TONE_CTL_1 (AR_SM1_BASE + 0xd4)
966 #define AR_PHY_CL_TAB_1 (AR_SM1_BASE + 0x100)
967 #define AR_PHY_CHAN_INFO_GAIN_1 (AR_SM1_BASE + 0x180)
968 #define AR_PHY_TPC_4_B1 (AR_SM1_BASE + 0x204)
969 #define AR_PHY_TPC_5_B1 (AR_SM1_BASE + 0x208)
970 #define AR_PHY_TPC_6_B1 (AR_SM1_BASE + 0x20c)
971 #define AR_PHY_TPC_11_B1 (AR_SM1_BASE + 0x220)
972 #define AR_PHY_PDADC_TAB_1 (AR_SM1_BASE + (AR_SREV_9462_20_OR_LATER(ah) ? \
974 #define AR_PHY_TPC_19_B1 (AR_SM1_BASE + 0x240)
975 #define AR_PHY_TPC_19_B1_ALPHA_THERM 0xff
976 #define AR_PHY_TPC_19_B1_ALPHA_THERM_S 0
977 #define AR_PHY_TX_IQCAL_STATUS_B1 (AR_SM1_BASE + 0x48c)
978 #define AR_PHY_TX_IQCAL_CORR_COEFF_B1(_i) (AR_SM1_BASE + 0x450 + ((_i) << 2))
980 /* SM 1 AIC Registers */
982 #define AR_PHY_AIC_CTRL_0_B1 (AR_SM1_BASE + 0x4b0)
983 #define AR_PHY_AIC_CTRL_1_B1 (AR_SM1_BASE + 0x4b4)
984 #define AR_PHY_AIC_CTRL_2_B1 (AR_SM1_BASE + 0x4b8)
985 #define AR_PHY_AIC_STAT_0_B1 (AR_SM1_BASE + (AR_SREV_9462_10(ah) ? \
987 #define AR_PHY_AIC_STAT_1_B1 (AR_SM1_BASE + (AR_SREV_9462_10(ah) ? \
989 #define AR_PHY_AIC_CTRL_4_B1 (AR_SM1_BASE + 0x4c0)
990 #define AR_PHY_AIC_STAT_2_B1 (AR_SM1_BASE + 0x4cc)
992 #define AR_PHY_AIC_SRAM_ADDR_B1 (AR_SM1_BASE + 0x5f0)
993 #define AR_PHY_AIC_SRAM_DATA_B1 (AR_SM1_BASE + 0x5f4)
995 #define AR_PHY_RTT_TABLE_SW_INTF_B(i) (0x384 + ((i) ? \
996 AR_SM1_BASE : AR_SM_BASE))
997 #define AR_PHY_RTT_TABLE_SW_INTF_1_B(i) (0x388 + ((i) ? \
998 AR_SM1_BASE : AR_SM_BASE))
1000 * Channel 2 Register Map
1002 #define AR_CHAN2_BASE 0xb800
1004 #define AR_PHY_EXT_CCA_2 (AR_CHAN2_BASE + 0x30)
1005 #define AR_PHY_TX_PHASE_RAMP_2 (AR_CHAN2_BASE + 0xd0)
1006 #define AR_PHY_ADC_GAIN_DC_CORR_2 (AR_CHAN2_BASE + 0xd4)
1008 #define AR_PHY_SPUR_REPORT_2 (AR_CHAN2_BASE + 0xa8)
1009 #define AR_PHY_CHAN_INFO_TAB_2 (AR_CHAN2_BASE + 0x300)
1010 #define AR_PHY_RX_IQCAL_CORR_B2 (AR_CHAN2_BASE + 0xdc)
1013 * Channel 2 Field Definitions
1015 #define AR_PHY_CH2_EXT_MINCCA_PWR 0x01FF0000
1016 #define AR_PHY_CH2_EXT_MINCCA_PWR_S 16
1018 * AGC 2 Register Map
1020 #define AR_AGC2_BASE 0xbe00
1022 #define AR_PHY_FORCEMAX_GAINS_2 (AR_AGC2_BASE + 0x4)
1023 #define AR_PHY_EXT_ATTEN_CTL_2 (AR_AGC2_BASE + 0x18)
1024 #define AR_PHY_CCA_2 (AR_AGC2_BASE + 0x1c)
1025 #define AR_PHY_CCA_CTRL_2 (AR_AGC2_BASE + 0x20)
1026 #define AR_PHY_RSSI_2 (AR_AGC2_BASE + 0x180)
1029 * AGC 2 Field Definitions
1031 #define AR_PHY_CH2_MINCCA_PWR 0x1FF00000
1032 #define AR_PHY_CH2_MINCCA_PWR_S 20
1037 #define AR_SM2_BASE 0xc200
1039 #define AR_PHY_SWITCH_CHAIN_2 (AR_SM2_BASE + 0x84)
1040 #define AR_PHY_FCAL_2_2 (AR_SM2_BASE + 0xd0)
1041 #define AR_PHY_DFT_TONE_CTL_2 (AR_SM2_BASE + 0xd4)
1042 #define AR_PHY_CL_TAB_2 (AR_SM2_BASE + 0x100)
1043 #define AR_PHY_CHAN_INFO_GAIN_2 (AR_SM2_BASE + 0x180)
1044 #define AR_PHY_TPC_4_B2 (AR_SM2_BASE + 0x204)
1045 #define AR_PHY_TPC_5_B2 (AR_SM2_BASE + 0x208)
1046 #define AR_PHY_TPC_6_B2 (AR_SM2_BASE + 0x20c)
1047 #define AR_PHY_TPC_11_B2 (AR_SM2_BASE + 0x220)
1048 #define AR_PHY_TPC_19_B2 (AR_SM2_BASE + 0x240)
1049 #define AR_PHY_TX_IQCAL_STATUS_B2 (AR_SM2_BASE + 0x48c)
1050 #define AR_PHY_TX_IQCAL_CORR_COEFF_B2(_i) (AR_SM2_BASE + 0x450 + ((_i) << 2))
1052 #define AR_PHY_TX_IQCAL_STATUS_B2_FAILED 0x00000001
1055 * AGC 3 Register Map
1057 #define AR_AGC3_BASE 0xce00
1059 #define AR_PHY_RSSI_3 (AR_AGC3_BASE + 0x180)
1062 #define AR_GLB_BASE 0x20000
1063 #define AR_GLB_GPIO_CONTROL (AR_GLB_BASE)
1064 #define AR_PHY_GLB_CONTROL (AR_GLB_BASE + 0x44)
1065 #define AR_GLB_SCRATCH(_ah) (AR_GLB_BASE + \
1066 (AR_SREV_9462_20_OR_LATER(_ah) ? 0x4c : 0x50))
1067 #define AR_GLB_STATUS (AR_GLB_BASE + 0x48)
1070 * Misc helper defines
1072 #define AR_PHY_CHAIN_OFFSET (AR_CHAN1_BASE - AR_CHAN_BASE)
1074 #define AR_PHY_NEW_ADC_DC_GAIN_CORR(_i) (AR_PHY_ADC_GAIN_DC_CORR_0 + (AR_PHY_CHAIN_OFFSET * (_i)))
1075 #define AR_PHY_NEW_ADC_DC_GAIN_CORR_9300_10(_i) (AR_PHY_ADC_GAIN_DC_CORR_0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i)))
1076 #define AR_PHY_SWITCH_CHAIN(_i) (AR_PHY_SWITCH_CHAIN_0 + (AR_PHY_CHAIN_OFFSET * (_i)))
1077 #define AR_PHY_EXT_ATTEN_CTL(_i) (AR_PHY_EXT_ATTEN_CTL_0 + (AR_PHY_CHAIN_OFFSET * (_i)))
1079 #define AR_PHY_RXGAIN(_i) (AR_PHY_FORCEMAX_GAINS_0 + (AR_PHY_CHAIN_OFFSET * (_i)))
1080 #define AR_PHY_TPCRG5(_i) (AR_PHY_TPC_5_B0 + (AR_PHY_CHAIN_OFFSET * (_i)))
1081 #define AR_PHY_PDADC_TAB(_i) (AR_PHY_PDADC_TAB_0 + (AR_PHY_CHAIN_OFFSET * (_i)))
1083 #define AR_PHY_CAL_MEAS_0(_i) (AR_PHY_IQ_ADC_MEAS_0_B0 + (AR_PHY_CHAIN_OFFSET * (_i)))
1084 #define AR_PHY_CAL_MEAS_1(_i) (AR_PHY_IQ_ADC_MEAS_1_B0 + (AR_PHY_CHAIN_OFFSET * (_i)))
1085 #define AR_PHY_CAL_MEAS_2(_i) (AR_PHY_IQ_ADC_MEAS_2_B0 + (AR_PHY_CHAIN_OFFSET * (_i)))
1086 #define AR_PHY_CAL_MEAS_3(_i) (AR_PHY_IQ_ADC_MEAS_3_B0 + (AR_PHY_CHAIN_OFFSET * (_i)))
1087 #define AR_PHY_CAL_MEAS_0_9300_10(_i) (AR_PHY_IQ_ADC_MEAS_0_B0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i)))
1088 #define AR_PHY_CAL_MEAS_1_9300_10(_i) (AR_PHY_IQ_ADC_MEAS_1_B0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i)))
1089 #define AR_PHY_CAL_MEAS_2_9300_10(_i) (AR_PHY_IQ_ADC_MEAS_2_B0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i)))
1090 #define AR_PHY_CAL_MEAS_3_9300_10(_i) (AR_PHY_IQ_ADC_MEAS_3_B0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i)))
1092 #define AR_PHY_WATCHDOG_NON_IDLE_ENABLE 0x00000001
1093 #define AR_PHY_WATCHDOG_IDLE_ENABLE 0x00000002
1094 #define AR_PHY_WATCHDOG_IDLE_MASK 0xFFFF0000
1095 #define AR_PHY_WATCHDOG_NON_IDLE_MASK 0x0000FFFC
1097 #define AR_PHY_WATCHDOG_RST_ENABLE 0x00000002
1098 #define AR_PHY_WATCHDOG_IRQ_ENABLE 0x00000004
1099 #define AR_PHY_WATCHDOG_CNTL2_MASK 0xFFFFFFF9
1101 #define AR_PHY_WATCHDOG_INFO 0x00000007
1102 #define AR_PHY_WATCHDOG_INFO_S 0
1103 #define AR_PHY_WATCHDOG_DET_HANG 0x00000008
1104 #define AR_PHY_WATCHDOG_DET_HANG_S 3
1105 #define AR_PHY_WATCHDOG_RADAR_SM 0x000000F0
1106 #define AR_PHY_WATCHDOG_RADAR_SM_S 4
1107 #define AR_PHY_WATCHDOG_RX_OFDM_SM 0x00000F00
1108 #define AR_PHY_WATCHDOG_RX_OFDM_SM_S 8
1109 #define AR_PHY_WATCHDOG_RX_CCK_SM 0x0000F000
1110 #define AR_PHY_WATCHDOG_RX_CCK_SM_S 12
1111 #define AR_PHY_WATCHDOG_TX_OFDM_SM 0x000F0000
1112 #define AR_PHY_WATCHDOG_TX_OFDM_SM_S 16
1113 #define AR_PHY_WATCHDOG_TX_CCK_SM 0x00F00000
1114 #define AR_PHY_WATCHDOG_TX_CCK_SM_S 20
1115 #define AR_PHY_WATCHDOG_AGC_SM 0x0F000000
1116 #define AR_PHY_WATCHDOG_AGC_SM_S 24
1117 #define AR_PHY_WATCHDOG_SRCH_SM 0xF0000000
1118 #define AR_PHY_WATCHDOG_SRCH_SM_S 28
1120 #define AR_PHY_WATCHDOG_STATUS_CLR 0x00000008
1125 #define AR_PHY_XPA_TIMING_CTL (AR_SM_BASE + 0x64)
1127 #define AR_PHY_PAPRD_AM2AM (AR_CHAN_BASE + 0xe4)
1128 #define AR_PHY_PAPRD_AM2AM_MASK 0x01ffffff
1129 #define AR_PHY_PAPRD_AM2AM_MASK_S 0
1131 #define AR_PHY_PAPRD_AM2PM (AR_CHAN_BASE + 0xe8)
1132 #define AR_PHY_PAPRD_AM2PM_MASK 0x01ffffff
1133 #define AR_PHY_PAPRD_AM2PM_MASK_S 0
1135 #define AR_PHY_PAPRD_HT40 (AR_CHAN_BASE + 0xec)
1136 #define AR_PHY_PAPRD_HT40_MASK 0x01ffffff
1137 #define AR_PHY_PAPRD_HT40_MASK_S 0
1139 #define AR_PHY_PAPRD_CTRL0_B0 (AR_CHAN_BASE + 0xf0)
1140 #define AR_PHY_PAPRD_CTRL0_B1 (AR_CHAN1_BASE + 0xf0)
1141 #define AR_PHY_PAPRD_CTRL0_B2 (AR_CHAN2_BASE + 0xf0)
1142 #define AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE 0x00000001
1143 #define AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE_S 0
1144 #define AR_PHY_PAPRD_CTRL0_USE_SINGLE_TABLE_MASK 0x00000002
1145 #define AR_PHY_PAPRD_CTRL0_USE_SINGLE_TABLE_MASK_S 1
1146 #define AR_PHY_PAPRD_CTRL0_PAPRD_MAG_THRSH 0xf8000000
1147 #define AR_PHY_PAPRD_CTRL0_PAPRD_MAG_THRSH_S 27
1149 #define AR_PHY_PAPRD_CTRL1_B0 (AR_CHAN_BASE + 0xf4)
1150 #define AR_PHY_PAPRD_CTRL1_B1 (AR_CHAN1_BASE + 0xf4)
1151 #define AR_PHY_PAPRD_CTRL1_B2 (AR_CHAN2_BASE + 0xf4)
1152 #define AR_PHY_PAPRD_CTRL1_ADAPTIVE_SCALING_ENA 0x00000001
1153 #define AR_PHY_PAPRD_CTRL1_ADAPTIVE_SCALING_ENA_S 0
1154 #define AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2AM_ENABLE 0x00000002
1155 #define AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2AM_ENABLE_S 1
1156 #define AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2PM_ENABLE 0x00000004
1157 #define AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2PM_ENABLE_S 2
1158 #define AR_PHY_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL 0x000001f8
1159 #define AR_PHY_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL_S 3
1160 #define AR_PHY_PAPRD_CTRL1_PA_GAIN_SCALE_FACT_MASK 0x0001fe00
1161 #define AR_PHY_PAPRD_CTRL1_PA_GAIN_SCALE_FACT_MASK_S 9
1162 #define AR_PHY_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACT 0x0ffe0000
1163 #define AR_PHY_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACT_S 17
1165 #define AR_PHY_PAPRD_TRAINER_CNTL1 (AR_SM_BASE + (AR_SREV_9485(ah) ? 0x580 : 0x490))
1167 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_CF_PAPRD_TRAIN_ENABLE 0x00000001
1168 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_CF_PAPRD_TRAIN_ENABLE_S 0
1169 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING 0x0000007e
1170 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING_S 1
1171 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE 0x00000100
1172 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE_S 8
1173 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE 0x00000200
1174 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE_S 9
1175 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE 0x00000400
1176 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE_S 10
1177 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE 0x00000800
1178 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE_S 11
1179 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP 0x0003f000
1180 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP_S 12
1182 #define AR_PHY_PAPRD_TRAINER_CNTL2 (AR_SM_BASE + (AR_SREV_9485(ah) ? 0x584 : 0x494))
1184 #define AR_PHY_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN 0xFFFFFFFF
1185 #define AR_PHY_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_S 0
1187 #define AR_PHY_PAPRD_TRAINER_CNTL3 (AR_SM_BASE + (AR_SREV_9485(ah) ? 0x588 : 0x498))
1189 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE 0x0000003f
1190 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE_S 0
1191 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP 0x00000fc0
1192 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP_S 6
1193 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL 0x0001f000
1194 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL_S 12
1195 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES 0x000e0000
1196 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES_S 17
1197 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN 0x00f00000
1198 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN_S 20
1199 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN 0x0f000000
1200 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN_S 24
1201 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE 0x20000000
1202 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_S 29
1204 #define AR_PHY_PAPRD_TRAINER_CNTL4 (AR_SM_BASE + (AR_SREV_9485(ah) ? 0x58c : 0x49c))
1206 #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES 0x03ff0000
1207 #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_S 16
1208 #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA 0x0000f000
1209 #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA_S 12
1210 #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR 0x00000fff
1211 #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR_S 0
1213 #define AR_PHY_PAPRD_PRE_POST_SCALE_0_B0 (AR_CHAN_BASE + 0x100)
1214 #define AR_PHY_PAPRD_PRE_POST_SCALE_1_B0 (AR_CHAN_BASE + 0x104)
1215 #define AR_PHY_PAPRD_PRE_POST_SCALE_2_B0 (AR_CHAN_BASE + 0x108)
1216 #define AR_PHY_PAPRD_PRE_POST_SCALE_3_B0 (AR_CHAN_BASE + 0x10c)
1217 #define AR_PHY_PAPRD_PRE_POST_SCALE_4_B0 (AR_CHAN_BASE + 0x110)
1218 #define AR_PHY_PAPRD_PRE_POST_SCALE_5_B0 (AR_CHAN_BASE + 0x114)
1219 #define AR_PHY_PAPRD_PRE_POST_SCALE_6_B0 (AR_CHAN_BASE + 0x118)
1220 #define AR_PHY_PAPRD_PRE_POST_SCALE_7_B0 (AR_CHAN_BASE + 0x11c)
1221 #define AR_PHY_PAPRD_PRE_POST_SCALING 0x3FFFF
1222 #define AR_PHY_PAPRD_PRE_POST_SCALING_S 0
1224 #define AR_PHY_PAPRD_TRAINER_STAT1 (AR_SM_BASE + (AR_SREV_9485(ah) ? 0x590 : 0x4a0))
1226 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE 0x00000001
1227 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE_S 0
1228 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE 0x00000002
1229 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE_S 1
1230 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR 0x00000004
1231 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR_S 2
1232 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE 0x00000008
1233 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE_S 3
1234 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX 0x000001f0
1235 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX_S 4
1236 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR 0x0001fe00
1237 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR_S 9
1239 #define AR_PHY_PAPRD_TRAINER_STAT2 (AR_SM_BASE + (AR_SREV_9485(ah) ? 0x594 : 0x4a4))
1241 #define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL 0x0000ffff
1242 #define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL_S 0
1243 #define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX 0x001f0000
1244 #define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX_S 16
1245 #define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX 0x00600000
1246 #define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX_S 21
1248 #define AR_PHY_PAPRD_TRAINER_STAT3 (AR_SM_BASE + (AR_SREV_9485(ah) ? 0x598 : 0x4a8))
1250 #define AR_PHY_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT 0x000fffff
1251 #define AR_PHY_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT_S 0
1253 #define AR_PHY_PAPRD_MEM_TAB_B0 (AR_CHAN_BASE + 0x120)
1254 #define AR_PHY_PAPRD_MEM_TAB_B1 (AR_CHAN1_BASE + 0x120)
1255 #define AR_PHY_PAPRD_MEM_TAB_B2 (AR_CHAN2_BASE + 0x120)
1257 #define AR_PHY_PA_GAIN123_B0 (AR_CHAN_BASE + 0xf8)
1258 #define AR_PHY_PA_GAIN123_B1 (AR_CHAN1_BASE + 0xf8)
1259 #define AR_PHY_PA_GAIN123_B2 (AR_CHAN2_BASE + 0xf8)
1260 #define AR_PHY_PA_GAIN123_PA_GAIN1 0x3FF
1261 #define AR_PHY_PA_GAIN123_PA_GAIN1_S 0
1263 #define AR_PHY_POWERTX_RATE5 (AR_SM_BASE + 0x1d0)
1264 #define AR_PHY_POWERTX_RATE5_POWERTXHT20_0 0x3F
1265 #define AR_PHY_POWERTX_RATE5_POWERTXHT20_0_S 0
1267 #define AR_PHY_POWERTX_RATE6 (AR_SM_BASE + 0x1d4)
1268 #define AR_PHY_POWERTX_RATE6_POWERTXHT20_5 0x3F00
1269 #define AR_PHY_POWERTX_RATE6_POWERTXHT20_5_S 8
1271 #define AR_PHY_POWERTX_RATE8 (AR_SM_BASE + 0x1dc)
1272 #define AR_PHY_POWERTX_RATE8_POWERTXHT40_5 0x3F00
1273 #define AR_PHY_POWERTX_RATE8_POWERTXHT40_5_S 8
1275 #define AR_PHY_CL_TAB_CL_GAIN_MOD 0x1f
1276 #define AR_PHY_CL_TAB_CL_GAIN_MOD_S 0
1278 #define AR_BTCOEX_WL_LNADIV 0x1a64
1279 #define AR_BTCOEX_WL_LNADIV_PREDICTED_PERIOD 0x00003FFF
1280 #define AR_BTCOEX_WL_LNADIV_PREDICTED_PERIOD_S 0
1281 #define AR_BTCOEX_WL_LNADIV_DPDT_IGNORE_PRIORITY 0x00004000
1282 #define AR_BTCOEX_WL_LNADIV_DPDT_IGNORE_PRIORITY_S 14
1283 #define AR_BTCOEX_WL_LNADIV_FORCE_ON 0x00008000
1284 #define AR_BTCOEX_WL_LNADIV_FORCE_ON_S 15
1285 #define AR_BTCOEX_WL_LNADIV_MODE_OPTION 0x00030000
1286 #define AR_BTCOEX_WL_LNADIV_MODE_OPTION_S 16
1287 #define AR_BTCOEX_WL_LNADIV_MODE 0x007c0000
1288 #define AR_BTCOEX_WL_LNADIV_MODE_S 18
1289 #define AR_BTCOEX_WL_LNADIV_ALLOWED_TX_ANTDIV_WL_TX_REQ 0x00800000
1290 #define AR_BTCOEX_WL_LNADIV_ALLOWED_TX_ANTDIV_WL_TX_REQ_S 23
1291 #define AR_BTCOEX_WL_LNADIV_DISABLE_TX_ANTDIV_ENABLE 0x01000000
1292 #define AR_BTCOEX_WL_LNADIV_DISABLE_TX_ANTDIV_ENABLE_S 24
1293 #define AR_BTCOEX_WL_LNADIV_CONTINUOUS_BT_ACTIVE_PROTECT 0x02000000
1294 #define AR_BTCOEX_WL_LNADIV_CONTINUOUS_BT_ACTIVE_PROTECT_S 25
1295 #define AR_BTCOEX_WL_LNADIV_BT_INACTIVE_THRESHOLD 0xFC000000
1296 #define AR_BTCOEX_WL_LNADIV_BT_INACTIVE_THRESHOLD_S 26
1298 /* Manual Peak detector calibration */
1299 #define AR_PHY_65NM_BASE 0x16000
1300 #define AR_PHY_65NM_RXRF_GAINSTAGES(i) (AR_PHY_65NM_BASE + \
1302 #define AR_PHY_65NM_RXRF_GAINSTAGES_RX_OVERRIDE 0x80000000
1303 #define AR_PHY_65NM_RXRF_GAINSTAGES_RX_OVERRIDE_S 31
1304 #define AR_PHY_65NM_RXRF_GAINSTAGES_LNAON_CALDC 0x00000002
1305 #define AR_PHY_65NM_RXRF_GAINSTAGES_LNAON_CALDC_S 1
1306 #define AR_PHY_65NM_RXRF_GAINSTAGES_LNA2G_GAIN_OVR 0x70000000
1307 #define AR_PHY_65NM_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_S 28
1308 #define AR_PHY_65NM_RXRF_GAINSTAGES_LNA5G_GAIN_OVR 0x03800000
1309 #define AR_PHY_65NM_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_S 23
1311 #define AR_PHY_65NM_RXTX2(i) (AR_PHY_65NM_BASE + \
1312 (i * 0x400) + 0x104)
1313 #define AR_PHY_65NM_RXTX2_RXON_OVR 0x00001000
1314 #define AR_PHY_65NM_RXTX2_RXON_OVR_S 12
1315 #define AR_PHY_65NM_RXTX2_RXON 0x00000800
1316 #define AR_PHY_65NM_RXTX2_RXON_S 11
1318 #define AR_PHY_65NM_RXRF_AGC(i) (AR_PHY_65NM_BASE + \
1320 #define AR_PHY_65NM_RXRF_AGC_AGC_OVERRIDE 0x80000000
1321 #define AR_PHY_65NM_RXRF_AGC_AGC_OVERRIDE_S 31
1322 #define AR_PHY_65NM_RXRF_AGC_AGC_ON_OVR 0x40000000
1323 #define AR_PHY_65NM_RXRF_AGC_AGC_ON_OVR_S 30
1324 #define AR_PHY_65NM_RXRF_AGC_AGC_CAL_OVR 0x20000000
1325 #define AR_PHY_65NM_RXRF_AGC_AGC_CAL_OVR_S 29
1326 #define AR_PHY_65NM_RXRF_AGC_AGC2G_DBDAC_OVR 0x1E000000
1327 #define AR_PHY_65NM_RXRF_AGC_AGC2G_DBDAC_OVR_S 25
1328 #define AR_PHY_65NM_RXRF_AGC_AGC5G_DBDAC_OVR 0x00078000
1329 #define AR_PHY_65NM_RXRF_AGC_AGC5G_DBDAC_OVR_S 15
1330 #define AR_PHY_65NM_RXRF_AGC_AGC2G_CALDAC_OVR 0x01F80000
1331 #define AR_PHY_65NM_RXRF_AGC_AGC2G_CALDAC_OVR_S 19
1332 #define AR_PHY_65NM_RXRF_AGC_AGC5G_CALDAC_OVR 0x00007e00
1333 #define AR_PHY_65NM_RXRF_AGC_AGC5G_CALDAC_OVR_S 9
1334 #define AR_PHY_65NM_RXRF_AGC_AGC_OUT 0x00000004
1335 #define AR_PHY_65NM_RXRF_AGC_AGC_OUT_S 2
1337 #define AR9300_DFS_FIRPWR -28
1339 #endif /* AR9003_PHY_H */