2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/export.h>
20 #include "ar9003_phy.h"
21 #include "ar9003_mci.h"
23 static void ar9003_mci_reset_req_wakeup(struct ath_hw *ah)
25 REG_RMW_FIELD(ah, AR_MCI_COMMAND2,
26 AR_MCI_COMMAND2_RESET_REQ_WAKEUP, 1);
28 REG_RMW_FIELD(ah, AR_MCI_COMMAND2,
29 AR_MCI_COMMAND2_RESET_REQ_WAKEUP, 0);
32 static int ar9003_mci_wait_for_interrupt(struct ath_hw *ah, u32 address,
33 u32 bit_position, int time_out)
35 struct ath_common *common = ath9k_hw_common(ah);
38 if (REG_READ(ah, address) & bit_position) {
39 REG_WRITE(ah, address, bit_position);
41 if (address == AR_MCI_INTERRUPT_RX_MSG_RAW) {
43 AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE)
44 ar9003_mci_reset_req_wakeup(ah);
47 (AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING |
48 AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING))
49 REG_WRITE(ah, AR_MCI_INTERRUPT_RAW,
50 AR_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE);
52 REG_WRITE(ah, AR_MCI_INTERRUPT_RAW,
53 AR_MCI_INTERRUPT_RX_MSG);
67 "MCI Wait for Reg 0x%08x = 0x%08x timeout\n",
68 address, bit_position);
70 "MCI INT_RAW = 0x%08x, RX_MSG_RAW = 0x%08x\n",
71 REG_READ(ah, AR_MCI_INTERRUPT_RAW),
72 REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW));
79 static void ar9003_mci_remote_reset(struct ath_hw *ah, bool wait_done)
81 u32 payload[4] = { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffff00};
83 ar9003_mci_send_message(ah, MCI_REMOTE_RESET, 0, payload, 16,
88 static void ar9003_mci_send_lna_transfer(struct ath_hw *ah, bool wait_done)
90 u32 payload = 0x00000000;
92 ar9003_mci_send_message(ah, MCI_LNA_TRANS, 0, &payload, 1,
96 static void ar9003_mci_send_req_wake(struct ath_hw *ah, bool wait_done)
98 ar9003_mci_send_message(ah, MCI_REQ_WAKE, MCI_FLAG_DISABLE_TIMESTAMP,
99 NULL, 0, wait_done, false);
103 static void ar9003_mci_send_sys_waking(struct ath_hw *ah, bool wait_done)
105 ar9003_mci_send_message(ah, MCI_SYS_WAKING, MCI_FLAG_DISABLE_TIMESTAMP,
106 NULL, 0, wait_done, false);
109 static void ar9003_mci_send_lna_take(struct ath_hw *ah, bool wait_done)
111 u32 payload = 0x70000000;
113 ar9003_mci_send_message(ah, MCI_LNA_TAKE, 0, &payload, 1,
117 static void ar9003_mci_send_sys_sleeping(struct ath_hw *ah, bool wait_done)
119 ar9003_mci_send_message(ah, MCI_SYS_SLEEPING,
120 MCI_FLAG_DISABLE_TIMESTAMP,
121 NULL, 0, wait_done, false);
124 static void ar9003_mci_send_coex_version_query(struct ath_hw *ah,
127 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
128 u32 payload[4] = {0, 0, 0, 0};
130 if (!mci->bt_version_known &&
131 (mci->bt_state != MCI_BT_SLEEP)) {
132 MCI_GPM_SET_TYPE_OPCODE(payload,
134 MCI_GPM_COEX_VERSION_QUERY);
135 ar9003_mci_send_message(ah, MCI_GPM, 0, payload, 16,
140 static void ar9003_mci_send_coex_version_response(struct ath_hw *ah,
143 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
144 u32 payload[4] = {0, 0, 0, 0};
146 MCI_GPM_SET_TYPE_OPCODE(payload, MCI_GPM_COEX_AGENT,
147 MCI_GPM_COEX_VERSION_RESPONSE);
148 *(((u8 *)payload) + MCI_GPM_COEX_B_MAJOR_VERSION) =
150 *(((u8 *)payload) + MCI_GPM_COEX_B_MINOR_VERSION) =
152 ar9003_mci_send_message(ah, MCI_GPM, 0, payload, 16, wait_done, true);
155 static void ar9003_mci_send_coex_wlan_channels(struct ath_hw *ah,
158 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
159 u32 *payload = &mci->wlan_channels[0];
161 if ((mci->wlan_channels_update == true) &&
162 (mci->bt_state != MCI_BT_SLEEP)) {
163 MCI_GPM_SET_TYPE_OPCODE(payload,
165 MCI_GPM_COEX_WLAN_CHANNELS);
166 ar9003_mci_send_message(ah, MCI_GPM, 0, payload, 16,
168 MCI_GPM_SET_TYPE_OPCODE(payload, 0xff, 0xff);
172 static void ar9003_mci_send_coex_bt_status_query(struct ath_hw *ah,
173 bool wait_done, u8 query_type)
175 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
176 u32 payload[4] = {0, 0, 0, 0};
177 bool query_btinfo = !!(query_type & (MCI_GPM_COEX_QUERY_BT_ALL_INFO |
178 MCI_GPM_COEX_QUERY_BT_TOPOLOGY));
180 if (mci->bt_state != MCI_BT_SLEEP) {
182 MCI_GPM_SET_TYPE_OPCODE(payload, MCI_GPM_COEX_AGENT,
183 MCI_GPM_COEX_STATUS_QUERY);
185 *(((u8 *)payload) + MCI_GPM_COEX_B_BT_BITMAP) = query_type;
188 * If bt_status_query message is not sent successfully,
189 * then need_flush_btinfo should be set again.
191 if (!ar9003_mci_send_message(ah, MCI_GPM, 0, payload, 16,
194 mci->need_flush_btinfo = true;
198 mci->query_bt = false;
202 static void ar9003_mci_send_coex_halt_bt_gpm(struct ath_hw *ah, bool halt,
205 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
206 u32 payload[4] = {0, 0, 0, 0};
208 MCI_GPM_SET_TYPE_OPCODE(payload, MCI_GPM_COEX_AGENT,
209 MCI_GPM_COEX_HALT_BT_GPM);
212 mci->query_bt = true;
213 /* Send next unhalt no matter halt sent or not */
214 mci->unhalt_bt_gpm = true;
215 mci->need_flush_btinfo = true;
216 *(((u8 *)payload) + MCI_GPM_COEX_B_HALT_STATE) =
217 MCI_GPM_COEX_BT_GPM_HALT;
219 *(((u8 *)payload) + MCI_GPM_COEX_B_HALT_STATE) =
220 MCI_GPM_COEX_BT_GPM_UNHALT;
222 ar9003_mci_send_message(ah, MCI_GPM, 0, payload, 16, wait_done, true);
225 static void ar9003_mci_prep_interface(struct ath_hw *ah)
227 struct ath_common *common = ath9k_hw_common(ah);
228 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
229 u32 saved_mci_int_en;
230 u32 mci_timeout = 150;
232 mci->bt_state = MCI_BT_SLEEP;
233 saved_mci_int_en = REG_READ(ah, AR_MCI_INTERRUPT_EN);
235 REG_WRITE(ah, AR_MCI_INTERRUPT_EN, 0);
236 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,
237 REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW));
238 REG_WRITE(ah, AR_MCI_INTERRUPT_RAW,
239 REG_READ(ah, AR_MCI_INTERRUPT_RAW));
241 ar9003_mci_remote_reset(ah, true);
242 ar9003_mci_send_req_wake(ah, true);
244 if (ar9003_mci_wait_for_interrupt(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,
245 AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING, 500)) {
247 mci->bt_state = MCI_BT_AWAKE;
250 * we don't need to send more remote_reset at this moment.
251 * If BT receive first remote_reset, then BT HW will
252 * be cleaned up and will be able to receive req_wake
253 * and BT HW will respond sys_waking.
254 * In this case, WLAN will receive BT's HW sys_waking.
255 * Otherwise, if BT SW missed initial remote_reset,
256 * that remote_reset will still clean up BT MCI RX,
257 * and the req_wake will wake BT up,
258 * and BT SW will respond this req_wake with a remote_reset and
259 * sys_waking. In this case, WLAN will receive BT's SW
260 * sys_waking. In either case, BT's RX is cleaned up. So we
261 * don't need to reply BT's remote_reset now, if any.
262 * Similarly, if in any case, WLAN can receive BT's sys_waking,
263 * that means WLAN's RX is also fine.
265 ar9003_mci_send_sys_waking(ah, true);
269 * Set BT priority interrupt value to be 0xff to
270 * avoid having too many BT PRIORITY interrupts.
272 REG_WRITE(ah, AR_MCI_BT_PRI0, 0xFFFFFFFF);
273 REG_WRITE(ah, AR_MCI_BT_PRI1, 0xFFFFFFFF);
274 REG_WRITE(ah, AR_MCI_BT_PRI2, 0xFFFFFFFF);
275 REG_WRITE(ah, AR_MCI_BT_PRI3, 0xFFFFFFFF);
276 REG_WRITE(ah, AR_MCI_BT_PRI, 0X000000FF);
279 * A contention reset will be received after send out
280 * sys_waking. Also BT priority interrupt bits will be set.
281 * Clear those bits before the next step.
284 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,
285 AR_MCI_INTERRUPT_RX_MSG_CONT_RST);
286 REG_WRITE(ah, AR_MCI_INTERRUPT_RAW,
287 AR_MCI_INTERRUPT_BT_PRI);
290 ar9003_mci_send_lna_transfer(ah, true);
294 if ((mci->is_2g && !mci->update_2g5g)) {
295 if (ar9003_mci_wait_for_interrupt(ah,
296 AR_MCI_INTERRUPT_RX_MSG_RAW,
297 AR_MCI_INTERRUPT_RX_MSG_LNA_INFO,
300 "MCI WLAN has control over the LNA & BT obeys it\n");
303 "MCI BT didn't respond to LNA_TRANS\n");
307 /* Clear the extra redundant SYS_WAKING from BT */
308 if ((mci->bt_state == MCI_BT_AWAKE) &&
309 (REG_READ_FIELD(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,
310 AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING)) &&
311 (REG_READ_FIELD(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,
312 AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING) == 0)) {
313 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,
314 AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING);
315 REG_WRITE(ah, AR_MCI_INTERRUPT_RAW,
316 AR_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE);
319 REG_WRITE(ah, AR_MCI_INTERRUPT_EN, saved_mci_int_en);
322 void ar9003_mci_set_full_sleep(struct ath_hw *ah)
324 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
326 if (ar9003_mci_state(ah, MCI_STATE_ENABLE, NULL) &&
327 (mci->bt_state != MCI_BT_SLEEP) &&
328 !mci->halted_bt_gpm) {
329 ar9003_mci_send_coex_halt_bt_gpm(ah, true, true);
333 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
336 static void ar9003_mci_disable_interrupt(struct ath_hw *ah)
338 REG_WRITE(ah, AR_MCI_INTERRUPT_EN, 0);
339 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0);
342 static void ar9003_mci_enable_interrupt(struct ath_hw *ah)
344 REG_WRITE(ah, AR_MCI_INTERRUPT_EN, AR_MCI_INTERRUPT_DEFAULT);
345 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN,
346 AR_MCI_INTERRUPT_RX_MSG_DEFAULT);
349 static bool ar9003_mci_check_int(struct ath_hw *ah, u32 ints)
353 intr = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW);
354 return ((intr & ints) == ints);
357 void ar9003_mci_get_interrupt(struct ath_hw *ah, u32 *raw_intr,
360 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
362 *raw_intr = mci->raw_intr;
363 *rx_msg_intr = mci->rx_msg_intr;
365 /* Clean int bits after the values are read. */
367 mci->rx_msg_intr = 0;
369 EXPORT_SYMBOL(ar9003_mci_get_interrupt);
371 void ar9003_mci_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
373 struct ath_common *common = ath9k_hw_common(ah);
374 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
375 u32 raw_intr, rx_msg_intr;
377 rx_msg_intr = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW);
378 raw_intr = REG_READ(ah, AR_MCI_INTERRUPT_RAW);
380 if ((raw_intr == 0xdeadbeef) || (rx_msg_intr == 0xdeadbeef)) {
382 "MCI gets 0xdeadbeef during int processing\n");
384 mci->rx_msg_intr |= rx_msg_intr;
385 mci->raw_intr |= raw_intr;
386 *masked |= ATH9K_INT_MCI;
388 if (rx_msg_intr & AR_MCI_INTERRUPT_RX_MSG_CONT_INFO)
389 mci->cont_status = REG_READ(ah, AR_MCI_CONT_STATUS);
391 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW, rx_msg_intr);
392 REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, raw_intr);
396 static void ar9003_mci_2g5g_changed(struct ath_hw *ah, bool is_2g)
398 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
400 if (!mci->update_2g5g &&
401 (mci->is_2g != is_2g))
402 mci->update_2g5g = true;
407 static bool ar9003_mci_is_gpm_valid(struct ath_hw *ah, u32 msg_index)
409 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
411 u32 recv_type, offset;
413 if (msg_index == MCI_GPM_INVALID)
416 offset = msg_index << 4;
418 payload = (u32 *)(mci->gpm_buf + offset);
419 recv_type = MCI_GPM_TYPE(payload);
421 if (recv_type == MCI_GPM_RSVD_PATTERN)
427 static void ar9003_mci_observation_set_up(struct ath_hw *ah)
429 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
431 if (mci->config & ATH_MCI_CONFIG_MCI_OBS_MCI) {
432 ath9k_hw_cfg_output(ah, 3, AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA);
433 ath9k_hw_cfg_output(ah, 2, AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK);
434 ath9k_hw_cfg_output(ah, 1, AR_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA);
435 ath9k_hw_cfg_output(ah, 0, AR_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK);
436 } else if (mci->config & ATH_MCI_CONFIG_MCI_OBS_TXRX) {
437 ath9k_hw_cfg_output(ah, 3, AR_GPIO_OUTPUT_MUX_AS_WL_IN_TX);
438 ath9k_hw_cfg_output(ah, 2, AR_GPIO_OUTPUT_MUX_AS_WL_IN_RX);
439 ath9k_hw_cfg_output(ah, 1, AR_GPIO_OUTPUT_MUX_AS_BT_IN_TX);
440 ath9k_hw_cfg_output(ah, 0, AR_GPIO_OUTPUT_MUX_AS_BT_IN_RX);
441 ath9k_hw_cfg_output(ah, 5, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
442 } else if (mci->config & ATH_MCI_CONFIG_MCI_OBS_BT) {
443 ath9k_hw_cfg_output(ah, 3, AR_GPIO_OUTPUT_MUX_AS_BT_IN_TX);
444 ath9k_hw_cfg_output(ah, 2, AR_GPIO_OUTPUT_MUX_AS_BT_IN_RX);
445 ath9k_hw_cfg_output(ah, 1, AR_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA);
446 ath9k_hw_cfg_output(ah, 0, AR_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK);
450 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
452 REG_RMW_FIELD(ah, AR_PHY_GLB_CONTROL, AR_GLB_DS_JTAG_DISABLE, 1);
453 REG_RMW_FIELD(ah, AR_PHY_GLB_CONTROL, AR_GLB_WLAN_UART_INTF_EN, 0);
454 REG_SET_BIT(ah, AR_GLB_GPIO_CONTROL, ATH_MCI_CONFIG_MCI_OBS_GPIO);
456 REG_RMW_FIELD(ah, AR_BTCOEX_CTRL2, AR_BTCOEX_CTRL2_GPIO_OBS_SEL, 0);
457 REG_RMW_FIELD(ah, AR_BTCOEX_CTRL2, AR_BTCOEX_CTRL2_MAC_BB_OBS_SEL, 1);
458 REG_WRITE(ah, AR_OBS, 0x4b);
459 REG_RMW_FIELD(ah, AR_DIAG_SW, AR_DIAG_OBS_PT_SEL1, 0x03);
460 REG_RMW_FIELD(ah, AR_DIAG_SW, AR_DIAG_OBS_PT_SEL2, 0x01);
461 REG_RMW_FIELD(ah, AR_MACMISC, AR_MACMISC_MISC_OBS_BUS_LSB, 0x02);
462 REG_RMW_FIELD(ah, AR_MACMISC, AR_MACMISC_MISC_OBS_BUS_MSB, 0x03);
463 REG_RMW_FIELD(ah, AR_PHY_TEST_CTL_STATUS,
464 AR_PHY_TEST_CTL_DEBUGPORT_SEL, 0x07);
467 static bool ar9003_mci_send_coex_bt_flags(struct ath_hw *ah, bool wait_done,
468 u8 opcode, u32 bt_flags)
470 u32 pld[4] = {0, 0, 0, 0};
472 MCI_GPM_SET_TYPE_OPCODE(pld, MCI_GPM_COEX_AGENT,
473 MCI_GPM_COEX_BT_UPDATE_FLAGS);
475 *(((u8 *)pld) + MCI_GPM_COEX_B_BT_FLAGS_OP) = opcode;
476 *(((u8 *)pld) + MCI_GPM_COEX_W_BT_FLAGS + 0) = bt_flags & 0xFF;
477 *(((u8 *)pld) + MCI_GPM_COEX_W_BT_FLAGS + 1) = (bt_flags >> 8) & 0xFF;
478 *(((u8 *)pld) + MCI_GPM_COEX_W_BT_FLAGS + 2) = (bt_flags >> 16) & 0xFF;
479 *(((u8 *)pld) + MCI_GPM_COEX_W_BT_FLAGS + 3) = (bt_flags >> 24) & 0xFF;
481 return ar9003_mci_send_message(ah, MCI_GPM, 0, pld, 16,
485 static void ar9003_mci_sync_bt_state(struct ath_hw *ah)
487 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
490 cur_bt_state = ar9003_mci_state(ah, MCI_STATE_REMOTE_SLEEP, NULL);
492 if (mci->bt_state != cur_bt_state)
493 mci->bt_state = cur_bt_state;
495 if (mci->bt_state != MCI_BT_SLEEP) {
497 ar9003_mci_send_coex_version_query(ah, true);
498 ar9003_mci_send_coex_wlan_channels(ah, true);
500 if (mci->unhalt_bt_gpm == true)
501 ar9003_mci_send_coex_halt_bt_gpm(ah, false, true);
505 void ar9003_mci_check_bt(struct ath_hw *ah)
507 struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci;
513 * check BT state again to make
514 * sure it's not changed.
516 ar9003_mci_sync_bt_state(ah);
517 ar9003_mci_2g5g_switch(ah, true);
519 if ((mci_hw->bt_state == MCI_BT_AWAKE) &&
520 (mci_hw->query_bt == true)) {
521 mci_hw->need_flush_btinfo = true;
525 static void ar9003_mci_process_gpm_extra(struct ath_hw *ah, u8 gpm_type,
526 u8 gpm_opcode, u32 *p_gpm)
528 struct ath_common *common = ath9k_hw_common(ah);
529 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
530 u8 *p_data = (u8 *) p_gpm;
532 if (gpm_type != MCI_GPM_COEX_AGENT)
535 switch (gpm_opcode) {
536 case MCI_GPM_COEX_VERSION_QUERY:
537 ath_dbg(common, MCI, "MCI Recv GPM COEX Version Query\n");
538 ar9003_mci_send_coex_version_response(ah, true);
540 case MCI_GPM_COEX_VERSION_RESPONSE:
541 ath_dbg(common, MCI, "MCI Recv GPM COEX Version Response\n");
543 *(p_data + MCI_GPM_COEX_B_MAJOR_VERSION);
545 *(p_data + MCI_GPM_COEX_B_MINOR_VERSION);
546 mci->bt_version_known = true;
547 ath_dbg(common, MCI, "MCI BT Coex version: %d.%d\n",
548 mci->bt_ver_major, mci->bt_ver_minor);
550 case MCI_GPM_COEX_STATUS_QUERY:
552 "MCI Recv GPM COEX Status Query = 0x%02X\n",
553 *(p_data + MCI_GPM_COEX_B_WLAN_BITMAP));
554 mci->wlan_channels_update = true;
555 ar9003_mci_send_coex_wlan_channels(ah, true);
557 case MCI_GPM_COEX_BT_PROFILE_INFO:
558 mci->query_bt = true;
559 ath_dbg(common, MCI, "MCI Recv GPM COEX BT_Profile_Info\n");
561 case MCI_GPM_COEX_BT_STATUS_UPDATE:
562 mci->query_bt = true;
564 "MCI Recv GPM COEX BT_Status_Update SEQ=%d (drop&query)\n",
572 static u32 ar9003_mci_wait_for_gpm(struct ath_hw *ah, u8 gpm_type,
573 u8 gpm_opcode, int time_out)
575 struct ath_common *common = ath9k_hw_common(ah);
576 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
577 u32 *p_gpm = NULL, mismatch = 0, more_data;
579 u8 recv_type = 0, recv_opcode = 0;
580 bool b_is_bt_cal_done = (gpm_type == MCI_GPM_BT_CAL_DONE);
582 more_data = time_out ? MCI_GPM_NOMORE : MCI_GPM_MORE;
584 while (time_out > 0) {
586 MCI_GPM_RECYCLE(p_gpm);
590 if (more_data != MCI_GPM_MORE)
591 time_out = ar9003_mci_wait_for_interrupt(ah,
592 AR_MCI_INTERRUPT_RX_MSG_RAW,
593 AR_MCI_INTERRUPT_RX_MSG_GPM,
599 offset = ar9003_mci_state(ah, MCI_STATE_NEXT_GPM_OFFSET,
602 if (offset == MCI_GPM_INVALID)
605 p_gpm = (u32 *) (mci->gpm_buf + offset);
606 recv_type = MCI_GPM_TYPE(p_gpm);
607 recv_opcode = MCI_GPM_OPCODE(p_gpm);
609 if (MCI_GPM_IS_CAL_TYPE(recv_type)) {
610 if (recv_type == gpm_type) {
611 if ((gpm_type == MCI_GPM_BT_CAL_DONE) &&
613 gpm_type = MCI_GPM_BT_CAL_GRANT;
618 } else if ((recv_type == gpm_type) && (recv_opcode == gpm_opcode)) {
623 * check if it's cal_grant
625 * When we're waiting for cal_grant in reset routine,
626 * it's possible that BT sends out cal_request at the
627 * same time. Since BT's calibration doesn't happen
628 * that often, we'll let BT completes calibration then
629 * we continue to wait for cal_grant from BT.
630 * Orginal: Wait BT_CAL_GRANT.
631 * New: Receive BT_CAL_REQ -> send WLAN_CAL_GRANT->wait
632 * BT_CAL_DONE -> Wait BT_CAL_GRANT.
635 if ((gpm_type == MCI_GPM_BT_CAL_GRANT) &&
636 (recv_type == MCI_GPM_BT_CAL_REQ)) {
638 u32 payload[4] = {0, 0, 0, 0};
640 gpm_type = MCI_GPM_BT_CAL_DONE;
641 MCI_GPM_SET_CAL_TYPE(payload,
642 MCI_GPM_WLAN_CAL_GRANT);
643 ar9003_mci_send_message(ah, MCI_GPM, 0, payload, 16,
647 ath_dbg(common, MCI, "MCI GPM subtype not match 0x%x\n",
650 ar9003_mci_process_gpm_extra(ah, recv_type,
656 MCI_GPM_RECYCLE(p_gpm);
663 while (more_data == MCI_GPM_MORE) {
664 offset = ar9003_mci_state(ah, MCI_STATE_NEXT_GPM_OFFSET,
666 if (offset == MCI_GPM_INVALID)
669 p_gpm = (u32 *) (mci->gpm_buf + offset);
670 recv_type = MCI_GPM_TYPE(p_gpm);
671 recv_opcode = MCI_GPM_OPCODE(p_gpm);
673 if (!MCI_GPM_IS_CAL_TYPE(recv_type))
674 ar9003_mci_process_gpm_extra(ah, recv_type,
677 MCI_GPM_RECYCLE(p_gpm);
683 bool ar9003_mci_start_reset(struct ath_hw *ah, struct ath9k_channel *chan)
685 struct ath_common *common = ath9k_hw_common(ah);
686 struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci;
687 u32 payload[4] = {0, 0, 0, 0};
689 ar9003_mci_2g5g_changed(ah, IS_CHAN_2GHZ(chan));
691 if (mci_hw->bt_state != MCI_BT_CAL_START)
694 mci_hw->bt_state = MCI_BT_CAL;
697 * MCI FIX: disable mci interrupt here. This is to avoid
698 * SW_MSG_DONE or RX_MSG bits to trigger MCI_INT and
699 * lead to mci_intr reentry.
701 ar9003_mci_disable_interrupt(ah);
703 MCI_GPM_SET_CAL_TYPE(payload, MCI_GPM_WLAN_CAL_GRANT);
704 ar9003_mci_send_message(ah, MCI_GPM, 0, payload,
707 /* Wait BT calibration to be completed for 25ms */
709 if (ar9003_mci_wait_for_gpm(ah, MCI_GPM_BT_CAL_DONE,
711 ath_dbg(common, MCI, "MCI BT_CAL_DONE received\n");
714 "MCI BT_CAL_DONE not received\n");
716 mci_hw->bt_state = MCI_BT_AWAKE;
717 /* MCI FIX: enable mci interrupt here */
718 ar9003_mci_enable_interrupt(ah);
723 int ar9003_mci_end_reset(struct ath_hw *ah, struct ath9k_channel *chan,
724 struct ath9k_hw_cal_data *caldata)
726 struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci;
731 if (!IS_CHAN_2GHZ(chan) || (mci_hw->bt_state != MCI_BT_SLEEP))
734 if (ar9003_mci_check_int(ah, AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET) ||
735 ar9003_mci_check_int(ah, AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE)) {
738 * BT is sleeping. Check if BT wakes up during
739 * WLAN calibration. If BT wakes up during
740 * WLAN calibration, need to go through all
741 * message exchanges again and recal.
743 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,
744 AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET |
745 AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE);
747 ar9003_mci_remote_reset(ah, true);
748 ar9003_mci_send_sys_waking(ah, true);
751 if (IS_CHAN_2GHZ(chan))
752 ar9003_mci_send_lna_transfer(ah, true);
754 mci_hw->bt_state = MCI_BT_AWAKE;
757 caldata->done_txiqcal_once = false;
758 caldata->done_txclcal_once = false;
759 caldata->rtt_hist.num_readings = 0;
762 if (!ath9k_hw_init_cal(ah, chan))
767 ar9003_mci_enable_interrupt(ah);
771 static void ar9003_mci_mute_bt(struct ath_hw *ah)
773 /* disable all MCI messages */
774 REG_WRITE(ah, AR_MCI_MSG_ATTRIBUTES_TABLE, 0xffff0000);
775 REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS0, 0xffffffff);
776 REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS1, 0xffffffff);
777 REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS2, 0xffffffff);
778 REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS3, 0xffffffff);
779 REG_SET_BIT(ah, AR_MCI_TX_CTRL, AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE);
781 /* wait pending HW messages to flush out */
785 * Send LNA_TAKE and SYS_SLEEPING when
786 * 1. reset not after resuming from full sleep
787 * 2. before reset MCI RX, to quiet BT and avoid MCI RX misalignment
789 ar9003_mci_send_lna_take(ah, true);
793 ar9003_mci_send_sys_sleeping(ah, true);
796 static void ar9003_mci_osla_setup(struct ath_hw *ah, bool enable)
798 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
802 REG_RMW_FIELD(ah, AR_MCI_SCHD_TABLE_2,
803 AR_MCI_SCHD_TABLE_2_HW_BASED, 1);
804 REG_RMW_FIELD(ah, AR_MCI_SCHD_TABLE_2,
805 AR_MCI_SCHD_TABLE_2_MEM_BASED, 1);
807 if (!(mci->config & ATH_MCI_CONFIG_DISABLE_AGGR_THRESH)) {
808 thresh = MS(mci->config, ATH_MCI_CONFIG_AGGR_THRESH);
809 REG_RMW_FIELD(ah, AR_BTCOEX_CTRL,
810 AR_BTCOEX_CTRL_AGGR_THRESH, thresh);
811 REG_RMW_FIELD(ah, AR_BTCOEX_CTRL,
812 AR_BTCOEX_CTRL_TIME_TO_NEXT_BT_THRESH_EN, 1);
814 REG_RMW_FIELD(ah, AR_BTCOEX_CTRL,
815 AR_BTCOEX_CTRL_TIME_TO_NEXT_BT_THRESH_EN, 0);
818 REG_RMW_FIELD(ah, AR_BTCOEX_CTRL,
819 AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN, 1);
821 REG_CLR_BIT(ah, AR_BTCOEX_CTRL,
822 AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN);
826 void ar9003_mci_reset(struct ath_hw *ah, bool en_int, bool is_2g,
829 struct ath_common *common = ath9k_hw_common(ah);
830 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
833 ath_dbg(common, MCI, "MCI Reset (full_sleep = %d, is_2g = %d)\n",
834 is_full_sleep, is_2g);
836 if (!mci->gpm_addr && !mci->sched_addr) {
838 "MCI GPM and schedule buffers are not allocated\n");
842 if (REG_READ(ah, AR_BTCOEX_CTRL) == 0xdeadbeef) {
843 ath_dbg(common, MCI, "BTCOEX control register is dead\n");
847 /* Program MCI DMA related registers */
848 REG_WRITE(ah, AR_MCI_GPM_0, mci->gpm_addr);
849 REG_WRITE(ah, AR_MCI_GPM_1, mci->gpm_len);
850 REG_WRITE(ah, AR_MCI_SCHD_TABLE_0, mci->sched_addr);
853 * To avoid MCI state machine be affected by incoming remote MCI msgs,
854 * MCI mode will be enabled later, right before reset the MCI TX and RX.
857 regval = SM(1, AR_BTCOEX_CTRL_AR9462_MODE) |
858 SM(1, AR_BTCOEX_CTRL_WBTIMER_EN) |
859 SM(1, AR_BTCOEX_CTRL_PA_SHARED) |
860 SM(1, AR_BTCOEX_CTRL_LNA_SHARED) |
861 SM(2, AR_BTCOEX_CTRL_NUM_ANTENNAS) |
862 SM(3, AR_BTCOEX_CTRL_RX_CHAIN_MASK) |
863 SM(0, AR_BTCOEX_CTRL_1_CHAIN_ACK) |
864 SM(0, AR_BTCOEX_CTRL_1_CHAIN_BCN) |
865 SM(0, AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN);
867 REG_WRITE(ah, AR_BTCOEX_CTRL, regval);
869 if (is_2g && !(mci->config & ATH_MCI_CONFIG_DISABLE_OSLA))
870 ar9003_mci_osla_setup(ah, true);
872 ar9003_mci_osla_setup(ah, false);
874 REG_SET_BIT(ah, AR_PHY_GLB_CONTROL,
875 AR_BTCOEX_CTRL_SPDT_ENABLE);
876 REG_RMW_FIELD(ah, AR_BTCOEX_CTRL3,
877 AR_BTCOEX_CTRL3_CONT_INFO_TIMEOUT, 20);
879 REG_RMW_FIELD(ah, AR_BTCOEX_CTRL2, AR_BTCOEX_CTRL2_RX_DEWEIGHT, 1);
880 REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0);
882 regval = MS(mci->config, ATH_MCI_CONFIG_CLK_DIV);
883 REG_RMW_FIELD(ah, AR_MCI_TX_CTRL, AR_MCI_TX_CTRL_CLK_DIV, regval);
884 REG_SET_BIT(ah, AR_BTCOEX_CTRL, AR_BTCOEX_CTRL_MCI_MODE_EN);
886 /* Resetting the Rx and Tx paths of MCI */
887 regval = REG_READ(ah, AR_MCI_COMMAND2);
888 regval |= SM(1, AR_MCI_COMMAND2_RESET_TX);
889 REG_WRITE(ah, AR_MCI_COMMAND2, regval);
893 regval &= ~SM(1, AR_MCI_COMMAND2_RESET_TX);
894 REG_WRITE(ah, AR_MCI_COMMAND2, regval);
897 ar9003_mci_mute_bt(ah);
901 regval |= SM(1, AR_MCI_COMMAND2_RESET_RX);
902 REG_WRITE(ah, AR_MCI_COMMAND2, regval);
904 regval &= ~SM(1, AR_MCI_COMMAND2_RESET_RX);
905 REG_WRITE(ah, AR_MCI_COMMAND2, regval);
907 ar9003_mci_state(ah, MCI_STATE_INIT_GPM_OFFSET, NULL);
909 REG_WRITE(ah, AR_MCI_MSG_ATTRIBUTES_TABLE,
910 (SM(0xe801, AR_MCI_MSG_ATTRIBUTES_TABLE_INVALID_HDR) |
911 SM(0x0000, AR_MCI_MSG_ATTRIBUTES_TABLE_CHECKSUM)));
913 REG_CLR_BIT(ah, AR_MCI_TX_CTRL,
914 AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE);
916 ar9003_mci_observation_set_up(ah);
919 ar9003_mci_prep_interface(ah);
922 ar9003_mci_enable_interrupt(ah);
925 void ar9003_mci_stop_bt(struct ath_hw *ah, bool save_fullsleep)
927 struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci;
929 ar9003_mci_disable_interrupt(ah);
931 if (mci_hw->ready && !save_fullsleep) {
932 ar9003_mci_mute_bt(ah);
934 REG_WRITE(ah, AR_BTCOEX_CTRL, 0);
937 mci_hw->bt_state = MCI_BT_SLEEP;
938 mci_hw->ready = false;
941 static void ar9003_mci_send_2g5g_status(struct ath_hw *ah, bool wait_done)
943 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
944 u32 new_flags, to_set, to_clear;
946 if (mci->update_2g5g && (mci->bt_state != MCI_BT_SLEEP)) {
948 new_flags = MCI_2G_FLAGS;
949 to_clear = MCI_2G_FLAGS_CLEAR_MASK;
950 to_set = MCI_2G_FLAGS_SET_MASK;
952 new_flags = MCI_5G_FLAGS;
953 to_clear = MCI_5G_FLAGS_CLEAR_MASK;
954 to_set = MCI_5G_FLAGS_SET_MASK;
958 ar9003_mci_send_coex_bt_flags(ah, wait_done,
959 MCI_GPM_COEX_BT_FLAGS_CLEAR,
962 ar9003_mci_send_coex_bt_flags(ah, wait_done,
963 MCI_GPM_COEX_BT_FLAGS_SET,
968 static void ar9003_mci_queue_unsent_gpm(struct ath_hw *ah, u8 header,
969 u32 *payload, bool queue)
971 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
974 /* check if the message is to be queued */
975 if (header != MCI_GPM)
978 type = MCI_GPM_TYPE(payload);
979 opcode = MCI_GPM_OPCODE(payload);
981 if (type != MCI_GPM_COEX_AGENT)
985 case MCI_GPM_COEX_BT_UPDATE_FLAGS:
986 if (*(((u8 *)payload) + MCI_GPM_COEX_B_BT_FLAGS_OP) ==
987 MCI_GPM_COEX_BT_FLAGS_READ)
990 mci->update_2g5g = queue;
993 case MCI_GPM_COEX_WLAN_CHANNELS:
994 mci->wlan_channels_update = queue;
996 case MCI_GPM_COEX_HALT_BT_GPM:
997 if (*(((u8 *)payload) + MCI_GPM_COEX_B_HALT_STATE) ==
998 MCI_GPM_COEX_BT_GPM_UNHALT) {
999 mci->unhalt_bt_gpm = queue;
1002 mci->halted_bt_gpm = false;
1005 if (*(((u8 *)payload) + MCI_GPM_COEX_B_HALT_STATE) ==
1006 MCI_GPM_COEX_BT_GPM_HALT) {
1008 mci->halted_bt_gpm = !queue;
1017 void ar9003_mci_2g5g_switch(struct ath_hw *ah, bool wait_done)
1019 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
1021 if (mci->update_2g5g) {
1023 ar9003_mci_send_2g5g_status(ah, true);
1024 ar9003_mci_send_lna_transfer(ah, true);
1027 REG_CLR_BIT(ah, AR_MCI_TX_CTRL,
1028 AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE);
1029 REG_CLR_BIT(ah, AR_PHY_GLB_CONTROL,
1030 AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL);
1032 if (!(mci->config & ATH_MCI_CONFIG_DISABLE_OSLA)) {
1033 REG_SET_BIT(ah, AR_BTCOEX_CTRL,
1034 AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN);
1037 ar9003_mci_send_lna_take(ah, true);
1040 REG_SET_BIT(ah, AR_MCI_TX_CTRL,
1041 AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE);
1042 REG_SET_BIT(ah, AR_PHY_GLB_CONTROL,
1043 AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL);
1044 REG_CLR_BIT(ah, AR_BTCOEX_CTRL,
1045 AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN);
1047 ar9003_mci_send_2g5g_status(ah, true);
1052 bool ar9003_mci_send_message(struct ath_hw *ah, u8 header, u32 flag,
1053 u32 *payload, u8 len, bool wait_done,
1056 struct ath_common *common = ath9k_hw_common(ah);
1057 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
1058 bool msg_sent = false;
1060 u32 saved_mci_int_en;
1063 saved_mci_int_en = REG_READ(ah, AR_MCI_INTERRUPT_EN);
1064 regval = REG_READ(ah, AR_BTCOEX_CTRL);
1066 if ((regval == 0xdeadbeef) || !(regval & AR_BTCOEX_CTRL_MCI_MODE_EN)) {
1067 ath_dbg(common, MCI,
1068 "MCI Not sending 0x%x. MCI is not enabled. full_sleep = %d\n",
1069 header, (ah->power_mode == ATH9K_PM_FULL_SLEEP) ? 1 : 0);
1070 ar9003_mci_queue_unsent_gpm(ah, header, payload, true);
1072 } else if (check_bt && (mci->bt_state == MCI_BT_SLEEP)) {
1073 ath_dbg(common, MCI,
1074 "MCI Don't send message 0x%x. BT is in sleep state\n",
1076 ar9003_mci_queue_unsent_gpm(ah, header, payload, true);
1081 REG_WRITE(ah, AR_MCI_INTERRUPT_EN, 0);
1083 /* Need to clear SW_MSG_DONE raw bit before wait */
1085 REG_WRITE(ah, AR_MCI_INTERRUPT_RAW,
1086 (AR_MCI_INTERRUPT_SW_MSG_DONE |
1087 AR_MCI_INTERRUPT_MSG_FAIL_MASK));
1090 for (i = 0; (i * 4) < len; i++)
1091 REG_WRITE(ah, (AR_MCI_TX_PAYLOAD0 + i * 4),
1095 REG_WRITE(ah, AR_MCI_COMMAND0,
1096 (SM((flag & MCI_FLAG_DISABLE_TIMESTAMP),
1097 AR_MCI_COMMAND0_DISABLE_TIMESTAMP) |
1098 SM(len, AR_MCI_COMMAND0_LEN) |
1099 SM(header, AR_MCI_COMMAND0_HEADER)));
1102 !(ar9003_mci_wait_for_interrupt(ah, AR_MCI_INTERRUPT_RAW,
1103 AR_MCI_INTERRUPT_SW_MSG_DONE, 500)))
1104 ar9003_mci_queue_unsent_gpm(ah, header, payload, true);
1106 ar9003_mci_queue_unsent_gpm(ah, header, payload, false);
1111 REG_WRITE(ah, AR_MCI_INTERRUPT_EN, saved_mci_int_en);
1115 EXPORT_SYMBOL(ar9003_mci_send_message);
1117 void ar9003_mci_init_cal_req(struct ath_hw *ah, bool *is_reusable)
1119 struct ath_common *common = ath9k_hw_common(ah);
1120 struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci;
1121 u32 pld[4] = {0, 0, 0, 0};
1123 if ((mci_hw->bt_state != MCI_BT_AWAKE) ||
1124 (mci_hw->config & ATH_MCI_CONFIG_DISABLE_MCI_CAL))
1127 MCI_GPM_SET_CAL_TYPE(pld, MCI_GPM_WLAN_CAL_REQ);
1128 pld[MCI_GPM_WLAN_CAL_W_SEQUENCE] = mci_hw->wlan_cal_seq++;
1130 ar9003_mci_send_message(ah, MCI_GPM, 0, pld, 16, true, false);
1132 if (ar9003_mci_wait_for_gpm(ah, MCI_GPM_BT_CAL_GRANT, 0, 50000)) {
1133 ath_dbg(common, MCI, "MCI BT_CAL_GRANT received\n");
1135 is_reusable = false;
1136 ath_dbg(common, MCI, "MCI BT_CAL_GRANT not received\n");
1140 void ar9003_mci_init_cal_done(struct ath_hw *ah)
1142 struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci;
1143 u32 pld[4] = {0, 0, 0, 0};
1145 if ((mci_hw->bt_state != MCI_BT_AWAKE) ||
1146 (mci_hw->config & ATH_MCI_CONFIG_DISABLE_MCI_CAL))
1149 MCI_GPM_SET_CAL_TYPE(pld, MCI_GPM_WLAN_CAL_DONE);
1150 pld[MCI_GPM_WLAN_CAL_W_SEQUENCE] = mci_hw->wlan_cal_done++;
1151 ar9003_mci_send_message(ah, MCI_GPM, 0, pld, 16, true, false);
1154 void ar9003_mci_setup(struct ath_hw *ah, u32 gpm_addr, void *gpm_buf,
1155 u16 len, u32 sched_addr)
1157 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
1159 mci->gpm_addr = gpm_addr;
1160 mci->gpm_buf = gpm_buf;
1162 mci->sched_addr = sched_addr;
1164 ar9003_mci_reset(ah, true, true, true);
1166 EXPORT_SYMBOL(ar9003_mci_setup);
1168 void ar9003_mci_cleanup(struct ath_hw *ah)
1170 /* Turn off MCI and Jupiter mode. */
1171 REG_WRITE(ah, AR_BTCOEX_CTRL, 0x00);
1172 ar9003_mci_disable_interrupt(ah);
1174 EXPORT_SYMBOL(ar9003_mci_cleanup);
1176 u32 ar9003_mci_state(struct ath_hw *ah, u32 state_type, u32 *p_data)
1178 struct ath_common *common = ath9k_hw_common(ah);
1179 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
1180 u32 value = 0, more_gpm = 0, gpm_ptr;
1183 switch (state_type) {
1184 case MCI_STATE_ENABLE:
1186 value = REG_READ(ah, AR_BTCOEX_CTRL);
1188 if ((value == 0xdeadbeef) || (value == 0xffffffff))
1191 value &= AR_BTCOEX_CTRL_MCI_MODE_EN;
1193 case MCI_STATE_INIT_GPM_OFFSET:
1194 value = MS(REG_READ(ah, AR_MCI_GPM_1), AR_MCI_GPM_WRITE_PTR);
1195 mci->gpm_idx = value;
1197 case MCI_STATE_NEXT_GPM_OFFSET:
1198 case MCI_STATE_LAST_GPM_OFFSET:
1200 * This could be useful to avoid new GPM message interrupt which
1201 * may lead to spurious interrupt after power sleep, or multiple
1202 * entry of ath_mci_intr().
1203 * Adding empty GPM check by returning HAL_MCI_GPM_INVALID can
1204 * alleviate this effect, but clearing GPM RX interrupt bit is
1205 * safe, because whether this is called from hw or driver code
1206 * there must be an interrupt bit set/triggered initially
1208 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,
1209 AR_MCI_INTERRUPT_RX_MSG_GPM);
1211 gpm_ptr = MS(REG_READ(ah, AR_MCI_GPM_1), AR_MCI_GPM_WRITE_PTR);
1215 value = mci->gpm_len - 1;
1216 else if (value >= mci->gpm_len) {
1217 if (value != 0xFFFF)
1223 if (value == 0xFFFF) {
1224 value = MCI_GPM_INVALID;
1225 more_gpm = MCI_GPM_NOMORE;
1226 } else if (state_type == MCI_STATE_NEXT_GPM_OFFSET) {
1227 if (gpm_ptr == mci->gpm_idx) {
1228 value = MCI_GPM_INVALID;
1229 more_gpm = MCI_GPM_NOMORE;
1234 /* skip reserved GPM if any */
1236 if (value != mci->gpm_idx)
1237 more_gpm = MCI_GPM_MORE;
1239 more_gpm = MCI_GPM_NOMORE;
1241 temp_index = mci->gpm_idx;
1248 if (ar9003_mci_is_gpm_valid(ah,
1254 if (more_gpm == MCI_GPM_NOMORE) {
1255 value = MCI_GPM_INVALID;
1264 if (value != MCI_GPM_INVALID)
1268 case MCI_STATE_LAST_SCHD_MSG_OFFSET:
1269 value = MS(REG_READ(ah, AR_MCI_RX_STATUS),
1270 AR_MCI_RX_LAST_SCHD_MSG_INDEX);
1271 /* Make it in bytes */
1274 case MCI_STATE_REMOTE_SLEEP:
1275 value = MS(REG_READ(ah, AR_MCI_RX_STATUS),
1276 AR_MCI_RX_REMOTE_SLEEP) ?
1277 MCI_BT_SLEEP : MCI_BT_AWAKE;
1279 case MCI_STATE_CONT_RSSI_POWER:
1280 value = MS(mci->cont_status, AR_MCI_CONT_RSSI_POWER);
1282 case MCI_STATE_CONT_PRIORITY:
1283 value = MS(mci->cont_status, AR_MCI_CONT_RRIORITY);
1285 case MCI_STATE_CONT_TXRX:
1286 value = MS(mci->cont_status, AR_MCI_CONT_TXRX);
1289 value = mci->bt_state;
1291 case MCI_STATE_SET_BT_SLEEP:
1292 mci->bt_state = MCI_BT_SLEEP;
1294 case MCI_STATE_SET_BT_AWAKE:
1295 mci->bt_state = MCI_BT_AWAKE;
1296 ar9003_mci_send_coex_version_query(ah, true);
1297 ar9003_mci_send_coex_wlan_channels(ah, true);
1299 if (mci->unhalt_bt_gpm)
1300 ar9003_mci_send_coex_halt_bt_gpm(ah, false, true);
1302 ar9003_mci_2g5g_switch(ah, true);
1304 case MCI_STATE_SET_BT_CAL_START:
1305 mci->bt_state = MCI_BT_CAL_START;
1307 case MCI_STATE_SET_BT_CAL:
1308 mci->bt_state = MCI_BT_CAL;
1310 case MCI_STATE_RESET_REQ_WAKE:
1311 ar9003_mci_reset_req_wakeup(ah);
1312 mci->update_2g5g = true;
1314 if (mci->config & ATH_MCI_CONFIG_MCI_OBS_MASK) {
1315 /* Check if we still have control of the GPIOs */
1316 if ((REG_READ(ah, AR_GLB_GPIO_CONTROL) &
1317 ATH_MCI_CONFIG_MCI_OBS_GPIO) !=
1318 ATH_MCI_CONFIG_MCI_OBS_GPIO) {
1319 ar9003_mci_observation_set_up(ah);
1323 case MCI_STATE_SEND_WLAN_COEX_VERSION:
1324 ar9003_mci_send_coex_version_response(ah, true);
1326 case MCI_STATE_SET_BT_COEX_VERSION:
1328 ath_dbg(common, MCI,
1329 "MCI Set BT Coex version with NULL data!!\n");
1331 mci->bt_ver_major = (*p_data >> 8) & 0xff;
1332 mci->bt_ver_minor = (*p_data) & 0xff;
1333 mci->bt_version_known = true;
1334 ath_dbg(common, MCI, "MCI BT version set: %d.%d\n",
1335 mci->bt_ver_major, mci->bt_ver_minor);
1338 case MCI_STATE_SEND_WLAN_CHANNELS:
1340 if (((mci->wlan_channels[1] & 0xffff0000) ==
1341 (*(p_data + 1) & 0xffff0000)) &&
1342 (mci->wlan_channels[2] == *(p_data + 2)) &&
1343 (mci->wlan_channels[3] == *(p_data + 3)))
1346 mci->wlan_channels[0] = *p_data++;
1347 mci->wlan_channels[1] = *p_data++;
1348 mci->wlan_channels[2] = *p_data++;
1349 mci->wlan_channels[3] = *p_data++;
1351 mci->wlan_channels_update = true;
1352 ar9003_mci_send_coex_wlan_channels(ah, true);
1354 case MCI_STATE_SEND_VERSION_QUERY:
1355 ar9003_mci_send_coex_version_query(ah, true);
1357 case MCI_STATE_SEND_STATUS_QUERY:
1358 query_type = MCI_GPM_COEX_QUERY_BT_TOPOLOGY;
1359 ar9003_mci_send_coex_bt_status_query(ah, true, query_type);
1361 case MCI_STATE_NEED_FLUSH_BT_INFO:
1363 * btcoex_hw.mci.unhalt_bt_gpm means whether it's
1364 * needed to send UNHALT message. It's set whenever
1365 * there's a request to send HALT message.
1366 * mci_halted_bt_gpm means whether HALT message is sent
1369 * Checking (mci_unhalt_bt_gpm == false) instead of
1370 * checking (ah->mci_halted_bt_gpm == false) will make
1371 * sure currently is in UNHALT-ed mode and BT can
1372 * respond to status query.
1374 value = (!mci->unhalt_bt_gpm &&
1375 mci->need_flush_btinfo) ? 1 : 0;
1377 mci->need_flush_btinfo =
1378 (*p_data != 0) ? true : false;
1380 case MCI_STATE_RECOVER_RX:
1381 ar9003_mci_prep_interface(ah);
1382 mci->query_bt = true;
1383 mci->need_flush_btinfo = true;
1384 ar9003_mci_send_coex_wlan_channels(ah, true);
1385 ar9003_mci_2g5g_switch(ah, true);
1387 case MCI_STATE_NEED_FTP_STOMP:
1388 value = !(mci->config & ATH_MCI_CONFIG_DISABLE_FTP_STOMP);
1390 case MCI_STATE_NEED_TUNING:
1391 value = !(mci->config & ATH_MCI_CONFIG_DISABLE_TUNING);
1399 EXPORT_SYMBOL(ar9003_mci_state);