2 * Copyright (c) 2010-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #ifndef AR9003_EEPROM_H
18 #define AR9003_EEPROM_H
20 #include <linux/types.h>
22 #define AR9300_EEP_VER 0xD000
23 #define AR9300_EEP_VER_MINOR_MASK 0xFFF
24 #define AR9300_EEP_MINOR_VER_1 0x1
25 #define AR9300_EEP_MINOR_VER AR9300_EEP_MINOR_VER_1
27 /* 16-bit offset location start of calibration struct */
28 #define AR9300_EEP_START_LOC 256
29 #define AR9300_NUM_5G_CAL_PIERS 8
30 #define AR9300_NUM_2G_CAL_PIERS 3
31 #define AR9300_NUM_5G_20_TARGET_POWERS 8
32 #define AR9300_NUM_5G_40_TARGET_POWERS 8
33 #define AR9300_NUM_2G_CCK_TARGET_POWERS 2
34 #define AR9300_NUM_2G_20_TARGET_POWERS 3
35 #define AR9300_NUM_2G_40_TARGET_POWERS 3
36 /* #define AR9300_NUM_CTLS 21 */
37 #define AR9300_NUM_CTLS_5G 9
38 #define AR9300_NUM_CTLS_2G 12
39 #define AR9300_NUM_BAND_EDGES_5G 8
40 #define AR9300_NUM_BAND_EDGES_2G 4
41 #define AR9300_EEPMISC_BIG_ENDIAN 0x01
42 #define AR9300_EEPMISC_WOW 0x02
43 #define AR9300_CUSTOMER_DATA_SIZE 20
45 #define AR9300_MAX_CHAINS 3
46 #define AR9300_ANT_16S 25
47 #define AR9300_FUTURE_MODAL_SZ 6
49 #define AR9300_PAPRD_RATE_MASK 0x01ffffff
50 #define AR9300_PAPRD_SCALE_1 0x0e000000
51 #define AR9300_PAPRD_SCALE_1_S 25
52 #define AR9300_PAPRD_SCALE_2 0x70000000
53 #define AR9300_PAPRD_SCALE_2_S 28
55 /* Delta from which to start power to pdadc table */
56 /* This offset is used in both open loop and closed loop power control
57 * schemes. In open loop power control, it is not really needed, but for
58 * the "sake of consistency" it was kept. For certain AP designs, this
59 * value is overwritten by the value in the flag "pwrTableOffset" just
60 * before writing the pdadc vs pwr into the chip registers.
62 #define AR9300_PWR_TABLE_OFFSET 0
64 /* byte addressable */
65 #define AR9300_EEPROM_SIZE (16*1024)
67 #define AR9300_BASE_ADDR_4K 0xfff
68 #define AR9300_BASE_ADDR 0x3ff
69 #define AR9300_BASE_ADDR_512 0x1ff
71 #define AR9300_OTP_BASE \
72 ((AR_SREV_9340(ah) || AR_SREV_9550(ah)) ? 0x30000 : 0x14000)
73 #define AR9300_OTP_STATUS \
74 ((AR_SREV_9340(ah) || AR_SREV_9550(ah)) ? 0x30018 : 0x15f18)
75 #define AR9300_OTP_STATUS_TYPE 0x7
76 #define AR9300_OTP_STATUS_VALID 0x4
77 #define AR9300_OTP_STATUS_ACCESS_BUSY 0x2
78 #define AR9300_OTP_STATUS_SM_BUSY 0x1
79 #define AR9300_OTP_READ_DATA \
80 ((AR_SREV_9340(ah) || AR_SREV_9550(ah)) ? 0x3001c : 0x15f1c)
82 enum targetPowerHTRates {
83 HT_TARGET_RATE_0_8_16,
84 HT_TARGET_RATE_1_3_9_11_17_19,
99 enum targetPowerLegacyRates {
100 LEGACY_TARGET_RATE_6_24,
101 LEGACY_TARGET_RATE_36,
102 LEGACY_TARGET_RATE_48,
103 LEGACY_TARGET_RATE_54
106 enum targetPowerCckRates {
107 LEGACY_TARGET_RATE_1L_5L,
108 LEGACY_TARGET_RATE_5S,
109 LEGACY_TARGET_RATE_11L,
110 LEGACY_TARGET_RATE_11S
114 ALL_TARGET_LEGACY_6_24,
115 ALL_TARGET_LEGACY_36,
116 ALL_TARGET_LEGACY_48,
117 ALL_TARGET_LEGACY_54,
118 ALL_TARGET_LEGACY_1L_5L,
119 ALL_TARGET_LEGACY_5S,
120 ALL_TARGET_LEGACY_11L,
121 ALL_TARGET_LEGACY_11S,
122 ALL_TARGET_HT20_0_8_16,
123 ALL_TARGET_HT20_1_3_9_11_17_19,
136 ALL_TARGET_HT40_0_8_16,
137 ALL_TARGET_HT40_1_3_9_11_17_19,
159 enum CompressAlgorithm {
170 struct ar9300_base_eep_hdr {
172 /* 4 bits tx and 4 bits rx */
174 struct eepFlags opCapFlags;
178 /* takes lower byte in eeprom location */
180 /* offset in dB to be added to beginning
181 * of pdadc table in calibration
183 int8_t pwrTableOffset;
184 u8 params_for_tuning_caps[2];
186 * bit0 - enable tx temp comp
187 * bit1 - enable tx volt comp
188 * bit2 - enable fastClock - default to 1
189 * bit3 - enable doubling - default to 1
190 * bit4 - enable internal regulator - default to 1
193 /* misc flags: bit0 - turn down drivestrength */
194 u8 miscConfiguration;
195 u8 eepromWriteEnableGpio;
200 /* SW controlled internal regulator fields */
204 struct ar9300_modal_eep_header {
205 /* 4 idle, t1, t2, b (4 bits per setting) */
206 __le32 antCtrlCommon;
207 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
208 __le32 antCtrlCommon2;
209 /* 6 idle, t, r, rx1, rx12, b (2 bits each) */
210 __le16 antCtrlChain[AR9300_MAX_CHAINS];
211 /* 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
212 u8 xatten1DB[AR9300_MAX_CHAINS];
213 /* 3 xatten1_margin for merlin (0xa20c/b20c 16:12 */
214 u8 xatten1Margin[AR9300_MAX_CHAINS];
217 /* spur channels in usual fbin coding format */
218 u8 spurChans[AR_EEPROM_MODAL_SPURS];
219 /* 3 Check if the register is per chain */
220 int8_t noiseFloorThreshCh[AR9300_MAX_CHAINS];
224 u8 txFrameToDataStart;
229 int8_t adcDesiredSize;
234 __le32 papdRateMaskHt20;
235 __le32 papdRateMaskHt40;
236 __le16 switchcomspdt;
237 u8 xlna_bias_strength;
241 struct ar9300_cal_data_per_freq_op_loop {
243 /* pdadc voltage at power measurement */
245 /* pcdac used for power measurement */
247 /* range is -60 to -127 create a mapping equation 1db resolution */
248 int8_t rxNoisefloorCal;
249 /*range is same as noisefloor */
250 int8_t rxNoisefloorPower;
251 /* temp measured when noisefloor cal was performed */
255 struct cal_tgt_pow_legacy {
259 struct cal_tgt_pow_ht {
263 struct cal_ctl_data_2g {
264 u8 ctlEdges[AR9300_NUM_BAND_EDGES_2G];
267 struct cal_ctl_data_5g {
268 u8 ctlEdges[AR9300_NUM_BAND_EDGES_5G];
271 struct ar9300_BaseExtension_1 {
274 u8 tempslopextension[8];
275 int8_t quick_drop_low;
276 int8_t quick_drop_high;
279 struct ar9300_BaseExtension_2 {
281 int8_t tempSlopeHigh;
282 u8 xatten1DBLow[AR9300_MAX_CHAINS];
283 u8 xatten1MarginLow[AR9300_MAX_CHAINS];
284 u8 xatten1DBHigh[AR9300_MAX_CHAINS];
285 u8 xatten1MarginHigh[AR9300_MAX_CHAINS];
288 struct ar9300_eeprom {
292 u8 custData[AR9300_CUSTOMER_DATA_SIZE];
294 struct ar9300_base_eep_hdr baseEepHeader;
296 struct ar9300_modal_eep_header modalHeader2G;
297 struct ar9300_BaseExtension_1 base_ext1;
298 u8 calFreqPier2G[AR9300_NUM_2G_CAL_PIERS];
299 struct ar9300_cal_data_per_freq_op_loop
300 calPierData2G[AR9300_MAX_CHAINS][AR9300_NUM_2G_CAL_PIERS];
301 u8 calTarget_freqbin_Cck[AR9300_NUM_2G_CCK_TARGET_POWERS];
302 u8 calTarget_freqbin_2G[AR9300_NUM_2G_20_TARGET_POWERS];
303 u8 calTarget_freqbin_2GHT20[AR9300_NUM_2G_20_TARGET_POWERS];
304 u8 calTarget_freqbin_2GHT40[AR9300_NUM_2G_40_TARGET_POWERS];
305 struct cal_tgt_pow_legacy
306 calTargetPowerCck[AR9300_NUM_2G_CCK_TARGET_POWERS];
307 struct cal_tgt_pow_legacy
308 calTargetPower2G[AR9300_NUM_2G_20_TARGET_POWERS];
309 struct cal_tgt_pow_ht
310 calTargetPower2GHT20[AR9300_NUM_2G_20_TARGET_POWERS];
311 struct cal_tgt_pow_ht
312 calTargetPower2GHT40[AR9300_NUM_2G_40_TARGET_POWERS];
313 u8 ctlIndex_2G[AR9300_NUM_CTLS_2G];
314 u8 ctl_freqbin_2G[AR9300_NUM_CTLS_2G][AR9300_NUM_BAND_EDGES_2G];
315 struct cal_ctl_data_2g ctlPowerData_2G[AR9300_NUM_CTLS_2G];
316 struct ar9300_modal_eep_header modalHeader5G;
317 struct ar9300_BaseExtension_2 base_ext2;
318 u8 calFreqPier5G[AR9300_NUM_5G_CAL_PIERS];
319 struct ar9300_cal_data_per_freq_op_loop
320 calPierData5G[AR9300_MAX_CHAINS][AR9300_NUM_5G_CAL_PIERS];
321 u8 calTarget_freqbin_5G[AR9300_NUM_5G_20_TARGET_POWERS];
322 u8 calTarget_freqbin_5GHT20[AR9300_NUM_5G_20_TARGET_POWERS];
323 u8 calTarget_freqbin_5GHT40[AR9300_NUM_5G_40_TARGET_POWERS];
324 struct cal_tgt_pow_legacy
325 calTargetPower5G[AR9300_NUM_5G_20_TARGET_POWERS];
326 struct cal_tgt_pow_ht
327 calTargetPower5GHT20[AR9300_NUM_5G_20_TARGET_POWERS];
328 struct cal_tgt_pow_ht
329 calTargetPower5GHT40[AR9300_NUM_5G_40_TARGET_POWERS];
330 u8 ctlIndex_5G[AR9300_NUM_CTLS_5G];
331 u8 ctl_freqbin_5G[AR9300_NUM_CTLS_5G][AR9300_NUM_BAND_EDGES_5G];
332 struct cal_ctl_data_5g ctlPowerData_5G[AR9300_NUM_CTLS_5G];
335 s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah);
336 s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah);
337 u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz);
338 u32 ar9003_hw_ant_ctrl_common_2_get(struct ath_hw *ah, bool is2ghz);
340 u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is_2ghz);
342 unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah,
343 struct ath9k_channel *chan);
345 void ar9003_hw_internal_regulator_apply(struct ath_hw *ah);