2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/kernel.h>
18 #include <linux/export.h>
22 struct ani_ofdm_level_entry {
23 int spur_immunity_level;
25 int ofdm_weak_signal_on;
28 /* values here are relative to the INI */
35 * WS: OFDM / CCK Weak Signal detection
36 * MRC-CCK: Maximal Ratio Combining for CCK
39 static const struct ani_ofdm_level_entry ofdm_level_table[] = {
41 { 0, 0, 1 }, /* lvl 0 */
42 { 1, 1, 1 }, /* lvl 1 */
43 { 2, 2, 1 }, /* lvl 2 */
44 { 3, 2, 1 }, /* lvl 3 (default) */
45 { 4, 3, 1 }, /* lvl 4 */
46 { 5, 4, 1 }, /* lvl 5 */
47 { 6, 5, 1 }, /* lvl 6 */
48 { 7, 6, 1 }, /* lvl 7 */
49 { 7, 6, 0 }, /* lvl 8 */
50 { 7, 7, 0 } /* lvl 9 */
52 #define ATH9K_ANI_OFDM_NUM_LEVEL \
53 ARRAY_SIZE(ofdm_level_table)
54 #define ATH9K_ANI_OFDM_MAX_LEVEL \
55 (ATH9K_ANI_OFDM_NUM_LEVEL-1)
56 #define ATH9K_ANI_OFDM_DEF_LEVEL \
57 3 /* default level - matches the INI settings */
60 * MRC (Maximal Ratio Combining) has always been used with multi-antenna ofdm.
61 * With OFDM for single stream you just add up all antenna inputs, you're
62 * only interested in what you get after FFT. Signal aligment is also not
63 * required for OFDM because any phase difference adds up in the frequency
66 * MRC requires extra work for use with CCK. You need to align the antenna
67 * signals from the different antenna before you can add the signals together.
68 * You need aligment of signals as CCK is in time domain, so addition can cancel
69 * your signal completely if phase is 180 degrees (think of adding sine waves).
70 * You also need to remove noise before the addition and this is where ANI
71 * MRC CCK comes into play. One of the antenna inputs may be stronger but
72 * lower SNR, so just adding after alignment can be dangerous.
74 * Regardless of alignment in time, the antenna signals add constructively after
75 * FFT and improve your reception. For more information:
77 * http://en.wikipedia.org/wiki/Maximal-ratio_combining
80 struct ani_cck_level_entry {
85 static const struct ani_cck_level_entry cck_level_table[] = {
89 { 2, 1 }, /* lvl 2 (default) */
94 { 6, 0 }, /* lvl 7 (only for high rssi) */
95 { 7, 0 } /* lvl 8 (only for high rssi) */
98 #define ATH9K_ANI_CCK_NUM_LEVEL \
99 ARRAY_SIZE(cck_level_table)
100 #define ATH9K_ANI_CCK_MAX_LEVEL \
101 (ATH9K_ANI_CCK_NUM_LEVEL-1)
102 #define ATH9K_ANI_CCK_MAX_LEVEL_LOW_RSSI \
103 (ATH9K_ANI_CCK_NUM_LEVEL-3)
104 #define ATH9K_ANI_CCK_DEF_LEVEL \
105 2 /* default level - matches the INI settings */
107 static void ath9k_hw_update_mibstats(struct ath_hw *ah,
108 struct ath9k_mib_stats *stats)
110 stats->ackrcv_bad += REG_READ(ah, AR_ACK_FAIL);
111 stats->rts_bad += REG_READ(ah, AR_RTS_FAIL);
112 stats->fcs_bad += REG_READ(ah, AR_FCS_FAIL);
113 stats->rts_good += REG_READ(ah, AR_RTS_OK);
114 stats->beacons += REG_READ(ah, AR_BEACON_CNT);
117 static void ath9k_ani_restart(struct ath_hw *ah)
119 struct ar5416AniState *aniState;
124 aniState = &ah->curchan->ani;
125 aniState->listenTime = 0;
127 ENABLE_REGWRITE_BUFFER(ah);
129 REG_WRITE(ah, AR_PHY_ERR_1, 0);
130 REG_WRITE(ah, AR_PHY_ERR_2, 0);
131 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
132 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
134 REGWRITE_BUFFER_FLUSH(ah);
136 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
138 aniState->ofdmPhyErrCount = 0;
139 aniState->cckPhyErrCount = 0;
142 /* Adjust the OFDM Noise Immunity Level */
143 static void ath9k_hw_set_ofdm_nil(struct ath_hw *ah, u8 immunityLevel)
145 struct ar5416AniState *aniState = &ah->curchan->ani;
146 struct ath_common *common = ath9k_hw_common(ah);
147 const struct ani_ofdm_level_entry *entry_ofdm;
148 const struct ani_cck_level_entry *entry_cck;
151 ath_dbg(common, ANI, "**** ofdmlevel %d=>%d, rssi=%d[lo=%d hi=%d]\n",
152 aniState->ofdmNoiseImmunityLevel,
153 immunityLevel, BEACON_RSSI(ah),
154 aniState->rssiThrLow, aniState->rssiThrHigh);
156 if (aniState->update_ani)
157 aniState->ofdmNoiseImmunityLevel = immunityLevel;
159 entry_ofdm = &ofdm_level_table[aniState->ofdmNoiseImmunityLevel];
160 entry_cck = &cck_level_table[aniState->cckNoiseImmunityLevel];
162 if (aniState->spurImmunityLevel != entry_ofdm->spur_immunity_level)
163 ath9k_hw_ani_control(ah,
164 ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
165 entry_ofdm->spur_immunity_level);
167 if (aniState->firstepLevel != entry_ofdm->fir_step_level &&
168 entry_ofdm->fir_step_level >= entry_cck->fir_step_level)
169 ath9k_hw_ani_control(ah,
170 ATH9K_ANI_FIRSTEP_LEVEL,
171 entry_ofdm->fir_step_level);
173 weak_sig = entry_ofdm->ofdm_weak_signal_on;
174 if (ah->opmode == NL80211_IFTYPE_STATION &&
175 BEACON_RSSI(ah) <= aniState->rssiThrHigh)
178 if (aniState->ofdmWeakSigDetect != weak_sig)
179 ath9k_hw_ani_control(ah,
180 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
181 entry_ofdm->ofdm_weak_signal_on);
183 if (aniState->ofdmNoiseImmunityLevel >= ATH9K_ANI_OFDM_DEF_LEVEL) {
184 ah->config.ofdm_trig_high = ATH9K_ANI_OFDM_TRIG_HIGH;
185 ah->config.ofdm_trig_low = ATH9K_ANI_OFDM_TRIG_LOW_ABOVE_INI;
187 ah->config.ofdm_trig_high = ATH9K_ANI_OFDM_TRIG_HIGH_BELOW_INI;
188 ah->config.ofdm_trig_low = ATH9K_ANI_OFDM_TRIG_LOW;
192 static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hw *ah)
194 struct ar5416AniState *aniState;
199 aniState = &ah->curchan->ani;
201 if (aniState->ofdmNoiseImmunityLevel < ATH9K_ANI_OFDM_MAX_LEVEL)
202 ath9k_hw_set_ofdm_nil(ah, aniState->ofdmNoiseImmunityLevel + 1);
206 * Set the ANI settings to match an CCK level.
208 static void ath9k_hw_set_cck_nil(struct ath_hw *ah, u_int8_t immunityLevel)
210 struct ar5416AniState *aniState = &ah->curchan->ani;
211 struct ath_common *common = ath9k_hw_common(ah);
212 const struct ani_ofdm_level_entry *entry_ofdm;
213 const struct ani_cck_level_entry *entry_cck;
215 ath_dbg(common, ANI, "**** ccklevel %d=>%d, rssi=%d[lo=%d hi=%d]\n",
216 aniState->cckNoiseImmunityLevel, immunityLevel,
217 BEACON_RSSI(ah), aniState->rssiThrLow,
218 aniState->rssiThrHigh);
220 if (ah->opmode == NL80211_IFTYPE_STATION &&
221 BEACON_RSSI(ah) <= aniState->rssiThrLow &&
222 immunityLevel > ATH9K_ANI_CCK_MAX_LEVEL_LOW_RSSI)
223 immunityLevel = ATH9K_ANI_CCK_MAX_LEVEL_LOW_RSSI;
225 if (aniState->update_ani)
226 aniState->cckNoiseImmunityLevel = immunityLevel;
228 entry_ofdm = &ofdm_level_table[aniState->ofdmNoiseImmunityLevel];
229 entry_cck = &cck_level_table[aniState->cckNoiseImmunityLevel];
231 if (aniState->firstepLevel != entry_cck->fir_step_level &&
232 entry_cck->fir_step_level >= entry_ofdm->fir_step_level)
233 ath9k_hw_ani_control(ah,
234 ATH9K_ANI_FIRSTEP_LEVEL,
235 entry_cck->fir_step_level);
237 /* Skip MRC CCK for pre AR9003 families */
238 if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9485(ah))
241 if (aniState->mrcCCKOff == entry_cck->mrc_cck_on)
242 ath9k_hw_ani_control(ah,
244 entry_cck->mrc_cck_on);
247 static void ath9k_hw_ani_cck_err_trigger(struct ath_hw *ah)
249 struct ar5416AniState *aniState;
254 aniState = &ah->curchan->ani;
256 if (aniState->cckNoiseImmunityLevel < ATH9K_ANI_CCK_MAX_LEVEL)
257 ath9k_hw_set_cck_nil(ah, aniState->cckNoiseImmunityLevel + 1);
261 * only lower either OFDM or CCK errors per turn
262 * we lower the other one next time
264 static void ath9k_hw_ani_lower_immunity(struct ath_hw *ah)
266 struct ar5416AniState *aniState;
268 aniState = &ah->curchan->ani;
270 /* lower OFDM noise immunity */
271 if (aniState->ofdmNoiseImmunityLevel > 0 &&
272 (aniState->ofdmsTurn || aniState->cckNoiseImmunityLevel == 0)) {
273 ath9k_hw_set_ofdm_nil(ah, aniState->ofdmNoiseImmunityLevel - 1);
277 /* lower CCK noise immunity */
278 if (aniState->cckNoiseImmunityLevel > 0)
279 ath9k_hw_set_cck_nil(ah, aniState->cckNoiseImmunityLevel - 1);
283 * Restore the ANI parameters in the HAL and reset the statistics.
284 * This routine should be called for every hardware reset and for
285 * every channel change.
287 void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning)
289 struct ar5416AniState *aniState = &ah->curchan->ani;
290 struct ath9k_channel *chan = ah->curchan;
291 struct ath_common *common = ath9k_hw_common(ah);
292 int ofdm_nil, cck_nil;
297 BUG_ON(aniState == NULL);
298 ah->stats.ast_ani_reset++;
300 /* only allow a subset of functions in AP mode */
301 if (ah->opmode == NL80211_IFTYPE_AP) {
302 if (IS_CHAN_2GHZ(chan)) {
303 ah->ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL |
304 ATH9K_ANI_FIRSTEP_LEVEL);
305 if (AR_SREV_9300_20_OR_LATER(ah))
306 ah->ani_function |= ATH9K_ANI_MRC_CCK;
308 ah->ani_function = 0;
311 /* always allow mode (on/off) to be controlled */
312 ah->ani_function |= ATH9K_ANI_MODE;
314 ofdm_nil = max_t(int, ATH9K_ANI_OFDM_DEF_LEVEL,
315 aniState->ofdmNoiseImmunityLevel);
316 cck_nil = max_t(int, ATH9K_ANI_CCK_DEF_LEVEL,
317 aniState->cckNoiseImmunityLevel);
320 (ah->opmode != NL80211_IFTYPE_STATION &&
321 ah->opmode != NL80211_IFTYPE_ADHOC)) {
323 * If we're scanning or in AP mode, the defaults (ini)
324 * should be in place. For an AP we assume the historical
325 * levels for this channel are probably outdated so start
326 * from defaults instead.
328 if (aniState->ofdmNoiseImmunityLevel !=
329 ATH9K_ANI_OFDM_DEF_LEVEL ||
330 aniState->cckNoiseImmunityLevel !=
331 ATH9K_ANI_CCK_DEF_LEVEL) {
333 "Restore defaults: opmode %u chan %d Mhz/0x%x is_scanning=%d ofdm:%d cck:%d\n",
338 aniState->ofdmNoiseImmunityLevel,
339 aniState->cckNoiseImmunityLevel);
341 aniState->update_ani = false;
342 ofdm_nil = ATH9K_ANI_OFDM_DEF_LEVEL;
343 cck_nil = ATH9K_ANI_CCK_DEF_LEVEL;
347 * restore historical levels for this channel
350 "Restore history: opmode %u chan %d Mhz/0x%x is_scanning=%d ofdm:%d cck:%d\n",
355 aniState->ofdmNoiseImmunityLevel,
356 aniState->cckNoiseImmunityLevel);
358 aniState->update_ani = true;
360 ath9k_hw_set_ofdm_nil(ah, ofdm_nil);
361 ath9k_hw_set_cck_nil(ah, cck_nil);
364 * enable phy counters if hw supports or if not, enable phy
365 * interrupts (so we can count each one)
367 ath9k_ani_restart(ah);
369 ENABLE_REGWRITE_BUFFER(ah);
371 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
372 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
374 REGWRITE_BUFFER_FLUSH(ah);
377 static bool ath9k_hw_ani_read_counters(struct ath_hw *ah)
379 struct ath_common *common = ath9k_hw_common(ah);
380 struct ar5416AniState *aniState = &ah->curchan->ani;
381 u32 phyCnt1, phyCnt2;
384 ath_hw_cycle_counters_update(common);
385 listenTime = ath_hw_get_listen_time(common);
387 if (listenTime <= 0) {
388 ah->stats.ast_ani_lneg_or_lzero++;
389 ath9k_ani_restart(ah);
393 aniState->listenTime += listenTime;
395 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
397 phyCnt1 = REG_READ(ah, AR_PHY_ERR_1);
398 phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);
400 ah->stats.ast_ani_ofdmerrs += phyCnt1 - aniState->ofdmPhyErrCount;
401 aniState->ofdmPhyErrCount = phyCnt1;
403 ah->stats.ast_ani_cckerrs += phyCnt2 - aniState->cckPhyErrCount;
404 aniState->cckPhyErrCount = phyCnt2;
409 void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan)
411 struct ar5416AniState *aniState;
412 struct ath_common *common = ath9k_hw_common(ah);
413 u32 ofdmPhyErrRate, cckPhyErrRate;
418 aniState = &ah->curchan->ani;
419 if (WARN_ON(!aniState))
422 if (!ath9k_hw_ani_read_counters(ah))
425 ofdmPhyErrRate = aniState->ofdmPhyErrCount * 1000 /
426 aniState->listenTime;
427 cckPhyErrRate = aniState->cckPhyErrCount * 1000 /
428 aniState->listenTime;
431 "listenTime=%d OFDM:%d errs=%d/s CCK:%d errs=%d/s ofdm_turn=%d\n",
432 aniState->listenTime,
433 aniState->ofdmNoiseImmunityLevel,
434 ofdmPhyErrRate, aniState->cckNoiseImmunityLevel,
435 cckPhyErrRate, aniState->ofdmsTurn);
437 if (aniState->listenTime > ah->aniperiod) {
438 if (cckPhyErrRate < ah->config.cck_trig_low &&
439 ofdmPhyErrRate < ah->config.ofdm_trig_low) {
440 ath9k_hw_ani_lower_immunity(ah);
441 aniState->ofdmsTurn = !aniState->ofdmsTurn;
442 } else if (ofdmPhyErrRate > ah->config.ofdm_trig_high) {
443 ath9k_hw_ani_ofdm_err_trigger(ah);
444 aniState->ofdmsTurn = false;
445 } else if (cckPhyErrRate > ah->config.cck_trig_high) {
446 ath9k_hw_ani_cck_err_trigger(ah);
447 aniState->ofdmsTurn = true;
449 ath9k_ani_restart(ah);
452 EXPORT_SYMBOL(ath9k_hw_ani_monitor);
454 void ath9k_enable_mib_counters(struct ath_hw *ah)
456 struct ath_common *common = ath9k_hw_common(ah);
458 ath_dbg(common, ANI, "Enable MIB counters\n");
460 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
462 ENABLE_REGWRITE_BUFFER(ah);
464 REG_WRITE(ah, AR_FILT_OFDM, 0);
465 REG_WRITE(ah, AR_FILT_CCK, 0);
466 REG_WRITE(ah, AR_MIBC,
467 ~(AR_MIBC_COW | AR_MIBC_FMC | AR_MIBC_CMC | AR_MIBC_MCS)
469 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
470 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
472 REGWRITE_BUFFER_FLUSH(ah);
475 /* Freeze the MIB counters, get the stats and then clear them */
476 void ath9k_hw_disable_mib_counters(struct ath_hw *ah)
478 struct ath_common *common = ath9k_hw_common(ah);
480 ath_dbg(common, ANI, "Disable MIB counters\n");
482 REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC);
483 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
484 REG_WRITE(ah, AR_MIBC, AR_MIBC_CMC);
485 REG_WRITE(ah, AR_FILT_OFDM, 0);
486 REG_WRITE(ah, AR_FILT_CCK, 0);
488 EXPORT_SYMBOL(ath9k_hw_disable_mib_counters);
490 void ath9k_hw_ani_setup(struct ath_hw *ah)
494 static const int totalSizeDesired[] = { -55, -55, -55, -55, -62 };
495 static const int coarseHigh[] = { -14, -14, -14, -14, -12 };
496 static const int coarseLow[] = { -64, -64, -64, -64, -70 };
497 static const int firpwr[] = { -78, -78, -78, -78, -80 };
499 for (i = 0; i < 5; i++) {
500 ah->totalSizeDesired[i] = totalSizeDesired[i];
501 ah->coarse_high[i] = coarseHigh[i];
502 ah->coarse_low[i] = coarseLow[i];
503 ah->firpwr[i] = firpwr[i];
507 void ath9k_hw_ani_init(struct ath_hw *ah)
509 struct ath_common *common = ath9k_hw_common(ah);
512 ath_dbg(common, ANI, "Initialize ANI\n");
514 ah->config.ofdm_trig_high = ATH9K_ANI_OFDM_TRIG_HIGH;
515 ah->config.ofdm_trig_low = ATH9K_ANI_OFDM_TRIG_LOW;
517 ah->config.cck_trig_high = ATH9K_ANI_CCK_TRIG_HIGH;
518 ah->config.cck_trig_low = ATH9K_ANI_CCK_TRIG_LOW;
520 for (i = 0; i < ARRAY_SIZE(ah->channels); i++) {
521 struct ath9k_channel *chan = &ah->channels[i];
522 struct ar5416AniState *ani = &chan->ani;
524 ani->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL;
526 ani->firstepLevel = ATH9K_ANI_FIRSTEP_LVL;
528 if (AR_SREV_9300_20_OR_LATER(ah))
530 !ATH9K_ANI_ENABLE_MRC_CCK;
532 ani->mrcCCKOff = true;
534 ani->ofdmsTurn = true;
536 ani->rssiThrHigh = ATH9K_ANI_RSSI_THR_HIGH;
537 ani->rssiThrLow = ATH9K_ANI_RSSI_THR_LOW;
538 ani->ofdmWeakSigDetect = ATH9K_ANI_USE_OFDM_WEAK_SIG;
539 ani->cckNoiseImmunityLevel = ATH9K_ANI_CCK_DEF_LEVEL;
540 ani->ofdmNoiseImmunityLevel = ATH9K_ANI_OFDM_DEF_LEVEL;
541 ani->update_ani = false;
545 * since we expect some ongoing maintenance on the tables, let's sanity
546 * check here default level should not modify INI setting.
548 ah->aniperiod = ATH9K_ANI_PERIOD;
549 ah->config.ani_poll_interval = ATH9K_ANI_POLLINTERVAL;
551 if (ah->config.enable_ani)
552 ah->proc_phyerr |= HAL_PROCESS_ANI;
554 ath9k_ani_restart(ah);
555 ath9k_enable_mib_counters(ah);