drivers/net/wireless/ath/ath5k/eeprom.c

   1 /*
   2  * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
   3  * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com>
   4  * Copyright (c) 2008-2009 Felix Fietkau <nbd@openwrt.org>
   5  *
   6  * Permission to use, copy, modify, and distribute this software for any
   7  * purpose with or without fee is hereby granted, provided that the above
   8  * copyright notice and this permission notice appear in all copies.
   9  *
  10  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 /*************************************\
  21 * EEPROM access functions and helpers *
  22 \*************************************/
  23
  24 #include <linux/slab.h>
  25
  26 #include "ath5k.h"
  27 #include "reg.h"
  28 #include "debug.h"
  29 #include "base.h"
  30
  31
  32 /******************\
  33 * Helper functions *
  34 \******************/
  35
  36 /*
  37  * Translate binary channel representation in EEPROM to frequency
  38  */
  39 static u16 ath5k_eeprom_bin2freq(struct ath5k_eeprom_info *ee, u16 bin,
  40                                                         unsigned int mode)
  41 {
  42         u16 val;
  43
  44         if (bin == AR5K_EEPROM_CHANNEL_DIS)
  45                 return bin;
  46
  47         if (mode == AR5K_EEPROM_MODE_11A) {
  48                 if (ee->ee_version > AR5K_EEPROM_VERSION_3_2)
  49                         val = (5 * bin) + 4800;
  50                 else
  51                         val = bin > 62 ? (10 * 62) + (5 * (bin - 62)) + 5100 :
  52                                 (bin * 10) + 5100;
  53         } else {
  54                 if (ee->ee_version > AR5K_EEPROM_VERSION_3_2)
  55                         val = bin + 2300;
  56                 else
  57                         val = bin + 2400;
  58         }
  59
  60         return val;
  61 }
  62
  63
  64 /*********\
  65 * Parsers *
  66 \*********/
  67
  68 /*
  69  * Initialize eeprom & capabilities structs
  70  */
  71 static int
  72 ath5k_eeprom_init_header(struct ath5k_hw *ah)
  73 {
  74         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
  75         u16 val;
  76         u32 cksum, offset, eep_max = AR5K_EEPROM_INFO_MAX;
  77
  78         /*
  79          * Read values from EEPROM and store them in the capability structure
  80          */
  81         AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MAGIC, ee_magic);
  82         AR5K_EEPROM_READ_HDR(AR5K_EEPROM_PROTECT, ee_protect);
  83         AR5K_EEPROM_READ_HDR(AR5K_EEPROM_REG_DOMAIN, ee_regdomain);
  84         AR5K_EEPROM_READ_HDR(AR5K_EEPROM_VERSION, ee_version);
  85         AR5K_EEPROM_READ_HDR(AR5K_EEPROM_HDR, ee_header);
  86
  87         /* Return if we have an old EEPROM */
  88         if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_0)
  89                 return 0;
  90
  91         /*
  92          * Validate the checksum of the EEPROM date. There are some
  93          * devices with invalid EEPROMs.
  94          */
  95         AR5K_EEPROM_READ(AR5K_EEPROM_SIZE_UPPER, val);
  96         if (val) {
  97                 eep_max = (val & AR5K_EEPROM_SIZE_UPPER_MASK) <<
  98                            AR5K_EEPROM_SIZE_ENDLOC_SHIFT;
  99                 AR5K_EEPROM_READ(AR5K_EEPROM_SIZE_LOWER, val);
 100                 eep_max = (eep_max | val) - AR5K_EEPROM_INFO_BASE;
 101
 102                 /*
 103                  * Fail safe check to prevent stupid loops due
 104                  * to busted EEPROMs. XXX: This value is likely too
 105                  * big still, waiting on a better value.
 106                  */
 107                 if (eep_max > (3 * AR5K_EEPROM_INFO_MAX)) {
 108                         ATH5K_ERR(ah->ah_sc, "Invalid max custom EEPROM size: "
 109                                   "%d (0x%04x) max expected: %d (0x%04x)\n",
 110                                   eep_max, eep_max,
 111                                   3 * AR5K_EEPROM_INFO_MAX,
 112                                   3 * AR5K_EEPROM_INFO_MAX);
 113                         return -EIO;
 114                 }
 115         }
 116
 117         for (cksum = 0, offset = 0; offset < eep_max; offset++) {
 118                 AR5K_EEPROM_READ(AR5K_EEPROM_INFO(offset), val);
 119                 cksum ^= val;
 120         }
 121         if (cksum != AR5K_EEPROM_INFO_CKSUM) {
 122                 ATH5K_ERR(ah->ah_sc, "Invalid EEPROM "
 123                           "checksum: 0x%04x eep_max: 0x%04x (%s)\n",
 124                           cksum, eep_max,
 125                           eep_max == AR5K_EEPROM_INFO_MAX ?
 126                                 "default size" : "custom size");
 127                 return -EIO;
 128         }
 129
 130         AR5K_EEPROM_READ_HDR(AR5K_EEPROM_ANT_GAIN(ah->ah_ee_version),
 131             ee_ant_gain);
 132
 133         if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
 134                 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC0, ee_misc0);
 135                 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC1, ee_misc1);
 136
 137                 /* XXX: Don't know which versions include these two */
 138                 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC2, ee_misc2);
 139
 140                 if (ee->ee_version >= AR5K_EEPROM_VERSION_4_3)
 141                         AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC3, ee_misc3);
 142
 143                 if (ee->ee_version >= AR5K_EEPROM_VERSION_5_0) {
 144                         AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC4, ee_misc4);
 145                         AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC5, ee_misc5);
 146                         AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC6, ee_misc6);
 147                 }
 148         }
 149
 150         if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_3) {
 151                 AR5K_EEPROM_READ(AR5K_EEPROM_OBDB0_2GHZ, val);
 152                 ee->ee_ob[AR5K_EEPROM_MODE_11B][0] = val & 0x7;
 153                 ee->ee_db[AR5K_EEPROM_MODE_11B][0] = (val >> 3) & 0x7;
 154
 155                 AR5K_EEPROM_READ(AR5K_EEPROM_OBDB1_2GHZ, val);
 156                 ee->ee_ob[AR5K_EEPROM_MODE_11G][0] = val & 0x7;
 157                 ee->ee_db[AR5K_EEPROM_MODE_11G][0] = (val >> 3) & 0x7;
 158         }
 159
 160         AR5K_EEPROM_READ(AR5K_EEPROM_IS_HB63, val);
 161
 162         if ((ah->ah_mac_version == (AR5K_SREV_AR2425 >> 4)) && val)
 163                 ee->ee_is_hb63 = true;
 164         else
 165                 ee->ee_is_hb63 = false;
 166
 167         AR5K_EEPROM_READ(AR5K_EEPROM_RFKILL, val);
 168         ee->ee_rfkill_pin = (u8) AR5K_REG_MS(val, AR5K_EEPROM_RFKILL_GPIO_SEL);
 169         ee->ee_rfkill_pol = val & AR5K_EEPROM_RFKILL_POLARITY ? true : false;
 170
 171         /* Check if PCIE_OFFSET points to PCIE_SERDES_SECTION
 172          * and enable serdes programming if needed.
 173          *
 174          * XXX: Serdes values seem to be fixed so
 175          * no need to read them here, we write them
 176          * during ath5k_hw_init */
 177         AR5K_EEPROM_READ(AR5K_EEPROM_PCIE_OFFSET, val);
 178         ee->ee_serdes = (val == AR5K_EEPROM_PCIE_SERDES_SECTION) ?
 179                                                         true : false;
 180
 181         return 0;
 182 }
 183
 184
 185 /*
 186  * Read antenna infos from eeprom
 187  */
 188 static int ath5k_eeprom_read_ants(struct ath5k_hw *ah, u32 *offset,
 189                 unsigned int mode)
 190 {
 191         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
 192         u32 o = *offset;
 193         u16 val;
 194         int i = 0;
 195
 196         AR5K_EEPROM_READ(o++, val);
 197         ee->ee_switch_settling[mode]    = (val >> 8) & 0x7f;
 198         ee->ee_atn_tx_rx[mode]          = (val >> 2) & 0x3f;
 199         ee->ee_ant_control[mode][i]     = (val << 4) & 0x3f;
 200
 201         AR5K_EEPROM_READ(o++, val);
 202         ee->ee_ant_control[mode][i++]   |= (val >> 12) & 0xf;
 203         ee->ee_ant_control[mode][i++]   = (val >> 6) & 0x3f;
 204         ee->ee_ant_control[mode][i++]   = val & 0x3f;
 205
 206         AR5K_EEPROM_READ(o++, val);
 207         ee->ee_ant_control[mode][i++]   = (val >> 10) & 0x3f;
 208         ee->ee_ant_control[mode][i++]   = (val >> 4) & 0x3f;
 209         ee->ee_ant_control[mode][i]     = (val << 2) & 0x3f;
 210
 211         AR5K_EEPROM_READ(o++, val);
 212         ee->ee_ant_control[mode][i++]   |= (val >> 14) & 0x3;
 213         ee->ee_ant_control[mode][i++]   = (val >> 8) & 0x3f;
 214         ee->ee_ant_control[mode][i++]   = (val >> 2) & 0x3f;
 215         ee->ee_ant_control[mode][i]     = (val << 4) & 0x3f;
 216
 217         AR5K_EEPROM_READ(o++, val);
 218         ee->ee_ant_control[mode][i++]   |= (val >> 12) & 0xf;
 219         ee->ee_ant_control[mode][i++]   = (val >> 6) & 0x3f;
 220         ee->ee_ant_control[mode][i++]   = val & 0x3f;
 221
 222         /* Get antenna switch tables */
 223         ah->ah_ant_ctl[mode][AR5K_ANT_CTL] =
 224             (ee->ee_ant_control[mode][0] << 4);
 225         ah->ah_ant_ctl[mode][AR5K_ANT_SWTABLE_A] =
 226              ee->ee_ant_control[mode][1]        |
 227             (ee->ee_ant_control[mode][2] << 6)  |
 228             (ee->ee_ant_control[mode][3] << 12) |
 229             (ee->ee_ant_control[mode][4] << 18) |
 230             (ee->ee_ant_control[mode][5] << 24);
 231         ah->ah_ant_ctl[mode][AR5K_ANT_SWTABLE_B] =
 232              ee->ee_ant_control[mode][6]        |
 233             (ee->ee_ant_control[mode][7] << 6)  |
 234             (ee->ee_ant_control[mode][8] << 12) |
 235             (ee->ee_ant_control[mode][9] << 18) |
 236             (ee->ee_ant_control[mode][10] << 24);
 237
 238         /* return new offset */
 239         *offset = o;
 240
 241         return 0;
 242 }
 243
 244 /*
 245  * Read supported modes and some mode-specific calibration data
 246  * from eeprom
 247  */
 248 static int ath5k_eeprom_read_modes(struct ath5k_hw *ah, u32 *offset,
 249                 unsigned int mode)
 250 {
 251         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
 252         u32 o = *offset;
 253         u16 val;
 254
 255         ee->ee_n_piers[mode] = 0;
 256         AR5K_EEPROM_READ(o++, val);
 257         ee->ee_adc_desired_size[mode]   = (s8)((val >> 8) & 0xff);
 258         switch(mode) {
 259         case AR5K_EEPROM_MODE_11A:
 260                 ee->ee_ob[mode][3]      = (val >> 5) & 0x7;
 261                 ee->ee_db[mode][3]      = (val >> 2) & 0x7;
 262                 ee->ee_ob[mode][2]      = (val << 1) & 0x7;
 263
 264                 AR5K_EEPROM_READ(o++, val);
 265                 ee->ee_ob[mode][2]      |= (val >> 15) & 0x1;
 266                 ee->ee_db[mode][2]      = (val >> 12) & 0x7;
 267                 ee->ee_ob[mode][1]      = (val >> 9) & 0x7;
 268                 ee->ee_db[mode][1]      = (val >> 6) & 0x7;
 269                 ee->ee_ob[mode][0]      = (val >> 3) & 0x7;
 270                 ee->ee_db[mode][0]      = val & 0x7;
 271                 break;
 272         case AR5K_EEPROM_MODE_11G:
 273         case AR5K_EEPROM_MODE_11B:
 274                 ee->ee_ob[mode][1]      = (val >> 4) & 0x7;
 275                 ee->ee_db[mode][1]      = val & 0x7;
 276                 break;
 277         }
 278
 279         AR5K_EEPROM_READ(o++, val);
 280         ee->ee_tx_end2xlna_enable[mode] = (val >> 8) & 0xff;
 281         ee->ee_thr_62[mode]             = val & 0xff;
 282
 283         if (ah->ah_ee_version <= AR5K_EEPROM_VERSION_3_2)
 284                 ee->ee_thr_62[mode] = mode == AR5K_EEPROM_MODE_11A ? 15 : 28;
 285
 286         AR5K_EEPROM_READ(o++, val);
 287         ee->ee_tx_end2xpa_disable[mode] = (val >> 8) & 0xff;
 288         ee->ee_tx_frm2xpa_enable[mode]  = val & 0xff;
 289
 290         AR5K_EEPROM_READ(o++, val);
 291         ee->ee_pga_desired_size[mode]   = (val >> 8) & 0xff;
 292
 293         if ((val & 0xff) & 0x80)
 294                 ee->ee_noise_floor_thr[mode] = -((((val & 0xff) ^ 0xff)) + 1);
 295         else
 296                 ee->ee_noise_floor_thr[mode] = val & 0xff;
 297
 298         if (ah->ah_ee_version <= AR5K_EEPROM_VERSION_3_2)
 299                 ee->ee_noise_floor_thr[mode] =
 300                     mode == AR5K_EEPROM_MODE_11A ? -54 : -1;
 301
 302         AR5K_EEPROM_READ(o++, val);
 303         ee->ee_xlna_gain[mode]          = (val >> 5) & 0xff;
 304         ee->ee_x_gain[mode]             = (val >> 1) & 0xf;
 305         ee->ee_xpd[mode]                = val & 0x1;
 306
 307         if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0 &&
 308             mode != AR5K_EEPROM_MODE_11B)
 309                 ee->ee_fixed_bias[mode] = (val >> 13) & 0x1;
 310
 311         if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_3_3) {
 312                 AR5K_EEPROM_READ(o++, val);
 313                 ee->ee_false_detect[mode] = (val >> 6) & 0x7f;
 314
 315                 if (mode == AR5K_EEPROM_MODE_11A)
 316                         ee->ee_xr_power[mode] = val & 0x3f;
 317                 else {
 318                         /* b_DB_11[bg] and b_OB_11[bg] */
 319                         ee->ee_ob[mode][0] = val & 0x7;
 320                         ee->ee_db[mode][0] = (val >> 3) & 0x7;
 321                 }
 322         }
 323
 324         if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_4) {
 325                 ee->ee_i_gain[mode] = AR5K_EEPROM_I_GAIN;
 326                 ee->ee_cck_ofdm_power_delta = AR5K_EEPROM_CCK_OFDM_DELTA;
 327         } else {
 328                 ee->ee_i_gain[mode] = (val >> 13) & 0x7;
 329
 330                 AR5K_EEPROM_READ(o++, val);
 331                 ee->ee_i_gain[mode] |= (val << 3) & 0x38;
 332
 333                 if (mode == AR5K_EEPROM_MODE_11G) {
 334                         ee->ee_cck_ofdm_power_delta = (val >> 3) & 0xff;
 335                         if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_6)
 336                                 ee->ee_scaled_cck_delta = (val >> 11) & 0x1f;
 337                 }
 338         }
 339
 340         if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0 &&
 341                         mode == AR5K_EEPROM_MODE_11A) {
 342                 ee->ee_i_cal[mode] = (val >> 8) & 0x3f;
 343                 ee->ee_q_cal[mode] = (val >> 3) & 0x1f;
 344         }
 345
 346         if (ah->ah_ee_version < AR5K_EEPROM_VERSION_4_0)
 347                 goto done;
 348
 349         /* Note: >= v5 have bg freq piers on another location
 350          * so these freq piers are ignored for >= v5 (should be 0xff
 351          * anyway) */
 352         switch(mode) {
 353         case AR5K_EEPROM_MODE_11A:
 354                 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_4_1)
 355                         break;
 356
 357                 AR5K_EEPROM_READ(o++, val);
 358                 ee->ee_margin_tx_rx[mode] = val & 0x3f;
 359                 break;
 360         case AR5K_EEPROM_MODE_11B:
 361                 AR5K_EEPROM_READ(o++, val);
 362
 363                 ee->ee_pwr_cal_b[0].freq =
 364                         ath5k_eeprom_bin2freq(ee, val & 0xff, mode);
 365                 if (ee->ee_pwr_cal_b[0].freq != AR5K_EEPROM_CHANNEL_DIS)
 366                         ee->ee_n_piers[mode]++;
 367
 368                 ee->ee_pwr_cal_b[1].freq =
 369                         ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff, mode);
 370                 if (ee->ee_pwr_cal_b[1].freq != AR5K_EEPROM_CHANNEL_DIS)
 371                         ee->ee_n_piers[mode]++;
 372
 373                 AR5K_EEPROM_READ(o++, val);
 374                 ee->ee_pwr_cal_b[2].freq =
 375                         ath5k_eeprom_bin2freq(ee, val & 0xff, mode);
 376                 if (ee->ee_pwr_cal_b[2].freq != AR5K_EEPROM_CHANNEL_DIS)
 377                         ee->ee_n_piers[mode]++;
 378
 379                 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
 380                         ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f;
 381                 break;
 382         case AR5K_EEPROM_MODE_11G:
 383                 AR5K_EEPROM_READ(o++, val);
 384
 385                 ee->ee_pwr_cal_g[0].freq =
 386                         ath5k_eeprom_bin2freq(ee, val & 0xff, mode);
 387                 if (ee->ee_pwr_cal_g[0].freq != AR5K_EEPROM_CHANNEL_DIS)
 388                         ee->ee_n_piers[mode]++;
 389
 390                 ee->ee_pwr_cal_g[1].freq =
 391                         ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff, mode);
 392                 if (ee->ee_pwr_cal_g[1].freq != AR5K_EEPROM_CHANNEL_DIS)
 393                         ee->ee_n_piers[mode]++;
 394
 395                 AR5K_EEPROM_READ(o++, val);
 396                 ee->ee_turbo_max_power[mode] = val & 0x7f;
 397                 ee->ee_xr_power[mode] = (val >> 7) & 0x3f;
 398
 399                 AR5K_EEPROM_READ(o++, val);
 400                 ee->ee_pwr_cal_g[2].freq =
 401                         ath5k_eeprom_bin2freq(ee, val & 0xff, mode);
 402                 if (ee->ee_pwr_cal_g[2].freq != AR5K_EEPROM_CHANNEL_DIS)
 403                         ee->ee_n_piers[mode]++;
 404
 405                 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
 406                         ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f;
 407
 408                 AR5K_EEPROM_READ(o++, val);
 409                 ee->ee_i_cal[mode] = (val >> 5) & 0x3f;
 410                 ee->ee_q_cal[mode] = val & 0x1f;
 411
 412                 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_2) {
 413                         AR5K_EEPROM_READ(o++, val);
 414                         ee->ee_cck_ofdm_gain_delta = val & 0xff;
 415                 }
 416                 break;
 417         }
 418
 419         /*
 420          * Read turbo mode information on newer EEPROM versions
 421          */
 422         if (ee->ee_version < AR5K_EEPROM_VERSION_5_0)
 423                 goto done;
 424
 425         switch (mode){
 426         case AR5K_EEPROM_MODE_11A:
 427                 ee->ee_switch_settling_turbo[mode] = (val >> 6) & 0x7f;
 428
 429                 ee->ee_atn_tx_rx_turbo[mode] = (val >> 13) & 0x7;
 430                 AR5K_EEPROM_READ(o++, val);
 431                 ee->ee_atn_tx_rx_turbo[mode] |= (val & 0x7) << 3;
 432                 ee->ee_margin_tx_rx_turbo[mode] = (val >> 3) & 0x3f;
 433
 434                 ee->ee_adc_desired_size_turbo[mode] = (val >> 9) & 0x7f;
 435                 AR5K_EEPROM_READ(o++, val);
 436                 ee->ee_adc_desired_size_turbo[mode] |= (val & 0x1) << 7;
 437                 ee->ee_pga_desired_size_turbo[mode] = (val >> 1) & 0xff;
 438
 439                 if (AR5K_EEPROM_EEMAP(ee->ee_misc0) >=2)
 440                         ee->ee_pd_gain_overlap = (val >> 9) & 0xf;
 441                 break;
 442         case AR5K_EEPROM_MODE_11G:
 443                 ee->ee_switch_settling_turbo[mode] = (val >> 8) & 0x7f;
 444
 445                 ee->ee_atn_tx_rx_turbo[mode] = (val >> 15) & 0x7;
 446                 AR5K_EEPROM_READ(o++, val);
 447                 ee->ee_atn_tx_rx_turbo[mode] |= (val & 0x1f) << 1;
 448                 ee->ee_margin_tx_rx_turbo[mode] = (val >> 5) & 0x3f;
 449
 450                 ee->ee_adc_desired_size_turbo[mode] = (val >> 11) & 0x7f;
 451                 AR5K_EEPROM_READ(o++, val);
 452                 ee->ee_adc_desired_size_turbo[mode] |= (val & 0x7) << 5;
 453                 ee->ee_pga_desired_size_turbo[mode] = (val >> 3) & 0xff;
 454                 break;
 455         }
 456
 457 done:
 458         /* return new offset */
 459         *offset = o;
 460
 461         return 0;
 462 }
 463
 464 /* Read mode-specific data (except power calibration data) */
 465 static int
 466 ath5k_eeprom_init_modes(struct ath5k_hw *ah)
 467 {
 468         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
 469         u32 mode_offset[3];
 470         unsigned int mode;
 471         u32 offset;
 472         int ret;
 473
 474         /*
 475          * Get values for all modes
 476          */
 477         mode_offset[AR5K_EEPROM_MODE_11A] = AR5K_EEPROM_MODES_11A(ah->ah_ee_version);
 478         mode_offset[AR5K_EEPROM_MODE_11B] = AR5K_EEPROM_MODES_11B(ah->ah_ee_version);
 479         mode_offset[AR5K_EEPROM_MODE_11G] = AR5K_EEPROM_MODES_11G(ah->ah_ee_version);
 480
 481         ee->ee_turbo_max_power[AR5K_EEPROM_MODE_11A] =
 482                 AR5K_EEPROM_HDR_T_5GHZ_DBM(ee->ee_header);
 483
 484         for (mode = AR5K_EEPROM_MODE_11A; mode <= AR5K_EEPROM_MODE_11G; mode++) {
 485                 offset = mode_offset[mode];
 486
 487                 ret = ath5k_eeprom_read_ants(ah, &offset, mode);
 488                 if (ret)
 489                         return ret;
 490
 491                 ret = ath5k_eeprom_read_modes(ah, &offset, mode);
 492                 if (ret)
 493                         return ret;
 494         }
 495
 496         /* override for older eeprom versions for better performance */
 497         if (ah->ah_ee_version <= AR5K_EEPROM_VERSION_3_2) {
 498                 ee->ee_thr_62[AR5K_EEPROM_MODE_11A] = 15;
 499                 ee->ee_thr_62[AR5K_EEPROM_MODE_11B] = 28;
 500                 ee->ee_thr_62[AR5K_EEPROM_MODE_11G] = 28;
 501         }
 502
 503         return 0;
 504 }
 505
 506 /* Read the frequency piers for each mode (mostly used on newer eeproms with 0xff
 507  * frequency mask) */
 508 static inline int
 509 ath5k_eeprom_read_freq_list(struct ath5k_hw *ah, int *offset, int max,
 510                         struct ath5k_chan_pcal_info *pc, unsigned int mode)
 511 {
 512         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
 513         int o = *offset;
 514         int i = 0;
 515         u8 freq1, freq2;
 516         u16 val;
 517
 518         ee->ee_n_piers[mode] = 0;
 519         while(i < max) {
 520                 AR5K_EEPROM_READ(o++, val);
 521
 522                 freq1 = val & 0xff;
 523                 if (!freq1)
 524                         break;
 525
 526                 pc[i++].freq = ath5k_eeprom_bin2freq(ee,
 527                                 freq1, mode);
 528                 ee->ee_n_piers[mode]++;
 529
 530                 freq2 = (val >> 8) & 0xff;
 531                 if (!freq2)
 532                         break;
 533
 534                 pc[i++].freq = ath5k_eeprom_bin2freq(ee,
 535                                 freq2, mode);
 536                 ee->ee_n_piers[mode]++;
 537         }
 538
 539         /* return new offset */
 540         *offset = o;
 541
 542         return 0;
 543 }
 544
 545 /* Read frequency piers for 802.11a */
 546 static int
 547 ath5k_eeprom_init_11a_pcal_freq(struct ath5k_hw *ah, int offset)
 548 {
 549         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
 550         struct ath5k_chan_pcal_info *pcal = ee->ee_pwr_cal_a;
 551         int i;
 552         u16 val;
 553         u8 mask;
 554
 555         if (ee->ee_version >= AR5K_EEPROM_VERSION_3_3) {
 556                 ath5k_eeprom_read_freq_list(ah, &offset,
 557                         AR5K_EEPROM_N_5GHZ_CHAN, pcal,
 558                         AR5K_EEPROM_MODE_11A);
 559         } else {
 560                 mask = AR5K_EEPROM_FREQ_M(ah->ah_ee_version);
 561
 562                 AR5K_EEPROM_READ(offset++, val);
 563                 pcal[0].freq  = (val >> 9) & mask;
 564                 pcal[1].freq  = (val >> 2) & mask;
 565                 pcal[2].freq  = (val << 5) & mask;
 566
 567                 AR5K_EEPROM_READ(offset++, val);
 568                 pcal[2].freq |= (val >> 11) & 0x1f;
 569                 pcal[3].freq  = (val >> 4) & mask;
 570                 pcal[4].freq  = (val << 3) & mask;
 571
 572                 AR5K_EEPROM_READ(offset++, val);
 573                 pcal[4].freq |= (val >> 13) & 0x7;
 574                 pcal[5].freq  = (val >> 6) & mask;
 575                 pcal[6].freq  = (val << 1) & mask;
 576
 577                 AR5K_EEPROM_READ(offset++, val);
 578                 pcal[6].freq |= (val >> 15) & 0x1;
 579                 pcal[7].freq  = (val >> 8) & mask;
 580                 pcal[8].freq  = (val >> 1) & mask;
 581                 pcal[9].freq  = (val << 6) & mask;
 582
 583                 AR5K_EEPROM_READ(offset++, val);
 584                 pcal[9].freq |= (val >> 10) & 0x3f;
 585
 586                 /* Fixed number of piers */
 587                 ee->ee_n_piers[AR5K_EEPROM_MODE_11A] = 10;
 588
 589                 for (i = 0; i < AR5K_EEPROM_N_5GHZ_CHAN; i++) {
 590                         pcal[i].freq = ath5k_eeprom_bin2freq(ee,
 591                                 pcal[i].freq, AR5K_EEPROM_MODE_11A);
 592                 }
 593         }
 594
 595         return 0;
 596 }
 597
 598 /* Read frequency piers for 802.11bg on eeprom versions >= 5 and eemap >= 2 */
 599 static inline int
 600 ath5k_eeprom_init_11bg_2413(struct ath5k_hw *ah, unsigned int mode, int offset)
 601 {
 602         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
 603         struct ath5k_chan_pcal_info *pcal;
 604
 605         switch(mode) {
 606         case AR5K_EEPROM_MODE_11B:
 607                 pcal = ee->ee_pwr_cal_b;
 608                 break;
 609         case AR5K_EEPROM_MODE_11G:
 610                 pcal = ee->ee_pwr_cal_g;
 611                 break;
 612         default:
 613                 return -EINVAL;
 614         }
 615
 616         ath5k_eeprom_read_freq_list(ah, &offset,
 617                 AR5K_EEPROM_N_2GHZ_CHAN_2413, pcal,
 618                 mode);
 619
 620         return 0;
 621 }
 622
 623
 624 /*
 625  * Read power calibration for RF5111 chips
 626  *
 627  * For RF5111 we have an XPD -eXternal Power Detector- curve
 628  * for each calibrated channel. Each curve has 0,5dB Power steps
 629  * on x axis and PCDAC steps (offsets) on y axis and looks like an
 630  * exponential function. To recreate the curve we read 11 points
 631  * here and interpolate later.
 632  */
 633
 634 /* Used to match PCDAC steps with power values on RF5111 chips
 635  * (eeprom versions < 4). For RF5111 we have 11 pre-defined PCDAC
 636  * steps that match with the power values we read from eeprom. On
 637  * older eeprom versions (< 3.2) these steps are equaly spaced at
 638  * 10% of the pcdac curve -until the curve reaches its maximum-
 639  * (11 steps from 0 to 100%) but on newer eeprom versions (>= 3.2)
 640  * these 11 steps are spaced in a different way. This function returns
 641  * the pcdac steps based on eeprom version and curve min/max so that we
 642  * can have pcdac/pwr points.
 643  */
 644 static inline void
 645 ath5k_get_pcdac_intercepts(struct ath5k_hw *ah, u8 min, u8 max, u8 *vp)
 646 {
 647         static const u16 intercepts3[] = {
 648                 0, 5, 10, 20, 30, 50, 70, 85, 90, 95, 100
 649         };
 650         static const u16 intercepts3_2[] = {
 651                 0, 10, 20, 30, 40, 50, 60, 70, 80, 90, 100
 652         };
 653         const u16 *ip;
 654         int i;
 655
 656         if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_3_2)
 657                 ip = intercepts3_2;
 658         else
 659                 ip = intercepts3;
 660
 661         for (i = 0; i < ARRAY_SIZE(intercepts3); i++)
 662                 vp[i] = (ip[i] * max + (100 - ip[i]) * min) / 100;
 663 }
 664
 665 static int
 666 ath5k_eeprom_free_pcal_info(struct ath5k_hw *ah, int mode)
 667 {
 668         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
 669         struct ath5k_chan_pcal_info *chinfo;
 670         u8 pier, pdg;
 671
 672         switch (mode) {
 673         case AR5K_EEPROM_MODE_11A:
 674                 if (!AR5K_EEPROM_HDR_11A(ee->ee_header))
 675                         return 0;
 676                 chinfo = ee->ee_pwr_cal_a;
 677                 break;
 678         case AR5K_EEPROM_MODE_11B:
 679                 if (!AR5K_EEPROM_HDR_11B(ee->ee_header))
 680                         return 0;
 681                 chinfo = ee->ee_pwr_cal_b;
 682                 break;
 683         case AR5K_EEPROM_MODE_11G:
 684                 if (!AR5K_EEPROM_HDR_11G(ee->ee_header))
 685                         return 0;
 686                 chinfo = ee->ee_pwr_cal_g;
 687                 break;
 688         default:
 689                 return -EINVAL;
 690         }
 691
 692         for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) {
 693                 if (!chinfo[pier].pd_curves)
 694                         continue;
 695
 696                 for (pdg = 0; pdg < ee->ee_pd_gains[mode]; pdg++) {
 697                         struct ath5k_pdgain_info *pd =
 698                                         &chinfo[pier].pd_curves[pdg];
 699
 700                         if (pd != NULL) {
 701                                 kfree(pd->pd_step);
 702                                 kfree(pd->pd_pwr);
 703                         }
 704                 }
 705
 706                 kfree(chinfo[pier].pd_curves);
 707         }
 708
 709         return 0;
 710 }
 711
 712 /* Convert RF5111 specific data to generic raw data
 713  * used by interpolation code */
 714 static int
 715 ath5k_eeprom_convert_pcal_info_5111(struct ath5k_hw *ah, int mode,
 716                                 struct ath5k_chan_pcal_info *chinfo)
 717 {
 718         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
 719         struct ath5k_chan_pcal_info_rf5111 *pcinfo;
 720         struct ath5k_pdgain_info *pd;
 721         u8 pier, point, idx;
 722         u8 *pdgain_idx = ee->ee_pdc_to_idx[mode];
 723
 724         /* Fill raw data for each calibration pier */
 725         for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) {
 726
 727                 pcinfo = &chinfo[pier].rf5111_info;
 728
 729                 /* Allocate pd_curves for this cal pier */
 730                 chinfo[pier].pd_curves =
 731                         kcalloc(AR5K_EEPROM_N_PD_CURVES,
 732                                 sizeof(struct ath5k_pdgain_info),
 733                                 GFP_KERNEL);
 734
 735                 if (!chinfo[pier].pd_curves)
 736                         goto err_out;
 737
 738                 /* Only one curve for RF5111
 739                  * find out which one and place
 740                  * in pd_curves.
 741                  * Note: ee_x_gain is reversed here */
 742                 for (idx = 0; idx < AR5K_EEPROM_N_PD_CURVES; idx++) {
 743
 744                         if (!((ee->ee_x_gain[mode] >> idx) & 0x1)) {
 745                                 pdgain_idx[0] = idx;
 746                                 break;
 747                         }
 748                 }
 749
 750                 ee->ee_pd_gains[mode] = 1;
 751
 752                 pd = &chinfo[pier].pd_curves[idx];
 753
 754                 pd->pd_points = AR5K_EEPROM_N_PWR_POINTS_5111;
 755
 756                 /* Allocate pd points for this curve */
 757                 pd->pd_step = kcalloc(AR5K_EEPROM_N_PWR_POINTS_5111,
 758                                         sizeof(u8), GFP_KERNEL);
 759                 if (!pd->pd_step)
 760                         goto err_out;
 761
 762                 pd->pd_pwr = kcalloc(AR5K_EEPROM_N_PWR_POINTS_5111,
 763                                         sizeof(s16), GFP_KERNEL);
 764                 if (!pd->pd_pwr)
 765                         goto err_out;
 766
 767                 /* Fill raw dataset
 768                  * (convert power to 0.25dB units
 769                  * for RF5112 combatibility) */
 770                 for (point = 0; point < pd->pd_points; point++) {
 771
 772                         /* Absolute values */
 773                         pd->pd_pwr[point] = 2 * pcinfo->pwr[point];
 774
 775                         /* Already sorted */
 776                         pd->pd_step[point] = pcinfo->pcdac[point];
 777                 }
 778
 779                 /* Set min/max pwr */
 780                 chinfo[pier].min_pwr = pd->pd_pwr[0];
 781                 chinfo[pier].max_pwr = pd->pd_pwr[10];
 782
 783         }
 784
 785         return 0;
 786
 787 err_out:
 788         ath5k_eeprom_free_pcal_info(ah, mode);
 789         return -ENOMEM;
 790 }
 791
 792 /* Parse EEPROM data */
 793 static int
 794 ath5k_eeprom_read_pcal_info_5111(struct ath5k_hw *ah, int mode)
 795 {
 796         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
 797         struct ath5k_chan_pcal_info *pcal;
 798         int offset, ret;
 799         int i;
 800         u16 val;
 801
 802         offset = AR5K_EEPROM_GROUPS_START(ee->ee_version);
 803         switch(mode) {
 804         case AR5K_EEPROM_MODE_11A:
 805                 if (!AR5K_EEPROM_HDR_11A(ee->ee_header))
 806                         return 0;
 807
 808                 ret = ath5k_eeprom_init_11a_pcal_freq(ah,
 809                         offset + AR5K_EEPROM_GROUP1_OFFSET);
 810                 if (ret < 0)
 811                         return ret;
 812
 813                 offset += AR5K_EEPROM_GROUP2_OFFSET;
 814                 pcal = ee->ee_pwr_cal_a;
 815                 break;
 816         case AR5K_EEPROM_MODE_11B:
 817                 if (!AR5K_EEPROM_HDR_11B(ee->ee_header) &&
 818                     !AR5K_EEPROM_HDR_11G(ee->ee_header))
 819                         return 0;
 820
 821                 pcal = ee->ee_pwr_cal_b;
 822                 offset += AR5K_EEPROM_GROUP3_OFFSET;
 823
 824                 /* fixed piers */
 825                 pcal[0].freq = 2412;
 826                 pcal[1].freq = 2447;
 827                 pcal[2].freq = 2484;
 828                 ee->ee_n_piers[mode] = 3;
 829                 break;
 830         case AR5K_EEPROM_MODE_11G:
 831                 if (!AR5K_EEPROM_HDR_11G(ee->ee_header))
 832                         return 0;
 833
 834                 pcal = ee->ee_pwr_cal_g;
 835                 offset += AR5K_EEPROM_GROUP4_OFFSET;
 836
 837                 /* fixed piers */
 838                 pcal[0].freq = 2312;
 839                 pcal[1].freq = 2412;
 840                 pcal[2].freq = 2484;
 841                 ee->ee_n_piers[mode] = 3;
 842                 break;
 843         default:
 844                 return -EINVAL;
 845         }
 846
 847         for (i = 0; i < ee->ee_n_piers[mode]; i++) {
 848                 struct ath5k_chan_pcal_info_rf5111 *cdata =
 849                         &pcal[i].rf5111_info;
 850
 851                 AR5K_EEPROM_READ(offset++, val);
 852                 cdata->pcdac_max = ((val >> 10) & AR5K_EEPROM_PCDAC_M);
 853                 cdata->pcdac_min = ((val >> 4) & AR5K_EEPROM_PCDAC_M);
 854                 cdata->pwr[0] = ((val << 2) & AR5K_EEPROM_POWER_M);
 855
 856                 AR5K_EEPROM_READ(offset++, val);
 857                 cdata->pwr[0] |= ((val >> 14) & 0x3);
 858                 cdata->pwr[1] = ((val >> 8) & AR5K_EEPROM_POWER_M);
 859                 cdata->pwr[2] = ((val >> 2) & AR5K_EEPROM_POWER_M);
 860                 cdata->pwr[3] = ((val << 4) & AR5K_EEPROM_POWER_M);
 861
 862                 AR5K_EEPROM_READ(offset++, val);
 863                 cdata->pwr[3] |= ((val >> 12) & 0xf);
 864                 cdata->pwr[4] = ((val >> 6) & AR5K_EEPROM_POWER_M);
 865                 cdata->pwr[5] = (val  & AR5K_EEPROM_POWER_M);
 866
 867                 AR5K_EEPROM_READ(offset++, val);
 868                 cdata->pwr[6] = ((val >> 10) & AR5K_EEPROM_POWER_M);
 869                 cdata->pwr[7] = ((val >> 4) & AR5K_EEPROM_POWER_M);
 870                 cdata->pwr[8] = ((val << 2) & AR5K_EEPROM_POWER_M);
 871
 872                 AR5K_EEPROM_READ(offset++, val);
 873                 cdata->pwr[8] |= ((val >> 14) & 0x3);
 874                 cdata->pwr[9] = ((val >> 8) & AR5K_EEPROM_POWER_M);
 875                 cdata->pwr[10] = ((val >> 2) & AR5K_EEPROM_POWER_M);
 876
 877                 ath5k_get_pcdac_intercepts(ah, cdata->pcdac_min,
 878                         cdata->pcdac_max, cdata->pcdac);
 879         }
 880
 881         return ath5k_eeprom_convert_pcal_info_5111(ah, mode, pcal);
 882 }
 883
 884
 885 /*
 886  * Read power calibration for RF5112 chips
 887  *
 888  * For RF5112 we have 4 XPD -eXternal Power Detector- curves
 889  * for each calibrated channel on 0, -6, -12 and -18dbm but we only
 890  * use the higher (3) and the lower (0) curves. Each curve has 0.5dB
 891  * power steps on x axis and PCDAC steps on y axis and looks like a
 892  * linear function. To recreate the curve and pass the power values
 893  * on hw, we read 4 points for xpd 0 (lower gain -> max power)
 894  * and 3 points for xpd 3 (higher gain -> lower power) here and
 895  * interpolate later.
 896  *
 897  * Note: Many vendors just use xpd 0 so xpd 3 is zeroed.
 898  */
 899
 900 /* Convert RF5112 specific data to generic raw data
 901  * used by interpolation code */
 902 static int
 903 ath5k_eeprom_convert_pcal_info_5112(struct ath5k_hw *ah, int mode,
 904                                 struct ath5k_chan_pcal_info *chinfo)
 905 {
 906         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
 907         struct ath5k_chan_pcal_info_rf5112 *pcinfo;
 908         u8 *pdgain_idx = ee->ee_pdc_to_idx[mode];
 909         unsigned int pier, pdg, point;
 910
 911         /* Fill raw data for each calibration pier */
 912         for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) {
 913
 914                 pcinfo = &chinfo[pier].rf5112_info;
 915
 916                 /* Allocate pd_curves for this cal pier */
 917                 chinfo[pier].pd_curves =
 918                                 kcalloc(AR5K_EEPROM_N_PD_CURVES,
 919                                         sizeof(struct ath5k_pdgain_info),
 920                                         GFP_KERNEL);
 921
 922                 if (!chinfo[pier].pd_curves)
 923                         goto err_out;
 924
 925                 /* Fill pd_curves */
 926                 for (pdg = 0; pdg < ee->ee_pd_gains[mode]; pdg++) {
 927
 928                         u8 idx = pdgain_idx[pdg];
 929                         struct ath5k_pdgain_info *pd =
 930                                         &chinfo[pier].pd_curves[idx];
 931
 932                         /* Lowest gain curve (max power) */
 933                         if (pdg == 0) {
 934                                 /* One more point for better accuracy */
 935                                 pd->pd_points = AR5K_EEPROM_N_XPD0_POINTS;
 936
 937                                 /* Allocate pd points for this curve */
 938                                 pd->pd_step = kcalloc(pd->pd_points,
 939                                                 sizeof(u8), GFP_KERNEL);
 940
 941                                 if (!pd->pd_step)
 942                                         goto err_out;
 943
 944                                 pd->pd_pwr = kcalloc(pd->pd_points,
 945                                                 sizeof(s16), GFP_KERNEL);
 946
 947                                 if (!pd->pd_pwr)
 948                                         goto err_out;
 949
 950                                 /* Fill raw dataset
 951                                  * (all power levels are in 0.25dB units) */
 952                                 pd->pd_step[0] = pcinfo->pcdac_x0[0];
 953                                 pd->pd_pwr[0] = pcinfo->pwr_x0[0];
 954
 955                                 for (point = 1; point < pd->pd_points;
 956                                 point++) {
 957                                         /* Absolute values */
 958                                         pd->pd_pwr[point] =
 959                                                 pcinfo->pwr_x0[point];
 960
 961                                         /* Deltas */
 962                                         pd->pd_step[point] =
 963                                                 pd->pd_step[point - 1] +
 964                                                 pcinfo->pcdac_x0[point];
 965                                 }
 966
 967                                 /* Set min power for this frequency */
 968                                 chinfo[pier].min_pwr = pd->pd_pwr[0];
 969
 970                         /* Highest gain curve (min power) */
 971                         } else if (pdg == 1) {
 972
 973                                 pd->pd_points = AR5K_EEPROM_N_XPD3_POINTS;
 974
 975                                 /* Allocate pd points for this curve */
 976                                 pd->pd_step = kcalloc(pd->pd_points,
 977                                                 sizeof(u8), GFP_KERNEL);
 978
 979                                 if (!pd->pd_step)
 980                                         goto err_out;
 981
 982                                 pd->pd_pwr = kcalloc(pd->pd_points,
 983                                                 sizeof(s16), GFP_KERNEL);
 984
 985                                 if (!pd->pd_pwr)
 986                                         goto err_out;
 987
 988                                 /* Fill raw dataset
 989                                  * (all power levels are in 0.25dB units) */
 990                                 for (point = 0; point < pd->pd_points;
 991                                 point++) {
 992                                         /* Absolute values */
 993                                         pd->pd_pwr[point] =
 994                                                 pcinfo->pwr_x3[point];
 995
 996                                         /* Fixed points */
 997                                         pd->pd_step[point] =
 998                                                 pcinfo->pcdac_x3[point];
 999                                 }
1000
1001                                 /* Since we have a higher gain curve
1002                                  * override min power */
1003                                 chinfo[pier].min_pwr = pd->pd_pwr[0];
1004                         }
1005                 }
1006         }
1007
1008         return 0;
1009
1010 err_out:
1011         ath5k_eeprom_free_pcal_info(ah, mode);
1012         return -ENOMEM;
1013 }
1014
1015 /* Parse EEPROM data */
1016 static int
1017 ath5k_eeprom_read_pcal_info_5112(struct ath5k_hw *ah, int mode)
1018 {
1019         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1020         struct ath5k_chan_pcal_info_rf5112 *chan_pcal_info;
1021         struct ath5k_chan_pcal_info *gen_chan_info;
1022         u8 *pdgain_idx = ee->ee_pdc_to_idx[mode];
1023         u32 offset;
1024         u8 i, c;
1025         u16 val;
1026         u8 pd_gains = 0;
1027
1028         /* Count how many curves we have and
1029          * identify them (which one of the 4
1030          * available curves we have on each count).
1031          * Curves are stored from lower (x0) to
1032          * higher (x3) gain */
1033         for (i = 0; i < AR5K_EEPROM_N_PD_CURVES; i++) {
1034                 /* ee_x_gain[mode] is x gain mask */
1035                 if ((ee->ee_x_gain[mode] >> i) & 0x1)
1036                         pdgain_idx[pd_gains++] = i;
1037         }
1038         ee->ee_pd_gains[mode] = pd_gains;
1039
1040         if (pd_gains == 0 || pd_gains > 2)
1041                 return -EINVAL;
1042
1043         switch (mode) {
1044         case AR5K_EEPROM_MODE_11A:
1045                 /*
1046                  * Read 5GHz EEPROM channels
1047                  */
1048                 offset = AR5K_EEPROM_GROUPS_START(ee->ee_version);
1049                 ath5k_eeprom_init_11a_pcal_freq(ah, offset);
1050
1051                 offset += AR5K_EEPROM_GROUP2_OFFSET;
1052                 gen_chan_info = ee->ee_pwr_cal_a;
1053                 break;
1054         case AR5K_EEPROM_MODE_11B:
1055                 offset = AR5K_EEPROM_GROUPS_START(ee->ee_version);
1056                 if (AR5K_EEPROM_HDR_11A(ee->ee_header))
1057                         offset += AR5K_EEPROM_GROUP3_OFFSET;
1058
1059                 /* NB: frequency piers parsed during mode init */
1060                 gen_chan_info = ee->ee_pwr_cal_b;
1061                 break;
1062         case AR5K_EEPROM_MODE_11G:
1063                 offset = AR5K_EEPROM_GROUPS_START(ee->ee_version);
1064                 if (AR5K_EEPROM_HDR_11A(ee->ee_header))
1065                         offset += AR5K_EEPROM_GROUP4_OFFSET;
1066                 else if (AR5K_EEPROM_HDR_11B(ee->ee_header))
1067                         offset += AR5K_EEPROM_GROUP2_OFFSET;
1068
1069                 /* NB: frequency piers parsed during mode init */
1070                 gen_chan_info = ee->ee_pwr_cal_g;
1071                 break;
1072         default:
1073                 return -EINVAL;
1074         }
1075
1076         for (i = 0; i < ee->ee_n_piers[mode]; i++) {
1077                 chan_pcal_info = &gen_chan_info[i].rf5112_info;
1078
1079                 /* Power values in quarter dB
1080                  * for the lower xpd gain curve
1081                  * (0 dBm -> higher output power) */
1082                 for (c = 0; c < AR5K_EEPROM_N_XPD0_POINTS; c++) {
1083                         AR5K_EEPROM_READ(offset++, val);
1084                         chan_pcal_info->pwr_x0[c] = (s8) (val & 0xff);
1085                         chan_pcal_info->pwr_x0[++c] = (s8) ((val >> 8) & 0xff);
1086                 }
1087
1088                 /* PCDAC steps
1089                  * corresponding to the above power
1090                  * measurements */
1091                 AR5K_EEPROM_READ(offset++, val);
1092                 chan_pcal_info->pcdac_x0[1] = (val & 0x1f);
1093                 chan_pcal_info->pcdac_x0[2] = ((val >> 5) & 0x1f);
1094                 chan_pcal_info->pcdac_x0[3] = ((val >> 10) & 0x1f);
1095
1096                 /* Power values in quarter dB
1097                  * for the higher xpd gain curve
1098                  * (18 dBm -> lower output power) */
1099                 AR5K_EEPROM_READ(offset++, val);
1100                 chan_pcal_info->pwr_x3[0] = (s8) (val & 0xff);
1101                 chan_pcal_info->pwr_x3[1] = (s8) ((val >> 8) & 0xff);
1102
1103                 AR5K_EEPROM_READ(offset++, val);
1104                 chan_pcal_info->pwr_x3[2] = (val & 0xff);
1105
1106                 /* PCDAC steps
1107                  * corresponding to the above power
1108                  * measurements (fixed) */
1109                 chan_pcal_info->pcdac_x3[0] = 20;
1110                 chan_pcal_info->pcdac_x3[1] = 35;
1111                 chan_pcal_info->pcdac_x3[2] = 63;
1112
1113                 if (ee->ee_version >= AR5K_EEPROM_VERSION_4_3) {
1114                         chan_pcal_info->pcdac_x0[0] = ((val >> 8) & 0x3f);
1115
1116                         /* Last xpd0 power level is also channel maximum */
1117                         gen_chan_info[i].max_pwr = chan_pcal_info->pwr_x0[3];
1118                 } else {
1119                         chan_pcal_info->pcdac_x0[0] = 1;
1120                         gen_chan_info[i].max_pwr = (s8) ((val >> 8) & 0xff);
1121                 }
1122
1123         }
1124
1125         return ath5k_eeprom_convert_pcal_info_5112(ah, mode, gen_chan_info);
1126 }
1127
1128
1129 /*
1130  * Read power calibration for RF2413 chips
1131  *
1132  * For RF2413 we have a Power to PDDAC table (Power Detector)
1133  * instead of a PCDAC and 4 pd gain curves for each calibrated channel.
1134  * Each curve has power on x axis in 0.5 db steps and PDDADC steps on y
1135  * axis and looks like an exponential function like the RF5111 curve.
1136  *
1137  * To recreate the curves we read here the points and interpolate
1138  * later. Note that in most cases only 2 (higher and lower) curves are
1139  * used (like RF5112) but vendors have the opportunity to include all
1140  * 4 curves on eeprom. The final curve (higher power) has an extra
1141  * point for better accuracy like RF5112.
1142  */
1143
1144 /* For RF2413 power calibration data doesn't start on a fixed location and
1145  * if a mode is not supported, its section is missing -not zeroed-.
1146  * So we need to calculate the starting offset for each section by using
1147  * these two functions */
1148
1149 /* Return the size of each section based on the mode and the number of pd
1150  * gains available (maximum 4). */
1151 static inline unsigned int
1152 ath5k_pdgains_size_2413(struct ath5k_eeprom_info *ee, unsigned int mode)
1153 {
1154         static const unsigned int pdgains_size[] = { 4, 6, 9, 12 };
1155         unsigned int sz;
1156
1157         sz = pdgains_size[ee->ee_pd_gains[mode] - 1];
1158         sz *= ee->ee_n_piers[mode];
1159
1160         return sz;
1161 }
1162
1163 /* Return the starting offset for a section based on the modes supported
1164  * and each section's size. */
1165 static unsigned int
1166 ath5k_cal_data_offset_2413(struct ath5k_eeprom_info *ee, int mode)
1167 {
1168         u32 offset = AR5K_EEPROM_CAL_DATA_START(ee->ee_misc4);
1169
1170         switch(mode) {
1171         case AR5K_EEPROM_MODE_11G:
1172                 if (AR5K_EEPROM_HDR_11B(ee->ee_header))
1173                         offset += ath5k_pdgains_size_2413(ee,
1174                                         AR5K_EEPROM_MODE_11B) +
1175                                         AR5K_EEPROM_N_2GHZ_CHAN_2413 / 2;
1176                 /* fall through */
1177         case AR5K_EEPROM_MODE_11B:
1178                 if (AR5K_EEPROM_HDR_11A(ee->ee_header))
1179                         offset += ath5k_pdgains_size_2413(ee,
1180                                         AR5K_EEPROM_MODE_11A) +
1181                                         AR5K_EEPROM_N_5GHZ_CHAN / 2;
1182                 /* fall through */
1183         case AR5K_EEPROM_MODE_11A:
1184                 break;
1185         default:
1186                 break;
1187         }
1188
1189         return offset;
1190 }
1191
1192 /* Convert RF2413 specific data to generic raw data
1193  * used by interpolation code */
1194 static int
1195 ath5k_eeprom_convert_pcal_info_2413(struct ath5k_hw *ah, int mode,
1196                                 struct ath5k_chan_pcal_info *chinfo)
1197 {
1198         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1199         struct ath5k_chan_pcal_info_rf2413 *pcinfo;
1200         u8 *pdgain_idx = ee->ee_pdc_to_idx[mode];
1201         unsigned int pier, pdg, point;
1202
1203         /* Fill raw data for each calibration pier */
1204         for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) {
1205
1206                 pcinfo = &chinfo[pier].rf2413_info;
1207
1208                 /* Allocate pd_curves for this cal pier */
1209                 chinfo[pier].pd_curves =
1210                                 kcalloc(AR5K_EEPROM_N_PD_CURVES,
1211                                         sizeof(struct ath5k_pdgain_info),
1212                                         GFP_KERNEL);
1213
1214                 if (!chinfo[pier].pd_curves)
1215                         goto err_out;
1216
1217                 /* Fill pd_curves */
1218                 for (pdg = 0; pdg < ee->ee_pd_gains[mode]; pdg++) {
1219
1220                         u8 idx = pdgain_idx[pdg];
1221                         struct ath5k_pdgain_info *pd =
1222                                         &chinfo[pier].pd_curves[idx];
1223
1224                         /* One more point for the highest power
1225                          * curve (lowest gain) */
1226                         if (pdg == ee->ee_pd_gains[mode] - 1)
1227                                 pd->pd_points = AR5K_EEPROM_N_PD_POINTS;
1228                         else
1229                                 pd->pd_points = AR5K_EEPROM_N_PD_POINTS - 1;
1230
1231                         /* Allocate pd points for this curve */
1232                         pd->pd_step = kcalloc(pd->pd_points,
1233                                         sizeof(u8), GFP_KERNEL);
1234
1235                         if (!pd->pd_step)
1236                                 goto err_out;
1237
1238                         pd->pd_pwr = kcalloc(pd->pd_points,
1239                                         sizeof(s16), GFP_KERNEL);
1240
1241                         if (!pd->pd_pwr)
1242                                 goto err_out;
1243
1244                         /* Fill raw dataset
1245                          * convert all pwr levels to
1246                          * quarter dB for RF5112 combatibility */
1247                         pd->pd_step[0] = pcinfo->pddac_i[pdg];
1248                         pd->pd_pwr[0] = 4 * pcinfo->pwr_i[pdg];
1249
1250                         for (point = 1; point < pd->pd_points; point++) {
1251
1252                                 pd->pd_pwr[point] = pd->pd_pwr[point - 1] +
1253                                         2 * pcinfo->pwr[pdg][point - 1];
1254
1255                                 pd->pd_step[point] = pd->pd_step[point - 1] +
1256                                                 pcinfo->pddac[pdg][point - 1];
1257
1258                         }
1259
1260                         /* Highest gain curve -> min power */
1261                         if (pdg == 0)
1262                                 chinfo[pier].min_pwr = pd->pd_pwr[0];
1263
1264                         /* Lowest gain curve -> max power */
1265                         if (pdg == ee->ee_pd_gains[mode] - 1)
1266                                 chinfo[pier].max_pwr =
1267                                         pd->pd_pwr[pd->pd_points - 1];
1268                 }
1269         }
1270
1271         return 0;
1272
1273 err_out:
1274         ath5k_eeprom_free_pcal_info(ah, mode);
1275         return -ENOMEM;
1276 }
1277
1278 /* Parse EEPROM data */
1279 static int
1280 ath5k_eeprom_read_pcal_info_2413(struct ath5k_hw *ah, int mode)
1281 {
1282         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1283         struct ath5k_chan_pcal_info_rf2413 *pcinfo;
1284         struct ath5k_chan_pcal_info *chinfo;
1285         u8 *pdgain_idx = ee->ee_pdc_to_idx[mode];
1286         u32 offset;
1287         int idx, i;
1288         u16 val;
1289         u8 pd_gains = 0;
1290
1291         /* Count how many curves we have and
1292          * identify them (which one of the 4
1293          * available curves we have on each count).
1294          * Curves are stored from higher to
1295          * lower gain so we go backwards */
1296         for (idx = AR5K_EEPROM_N_PD_CURVES - 1; idx >= 0; idx--) {
1297                 /* ee_x_gain[mode] is x gain mask */
1298                 if ((ee->ee_x_gain[mode] >> idx) & 0x1)
1299                         pdgain_idx[pd_gains++] = idx;
1300
1301         }
1302         ee->ee_pd_gains[mode] = pd_gains;
1303
1304         if (pd_gains == 0)
1305                 return -EINVAL;
1306
1307         offset = ath5k_cal_data_offset_2413(ee, mode);
1308         switch (mode) {
1309         case AR5K_EEPROM_MODE_11A:
1310                 if (!AR5K_EEPROM_HDR_11A(ee->ee_header))
1311                         return 0;
1312
1313                 ath5k_eeprom_init_11a_pcal_freq(ah, offset);
1314                 offset += AR5K_EEPROM_N_5GHZ_CHAN / 2;
1315                 chinfo = ee->ee_pwr_cal_a;
1316                 break;
1317         case AR5K_EEPROM_MODE_11B:
1318                 if (!AR5K_EEPROM_HDR_11B(ee->ee_header))
1319                         return 0;
1320
1321                 ath5k_eeprom_init_11bg_2413(ah, mode, offset);
1322                 offset += AR5K_EEPROM_N_2GHZ_CHAN_2413 / 2;
1323                 chinfo = ee->ee_pwr_cal_b;
1324                 break;
1325         case AR5K_EEPROM_MODE_11G:
1326                 if (!AR5K_EEPROM_HDR_11G(ee->ee_header))
1327                         return 0;
1328
1329                 ath5k_eeprom_init_11bg_2413(ah, mode, offset);
1330                 offset += AR5K_EEPROM_N_2GHZ_CHAN_2413 / 2;
1331                 chinfo = ee->ee_pwr_cal_g;
1332                 break;
1333         default:
1334                 return -EINVAL;
1335         }
1336
1337         for (i = 0; i < ee->ee_n_piers[mode]; i++) {
1338                 pcinfo = &chinfo[i].rf2413_info;
1339
1340                 /*
1341                  * Read pwr_i, pddac_i and the first
1342                  * 2 pd points (pwr, pddac)
1343                  */
1344                 AR5K_EEPROM_READ(offset++, val);
1345                 pcinfo->pwr_i[0] = val & 0x1f;
1346                 pcinfo->pddac_i[0] = (val >> 5) & 0x7f;
1347                 pcinfo->pwr[0][0] = (val >> 12) & 0xf;
1348
1349                 AR5K_EEPROM_READ(offset++, val);
1350                 pcinfo->pddac[0][0] = val & 0x3f;
1351                 pcinfo->pwr[0][1] = (val >> 6) & 0xf;
1352                 pcinfo->pddac[0][1] = (val >> 10) & 0x3f;
1353
1354                 AR5K_EEPROM_READ(offset++, val);
1355                 pcinfo->pwr[0][2] = val & 0xf;
1356                 pcinfo->pddac[0][2] = (val >> 4) & 0x3f;
1357
1358                 pcinfo->pwr[0][3] = 0;
1359                 pcinfo->pddac[0][3] = 0;
1360
1361                 if (pd_gains > 1) {
1362                         /*
1363                          * Pd gain 0 is not the last pd gain
1364                          * so it only has 2 pd points.
1365                          * Continue with pd gain 1.
1366                          */
1367                         pcinfo->pwr_i[1] = (val >> 10) & 0x1f;
1368
1369                         pcinfo->pddac_i[1] = (val >> 15) & 0x1;
1370                         AR5K_EEPROM_READ(offset++, val);
1371                         pcinfo->pddac_i[1] |= (val & 0x3F) << 1;
1372
1373                         pcinfo->pwr[1][0] = (val >> 6) & 0xf;
1374                         pcinfo->pddac[1][0] = (val >> 10) & 0x3f;
1375
1376                         AR5K_EEPROM_READ(offset++, val);
1377                         pcinfo->pwr[1][1] = val & 0xf;
1378                         pcinfo->pddac[1][1] = (val >> 4) & 0x3f;
1379                         pcinfo->pwr[1][2] = (val >> 10) & 0xf;
1380
1381                         pcinfo->pddac[1][2] = (val >> 14) & 0x3;
1382                         AR5K_EEPROM_READ(offset++, val);
1383                         pcinfo->pddac[1][2] |= (val & 0xF) << 2;
1384
1385                         pcinfo->pwr[1][3] = 0;
1386                         pcinfo->pddac[1][3] = 0;
1387                 } else if (pd_gains == 1) {
1388                         /*
1389                          * Pd gain 0 is the last one so
1390                          * read the extra point.
1391                          */
1392                         pcinfo->pwr[0][3] = (val >> 10) & 0xf;
1393
1394                         pcinfo->pddac[0][3] = (val >> 14) & 0x3;
1395                         AR5K_EEPROM_READ(offset++, val);
1396                         pcinfo->pddac[0][3] |= (val & 0xF) << 2;
1397                 }
1398
1399                 /*
1400                  * Proceed with the other pd_gains
1401                  * as above.
1402                  */
1403                 if (pd_gains > 2) {
1404                         pcinfo->pwr_i[2] = (val >> 4) & 0x1f;
1405                         pcinfo->pddac_i[2] = (val >> 9) & 0x7f;
1406
1407                         AR5K_EEPROM_READ(offset++, val);
1408                         pcinfo->pwr[2][0] = (val >> 0) & 0xf;
1409                         pcinfo->pddac[2][0] = (val >> 4) & 0x3f;
1410                         pcinfo->pwr[2][1] = (val >> 10) & 0xf;
1411
1412                         pcinfo->pddac[2][1] = (val >> 14) & 0x3;
1413                         AR5K_EEPROM_READ(offset++, val);
1414                         pcinfo->pddac[2][1] |= (val & 0xF) << 2;
1415
1416                         pcinfo->pwr[2][2] = (val >> 4) & 0xf;
1417                         pcinfo->pddac[2][2] = (val >> 8) & 0x3f;
1418
1419                         pcinfo->pwr[2][3] = 0;
1420                         pcinfo->pddac[2][3] = 0;
1421                 } else if (pd_gains == 2) {
1422                         pcinfo->pwr[1][3] = (val >> 4) & 0xf;
1423                         pcinfo->pddac[1][3] = (val >> 8) & 0x3f;
1424                 }
1425
1426                 if (pd_gains > 3) {
1427                         pcinfo->pwr_i[3] = (val >> 14) & 0x3;
1428                         AR5K_EEPROM_READ(offset++, val);
1429                         pcinfo->pwr_i[3] |= ((val >> 0) & 0x7) << 2;
1430
1431                         pcinfo->pddac_i[3] = (val >> 3) & 0x7f;
1432                         pcinfo->pwr[3][0] = (val >> 10) & 0xf;
1433                         pcinfo->pddac[3][0] = (val >> 14) & 0x3;
1434
1435                         AR5K_EEPROM_READ(offset++, val);
1436                         pcinfo->pddac[3][0] |= (val & 0xF) << 2;
1437                         pcinfo->pwr[3][1] = (val >> 4) & 0xf;
1438                         pcinfo->pddac[3][1] = (val >> 8) & 0x3f;
1439
1440                         pcinfo->pwr[3][2] = (val >> 14) & 0x3;
1441                         AR5K_EEPROM_READ(offset++, val);
1442                         pcinfo->pwr[3][2] |= ((val >> 0) & 0x3) << 2;
1443
1444                         pcinfo->pddac[3][2] = (val >> 2) & 0x3f;
1445                         pcinfo->pwr[3][3] = (val >> 8) & 0xf;
1446
1447                         pcinfo->pddac[3][3] = (val >> 12) & 0xF;
1448                         AR5K_EEPROM_READ(offset++, val);
1449                         pcinfo->pddac[3][3] |= ((val >> 0) & 0x3) << 4;
1450                 } else if (pd_gains == 3) {
1451                         pcinfo->pwr[2][3] = (val >> 14) & 0x3;
1452                         AR5K_EEPROM_READ(offset++, val);
1453                         pcinfo->pwr[2][3] |= ((val >> 0) & 0x3) << 2;
1454
1455                         pcinfo->pddac[2][3] = (val >> 2) & 0x3f;
1456                 }
1457         }
1458
1459         return ath5k_eeprom_convert_pcal_info_2413(ah, mode, chinfo);
1460 }
1461
1462
1463 /*
1464  * Read per rate target power (this is the maximum tx power
1465  * supported by the card). This info is used when setting
1466  * tx power, no matter the channel.
1467  *
1468  * This also works for v5 EEPROMs.
1469  */
1470 static int
1471 ath5k_eeprom_read_target_rate_pwr_info(struct ath5k_hw *ah, unsigned int mode)
1472 {
1473         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1474         struct ath5k_rate_pcal_info *rate_pcal_info;
1475         u8 *rate_target_pwr_num;
1476         u32 offset;
1477         u16 val;
1478         int i;
1479
1480         offset = AR5K_EEPROM_TARGET_PWRSTART(ee->ee_misc1);
1481         rate_target_pwr_num = &ee->ee_rate_target_pwr_num[mode];
1482         switch (mode) {
1483         case AR5K_EEPROM_MODE_11A:
1484                 offset += AR5K_EEPROM_TARGET_PWR_OFF_11A(ee->ee_version);
1485                 rate_pcal_info = ee->ee_rate_tpwr_a;
1486                 ee->ee_rate_target_pwr_num[mode] = AR5K_EEPROM_N_5GHZ_CHAN;
1487                 break;
1488         case AR5K_EEPROM_MODE_11B:
1489                 offset += AR5K_EEPROM_TARGET_PWR_OFF_11B(ee->ee_version);
1490                 rate_pcal_info = ee->ee_rate_tpwr_b;
1491                 ee->ee_rate_target_pwr_num[mode] = 2; /* 3rd is g mode's 1st */
1492                 break;
1493         case AR5K_EEPROM_MODE_11G:
1494                 offset += AR5K_EEPROM_TARGET_PWR_OFF_11G(ee->ee_version);
1495                 rate_pcal_info = ee->ee_rate_tpwr_g;
1496                 ee->ee_rate_target_pwr_num[mode] = AR5K_EEPROM_N_2GHZ_CHAN;
1497                 break;
1498         default:
1499                 return -EINVAL;
1500         }
1501
1502         /* Different freq mask for older eeproms (<= v3.2) */
1503         if (ee->ee_version <= AR5K_EEPROM_VERSION_3_2) {
1504                 for (i = 0; i < (*rate_target_pwr_num); i++) {
1505                         AR5K_EEPROM_READ(offset++, val);
1506                         rate_pcal_info[i].freq =
1507                             ath5k_eeprom_bin2freq(ee, (val >> 9) & 0x7f, mode);
1508
1509                         rate_pcal_info[i].target_power_6to24 = ((val >> 3) & 0x3f);
1510                         rate_pcal_info[i].target_power_36 = (val << 3) & 0x3f;
1511
1512                         AR5K_EEPROM_READ(offset++, val);
1513
1514                         if (rate_pcal_info[i].freq == AR5K_EEPROM_CHANNEL_DIS ||
1515                             val == 0) {
1516                                 (*rate_target_pwr_num) = i;
1517                                 break;
1518                         }
1519
1520                         rate_pcal_info[i].target_power_36 |= ((val >> 13) & 0x7);
1521                         rate_pcal_info[i].target_power_48 = ((val >> 7) & 0x3f);
1522                         rate_pcal_info[i].target_power_54 = ((val >> 1) & 0x3f);
1523                 }
1524         } else {
1525                 for (i = 0; i < (*rate_target_pwr_num); i++) {
1526                         AR5K_EEPROM_READ(offset++, val);
1527                         rate_pcal_info[i].freq =
1528                             ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff, mode);
1529
1530                         rate_pcal_info[i].target_power_6to24 = ((val >> 2) & 0x3f);
1531                         rate_pcal_info[i].target_power_36 = (val << 4) & 0x3f;
1532
1533                         AR5K_EEPROM_READ(offset++, val);
1534
1535                         if (rate_pcal_info[i].freq == AR5K_EEPROM_CHANNEL_DIS ||
1536                             val == 0) {
1537                                 (*rate_target_pwr_num) = i;
1538                                 break;
1539                         }
1540
1541                         rate_pcal_info[i].target_power_36 |= (val >> 12) & 0xf;
1542                         rate_pcal_info[i].target_power_48 = ((val >> 6) & 0x3f);
1543                         rate_pcal_info[i].target_power_54 = (val & 0x3f);
1544                 }
1545         }
1546
1547         return 0;
1548 }
1549
1550
1551 /*
1552  * Read per channel calibration info from EEPROM
1553  *
1554  * This info is used to calibrate the baseband power table. Imagine
1555  * that for each channel there is a power curve that's hw specific
1556  * (depends on amplifier etc) and we try to "correct" this curve using
1557  * offsets we pass on to phy chip (baseband -> before amplifier) so that
1558  * it can use accurate power values when setting tx power (takes amplifier's
1559  * performance on each channel into account).
1560  *
1561  * EEPROM provides us with the offsets for some pre-calibrated channels
1562  * and we have to interpolate to create the full table for these channels and
1563  * also the table for any channel.
1564  */
1565 static int
1566 ath5k_eeprom_read_pcal_info(struct ath5k_hw *ah)
1567 {
1568         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1569         int (*read_pcal)(struct ath5k_hw *hw, int mode);
1570         int mode;
1571         int err;
1572
1573         if ((ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) &&
1574                         (AR5K_EEPROM_EEMAP(ee->ee_misc0) == 1))
1575                 read_pcal = ath5k_eeprom_read_pcal_info_5112;
1576         else if ((ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_0) &&
1577                         (AR5K_EEPROM_EEMAP(ee->ee_misc0) == 2))
1578                 read_pcal = ath5k_eeprom_read_pcal_info_2413;
1579         else
1580                 read_pcal = ath5k_eeprom_read_pcal_info_5111;
1581
1582
1583         for (mode = AR5K_EEPROM_MODE_11A; mode <= AR5K_EEPROM_MODE_11G;
1584         mode++) {
1585                 err = read_pcal(ah, mode);
1586                 if (err)
1587                         return err;
1588
1589                 err = ath5k_eeprom_read_target_rate_pwr_info(ah, mode);
1590                 if (err < 0)
1591                         return err;
1592         }
1593
1594         return 0;
1595 }
1596
1597 /* Read conformance test limits used for regulatory control */
1598 static int
1599 ath5k_eeprom_read_ctl_info(struct ath5k_hw *ah)
1600 {
1601         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1602         struct ath5k_edge_power *rep;
1603         unsigned int fmask, pmask;
1604         unsigned int ctl_mode;
1605         int i, j;
1606         u32 offset;
1607         u16 val;
1608
1609         pmask = AR5K_EEPROM_POWER_M;
1610         fmask = AR5K_EEPROM_FREQ_M(ee->ee_version);
1611         offset = AR5K_EEPROM_CTL(ee->ee_version);
1612         ee->ee_ctls = AR5K_EEPROM_N_CTLS(ee->ee_version);
1613         for (i = 0; i < ee->ee_ctls; i += 2) {
1614                 AR5K_EEPROM_READ(offset++, val);
1615                 ee->ee_ctl[i] = (val >> 8) & 0xff;
1616                 ee->ee_ctl[i + 1] = val & 0xff;
1617         }
1618
1619         offset = AR5K_EEPROM_GROUP8_OFFSET;
1620         if (ee->ee_version >= AR5K_EEPROM_VERSION_4_0)
1621                 offset += AR5K_EEPROM_TARGET_PWRSTART(ee->ee_misc1) -
1622                         AR5K_EEPROM_GROUP5_OFFSET;
1623         else
1624                 offset += AR5K_EEPROM_GROUPS_START(ee->ee_version);
1625
1626         rep = ee->ee_ctl_pwr;
1627         for(i = 0; i < ee->ee_ctls; i++) {
1628                 switch(ee->ee_ctl[i] & AR5K_CTL_MODE_M) {
1629                 case AR5K_CTL_11A:
1630                 case AR5K_CTL_TURBO:
1631                         ctl_mode = AR5K_EEPROM_MODE_11A;
1632                         break;
1633                 default:
1634                         ctl_mode = AR5K_EEPROM_MODE_11G;
1635                         break;
1636                 }
1637                 if (ee->ee_ctl[i] == 0) {
1638                         if (ee->ee_version >= AR5K_EEPROM_VERSION_3_3)
1639                                 offset += 8;
1640                         else
1641                                 offset += 7;
1642                         rep += AR5K_EEPROM_N_EDGES;
1643                         continue;
1644                 }
1645                 if (ee->ee_version >= AR5K_EEPROM_VERSION_3_3) {
1646                         for (j = 0; j < AR5K_EEPROM_N_EDGES; j += 2) {
1647                                 AR5K_EEPROM_READ(offset++, val);
1648                                 rep[j].freq = (val >> 8) & fmask;
1649                                 rep[j + 1].freq = val & fmask;
1650                         }
1651                         for (j = 0; j < AR5K_EEPROM_N_EDGES; j += 2) {
1652                                 AR5K_EEPROM_READ(offset++, val);
1653                                 rep[j].edge = (val >> 8) & pmask;
1654                                 rep[j].flag = (val >> 14) & 1;
1655                                 rep[j + 1].edge = val & pmask;
1656                                 rep[j + 1].flag = (val >> 6) & 1;
1657                         }
1658                 } else {
1659                         AR5K_EEPROM_READ(offset++, val);
1660                         rep[0].freq = (val >> 9) & fmask;
1661                         rep[1].freq = (val >> 2) & fmask;
1662                         rep[2].freq = (val << 5) & fmask;
1663
1664                         AR5K_EEPROM_READ(offset++, val);
1665                         rep[2].freq |= (val >> 11) & 0x1f;
1666                         rep[3].freq = (val >> 4) & fmask;
1667                         rep[4].freq = (val << 3) & fmask;
1668
1669                         AR5K_EEPROM_READ(offset++, val);
1670                         rep[4].freq |= (val >> 13) & 0x7;
1671                         rep[5].freq = (val >> 6) & fmask;
1672                         rep[6].freq = (val << 1) & fmask;
1673
1674                         AR5K_EEPROM_READ(offset++, val);
1675                         rep[6].freq |= (val >> 15) & 0x1;
1676                         rep[7].freq = (val >> 8) & fmask;
1677
1678                         rep[0].edge = (val >> 2) & pmask;
1679                         rep[1].edge = (val << 4) & pmask;
1680
1681                         AR5K_EEPROM_READ(offset++, val);
1682                         rep[1].edge |= (val >> 12) & 0xf;
1683                         rep[2].edge = (val >> 6) & pmask;
1684                         rep[3].edge = val & pmask;
1685
1686                         AR5K_EEPROM_READ(offset++, val);
1687                         rep[4].edge = (val >> 10) & pmask;
1688                         rep[5].edge = (val >> 4) & pmask;
1689                         rep[6].edge = (val << 2) & pmask;
1690
1691                         AR5K_EEPROM_READ(offset++, val);
1692                         rep[6].edge |= (val >> 14) & 0x3;
1693                         rep[7].edge = (val >> 8) & pmask;
1694                 }
1695                 for (j = 0; j < AR5K_EEPROM_N_EDGES; j++) {
1696                         rep[j].freq = ath5k_eeprom_bin2freq(ee,
1697                                 rep[j].freq, ctl_mode);
1698                 }
1699                 rep += AR5K_EEPROM_N_EDGES;
1700         }
1701
1702         return 0;
1703 }
1704
1705 static int
1706 ath5k_eeprom_read_spur_chans(struct ath5k_hw *ah)
1707 {
1708         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1709         u32 offset;
1710         u16 val;
1711         int ret = 0, i;
1712
1713         offset = AR5K_EEPROM_CTL(ee->ee_version) +
1714                                 AR5K_EEPROM_N_CTLS(ee->ee_version);
1715
1716         if (ee->ee_version < AR5K_EEPROM_VERSION_5_3) {
1717                 /* No spur info for 5GHz */
1718                 ee->ee_spur_chans[0][0] = AR5K_EEPROM_NO_SPUR;
1719                 /* 2 channels for 2GHz (2464/2420) */
1720                 ee->ee_spur_chans[0][1] = AR5K_EEPROM_5413_SPUR_CHAN_1;
1721                 ee->ee_spur_chans[1][1] = AR5K_EEPROM_5413_SPUR_CHAN_2;
1722                 ee->ee_spur_chans[2][1] = AR5K_EEPROM_NO_SPUR;
1723         } else if (ee->ee_version >= AR5K_EEPROM_VERSION_5_3) {
1724                 for (i = 0; i < AR5K_EEPROM_N_SPUR_CHANS; i++) {
1725                         AR5K_EEPROM_READ(offset, val);
1726                         ee->ee_spur_chans[i][0] = val;
1727                         AR5K_EEPROM_READ(offset + AR5K_EEPROM_N_SPUR_CHANS,
1728                                                                         val);
1729                         ee->ee_spur_chans[i][1] = val;
1730                         offset++;
1731                 }
1732         }
1733
1734         return ret;
1735 }
1736
1737
1738 /***********************\
1739 * Init/Detach functions *
1740 \***********************/
1741
1742 /*
1743  * Initialize eeprom data structure
1744  */
1745 int
1746 ath5k_eeprom_init(struct ath5k_hw *ah)
1747 {
1748         int err;
1749
1750         err = ath5k_eeprom_init_header(ah);
1751         if (err < 0)
1752                 return err;
1753
1754         err = ath5k_eeprom_init_modes(ah);
1755         if (err < 0)
1756                 return err;
1757
1758         err = ath5k_eeprom_read_pcal_info(ah);
1759         if (err < 0)
1760                 return err;
1761
1762         err = ath5k_eeprom_read_ctl_info(ah);
1763         if (err < 0)
1764                 return err;
1765
1766         err = ath5k_eeprom_read_spur_chans(ah);
1767         if (err < 0)
1768                 return err;
1769
1770         return 0;
1771 }
1772
1773 void
1774 ath5k_eeprom_detach(struct ath5k_hw *ah)
1775 {
1776         u8 mode;
1777
1778         for (mode = AR5K_EEPROM_MODE_11A; mode <= AR5K_EEPROM_MODE_11G; mode++)
1779                 ath5k_eeprom_free_pcal_info(ah, mode);
1780 }
1781
1782 int
1783 ath5k_eeprom_mode_from_channel(struct ieee80211_channel *channel)
1784 {
1785         switch (channel->hw_value & CHANNEL_MODES) {
1786         case CHANNEL_A:
1787         case CHANNEL_XR:
1788                 return AR5K_EEPROM_MODE_11A;
1789         case CHANNEL_G:
1790                 return AR5K_EEPROM_MODE_11G;
1791         case CHANNEL_B:
1792                 return AR5K_EEPROM_MODE_11B;
1793         default:
1794                 return -1;
1795         }
1796 }