2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
43 #include <linux/module.h>
44 #include <linux/delay.h>
45 #include <linux/dma-mapping.h>
46 #include <linux/hardirq.h>
49 #include <linux/netdevice.h>
50 #include <linux/cache.h>
51 #include <linux/ethtool.h>
52 #include <linux/uaccess.h>
53 #include <linux/slab.h>
54 #include <linux/etherdevice.h>
56 #include <net/ieee80211_radiotap.h>
58 #include <asm/unaligned.h>
65 #define CREATE_TRACE_POINTS
68 int ath5k_modparam_nohwcrypt;
69 module_param_named(nohwcrypt, ath5k_modparam_nohwcrypt, bool, S_IRUGO);
70 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
72 static int modparam_all_channels;
73 module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO);
74 MODULE_PARM_DESC(all_channels, "Expose all channels the device can use.");
76 static int modparam_fastchanswitch;
77 module_param_named(fastchanswitch, modparam_fastchanswitch, bool, S_IRUGO);
78 MODULE_PARM_DESC(fastchanswitch, "Enable fast channel switching for AR2413/AR5413 radios.");
82 MODULE_AUTHOR("Jiri Slaby");
83 MODULE_AUTHOR("Nick Kossifidis");
84 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
85 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
86 MODULE_LICENSE("Dual BSD/GPL");
88 static int ath5k_init(struct ieee80211_hw *hw);
89 static int ath5k_reset(struct ath5k_hw *ah, struct ieee80211_channel *chan,
93 static const struct ath5k_srev_name srev_names[] = {
94 #ifdef CONFIG_ATHEROS_AR231X
95 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R2 },
96 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R7 },
97 { "2313", AR5K_VERSION_MAC, AR5K_SREV_AR2313_R8 },
98 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R6 },
99 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R7 },
100 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R1 },
101 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R2 },
103 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
104 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
105 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
106 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
107 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
108 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
109 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
110 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
111 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
112 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
113 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
114 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
115 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
116 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
117 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
118 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
119 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
120 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
122 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
123 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
124 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
125 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
126 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
127 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
128 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
129 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
130 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
131 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
132 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
133 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
134 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
135 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
136 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
137 #ifdef CONFIG_ATHEROS_AR231X
138 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
139 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
141 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
144 static const struct ieee80211_rate ath5k_rates[] = {
146 .hw_value = ATH5K_RATE_CODE_1M, },
148 .hw_value = ATH5K_RATE_CODE_2M,
149 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
150 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
152 .hw_value = ATH5K_RATE_CODE_5_5M,
153 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
154 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
156 .hw_value = ATH5K_RATE_CODE_11M,
157 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
158 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
160 .hw_value = ATH5K_RATE_CODE_6M,
163 .hw_value = ATH5K_RATE_CODE_9M,
166 .hw_value = ATH5K_RATE_CODE_12M,
169 .hw_value = ATH5K_RATE_CODE_18M,
172 .hw_value = ATH5K_RATE_CODE_24M,
175 .hw_value = ATH5K_RATE_CODE_36M,
178 .hw_value = ATH5K_RATE_CODE_48M,
181 .hw_value = ATH5K_RATE_CODE_54M,
186 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
188 u64 tsf = ath5k_hw_get_tsf64(ah);
190 if ((tsf & 0x7fff) < rstamp)
193 return (tsf & ~0x7fff) | rstamp;
197 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
199 const char *name = "xxxxx";
202 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
203 if (srev_names[i].sr_type != type)
206 if ((val & 0xf0) == srev_names[i].sr_val)
207 name = srev_names[i].sr_name;
209 if ((val & 0xff) == srev_names[i].sr_val) {
210 name = srev_names[i].sr_name;
217 static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset)
219 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
220 return ath5k_hw_reg_read(ah, reg_offset);
223 static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
225 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
226 ath5k_hw_reg_write(ah, val, reg_offset);
229 static const struct ath_ops ath5k_common_ops = {
230 .read = ath5k_ioread32,
231 .write = ath5k_iowrite32,
234 /***********************\
235 * Driver Initialization *
236 \***********************/
238 static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
240 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
241 struct ath5k_hw *ah = hw->priv;
242 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
244 return ath_reg_notifier_apply(wiphy, request, regulatory);
247 /********************\
248 * Channel/mode setup *
249 \********************/
252 * Returns true for the channel numbers used without all_channels modparam.
254 static bool ath5k_is_standard_channel(short chan, enum ieee80211_band band)
256 if (band == IEEE80211_BAND_2GHZ && chan <= 14)
259 return /* UNII 1,2 */
260 (((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
262 ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
264 ((chan & 3) == 1 && chan >= 149 && chan <= 165) ||
265 /* 802.11j 5.030-5.080 GHz (20MHz) */
266 (chan == 8 || chan == 12 || chan == 16) ||
267 /* 802.11j 4.9GHz (20MHz) */
268 (chan == 184 || chan == 188 || chan == 192 || chan == 196));
272 ath5k_setup_channels(struct ath5k_hw *ah, struct ieee80211_channel *channels,
273 unsigned int mode, unsigned int max)
275 unsigned int count, size, chfreq, freq, ch;
276 enum ieee80211_band band;
280 /* 1..220, but 2GHz frequencies are filtered by check_channel */
282 chfreq = CHANNEL_5GHZ;
283 band = IEEE80211_BAND_5GHZ;
288 chfreq = CHANNEL_2GHZ;
289 band = IEEE80211_BAND_2GHZ;
292 ATH5K_WARN(ah, "bad mode, not copying channels\n");
297 for (ch = 1; ch <= size && count < max; ch++) {
298 freq = ieee80211_channel_to_frequency(ch, band);
300 if (freq == 0) /* mapping failed - not a standard channel */
303 /* Check if channel is supported by the chipset */
304 if (!ath5k_channel_ok(ah, freq, chfreq))
307 if (!modparam_all_channels &&
308 !ath5k_is_standard_channel(ch, band))
311 /* Write channel info and increment counter */
312 channels[count].center_freq = freq;
313 channels[count].band = band;
317 channels[count].hw_value = chfreq | CHANNEL_OFDM;
320 channels[count].hw_value = CHANNEL_B;
330 ath5k_setup_rate_idx(struct ath5k_hw *ah, struct ieee80211_supported_band *b)
334 for (i = 0; i < AR5K_MAX_RATES; i++)
335 ah->rate_idx[b->band][i] = -1;
337 for (i = 0; i < b->n_bitrates; i++) {
338 ah->rate_idx[b->band][b->bitrates[i].hw_value] = i;
339 if (b->bitrates[i].hw_value_short)
340 ah->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
345 ath5k_setup_bands(struct ieee80211_hw *hw)
347 struct ath5k_hw *ah = hw->priv;
348 struct ieee80211_supported_band *sband;
349 int max_c, count_c = 0;
352 BUILD_BUG_ON(ARRAY_SIZE(ah->sbands) < IEEE80211_NUM_BANDS);
353 max_c = ARRAY_SIZE(ah->channels);
356 sband = &ah->sbands[IEEE80211_BAND_2GHZ];
357 sband->band = IEEE80211_BAND_2GHZ;
358 sband->bitrates = &ah->rates[IEEE80211_BAND_2GHZ][0];
360 if (test_bit(AR5K_MODE_11G, ah->ah_capabilities.cap_mode)) {
362 memcpy(sband->bitrates, &ath5k_rates[0],
363 sizeof(struct ieee80211_rate) * 12);
364 sband->n_bitrates = 12;
366 sband->channels = ah->channels;
367 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
368 AR5K_MODE_11G, max_c);
370 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
371 count_c = sband->n_channels;
373 } else if (test_bit(AR5K_MODE_11B, ah->ah_capabilities.cap_mode)) {
375 memcpy(sband->bitrates, &ath5k_rates[0],
376 sizeof(struct ieee80211_rate) * 4);
377 sband->n_bitrates = 4;
379 /* 5211 only supports B rates and uses 4bit rate codes
380 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
383 if (ah->ah_version == AR5K_AR5211) {
384 for (i = 0; i < 4; i++) {
385 sband->bitrates[i].hw_value =
386 sband->bitrates[i].hw_value & 0xF;
387 sband->bitrates[i].hw_value_short =
388 sband->bitrates[i].hw_value_short & 0xF;
392 sband->channels = ah->channels;
393 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
394 AR5K_MODE_11B, max_c);
396 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
397 count_c = sband->n_channels;
400 ath5k_setup_rate_idx(ah, sband);
402 /* 5GHz band, A mode */
403 if (test_bit(AR5K_MODE_11A, ah->ah_capabilities.cap_mode)) {
404 sband = &ah->sbands[IEEE80211_BAND_5GHZ];
405 sband->band = IEEE80211_BAND_5GHZ;
406 sband->bitrates = &ah->rates[IEEE80211_BAND_5GHZ][0];
408 memcpy(sband->bitrates, &ath5k_rates[4],
409 sizeof(struct ieee80211_rate) * 8);
410 sband->n_bitrates = 8;
412 sband->channels = &ah->channels[count_c];
413 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
414 AR5K_MODE_11A, max_c);
416 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
418 ath5k_setup_rate_idx(ah, sband);
420 ath5k_debug_dump_bands(ah);
426 * Set/change channels. We always reset the chip.
427 * To accomplish this we must first cleanup any pending DMA,
428 * then restart stuff after a la ath5k_init.
430 * Called with ah->lock.
433 ath5k_chan_set(struct ath5k_hw *ah, struct ieee80211_channel *chan)
435 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
436 "channel set, resetting (%u -> %u MHz)\n",
437 ah->curchan->center_freq, chan->center_freq);
440 * To switch channels clear any pending DMA operations;
441 * wait long enough for the RX fifo to drain, reset the
442 * hardware at the new frequency, and then re-enable
443 * the relevant bits of the h/w.
445 return ath5k_reset(ah, chan, true);
448 void ath5k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
450 struct ath5k_vif_iter_data *iter_data = data;
452 struct ath5k_vif *avf = (void *)vif->drv_priv;
454 if (iter_data->hw_macaddr)
455 for (i = 0; i < ETH_ALEN; i++)
456 iter_data->mask[i] &=
457 ~(iter_data->hw_macaddr[i] ^ mac[i]);
459 if (!iter_data->found_active) {
460 iter_data->found_active = true;
461 memcpy(iter_data->active_mac, mac, ETH_ALEN);
464 if (iter_data->need_set_hw_addr && iter_data->hw_macaddr)
465 if (compare_ether_addr(iter_data->hw_macaddr, mac) == 0)
466 iter_data->need_set_hw_addr = false;
468 if (!iter_data->any_assoc) {
470 iter_data->any_assoc = true;
473 /* Calculate combined mode - when APs are active, operate in AP mode.
474 * Otherwise use the mode of the new interface. This can currently
475 * only deal with combinations of APs and STAs. Only one ad-hoc
476 * interfaces is allowed.
478 if (avf->opmode == NL80211_IFTYPE_AP)
479 iter_data->opmode = NL80211_IFTYPE_AP;
481 if (avf->opmode == NL80211_IFTYPE_STATION)
483 if (iter_data->opmode == NL80211_IFTYPE_UNSPECIFIED)
484 iter_data->opmode = avf->opmode;
489 ath5k_update_bssid_mask_and_opmode(struct ath5k_hw *ah,
490 struct ieee80211_vif *vif)
492 struct ath_common *common = ath5k_hw_common(ah);
493 struct ath5k_vif_iter_data iter_data;
497 * Use the hardware MAC address as reference, the hardware uses it
498 * together with the BSSID mask when matching addresses.
500 iter_data.hw_macaddr = common->macaddr;
501 memset(&iter_data.mask, 0xff, ETH_ALEN);
502 iter_data.found_active = false;
503 iter_data.need_set_hw_addr = true;
504 iter_data.opmode = NL80211_IFTYPE_UNSPECIFIED;
505 iter_data.n_stas = 0;
508 ath5k_vif_iter(&iter_data, vif->addr, vif);
510 /* Get list of all active MAC addresses */
511 ieee80211_iterate_active_interfaces_atomic(ah->hw, ath5k_vif_iter,
513 memcpy(ah->bssidmask, iter_data.mask, ETH_ALEN);
515 ah->opmode = iter_data.opmode;
516 if (ah->opmode == NL80211_IFTYPE_UNSPECIFIED)
517 /* Nothing active, default to station mode */
518 ah->opmode = NL80211_IFTYPE_STATION;
520 ath5k_hw_set_opmode(ah, ah->opmode);
521 ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "mode setup opmode %d (%s)\n",
522 ah->opmode, ath_opmode_to_string(ah->opmode));
524 if (iter_data.need_set_hw_addr && iter_data.found_active)
525 ath5k_hw_set_lladdr(ah, iter_data.active_mac);
527 if (ath5k_hw_hasbssidmask(ah))
528 ath5k_hw_set_bssid_mask(ah, ah->bssidmask);
530 /* Set up RX Filter */
531 if (iter_data.n_stas > 1) {
532 /* If you have multiple STA interfaces connected to
533 * different APs, ARPs are not received (most of the time?)
534 * Enabling PROMISC appears to fix that problem.
536 ah->filter_flags |= AR5K_RX_FILTER_PROM;
539 rfilt = ah->filter_flags;
540 ath5k_hw_set_rx_filter(ah, rfilt);
541 ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
545 ath5k_hw_to_driver_rix(struct ath5k_hw *ah, int hw_rix)
549 /* return base rate on errors */
550 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
551 "hw_rix out of bounds: %x\n", hw_rix))
554 rix = ah->rate_idx[ah->curchan->band][hw_rix];
555 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
566 struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_hw *ah, dma_addr_t *skb_addr)
568 struct ath_common *common = ath5k_hw_common(ah);
572 * Allocate buffer with headroom_needed space for the
573 * fake physical layer header at the start.
575 skb = ath_rxbuf_alloc(common,
580 ATH5K_ERR(ah, "can't alloc skbuff of size %u\n",
585 *skb_addr = dma_map_single(ah->dev,
586 skb->data, common->rx_bufsize,
589 if (unlikely(dma_mapping_error(ah->dev, *skb_addr))) {
590 ATH5K_ERR(ah, "%s: DMA mapping failed\n", __func__);
598 ath5k_rxbuf_setup(struct ath5k_hw *ah, struct ath5k_buf *bf)
600 struct sk_buff *skb = bf->skb;
601 struct ath5k_desc *ds;
605 skb = ath5k_rx_skb_alloc(ah, &bf->skbaddr);
612 * Setup descriptors. For receive we always terminate
613 * the descriptor list with a self-linked entry so we'll
614 * not get overrun under high load (as can happen with a
615 * 5212 when ANI processing enables PHY error frames).
617 * To ensure the last descriptor is self-linked we create
618 * each descriptor as self-linked and add it to the end. As
619 * each additional descriptor is added the previous self-linked
620 * entry is "fixed" naturally. This should be safe even
621 * if DMA is happening. When processing RX interrupts we
622 * never remove/process the last, self-linked, entry on the
623 * descriptor list. This ensures the hardware always has
624 * someplace to write a new frame.
627 ds->ds_link = bf->daddr; /* link to self */
628 ds->ds_data = bf->skbaddr;
629 ret = ath5k_hw_setup_rx_desc(ah, ds, ah->common.rx_bufsize, 0);
631 ATH5K_ERR(ah, "%s: could not setup RX desc\n", __func__);
635 if (ah->rxlink != NULL)
636 *ah->rxlink = bf->daddr;
637 ah->rxlink = &ds->ds_link;
641 static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb)
643 struct ieee80211_hdr *hdr;
644 enum ath5k_pkt_type htype;
647 hdr = (struct ieee80211_hdr *)skb->data;
648 fc = hdr->frame_control;
650 if (ieee80211_is_beacon(fc))
651 htype = AR5K_PKT_TYPE_BEACON;
652 else if (ieee80211_is_probe_resp(fc))
653 htype = AR5K_PKT_TYPE_PROBE_RESP;
654 else if (ieee80211_is_atim(fc))
655 htype = AR5K_PKT_TYPE_ATIM;
656 else if (ieee80211_is_pspoll(fc))
657 htype = AR5K_PKT_TYPE_PSPOLL;
659 htype = AR5K_PKT_TYPE_NORMAL;
665 ath5k_txbuf_setup(struct ath5k_hw *ah, struct ath5k_buf *bf,
666 struct ath5k_txq *txq, int padsize)
668 struct ath5k_desc *ds = bf->desc;
669 struct sk_buff *skb = bf->skb;
670 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
671 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
672 struct ieee80211_rate *rate;
673 unsigned int mrr_rate[3], mrr_tries[3];
680 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
683 bf->skbaddr = dma_map_single(ah->dev, skb->data, skb->len,
686 rate = ieee80211_get_tx_rate(ah->hw, info);
692 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
693 flags |= AR5K_TXDESC_NOACK;
695 rc_flags = info->control.rates[0].flags;
696 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
697 rate->hw_value_short : rate->hw_value;
701 /* FIXME: If we are in g mode and rate is a CCK rate
702 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
703 * from tx power (value is in dB units already) */
704 if (info->control.hw_key) {
705 keyidx = info->control.hw_key->hw_key_idx;
706 pktlen += info->control.hw_key->icv_len;
708 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
709 flags |= AR5K_TXDESC_RTSENA;
710 cts_rate = ieee80211_get_rts_cts_rate(ah->hw, info)->hw_value;
711 duration = le16_to_cpu(ieee80211_rts_duration(ah->hw,
712 info->control.vif, pktlen, info));
714 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
715 flags |= AR5K_TXDESC_CTSENA;
716 cts_rate = ieee80211_get_rts_cts_rate(ah->hw, info)->hw_value;
717 duration = le16_to_cpu(ieee80211_ctstoself_duration(ah->hw,
718 info->control.vif, pktlen, info));
720 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
721 ieee80211_get_hdrlen_from_skb(skb), padsize,
722 get_hw_packet_type(skb),
723 (ah->power_level * 2),
725 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags,
730 memset(mrr_rate, 0, sizeof(mrr_rate));
731 memset(mrr_tries, 0, sizeof(mrr_tries));
732 for (i = 0; i < 3; i++) {
733 rate = ieee80211_get_alt_retry_rate(ah->hw, info, i);
737 mrr_rate[i] = rate->hw_value;
738 mrr_tries[i] = info->control.rates[i + 1].count;
741 ath5k_hw_setup_mrr_tx_desc(ah, ds,
742 mrr_rate[0], mrr_tries[0],
743 mrr_rate[1], mrr_tries[1],
744 mrr_rate[2], mrr_tries[2]);
747 ds->ds_data = bf->skbaddr;
749 spin_lock_bh(&txq->lock);
750 list_add_tail(&bf->list, &txq->q);
752 if (txq->link == NULL) /* is this first packet? */
753 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
754 else /* no, so only link it */
755 *txq->link = bf->daddr;
757 txq->link = &ds->ds_link;
758 ath5k_hw_start_tx_dma(ah, txq->qnum);
760 spin_unlock_bh(&txq->lock);
764 dma_unmap_single(ah->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
768 /*******************\
769 * Descriptors setup *
770 \*******************/
773 ath5k_desc_alloc(struct ath5k_hw *ah)
775 struct ath5k_desc *ds;
776 struct ath5k_buf *bf;
781 /* allocate descriptors */
782 ah->desc_len = sizeof(struct ath5k_desc) *
783 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
785 ah->desc = dma_alloc_coherent(ah->dev, ah->desc_len,
786 &ah->desc_daddr, GFP_KERNEL);
787 if (ah->desc == NULL) {
788 ATH5K_ERR(ah, "can't allocate descriptors\n");
794 ATH5K_DBG(ah, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
795 ds, ah->desc_len, (unsigned long long)ah->desc_daddr);
797 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
798 sizeof(struct ath5k_buf), GFP_KERNEL);
800 ATH5K_ERR(ah, "can't allocate bufptr\n");
806 INIT_LIST_HEAD(&ah->rxbuf);
807 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
810 list_add_tail(&bf->list, &ah->rxbuf);
813 INIT_LIST_HEAD(&ah->txbuf);
814 ah->txbuf_len = ATH_TXBUF;
815 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
818 list_add_tail(&bf->list, &ah->txbuf);
822 INIT_LIST_HEAD(&ah->bcbuf);
823 for (i = 0; i < ATH_BCBUF; i++, bf++, ds++, da += sizeof(*ds)) {
826 list_add_tail(&bf->list, &ah->bcbuf);
831 dma_free_coherent(ah->dev, ah->desc_len, ah->desc, ah->desc_daddr);
838 ath5k_txbuf_free_skb(struct ath5k_hw *ah, struct ath5k_buf *bf)
843 dma_unmap_single(ah->dev, bf->skbaddr, bf->skb->len,
845 dev_kfree_skb_any(bf->skb);
848 bf->desc->ds_data = 0;
852 ath5k_rxbuf_free_skb(struct ath5k_hw *ah, struct ath5k_buf *bf)
854 struct ath_common *common = ath5k_hw_common(ah);
859 dma_unmap_single(ah->dev, bf->skbaddr, common->rx_bufsize,
861 dev_kfree_skb_any(bf->skb);
864 bf->desc->ds_data = 0;
868 ath5k_desc_free(struct ath5k_hw *ah)
870 struct ath5k_buf *bf;
872 list_for_each_entry(bf, &ah->txbuf, list)
873 ath5k_txbuf_free_skb(ah, bf);
874 list_for_each_entry(bf, &ah->rxbuf, list)
875 ath5k_rxbuf_free_skb(ah, bf);
876 list_for_each_entry(bf, &ah->bcbuf, list)
877 ath5k_txbuf_free_skb(ah, bf);
879 /* Free memory associated with all descriptors */
880 dma_free_coherent(ah->dev, ah->desc_len, ah->desc, ah->desc_daddr);
893 static struct ath5k_txq *
894 ath5k_txq_setup(struct ath5k_hw *ah,
895 int qtype, int subtype)
897 struct ath5k_txq *txq;
898 struct ath5k_txq_info qi = {
899 .tqi_subtype = subtype,
900 /* XXX: default values not correct for B and XR channels,
902 .tqi_aifs = AR5K_TUNE_AIFS,
903 .tqi_cw_min = AR5K_TUNE_CWMIN,
904 .tqi_cw_max = AR5K_TUNE_CWMAX
909 * Enable interrupts only for EOL and DESC conditions.
910 * We mark tx descriptors to receive a DESC interrupt
911 * when a tx queue gets deep; otherwise we wait for the
912 * EOL to reap descriptors. Note that this is done to
913 * reduce interrupt load and this only defers reaping
914 * descriptors, never transmitting frames. Aside from
915 * reducing interrupts this also permits more concurrency.
916 * The only potential downside is if the tx queue backs
917 * up in which case the top half of the kernel may backup
918 * due to a lack of tx descriptors.
920 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
921 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
922 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
925 * NB: don't print a message, this happens
926 * normally on parts with too few tx queues
928 return ERR_PTR(qnum);
930 if (qnum >= ARRAY_SIZE(ah->txqs)) {
931 ATH5K_ERR(ah, "hw qnum %u out of range, max %tu!\n",
932 qnum, ARRAY_SIZE(ah->txqs));
933 ath5k_hw_release_tx_queue(ah, qnum);
934 return ERR_PTR(-EINVAL);
936 txq = &ah->txqs[qnum];
940 INIT_LIST_HEAD(&txq->q);
941 spin_lock_init(&txq->lock);
944 txq->txq_max = ATH5K_TXQ_LEN_MAX;
945 txq->txq_poll_mark = false;
948 return &ah->txqs[qnum];
952 ath5k_beaconq_setup(struct ath5k_hw *ah)
954 struct ath5k_txq_info qi = {
955 /* XXX: default values not correct for B and XR channels,
957 .tqi_aifs = AR5K_TUNE_AIFS,
958 .tqi_cw_min = AR5K_TUNE_CWMIN,
959 .tqi_cw_max = AR5K_TUNE_CWMAX,
960 /* NB: for dynamic turbo, don't enable any other interrupts */
961 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
964 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
968 ath5k_beaconq_config(struct ath5k_hw *ah)
970 struct ath5k_txq_info qi;
973 ret = ath5k_hw_get_tx_queueprops(ah, ah->bhalq, &qi);
977 if (ah->opmode == NL80211_IFTYPE_AP ||
978 ah->opmode == NL80211_IFTYPE_MESH_POINT) {
980 * Always burst out beacon and CAB traffic
981 * (aifs = cwmin = cwmax = 0)
986 } else if (ah->opmode == NL80211_IFTYPE_ADHOC) {
988 * Adhoc mode; backoff between 0 and (2 * cw_min).
992 qi.tqi_cw_max = 2 * AR5K_TUNE_CWMIN;
995 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
996 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
997 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
999 ret = ath5k_hw_set_tx_queueprops(ah, ah->bhalq, &qi);
1001 ATH5K_ERR(ah, "%s: unable to update parameters for beacon "
1002 "hardware queue!\n", __func__);
1005 ret = ath5k_hw_reset_tx_queue(ah, ah->bhalq); /* push to h/w */
1009 /* reconfigure cabq with ready time to 80% of beacon_interval */
1010 ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1014 qi.tqi_ready_time = (ah->bintval * 80) / 100;
1015 ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1019 ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB);
1025 * ath5k_drain_tx_buffs - Empty tx buffers
1027 * @ah The &struct ath5k_hw
1029 * Empty tx buffers from all queues in preparation
1030 * of a reset or during shutdown.
1032 * NB: this assumes output has been stopped and
1033 * we do not need to block ath5k_tx_tasklet
1036 ath5k_drain_tx_buffs(struct ath5k_hw *ah)
1038 struct ath5k_txq *txq;
1039 struct ath5k_buf *bf, *bf0;
1042 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++) {
1043 if (ah->txqs[i].setup) {
1045 spin_lock_bh(&txq->lock);
1046 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1047 ath5k_debug_printtxbuf(ah, bf);
1049 ath5k_txbuf_free_skb(ah, bf);
1051 spin_lock_bh(&ah->txbuflock);
1052 list_move_tail(&bf->list, &ah->txbuf);
1055 spin_unlock_bh(&ah->txbuflock);
1058 txq->txq_poll_mark = false;
1059 spin_unlock_bh(&txq->lock);
1065 ath5k_txq_release(struct ath5k_hw *ah)
1067 struct ath5k_txq *txq = ah->txqs;
1070 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++, txq++)
1072 ath5k_hw_release_tx_queue(ah, txq->qnum);
1083 * Enable the receive h/w following a reset.
1086 ath5k_rx_start(struct ath5k_hw *ah)
1088 struct ath_common *common = ath5k_hw_common(ah);
1089 struct ath5k_buf *bf;
1092 common->rx_bufsize = roundup(IEEE80211_MAX_FRAME_LEN, common->cachelsz);
1094 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n",
1095 common->cachelsz, common->rx_bufsize);
1097 spin_lock_bh(&ah->rxbuflock);
1099 list_for_each_entry(bf, &ah->rxbuf, list) {
1100 ret = ath5k_rxbuf_setup(ah, bf);
1102 spin_unlock_bh(&ah->rxbuflock);
1106 bf = list_first_entry(&ah->rxbuf, struct ath5k_buf, list);
1107 ath5k_hw_set_rxdp(ah, bf->daddr);
1108 spin_unlock_bh(&ah->rxbuflock);
1110 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
1111 ath5k_update_bssid_mask_and_opmode(ah, NULL); /* set filters, etc. */
1112 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1120 * Disable the receive logic on PCU (DRU)
1121 * In preparation for a shutdown.
1123 * Note: Doesn't stop rx DMA, ath5k_hw_dma_stop
1127 ath5k_rx_stop(struct ath5k_hw *ah)
1130 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1131 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
1133 ath5k_debug_printrxbuffs(ah);
1137 ath5k_rx_decrypted(struct ath5k_hw *ah, struct sk_buff *skb,
1138 struct ath5k_rx_status *rs)
1140 struct ath_common *common = ath5k_hw_common(ah);
1141 struct ieee80211_hdr *hdr = (void *)skb->data;
1142 unsigned int keyix, hlen;
1144 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1145 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1146 return RX_FLAG_DECRYPTED;
1148 /* Apparently when a default key is used to decrypt the packet
1149 the hw does not set the index used to decrypt. In such cases
1150 get the index from the packet. */
1151 hlen = ieee80211_hdrlen(hdr->frame_control);
1152 if (ieee80211_has_protected(hdr->frame_control) &&
1153 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1154 skb->len >= hlen + 4) {
1155 keyix = skb->data[hlen + 3] >> 6;
1157 if (test_bit(keyix, common->keymap))
1158 return RX_FLAG_DECRYPTED;
1166 ath5k_check_ibss_tsf(struct ath5k_hw *ah, struct sk_buff *skb,
1167 struct ieee80211_rx_status *rxs)
1169 struct ath_common *common = ath5k_hw_common(ah);
1172 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1174 if (ieee80211_is_beacon(mgmt->frame_control) &&
1175 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1176 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) == 0) {
1178 * Received an IBSS beacon with the same BSSID. Hardware *must*
1179 * have updated the local TSF. We have to work around various
1180 * hardware bugs, though...
1182 tsf = ath5k_hw_get_tsf64(ah);
1183 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1184 hw_tu = TSF_TO_TU(tsf);
1186 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
1187 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1188 (unsigned long long)bc_tstamp,
1189 (unsigned long long)rxs->mactime,
1190 (unsigned long long)(rxs->mactime - bc_tstamp),
1191 (unsigned long long)tsf);
1194 * Sometimes the HW will give us a wrong tstamp in the rx
1195 * status, causing the timestamp extension to go wrong.
1196 * (This seems to happen especially with beacon frames bigger
1197 * than 78 byte (incl. FCS))
1198 * But we know that the receive timestamp must be later than the
1199 * timestamp of the beacon since HW must have synced to that.
1201 * NOTE: here we assume mactime to be after the frame was
1202 * received, not like mac80211 which defines it at the start.
1204 if (bc_tstamp > rxs->mactime) {
1205 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
1206 "fixing mactime from %llx to %llx\n",
1207 (unsigned long long)rxs->mactime,
1208 (unsigned long long)tsf);
1213 * Local TSF might have moved higher than our beacon timers,
1214 * in that case we have to update them to continue sending
1215 * beacons. This also takes care of synchronizing beacon sending
1216 * times with other stations.
1218 if (hw_tu >= ah->nexttbtt)
1219 ath5k_beacon_update_timers(ah, bc_tstamp);
1221 /* Check if the beacon timers are still correct, because a TSF
1222 * update might have created a window between them - for a
1223 * longer description see the comment of this function: */
1224 if (!ath5k_hw_check_beacon_timers(ah, ah->bintval)) {
1225 ath5k_beacon_update_timers(ah, bc_tstamp);
1226 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
1227 "fixed beacon timers after beacon receive\n");
1233 ath5k_update_beacon_rssi(struct ath5k_hw *ah, struct sk_buff *skb, int rssi)
1235 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1236 struct ath_common *common = ath5k_hw_common(ah);
1238 /* only beacons from our BSSID */
1239 if (!ieee80211_is_beacon(mgmt->frame_control) ||
1240 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) != 0)
1243 ewma_add(&ah->ah_beacon_rssi_avg, rssi);
1245 /* in IBSS mode we should keep RSSI statistics per neighbour */
1246 /* le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS */
1250 * Compute padding position. skb must contain an IEEE 802.11 frame
1252 static int ath5k_common_padpos(struct sk_buff *skb)
1254 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1255 __le16 frame_control = hdr->frame_control;
1258 if (ieee80211_has_a4(frame_control))
1261 if (ieee80211_is_data_qos(frame_control))
1262 padpos += IEEE80211_QOS_CTL_LEN;
1268 * This function expects an 802.11 frame and returns the number of
1269 * bytes added, or -1 if we don't have enough header room.
1271 static int ath5k_add_padding(struct sk_buff *skb)
1273 int padpos = ath5k_common_padpos(skb);
1274 int padsize = padpos & 3;
1276 if (padsize && skb->len > padpos) {
1278 if (skb_headroom(skb) < padsize)
1281 skb_push(skb, padsize);
1282 memmove(skb->data, skb->data + padsize, padpos);
1290 * The MAC header is padded to have 32-bit boundary if the
1291 * packet payload is non-zero. The general calculation for
1292 * padsize would take into account odd header lengths:
1293 * padsize = 4 - (hdrlen & 3); however, since only
1294 * even-length headers are used, padding can only be 0 or 2
1295 * bytes and we can optimize this a bit. We must not try to
1296 * remove padding from short control frames that do not have a
1299 * This function expects an 802.11 frame and returns the number of
1302 static int ath5k_remove_padding(struct sk_buff *skb)
1304 int padpos = ath5k_common_padpos(skb);
1305 int padsize = padpos & 3;
1307 if (padsize && skb->len >= padpos + padsize) {
1308 memmove(skb->data + padsize, skb->data, padpos);
1309 skb_pull(skb, padsize);
1317 ath5k_receive_frame(struct ath5k_hw *ah, struct sk_buff *skb,
1318 struct ath5k_rx_status *rs)
1320 struct ieee80211_rx_status *rxs;
1322 ath5k_remove_padding(skb);
1324 rxs = IEEE80211_SKB_RXCB(skb);
1327 if (unlikely(rs->rs_status & AR5K_RXERR_MIC))
1328 rxs->flag |= RX_FLAG_MMIC_ERROR;
1331 * always extend the mac timestamp, since this information is
1332 * also needed for proper IBSS merging.
1334 * XXX: it might be too late to do it here, since rs_tstamp is
1335 * 15bit only. that means TSF extension has to be done within
1336 * 32768usec (about 32ms). it might be necessary to move this to
1337 * the interrupt handler, like it is done in madwifi.
1339 * Unfortunately we don't know when the hardware takes the rx
1340 * timestamp (beginning of phy frame, data frame, end of rx?).
1341 * The only thing we know is that it is hardware specific...
1342 * On AR5213 it seems the rx timestamp is at the end of the
1343 * frame, but I'm not sure.
1345 * NOTE: mac80211 defines mactime at the beginning of the first
1346 * data symbol. Since we don't have any time references it's
1347 * impossible to comply to that. This affects IBSS merge only
1348 * right now, so it's not too bad...
1350 rxs->mactime = ath5k_extend_tsf(ah, rs->rs_tstamp);
1351 rxs->flag |= RX_FLAG_MACTIME_MPDU;
1353 rxs->freq = ah->curchan->center_freq;
1354 rxs->band = ah->curchan->band;
1356 rxs->signal = ah->ah_noise_floor + rs->rs_rssi;
1358 rxs->antenna = rs->rs_antenna;
1360 if (rs->rs_antenna > 0 && rs->rs_antenna < 5)
1361 ah->stats.antenna_rx[rs->rs_antenna]++;
1363 ah->stats.antenna_rx[0]++; /* invalid */
1365 rxs->rate_idx = ath5k_hw_to_driver_rix(ah, rs->rs_rate);
1366 rxs->flag |= ath5k_rx_decrypted(ah, skb, rs);
1368 if (rxs->rate_idx >= 0 && rs->rs_rate ==
1369 ah->sbands[ah->curchan->band].bitrates[rxs->rate_idx].hw_value_short)
1370 rxs->flag |= RX_FLAG_SHORTPRE;
1372 trace_ath5k_rx(ah, skb);
1374 ath5k_update_beacon_rssi(ah, skb, rs->rs_rssi);
1376 /* check beacons in IBSS mode */
1377 if (ah->opmode == NL80211_IFTYPE_ADHOC)
1378 ath5k_check_ibss_tsf(ah, skb, rxs);
1380 ieee80211_rx(ah->hw, skb);
1383 /** ath5k_frame_receive_ok() - Do we want to receive this frame or not?
1385 * Check if we want to further process this frame or not. Also update
1386 * statistics. Return true if we want this frame, false if not.
1389 ath5k_receive_frame_ok(struct ath5k_hw *ah, struct ath5k_rx_status *rs)
1391 ah->stats.rx_all_count++;
1392 ah->stats.rx_bytes_count += rs->rs_datalen;
1394 if (unlikely(rs->rs_status)) {
1395 if (rs->rs_status & AR5K_RXERR_CRC)
1396 ah->stats.rxerr_crc++;
1397 if (rs->rs_status & AR5K_RXERR_FIFO)
1398 ah->stats.rxerr_fifo++;
1399 if (rs->rs_status & AR5K_RXERR_PHY) {
1400 ah->stats.rxerr_phy++;
1401 if (rs->rs_phyerr > 0 && rs->rs_phyerr < 32)
1402 ah->stats.rxerr_phy_code[rs->rs_phyerr]++;
1405 if (rs->rs_status & AR5K_RXERR_DECRYPT) {
1407 * Decrypt error. If the error occurred
1408 * because there was no hardware key, then
1409 * let the frame through so the upper layers
1410 * can process it. This is necessary for 5210
1411 * parts which have no way to setup a ``clear''
1414 * XXX do key cache faulting
1416 ah->stats.rxerr_decrypt++;
1417 if (rs->rs_keyix == AR5K_RXKEYIX_INVALID &&
1418 !(rs->rs_status & AR5K_RXERR_CRC))
1421 if (rs->rs_status & AR5K_RXERR_MIC) {
1422 ah->stats.rxerr_mic++;
1426 /* reject any frames with non-crypto errors */
1427 if (rs->rs_status & ~(AR5K_RXERR_DECRYPT))
1431 if (unlikely(rs->rs_more)) {
1432 ah->stats.rxerr_jumbo++;
1439 ath5k_set_current_imask(struct ath5k_hw *ah)
1441 enum ath5k_int imask;
1442 unsigned long flags;
1444 spin_lock_irqsave(&ah->irqlock, flags);
1447 imask &= ~AR5K_INT_RX_ALL;
1449 imask &= ~AR5K_INT_TX_ALL;
1450 ath5k_hw_set_imr(ah, imask);
1451 spin_unlock_irqrestore(&ah->irqlock, flags);
1455 ath5k_tasklet_rx(unsigned long data)
1457 struct ath5k_rx_status rs = {};
1458 struct sk_buff *skb, *next_skb;
1459 dma_addr_t next_skb_addr;
1460 struct ath5k_hw *ah = (void *)data;
1461 struct ath_common *common = ath5k_hw_common(ah);
1462 struct ath5k_buf *bf;
1463 struct ath5k_desc *ds;
1466 spin_lock(&ah->rxbuflock);
1467 if (list_empty(&ah->rxbuf)) {
1468 ATH5K_WARN(ah, "empty rx buf pool\n");
1472 bf = list_first_entry(&ah->rxbuf, struct ath5k_buf, list);
1473 BUG_ON(bf->skb == NULL);
1477 /* bail if HW is still using self-linked descriptor */
1478 if (ath5k_hw_get_rxdp(ah) == bf->daddr)
1481 ret = ah->ah_proc_rx_desc(ah, ds, &rs);
1482 if (unlikely(ret == -EINPROGRESS))
1484 else if (unlikely(ret)) {
1485 ATH5K_ERR(ah, "error in processing rx descriptor\n");
1486 ah->stats.rxerr_proc++;
1490 if (ath5k_receive_frame_ok(ah, &rs)) {
1491 next_skb = ath5k_rx_skb_alloc(ah, &next_skb_addr);
1494 * If we can't replace bf->skb with a new skb under
1495 * memory pressure, just skip this packet
1500 dma_unmap_single(ah->dev, bf->skbaddr,
1504 skb_put(skb, rs.rs_datalen);
1506 ath5k_receive_frame(ah, skb, &rs);
1509 bf->skbaddr = next_skb_addr;
1512 list_move_tail(&bf->list, &ah->rxbuf);
1513 } while (ath5k_rxbuf_setup(ah, bf) == 0);
1515 spin_unlock(&ah->rxbuflock);
1516 ah->rx_pending = false;
1517 ath5k_set_current_imask(ah);
1526 ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
1527 struct ath5k_txq *txq)
1529 struct ath5k_hw *ah = hw->priv;
1530 struct ath5k_buf *bf;
1531 unsigned long flags;
1534 trace_ath5k_tx(ah, skb, txq);
1537 * The hardware expects the header padded to 4 byte boundaries.
1538 * If this is not the case, we add the padding after the header.
1540 padsize = ath5k_add_padding(skb);
1542 ATH5K_ERR(ah, "tx hdrlen not %%4: not enough"
1543 " headroom to pad");
1547 if (txq->txq_len >= txq->txq_max &&
1548 txq->qnum <= AR5K_TX_QUEUE_ID_DATA_MAX)
1549 ieee80211_stop_queue(hw, txq->qnum);
1551 spin_lock_irqsave(&ah->txbuflock, flags);
1552 if (list_empty(&ah->txbuf)) {
1553 ATH5K_ERR(ah, "no further txbuf available, dropping packet\n");
1554 spin_unlock_irqrestore(&ah->txbuflock, flags);
1555 ieee80211_stop_queues(hw);
1558 bf = list_first_entry(&ah->txbuf, struct ath5k_buf, list);
1559 list_del(&bf->list);
1561 if (list_empty(&ah->txbuf))
1562 ieee80211_stop_queues(hw);
1563 spin_unlock_irqrestore(&ah->txbuflock, flags);
1567 if (ath5k_txbuf_setup(ah, bf, txq, padsize)) {
1569 spin_lock_irqsave(&ah->txbuflock, flags);
1570 list_add_tail(&bf->list, &ah->txbuf);
1572 spin_unlock_irqrestore(&ah->txbuflock, flags);
1578 dev_kfree_skb_any(skb);
1582 ath5k_tx_frame_completed(struct ath5k_hw *ah, struct sk_buff *skb,
1583 struct ath5k_txq *txq, struct ath5k_tx_status *ts)
1585 struct ieee80211_tx_info *info;
1589 ah->stats.tx_all_count++;
1590 ah->stats.tx_bytes_count += skb->len;
1591 info = IEEE80211_SKB_CB(skb);
1593 tries[0] = info->status.rates[0].count;
1594 tries[1] = info->status.rates[1].count;
1595 tries[2] = info->status.rates[2].count;
1597 ieee80211_tx_info_clear_status(info);
1599 for (i = 0; i < ts->ts_final_idx; i++) {
1600 struct ieee80211_tx_rate *r =
1601 &info->status.rates[i];
1603 r->count = tries[i];
1606 info->status.rates[ts->ts_final_idx].count = ts->ts_final_retry;
1607 info->status.rates[ts->ts_final_idx + 1].idx = -1;
1609 if (unlikely(ts->ts_status)) {
1610 ah->stats.ack_fail++;
1611 if (ts->ts_status & AR5K_TXERR_FILT) {
1612 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1613 ah->stats.txerr_filt++;
1615 if (ts->ts_status & AR5K_TXERR_XRETRY)
1616 ah->stats.txerr_retry++;
1617 if (ts->ts_status & AR5K_TXERR_FIFO)
1618 ah->stats.txerr_fifo++;
1620 info->flags |= IEEE80211_TX_STAT_ACK;
1621 info->status.ack_signal = ts->ts_rssi;
1623 /* count the successful attempt as well */
1624 info->status.rates[ts->ts_final_idx].count++;
1628 * Remove MAC header padding before giving the frame
1631 ath5k_remove_padding(skb);
1633 if (ts->ts_antenna > 0 && ts->ts_antenna < 5)
1634 ah->stats.antenna_tx[ts->ts_antenna]++;
1636 ah->stats.antenna_tx[0]++; /* invalid */
1638 trace_ath5k_tx_complete(ah, skb, txq, ts);
1639 ieee80211_tx_status(ah->hw, skb);
1643 ath5k_tx_processq(struct ath5k_hw *ah, struct ath5k_txq *txq)
1645 struct ath5k_tx_status ts = {};
1646 struct ath5k_buf *bf, *bf0;
1647 struct ath5k_desc *ds;
1648 struct sk_buff *skb;
1651 spin_lock(&txq->lock);
1652 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1654 txq->txq_poll_mark = false;
1656 /* skb might already have been processed last time. */
1657 if (bf->skb != NULL) {
1660 ret = ah->ah_proc_tx_desc(ah, ds, &ts);
1661 if (unlikely(ret == -EINPROGRESS))
1663 else if (unlikely(ret)) {
1665 "error %d while processing "
1666 "queue %u\n", ret, txq->qnum);
1673 dma_unmap_single(ah->dev, bf->skbaddr, skb->len,
1675 ath5k_tx_frame_completed(ah, skb, txq, &ts);
1679 * It's possible that the hardware can say the buffer is
1680 * completed when it hasn't yet loaded the ds_link from
1681 * host memory and moved on.
1682 * Always keep the last descriptor to avoid HW races...
1684 if (ath5k_hw_get_txdp(ah, txq->qnum) != bf->daddr) {
1685 spin_lock(&ah->txbuflock);
1686 list_move_tail(&bf->list, &ah->txbuf);
1689 spin_unlock(&ah->txbuflock);
1692 spin_unlock(&txq->lock);
1693 if (txq->txq_len < ATH5K_TXQ_LEN_LOW && txq->qnum < 4)
1694 ieee80211_wake_queue(ah->hw, txq->qnum);
1698 ath5k_tasklet_tx(unsigned long data)
1701 struct ath5k_hw *ah = (void *)data;
1703 for (i = 0; i < AR5K_NUM_TX_QUEUES; i++)
1704 if (ah->txqs[i].setup && (ah->ah_txq_isr & BIT(i)))
1705 ath5k_tx_processq(ah, &ah->txqs[i]);
1707 ah->tx_pending = false;
1708 ath5k_set_current_imask(ah);
1717 * Setup the beacon frame for transmit.
1720 ath5k_beacon_setup(struct ath5k_hw *ah, struct ath5k_buf *bf)
1722 struct sk_buff *skb = bf->skb;
1723 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1724 struct ath5k_desc *ds;
1728 const int padsize = 0;
1730 bf->skbaddr = dma_map_single(ah->dev, skb->data, skb->len,
1732 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1733 "skbaddr %llx\n", skb, skb->data, skb->len,
1734 (unsigned long long)bf->skbaddr);
1736 if (dma_mapping_error(ah->dev, bf->skbaddr)) {
1737 ATH5K_ERR(ah, "beacon DMA mapping failed\n");
1742 antenna = ah->ah_tx_ant;
1744 flags = AR5K_TXDESC_NOACK;
1745 if (ah->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
1746 ds->ds_link = bf->daddr; /* self-linked */
1747 flags |= AR5K_TXDESC_VEOL;
1752 * If we use multiple antennas on AP and use
1753 * the Sectored AP scenario, switch antenna every
1754 * 4 beacons to make sure everybody hears our AP.
1755 * When a client tries to associate, hw will keep
1756 * track of the tx antenna to be used for this client
1757 * automatically, based on ACKed packets.
1759 * Note: AP still listens and transmits RTS on the
1760 * default antenna which is supposed to be an omni.
1762 * Note2: On sectored scenarios it's possible to have
1763 * multiple antennas (1 omni -- the default -- and 14
1764 * sectors), so if we choose to actually support this
1765 * mode, we need to allow the user to set how many antennas
1766 * we have and tweak the code below to send beacons
1769 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
1770 antenna = ah->bsent & 4 ? 2 : 1;
1773 /* FIXME: If we are in g mode and rate is a CCK rate
1774 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1775 * from tx power (value is in dB units already) */
1776 ds->ds_data = bf->skbaddr;
1777 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
1778 ieee80211_get_hdrlen_from_skb(skb), padsize,
1779 AR5K_PKT_TYPE_BEACON, (ah->power_level * 2),
1780 ieee80211_get_tx_rate(ah->hw, info)->hw_value,
1781 1, AR5K_TXKEYIX_INVALID,
1782 antenna, flags, 0, 0);
1788 dma_unmap_single(ah->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
1793 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
1794 * this is called only once at config_bss time, for AP we do it every
1795 * SWBA interrupt so that the TIM will reflect buffered frames.
1797 * Called with the beacon lock.
1800 ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1803 struct ath5k_hw *ah = hw->priv;
1804 struct ath5k_vif *avf = (void *)vif->drv_priv;
1805 struct sk_buff *skb;
1807 if (WARN_ON(!vif)) {
1812 skb = ieee80211_beacon_get(hw, vif);
1819 ath5k_txbuf_free_skb(ah, avf->bbuf);
1820 avf->bbuf->skb = skb;
1821 ret = ath5k_beacon_setup(ah, avf->bbuf);
1823 avf->bbuf->skb = NULL;
1829 * Transmit a beacon frame at SWBA. Dynamic updates to the
1830 * frame contents are done as needed and the slot time is
1831 * also adjusted based on current state.
1833 * This is called from software irq context (beacontq tasklets)
1834 * or user context from ath5k_beacon_config.
1837 ath5k_beacon_send(struct ath5k_hw *ah)
1839 struct ieee80211_vif *vif;
1840 struct ath5k_vif *avf;
1841 struct ath5k_buf *bf;
1842 struct sk_buff *skb;
1844 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, "in beacon_send\n");
1847 * Check if the previous beacon has gone out. If
1848 * not, don't don't try to post another: skip this
1849 * period and wait for the next. Missed beacons
1850 * indicate a problem and should not occur. If we
1851 * miss too many consecutive beacons reset the device.
1853 if (unlikely(ath5k_hw_num_tx_pending(ah, ah->bhalq) != 0)) {
1855 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
1856 "missed %u consecutive beacons\n", ah->bmisscount);
1857 if (ah->bmisscount > 10) { /* NB: 10 is a guess */
1858 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
1859 "stuck beacon time (%u missed)\n",
1861 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
1862 "stuck beacon, resetting\n");
1863 ieee80211_queue_work(ah->hw, &ah->reset_work);
1867 if (unlikely(ah->bmisscount != 0)) {
1868 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
1869 "resume beacon xmit after %u misses\n",
1874 if ((ah->opmode == NL80211_IFTYPE_AP && ah->num_ap_vifs > 1) ||
1875 ah->opmode == NL80211_IFTYPE_MESH_POINT) {
1876 u64 tsf = ath5k_hw_get_tsf64(ah);
1877 u32 tsftu = TSF_TO_TU(tsf);
1878 int slot = ((tsftu % ah->bintval) * ATH_BCBUF) / ah->bintval;
1879 vif = ah->bslot[(slot + 1) % ATH_BCBUF];
1880 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
1881 "tsf %llx tsftu %x intval %u slot %u vif %p\n",
1882 (unsigned long long)tsf, tsftu, ah->bintval, slot, vif);
1883 } else /* only one interface */
1889 avf = (void *)vif->drv_priv;
1891 if (unlikely(bf->skb == NULL || ah->opmode == NL80211_IFTYPE_STATION ||
1892 ah->opmode == NL80211_IFTYPE_MONITOR)) {
1893 ATH5K_WARN(ah, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
1898 * Stop any current dma and put the new frame on the queue.
1899 * This should never fail since we check above that no frames
1900 * are still pending on the queue.
1902 if (unlikely(ath5k_hw_stop_beacon_queue(ah, ah->bhalq))) {
1903 ATH5K_WARN(ah, "beacon queue %u didn't start/stop ?\n", ah->bhalq);
1904 /* NB: hw still stops DMA, so proceed */
1907 /* refresh the beacon for AP or MESH mode */
1908 if (ah->opmode == NL80211_IFTYPE_AP ||
1909 ah->opmode == NL80211_IFTYPE_MESH_POINT)
1910 ath5k_beacon_update(ah->hw, vif);
1912 trace_ath5k_tx(ah, bf->skb, &ah->txqs[ah->bhalq]);
1914 ath5k_hw_set_txdp(ah, ah->bhalq, bf->daddr);
1915 ath5k_hw_start_tx_dma(ah, ah->bhalq);
1916 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
1917 ah->bhalq, (unsigned long long)bf->daddr, bf->desc);
1919 skb = ieee80211_get_buffered_bc(ah->hw, vif);
1921 ath5k_tx_queue(ah->hw, skb, ah->cabq);
1923 if (ah->cabq->txq_len >= ah->cabq->txq_max)
1926 skb = ieee80211_get_buffered_bc(ah->hw, vif);
1933 * ath5k_beacon_update_timers - update beacon timers
1935 * @ah: struct ath5k_hw pointer we are operating on
1936 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
1937 * beacon timer update based on the current HW TSF.
1939 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
1940 * of a received beacon or the current local hardware TSF and write it to the
1941 * beacon timer registers.
1943 * This is called in a variety of situations, e.g. when a beacon is received,
1944 * when a TSF update has been detected, but also when an new IBSS is created or
1945 * when we otherwise know we have to update the timers, but we keep it in this
1946 * function to have it all together in one place.
1949 ath5k_beacon_update_timers(struct ath5k_hw *ah, u64 bc_tsf)
1951 u32 nexttbtt, intval, hw_tu, bc_tu;
1954 intval = ah->bintval & AR5K_BEACON_PERIOD;
1955 if (ah->opmode == NL80211_IFTYPE_AP && ah->num_ap_vifs > 1) {
1956 intval /= ATH_BCBUF; /* staggered multi-bss beacons */
1958 ATH5K_WARN(ah, "intval %u is too low, min 15\n",
1961 if (WARN_ON(!intval))
1964 /* beacon TSF converted to TU */
1965 bc_tu = TSF_TO_TU(bc_tsf);
1967 /* current TSF converted to TU */
1968 hw_tsf = ath5k_hw_get_tsf64(ah);
1969 hw_tu = TSF_TO_TU(hw_tsf);
1971 #define FUDGE (AR5K_TUNE_SW_BEACON_RESP + 3)
1972 /* We use FUDGE to make sure the next TBTT is ahead of the current TU.
1973 * Since we later subtract AR5K_TUNE_SW_BEACON_RESP (10) in the timer
1974 * configuration we need to make sure it is bigger than that. */
1978 * no beacons received, called internally.
1979 * just need to refresh timers based on HW TSF.
1981 nexttbtt = roundup(hw_tu + FUDGE, intval);
1982 } else if (bc_tsf == 0) {
1984 * no beacon received, probably called by ath5k_reset_tsf().
1985 * reset TSF to start with 0.
1988 intval |= AR5K_BEACON_RESET_TSF;
1989 } else if (bc_tsf > hw_tsf) {
1991 * beacon received, SW merge happened but HW TSF not yet updated.
1992 * not possible to reconfigure timers yet, but next time we
1993 * receive a beacon with the same BSSID, the hardware will
1994 * automatically update the TSF and then we need to reconfigure
1997 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
1998 "need to wait for HW TSF sync\n");
2002 * most important case for beacon synchronization between STA.
2004 * beacon received and HW TSF has been already updated by HW.
2005 * update next TBTT based on the TSF of the beacon, but make
2006 * sure it is ahead of our local TSF timer.
2008 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2012 ah->nexttbtt = nexttbtt;
2014 intval |= AR5K_BEACON_ENA;
2015 ath5k_hw_init_beacon(ah, nexttbtt, intval);
2018 * debugging output last in order to preserve the time critical aspect
2022 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
2023 "reconfigured timers based on HW TSF\n");
2024 else if (bc_tsf == 0)
2025 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
2026 "reset HW TSF and timers\n");
2028 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
2029 "updated timers based on beacon TSF\n");
2031 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
2032 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2033 (unsigned long long) bc_tsf,
2034 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
2035 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2036 intval & AR5K_BEACON_PERIOD,
2037 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2038 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
2042 * ath5k_beacon_config - Configure the beacon queues and interrupts
2044 * @ah: struct ath5k_hw pointer we are operating on
2046 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2047 * interrupts to detect TSF updates only.
2050 ath5k_beacon_config(struct ath5k_hw *ah)
2052 unsigned long flags;
2054 spin_lock_irqsave(&ah->block, flags);
2056 ah->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
2058 if (ah->enable_beacon) {
2060 * In IBSS mode we use a self-linked tx descriptor and let the
2061 * hardware send the beacons automatically. We have to load it
2063 * We use the SWBA interrupt only to keep track of the beacon
2064 * timers in order to detect automatic TSF updates.
2066 ath5k_beaconq_config(ah);
2068 ah->imask |= AR5K_INT_SWBA;
2070 if (ah->opmode == NL80211_IFTYPE_ADHOC) {
2071 if (ath5k_hw_hasveol(ah))
2072 ath5k_beacon_send(ah);
2074 ath5k_beacon_update_timers(ah, -1);
2076 ath5k_hw_stop_beacon_queue(ah, ah->bhalq);
2079 ath5k_hw_set_imr(ah, ah->imask);
2081 spin_unlock_irqrestore(&ah->block, flags);
2084 static void ath5k_tasklet_beacon(unsigned long data)
2086 struct ath5k_hw *ah = (struct ath5k_hw *) data;
2089 * Software beacon alert--time to send a beacon.
2091 * In IBSS mode we use this interrupt just to
2092 * keep track of the next TBTT (target beacon
2093 * transmission time) in order to detect whether
2094 * automatic TSF updates happened.
2096 if (ah->opmode == NL80211_IFTYPE_ADHOC) {
2097 /* XXX: only if VEOL supported */
2098 u64 tsf = ath5k_hw_get_tsf64(ah);
2099 ah->nexttbtt += ah->bintval;
2100 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
2101 "SWBA nexttbtt: %x hw_tu: %x "
2105 (unsigned long long) tsf);
2107 spin_lock(&ah->block);
2108 ath5k_beacon_send(ah);
2109 spin_unlock(&ah->block);
2114 /********************\
2115 * Interrupt handling *
2116 \********************/
2119 ath5k_intr_calibration_poll(struct ath5k_hw *ah)
2121 if (time_is_before_eq_jiffies(ah->ah_cal_next_ani) &&
2122 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL)) {
2123 /* run ANI only when full calibration is not active */
2124 ah->ah_cal_next_ani = jiffies +
2125 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI);
2126 tasklet_schedule(&ah->ani_tasklet);
2128 } else if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) {
2129 ah->ah_cal_next_full = jiffies +
2130 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL);
2131 tasklet_schedule(&ah->calib);
2133 /* we could use SWI to generate enough interrupts to meet our
2134 * calibration interval requirements, if necessary:
2135 * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */
2139 ath5k_schedule_rx(struct ath5k_hw *ah)
2141 ah->rx_pending = true;
2142 tasklet_schedule(&ah->rxtq);
2146 ath5k_schedule_tx(struct ath5k_hw *ah)
2148 ah->tx_pending = true;
2149 tasklet_schedule(&ah->txtq);
2153 ath5k_intr(int irq, void *dev_id)
2155 struct ath5k_hw *ah = dev_id;
2156 enum ath5k_int status;
2157 unsigned int counter = 1000;
2159 if (unlikely(test_bit(ATH_STAT_INVALID, ah->status) ||
2160 ((ath5k_get_bus_type(ah) != ATH_AHB) &&
2161 !ath5k_hw_is_intr_pending(ah))))
2165 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2166 ATH5K_DBG(ah, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2168 if (unlikely(status & AR5K_INT_FATAL)) {
2170 * Fatal errors are unrecoverable.
2171 * Typically these are caused by DMA errors.
2173 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
2174 "fatal int, resetting\n");
2175 ieee80211_queue_work(ah->hw, &ah->reset_work);
2176 } else if (unlikely(status & AR5K_INT_RXORN)) {
2178 * Receive buffers are full. Either the bus is busy or
2179 * the CPU is not fast enough to process all received
2181 * Older chipsets need a reset to come out of this
2182 * condition, but we treat it as RX for newer chips.
2183 * We don't know exactly which versions need a reset -
2184 * this guess is copied from the HAL.
2186 ah->stats.rxorn_intr++;
2187 if (ah->ah_mac_srev < AR5K_SREV_AR5212) {
2188 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
2189 "rx overrun, resetting\n");
2190 ieee80211_queue_work(ah->hw, &ah->reset_work);
2192 ath5k_schedule_rx(ah);
2194 if (status & AR5K_INT_SWBA)
2195 tasklet_hi_schedule(&ah->beacontq);
2197 if (status & AR5K_INT_RXEOL) {
2199 * NB: the hardware should re-read the link when
2200 * RXE bit is written, but it doesn't work at
2201 * least on older hardware revs.
2203 ah->stats.rxeol_intr++;
2205 if (status & AR5K_INT_TXURN) {
2206 /* bump tx trigger level */
2207 ath5k_hw_update_tx_triglevel(ah, true);
2209 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
2210 ath5k_schedule_rx(ah);
2211 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2212 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
2213 ath5k_schedule_tx(ah);
2214 if (status & AR5K_INT_BMISS) {
2217 if (status & AR5K_INT_MIB) {
2218 ah->stats.mib_intr++;
2219 ath5k_hw_update_mib_counters(ah);
2220 ath5k_ani_mib_intr(ah);
2222 if (status & AR5K_INT_GPIO)
2223 tasklet_schedule(&ah->rf_kill.toggleq);
2227 if (ath5k_get_bus_type(ah) == ATH_AHB)
2230 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
2232 if (ah->rx_pending || ah->tx_pending)
2233 ath5k_set_current_imask(ah);
2235 if (unlikely(!counter))
2236 ATH5K_WARN(ah, "too many interrupts, giving up for now\n");
2238 ath5k_intr_calibration_poll(ah);
2244 * Periodically recalibrate the PHY to account
2245 * for temperature/environment changes.
2248 ath5k_tasklet_calibrate(unsigned long data)
2250 struct ath5k_hw *ah = (void *)data;
2252 /* Only full calibration for now */
2253 ah->ah_cal_mask |= AR5K_CALIBRATION_FULL;
2255 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2256 ieee80211_frequency_to_channel(ah->curchan->center_freq),
2257 ah->curchan->hw_value);
2259 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2261 * Rfgain is out of bounds, reset the chip
2262 * to load new gain values.
2264 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "calibration, resetting\n");
2265 ieee80211_queue_work(ah->hw, &ah->reset_work);
2267 if (ath5k_hw_phy_calibrate(ah, ah->curchan))
2268 ATH5K_ERR(ah, "calibration of channel %u failed\n",
2269 ieee80211_frequency_to_channel(
2270 ah->curchan->center_freq));
2272 /* Noise floor calibration interrupts rx/tx path while I/Q calibration
2274 * TODO: We should stop TX here, so that it doesn't interfere.
2275 * Note that stopping the queues is not enough to stop TX! */
2276 if (time_is_before_eq_jiffies(ah->ah_cal_next_nf)) {
2277 ah->ah_cal_next_nf = jiffies +
2278 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_NF);
2279 ath5k_hw_update_noise_floor(ah);
2282 ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL;
2287 ath5k_tasklet_ani(unsigned long data)
2289 struct ath5k_hw *ah = (void *)data;
2291 ah->ah_cal_mask |= AR5K_CALIBRATION_ANI;
2292 ath5k_ani_calibration(ah);
2293 ah->ah_cal_mask &= ~AR5K_CALIBRATION_ANI;
2298 ath5k_tx_complete_poll_work(struct work_struct *work)
2300 struct ath5k_hw *ah = container_of(work, struct ath5k_hw,
2301 tx_complete_work.work);
2302 struct ath5k_txq *txq;
2304 bool needreset = false;
2306 mutex_lock(&ah->lock);
2308 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++) {
2309 if (ah->txqs[i].setup) {
2311 spin_lock_bh(&txq->lock);
2312 if (txq->txq_len > 1) {
2313 if (txq->txq_poll_mark) {
2314 ATH5K_DBG(ah, ATH5K_DEBUG_XMIT,
2315 "TX queue stuck %d\n",
2319 spin_unlock_bh(&txq->lock);
2322 txq->txq_poll_mark = true;
2325 spin_unlock_bh(&txq->lock);
2330 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
2331 "TX queues stuck, resetting\n");
2332 ath5k_reset(ah, NULL, true);
2335 mutex_unlock(&ah->lock);
2337 ieee80211_queue_delayed_work(ah->hw, &ah->tx_complete_work,
2338 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2342 /*************************\
2343 * Initialization routines *
2344 \*************************/
2347 ath5k_init_softc(struct ath5k_hw *ah, const struct ath_bus_ops *bus_ops)
2349 struct ieee80211_hw *hw = ah->hw;
2350 struct ath_common *common;
2354 /* Initialize driver private data */
2355 SET_IEEE80211_DEV(hw, ah->dev);
2356 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
2357 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2358 IEEE80211_HW_SIGNAL_DBM |
2359 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
2361 hw->wiphy->interface_modes =
2362 BIT(NL80211_IFTYPE_AP) |
2363 BIT(NL80211_IFTYPE_STATION) |
2364 BIT(NL80211_IFTYPE_ADHOC) |
2365 BIT(NL80211_IFTYPE_MESH_POINT);
2367 /* both antennas can be configured as RX or TX */
2368 hw->wiphy->available_antennas_tx = 0x3;
2369 hw->wiphy->available_antennas_rx = 0x3;
2371 hw->extra_tx_headroom = 2;
2372 hw->channel_change_time = 5000;
2375 * Mark the device as detached to avoid processing
2376 * interrupts until setup is complete.
2378 __set_bit(ATH_STAT_INVALID, ah->status);
2380 ah->opmode = NL80211_IFTYPE_STATION;
2382 mutex_init(&ah->lock);
2383 spin_lock_init(&ah->rxbuflock);
2384 spin_lock_init(&ah->txbuflock);
2385 spin_lock_init(&ah->block);
2386 spin_lock_init(&ah->irqlock);
2388 /* Setup interrupt handler */
2389 ret = request_irq(ah->irq, ath5k_intr, IRQF_SHARED, "ath", ah);
2391 ATH5K_ERR(ah, "request_irq failed\n");
2395 common = ath5k_hw_common(ah);
2396 common->ops = &ath5k_common_ops;
2397 common->bus_ops = bus_ops;
2401 common->clockrate = 40;
2404 * Cache line size is used to size and align various
2405 * structures used to communicate with the hardware.
2407 ath5k_read_cachesize(common, &csz);
2408 common->cachelsz = csz << 2; /* convert to bytes */
2410 spin_lock_init(&common->cc_lock);
2412 /* Initialize device */
2413 ret = ath5k_hw_init(ah);
2417 /* set up multi-rate retry capabilities */
2418 if (ah->ah_version == AR5K_AR5212) {
2420 hw->max_rate_tries = max(AR5K_INIT_RETRY_SHORT,
2421 AR5K_INIT_RETRY_LONG);
2424 hw->vif_data_size = sizeof(struct ath5k_vif);
2426 /* Finish private driver data initialization */
2427 ret = ath5k_init(hw);
2431 ATH5K_INFO(ah, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
2432 ath5k_chip_name(AR5K_VERSION_MAC, ah->ah_mac_srev),
2434 ah->ah_phy_revision);
2436 if (!ah->ah_single_chip) {
2437 /* Single chip radio (!RF5111) */
2438 if (ah->ah_radio_5ghz_revision &&
2439 !ah->ah_radio_2ghz_revision) {
2440 /* No 5GHz support -> report 2GHz radio */
2441 if (!test_bit(AR5K_MODE_11A,
2442 ah->ah_capabilities.cap_mode)) {
2443 ATH5K_INFO(ah, "RF%s 2GHz radio found (0x%x)\n",
2444 ath5k_chip_name(AR5K_VERSION_RAD,
2445 ah->ah_radio_5ghz_revision),
2446 ah->ah_radio_5ghz_revision);
2447 /* No 2GHz support (5110 and some
2448 * 5GHz only cards) -> report 5GHz radio */
2449 } else if (!test_bit(AR5K_MODE_11B,
2450 ah->ah_capabilities.cap_mode)) {
2451 ATH5K_INFO(ah, "RF%s 5GHz radio found (0x%x)\n",
2452 ath5k_chip_name(AR5K_VERSION_RAD,
2453 ah->ah_radio_5ghz_revision),
2454 ah->ah_radio_5ghz_revision);
2455 /* Multiband radio */
2457 ATH5K_INFO(ah, "RF%s multiband radio found"
2459 ath5k_chip_name(AR5K_VERSION_RAD,
2460 ah->ah_radio_5ghz_revision),
2461 ah->ah_radio_5ghz_revision);
2464 /* Multi chip radio (RF5111 - RF2111) ->
2465 * report both 2GHz/5GHz radios */
2466 else if (ah->ah_radio_5ghz_revision &&
2467 ah->ah_radio_2ghz_revision) {
2468 ATH5K_INFO(ah, "RF%s 5GHz radio found (0x%x)\n",
2469 ath5k_chip_name(AR5K_VERSION_RAD,
2470 ah->ah_radio_5ghz_revision),
2471 ah->ah_radio_5ghz_revision);
2472 ATH5K_INFO(ah, "RF%s 2GHz radio found (0x%x)\n",
2473 ath5k_chip_name(AR5K_VERSION_RAD,
2474 ah->ah_radio_2ghz_revision),
2475 ah->ah_radio_2ghz_revision);
2479 ath5k_debug_init_device(ah);
2481 /* ready to process interrupts */
2482 __clear_bit(ATH_STAT_INVALID, ah->status);
2486 ath5k_hw_deinit(ah);
2488 free_irq(ah->irq, ah);
2494 ath5k_stop_locked(struct ath5k_hw *ah)
2497 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "invalid %u\n",
2498 test_bit(ATH_STAT_INVALID, ah->status));
2501 * Shutdown the hardware and driver:
2502 * stop output from above
2503 * disable interrupts
2505 * turn off the radio
2506 * clear transmit machinery
2507 * clear receive machinery
2508 * drain and release tx queues
2509 * reclaim beacon resources
2510 * power down hardware
2512 * Note that some of this work is not possible if the
2513 * hardware is gone (invalid).
2515 ieee80211_stop_queues(ah->hw);
2517 if (!test_bit(ATH_STAT_INVALID, ah->status)) {
2519 ath5k_hw_set_imr(ah, 0);
2520 synchronize_irq(ah->irq);
2522 ath5k_hw_dma_stop(ah);
2523 ath5k_drain_tx_buffs(ah);
2524 ath5k_hw_phy_disable(ah);
2530 int ath5k_start(struct ieee80211_hw *hw)
2532 struct ath5k_hw *ah = hw->priv;
2533 struct ath_common *common = ath5k_hw_common(ah);
2536 mutex_lock(&ah->lock);
2538 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "mode %d\n", ah->opmode);
2541 * Stop anything previously setup. This is safe
2542 * no matter this is the first time through or not.
2544 ath5k_stop_locked(ah);
2547 * The basic interface to setting the hardware in a good
2548 * state is ``reset''. On return the hardware is known to
2549 * be powered up and with interrupts disabled. This must
2550 * be followed by initialization of the appropriate bits
2551 * and then setup of the interrupt mask.
2553 ah->curchan = ah->hw->conf.channel;
2554 ah->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2555 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
2556 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB;
2558 ret = ath5k_reset(ah, NULL, false);
2562 ath5k_rfkill_hw_start(ah);
2565 * Reset the key cache since some parts do not reset the
2566 * contents on initial power up or resume from suspend.
2568 for (i = 0; i < common->keymax; i++)
2569 ath_hw_keyreset(common, (u16) i);
2571 /* Use higher rates for acks instead of base
2573 ah->ah_ack_bitrate_high = true;
2575 for (i = 0; i < ARRAY_SIZE(ah->bslot); i++)
2576 ah->bslot[i] = NULL;
2581 mutex_unlock(&ah->lock);
2583 ieee80211_queue_delayed_work(ah->hw, &ah->tx_complete_work,
2584 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2589 static void ath5k_stop_tasklets(struct ath5k_hw *ah)
2591 ah->rx_pending = false;
2592 ah->tx_pending = false;
2593 tasklet_kill(&ah->rxtq);
2594 tasklet_kill(&ah->txtq);
2595 tasklet_kill(&ah->calib);
2596 tasklet_kill(&ah->beacontq);
2597 tasklet_kill(&ah->ani_tasklet);
2601 * Stop the device, grabbing the top-level lock to protect
2602 * against concurrent entry through ath5k_init (which can happen
2603 * if another thread does a system call and the thread doing the
2604 * stop is preempted).
2606 void ath5k_stop(struct ieee80211_hw *hw)
2608 struct ath5k_hw *ah = hw->priv;
2611 mutex_lock(&ah->lock);
2612 ret = ath5k_stop_locked(ah);
2613 if (ret == 0 && !test_bit(ATH_STAT_INVALID, ah->status)) {
2615 * Don't set the card in full sleep mode!
2617 * a) When the device is in this state it must be carefully
2618 * woken up or references to registers in the PCI clock
2619 * domain may freeze the bus (and system). This varies
2620 * by chip and is mostly an issue with newer parts
2621 * (madwifi sources mentioned srev >= 0x78) that go to
2622 * sleep more quickly.
2624 * b) On older chips full sleep results a weird behaviour
2625 * during wakeup. I tested various cards with srev < 0x78
2626 * and they don't wake up after module reload, a second
2627 * module reload is needed to bring the card up again.
2629 * Until we figure out what's going on don't enable
2630 * full chip reset on any chip (this is what Legacy HAL
2631 * and Sam's HAL do anyway). Instead Perform a full reset
2632 * on the device (same as initial state after attach) and
2633 * leave it idle (keep MAC/BB on warm reset) */
2634 ret = ath5k_hw_on_hold(ah);
2636 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
2637 "putting device to sleep\n");
2641 mutex_unlock(&ah->lock);
2643 ath5k_stop_tasklets(ah);
2645 cancel_delayed_work_sync(&ah->tx_complete_work);
2647 ath5k_rfkill_hw_stop(ah);
2651 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2652 * and change to the given channel.
2654 * This should be called with ah->lock.
2657 ath5k_reset(struct ath5k_hw *ah, struct ieee80211_channel *chan,
2660 struct ath_common *common = ath5k_hw_common(ah);
2664 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "resetting\n");
2666 ath5k_hw_set_imr(ah, 0);
2667 synchronize_irq(ah->irq);
2668 ath5k_stop_tasklets(ah);
2670 /* Save ani mode and disable ANI during
2671 * reset. If we don't we might get false
2672 * PHY error interrupts. */
2673 ani_mode = ah->ani_state.ani_mode;
2674 ath5k_ani_init(ah, ATH5K_ANI_MODE_OFF);
2676 /* We are going to empty hw queues
2677 * so we should also free any remaining
2679 ath5k_drain_tx_buffs(ah);
2683 fast = ((chan != NULL) && modparam_fastchanswitch) ? 1 : 0;
2685 ret = ath5k_hw_reset(ah, ah->opmode, ah->curchan, fast, skip_pcu);
2687 ATH5K_ERR(ah, "can't reset hardware (%d)\n", ret);
2691 ret = ath5k_rx_start(ah);
2693 ATH5K_ERR(ah, "can't start recv logic\n");
2697 ath5k_ani_init(ah, ani_mode);
2699 ah->ah_cal_next_full = jiffies + msecs_to_jiffies(100);
2700 ah->ah_cal_next_ani = jiffies;
2701 ah->ah_cal_next_nf = jiffies;
2702 ewma_init(&ah->ah_beacon_rssi_avg, 1024, 8);
2704 /* clear survey data and cycle counters */
2705 memset(&ah->survey, 0, sizeof(ah->survey));
2706 spin_lock_bh(&common->cc_lock);
2707 ath_hw_cycle_counters_update(common);
2708 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
2709 memset(&common->cc_ani, 0, sizeof(common->cc_ani));
2710 spin_unlock_bh(&common->cc_lock);
2713 * Change channels and update the h/w rate map if we're switching;
2714 * e.g. 11a to 11b/g.
2716 * We may be doing a reset in response to an ioctl that changes the
2717 * channel so update any state that might change as a result.
2721 /* ath5k_chan_change(ah, c); */
2723 ath5k_beacon_config(ah);
2724 /* intrs are enabled by ath5k_beacon_config */
2726 ieee80211_wake_queues(ah->hw);
2733 static void ath5k_reset_work(struct work_struct *work)
2735 struct ath5k_hw *ah = container_of(work, struct ath5k_hw,
2738 mutex_lock(&ah->lock);
2739 ath5k_reset(ah, NULL, true);
2740 mutex_unlock(&ah->lock);
2743 static int __devinit
2744 ath5k_init(struct ieee80211_hw *hw)
2747 struct ath5k_hw *ah = hw->priv;
2748 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
2749 struct ath5k_txq *txq;
2750 u8 mac[ETH_ALEN] = {};
2755 * Check if the MAC has multi-rate retry support.
2756 * We do this by trying to setup a fake extended
2757 * descriptor. MACs that don't have support will
2758 * return false w/o doing anything. MACs that do
2759 * support it will return true w/o doing anything.
2761 ret = ath5k_hw_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
2766 __set_bit(ATH_STAT_MRRETRY, ah->status);
2769 * Collect the channel list. The 802.11 layer
2770 * is responsible for filtering this list based
2771 * on settings like the phy mode and regulatory
2772 * domain restrictions.
2774 ret = ath5k_setup_bands(hw);
2776 ATH5K_ERR(ah, "can't get channels\n");
2781 * Allocate tx+rx descriptors and populate the lists.
2783 ret = ath5k_desc_alloc(ah);
2785 ATH5K_ERR(ah, "can't allocate descriptors\n");
2790 * Allocate hardware transmit queues: one queue for
2791 * beacon frames and one data queue for each QoS
2792 * priority. Note that hw functions handle resetting
2793 * these queues at the needed time.
2795 ret = ath5k_beaconq_setup(ah);
2797 ATH5K_ERR(ah, "can't setup a beacon xmit queue\n");
2801 ah->cabq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_CAB, 0);
2802 if (IS_ERR(ah->cabq)) {
2803 ATH5K_ERR(ah, "can't setup cab queue\n");
2804 ret = PTR_ERR(ah->cabq);
2808 /* 5211 and 5212 usually support 10 queues but we better rely on the
2809 * capability information */
2810 if (ah->ah_capabilities.cap_queues.q_tx_num >= 6) {
2811 /* This order matches mac80211's queue priority, so we can
2812 * directly use the mac80211 queue number without any mapping */
2813 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VO);
2815 ATH5K_ERR(ah, "can't setup xmit queue\n");
2819 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VI);
2821 ATH5K_ERR(ah, "can't setup xmit queue\n");
2825 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
2827 ATH5K_ERR(ah, "can't setup xmit queue\n");
2831 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
2833 ATH5K_ERR(ah, "can't setup xmit queue\n");
2839 /* older hardware (5210) can only support one data queue */
2840 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
2842 ATH5K_ERR(ah, "can't setup xmit queue\n");
2849 tasklet_init(&ah->rxtq, ath5k_tasklet_rx, (unsigned long)ah);
2850 tasklet_init(&ah->txtq, ath5k_tasklet_tx, (unsigned long)ah);
2851 tasklet_init(&ah->calib, ath5k_tasklet_calibrate, (unsigned long)ah);
2852 tasklet_init(&ah->beacontq, ath5k_tasklet_beacon, (unsigned long)ah);
2853 tasklet_init(&ah->ani_tasklet, ath5k_tasklet_ani, (unsigned long)ah);
2855 INIT_WORK(&ah->reset_work, ath5k_reset_work);
2856 INIT_DELAYED_WORK(&ah->tx_complete_work, ath5k_tx_complete_poll_work);
2858 ret = ath5k_hw_common(ah)->bus_ops->eeprom_read_mac(ah, mac);
2860 ATH5K_ERR(ah, "unable to read address from EEPROM\n");
2864 SET_IEEE80211_PERM_ADDR(hw, mac);
2865 memcpy(&ah->lladdr, mac, ETH_ALEN);
2866 /* All MAC address bits matter for ACKs */
2867 ath5k_update_bssid_mask_and_opmode(ah, NULL);
2869 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
2870 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
2872 ATH5K_ERR(ah, "can't initialize regulatory system\n");
2876 ret = ieee80211_register_hw(hw);
2878 ATH5K_ERR(ah, "can't register ieee80211 hw\n");
2882 if (!ath_is_world_regd(regulatory))
2883 regulatory_hint(hw->wiphy, regulatory->alpha2);
2885 ath5k_init_leds(ah);
2887 ath5k_sysfs_register(ah);
2891 ath5k_txq_release(ah);
2893 ath5k_hw_release_tx_queue(ah, ah->bhalq);
2895 ath5k_desc_free(ah);
2901 ath5k_deinit_softc(struct ath5k_hw *ah)
2903 struct ieee80211_hw *hw = ah->hw;
2906 * NB: the order of these is important:
2907 * o call the 802.11 layer before detaching ath5k_hw to
2908 * ensure callbacks into the driver to delete global
2909 * key cache entries can be handled
2910 * o reclaim the tx queue data structures after calling
2911 * the 802.11 layer as we'll get called back to reclaim
2912 * node state and potentially want to use them
2913 * o to cleanup the tx queues the hal is called, so detach
2915 * XXX: ??? detach ath5k_hw ???
2916 * Other than that, it's straightforward...
2918 ieee80211_unregister_hw(hw);
2919 ath5k_desc_free(ah);
2920 ath5k_txq_release(ah);
2921 ath5k_hw_release_tx_queue(ah, ah->bhalq);
2922 ath5k_unregister_leds(ah);
2924 ath5k_sysfs_unregister(ah);
2926 * NB: can't reclaim these until after ieee80211_ifdetach
2927 * returns because we'll get called back to reclaim node
2928 * state and potentially want to use them.
2930 ath5k_hw_deinit(ah);
2931 free_irq(ah->irq, ah);
2935 ath5k_any_vif_assoc(struct ath5k_hw *ah)
2937 struct ath5k_vif_iter_data iter_data;
2938 iter_data.hw_macaddr = NULL;
2939 iter_data.any_assoc = false;
2940 iter_data.need_set_hw_addr = false;
2941 iter_data.found_active = true;
2943 ieee80211_iterate_active_interfaces_atomic(ah->hw, ath5k_vif_iter,
2945 return iter_data.any_assoc;
2949 ath5k_set_beacon_filter(struct ieee80211_hw *hw, bool enable)
2951 struct ath5k_hw *ah = hw->priv;
2953 rfilt = ath5k_hw_get_rx_filter(ah);
2955 rfilt |= AR5K_RX_FILTER_BEACON;
2957 rfilt &= ~AR5K_RX_FILTER_BEACON;
2958 ath5k_hw_set_rx_filter(ah, rfilt);
2959 ah->filter_flags = rfilt;