2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
43 #include <linux/module.h>
44 #include <linux/delay.h>
45 #include <linux/hardirq.h>
48 #include <linux/netdevice.h>
49 #include <linux/cache.h>
50 #include <linux/pci.h>
51 #include <linux/ethtool.h>
52 #include <linux/uaccess.h>
53 #include <linux/slab.h>
55 #include <net/ieee80211_radiotap.h>
57 #include <asm/unaligned.h>
64 static int modparam_nohwcrypt;
65 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
66 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
68 static int modparam_all_channels;
69 module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO);
70 MODULE_PARM_DESC(all_channels, "Expose all channels the device can use.");
78 MODULE_AUTHOR("Jiri Slaby");
79 MODULE_AUTHOR("Nick Kossifidis");
80 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
81 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
82 MODULE_LICENSE("Dual BSD/GPL");
83 MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
87 static DEFINE_PCI_DEVICE_TABLE(ath5k_pci_id_table) = {
88 { PCI_VDEVICE(ATHEROS, 0x0207) }, /* 5210 early */
89 { PCI_VDEVICE(ATHEROS, 0x0007) }, /* 5210 */
90 { PCI_VDEVICE(ATHEROS, 0x0011) }, /* 5311 - this is on AHB bus !*/
91 { PCI_VDEVICE(ATHEROS, 0x0012) }, /* 5211 */
92 { PCI_VDEVICE(ATHEROS, 0x0013) }, /* 5212 */
93 { PCI_VDEVICE(3COM_2, 0x0013) }, /* 3com 5212 */
94 { PCI_VDEVICE(3COM, 0x0013) }, /* 3com 3CRDAG675 5212 */
95 { PCI_VDEVICE(ATHEROS, 0x1014) }, /* IBM minipci 5212 */
96 { PCI_VDEVICE(ATHEROS, 0x0014) }, /* 5212 combatible */
97 { PCI_VDEVICE(ATHEROS, 0x0015) }, /* 5212 combatible */
98 { PCI_VDEVICE(ATHEROS, 0x0016) }, /* 5212 combatible */
99 { PCI_VDEVICE(ATHEROS, 0x0017) }, /* 5212 combatible */
100 { PCI_VDEVICE(ATHEROS, 0x0018) }, /* 5212 combatible */
101 { PCI_VDEVICE(ATHEROS, 0x0019) }, /* 5212 combatible */
102 { PCI_VDEVICE(ATHEROS, 0x001a) }, /* 2413 Griffin-lite */
103 { PCI_VDEVICE(ATHEROS, 0x001b) }, /* 5413 Eagle */
104 { PCI_VDEVICE(ATHEROS, 0x001c) }, /* PCI-E cards */
105 { PCI_VDEVICE(ATHEROS, 0x001d) }, /* 2417 Nala */
108 MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
111 static const struct ath5k_srev_name srev_names[] = {
112 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
113 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
114 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
115 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
116 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
117 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
118 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
119 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
120 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
121 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
122 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
123 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
124 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
125 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
126 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
127 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
128 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
129 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
130 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
131 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
132 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
133 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
134 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
135 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
136 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
137 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
138 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
139 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
140 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
141 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
142 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
143 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
144 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
145 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
146 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
147 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
150 static const struct ieee80211_rate ath5k_rates[] = {
152 .hw_value = ATH5K_RATE_CODE_1M, },
154 .hw_value = ATH5K_RATE_CODE_2M,
155 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
156 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
158 .hw_value = ATH5K_RATE_CODE_5_5M,
159 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
160 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
162 .hw_value = ATH5K_RATE_CODE_11M,
163 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
164 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
166 .hw_value = ATH5K_RATE_CODE_6M,
169 .hw_value = ATH5K_RATE_CODE_9M,
172 .hw_value = ATH5K_RATE_CODE_12M,
175 .hw_value = ATH5K_RATE_CODE_18M,
178 .hw_value = ATH5K_RATE_CODE_24M,
181 .hw_value = ATH5K_RATE_CODE_36M,
184 .hw_value = ATH5K_RATE_CODE_48M,
187 .hw_value = ATH5K_RATE_CODE_54M,
193 * Prototypes - PCI stack related functions
195 static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
196 const struct pci_device_id *id);
197 static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
198 #ifdef CONFIG_PM_SLEEP
199 static int ath5k_pci_suspend(struct device *dev);
200 static int ath5k_pci_resume(struct device *dev);
202 static SIMPLE_DEV_PM_OPS(ath5k_pm_ops, ath5k_pci_suspend, ath5k_pci_resume);
203 #define ATH5K_PM_OPS (&ath5k_pm_ops)
205 #define ATH5K_PM_OPS NULL
206 #endif /* CONFIG_PM_SLEEP */
208 static struct pci_driver ath5k_pci_driver = {
209 .name = KBUILD_MODNAME,
210 .id_table = ath5k_pci_id_table,
211 .probe = ath5k_pci_probe,
212 .remove = __devexit_p(ath5k_pci_remove),
213 .driver.pm = ATH5K_PM_OPS,
219 * Prototypes - MAC 802.11 stack related functions
221 static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
222 static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
223 struct ath5k_txq *txq);
224 static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan);
225 static int ath5k_start(struct ieee80211_hw *hw);
226 static void ath5k_stop(struct ieee80211_hw *hw);
227 static int ath5k_add_interface(struct ieee80211_hw *hw,
228 struct ieee80211_vif *vif);
229 static void ath5k_remove_interface(struct ieee80211_hw *hw,
230 struct ieee80211_vif *vif);
231 static int ath5k_config(struct ieee80211_hw *hw, u32 changed);
232 static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw,
233 struct netdev_hw_addr_list *mc_list);
234 static void ath5k_configure_filter(struct ieee80211_hw *hw,
235 unsigned int changed_flags,
236 unsigned int *new_flags,
238 static int ath5k_set_key(struct ieee80211_hw *hw,
239 enum set_key_cmd cmd,
240 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
241 struct ieee80211_key_conf *key);
242 static int ath5k_get_stats(struct ieee80211_hw *hw,
243 struct ieee80211_low_level_stats *stats);
244 static int ath5k_get_survey(struct ieee80211_hw *hw,
245 int idx, struct survey_info *survey);
246 static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
247 static void ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf);
248 static void ath5k_reset_tsf(struct ieee80211_hw *hw);
249 static int ath5k_beacon_update(struct ieee80211_hw *hw,
250 struct ieee80211_vif *vif);
251 static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
252 struct ieee80211_vif *vif,
253 struct ieee80211_bss_conf *bss_conf,
255 static void ath5k_sw_scan_start(struct ieee80211_hw *hw);
256 static void ath5k_sw_scan_complete(struct ieee80211_hw *hw);
257 static void ath5k_set_coverage_class(struct ieee80211_hw *hw,
260 static const struct ieee80211_ops ath5k_hw_ops = {
262 .start = ath5k_start,
264 .add_interface = ath5k_add_interface,
265 .remove_interface = ath5k_remove_interface,
266 .config = ath5k_config,
267 .prepare_multicast = ath5k_prepare_multicast,
268 .configure_filter = ath5k_configure_filter,
269 .set_key = ath5k_set_key,
270 .get_stats = ath5k_get_stats,
271 .get_survey = ath5k_get_survey,
273 .get_tsf = ath5k_get_tsf,
274 .set_tsf = ath5k_set_tsf,
275 .reset_tsf = ath5k_reset_tsf,
276 .bss_info_changed = ath5k_bss_info_changed,
277 .sw_scan_start = ath5k_sw_scan_start,
278 .sw_scan_complete = ath5k_sw_scan_complete,
279 .set_coverage_class = ath5k_set_coverage_class,
283 * Prototypes - Internal functions
286 static int ath5k_attach(struct pci_dev *pdev,
287 struct ieee80211_hw *hw);
288 static void ath5k_detach(struct pci_dev *pdev,
289 struct ieee80211_hw *hw);
290 /* Channel/mode setup */
291 static inline short ath5k_ieee2mhz(short chan);
292 static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
293 struct ieee80211_channel *channels,
296 static int ath5k_setup_bands(struct ieee80211_hw *hw);
297 static int ath5k_chan_set(struct ath5k_softc *sc,
298 struct ieee80211_channel *chan);
299 static void ath5k_setcurmode(struct ath5k_softc *sc,
301 static void ath5k_mode_setup(struct ath5k_softc *sc);
303 /* Descriptor setup */
304 static int ath5k_desc_alloc(struct ath5k_softc *sc,
305 struct pci_dev *pdev);
306 static void ath5k_desc_free(struct ath5k_softc *sc,
307 struct pci_dev *pdev);
309 static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
310 struct ath5k_buf *bf);
311 static int ath5k_txbuf_setup(struct ath5k_softc *sc,
312 struct ath5k_buf *bf,
313 struct ath5k_txq *txq, int padsize);
315 static inline void ath5k_txbuf_free_skb(struct ath5k_softc *sc,
316 struct ath5k_buf *bf)
321 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
323 dev_kfree_skb_any(bf->skb);
326 bf->desc->ds_data = 0;
329 static inline void ath5k_rxbuf_free_skb(struct ath5k_softc *sc,
330 struct ath5k_buf *bf)
332 struct ath5k_hw *ah = sc->ah;
333 struct ath_common *common = ath5k_hw_common(ah);
338 pci_unmap_single(sc->pdev, bf->skbaddr, common->rx_bufsize,
340 dev_kfree_skb_any(bf->skb);
343 bf->desc->ds_data = 0;
348 static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
349 int qtype, int subtype);
350 static int ath5k_beaconq_setup(struct ath5k_hw *ah);
351 static int ath5k_beaconq_config(struct ath5k_softc *sc);
352 static void ath5k_txq_drainq(struct ath5k_softc *sc,
353 struct ath5k_txq *txq);
354 static void ath5k_txq_cleanup(struct ath5k_softc *sc);
355 static void ath5k_txq_release(struct ath5k_softc *sc);
357 static int ath5k_rx_start(struct ath5k_softc *sc);
358 static void ath5k_rx_stop(struct ath5k_softc *sc);
359 static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
361 struct ath5k_rx_status *rs);
362 static void ath5k_tasklet_rx(unsigned long data);
364 static void ath5k_tx_processq(struct ath5k_softc *sc,
365 struct ath5k_txq *txq);
366 static void ath5k_tasklet_tx(unsigned long data);
367 /* Beacon handling */
368 static int ath5k_beacon_setup(struct ath5k_softc *sc,
369 struct ath5k_buf *bf);
370 static void ath5k_beacon_send(struct ath5k_softc *sc);
371 static void ath5k_beacon_config(struct ath5k_softc *sc);
372 static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
373 static void ath5k_tasklet_beacon(unsigned long data);
374 static void ath5k_tasklet_ani(unsigned long data);
376 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
378 u64 tsf = ath5k_hw_get_tsf64(ah);
380 if ((tsf & 0x7fff) < rstamp)
383 return (tsf & ~0x7fff) | rstamp;
386 /* Interrupt handling */
387 static int ath5k_init(struct ath5k_softc *sc);
388 static int ath5k_stop_locked(struct ath5k_softc *sc);
389 static int ath5k_stop_hw(struct ath5k_softc *sc);
390 static irqreturn_t ath5k_intr(int irq, void *dev_id);
391 static void ath5k_tasklet_reset(unsigned long data);
393 static void ath5k_tasklet_calibrate(unsigned long data);
396 * Module init/exit functions
405 ret = pci_register_driver(&ath5k_pci_driver);
407 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
417 pci_unregister_driver(&ath5k_pci_driver);
419 ath5k_debug_finish();
422 module_init(init_ath5k_pci);
423 module_exit(exit_ath5k_pci);
426 /********************\
427 * PCI Initialization *
428 \********************/
431 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
433 const char *name = "xxxxx";
436 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
437 if (srev_names[i].sr_type != type)
440 if ((val & 0xf0) == srev_names[i].sr_val)
441 name = srev_names[i].sr_name;
443 if ((val & 0xff) == srev_names[i].sr_val) {
444 name = srev_names[i].sr_name;
451 static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset)
453 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
454 return ath5k_hw_reg_read(ah, reg_offset);
457 static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
459 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
460 ath5k_hw_reg_write(ah, val, reg_offset);
463 static const struct ath_ops ath5k_common_ops = {
464 .read = ath5k_ioread32,
465 .write = ath5k_iowrite32,
469 ath5k_pci_probe(struct pci_dev *pdev,
470 const struct pci_device_id *id)
473 struct ath5k_softc *sc;
474 struct ath_common *common;
475 struct ieee80211_hw *hw;
479 ret = pci_enable_device(pdev);
481 dev_err(&pdev->dev, "can't enable device\n");
485 /* XXX 32-bit addressing only */
486 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
488 dev_err(&pdev->dev, "32-bit DMA not available\n");
493 * Cache line size is used to size and align various
494 * structures used to communicate with the hardware.
496 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
499 * Linux 2.4.18 (at least) writes the cache line size
500 * register as a 16-bit wide register which is wrong.
501 * We must have this setup properly for rx buffer
502 * DMA to work so force a reasonable value here if it
505 csz = L1_CACHE_BYTES >> 2;
506 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
509 * The default setting of latency timer yields poor results,
510 * set it to the value used by other systems. It may be worth
511 * tweaking this setting more.
513 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
515 /* Enable bus mastering */
516 pci_set_master(pdev);
519 * Disable the RETRY_TIMEOUT register (0x41) to keep
520 * PCI Tx retries from interfering with C3 CPU state.
522 pci_write_config_byte(pdev, 0x41, 0);
524 ret = pci_request_region(pdev, 0, "ath5k");
526 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
530 mem = pci_iomap(pdev, 0, 0);
532 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
538 * Allocate hw (mac80211 main struct)
539 * and hw->priv (driver private data)
541 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
543 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
548 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
550 /* Initialize driver private data */
551 SET_IEEE80211_DEV(hw, &pdev->dev);
552 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
553 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
554 IEEE80211_HW_SIGNAL_DBM;
556 hw->wiphy->interface_modes =
557 BIT(NL80211_IFTYPE_AP) |
558 BIT(NL80211_IFTYPE_STATION) |
559 BIT(NL80211_IFTYPE_ADHOC) |
560 BIT(NL80211_IFTYPE_MESH_POINT);
562 hw->extra_tx_headroom = 2;
563 hw->channel_change_time = 5000;
568 ath5k_debug_init_device(sc);
571 * Mark the device as detached to avoid processing
572 * interrupts until setup is complete.
574 __set_bit(ATH_STAT_INVALID, sc->status);
576 sc->iobase = mem; /* So we can unmap it on detach */
577 sc->opmode = NL80211_IFTYPE_STATION;
579 mutex_init(&sc->lock);
580 spin_lock_init(&sc->rxbuflock);
581 spin_lock_init(&sc->txbuflock);
582 spin_lock_init(&sc->block);
584 /* Set private data */
585 pci_set_drvdata(pdev, sc);
587 /* Setup interrupt handler */
588 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
590 ATH5K_ERR(sc, "request_irq failed\n");
594 /*If we passed the test malloc a ath5k_hw struct*/
595 sc->ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL);
598 ATH5K_ERR(sc, "out of memory\n");
603 sc->ah->ah_iobase = sc->iobase;
604 common = ath5k_hw_common(sc->ah);
605 common->ops = &ath5k_common_ops;
608 common->cachelsz = csz << 2; /* convert to bytes */
610 /* Initialize device */
611 ret = ath5k_hw_attach(sc);
616 /* set up multi-rate retry capabilities */
617 if (sc->ah->ah_version == AR5K_AR5212) {
619 hw->max_rate_tries = 11;
622 /* Finish private driver data initialization */
623 ret = ath5k_attach(pdev, hw);
627 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
628 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
630 sc->ah->ah_phy_revision);
632 if (!sc->ah->ah_single_chip) {
633 /* Single chip radio (!RF5111) */
634 if (sc->ah->ah_radio_5ghz_revision &&
635 !sc->ah->ah_radio_2ghz_revision) {
636 /* No 5GHz support -> report 2GHz radio */
637 if (!test_bit(AR5K_MODE_11A,
638 sc->ah->ah_capabilities.cap_mode)) {
639 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
640 ath5k_chip_name(AR5K_VERSION_RAD,
641 sc->ah->ah_radio_5ghz_revision),
642 sc->ah->ah_radio_5ghz_revision);
643 /* No 2GHz support (5110 and some
644 * 5Ghz only cards) -> report 5Ghz radio */
645 } else if (!test_bit(AR5K_MODE_11B,
646 sc->ah->ah_capabilities.cap_mode)) {
647 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
648 ath5k_chip_name(AR5K_VERSION_RAD,
649 sc->ah->ah_radio_5ghz_revision),
650 sc->ah->ah_radio_5ghz_revision);
651 /* Multiband radio */
653 ATH5K_INFO(sc, "RF%s multiband radio found"
655 ath5k_chip_name(AR5K_VERSION_RAD,
656 sc->ah->ah_radio_5ghz_revision),
657 sc->ah->ah_radio_5ghz_revision);
660 /* Multi chip radio (RF5111 - RF2111) ->
661 * report both 2GHz/5GHz radios */
662 else if (sc->ah->ah_radio_5ghz_revision &&
663 sc->ah->ah_radio_2ghz_revision){
664 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
665 ath5k_chip_name(AR5K_VERSION_RAD,
666 sc->ah->ah_radio_5ghz_revision),
667 sc->ah->ah_radio_5ghz_revision);
668 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
669 ath5k_chip_name(AR5K_VERSION_RAD,
670 sc->ah->ah_radio_2ghz_revision),
671 sc->ah->ah_radio_2ghz_revision);
676 /* ready to process interrupts */
677 __clear_bit(ATH_STAT_INVALID, sc->status);
681 ath5k_hw_detach(sc->ah);
683 free_irq(pdev->irq, sc);
687 ieee80211_free_hw(hw);
689 pci_iounmap(pdev, mem);
691 pci_release_region(pdev, 0);
693 pci_disable_device(pdev);
698 static void __devexit
699 ath5k_pci_remove(struct pci_dev *pdev)
701 struct ath5k_softc *sc = pci_get_drvdata(pdev);
703 ath5k_debug_finish_device(sc);
704 ath5k_detach(pdev, sc->hw);
705 ath5k_hw_detach(sc->ah);
707 free_irq(pdev->irq, sc);
708 pci_iounmap(pdev, sc->iobase);
709 pci_release_region(pdev, 0);
710 pci_disable_device(pdev);
711 ieee80211_free_hw(sc->hw);
714 #ifdef CONFIG_PM_SLEEP
715 static int ath5k_pci_suspend(struct device *dev)
717 struct ath5k_softc *sc = pci_get_drvdata(to_pci_dev(dev));
723 static int ath5k_pci_resume(struct device *dev)
725 struct pci_dev *pdev = to_pci_dev(dev);
726 struct ath5k_softc *sc = pci_get_drvdata(pdev);
729 * Suspend/Resume resets the PCI configuration space, so we have to
730 * re-disable the RETRY_TIMEOUT register (0x41) to keep
731 * PCI Tx retries from interfering with C3 CPU state
733 pci_write_config_byte(pdev, 0x41, 0);
735 ath5k_led_enable(sc);
738 #endif /* CONFIG_PM_SLEEP */
741 /***********************\
742 * Driver Initialization *
743 \***********************/
745 static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
747 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
748 struct ath5k_softc *sc = hw->priv;
749 struct ath_regulatory *regulatory = ath5k_hw_regulatory(sc->ah);
751 return ath_reg_notifier_apply(wiphy, request, regulatory);
755 ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
757 struct ath5k_softc *sc = hw->priv;
758 struct ath5k_hw *ah = sc->ah;
759 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
760 u8 mac[ETH_ALEN] = {};
763 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
766 * Check if the MAC has multi-rate retry support.
767 * We do this by trying to setup a fake extended
768 * descriptor. MAC's that don't have support will
769 * return false w/o doing anything. MAC's that do
770 * support it will return true w/o doing anything.
772 ret = ath5k_hw_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
777 __set_bit(ATH_STAT_MRRETRY, sc->status);
780 * Collect the channel list. The 802.11 layer
781 * is resposible for filtering this list based
782 * on settings like the phy mode and regulatory
783 * domain restrictions.
785 ret = ath5k_setup_bands(hw);
787 ATH5K_ERR(sc, "can't get channels\n");
791 /* NB: setup here so ath5k_rate_update is happy */
792 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
793 ath5k_setcurmode(sc, AR5K_MODE_11A);
795 ath5k_setcurmode(sc, AR5K_MODE_11B);
798 * Allocate tx+rx descriptors and populate the lists.
800 ret = ath5k_desc_alloc(sc, pdev);
802 ATH5K_ERR(sc, "can't allocate descriptors\n");
807 * Allocate hardware transmit queues: one queue for
808 * beacon frames and one data queue for each QoS
809 * priority. Note that hw functions handle reseting
810 * these queues at the needed time.
812 ret = ath5k_beaconq_setup(ah);
814 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
818 sc->cabq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0);
819 if (IS_ERR(sc->cabq)) {
820 ATH5K_ERR(sc, "can't setup cab queue\n");
821 ret = PTR_ERR(sc->cabq);
825 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
826 if (IS_ERR(sc->txq)) {
827 ATH5K_ERR(sc, "can't setup xmit queue\n");
828 ret = PTR_ERR(sc->txq);
832 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
833 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
834 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
835 tasklet_init(&sc->calib, ath5k_tasklet_calibrate, (unsigned long)sc);
836 tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc);
837 tasklet_init(&sc->ani_tasklet, ath5k_tasklet_ani, (unsigned long)sc);
839 ret = ath5k_eeprom_read_mac(ah, mac);
841 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
846 SET_IEEE80211_PERM_ADDR(hw, mac);
847 /* All MAC address bits matter for ACKs */
848 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
849 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
851 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
852 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
854 ATH5K_ERR(sc, "can't initialize regulatory system\n");
858 ret = ieee80211_register_hw(hw);
860 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
864 if (!ath_is_world_regd(regulatory))
865 regulatory_hint(hw->wiphy, regulatory->alpha2);
869 ath5k_sysfs_register(sc);
873 ath5k_txq_release(sc);
875 ath5k_hw_release_tx_queue(ah, sc->bhalq);
877 ath5k_desc_free(sc, pdev);
883 ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
885 struct ath5k_softc *sc = hw->priv;
888 * NB: the order of these is important:
889 * o call the 802.11 layer before detaching ath5k_hw to
890 * insure callbacks into the driver to delete global
891 * key cache entries can be handled
892 * o reclaim the tx queue data structures after calling
893 * the 802.11 layer as we'll get called back to reclaim
894 * node state and potentially want to use them
895 * o to cleanup the tx queues the hal is called, so detach
897 * XXX: ??? detach ath5k_hw ???
898 * Other than that, it's straightforward...
900 ieee80211_unregister_hw(hw);
901 ath5k_desc_free(sc, pdev);
902 ath5k_txq_release(sc);
903 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
904 ath5k_unregister_leds(sc);
906 ath5k_sysfs_unregister(sc);
908 * NB: can't reclaim these until after ieee80211_ifdetach
909 * returns because we'll get called back to reclaim node
910 * state and potentially want to use them.
917 /********************\
918 * Channel/mode setup *
919 \********************/
922 * Convert IEEE channel number to MHz frequency.
925 ath5k_ieee2mhz(short chan)
927 if (chan <= 14 || chan >= 27)
928 return ieee80211chan2mhz(chan);
930 return 2212 + chan * 20;
934 * Returns true for the channel numbers used without all_channels modparam.
936 static bool ath5k_is_standard_channel(short chan)
938 return ((chan <= 14) ||
940 ((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
942 ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
944 ((chan & 3) == 1 && chan >= 149 && chan <= 165));
948 ath5k_copy_channels(struct ath5k_hw *ah,
949 struct ieee80211_channel *channels,
953 unsigned int i, count, size, chfreq, freq, ch;
955 if (!test_bit(mode, ah->ah_modes))
960 case AR5K_MODE_11A_TURBO:
961 /* 1..220, but 2GHz frequencies are filtered by check_channel */
963 chfreq = CHANNEL_5GHZ;
967 case AR5K_MODE_11G_TURBO:
969 chfreq = CHANNEL_2GHZ;
972 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
976 for (i = 0, count = 0; i < size && max > 0; i++) {
978 freq = ath5k_ieee2mhz(ch);
980 /* Check if channel is supported by the chipset */
981 if (!ath5k_channel_ok(ah, freq, chfreq))
984 if (!modparam_all_channels && !ath5k_is_standard_channel(ch))
987 /* Write channel info and increment counter */
988 channels[count].center_freq = freq;
989 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
990 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
994 channels[count].hw_value = chfreq | CHANNEL_OFDM;
996 case AR5K_MODE_11A_TURBO:
997 case AR5K_MODE_11G_TURBO:
998 channels[count].hw_value = chfreq |
999 CHANNEL_OFDM | CHANNEL_TURBO;
1002 channels[count].hw_value = CHANNEL_B;
1013 ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
1017 for (i = 0; i < AR5K_MAX_RATES; i++)
1018 sc->rate_idx[b->band][i] = -1;
1020 for (i = 0; i < b->n_bitrates; i++) {
1021 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
1022 if (b->bitrates[i].hw_value_short)
1023 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
1028 ath5k_setup_bands(struct ieee80211_hw *hw)
1030 struct ath5k_softc *sc = hw->priv;
1031 struct ath5k_hw *ah = sc->ah;
1032 struct ieee80211_supported_band *sband;
1033 int max_c, count_c = 0;
1036 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
1037 max_c = ARRAY_SIZE(sc->channels);
1040 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
1041 sband->band = IEEE80211_BAND_2GHZ;
1042 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
1044 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
1046 memcpy(sband->bitrates, &ath5k_rates[0],
1047 sizeof(struct ieee80211_rate) * 12);
1048 sband->n_bitrates = 12;
1050 sband->channels = sc->channels;
1051 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1052 AR5K_MODE_11G, max_c);
1054 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
1055 count_c = sband->n_channels;
1057 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
1059 memcpy(sband->bitrates, &ath5k_rates[0],
1060 sizeof(struct ieee80211_rate) * 4);
1061 sband->n_bitrates = 4;
1063 /* 5211 only supports B rates and uses 4bit rate codes
1064 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
1067 if (ah->ah_version == AR5K_AR5211) {
1068 for (i = 0; i < 4; i++) {
1069 sband->bitrates[i].hw_value =
1070 sband->bitrates[i].hw_value & 0xF;
1071 sband->bitrates[i].hw_value_short =
1072 sband->bitrates[i].hw_value_short & 0xF;
1076 sband->channels = sc->channels;
1077 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1078 AR5K_MODE_11B, max_c);
1080 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
1081 count_c = sband->n_channels;
1084 ath5k_setup_rate_idx(sc, sband);
1086 /* 5GHz band, A mode */
1087 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
1088 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
1089 sband->band = IEEE80211_BAND_5GHZ;
1090 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
1092 memcpy(sband->bitrates, &ath5k_rates[4],
1093 sizeof(struct ieee80211_rate) * 8);
1094 sband->n_bitrates = 8;
1096 sband->channels = &sc->channels[count_c];
1097 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1098 AR5K_MODE_11A, max_c);
1100 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
1102 ath5k_setup_rate_idx(sc, sband);
1104 ath5k_debug_dump_bands(sc);
1110 * Set/change channels. We always reset the chip.
1111 * To accomplish this we must first cleanup any pending DMA,
1112 * then restart stuff after a la ath5k_init.
1114 * Called with sc->lock.
1117 ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1119 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
1120 "channel set, resetting (%u -> %u MHz)\n",
1121 sc->curchan->center_freq, chan->center_freq);
1124 * To switch channels clear any pending DMA operations;
1125 * wait long enough for the RX fifo to drain, reset the
1126 * hardware at the new frequency, and then re-enable
1127 * the relevant bits of the h/w.
1129 return ath5k_reset(sc, chan);
1133 ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1137 if (mode == AR5K_MODE_11A) {
1138 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1140 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1145 ath5k_mode_setup(struct ath5k_softc *sc)
1147 struct ath5k_hw *ah = sc->ah;
1150 /* configure rx filter */
1151 rfilt = sc->filter_flags;
1152 ath5k_hw_set_rx_filter(ah, rfilt);
1154 if (ath5k_hw_hasbssidmask(ah))
1155 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1157 /* configure operational mode */
1158 ath5k_hw_set_opmode(ah, sc->opmode);
1160 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "mode setup opmode %d\n", sc->opmode);
1161 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1165 ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
1169 /* return base rate on errors */
1170 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
1171 "hw_rix out of bounds: %x\n", hw_rix))
1174 rix = sc->rate_idx[sc->curband->band][hw_rix];
1175 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
1186 struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
1188 struct ath_common *common = ath5k_hw_common(sc->ah);
1189 struct sk_buff *skb;
1192 * Allocate buffer with headroom_needed space for the
1193 * fake physical layer header at the start.
1195 skb = ath_rxbuf_alloc(common,
1200 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1201 common->rx_bufsize);
1205 *skb_addr = pci_map_single(sc->pdev,
1206 skb->data, common->rx_bufsize,
1207 PCI_DMA_FROMDEVICE);
1208 if (unlikely(pci_dma_mapping_error(sc->pdev, *skb_addr))) {
1209 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1217 ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1219 struct ath5k_hw *ah = sc->ah;
1220 struct sk_buff *skb = bf->skb;
1221 struct ath5k_desc *ds;
1225 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
1232 * Setup descriptors. For receive we always terminate
1233 * the descriptor list with a self-linked entry so we'll
1234 * not get overrun under high load (as can happen with a
1235 * 5212 when ANI processing enables PHY error frames).
1237 * To ensure the last descriptor is self-linked we create
1238 * each descriptor as self-linked and add it to the end. As
1239 * each additional descriptor is added the previous self-linked
1240 * entry is "fixed" naturally. This should be safe even
1241 * if DMA is happening. When processing RX interrupts we
1242 * never remove/process the last, self-linked, entry on the
1243 * descriptor list. This ensures the hardware always has
1244 * someplace to write a new frame.
1247 ds->ds_link = bf->daddr; /* link to self */
1248 ds->ds_data = bf->skbaddr;
1249 ret = ath5k_hw_setup_rx_desc(ah, ds, ah->common.rx_bufsize, 0);
1251 ATH5K_ERR(sc, "%s: could not setup RX desc\n", __func__);
1255 if (sc->rxlink != NULL)
1256 *sc->rxlink = bf->daddr;
1257 sc->rxlink = &ds->ds_link;
1261 static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1263 struct ieee80211_hdr *hdr;
1264 enum ath5k_pkt_type htype;
1267 hdr = (struct ieee80211_hdr *)skb->data;
1268 fc = hdr->frame_control;
1270 if (ieee80211_is_beacon(fc))
1271 htype = AR5K_PKT_TYPE_BEACON;
1272 else if (ieee80211_is_probe_resp(fc))
1273 htype = AR5K_PKT_TYPE_PROBE_RESP;
1274 else if (ieee80211_is_atim(fc))
1275 htype = AR5K_PKT_TYPE_ATIM;
1276 else if (ieee80211_is_pspoll(fc))
1277 htype = AR5K_PKT_TYPE_PSPOLL;
1279 htype = AR5K_PKT_TYPE_NORMAL;
1285 ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
1286 struct ath5k_txq *txq, int padsize)
1288 struct ath5k_hw *ah = sc->ah;
1289 struct ath5k_desc *ds = bf->desc;
1290 struct sk_buff *skb = bf->skb;
1291 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1292 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
1293 struct ieee80211_rate *rate;
1294 unsigned int mrr_rate[3], mrr_tries[3];
1301 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
1303 /* XXX endianness */
1304 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1307 rate = ieee80211_get_tx_rate(sc->hw, info);
1309 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
1310 flags |= AR5K_TXDESC_NOACK;
1312 rc_flags = info->control.rates[0].flags;
1313 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
1314 rate->hw_value_short : rate->hw_value;
1318 /* FIXME: If we are in g mode and rate is a CCK rate
1319 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1320 * from tx power (value is in dB units already) */
1321 if (info->control.hw_key) {
1322 keyidx = info->control.hw_key->hw_key_idx;
1323 pktlen += info->control.hw_key->icv_len;
1325 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1326 flags |= AR5K_TXDESC_RTSENA;
1327 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1328 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
1329 sc->vif, pktlen, info));
1331 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1332 flags |= AR5K_TXDESC_CTSENA;
1333 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1334 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
1335 sc->vif, pktlen, info));
1337 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1338 ieee80211_get_hdrlen_from_skb(skb), padsize,
1339 get_hw_packet_type(skb),
1340 (sc->power_level * 2),
1342 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags,
1343 cts_rate, duration);
1347 memset(mrr_rate, 0, sizeof(mrr_rate));
1348 memset(mrr_tries, 0, sizeof(mrr_tries));
1349 for (i = 0; i < 3; i++) {
1350 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
1354 mrr_rate[i] = rate->hw_value;
1355 mrr_tries[i] = info->control.rates[i + 1].count;
1358 ath5k_hw_setup_mrr_tx_desc(ah, ds,
1359 mrr_rate[0], mrr_tries[0],
1360 mrr_rate[1], mrr_tries[1],
1361 mrr_rate[2], mrr_tries[2]);
1364 ds->ds_data = bf->skbaddr;
1366 spin_lock_bh(&txq->lock);
1367 list_add_tail(&bf->list, &txq->q);
1368 if (txq->link == NULL) /* is this first packet? */
1369 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
1370 else /* no, so only link it */
1371 *txq->link = bf->daddr;
1373 txq->link = &ds->ds_link;
1374 ath5k_hw_start_tx_dma(ah, txq->qnum);
1376 spin_unlock_bh(&txq->lock);
1380 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1384 /*******************\
1385 * Descriptors setup *
1386 \*******************/
1389 ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1391 struct ath5k_desc *ds;
1392 struct ath5k_buf *bf;
1397 /* allocate descriptors */
1398 sc->desc_len = sizeof(struct ath5k_desc) *
1399 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1400 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1401 if (sc->desc == NULL) {
1402 ATH5K_ERR(sc, "can't allocate descriptors\n");
1407 da = sc->desc_daddr;
1408 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1409 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1411 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1412 sizeof(struct ath5k_buf), GFP_KERNEL);
1414 ATH5K_ERR(sc, "can't allocate bufptr\n");
1420 INIT_LIST_HEAD(&sc->rxbuf);
1421 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1424 list_add_tail(&bf->list, &sc->rxbuf);
1427 INIT_LIST_HEAD(&sc->txbuf);
1428 sc->txbuf_len = ATH_TXBUF;
1429 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1430 da += sizeof(*ds)) {
1433 list_add_tail(&bf->list, &sc->txbuf);
1443 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1450 ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1452 struct ath5k_buf *bf;
1454 ath5k_txbuf_free_skb(sc, sc->bbuf);
1455 list_for_each_entry(bf, &sc->txbuf, list)
1456 ath5k_txbuf_free_skb(sc, bf);
1457 list_for_each_entry(bf, &sc->rxbuf, list)
1458 ath5k_rxbuf_free_skb(sc, bf);
1460 /* Free memory associated with all descriptors */
1461 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1478 static struct ath5k_txq *
1479 ath5k_txq_setup(struct ath5k_softc *sc,
1480 int qtype, int subtype)
1482 struct ath5k_hw *ah = sc->ah;
1483 struct ath5k_txq *txq;
1484 struct ath5k_txq_info qi = {
1485 .tqi_subtype = subtype,
1486 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1487 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1488 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1493 * Enable interrupts only for EOL and DESC conditions.
1494 * We mark tx descriptors to receive a DESC interrupt
1495 * when a tx queue gets deep; otherwise waiting for the
1496 * EOL to reap descriptors. Note that this is done to
1497 * reduce interrupt load and this only defers reaping
1498 * descriptors, never transmitting frames. Aside from
1499 * reducing interrupts this also permits more concurrency.
1500 * The only potential downside is if the tx queue backs
1501 * up in which case the top half of the kernel may backup
1502 * due to a lack of tx descriptors.
1504 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1505 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1506 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1509 * NB: don't print a message, this happens
1510 * normally on parts with too few tx queues
1512 return ERR_PTR(qnum);
1514 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1515 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1516 qnum, ARRAY_SIZE(sc->txqs));
1517 ath5k_hw_release_tx_queue(ah, qnum);
1518 return ERR_PTR(-EINVAL);
1520 txq = &sc->txqs[qnum];
1524 INIT_LIST_HEAD(&txq->q);
1525 spin_lock_init(&txq->lock);
1528 return &sc->txqs[qnum];
1532 ath5k_beaconq_setup(struct ath5k_hw *ah)
1534 struct ath5k_txq_info qi = {
1535 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1536 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1537 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1538 /* NB: for dynamic turbo, don't enable any other interrupts */
1539 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1542 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1546 ath5k_beaconq_config(struct ath5k_softc *sc)
1548 struct ath5k_hw *ah = sc->ah;
1549 struct ath5k_txq_info qi;
1552 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1556 if (sc->opmode == NL80211_IFTYPE_AP ||
1557 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
1559 * Always burst out beacon and CAB traffic
1560 * (aifs = cwmin = cwmax = 0)
1565 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
1567 * Adhoc mode; backoff between 0 and (2 * cw_min).
1571 qi.tqi_cw_max = 2 * ah->ah_cw_min;
1574 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1575 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1576 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1578 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
1580 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1581 "hardware queue!\n", __func__);
1584 ret = ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */
1588 /* reconfigure cabq with ready time to 80% of beacon_interval */
1589 ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1593 qi.tqi_ready_time = (sc->bintval * 80) / 100;
1594 ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1598 ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB);
1604 ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1606 struct ath5k_buf *bf, *bf0;
1609 * NB: this assumes output has been stopped and
1610 * we do not need to block ath5k_tx_tasklet
1612 spin_lock_bh(&txq->lock);
1613 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1614 ath5k_debug_printtxbuf(sc, bf);
1616 ath5k_txbuf_free_skb(sc, bf);
1618 spin_lock_bh(&sc->txbuflock);
1619 list_move_tail(&bf->list, &sc->txbuf);
1621 spin_unlock_bh(&sc->txbuflock);
1624 spin_unlock_bh(&txq->lock);
1628 * Drain the transmit queues and reclaim resources.
1631 ath5k_txq_cleanup(struct ath5k_softc *sc)
1633 struct ath5k_hw *ah = sc->ah;
1636 /* XXX return value */
1637 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1638 /* don't touch the hardware if marked invalid */
1639 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1640 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
1641 ath5k_hw_get_txdp(ah, sc->bhalq));
1642 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1643 if (sc->txqs[i].setup) {
1644 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1645 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1648 ath5k_hw_get_txdp(ah,
1654 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1655 if (sc->txqs[i].setup)
1656 ath5k_txq_drainq(sc, &sc->txqs[i]);
1660 ath5k_txq_release(struct ath5k_softc *sc)
1662 struct ath5k_txq *txq = sc->txqs;
1665 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1667 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1680 * Enable the receive h/w following a reset.
1683 ath5k_rx_start(struct ath5k_softc *sc)
1685 struct ath5k_hw *ah = sc->ah;
1686 struct ath_common *common = ath5k_hw_common(ah);
1687 struct ath5k_buf *bf;
1690 common->rx_bufsize = roundup(IEEE80211_MAX_LEN, common->cachelsz);
1692 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n",
1693 common->cachelsz, common->rx_bufsize);
1695 spin_lock_bh(&sc->rxbuflock);
1697 list_for_each_entry(bf, &sc->rxbuf, list) {
1698 ret = ath5k_rxbuf_setup(sc, bf);
1700 spin_unlock_bh(&sc->rxbuflock);
1704 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1705 ath5k_hw_set_rxdp(ah, bf->daddr);
1706 spin_unlock_bh(&sc->rxbuflock);
1708 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
1709 ath5k_mode_setup(sc); /* set filters, etc. */
1710 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1718 * Disable the receive h/w in preparation for a reset.
1721 ath5k_rx_stop(struct ath5k_softc *sc)
1723 struct ath5k_hw *ah = sc->ah;
1725 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
1726 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1727 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
1729 ath5k_debug_printrxbuffs(sc, ah);
1731 sc->rxlink = NULL; /* just in case */
1735 ath5k_rx_decrypted(struct ath5k_softc *sc, struct sk_buff *skb,
1736 struct ath5k_rx_status *rs)
1738 struct ath5k_hw *ah = sc->ah;
1739 struct ath_common *common = ath5k_hw_common(ah);
1740 struct ieee80211_hdr *hdr = (void *)skb->data;
1741 unsigned int keyix, hlen;
1743 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1744 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1745 return RX_FLAG_DECRYPTED;
1747 /* Apparently when a default key is used to decrypt the packet
1748 the hw does not set the index used to decrypt. In such cases
1749 get the index from the packet. */
1750 hlen = ieee80211_hdrlen(hdr->frame_control);
1751 if (ieee80211_has_protected(hdr->frame_control) &&
1752 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1753 skb->len >= hlen + 4) {
1754 keyix = skb->data[hlen + 3] >> 6;
1756 if (test_bit(keyix, common->keymap))
1757 return RX_FLAG_DECRYPTED;
1765 ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1766 struct ieee80211_rx_status *rxs)
1768 struct ath_common *common = ath5k_hw_common(sc->ah);
1771 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1773 if (ieee80211_is_beacon(mgmt->frame_control) &&
1774 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1775 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) == 0) {
1777 * Received an IBSS beacon with the same BSSID. Hardware *must*
1778 * have updated the local TSF. We have to work around various
1779 * hardware bugs, though...
1781 tsf = ath5k_hw_get_tsf64(sc->ah);
1782 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1783 hw_tu = TSF_TO_TU(tsf);
1785 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1786 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1787 (unsigned long long)bc_tstamp,
1788 (unsigned long long)rxs->mactime,
1789 (unsigned long long)(rxs->mactime - bc_tstamp),
1790 (unsigned long long)tsf);
1793 * Sometimes the HW will give us a wrong tstamp in the rx
1794 * status, causing the timestamp extension to go wrong.
1795 * (This seems to happen especially with beacon frames bigger
1796 * than 78 byte (incl. FCS))
1797 * But we know that the receive timestamp must be later than the
1798 * timestamp of the beacon since HW must have synced to that.
1800 * NOTE: here we assume mactime to be after the frame was
1801 * received, not like mac80211 which defines it at the start.
1803 if (bc_tstamp > rxs->mactime) {
1804 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1805 "fixing mactime from %llx to %llx\n",
1806 (unsigned long long)rxs->mactime,
1807 (unsigned long long)tsf);
1812 * Local TSF might have moved higher than our beacon timers,
1813 * in that case we have to update them to continue sending
1814 * beacons. This also takes care of synchronizing beacon sending
1815 * times with other stations.
1817 if (hw_tu >= sc->nexttbtt)
1818 ath5k_beacon_update_timers(sc, bc_tstamp);
1823 ath5k_update_beacon_rssi(struct ath5k_softc *sc, struct sk_buff *skb, int rssi)
1825 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1826 struct ath5k_hw *ah = sc->ah;
1827 struct ath_common *common = ath5k_hw_common(ah);
1829 /* only beacons from our BSSID */
1830 if (!ieee80211_is_beacon(mgmt->frame_control) ||
1831 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) != 0)
1834 ah->ah_beacon_rssi_avg = ath5k_moving_average(ah->ah_beacon_rssi_avg,
1837 /* in IBSS mode we should keep RSSI statistics per neighbour */
1838 /* le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS */
1842 * Compute padding position. skb must contains an IEEE 802.11 frame
1844 static int ath5k_common_padpos(struct sk_buff *skb)
1846 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
1847 __le16 frame_control = hdr->frame_control;
1850 if (ieee80211_has_a4(frame_control)) {
1853 if (ieee80211_is_data_qos(frame_control)) {
1854 padpos += IEEE80211_QOS_CTL_LEN;
1861 * This function expects a 802.11 frame and returns the number of
1862 * bytes added, or -1 if we don't have enought header room.
1865 static int ath5k_add_padding(struct sk_buff *skb)
1867 int padpos = ath5k_common_padpos(skb);
1868 int padsize = padpos & 3;
1870 if (padsize && skb->len>padpos) {
1872 if (skb_headroom(skb) < padsize)
1875 skb_push(skb, padsize);
1876 memmove(skb->data, skb->data+padsize, padpos);
1884 * This function expects a 802.11 frame and returns the number of
1888 static int ath5k_remove_padding(struct sk_buff *skb)
1890 int padpos = ath5k_common_padpos(skb);
1891 int padsize = padpos & 3;
1893 if (padsize && skb->len>=padpos+padsize) {
1894 memmove(skb->data + padsize, skb->data, padpos);
1895 skb_pull(skb, padsize);
1903 ath5k_receive_frame(struct ath5k_softc *sc, struct sk_buff *skb,
1904 struct ath5k_rx_status *rs)
1906 struct ieee80211_rx_status *rxs;
1908 /* The MAC header is padded to have 32-bit boundary if the
1909 * packet payload is non-zero. The general calculation for
1910 * padsize would take into account odd header lengths:
1911 * padsize = (4 - hdrlen % 4) % 4; However, since only
1912 * even-length headers are used, padding can only be 0 or 2
1913 * bytes and we can optimize this a bit. In addition, we must
1914 * not try to remove padding from short control frames that do
1915 * not have payload. */
1916 ath5k_remove_padding(skb);
1918 rxs = IEEE80211_SKB_RXCB(skb);
1921 if (unlikely(rs->rs_status & AR5K_RXERR_MIC))
1922 rxs->flag |= RX_FLAG_MMIC_ERROR;
1925 * always extend the mac timestamp, since this information is
1926 * also needed for proper IBSS merging.
1928 * XXX: it might be too late to do it here, since rs_tstamp is
1929 * 15bit only. that means TSF extension has to be done within
1930 * 32768usec (about 32ms). it might be necessary to move this to
1931 * the interrupt handler, like it is done in madwifi.
1933 * Unfortunately we don't know when the hardware takes the rx
1934 * timestamp (beginning of phy frame, data frame, end of rx?).
1935 * The only thing we know is that it is hardware specific...
1936 * On AR5213 it seems the rx timestamp is at the end of the
1937 * frame, but i'm not sure.
1939 * NOTE: mac80211 defines mactime at the beginning of the first
1940 * data symbol. Since we don't have any time references it's
1941 * impossible to comply to that. This affects IBSS merge only
1942 * right now, so it's not too bad...
1944 rxs->mactime = ath5k_extend_tsf(sc->ah, rs->rs_tstamp);
1945 rxs->flag |= RX_FLAG_TSFT;
1947 rxs->freq = sc->curchan->center_freq;
1948 rxs->band = sc->curband->band;
1950 rxs->signal = sc->ah->ah_noise_floor + rs->rs_rssi;
1952 rxs->antenna = rs->rs_antenna;
1954 if (rs->rs_antenna > 0 && rs->rs_antenna < 5)
1955 sc->stats.antenna_rx[rs->rs_antenna]++;
1957 sc->stats.antenna_rx[0]++; /* invalid */
1959 rxs->rate_idx = ath5k_hw_to_driver_rix(sc, rs->rs_rate);
1960 rxs->flag |= ath5k_rx_decrypted(sc, skb, rs);
1962 if (rxs->rate_idx >= 0 && rs->rs_rate ==
1963 sc->curband->bitrates[rxs->rate_idx].hw_value_short)
1964 rxs->flag |= RX_FLAG_SHORTPRE;
1966 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1968 ath5k_update_beacon_rssi(sc, skb, rs->rs_rssi);
1970 /* check beacons in IBSS mode */
1971 if (sc->opmode == NL80211_IFTYPE_ADHOC)
1972 ath5k_check_ibss_tsf(sc, skb, rxs);
1974 ieee80211_rx(sc->hw, skb);
1977 /** ath5k_frame_receive_ok() - Do we want to receive this frame or not?
1979 * Check if we want to further process this frame or not. Also update
1980 * statistics. Return true if we want this frame, false if not.
1983 ath5k_receive_frame_ok(struct ath5k_softc *sc, struct ath5k_rx_status *rs)
1985 sc->stats.rx_all_count++;
1987 if (unlikely(rs->rs_status)) {
1988 if (rs->rs_status & AR5K_RXERR_CRC)
1989 sc->stats.rxerr_crc++;
1990 if (rs->rs_status & AR5K_RXERR_FIFO)
1991 sc->stats.rxerr_fifo++;
1992 if (rs->rs_status & AR5K_RXERR_PHY) {
1993 sc->stats.rxerr_phy++;
1994 if (rs->rs_phyerr > 0 && rs->rs_phyerr < 32)
1995 sc->stats.rxerr_phy_code[rs->rs_phyerr]++;
1998 if (rs->rs_status & AR5K_RXERR_DECRYPT) {
2000 * Decrypt error. If the error occurred
2001 * because there was no hardware key, then
2002 * let the frame through so the upper layers
2003 * can process it. This is necessary for 5210
2004 * parts which have no way to setup a ``clear''
2007 * XXX do key cache faulting
2009 sc->stats.rxerr_decrypt++;
2010 if (rs->rs_keyix == AR5K_RXKEYIX_INVALID &&
2011 !(rs->rs_status & AR5K_RXERR_CRC))
2014 if (rs->rs_status & AR5K_RXERR_MIC) {
2015 sc->stats.rxerr_mic++;
2019 /* let crypto-error packets fall through in MNTR */
2020 if ((rs->rs_status & ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
2021 sc->opmode != NL80211_IFTYPE_MONITOR)
2025 if (unlikely(rs->rs_more)) {
2026 sc->stats.rxerr_jumbo++;
2033 ath5k_tasklet_rx(unsigned long data)
2035 struct ath5k_rx_status rs = {};
2036 struct sk_buff *skb, *next_skb;
2037 dma_addr_t next_skb_addr;
2038 struct ath5k_softc *sc = (void *)data;
2039 struct ath5k_hw *ah = sc->ah;
2040 struct ath_common *common = ath5k_hw_common(ah);
2041 struct ath5k_buf *bf;
2042 struct ath5k_desc *ds;
2045 spin_lock(&sc->rxbuflock);
2046 if (list_empty(&sc->rxbuf)) {
2047 ATH5K_WARN(sc, "empty rx buf pool\n");
2051 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
2052 BUG_ON(bf->skb == NULL);
2056 /* bail if HW is still using self-linked descriptor */
2057 if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr)
2060 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
2061 if (unlikely(ret == -EINPROGRESS))
2063 else if (unlikely(ret)) {
2064 ATH5K_ERR(sc, "error in processing rx descriptor\n");
2065 sc->stats.rxerr_proc++;
2069 if (ath5k_receive_frame_ok(sc, &rs)) {
2070 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
2073 * If we can't replace bf->skb with a new skb under
2074 * memory pressure, just skip this packet
2079 pci_unmap_single(sc->pdev, bf->skbaddr,
2081 PCI_DMA_FROMDEVICE);
2083 skb_put(skb, rs.rs_datalen);
2085 ath5k_receive_frame(sc, skb, &rs);
2088 bf->skbaddr = next_skb_addr;
2091 list_move_tail(&bf->list, &sc->rxbuf);
2092 } while (ath5k_rxbuf_setup(sc, bf) == 0);
2094 spin_unlock(&sc->rxbuflock);
2103 ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
2105 struct ath5k_tx_status ts = {};
2106 struct ath5k_buf *bf, *bf0;
2107 struct ath5k_desc *ds;
2108 struct sk_buff *skb;
2109 struct ieee80211_tx_info *info;
2112 spin_lock(&txq->lock);
2113 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
2117 * It's possible that the hardware can say the buffer is
2118 * completed when it hasn't yet loaded the ds_link from
2119 * host memory and moved on. If there are more TX
2120 * descriptors in the queue, wait for TXDP to change
2121 * before processing this one.
2123 if (ath5k_hw_get_txdp(sc->ah, txq->qnum) == bf->daddr &&
2124 !list_is_last(&bf->list, &txq->q))
2127 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
2128 if (unlikely(ret == -EINPROGRESS))
2130 else if (unlikely(ret)) {
2131 ATH5K_ERR(sc, "error %d while processing queue %u\n",
2136 sc->stats.tx_all_count++;
2138 info = IEEE80211_SKB_CB(skb);
2141 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
2144 ieee80211_tx_info_clear_status(info);
2145 for (i = 0; i < 4; i++) {
2146 struct ieee80211_tx_rate *r =
2147 &info->status.rates[i];
2149 if (ts.ts_rate[i]) {
2150 r->idx = ath5k_hw_to_driver_rix(sc, ts.ts_rate[i]);
2151 r->count = ts.ts_retry[i];
2158 /* count the successful attempt as well */
2159 info->status.rates[ts.ts_final_idx].count++;
2161 if (unlikely(ts.ts_status)) {
2162 sc->stats.ack_fail++;
2163 if (ts.ts_status & AR5K_TXERR_FILT) {
2164 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
2165 sc->stats.txerr_filt++;
2167 if (ts.ts_status & AR5K_TXERR_XRETRY)
2168 sc->stats.txerr_retry++;
2169 if (ts.ts_status & AR5K_TXERR_FIFO)
2170 sc->stats.txerr_fifo++;
2172 info->flags |= IEEE80211_TX_STAT_ACK;
2173 info->status.ack_signal = ts.ts_rssi;
2177 * Remove MAC header padding before giving the frame
2180 ath5k_remove_padding(skb);
2182 if (ts.ts_antenna > 0 && ts.ts_antenna < 5)
2183 sc->stats.antenna_tx[ts.ts_antenna]++;
2185 sc->stats.antenna_tx[0]++; /* invalid */
2187 ieee80211_tx_status(sc->hw, skb);
2189 spin_lock(&sc->txbuflock);
2190 list_move_tail(&bf->list, &sc->txbuf);
2192 spin_unlock(&sc->txbuflock);
2194 if (likely(list_empty(&txq->q)))
2196 spin_unlock(&txq->lock);
2197 if (sc->txbuf_len > ATH_TXBUF / 5)
2198 ieee80211_wake_queues(sc->hw);
2202 ath5k_tasklet_tx(unsigned long data)
2205 struct ath5k_softc *sc = (void *)data;
2207 for (i=0; i < AR5K_NUM_TX_QUEUES; i++)
2208 if (sc->txqs[i].setup && (sc->ah->ah_txq_isr & BIT(i)))
2209 ath5k_tx_processq(sc, &sc->txqs[i]);
2218 * Setup the beacon frame for transmit.
2221 ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
2223 struct sk_buff *skb = bf->skb;
2224 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2225 struct ath5k_hw *ah = sc->ah;
2226 struct ath5k_desc *ds;
2230 const int padsize = 0;
2232 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
2234 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
2235 "skbaddr %llx\n", skb, skb->data, skb->len,
2236 (unsigned long long)bf->skbaddr);
2237 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
2238 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
2243 antenna = ah->ah_tx_ant;
2245 flags = AR5K_TXDESC_NOACK;
2246 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
2247 ds->ds_link = bf->daddr; /* self-linked */
2248 flags |= AR5K_TXDESC_VEOL;
2253 * If we use multiple antennas on AP and use
2254 * the Sectored AP scenario, switch antenna every
2255 * 4 beacons to make sure everybody hears our AP.
2256 * When a client tries to associate, hw will keep
2257 * track of the tx antenna to be used for this client
2258 * automaticaly, based on ACKed packets.
2260 * Note: AP still listens and transmits RTS on the
2261 * default antenna which is supposed to be an omni.
2263 * Note2: On sectored scenarios it's possible to have
2264 * multiple antennas (1omni -the default- and 14 sectors)
2265 * so if we choose to actually support this mode we need
2266 * to allow user to set how many antennas we have and tweak
2267 * the code below to send beacons on all of them.
2269 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
2270 antenna = sc->bsent & 4 ? 2 : 1;
2273 /* FIXME: If we are in g mode and rate is a CCK rate
2274 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
2275 * from tx power (value is in dB units already) */
2276 ds->ds_data = bf->skbaddr;
2277 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
2278 ieee80211_get_hdrlen_from_skb(skb), padsize,
2279 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
2280 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2281 1, AR5K_TXKEYIX_INVALID,
2282 antenna, flags, 0, 0);
2288 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
2293 * Transmit a beacon frame at SWBA. Dynamic updates to the
2294 * frame contents are done as needed and the slot time is
2295 * also adjusted based on current state.
2297 * This is called from software irq context (beacontq or restq
2298 * tasklets) or user context from ath5k_beacon_config.
2301 ath5k_beacon_send(struct ath5k_softc *sc)
2303 struct ath5k_buf *bf = sc->bbuf;
2304 struct ath5k_hw *ah = sc->ah;
2305 struct sk_buff *skb;
2307 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
2309 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
2310 sc->opmode == NL80211_IFTYPE_MONITOR)) {
2311 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
2315 * Check if the previous beacon has gone out. If
2316 * not don't don't try to post another, skip this
2317 * period and wait for the next. Missed beacons
2318 * indicate a problem and should not occur. If we
2319 * miss too many consecutive beacons reset the device.
2321 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
2323 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2324 "missed %u consecutive beacons\n", sc->bmisscount);
2325 if (sc->bmisscount > 10) { /* NB: 10 is a guess */
2326 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2327 "stuck beacon time (%u missed)\n",
2329 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2330 "stuck beacon, resetting\n");
2331 tasklet_schedule(&sc->restq);
2335 if (unlikely(sc->bmisscount != 0)) {
2336 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2337 "resume beacon xmit after %u misses\n",
2343 * Stop any current dma and put the new frame on the queue.
2344 * This should never fail since we check above that no frames
2345 * are still pending on the queue.
2347 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
2348 ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq);
2349 /* NB: hw still stops DMA, so proceed */
2352 /* refresh the beacon for AP mode */
2353 if (sc->opmode == NL80211_IFTYPE_AP)
2354 ath5k_beacon_update(sc->hw, sc->vif);
2356 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
2357 ath5k_hw_start_tx_dma(ah, sc->bhalq);
2358 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
2359 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2361 skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
2363 ath5k_tx_queue(sc->hw, skb, sc->cabq);
2364 skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
2372 * ath5k_beacon_update_timers - update beacon timers
2374 * @sc: struct ath5k_softc pointer we are operating on
2375 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2376 * beacon timer update based on the current HW TSF.
2378 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2379 * of a received beacon or the current local hardware TSF and write it to the
2380 * beacon timer registers.
2382 * This is called in a variety of situations, e.g. when a beacon is received,
2383 * when a TSF update has been detected, but also when an new IBSS is created or
2384 * when we otherwise know we have to update the timers, but we keep it in this
2385 * function to have it all together in one place.
2388 ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
2390 struct ath5k_hw *ah = sc->ah;
2391 u32 nexttbtt, intval, hw_tu, bc_tu;
2394 intval = sc->bintval & AR5K_BEACON_PERIOD;
2395 if (WARN_ON(!intval))
2398 /* beacon TSF converted to TU */
2399 bc_tu = TSF_TO_TU(bc_tsf);
2401 /* current TSF converted to TU */
2402 hw_tsf = ath5k_hw_get_tsf64(ah);
2403 hw_tu = TSF_TO_TU(hw_tsf);
2406 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2409 * no beacons received, called internally.
2410 * just need to refresh timers based on HW TSF.
2412 nexttbtt = roundup(hw_tu + FUDGE, intval);
2413 } else if (bc_tsf == 0) {
2415 * no beacon received, probably called by ath5k_reset_tsf().
2416 * reset TSF to start with 0.
2419 intval |= AR5K_BEACON_RESET_TSF;
2420 } else if (bc_tsf > hw_tsf) {
2422 * beacon received, SW merge happend but HW TSF not yet updated.
2423 * not possible to reconfigure timers yet, but next time we
2424 * receive a beacon with the same BSSID, the hardware will
2425 * automatically update the TSF and then we need to reconfigure
2428 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2429 "need to wait for HW TSF sync\n");
2433 * most important case for beacon synchronization between STA.
2435 * beacon received and HW TSF has been already updated by HW.
2436 * update next TBTT based on the TSF of the beacon, but make
2437 * sure it is ahead of our local TSF timer.
2439 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2443 sc->nexttbtt = nexttbtt;
2445 intval |= AR5K_BEACON_ENA;
2446 ath5k_hw_init_beacon(ah, nexttbtt, intval);
2449 * debugging output last in order to preserve the time critical aspect
2453 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2454 "reconfigured timers based on HW TSF\n");
2455 else if (bc_tsf == 0)
2456 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2457 "reset HW TSF and timers\n");
2459 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2460 "updated timers based on beacon TSF\n");
2462 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2463 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2464 (unsigned long long) bc_tsf,
2465 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
2466 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2467 intval & AR5K_BEACON_PERIOD,
2468 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2469 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
2474 * ath5k_beacon_config - Configure the beacon queues and interrupts
2476 * @sc: struct ath5k_softc pointer we are operating on
2478 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2479 * interrupts to detect TSF updates only.
2482 ath5k_beacon_config(struct ath5k_softc *sc)
2484 struct ath5k_hw *ah = sc->ah;
2485 unsigned long flags;
2487 spin_lock_irqsave(&sc->block, flags);
2489 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
2491 if (sc->enable_beacon) {
2493 * In IBSS mode we use a self-linked tx descriptor and let the
2494 * hardware send the beacons automatically. We have to load it
2496 * We use the SWBA interrupt only to keep track of the beacon
2497 * timers in order to detect automatic TSF updates.
2499 ath5k_beaconq_config(sc);
2501 sc->imask |= AR5K_INT_SWBA;
2503 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2504 if (ath5k_hw_hasveol(ah))
2505 ath5k_beacon_send(sc);
2507 ath5k_beacon_update_timers(sc, -1);
2509 ath5k_hw_stop_tx_dma(sc->ah, sc->bhalq);
2512 ath5k_hw_set_imr(ah, sc->imask);
2514 spin_unlock_irqrestore(&sc->block, flags);
2517 static void ath5k_tasklet_beacon(unsigned long data)
2519 struct ath5k_softc *sc = (struct ath5k_softc *) data;
2522 * Software beacon alert--time to send a beacon.
2524 * In IBSS mode we use this interrupt just to
2525 * keep track of the next TBTT (target beacon
2526 * transmission time) in order to detect wether
2527 * automatic TSF updates happened.
2529 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2530 /* XXX: only if VEOL suppported */
2531 u64 tsf = ath5k_hw_get_tsf64(sc->ah);
2532 sc->nexttbtt += sc->bintval;
2533 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2534 "SWBA nexttbtt: %x hw_tu: %x "
2538 (unsigned long long) tsf);
2540 spin_lock(&sc->block);
2541 ath5k_beacon_send(sc);
2542 spin_unlock(&sc->block);
2547 /********************\
2548 * Interrupt handling *
2549 \********************/
2552 ath5k_init(struct ath5k_softc *sc)
2554 struct ath5k_hw *ah = sc->ah;
2557 mutex_lock(&sc->lock);
2559 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2562 * Stop anything previously setup. This is safe
2563 * no matter this is the first time through or not.
2565 ath5k_stop_locked(sc);
2568 * The basic interface to setting the hardware in a good
2569 * state is ``reset''. On return the hardware is known to
2570 * be powered up and with interrupts disabled. This must
2571 * be followed by initialization of the appropriate bits
2572 * and then setup of the interrupt mask.
2574 sc->curchan = sc->hw->conf.channel;
2575 sc->curband = &sc->sbands[sc->curchan->band];
2576 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2577 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
2578 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB;
2580 ret = ath5k_reset(sc, NULL);
2584 ath5k_rfkill_hw_start(ah);
2587 * Reset the key cache since some parts do not reset the
2588 * contents on initial power up or resume from suspend.
2590 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
2591 ath5k_hw_reset_key(ah, i);
2593 ath5k_hw_set_ack_bitrate_high(ah, true);
2597 mutex_unlock(&sc->lock);
2602 ath5k_stop_locked(struct ath5k_softc *sc)
2604 struct ath5k_hw *ah = sc->ah;
2606 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2607 test_bit(ATH_STAT_INVALID, sc->status));
2610 * Shutdown the hardware and driver:
2611 * stop output from above
2612 * disable interrupts
2614 * turn off the radio
2615 * clear transmit machinery
2616 * clear receive machinery
2617 * drain and release tx queues
2618 * reclaim beacon resources
2619 * power down hardware
2621 * Note that some of this work is not possible if the
2622 * hardware is gone (invalid).
2624 ieee80211_stop_queues(sc->hw);
2626 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2628 ath5k_hw_set_imr(ah, 0);
2629 synchronize_irq(sc->pdev->irq);
2631 ath5k_txq_cleanup(sc);
2632 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2634 ath5k_hw_phy_disable(ah);
2642 * Stop the device, grabbing the top-level lock to protect
2643 * against concurrent entry through ath5k_init (which can happen
2644 * if another thread does a system call and the thread doing the
2645 * stop is preempted).
2648 ath5k_stop_hw(struct ath5k_softc *sc)
2652 mutex_lock(&sc->lock);
2653 ret = ath5k_stop_locked(sc);
2654 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2656 * Don't set the card in full sleep mode!
2658 * a) When the device is in this state it must be carefully
2659 * woken up or references to registers in the PCI clock
2660 * domain may freeze the bus (and system). This varies
2661 * by chip and is mostly an issue with newer parts
2662 * (madwifi sources mentioned srev >= 0x78) that go to
2663 * sleep more quickly.
2665 * b) On older chips full sleep results a weird behaviour
2666 * during wakeup. I tested various cards with srev < 0x78
2667 * and they don't wake up after module reload, a second
2668 * module reload is needed to bring the card up again.
2670 * Until we figure out what's going on don't enable
2671 * full chip reset on any chip (this is what Legacy HAL
2672 * and Sam's HAL do anyway). Instead Perform a full reset
2673 * on the device (same as initial state after attach) and
2674 * leave it idle (keep MAC/BB on warm reset) */
2675 ret = ath5k_hw_on_hold(sc->ah);
2677 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2678 "putting device to sleep\n");
2680 ath5k_txbuf_free_skb(sc, sc->bbuf);
2683 mutex_unlock(&sc->lock);
2685 tasklet_kill(&sc->rxtq);
2686 tasklet_kill(&sc->txtq);
2687 tasklet_kill(&sc->restq);
2688 tasklet_kill(&sc->calib);
2689 tasklet_kill(&sc->beacontq);
2690 tasklet_kill(&sc->ani_tasklet);
2692 ath5k_rfkill_hw_stop(sc->ah);
2698 ath5k_intr_calibration_poll(struct ath5k_hw *ah)
2700 if (time_is_before_eq_jiffies(ah->ah_cal_next_ani) &&
2701 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL)) {
2702 /* run ANI only when full calibration is not active */
2703 ah->ah_cal_next_ani = jiffies +
2704 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI);
2705 tasklet_schedule(&ah->ah_sc->ani_tasklet);
2707 } else if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) {
2708 ah->ah_cal_next_full = jiffies +
2709 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL);
2710 tasklet_schedule(&ah->ah_sc->calib);
2712 /* we could use SWI to generate enough interrupts to meet our
2713 * calibration interval requirements, if necessary:
2714 * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */
2718 ath5k_intr(int irq, void *dev_id)
2720 struct ath5k_softc *sc = dev_id;
2721 struct ath5k_hw *ah = sc->ah;
2722 enum ath5k_int status;
2723 unsigned int counter = 1000;
2725 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2726 !ath5k_hw_is_intr_pending(ah)))
2730 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2731 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2733 if (unlikely(status & AR5K_INT_FATAL)) {
2735 * Fatal errors are unrecoverable.
2736 * Typically these are caused by DMA errors.
2738 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2739 "fatal int, resetting\n");
2740 tasklet_schedule(&sc->restq);
2741 } else if (unlikely(status & AR5K_INT_RXORN)) {
2743 * Receive buffers are full. Either the bus is busy or
2744 * the CPU is not fast enough to process all received
2746 * Older chipsets need a reset to come out of this
2747 * condition, but we treat it as RX for newer chips.
2748 * We don't know exactly which versions need a reset -
2749 * this guess is copied from the HAL.
2751 sc->stats.rxorn_intr++;
2752 if (ah->ah_mac_srev < AR5K_SREV_AR5212) {
2753 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2754 "rx overrun, resetting\n");
2755 tasklet_schedule(&sc->restq);
2758 tasklet_schedule(&sc->rxtq);
2760 if (status & AR5K_INT_SWBA) {
2761 tasklet_hi_schedule(&sc->beacontq);
2763 if (status & AR5K_INT_RXEOL) {
2765 * NB: the hardware should re-read the link when
2766 * RXE bit is written, but it doesn't work at
2767 * least on older hardware revs.
2771 if (status & AR5K_INT_TXURN) {
2772 /* bump tx trigger level */
2773 ath5k_hw_update_tx_triglevel(ah, true);
2775 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
2776 tasklet_schedule(&sc->rxtq);
2777 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2778 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
2779 tasklet_schedule(&sc->txtq);
2780 if (status & AR5K_INT_BMISS) {
2783 if (status & AR5K_INT_MIB) {
2784 sc->stats.mib_intr++;
2785 ath5k_hw_update_mib_counters(ah);
2786 ath5k_ani_mib_intr(ah);
2788 if (status & AR5K_INT_GPIO)
2789 tasklet_schedule(&sc->rf_kill.toggleq);
2792 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
2794 if (unlikely(!counter))
2795 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2797 ath5k_intr_calibration_poll(ah);
2803 ath5k_tasklet_reset(unsigned long data)
2805 struct ath5k_softc *sc = (void *)data;
2807 ath5k_reset(sc, sc->curchan);
2811 * Periodically recalibrate the PHY to account
2812 * for temperature/environment changes.
2815 ath5k_tasklet_calibrate(unsigned long data)
2817 struct ath5k_softc *sc = (void *)data;
2818 struct ath5k_hw *ah = sc->ah;
2820 /* Only full calibration for now */
2821 ah->ah_cal_mask |= AR5K_CALIBRATION_FULL;
2823 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2824 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2825 sc->curchan->hw_value);
2827 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2829 * Rfgain is out of bounds, reset the chip
2830 * to load new gain values.
2832 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
2833 ath5k_reset(sc, sc->curchan);
2835 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2836 ATH5K_ERR(sc, "calibration of channel %u failed\n",
2837 ieee80211_frequency_to_channel(
2838 sc->curchan->center_freq));
2840 /* Noise floor calibration interrupts rx/tx path while I/Q calibration
2841 * doesn't. We stop the queues so that calibration doesn't interfere
2842 * with TX and don't run it as often */
2843 if (time_is_before_eq_jiffies(ah->ah_cal_next_nf)) {
2844 ah->ah_cal_next_nf = jiffies +
2845 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_NF);
2846 ieee80211_stop_queues(sc->hw);
2847 ath5k_hw_update_noise_floor(ah);
2848 ieee80211_wake_queues(sc->hw);
2851 ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL;
2856 ath5k_tasklet_ani(unsigned long data)
2858 struct ath5k_softc *sc = (void *)data;
2859 struct ath5k_hw *ah = sc->ah;
2861 ah->ah_cal_mask |= AR5K_CALIBRATION_ANI;
2862 ath5k_ani_calibration(ah);
2863 ah->ah_cal_mask &= ~AR5K_CALIBRATION_ANI;
2867 /********************\
2868 * Mac80211 functions *
2869 \********************/
2872 ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2874 struct ath5k_softc *sc = hw->priv;
2876 return ath5k_tx_queue(hw, skb, sc->txq);
2879 static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
2880 struct ath5k_txq *txq)
2882 struct ath5k_softc *sc = hw->priv;
2883 struct ath5k_buf *bf;
2884 unsigned long flags;
2887 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2889 if (sc->opmode == NL80211_IFTYPE_MONITOR)
2890 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2893 * the hardware expects the header padded to 4 byte boundaries
2894 * if this is not the case we add the padding after the header
2896 padsize = ath5k_add_padding(skb);
2898 ATH5K_ERR(sc, "tx hdrlen not %%4: not enough"
2899 " headroom to pad");
2903 spin_lock_irqsave(&sc->txbuflock, flags);
2904 if (list_empty(&sc->txbuf)) {
2905 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2906 spin_unlock_irqrestore(&sc->txbuflock, flags);
2907 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
2910 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2911 list_del(&bf->list);
2913 if (list_empty(&sc->txbuf))
2914 ieee80211_stop_queues(hw);
2915 spin_unlock_irqrestore(&sc->txbuflock, flags);
2919 if (ath5k_txbuf_setup(sc, bf, txq, padsize)) {
2921 spin_lock_irqsave(&sc->txbuflock, flags);
2922 list_add_tail(&bf->list, &sc->txbuf);
2924 spin_unlock_irqrestore(&sc->txbuflock, flags);
2927 return NETDEV_TX_OK;
2930 dev_kfree_skb_any(skb);
2931 return NETDEV_TX_OK;
2935 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2936 * and change to the given channel.
2939 ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan)
2941 struct ath5k_hw *ah = sc->ah;
2944 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
2947 ath5k_hw_set_imr(ah, 0);
2948 ath5k_txq_cleanup(sc);
2952 sc->curband = &sc->sbands[chan->band];
2954 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, chan != NULL);
2956 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2960 ret = ath5k_rx_start(sc);
2962 ATH5K_ERR(sc, "can't start recv logic\n");
2966 ath5k_ani_init(ah, ah->ah_sc->ani_state.ani_mode);
2968 ah->ah_cal_next_full = jiffies;
2969 ah->ah_cal_next_ani = jiffies;
2970 ah->ah_cal_next_nf = jiffies;
2973 * Change channels and update the h/w rate map if we're switching;
2974 * e.g. 11a to 11b/g.
2976 * We may be doing a reset in response to an ioctl that changes the
2977 * channel so update any state that might change as a result.
2981 /* ath5k_chan_change(sc, c); */
2983 ath5k_beacon_config(sc);
2984 /* intrs are enabled by ath5k_beacon_config */
2986 ieee80211_wake_queues(sc->hw);
2993 static int ath5k_start(struct ieee80211_hw *hw)
2995 return ath5k_init(hw->priv);
2998 static void ath5k_stop(struct ieee80211_hw *hw)
3000 ath5k_stop_hw(hw->priv);
3003 static int ath5k_add_interface(struct ieee80211_hw *hw,
3004 struct ieee80211_vif *vif)
3006 struct ath5k_softc *sc = hw->priv;
3009 mutex_lock(&sc->lock);
3017 switch (vif->type) {
3018 case NL80211_IFTYPE_AP:
3019 case NL80211_IFTYPE_STATION:
3020 case NL80211_IFTYPE_ADHOC:
3021 case NL80211_IFTYPE_MESH_POINT:
3022 case NL80211_IFTYPE_MONITOR:
3023 sc->opmode = vif->type;
3030 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "add interface mode %d\n", sc->opmode);
3032 ath5k_hw_set_lladdr(sc->ah, vif->addr);
3033 ath5k_mode_setup(sc);
3037 mutex_unlock(&sc->lock);
3042 ath5k_remove_interface(struct ieee80211_hw *hw,
3043 struct ieee80211_vif *vif)
3045 struct ath5k_softc *sc = hw->priv;
3046 u8 mac[ETH_ALEN] = {};
3048 mutex_lock(&sc->lock);
3052 ath5k_hw_set_lladdr(sc->ah, mac);
3055 mutex_unlock(&sc->lock);
3059 * TODO: Phy disable/diversity etc
3062 ath5k_config(struct ieee80211_hw *hw, u32 changed)
3064 struct ath5k_softc *sc = hw->priv;
3065 struct ath5k_hw *ah = sc->ah;
3066 struct ieee80211_conf *conf = &hw->conf;
3069 mutex_lock(&sc->lock);
3071 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
3072 ret = ath5k_chan_set(sc, conf->channel);
3077 if ((changed & IEEE80211_CONF_CHANGE_POWER) &&
3078 (sc->power_level != conf->power_level)) {
3079 sc->power_level = conf->power_level;
3082 ath5k_hw_set_txpower_limit(ah, (conf->power_level * 2));
3086 * 1) Move this on config_interface and handle each case
3087 * separately eg. when we have only one STA vif, use
3088 * AR5K_ANTMODE_SINGLE_AP
3090 * 2) Allow the user to change antenna mode eg. when only
3091 * one antenna is present
3093 * 3) Allow the user to set default/tx antenna when possible
3095 * 4) Default mode should handle 90% of the cases, together
3096 * with fixed a/b and single AP modes we should be able to
3097 * handle 99%. Sectored modes are extreme cases and i still
3098 * haven't found a usage for them. If we decide to support them,
3099 * then we must allow the user to set how many tx antennas we
3102 ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode);
3105 mutex_unlock(&sc->lock);
3109 static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw,
3110 struct netdev_hw_addr_list *mc_list)
3114 struct netdev_hw_addr *ha;
3119 netdev_hw_addr_list_for_each(ha, mc_list) {
3120 /* calculate XOR of eight 6-bit values */
3121 val = get_unaligned_le32(ha->addr + 0);
3122 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
3123 val = get_unaligned_le32(ha->addr + 3);
3124 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
3126 mfilt[pos / 32] |= (1 << (pos % 32));
3127 /* XXX: we might be able to just do this instead,
3128 * but not sure, needs testing, if we do use this we'd
3129 * neet to inform below to not reset the mcast */
3130 /* ath5k_hw_set_mcast_filterindex(ah,
3134 return ((u64)(mfilt[1]) << 32) | mfilt[0];
3137 #define SUPPORTED_FIF_FLAGS \
3138 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
3139 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
3140 FIF_BCN_PRBRESP_PROMISC
3142 * o always accept unicast, broadcast, and multicast traffic
3143 * o multicast traffic for all BSSIDs will be enabled if mac80211
3145 * o maintain current state of phy ofdm or phy cck error reception.
3146 * If the hardware detects any of these type of errors then
3147 * ath5k_hw_get_rx_filter() will pass to us the respective
3148 * hardware filters to be able to receive these type of frames.
3149 * o probe request frames are accepted only when operating in
3150 * hostap, adhoc, or monitor modes
3151 * o enable promiscuous mode according to the interface state
3153 * - when operating in adhoc mode so the 802.11 layer creates
3154 * node table entries for peers,
3155 * - when operating in station mode for collecting rssi data when
3156 * the station is otherwise quiet, or
3159 static void ath5k_configure_filter(struct ieee80211_hw *hw,
3160 unsigned int changed_flags,
3161 unsigned int *new_flags,
3164 struct ath5k_softc *sc = hw->priv;
3165 struct ath5k_hw *ah = sc->ah;
3166 u32 mfilt[2], rfilt;
3168 mutex_lock(&sc->lock);
3170 mfilt[0] = multicast;
3171 mfilt[1] = multicast >> 32;
3173 /* Only deal with supported flags */
3174 changed_flags &= SUPPORTED_FIF_FLAGS;
3175 *new_flags &= SUPPORTED_FIF_FLAGS;
3177 /* If HW detects any phy or radar errors, leave those filters on.
3178 * Also, always enable Unicast, Broadcasts and Multicast
3179 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
3180 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
3181 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
3182 AR5K_RX_FILTER_MCAST);
3184 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
3185 if (*new_flags & FIF_PROMISC_IN_BSS) {
3186 __set_bit(ATH_STAT_PROMISC, sc->status);
3188 __clear_bit(ATH_STAT_PROMISC, sc->status);
3192 if (test_bit(ATH_STAT_PROMISC, sc->status))
3193 rfilt |= AR5K_RX_FILTER_PROM;
3195 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
3196 if (*new_flags & FIF_ALLMULTI) {
3201 /* This is the best we can do */
3202 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
3203 rfilt |= AR5K_RX_FILTER_PHYERR;
3205 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
3206 * and probes for any BSSID, this needs testing */
3207 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
3208 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
3210 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
3211 * set we should only pass on control frames for this
3212 * station. This needs testing. I believe right now this
3213 * enables *all* control frames, which is OK.. but
3214 * but we should see if we can improve on granularity */
3215 if (*new_flags & FIF_CONTROL)
3216 rfilt |= AR5K_RX_FILTER_CONTROL;
3218 /* Additional settings per mode -- this is per ath5k */
3220 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
3222 switch (sc->opmode) {
3223 case NL80211_IFTYPE_MESH_POINT:
3224 case NL80211_IFTYPE_MONITOR:
3225 rfilt |= AR5K_RX_FILTER_CONTROL |
3226 AR5K_RX_FILTER_BEACON |
3227 AR5K_RX_FILTER_PROBEREQ |
3228 AR5K_RX_FILTER_PROM;
3230 case NL80211_IFTYPE_AP:
3231 case NL80211_IFTYPE_ADHOC:
3232 rfilt |= AR5K_RX_FILTER_PROBEREQ |
3233 AR5K_RX_FILTER_BEACON;
3235 case NL80211_IFTYPE_STATION:
3237 rfilt |= AR5K_RX_FILTER_BEACON;
3243 ath5k_hw_set_rx_filter(ah, rfilt);
3245 /* Set multicast bits */
3246 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
3247 /* Set the cached hw filter flags, this will alter actually
3249 sc->filter_flags = rfilt;
3251 mutex_unlock(&sc->lock);
3255 ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3256 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3257 struct ieee80211_key_conf *key)
3259 struct ath5k_softc *sc = hw->priv;
3260 struct ath5k_hw *ah = sc->ah;
3261 struct ath_common *common = ath5k_hw_common(ah);
3264 if (modparam_nohwcrypt)
3267 if (sc->opmode == NL80211_IFTYPE_AP)
3275 if (sc->ah->ah_aes_support)
3284 mutex_lock(&sc->lock);
3288 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key,
3289 sta ? sta->addr : NULL);
3291 ATH5K_ERR(sc, "can't set the key\n");
3294 __set_bit(key->keyidx, common->keymap);
3295 key->hw_key_idx = key->keyidx;
3296 key->flags |= (IEEE80211_KEY_FLAG_GENERATE_IV |
3297 IEEE80211_KEY_FLAG_GENERATE_MMIC);
3300 ath5k_hw_reset_key(sc->ah, key->keyidx);
3301 __clear_bit(key->keyidx, common->keymap);
3310 mutex_unlock(&sc->lock);
3315 ath5k_get_stats(struct ieee80211_hw *hw,
3316 struct ieee80211_low_level_stats *stats)
3318 struct ath5k_softc *sc = hw->priv;
3321 ath5k_hw_update_mib_counters(sc->ah);
3323 stats->dot11ACKFailureCount = sc->stats.ack_fail;
3324 stats->dot11RTSFailureCount = sc->stats.rts_fail;
3325 stats->dot11RTSSuccessCount = sc->stats.rts_ok;
3326 stats->dot11FCSErrorCount = sc->stats.fcs_error;
3331 static int ath5k_get_survey(struct ieee80211_hw *hw, int idx,
3332 struct survey_info *survey)
3334 struct ath5k_softc *sc = hw->priv;
3335 struct ieee80211_conf *conf = &hw->conf;
3340 survey->channel = conf->channel;
3341 survey->filled = SURVEY_INFO_NOISE_DBM;
3342 survey->noise = sc->ah->ah_noise_floor;
3348 ath5k_get_tsf(struct ieee80211_hw *hw)
3350 struct ath5k_softc *sc = hw->priv;
3352 return ath5k_hw_get_tsf64(sc->ah);
3356 ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3358 struct ath5k_softc *sc = hw->priv;
3360 ath5k_hw_set_tsf64(sc->ah, tsf);
3364 ath5k_reset_tsf(struct ieee80211_hw *hw)
3366 struct ath5k_softc *sc = hw->priv;
3369 * in IBSS mode we need to update the beacon timers too.
3370 * this will also reset the TSF if we call it with 0
3372 if (sc->opmode == NL80211_IFTYPE_ADHOC)
3373 ath5k_beacon_update_timers(sc, 0);
3375 ath5k_hw_reset_tsf(sc->ah);
3379 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
3380 * this is called only once at config_bss time, for AP we do it every
3381 * SWBA interrupt so that the TIM will reflect buffered frames.
3383 * Called with the beacon lock.
3386 ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
3389 struct ath5k_softc *sc = hw->priv;
3390 struct sk_buff *skb;
3392 if (WARN_ON(!vif)) {
3397 skb = ieee80211_beacon_get(hw, vif);
3404 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
3406 ath5k_txbuf_free_skb(sc, sc->bbuf);
3407 sc->bbuf->skb = skb;
3408 ret = ath5k_beacon_setup(sc, sc->bbuf);
3410 sc->bbuf->skb = NULL;
3416 set_beacon_filter(struct ieee80211_hw *hw, bool enable)
3418 struct ath5k_softc *sc = hw->priv;
3419 struct ath5k_hw *ah = sc->ah;
3421 rfilt = ath5k_hw_get_rx_filter(ah);
3423 rfilt |= AR5K_RX_FILTER_BEACON;
3425 rfilt &= ~AR5K_RX_FILTER_BEACON;
3426 ath5k_hw_set_rx_filter(ah, rfilt);
3427 sc->filter_flags = rfilt;
3430 static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
3431 struct ieee80211_vif *vif,
3432 struct ieee80211_bss_conf *bss_conf,
3435 struct ath5k_softc *sc = hw->priv;
3436 struct ath5k_hw *ah = sc->ah;
3437 struct ath_common *common = ath5k_hw_common(ah);
3438 unsigned long flags;
3440 mutex_lock(&sc->lock);
3441 if (WARN_ON(sc->vif != vif))
3444 if (changes & BSS_CHANGED_BSSID) {
3445 /* Cache for later use during resets */
3446 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
3448 ath5k_hw_set_associd(ah);
3452 if (changes & BSS_CHANGED_BEACON_INT)
3453 sc->bintval = bss_conf->beacon_int;
3455 if (changes & BSS_CHANGED_ASSOC) {
3456 sc->assoc = bss_conf->assoc;
3457 if (sc->opmode == NL80211_IFTYPE_STATION)
3458 set_beacon_filter(hw, sc->assoc);
3459 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3460 AR5K_LED_ASSOC : AR5K_LED_INIT);
3461 if (bss_conf->assoc) {
3462 ATH5K_DBG(sc, ATH5K_DEBUG_ANY,
3463 "Bss Info ASSOC %d, bssid: %pM\n",
3464 bss_conf->aid, common->curbssid);
3465 common->curaid = bss_conf->aid;
3466 ath5k_hw_set_associd(ah);
3467 /* Once ANI is available you would start it here */
3471 if (changes & BSS_CHANGED_BEACON) {
3472 spin_lock_irqsave(&sc->block, flags);
3473 ath5k_beacon_update(hw, vif);
3474 spin_unlock_irqrestore(&sc->block, flags);
3477 if (changes & BSS_CHANGED_BEACON_ENABLED)
3478 sc->enable_beacon = bss_conf->enable_beacon;
3480 if (changes & (BSS_CHANGED_BEACON | BSS_CHANGED_BEACON_ENABLED |
3481 BSS_CHANGED_BEACON_INT))
3482 ath5k_beacon_config(sc);
3485 mutex_unlock(&sc->lock);
3488 static void ath5k_sw_scan_start(struct ieee80211_hw *hw)
3490 struct ath5k_softc *sc = hw->priv;
3492 ath5k_hw_set_ledstate(sc->ah, AR5K_LED_SCAN);
3495 static void ath5k_sw_scan_complete(struct ieee80211_hw *hw)
3497 struct ath5k_softc *sc = hw->priv;
3498 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3499 AR5K_LED_ASSOC : AR5K_LED_INIT);
3503 * ath5k_set_coverage_class - Set IEEE 802.11 coverage class
3505 * @hw: struct ieee80211_hw pointer
3506 * @coverage_class: IEEE 802.11 coverage class number
3508 * Mac80211 callback. Sets slot time, ACK timeout and CTS timeout for given
3509 * coverage class. The values are persistent, they are restored after device
3512 static void ath5k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
3514 struct ath5k_softc *sc = hw->priv;
3516 mutex_lock(&sc->lock);
3517 ath5k_hw_set_coverage_class(sc->ah, coverage_class);
3518 mutex_unlock(&sc->lock);
projects / firefly-linux-kernel-4.4.55.git / blob