2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21 #include <linux/interrupt.h>
27 #define REG_DUMP_COUNT_QCA988X 60
30 * maximum number of bytes that can be handled atomically by DiagRead/DiagWrite
32 #define DIAG_TRANSFER_LIMIT 2048
35 * maximum number of bytes that can be
36 * handled atomically by DiagRead/DiagWrite
38 #define DIAG_TRANSFER_LIMIT 2048
41 struct completion done;
46 enum ath10k_pci_compl_state {
47 ATH10K_PCI_COMPL_FREE = 0,
48 ATH10K_PCI_COMPL_SEND,
49 ATH10K_PCI_COMPL_RECV,
52 struct ath10k_pci_compl {
53 struct list_head list;
54 enum ath10k_pci_compl_state state;
55 struct ath10k_ce_pipe *ce_state;
56 struct ath10k_pci_pipe *pipe_info;
59 unsigned int transfer_id;
64 * PCI-specific Target state
66 * NOTE: Structure is shared between Host software and Target firmware!
68 * Much of this may be of interest to the Host so
69 * HOST_INTEREST->hi_interconnect_state points here
70 * (and all members are 32-bit quantities in order to
71 * facilitate Host access). In particular, Host software is
72 * required to initialize pipe_cfg_addr and svc_to_pipe_map.
75 /* Pipe configuration Target address */
76 /* NB: ce_pipe_config[CE_COUNT] */
79 /* Service to pipe map Target address */
80 /* NB: service_to_pipe[PIPE_TO_CE_MAP_CN] */
83 /* number of MSI interrupts requested */
86 /* number of MSI interrupts granted */
89 /* Message Signalled Interrupt address */
96 * Data for firmware interrupt;
97 * MSI data for other interrupts are
98 * in various SoC registers
100 u32 msi_fw_intr_data;
102 /* PCIE_PWR_METHOD_* */
103 u32 power_mgmt_method;
105 /* PCIE_CONFIG_FLAG_* */
109 /* PCIE_CONFIG_FLAG definitions */
110 #define PCIE_CONFIG_FLAG_ENABLE_L1 0x0000001
112 /* Host software's Copy Engine configuration. */
113 #define CE_ATTR_FLAGS 0
116 * Configuration information for a Copy Engine pipe.
117 * Passed from Host to Target during startup (one per CE).
119 * NOTE: Structure is shared between Host software and Target firmware!
121 struct ce_pipe_config {
131 * Directions for interconnect pipe configuration.
132 * These definitions may be used during configuration and are shared
133 * between Host and Target.
135 * Pipe Directions are relative to the Host, so PIPEDIR_IN means
136 * "coming IN over air through Target to Host" as with a WiFi Rx operation.
137 * Conversely, PIPEDIR_OUT means "going OUT from Host through Target over air"
138 * as with a WiFi Tx operation. This is somewhat awkward for the "middle-man"
139 * Target since things that are "PIPEDIR_OUT" are coming IN to the Target
140 * over the interconnect.
142 #define PIPEDIR_NONE 0
143 #define PIPEDIR_IN 1 /* Target-->Host, WiFi Rx direction */
144 #define PIPEDIR_OUT 2 /* Host->Target, WiFi Tx direction */
145 #define PIPEDIR_INOUT 3 /* bidirectional */
147 /* Establish a mapping between a service/direction and a pipe. */
148 struct service_to_pipe {
154 enum ath10k_pci_features {
155 ATH10K_PCI_FEATURE_MSI_X = 0,
156 ATH10K_PCI_FEATURE_SOC_POWER_SAVE = 1,
159 ATH10K_PCI_FEATURE_COUNT
162 /* Per-pipe state. */
163 struct ath10k_pci_pipe {
164 /* Handle of underlying Copy Engine */
165 struct ath10k_ce_pipe *ce_hdl;
167 /* Our pipe number; facilitiates use of pipe_info ptrs. */
170 /* Convenience back pointer to hif_ce_state. */
171 struct ath10k *hif_ce_state;
175 /* protects compl_free and num_send_allowed */
176 spinlock_t pipe_lock;
178 /* List of free CE completion slots */
179 struct list_head compl_free;
181 struct ath10k_pci *ar_pci;
182 struct tasklet_struct intr;
186 struct pci_dev *pdev;
191 DECLARE_BITMAP(features, ATH10K_PCI_FEATURE_COUNT);
194 * Number of MSI interrupts granted, 0 --> using legacy PCI line
199 struct tasklet_struct intr_tq;
200 struct tasklet_struct msi_fw_err;
202 /* Number of Copy Engines supported */
203 unsigned int ce_count;
207 atomic_t keep_awake_count;
210 /* List of CE completions to be processed */
211 struct list_head compl_process;
213 /* protects compl_processing and compl_process */
214 spinlock_t compl_lock;
216 bool compl_processing;
218 struct ath10k_pci_pipe pipe_info[CE_COUNT_MAX];
220 struct ath10k_hif_cb msg_callbacks_current;
222 /* Target address used to signal a pending firmware event */
223 u32 fw_indicator_address;
225 /* Copy Engine used for Diagnostic Accesses */
226 struct ath10k_ce_pipe *ce_diag;
228 /* FIXME: document what this really protects */
231 /* Map CE id to ce_state */
232 struct ath10k_ce_pipe ce_states[CE_COUNT_MAX];
235 static inline struct ath10k_pci *ath10k_pci_priv(struct ath10k *ar)
240 static inline u32 ath10k_pci_reg_read32(struct ath10k *ar, u32 addr)
242 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
244 return ioread32(ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + addr);
247 static inline void ath10k_pci_reg_write32(struct ath10k *ar, u32 addr, u32 val)
249 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
251 iowrite32(val, ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + addr);
254 #define ATH_PCI_RESET_WAIT_MAX 10 /* ms */
255 #define PCIE_WAKE_TIMEOUT 5000 /* 5ms */
259 #define CDC_WAR_MAGIC_STR 0xceef0000
260 #define CDC_WAR_DATA_CE 4
263 * TODO: Should be a function call specific to each Target-type.
264 * This convoluted macro converts from Target CPU Virtual Address Space to CE
265 * Address Space. As part of this process, we conservatively fetch the current
266 * PCIE_BAR. MOST of the time, this should match the upper bits of PCI space
267 * for this device; but that's not guaranteed.
269 #define TARG_CPU_SPACE_TO_CE_SPACE(ar, pci_addr, addr) \
270 (((ioread32((pci_addr)+(SOC_CORE_BASE_ADDRESS| \
271 CORE_CTRL_ADDRESS)) & 0x7ff) << 21) | \
272 0x100000 | ((addr) & 0xfffff))
274 /* Wait up to this many Ms for a Diagnostic Access CE operation to complete */
275 #define DIAG_ACCESS_CE_TIMEOUT_MS 10
278 * This API allows the Host to access Target registers directly
279 * and relatively efficiently over PCIe.
280 * This allows the Host to avoid extra overhead associated with
281 * sending a message to firmware and waiting for a response message
282 * from firmware, as is done on other interconnects.
284 * Yet there is some complexity with direct accesses because the
285 * Target's power state is not known a priori. The Host must issue
286 * special PCIe reads/writes in order to explicitly wake the Target
287 * and to verify that it is awake and will remain awake.
291 * Use ath10k_pci_read32 and ath10k_pci_write32 to access Target space.
292 * These calls must be bracketed by ath10k_pci_wake and
293 * ath10k_pci_sleep. A single BEGIN/END pair is adequate for
294 * multiple READ/WRITE operations.
296 * Use ath10k_pci_wake to put the Target in a state in
297 * which it is legal for the Host to directly access it. This
298 * may involve waking the Target from a low power state, which
299 * may take up to 2Ms!
301 * Use ath10k_pci_sleep to tell the Target that as far as
302 * this code path is concerned, it no longer needs to remain
303 * directly accessible. BEGIN/END is under a reference counter;
304 * multiple code paths may issue BEGIN/END on a single targid.
306 static inline void ath10k_pci_write32(struct ath10k *ar, u32 offset,
309 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
311 iowrite32(value, ar_pci->mem + offset);
314 static inline u32 ath10k_pci_read32(struct ath10k *ar, u32 offset)
316 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
318 return ioread32(ar_pci->mem + offset);
321 int ath10k_do_pci_wake(struct ath10k *ar);
322 void ath10k_do_pci_sleep(struct ath10k *ar);
324 static inline int ath10k_pci_wake(struct ath10k *ar)
326 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
328 if (test_bit(ATH10K_PCI_FEATURE_SOC_POWER_SAVE, ar_pci->features))
329 return ath10k_do_pci_wake(ar);
334 static inline void ath10k_pci_sleep(struct ath10k *ar)
336 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
338 if (test_bit(ATH10K_PCI_FEATURE_SOC_POWER_SAVE, ar_pci->features))
339 ath10k_do_pci_sleep(ar);