2 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * version 2 as published by the Free Software Foundation.
10 #include <linux/signal.h>
11 #include <linux/slab.h>
12 #include <linux/module.h>
13 #include <linux/netdevice.h>
14 #include <linux/etherdevice.h>
15 #include <linux/mii.h>
16 #include <linux/ethtool.h>
17 #include <linux/usb.h>
18 #include <linux/crc32.h>
19 #include <linux/if_vlan.h>
20 #include <linux/uaccess.h>
21 #include <linux/list.h>
23 #include <linux/ipv6.h>
24 #include <net/ip6_checksum.h>
25 #include <uapi/linux/mdio.h>
26 #include <linux/mdio.h>
27 #include <linux/usb/cdc.h>
29 /* Version Information */
30 #define DRIVER_VERSION "v1.08.0 (2015/01/13)"
31 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
32 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
33 #define MODULENAME "r8152"
35 #define R8152_PHY_ID 32
37 #define PLA_IDR 0xc000
38 #define PLA_RCR 0xc010
39 #define PLA_RMS 0xc016
40 #define PLA_RXFIFO_CTRL0 0xc0a0
41 #define PLA_RXFIFO_CTRL1 0xc0a4
42 #define PLA_RXFIFO_CTRL2 0xc0a8
43 #define PLA_DMY_REG0 0xc0b0
44 #define PLA_FMC 0xc0b4
45 #define PLA_CFG_WOL 0xc0b6
46 #define PLA_TEREDO_CFG 0xc0bc
47 #define PLA_MAR 0xcd00
48 #define PLA_BACKUP 0xd000
49 #define PAL_BDC_CR 0xd1a0
50 #define PLA_TEREDO_TIMER 0xd2cc
51 #define PLA_REALWOW_TIMER 0xd2e8
52 #define PLA_LEDSEL 0xdd90
53 #define PLA_LED_FEATURE 0xdd92
54 #define PLA_PHYAR 0xde00
55 #define PLA_BOOT_CTRL 0xe004
56 #define PLA_GPHY_INTR_IMR 0xe022
57 #define PLA_EEE_CR 0xe040
58 #define PLA_EEEP_CR 0xe080
59 #define PLA_MAC_PWR_CTRL 0xe0c0
60 #define PLA_MAC_PWR_CTRL2 0xe0ca
61 #define PLA_MAC_PWR_CTRL3 0xe0cc
62 #define PLA_MAC_PWR_CTRL4 0xe0ce
63 #define PLA_WDT6_CTRL 0xe428
64 #define PLA_TCR0 0xe610
65 #define PLA_TCR1 0xe612
66 #define PLA_MTPS 0xe615
67 #define PLA_TXFIFO_CTRL 0xe618
68 #define PLA_RSTTALLY 0xe800
70 #define PLA_CRWECR 0xe81c
71 #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
72 #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
73 #define PLA_CONFIG5 0xe822
74 #define PLA_PHY_PWR 0xe84c
75 #define PLA_OOB_CTRL 0xe84f
76 #define PLA_CPCR 0xe854
77 #define PLA_MISC_0 0xe858
78 #define PLA_MISC_1 0xe85a
79 #define PLA_OCP_GPHY_BASE 0xe86c
80 #define PLA_TALLYCNT 0xe890
81 #define PLA_SFF_STS_7 0xe8de
82 #define PLA_PHYSTATUS 0xe908
83 #define PLA_BP_BA 0xfc26
84 #define PLA_BP_0 0xfc28
85 #define PLA_BP_1 0xfc2a
86 #define PLA_BP_2 0xfc2c
87 #define PLA_BP_3 0xfc2e
88 #define PLA_BP_4 0xfc30
89 #define PLA_BP_5 0xfc32
90 #define PLA_BP_6 0xfc34
91 #define PLA_BP_7 0xfc36
92 #define PLA_BP_EN 0xfc38
94 #define USB_USB2PHY 0xb41e
95 #define USB_SSPHYLINK2 0xb428
96 #define USB_U2P3_CTRL 0xb460
97 #define USB_CSR_DUMMY1 0xb464
98 #define USB_CSR_DUMMY2 0xb466
99 #define USB_DEV_STAT 0xb808
100 #define USB_CONNECT_TIMER 0xcbf8
101 #define USB_BURST_SIZE 0xcfc0
102 #define USB_USB_CTRL 0xd406
103 #define USB_PHY_CTRL 0xd408
104 #define USB_TX_AGG 0xd40a
105 #define USB_RX_BUF_TH 0xd40c
106 #define USB_USB_TIMER 0xd428
107 #define USB_RX_EARLY_AGG 0xd42c
108 #define USB_PM_CTRL_STATUS 0xd432
109 #define USB_TX_DMA 0xd434
110 #define USB_TOLERANCE 0xd490
111 #define USB_LPM_CTRL 0xd41a
112 #define USB_UPS_CTRL 0xd800
113 #define USB_MISC_0 0xd81a
114 #define USB_POWER_CUT 0xd80a
115 #define USB_AFE_CTRL2 0xd824
116 #define USB_WDT11_CTRL 0xe43c
117 #define USB_BP_BA 0xfc26
118 #define USB_BP_0 0xfc28
119 #define USB_BP_1 0xfc2a
120 #define USB_BP_2 0xfc2c
121 #define USB_BP_3 0xfc2e
122 #define USB_BP_4 0xfc30
123 #define USB_BP_5 0xfc32
124 #define USB_BP_6 0xfc34
125 #define USB_BP_7 0xfc36
126 #define USB_BP_EN 0xfc38
129 #define OCP_ALDPS_CONFIG 0x2010
130 #define OCP_EEE_CONFIG1 0x2080
131 #define OCP_EEE_CONFIG2 0x2092
132 #define OCP_EEE_CONFIG3 0x2094
133 #define OCP_BASE_MII 0xa400
134 #define OCP_EEE_AR 0xa41a
135 #define OCP_EEE_DATA 0xa41c
136 #define OCP_PHY_STATUS 0xa420
137 #define OCP_POWER_CFG 0xa430
138 #define OCP_EEE_CFG 0xa432
139 #define OCP_SRAM_ADDR 0xa436
140 #define OCP_SRAM_DATA 0xa438
141 #define OCP_DOWN_SPEED 0xa442
142 #define OCP_EEE_ABLE 0xa5c4
143 #define OCP_EEE_ADV 0xa5d0
144 #define OCP_EEE_LPABLE 0xa5d2
145 #define OCP_ADC_CFG 0xbc06
148 #define SRAM_LPF_CFG 0x8012
149 #define SRAM_10M_AMP1 0x8080
150 #define SRAM_10M_AMP2 0x8082
151 #define SRAM_IMPEDANCE 0x8084
154 #define RCR_AAP 0x00000001
155 #define RCR_APM 0x00000002
156 #define RCR_AM 0x00000004
157 #define RCR_AB 0x00000008
158 #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
160 /* PLA_RXFIFO_CTRL0 */
161 #define RXFIFO_THR1_NORMAL 0x00080002
162 #define RXFIFO_THR1_OOB 0x01800003
164 /* PLA_RXFIFO_CTRL1 */
165 #define RXFIFO_THR2_FULL 0x00000060
166 #define RXFIFO_THR2_HIGH 0x00000038
167 #define RXFIFO_THR2_OOB 0x0000004a
168 #define RXFIFO_THR2_NORMAL 0x00a0
170 /* PLA_RXFIFO_CTRL2 */
171 #define RXFIFO_THR3_FULL 0x00000078
172 #define RXFIFO_THR3_HIGH 0x00000048
173 #define RXFIFO_THR3_OOB 0x0000005a
174 #define RXFIFO_THR3_NORMAL 0x0110
176 /* PLA_TXFIFO_CTRL */
177 #define TXFIFO_THR_NORMAL 0x00400008
178 #define TXFIFO_THR_NORMAL2 0x01000008
181 #define ECM_ALDPS 0x0002
184 #define FMC_FCR_MCU_EN 0x0001
187 #define EEEP_CR_EEEP_TX 0x0002
190 #define WDT6_SET_MODE 0x0010
193 #define TCR0_TX_EMPTY 0x0800
194 #define TCR0_AUTO_FIFO 0x0080
197 #define VERSION_MASK 0x7cf0
200 #define MTPS_JUMBO (12 * 1024 / 64)
201 #define MTPS_DEFAULT (6 * 1024 / 64)
204 #define TALLY_RESET 0x0001
212 #define CRWECR_NORAML 0x00
213 #define CRWECR_CONFIG 0xc0
216 #define NOW_IS_OOB 0x80
217 #define TXFIFO_EMPTY 0x20
218 #define RXFIFO_EMPTY 0x10
219 #define LINK_LIST_READY 0x02
220 #define DIS_MCU_CLROOB 0x01
221 #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
224 #define RXDY_GATED_EN 0x0008
227 #define RE_INIT_LL 0x8000
228 #define MCU_BORW_EN 0x4000
231 #define CPCR_RX_VLAN 0x0040
234 #define MAGIC_EN 0x0001
237 #define TEREDO_SEL 0x8000
238 #define TEREDO_WAKE_MASK 0x7f00
239 #define TEREDO_RS_EVENT_MASK 0x00fe
240 #define OOB_TEREDO_EN 0x0001
243 #define ALDPS_PROXY_MODE 0x0001
246 #define LINK_ON_WAKE_EN 0x0010
247 #define LINK_OFF_WAKE_EN 0x0008
250 #define BWF_EN 0x0040
251 #define MWF_EN 0x0020
252 #define UWF_EN 0x0010
253 #define LAN_WAKE_EN 0x0002
255 /* PLA_LED_FEATURE */
256 #define LED_MODE_MASK 0x0700
259 #define TX_10M_IDLE_EN 0x0080
260 #define PFM_PWM_SWITCH 0x0040
262 /* PLA_MAC_PWR_CTRL */
263 #define D3_CLK_GATED_EN 0x00004000
264 #define MCU_CLK_RATIO 0x07010f07
265 #define MCU_CLK_RATIO_MASK 0x0f0f0f0f
266 #define ALDPS_SPDWN_RATIO 0x0f87
268 /* PLA_MAC_PWR_CTRL2 */
269 #define EEE_SPDWN_RATIO 0x8007
271 /* PLA_MAC_PWR_CTRL3 */
272 #define PKT_AVAIL_SPDWN_EN 0x0100
273 #define SUSPEND_SPDWN_EN 0x0004
274 #define U1U2_SPDWN_EN 0x0002
275 #define L1_SPDWN_EN 0x0001
277 /* PLA_MAC_PWR_CTRL4 */
278 #define PWRSAVE_SPDWN_EN 0x1000
279 #define RXDV_SPDWN_EN 0x0800
280 #define TX10MIDLE_EN 0x0100
281 #define TP100_SPDWN_EN 0x0020
282 #define TP500_SPDWN_EN 0x0010
283 #define TP1000_SPDWN_EN 0x0008
284 #define EEE_SPDWN_EN 0x0001
286 /* PLA_GPHY_INTR_IMR */
287 #define GPHY_STS_MSK 0x0001
288 #define SPEED_DOWN_MSK 0x0002
289 #define SPDWN_RXDV_MSK 0x0004
290 #define SPDWN_LINKCHG_MSK 0x0008
293 #define PHYAR_FLAG 0x80000000
296 #define EEE_RX_EN 0x0001
297 #define EEE_TX_EN 0x0002
300 #define AUTOLOAD_DONE 0x0002
303 #define USB2PHY_SUSPEND 0x0001
304 #define USB2PHY_L1 0x0002
307 #define pwd_dn_scale_mask 0x3ffe
308 #define pwd_dn_scale(x) ((x) << 1)
311 #define DYNAMIC_BURST 0x0001
314 #define EP4_FULL_FC 0x0001
317 #define STAT_SPEED_MASK 0x0006
318 #define STAT_SPEED_HIGH 0x0000
319 #define STAT_SPEED_FULL 0x0002
322 #define TX_AGG_MAX_THRESHOLD 0x03
325 #define RX_THR_SUPPER 0x0c350180
326 #define RX_THR_HIGH 0x7a120180
327 #define RX_THR_SLOW 0xffff0180
330 #define TEST_MODE_DISABLE 0x00000001
331 #define TX_SIZE_ADJUST1 0x00000100
334 #define POWER_CUT 0x0100
336 /* USB_PM_CTRL_STATUS */
337 #define RESUME_INDICATE 0x0001
340 #define RX_AGG_DISABLE 0x0010
343 #define U2P3_ENABLE 0x0001
346 #define PWR_EN 0x0001
347 #define PHASE2_EN 0x0008
350 #define PCUT_STATUS 0x0001
352 /* USB_RX_EARLY_AGG */
353 #define EARLY_AGG_SUPPER 0x0e832981
354 #define EARLY_AGG_HIGH 0x0e837a12
355 #define EARLY_AGG_SLOW 0x0e83ffff
358 #define TIMER11_EN 0x0001
361 /* bit 4 ~ 5: fifo empty boundary */
362 #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */
363 /* bit 2 ~ 3: LMP timer */
364 #define LPM_TIMER_MASK 0x0c
365 #define LPM_TIMER_500MS 0x04 /* 500 ms */
366 #define LPM_TIMER_500US 0x0c /* 500 us */
367 #define ROK_EXIT_LPM 0x02
370 #define SEN_VAL_MASK 0xf800
371 #define SEN_VAL_NORMAL 0xa000
372 #define SEL_RXIDLE 0x0100
374 /* OCP_ALDPS_CONFIG */
375 #define ENPWRSAVE 0x8000
376 #define ENPDNPS 0x0200
377 #define LINKENA 0x0100
378 #define DIS_SDSAVE 0x0010
381 #define PHY_STAT_MASK 0x0007
382 #define PHY_STAT_LAN_ON 3
383 #define PHY_STAT_PWRDN 5
386 #define EEE_CLKDIV_EN 0x8000
387 #define EN_ALDPS 0x0004
388 #define EN_10M_PLLOFF 0x0001
390 /* OCP_EEE_CONFIG1 */
391 #define RG_TXLPI_MSK_HFDUP 0x8000
392 #define RG_MATCLR_EN 0x4000
393 #define EEE_10_CAP 0x2000
394 #define EEE_NWAY_EN 0x1000
395 #define TX_QUIET_EN 0x0200
396 #define RX_QUIET_EN 0x0100
397 #define sd_rise_time_mask 0x0070
398 #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */
399 #define RG_RXLPI_MSK_HFDUP 0x0008
400 #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
402 /* OCP_EEE_CONFIG2 */
403 #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
404 #define RG_DACQUIET_EN 0x0400
405 #define RG_LDVQUIET_EN 0x0200
406 #define RG_CKRSEL 0x0020
407 #define RG_EEEPRG_EN 0x0010
409 /* OCP_EEE_CONFIG3 */
410 #define fast_snr_mask 0xff80
411 #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */
412 #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
413 #define MSK_PH 0x0006 /* bit 0 ~ 3 */
416 /* bit[15:14] function */
417 #define FUN_ADDR 0x0000
418 #define FUN_DATA 0x4000
419 /* bit[4:0] device addr */
422 #define CTAP_SHORT_EN 0x0040
423 #define EEE10_EN 0x0010
426 #define EN_10M_BGOFF 0x0080
429 #define CKADSEL_L 0x0100
430 #define ADC_EN 0x0080
431 #define EN_EMI_L 0x0040
434 #define LPF_AUTO_TUNE 0x8000
437 #define GDAC_IB_UPALL 0x0008
440 #define AMP_DN 0x0200
443 #define RX_DRIVING_MASK 0x6000
445 enum rtl_register_content {
453 #define RTL8152_MAX_TX 4
454 #define RTL8152_MAX_RX 10
460 #define INTR_LINK 0x0004
462 #define RTL8152_REQT_READ 0xc0
463 #define RTL8152_REQT_WRITE 0x40
464 #define RTL8152_REQ_GET_REGS 0x05
465 #define RTL8152_REQ_SET_REGS 0x05
467 #define BYTE_EN_DWORD 0xff
468 #define BYTE_EN_WORD 0x33
469 #define BYTE_EN_BYTE 0x11
470 #define BYTE_EN_SIX_BYTES 0x3f
471 #define BYTE_EN_START_MASK 0x0f
472 #define BYTE_EN_END_MASK 0xf0
474 #define RTL8153_MAX_PACKET 9216 /* 9K */
475 #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - VLAN_HLEN)
476 #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN)
477 #define RTL8153_RMS RTL8153_MAX_PACKET
478 #define RTL8152_TX_TIMEOUT (5 * HZ)
479 #define RTL8152_NAPI_WEIGHT 64
492 /* Define these values to match your device */
493 #define VENDOR_ID_REALTEK 0x0bda
494 #define VENDOR_ID_SAMSUNG 0x04e8
495 #define VENDOR_ID_LENOVO 0x17ef
497 #define MCU_TYPE_PLA 0x0100
498 #define MCU_TYPE_USB 0x0000
500 struct tally_counter {
507 __le32 tx_one_collision;
508 __le32 tx_multi_collision;
518 #define RX_LEN_MASK 0x7fff
521 #define RD_UDP_CS BIT(23)
522 #define RD_TCP_CS BIT(22)
523 #define RD_IPV6_CS BIT(20)
524 #define RD_IPV4_CS BIT(19)
527 #define IPF BIT(23) /* IP checksum fail */
528 #define UDPF BIT(22) /* UDP checksum fail */
529 #define TCPF BIT(21) /* TCP checksum fail */
530 #define RX_VLAN_TAG BIT(16)
539 #define TX_FS BIT(31) /* First segment of a packet */
540 #define TX_LS BIT(30) /* Final segment of a packet */
541 #define GTSENDV4 BIT(28)
542 #define GTSENDV6 BIT(27)
543 #define GTTCPHO_SHIFT 18
544 #define GTTCPHO_MAX 0x7fU
545 #define TX_LEN_MAX 0x3ffffU
548 #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */
549 #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */
550 #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */
551 #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */
553 #define MSS_MAX 0x7ffU
554 #define TCPHO_SHIFT 17
555 #define TCPHO_MAX 0x7ffU
556 #define TX_VLAN_TAG BIT(16)
562 struct list_head list;
564 struct r8152 *context;
570 struct list_head list;
572 struct r8152 *context;
581 struct usb_device *udev;
582 struct napi_struct napi;
583 struct usb_interface *intf;
584 struct net_device *netdev;
585 struct urb *intr_urb;
586 struct tx_agg tx_info[RTL8152_MAX_TX];
587 struct rx_agg rx_info[RTL8152_MAX_RX];
588 struct list_head rx_done, tx_free;
589 struct sk_buff_head tx_queue, rx_queue;
590 spinlock_t rx_lock, tx_lock;
591 struct delayed_work schedule;
592 struct mii_if_info mii;
593 struct mutex control; /* use for hw setting */
596 void (*init)(struct r8152 *);
597 int (*enable)(struct r8152 *);
598 void (*disable)(struct r8152 *);
599 void (*up)(struct r8152 *);
600 void (*down)(struct r8152 *);
601 void (*unload)(struct r8152 *);
602 int (*eee_get)(struct r8152 *, struct ethtool_eee *);
603 int (*eee_set)(struct r8152 *, struct ethtool_eee *);
631 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
632 * The RTL chips use a 64 element hash table based on the Ethernet CRC.
634 static const int multicast_filter_limit = 32;
635 static unsigned int agg_buf_sz = 16384;
637 #define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \
638 VLAN_ETH_HLEN - VLAN_HLEN)
641 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
646 tmp = kmalloc(size, GFP_KERNEL);
650 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
651 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
652 value, index, tmp, size, 500);
654 memcpy(data, tmp, size);
661 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
666 tmp = kmemdup(data, size, GFP_KERNEL);
670 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
671 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
672 value, index, tmp, size, 500);
679 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
680 void *data, u16 type)
685 if (test_bit(RTL8152_UNPLUG, &tp->flags))
688 /* both size and indix must be 4 bytes align */
689 if ((size & 3) || !size || (index & 3) || !data)
692 if ((u32)index + (u32)size > 0xffff)
697 ret = get_registers(tp, index, type, limit, data);
705 ret = get_registers(tp, index, type, size, data);
717 set_bit(RTL8152_UNPLUG, &tp->flags);
722 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
723 u16 size, void *data, u16 type)
726 u16 byteen_start, byteen_end, byen;
729 if (test_bit(RTL8152_UNPLUG, &tp->flags))
732 /* both size and indix must be 4 bytes align */
733 if ((size & 3) || !size || (index & 3) || !data)
736 if ((u32)index + (u32)size > 0xffff)
739 byteen_start = byteen & BYTE_EN_START_MASK;
740 byteen_end = byteen & BYTE_EN_END_MASK;
742 byen = byteen_start | (byteen_start << 4);
743 ret = set_registers(tp, index, type | byen, 4, data);
756 ret = set_registers(tp, index,
757 type | BYTE_EN_DWORD,
766 ret = set_registers(tp, index,
767 type | BYTE_EN_DWORD,
779 byen = byteen_end | (byteen_end >> 4);
780 ret = set_registers(tp, index, type | byen, 4, data);
787 set_bit(RTL8152_UNPLUG, &tp->flags);
793 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
795 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
799 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
801 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
805 int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
807 return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB);
811 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
813 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
816 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
820 generic_ocp_read(tp, index, sizeof(data), &data, type);
822 return __le32_to_cpu(data);
825 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
827 __le32 tmp = __cpu_to_le32(data);
829 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
832 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
836 u8 shift = index & 2;
840 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
842 data = __le32_to_cpu(tmp);
843 data >>= (shift * 8);
849 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
853 u16 byen = BYTE_EN_WORD;
854 u8 shift = index & 2;
860 mask <<= (shift * 8);
861 data <<= (shift * 8);
865 tmp = __cpu_to_le32(data);
867 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
870 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
874 u8 shift = index & 3;
878 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
880 data = __le32_to_cpu(tmp);
881 data >>= (shift * 8);
887 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
891 u16 byen = BYTE_EN_BYTE;
892 u8 shift = index & 3;
898 mask <<= (shift * 8);
899 data <<= (shift * 8);
903 tmp = __cpu_to_le32(data);
905 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
908 static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
910 u16 ocp_base, ocp_index;
912 ocp_base = addr & 0xf000;
913 if (ocp_base != tp->ocp_base) {
914 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
915 tp->ocp_base = ocp_base;
918 ocp_index = (addr & 0x0fff) | 0xb000;
919 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
922 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
924 u16 ocp_base, ocp_index;
926 ocp_base = addr & 0xf000;
927 if (ocp_base != tp->ocp_base) {
928 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
929 tp->ocp_base = ocp_base;
932 ocp_index = (addr & 0x0fff) | 0xb000;
933 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
936 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
938 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
941 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
943 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
946 static void sram_write(struct r8152 *tp, u16 addr, u16 data)
948 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
949 ocp_reg_write(tp, OCP_SRAM_DATA, data);
952 static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
954 struct r8152 *tp = netdev_priv(netdev);
957 if (test_bit(RTL8152_UNPLUG, &tp->flags))
960 if (phy_id != R8152_PHY_ID)
963 ret = r8152_mdio_read(tp, reg);
969 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
971 struct r8152 *tp = netdev_priv(netdev);
973 if (test_bit(RTL8152_UNPLUG, &tp->flags))
976 if (phy_id != R8152_PHY_ID)
979 r8152_mdio_write(tp, reg, val);
983 r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
985 static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
987 struct r8152 *tp = netdev_priv(netdev);
988 struct sockaddr *addr = p;
989 int ret = -EADDRNOTAVAIL;
991 if (!is_valid_ether_addr(addr->sa_data))
994 ret = usb_autopm_get_interface(tp->intf);
998 mutex_lock(&tp->control);
1000 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1002 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1003 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
1004 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1006 mutex_unlock(&tp->control);
1008 usb_autopm_put_interface(tp->intf);
1013 static int set_ethernet_addr(struct r8152 *tp)
1015 struct net_device *dev = tp->netdev;
1019 if (tp->version == RTL_VER_01)
1020 ret = pla_ocp_read(tp, PLA_IDR, 8, sa.sa_data);
1022 ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa.sa_data);
1025 netif_err(tp, probe, dev, "Get ether addr fail\n");
1026 } else if (!is_valid_ether_addr(sa.sa_data)) {
1027 netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
1029 eth_hw_addr_random(dev);
1030 ether_addr_copy(sa.sa_data, dev->dev_addr);
1031 ret = rtl8152_set_mac_address(dev, &sa);
1032 netif_info(tp, probe, dev, "Random ether addr %pM\n",
1035 if (tp->version == RTL_VER_01)
1036 ether_addr_copy(dev->dev_addr, sa.sa_data);
1038 ret = rtl8152_set_mac_address(dev, &sa);
1044 static void read_bulk_callback(struct urb *urb)
1046 struct net_device *netdev;
1047 int status = urb->status;
1059 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1062 if (!test_bit(WORK_ENABLE, &tp->flags))
1065 netdev = tp->netdev;
1067 /* When link down, the driver would cancel all bulks. */
1068 /* This avoid the re-submitting bulk */
1069 if (!netif_carrier_ok(netdev))
1072 usb_mark_last_busy(tp->udev);
1076 if (urb->actual_length < ETH_ZLEN)
1079 spin_lock(&tp->rx_lock);
1080 list_add_tail(&agg->list, &tp->rx_done);
1081 spin_unlock(&tp->rx_lock);
1082 napi_schedule(&tp->napi);
1085 set_bit(RTL8152_UNPLUG, &tp->flags);
1086 netif_device_detach(tp->netdev);
1089 return; /* the urb is in unlink state */
1091 if (net_ratelimit())
1092 netdev_warn(netdev, "maybe reset is needed?\n");
1095 if (net_ratelimit())
1096 netdev_warn(netdev, "Rx status %d\n", status);
1100 r8152_submit_rx(tp, agg, GFP_ATOMIC);
1103 static void write_bulk_callback(struct urb *urb)
1105 struct net_device_stats *stats;
1106 struct net_device *netdev;
1109 int status = urb->status;
1119 netdev = tp->netdev;
1120 stats = &netdev->stats;
1122 if (net_ratelimit())
1123 netdev_warn(netdev, "Tx status %d\n", status);
1124 stats->tx_errors += agg->skb_num;
1126 stats->tx_packets += agg->skb_num;
1127 stats->tx_bytes += agg->skb_len;
1130 spin_lock(&tp->tx_lock);
1131 list_add_tail(&agg->list, &tp->tx_free);
1132 spin_unlock(&tp->tx_lock);
1134 usb_autopm_put_interface_async(tp->intf);
1136 if (!netif_carrier_ok(netdev))
1139 if (!test_bit(WORK_ENABLE, &tp->flags))
1142 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1145 if (!skb_queue_empty(&tp->tx_queue))
1146 napi_schedule(&tp->napi);
1149 static void intr_callback(struct urb *urb)
1153 int status = urb->status;
1160 if (!test_bit(WORK_ENABLE, &tp->flags))
1163 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1167 case 0: /* success */
1169 case -ECONNRESET: /* unlink */
1171 netif_device_detach(tp->netdev);
1174 netif_info(tp, intr, tp->netdev,
1175 "Stop submitting intr, status %d\n", status);
1178 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
1180 /* -EPIPE: should clear the halt */
1182 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1186 d = urb->transfer_buffer;
1187 if (INTR_LINK & __le16_to_cpu(d[0])) {
1188 if (!netif_carrier_ok(tp->netdev)) {
1189 set_bit(RTL8152_LINK_CHG, &tp->flags);
1190 schedule_delayed_work(&tp->schedule, 0);
1193 if (netif_carrier_ok(tp->netdev)) {
1194 set_bit(RTL8152_LINK_CHG, &tp->flags);
1195 schedule_delayed_work(&tp->schedule, 0);
1200 res = usb_submit_urb(urb, GFP_ATOMIC);
1201 if (res == -ENODEV) {
1202 set_bit(RTL8152_UNPLUG, &tp->flags);
1203 netif_device_detach(tp->netdev);
1205 netif_err(tp, intr, tp->netdev,
1206 "can't resubmit intr, status %d\n", res);
1210 static inline void *rx_agg_align(void *data)
1212 return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
1215 static inline void *tx_agg_align(void *data)
1217 return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
1220 static void free_all_mem(struct r8152 *tp)
1224 for (i = 0; i < RTL8152_MAX_RX; i++) {
1225 usb_free_urb(tp->rx_info[i].urb);
1226 tp->rx_info[i].urb = NULL;
1228 kfree(tp->rx_info[i].buffer);
1229 tp->rx_info[i].buffer = NULL;
1230 tp->rx_info[i].head = NULL;
1233 for (i = 0; i < RTL8152_MAX_TX; i++) {
1234 usb_free_urb(tp->tx_info[i].urb);
1235 tp->tx_info[i].urb = NULL;
1237 kfree(tp->tx_info[i].buffer);
1238 tp->tx_info[i].buffer = NULL;
1239 tp->tx_info[i].head = NULL;
1242 usb_free_urb(tp->intr_urb);
1243 tp->intr_urb = NULL;
1245 kfree(tp->intr_buff);
1246 tp->intr_buff = NULL;
1249 static int alloc_all_mem(struct r8152 *tp)
1251 struct net_device *netdev = tp->netdev;
1252 struct usb_interface *intf = tp->intf;
1253 struct usb_host_interface *alt = intf->cur_altsetting;
1254 struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
1259 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1261 spin_lock_init(&tp->rx_lock);
1262 spin_lock_init(&tp->tx_lock);
1263 INIT_LIST_HEAD(&tp->tx_free);
1264 skb_queue_head_init(&tp->tx_queue);
1265 skb_queue_head_init(&tp->rx_queue);
1267 for (i = 0; i < RTL8152_MAX_RX; i++) {
1268 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1272 if (buf != rx_agg_align(buf)) {
1274 buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL,
1280 urb = usb_alloc_urb(0, GFP_KERNEL);
1286 INIT_LIST_HEAD(&tp->rx_info[i].list);
1287 tp->rx_info[i].context = tp;
1288 tp->rx_info[i].urb = urb;
1289 tp->rx_info[i].buffer = buf;
1290 tp->rx_info[i].head = rx_agg_align(buf);
1293 for (i = 0; i < RTL8152_MAX_TX; i++) {
1294 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1298 if (buf != tx_agg_align(buf)) {
1300 buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
1306 urb = usb_alloc_urb(0, GFP_KERNEL);
1312 INIT_LIST_HEAD(&tp->tx_info[i].list);
1313 tp->tx_info[i].context = tp;
1314 tp->tx_info[i].urb = urb;
1315 tp->tx_info[i].buffer = buf;
1316 tp->tx_info[i].head = tx_agg_align(buf);
1318 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
1321 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
1325 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
1329 tp->intr_interval = (int)ep_intr->desc.bInterval;
1330 usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
1331 tp->intr_buff, INTBUFSIZE, intr_callback,
1332 tp, tp->intr_interval);
1341 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
1343 struct tx_agg *agg = NULL;
1344 unsigned long flags;
1346 if (list_empty(&tp->tx_free))
1349 spin_lock_irqsave(&tp->tx_lock, flags);
1350 if (!list_empty(&tp->tx_free)) {
1351 struct list_head *cursor;
1353 cursor = tp->tx_free.next;
1354 list_del_init(cursor);
1355 agg = list_entry(cursor, struct tx_agg, list);
1357 spin_unlock_irqrestore(&tp->tx_lock, flags);
1362 /* r8152_csum_workaround()
1363 * The hw limites the value the transport offset. When the offset is out of the
1364 * range, calculate the checksum by sw.
1366 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
1367 struct sk_buff_head *list)
1369 if (skb_shinfo(skb)->gso_size) {
1370 netdev_features_t features = tp->netdev->features;
1371 struct sk_buff_head seg_list;
1372 struct sk_buff *segs, *nskb;
1374 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
1375 segs = skb_gso_segment(skb, features);
1376 if (IS_ERR(segs) || !segs)
1379 __skb_queue_head_init(&seg_list);
1385 __skb_queue_tail(&seg_list, nskb);
1388 skb_queue_splice(&seg_list, list);
1390 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1391 if (skb_checksum_help(skb) < 0)
1394 __skb_queue_head(list, skb);
1396 struct net_device_stats *stats;
1399 stats = &tp->netdev->stats;
1400 stats->tx_dropped++;
1405 /* msdn_giant_send_check()
1406 * According to the document of microsoft, the TCP Pseudo Header excludes the
1407 * packet length for IPv6 TCP large packets.
1409 static int msdn_giant_send_check(struct sk_buff *skb)
1411 const struct ipv6hdr *ipv6h;
1415 ret = skb_cow_head(skb, 0);
1419 ipv6h = ipv6_hdr(skb);
1423 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
1428 static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
1430 if (skb_vlan_tag_present(skb)) {
1433 opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
1434 desc->opts2 |= cpu_to_le32(opts2);
1438 static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
1440 u32 opts2 = le32_to_cpu(desc->opts2);
1442 if (opts2 & RX_VLAN_TAG)
1443 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1444 swab16(opts2 & 0xffff));
1447 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
1448 struct sk_buff *skb, u32 len, u32 transport_offset)
1450 u32 mss = skb_shinfo(skb)->gso_size;
1451 u32 opts1, opts2 = 0;
1452 int ret = TX_CSUM_SUCCESS;
1454 WARN_ON_ONCE(len > TX_LEN_MAX);
1456 opts1 = len | TX_FS | TX_LS;
1459 if (transport_offset > GTTCPHO_MAX) {
1460 netif_warn(tp, tx_err, tp->netdev,
1461 "Invalid transport offset 0x%x for TSO\n",
1467 switch (vlan_get_protocol(skb)) {
1468 case htons(ETH_P_IP):
1472 case htons(ETH_P_IPV6):
1473 if (msdn_giant_send_check(skb)) {
1485 opts1 |= transport_offset << GTTCPHO_SHIFT;
1486 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
1487 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1490 if (transport_offset > TCPHO_MAX) {
1491 netif_warn(tp, tx_err, tp->netdev,
1492 "Invalid transport offset 0x%x\n",
1498 switch (vlan_get_protocol(skb)) {
1499 case htons(ETH_P_IP):
1501 ip_protocol = ip_hdr(skb)->protocol;
1504 case htons(ETH_P_IPV6):
1506 ip_protocol = ipv6_hdr(skb)->nexthdr;
1510 ip_protocol = IPPROTO_RAW;
1514 if (ip_protocol == IPPROTO_TCP)
1516 else if (ip_protocol == IPPROTO_UDP)
1521 opts2 |= transport_offset << TCPHO_SHIFT;
1524 desc->opts2 = cpu_to_le32(opts2);
1525 desc->opts1 = cpu_to_le32(opts1);
1531 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
1533 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
1537 __skb_queue_head_init(&skb_head);
1538 spin_lock(&tx_queue->lock);
1539 skb_queue_splice_init(tx_queue, &skb_head);
1540 spin_unlock(&tx_queue->lock);
1542 tx_data = agg->head;
1545 remain = agg_buf_sz;
1547 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
1548 struct tx_desc *tx_desc;
1549 struct sk_buff *skb;
1553 skb = __skb_dequeue(&skb_head);
1557 len = skb->len + sizeof(*tx_desc);
1560 __skb_queue_head(&skb_head, skb);
1564 tx_data = tx_agg_align(tx_data);
1565 tx_desc = (struct tx_desc *)tx_data;
1567 offset = (u32)skb_transport_offset(skb);
1569 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
1570 r8152_csum_workaround(tp, skb, &skb_head);
1574 rtl_tx_vlan_tag(tx_desc, skb);
1576 tx_data += sizeof(*tx_desc);
1579 if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
1580 struct net_device_stats *stats = &tp->netdev->stats;
1582 stats->tx_dropped++;
1583 dev_kfree_skb_any(skb);
1584 tx_data -= sizeof(*tx_desc);
1589 agg->skb_len += len;
1592 dev_kfree_skb_any(skb);
1594 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
1597 if (!skb_queue_empty(&skb_head)) {
1598 spin_lock(&tx_queue->lock);
1599 skb_queue_splice(&skb_head, tx_queue);
1600 spin_unlock(&tx_queue->lock);
1603 netif_tx_lock(tp->netdev);
1605 if (netif_queue_stopped(tp->netdev) &&
1606 skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
1607 netif_wake_queue(tp->netdev);
1609 netif_tx_unlock(tp->netdev);
1611 ret = usb_autopm_get_interface_async(tp->intf);
1615 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
1616 agg->head, (int)(tx_data - (u8 *)agg->head),
1617 (usb_complete_t)write_bulk_callback, agg);
1619 ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
1621 usb_autopm_put_interface_async(tp->intf);
1627 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
1629 u8 checksum = CHECKSUM_NONE;
1632 if (tp->version == RTL_VER_01)
1635 opts2 = le32_to_cpu(rx_desc->opts2);
1636 opts3 = le32_to_cpu(rx_desc->opts3);
1638 if (opts2 & RD_IPV4_CS) {
1640 checksum = CHECKSUM_NONE;
1641 else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF))
1642 checksum = CHECKSUM_NONE;
1643 else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF))
1644 checksum = CHECKSUM_NONE;
1646 checksum = CHECKSUM_UNNECESSARY;
1647 } else if (RD_IPV6_CS) {
1648 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
1649 checksum = CHECKSUM_UNNECESSARY;
1650 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
1651 checksum = CHECKSUM_UNNECESSARY;
1658 static int rx_bottom(struct r8152 *tp, int budget)
1660 unsigned long flags;
1661 struct list_head *cursor, *next, rx_queue;
1662 int ret = 0, work_done = 0;
1664 if (!skb_queue_empty(&tp->rx_queue)) {
1665 while (work_done < budget) {
1666 struct sk_buff *skb = __skb_dequeue(&tp->rx_queue);
1667 struct net_device *netdev = tp->netdev;
1668 struct net_device_stats *stats = &netdev->stats;
1669 unsigned int pkt_len;
1675 napi_gro_receive(&tp->napi, skb);
1677 stats->rx_packets++;
1678 stats->rx_bytes += pkt_len;
1682 if (list_empty(&tp->rx_done))
1685 INIT_LIST_HEAD(&rx_queue);
1686 spin_lock_irqsave(&tp->rx_lock, flags);
1687 list_splice_init(&tp->rx_done, &rx_queue);
1688 spin_unlock_irqrestore(&tp->rx_lock, flags);
1690 list_for_each_safe(cursor, next, &rx_queue) {
1691 struct rx_desc *rx_desc;
1697 list_del_init(cursor);
1699 agg = list_entry(cursor, struct rx_agg, list);
1701 if (urb->actual_length < ETH_ZLEN)
1704 rx_desc = agg->head;
1705 rx_data = agg->head;
1706 len_used += sizeof(struct rx_desc);
1708 while (urb->actual_length > len_used) {
1709 struct net_device *netdev = tp->netdev;
1710 struct net_device_stats *stats = &netdev->stats;
1711 unsigned int pkt_len;
1712 struct sk_buff *skb;
1714 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
1715 if (pkt_len < ETH_ZLEN)
1718 len_used += pkt_len;
1719 if (urb->actual_length < len_used)
1722 pkt_len -= CRC_SIZE;
1723 rx_data += sizeof(struct rx_desc);
1725 skb = netdev_alloc_skb_ip_align(netdev, pkt_len);
1727 stats->rx_dropped++;
1731 skb->ip_summed = r8152_rx_csum(tp, rx_desc);
1732 memcpy(skb->data, rx_data, pkt_len);
1733 skb_put(skb, pkt_len);
1734 skb->protocol = eth_type_trans(skb, netdev);
1735 rtl_rx_vlan_tag(rx_desc, skb);
1736 if (work_done < budget) {
1737 napi_gro_receive(&tp->napi, skb);
1739 stats->rx_packets++;
1740 stats->rx_bytes += pkt_len;
1742 __skb_queue_tail(&tp->rx_queue, skb);
1746 rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE);
1747 rx_desc = (struct rx_desc *)rx_data;
1748 len_used = (int)(rx_data - (u8 *)agg->head);
1749 len_used += sizeof(struct rx_desc);
1754 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
1756 urb->actual_length = 0;
1757 list_add_tail(&agg->list, next);
1761 if (!list_empty(&rx_queue)) {
1762 spin_lock_irqsave(&tp->rx_lock, flags);
1763 list_splice_tail(&rx_queue, &tp->rx_done);
1764 spin_unlock_irqrestore(&tp->rx_lock, flags);
1771 static void tx_bottom(struct r8152 *tp)
1778 if (skb_queue_empty(&tp->tx_queue))
1781 agg = r8152_get_tx_agg(tp);
1785 res = r8152_tx_agg_fill(tp, agg);
1787 struct net_device *netdev = tp->netdev;
1789 if (res == -ENODEV) {
1790 set_bit(RTL8152_UNPLUG, &tp->flags);
1791 netif_device_detach(netdev);
1793 struct net_device_stats *stats = &netdev->stats;
1794 unsigned long flags;
1796 netif_warn(tp, tx_err, netdev,
1797 "failed tx_urb %d\n", res);
1798 stats->tx_dropped += agg->skb_num;
1800 spin_lock_irqsave(&tp->tx_lock, flags);
1801 list_add_tail(&agg->list, &tp->tx_free);
1802 spin_unlock_irqrestore(&tp->tx_lock, flags);
1808 static void bottom_half(struct r8152 *tp)
1810 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1813 if (!test_bit(WORK_ENABLE, &tp->flags))
1816 /* When link down, the driver would cancel all bulks. */
1817 /* This avoid the re-submitting bulk */
1818 if (!netif_carrier_ok(tp->netdev))
1821 clear_bit(SCHEDULE_NAPI, &tp->flags);
1826 static int r8152_poll(struct napi_struct *napi, int budget)
1828 struct r8152 *tp = container_of(napi, struct r8152, napi);
1831 work_done = rx_bottom(tp, budget);
1834 if (work_done < budget) {
1835 napi_complete(napi);
1836 if (!list_empty(&tp->rx_done))
1837 napi_schedule(napi);
1844 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
1848 /* The rx would be stopped, so skip submitting */
1849 if (test_bit(RTL8152_UNPLUG, &tp->flags) ||
1850 !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))
1853 usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
1854 agg->head, agg_buf_sz,
1855 (usb_complete_t)read_bulk_callback, agg);
1857 ret = usb_submit_urb(agg->urb, mem_flags);
1858 if (ret == -ENODEV) {
1859 set_bit(RTL8152_UNPLUG, &tp->flags);
1860 netif_device_detach(tp->netdev);
1862 struct urb *urb = agg->urb;
1863 unsigned long flags;
1865 urb->actual_length = 0;
1866 spin_lock_irqsave(&tp->rx_lock, flags);
1867 list_add_tail(&agg->list, &tp->rx_done);
1868 spin_unlock_irqrestore(&tp->rx_lock, flags);
1870 netif_err(tp, rx_err, tp->netdev,
1871 "Couldn't submit rx[%p], ret = %d\n", agg, ret);
1873 napi_schedule(&tp->napi);
1879 static void rtl_drop_queued_tx(struct r8152 *tp)
1881 struct net_device_stats *stats = &tp->netdev->stats;
1882 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
1883 struct sk_buff *skb;
1885 if (skb_queue_empty(tx_queue))
1888 __skb_queue_head_init(&skb_head);
1889 spin_lock_bh(&tx_queue->lock);
1890 skb_queue_splice_init(tx_queue, &skb_head);
1891 spin_unlock_bh(&tx_queue->lock);
1893 while ((skb = __skb_dequeue(&skb_head))) {
1895 stats->tx_dropped++;
1899 static void rtl8152_tx_timeout(struct net_device *netdev)
1901 struct r8152 *tp = netdev_priv(netdev);
1904 netif_warn(tp, tx_err, netdev, "Tx timeout\n");
1905 for (i = 0; i < RTL8152_MAX_TX; i++)
1906 usb_unlink_urb(tp->tx_info[i].urb);
1909 static void rtl8152_set_rx_mode(struct net_device *netdev)
1911 struct r8152 *tp = netdev_priv(netdev);
1913 if (netif_carrier_ok(netdev)) {
1914 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
1915 schedule_delayed_work(&tp->schedule, 0);
1919 static void _rtl8152_set_rx_mode(struct net_device *netdev)
1921 struct r8152 *tp = netdev_priv(netdev);
1922 u32 mc_filter[2]; /* Multicast hash filter */
1926 clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
1927 netif_stop_queue(netdev);
1928 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1929 ocp_data &= ~RCR_ACPT_ALL;
1930 ocp_data |= RCR_AB | RCR_APM;
1932 if (netdev->flags & IFF_PROMISC) {
1933 /* Unconditionally log net taps. */
1934 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
1935 ocp_data |= RCR_AM | RCR_AAP;
1936 mc_filter[1] = 0xffffffff;
1937 mc_filter[0] = 0xffffffff;
1938 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
1939 (netdev->flags & IFF_ALLMULTI)) {
1940 /* Too many to filter perfectly -- accept all multicasts. */
1942 mc_filter[1] = 0xffffffff;
1943 mc_filter[0] = 0xffffffff;
1945 struct netdev_hw_addr *ha;
1949 netdev_for_each_mc_addr(ha, netdev) {
1950 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1952 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1957 tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
1958 tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
1960 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
1961 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1962 netif_wake_queue(netdev);
1965 static netdev_features_t
1966 rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
1967 netdev_features_t features)
1969 u32 mss = skb_shinfo(skb)->gso_size;
1970 int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
1971 int offset = skb_transport_offset(skb);
1973 if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset)
1974 features &= ~(NETIF_F_ALL_CSUM | NETIF_F_GSO_MASK);
1975 else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
1976 features &= ~NETIF_F_GSO_MASK;
1981 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
1982 struct net_device *netdev)
1984 struct r8152 *tp = netdev_priv(netdev);
1986 skb_tx_timestamp(skb);
1988 skb_queue_tail(&tp->tx_queue, skb);
1990 if (!list_empty(&tp->tx_free)) {
1991 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
1992 set_bit(SCHEDULE_NAPI, &tp->flags);
1993 schedule_delayed_work(&tp->schedule, 0);
1995 usb_mark_last_busy(tp->udev);
1996 napi_schedule(&tp->napi);
1998 } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
1999 netif_stop_queue(netdev);
2002 return NETDEV_TX_OK;
2005 static void r8152b_reset_packet_filter(struct r8152 *tp)
2009 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
2010 ocp_data &= ~FMC_FCR_MCU_EN;
2011 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2012 ocp_data |= FMC_FCR_MCU_EN;
2013 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2016 static void rtl8152_nic_reset(struct r8152 *tp)
2020 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
2022 for (i = 0; i < 1000; i++) {
2023 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
2025 usleep_range(100, 400);
2029 static void set_tx_qlen(struct r8152 *tp)
2031 struct net_device *netdev = tp->netdev;
2033 tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN +
2034 sizeof(struct tx_desc));
2037 static inline u8 rtl8152_get_speed(struct r8152 *tp)
2039 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
2042 static void rtl_set_eee_plus(struct r8152 *tp)
2047 speed = rtl8152_get_speed(tp);
2048 if (speed & _10bps) {
2049 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2050 ocp_data |= EEEP_CR_EEEP_TX;
2051 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2053 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2054 ocp_data &= ~EEEP_CR_EEEP_TX;
2055 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2059 static void rxdy_gated_en(struct r8152 *tp, bool enable)
2063 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
2065 ocp_data |= RXDY_GATED_EN;
2067 ocp_data &= ~RXDY_GATED_EN;
2068 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
2071 static int rtl_start_rx(struct r8152 *tp)
2075 napi_disable(&tp->napi);
2076 INIT_LIST_HEAD(&tp->rx_done);
2077 for (i = 0; i < RTL8152_MAX_RX; i++) {
2078 INIT_LIST_HEAD(&tp->rx_info[i].list);
2079 ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
2083 napi_enable(&tp->napi);
2085 if (ret && ++i < RTL8152_MAX_RX) {
2086 struct list_head rx_queue;
2087 unsigned long flags;
2089 INIT_LIST_HEAD(&rx_queue);
2092 struct rx_agg *agg = &tp->rx_info[i++];
2093 struct urb *urb = agg->urb;
2095 urb->actual_length = 0;
2096 list_add_tail(&agg->list, &rx_queue);
2097 } while (i < RTL8152_MAX_RX);
2099 spin_lock_irqsave(&tp->rx_lock, flags);
2100 list_splice_tail(&rx_queue, &tp->rx_done);
2101 spin_unlock_irqrestore(&tp->rx_lock, flags);
2107 static int rtl_stop_rx(struct r8152 *tp)
2111 for (i = 0; i < RTL8152_MAX_RX; i++)
2112 usb_kill_urb(tp->rx_info[i].urb);
2114 while (!skb_queue_empty(&tp->rx_queue))
2115 dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
2120 static int rtl_enable(struct r8152 *tp)
2124 r8152b_reset_packet_filter(tp);
2126 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2127 ocp_data |= CR_RE | CR_TE;
2128 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2130 rxdy_gated_en(tp, false);
2135 static int rtl8152_enable(struct r8152 *tp)
2137 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2141 rtl_set_eee_plus(tp);
2143 return rtl_enable(tp);
2146 static void r8153_set_rx_agg(struct r8152 *tp)
2150 speed = rtl8152_get_speed(tp);
2151 if (speed & _1000bps) {
2152 if (tp->udev->speed == USB_SPEED_SUPER) {
2153 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH,
2155 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
2158 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH,
2160 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
2164 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_SLOW);
2165 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
2170 static int rtl8153_enable(struct r8152 *tp)
2172 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2176 rtl_set_eee_plus(tp);
2177 r8153_set_rx_agg(tp);
2179 return rtl_enable(tp);
2182 static void rtl_disable(struct r8152 *tp)
2187 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2188 rtl_drop_queued_tx(tp);
2192 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2193 ocp_data &= ~RCR_ACPT_ALL;
2194 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2196 rtl_drop_queued_tx(tp);
2198 for (i = 0; i < RTL8152_MAX_TX; i++)
2199 usb_kill_urb(tp->tx_info[i].urb);
2201 rxdy_gated_en(tp, true);
2203 for (i = 0; i < 1000; i++) {
2204 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2205 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
2207 usleep_range(1000, 2000);
2210 for (i = 0; i < 1000; i++) {
2211 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
2213 usleep_range(1000, 2000);
2218 rtl8152_nic_reset(tp);
2221 static void r8152_power_cut_en(struct r8152 *tp, bool enable)
2225 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2227 ocp_data |= POWER_CUT;
2229 ocp_data &= ~POWER_CUT;
2230 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2232 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
2233 ocp_data &= ~RESUME_INDICATE;
2234 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
2237 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
2241 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2243 ocp_data |= CPCR_RX_VLAN;
2245 ocp_data &= ~CPCR_RX_VLAN;
2246 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2249 static int rtl8152_set_features(struct net_device *dev,
2250 netdev_features_t features)
2252 netdev_features_t changed = features ^ dev->features;
2253 struct r8152 *tp = netdev_priv(dev);
2256 ret = usb_autopm_get_interface(tp->intf);
2260 mutex_lock(&tp->control);
2262 if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
2263 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2264 rtl_rx_vlan_en(tp, true);
2266 rtl_rx_vlan_en(tp, false);
2269 mutex_unlock(&tp->control);
2271 usb_autopm_put_interface(tp->intf);
2277 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
2279 static u32 __rtl_get_wol(struct r8152 *tp)
2284 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2285 if (!(ocp_data & LAN_WAKE_EN))
2288 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2289 if (ocp_data & LINK_ON_WAKE_EN)
2290 wolopts |= WAKE_PHY;
2292 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2293 if (ocp_data & UWF_EN)
2294 wolopts |= WAKE_UCAST;
2295 if (ocp_data & BWF_EN)
2296 wolopts |= WAKE_BCAST;
2297 if (ocp_data & MWF_EN)
2298 wolopts |= WAKE_MCAST;
2300 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2301 if (ocp_data & MAGIC_EN)
2302 wolopts |= WAKE_MAGIC;
2307 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
2311 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2313 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2314 ocp_data &= ~LINK_ON_WAKE_EN;
2315 if (wolopts & WAKE_PHY)
2316 ocp_data |= LINK_ON_WAKE_EN;
2317 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2319 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2320 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN | LAN_WAKE_EN);
2321 if (wolopts & WAKE_UCAST)
2323 if (wolopts & WAKE_BCAST)
2325 if (wolopts & WAKE_MCAST)
2327 if (wolopts & WAKE_ANY)
2328 ocp_data |= LAN_WAKE_EN;
2329 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
2331 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2333 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2334 ocp_data &= ~MAGIC_EN;
2335 if (wolopts & WAKE_MAGIC)
2336 ocp_data |= MAGIC_EN;
2337 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
2339 if (wolopts & WAKE_ANY)
2340 device_set_wakeup_enable(&tp->udev->dev, true);
2342 device_set_wakeup_enable(&tp->udev->dev, false);
2345 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
2350 __rtl_set_wol(tp, WAKE_ANY);
2352 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2354 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2355 ocp_data |= LINK_OFF_WAKE_EN;
2356 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2358 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2360 __rtl_set_wol(tp, tp->saved_wolopts);
2364 static void rtl_phy_reset(struct r8152 *tp)
2369 clear_bit(PHY_RESET, &tp->flags);
2371 data = r8152_mdio_read(tp, MII_BMCR);
2373 /* don't reset again before the previous one complete */
2374 if (data & BMCR_RESET)
2378 r8152_mdio_write(tp, MII_BMCR, data);
2380 for (i = 0; i < 50; i++) {
2382 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
2387 static void r8153_teredo_off(struct r8152 *tp)
2391 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2392 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN);
2393 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2395 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
2396 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
2397 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
2400 static void r8152b_disable_aldps(struct r8152 *tp)
2402 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE);
2406 static inline void r8152b_enable_aldps(struct r8152 *tp)
2408 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
2409 LINKENA | DIS_SDSAVE);
2412 static void rtl8152_disable(struct r8152 *tp)
2414 r8152b_disable_aldps(tp);
2416 r8152b_enable_aldps(tp);
2419 static void r8152b_hw_phy_cfg(struct r8152 *tp)
2423 data = r8152_mdio_read(tp, MII_BMCR);
2424 if (data & BMCR_PDOWN) {
2425 data &= ~BMCR_PDOWN;
2426 r8152_mdio_write(tp, MII_BMCR, data);
2429 set_bit(PHY_RESET, &tp->flags);
2432 static void r8152b_exit_oob(struct r8152 *tp)
2437 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2438 ocp_data &= ~RCR_ACPT_ALL;
2439 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2441 rxdy_gated_en(tp, true);
2442 r8153_teredo_off(tp);
2443 r8152b_hw_phy_cfg(tp);
2445 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2446 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
2448 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2449 ocp_data &= ~NOW_IS_OOB;
2450 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2452 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2453 ocp_data &= ~MCU_BORW_EN;
2454 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2456 for (i = 0; i < 1000; i++) {
2457 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2458 if (ocp_data & LINK_LIST_READY)
2460 usleep_range(1000, 2000);
2463 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2464 ocp_data |= RE_INIT_LL;
2465 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2467 for (i = 0; i < 1000; i++) {
2468 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2469 if (ocp_data & LINK_LIST_READY)
2471 usleep_range(1000, 2000);
2474 rtl8152_nic_reset(tp);
2476 /* rx share fifo credit full threshold */
2477 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
2479 if (tp->udev->speed == USB_SPEED_FULL ||
2480 tp->udev->speed == USB_SPEED_LOW) {
2481 /* rx share fifo credit near full threshold */
2482 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
2484 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
2487 /* rx share fifo credit near full threshold */
2488 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
2490 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
2494 /* TX share fifo free credit full threshold */
2495 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
2497 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
2498 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
2499 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
2500 TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
2502 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
2504 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2506 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
2507 ocp_data |= TCR0_AUTO_FIFO;
2508 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
2511 static void r8152b_enter_oob(struct r8152 *tp)
2516 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2517 ocp_data &= ~NOW_IS_OOB;
2518 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2520 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
2521 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
2522 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
2526 for (i = 0; i < 1000; i++) {
2527 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2528 if (ocp_data & LINK_LIST_READY)
2530 usleep_range(1000, 2000);
2533 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2534 ocp_data |= RE_INIT_LL;
2535 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2537 for (i = 0; i < 1000; i++) {
2538 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2539 if (ocp_data & LINK_LIST_READY)
2541 usleep_range(1000, 2000);
2544 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2546 rtl_rx_vlan_en(tp, true);
2548 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
2549 ocp_data |= ALDPS_PROXY_MODE;
2550 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
2552 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2553 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
2554 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2556 rxdy_gated_en(tp, false);
2558 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2559 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
2560 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2563 static void r8153_hw_phy_cfg(struct r8152 *tp)
2568 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
2569 data = r8152_mdio_read(tp, MII_BMCR);
2570 if (data & BMCR_PDOWN) {
2571 data &= ~BMCR_PDOWN;
2572 r8152_mdio_write(tp, MII_BMCR, data);
2575 if (tp->version == RTL_VER_03) {
2576 data = ocp_reg_read(tp, OCP_EEE_CFG);
2577 data &= ~CTAP_SHORT_EN;
2578 ocp_reg_write(tp, OCP_EEE_CFG, data);
2581 data = ocp_reg_read(tp, OCP_POWER_CFG);
2582 data |= EEE_CLKDIV_EN;
2583 ocp_reg_write(tp, OCP_POWER_CFG, data);
2585 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
2586 data |= EN_10M_BGOFF;
2587 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
2588 data = ocp_reg_read(tp, OCP_POWER_CFG);
2589 data |= EN_10M_PLLOFF;
2590 ocp_reg_write(tp, OCP_POWER_CFG, data);
2591 sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
2593 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
2594 ocp_data |= PFM_PWM_SWITCH;
2595 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
2597 /* Enable LPF corner auto tune */
2598 sram_write(tp, SRAM_LPF_CFG, 0xf70f);
2600 /* Adjust 10M Amplitude */
2601 sram_write(tp, SRAM_10M_AMP1, 0x00af);
2602 sram_write(tp, SRAM_10M_AMP2, 0x0208);
2604 set_bit(PHY_RESET, &tp->flags);
2607 static void r8153_u1u2en(struct r8152 *tp, bool enable)
2612 memset(u1u2, 0xff, sizeof(u1u2));
2614 memset(u1u2, 0x00, sizeof(u1u2));
2616 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
2619 static void r8153_u2p3en(struct r8152 *tp, bool enable)
2623 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
2625 ocp_data |= U2P3_ENABLE;
2627 ocp_data &= ~U2P3_ENABLE;
2628 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
2631 static void r8153_power_cut_en(struct r8152 *tp, bool enable)
2635 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
2637 ocp_data |= PWR_EN | PHASE2_EN;
2639 ocp_data &= ~(PWR_EN | PHASE2_EN);
2640 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2642 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2643 ocp_data &= ~PCUT_STATUS;
2644 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2647 static void r8153_first_init(struct r8152 *tp)
2652 rxdy_gated_en(tp, true);
2653 r8153_teredo_off(tp);
2655 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2656 ocp_data &= ~RCR_ACPT_ALL;
2657 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2659 r8153_hw_phy_cfg(tp);
2661 rtl8152_nic_reset(tp);
2663 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2664 ocp_data &= ~NOW_IS_OOB;
2665 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2667 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2668 ocp_data &= ~MCU_BORW_EN;
2669 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2671 for (i = 0; i < 1000; i++) {
2672 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2673 if (ocp_data & LINK_LIST_READY)
2675 usleep_range(1000, 2000);
2678 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2679 ocp_data |= RE_INIT_LL;
2680 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2682 for (i = 0; i < 1000; i++) {
2683 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2684 if (ocp_data & LINK_LIST_READY)
2686 usleep_range(1000, 2000);
2689 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
2691 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
2692 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
2694 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
2695 ocp_data |= TCR0_AUTO_FIFO;
2696 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
2698 rtl8152_nic_reset(tp);
2700 /* rx share fifo credit full threshold */
2701 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
2702 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
2703 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
2704 /* TX share fifo free credit full threshold */
2705 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
2707 /* rx aggregation */
2708 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
2709 ocp_data &= ~RX_AGG_DISABLE;
2710 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
2713 static void r8153_enter_oob(struct r8152 *tp)
2718 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2719 ocp_data &= ~NOW_IS_OOB;
2720 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2724 for (i = 0; i < 1000; i++) {
2725 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2726 if (ocp_data & LINK_LIST_READY)
2728 usleep_range(1000, 2000);
2731 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2732 ocp_data |= RE_INIT_LL;
2733 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2735 for (i = 0; i < 1000; i++) {
2736 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2737 if (ocp_data & LINK_LIST_READY)
2739 usleep_range(1000, 2000);
2742 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
2744 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2745 ocp_data &= ~TEREDO_WAKE_MASK;
2746 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2748 rtl_rx_vlan_en(tp, true);
2750 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
2751 ocp_data |= ALDPS_PROXY_MODE;
2752 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
2754 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2755 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
2756 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2758 rxdy_gated_en(tp, false);
2760 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2761 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
2762 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2765 static void r8153_disable_aldps(struct r8152 *tp)
2769 data = ocp_reg_read(tp, OCP_POWER_CFG);
2771 ocp_reg_write(tp, OCP_POWER_CFG, data);
2775 static void r8153_enable_aldps(struct r8152 *tp)
2779 data = ocp_reg_read(tp, OCP_POWER_CFG);
2781 ocp_reg_write(tp, OCP_POWER_CFG, data);
2784 static void rtl8153_disable(struct r8152 *tp)
2786 r8153_disable_aldps(tp);
2788 r8153_enable_aldps(tp);
2791 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
2793 u16 bmcr, anar, gbcr;
2796 cancel_delayed_work_sync(&tp->schedule);
2797 anar = r8152_mdio_read(tp, MII_ADVERTISE);
2798 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
2799 ADVERTISE_100HALF | ADVERTISE_100FULL);
2800 if (tp->mii.supports_gmii) {
2801 gbcr = r8152_mdio_read(tp, MII_CTRL1000);
2802 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
2807 if (autoneg == AUTONEG_DISABLE) {
2808 if (speed == SPEED_10) {
2810 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2811 } else if (speed == SPEED_100) {
2812 bmcr = BMCR_SPEED100;
2813 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2814 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
2815 bmcr = BMCR_SPEED1000;
2816 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
2822 if (duplex == DUPLEX_FULL)
2823 bmcr |= BMCR_FULLDPLX;
2825 if (speed == SPEED_10) {
2826 if (duplex == DUPLEX_FULL)
2827 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2829 anar |= ADVERTISE_10HALF;
2830 } else if (speed == SPEED_100) {
2831 if (duplex == DUPLEX_FULL) {
2832 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2833 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2835 anar |= ADVERTISE_10HALF;
2836 anar |= ADVERTISE_100HALF;
2838 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
2839 if (duplex == DUPLEX_FULL) {
2840 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2841 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2842 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
2844 anar |= ADVERTISE_10HALF;
2845 anar |= ADVERTISE_100HALF;
2846 gbcr |= ADVERTISE_1000HALF;
2853 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
2856 if (test_bit(PHY_RESET, &tp->flags))
2859 if (tp->mii.supports_gmii)
2860 r8152_mdio_write(tp, MII_CTRL1000, gbcr);
2862 r8152_mdio_write(tp, MII_ADVERTISE, anar);
2863 r8152_mdio_write(tp, MII_BMCR, bmcr);
2865 if (test_bit(PHY_RESET, &tp->flags)) {
2868 clear_bit(PHY_RESET, &tp->flags);
2869 for (i = 0; i < 50; i++) {
2871 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
2881 static void rtl8152_up(struct r8152 *tp)
2883 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2886 r8152b_disable_aldps(tp);
2887 r8152b_exit_oob(tp);
2888 r8152b_enable_aldps(tp);
2891 static void rtl8152_down(struct r8152 *tp)
2893 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2894 rtl_drop_queued_tx(tp);
2898 r8152_power_cut_en(tp, false);
2899 r8152b_disable_aldps(tp);
2900 r8152b_enter_oob(tp);
2901 r8152b_enable_aldps(tp);
2904 static void rtl8153_up(struct r8152 *tp)
2906 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2909 r8153_disable_aldps(tp);
2910 r8153_first_init(tp);
2911 r8153_enable_aldps(tp);
2914 static void rtl8153_down(struct r8152 *tp)
2916 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2917 rtl_drop_queued_tx(tp);
2921 r8153_u1u2en(tp, false);
2922 r8153_power_cut_en(tp, false);
2923 r8153_disable_aldps(tp);
2924 r8153_enter_oob(tp);
2925 r8153_enable_aldps(tp);
2928 static void set_carrier(struct r8152 *tp)
2930 struct net_device *netdev = tp->netdev;
2933 clear_bit(RTL8152_LINK_CHG, &tp->flags);
2934 speed = rtl8152_get_speed(tp);
2936 if (speed & LINK_STATUS) {
2937 if (!netif_carrier_ok(netdev)) {
2938 tp->rtl_ops.enable(tp);
2939 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
2940 netif_carrier_on(netdev);
2944 if (netif_carrier_ok(netdev)) {
2945 netif_carrier_off(netdev);
2946 napi_disable(&tp->napi);
2947 tp->rtl_ops.disable(tp);
2948 napi_enable(&tp->napi);
2953 static void rtl_work_func_t(struct work_struct *work)
2955 struct r8152 *tp = container_of(work, struct r8152, schedule.work);
2957 /* If the device is unplugged or !netif_running(), the workqueue
2958 * doesn't need to wake the device, and could return directly.
2960 if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev))
2963 if (usb_autopm_get_interface(tp->intf) < 0)
2966 if (!test_bit(WORK_ENABLE, &tp->flags))
2969 if (!mutex_trylock(&tp->control)) {
2970 schedule_delayed_work(&tp->schedule, 0);
2974 if (test_bit(RTL8152_LINK_CHG, &tp->flags))
2977 if (test_bit(RTL8152_SET_RX_MODE, &tp->flags))
2978 _rtl8152_set_rx_mode(tp->netdev);
2980 /* don't schedule napi before linking */
2981 if (test_bit(SCHEDULE_NAPI, &tp->flags) &&
2982 netif_carrier_ok(tp->netdev)) {
2983 clear_bit(SCHEDULE_NAPI, &tp->flags);
2984 napi_schedule(&tp->napi);
2987 if (test_bit(PHY_RESET, &tp->flags))
2990 mutex_unlock(&tp->control);
2993 usb_autopm_put_interface(tp->intf);
2996 static int rtl8152_open(struct net_device *netdev)
2998 struct r8152 *tp = netdev_priv(netdev);
3001 res = alloc_all_mem(tp);
3005 netif_carrier_off(netdev);
3007 res = usb_autopm_get_interface(tp->intf);
3013 mutex_lock(&tp->control);
3015 /* The WORK_ENABLE may be set when autoresume occurs */
3016 if (test_bit(WORK_ENABLE, &tp->flags)) {
3017 clear_bit(WORK_ENABLE, &tp->flags);
3018 usb_kill_urb(tp->intr_urb);
3019 cancel_delayed_work_sync(&tp->schedule);
3021 /* disable the tx/rx, if the workqueue has enabled them. */
3022 if (netif_carrier_ok(netdev))
3023 tp->rtl_ops.disable(tp);
3028 rtl8152_set_speed(tp, AUTONEG_ENABLE,
3029 tp->mii.supports_gmii ? SPEED_1000 : SPEED_100,
3031 netif_carrier_off(netdev);
3032 netif_start_queue(netdev);
3033 set_bit(WORK_ENABLE, &tp->flags);
3035 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
3038 netif_device_detach(tp->netdev);
3039 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
3043 napi_enable(&tp->napi);
3046 mutex_unlock(&tp->control);
3048 usb_autopm_put_interface(tp->intf);
3054 static int rtl8152_close(struct net_device *netdev)
3056 struct r8152 *tp = netdev_priv(netdev);
3059 napi_disable(&tp->napi);
3060 clear_bit(WORK_ENABLE, &tp->flags);
3061 usb_kill_urb(tp->intr_urb);
3062 cancel_delayed_work_sync(&tp->schedule);
3063 netif_stop_queue(netdev);
3065 res = usb_autopm_get_interface(tp->intf);
3066 if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) {
3067 rtl_drop_queued_tx(tp);
3070 mutex_lock(&tp->control);
3072 /* The autosuspend may have been enabled and wouldn't
3073 * be disable when autoresume occurs, because the
3074 * netif_running() would be false.
3076 rtl_runtime_suspend_enable(tp, false);
3078 tp->rtl_ops.down(tp);
3080 mutex_unlock(&tp->control);
3082 usb_autopm_put_interface(tp->intf);
3090 static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
3092 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
3093 ocp_reg_write(tp, OCP_EEE_DATA, reg);
3094 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
3097 static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
3101 r8152_mmd_indirect(tp, dev, reg);
3102 data = ocp_reg_read(tp, OCP_EEE_DATA);
3103 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
3108 static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
3110 r8152_mmd_indirect(tp, dev, reg);
3111 ocp_reg_write(tp, OCP_EEE_DATA, data);
3112 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
3115 static void r8152_eee_en(struct r8152 *tp, bool enable)
3117 u16 config1, config2, config3;
3120 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3121 config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
3122 config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
3123 config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
3126 ocp_data |= EEE_RX_EN | EEE_TX_EN;
3127 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
3128 config1 |= sd_rise_time(1);
3129 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
3130 config3 |= fast_snr(42);
3132 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
3133 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
3135 config1 |= sd_rise_time(7);
3136 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
3137 config3 |= fast_snr(511);
3140 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
3141 ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
3142 ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
3143 ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
3146 static void r8152b_enable_eee(struct r8152 *tp)
3148 r8152_eee_en(tp, true);
3149 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX);
3152 static void r8153_eee_en(struct r8152 *tp, bool enable)
3157 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3158 config = ocp_reg_read(tp, OCP_EEE_CFG);
3161 ocp_data |= EEE_RX_EN | EEE_TX_EN;
3164 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
3165 config &= ~EEE10_EN;
3168 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
3169 ocp_reg_write(tp, OCP_EEE_CFG, config);
3172 static void r8153_enable_eee(struct r8152 *tp)
3174 r8153_eee_en(tp, true);
3175 ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
3178 static void r8152b_enable_fc(struct r8152 *tp)
3182 anar = r8152_mdio_read(tp, MII_ADVERTISE);
3183 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3184 r8152_mdio_write(tp, MII_ADVERTISE, anar);
3187 static void rtl_tally_reset(struct r8152 *tp)
3191 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
3192 ocp_data |= TALLY_RESET;
3193 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
3196 static void r8152b_init(struct r8152 *tp)
3200 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3203 r8152b_disable_aldps(tp);
3205 if (tp->version == RTL_VER_01) {
3206 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
3207 ocp_data &= ~LED_MODE_MASK;
3208 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
3211 r8152_power_cut_en(tp, false);
3213 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
3214 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
3215 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
3216 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
3217 ocp_data &= ~MCU_CLK_RATIO_MASK;
3218 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
3219 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
3220 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
3221 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
3222 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
3224 r8152b_enable_eee(tp);
3225 r8152b_enable_aldps(tp);
3226 r8152b_enable_fc(tp);
3227 rtl_tally_reset(tp);
3229 /* enable rx aggregation */
3230 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
3231 ocp_data &= ~RX_AGG_DISABLE;
3232 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
3235 static void r8153_init(struct r8152 *tp)
3240 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3243 r8153_disable_aldps(tp);
3244 r8153_u1u2en(tp, false);
3246 for (i = 0; i < 500; i++) {
3247 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
3253 for (i = 0; i < 500; i++) {
3254 ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK;
3255 if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN)
3260 r8153_u2p3en(tp, false);
3262 if (tp->version == RTL_VER_04) {
3263 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
3264 ocp_data &= ~pwd_dn_scale_mask;
3265 ocp_data |= pwd_dn_scale(96);
3266 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
3268 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
3269 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
3270 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
3271 } else if (tp->version == RTL_VER_05) {
3272 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
3273 ocp_data &= ~ECM_ALDPS;
3274 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
3276 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
3277 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
3278 ocp_data &= ~DYNAMIC_BURST;
3280 ocp_data |= DYNAMIC_BURST;
3281 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
3284 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
3285 ocp_data |= EP4_FULL_FC;
3286 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
3288 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
3289 ocp_data &= ~TIMER11_EN;
3290 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
3292 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
3293 ocp_data &= ~LED_MODE_MASK;
3294 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
3296 ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
3297 if (tp->version == RTL_VER_04 && tp->udev->speed != USB_SPEED_SUPER)
3298 ocp_data |= LPM_TIMER_500MS;
3300 ocp_data |= LPM_TIMER_500US;
3301 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
3303 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
3304 ocp_data &= ~SEN_VAL_MASK;
3305 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
3306 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
3308 ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
3310 r8153_power_cut_en(tp, false);
3311 r8153_u1u2en(tp, true);
3313 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ALDPS_SPDWN_RATIO);
3314 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, EEE_SPDWN_RATIO);
3315 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3,
3316 PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN |
3317 U1U2_SPDWN_EN | L1_SPDWN_EN);
3318 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4,
3319 PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN |
3320 TP100_SPDWN_EN | TP500_SPDWN_EN | TP1000_SPDWN_EN |
3323 r8153_enable_eee(tp);
3324 r8153_enable_aldps(tp);
3325 r8152b_enable_fc(tp);
3326 rtl_tally_reset(tp);
3329 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
3331 struct r8152 *tp = usb_get_intfdata(intf);
3332 struct net_device *netdev = tp->netdev;
3335 mutex_lock(&tp->control);
3337 if (PMSG_IS_AUTO(message)) {
3338 if (netif_running(netdev) && work_busy(&tp->schedule.work)) {
3343 set_bit(SELECTIVE_SUSPEND, &tp->flags);
3345 netif_device_detach(netdev);
3348 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
3349 clear_bit(WORK_ENABLE, &tp->flags);
3350 usb_kill_urb(tp->intr_urb);
3351 napi_disable(&tp->napi);
3352 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3354 rtl_runtime_suspend_enable(tp, true);
3356 cancel_delayed_work_sync(&tp->schedule);
3357 tp->rtl_ops.down(tp);
3359 napi_enable(&tp->napi);
3362 mutex_unlock(&tp->control);
3367 static int rtl8152_resume(struct usb_interface *intf)
3369 struct r8152 *tp = usb_get_intfdata(intf);
3371 mutex_lock(&tp->control);
3373 if (!test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3374 tp->rtl_ops.init(tp);
3375 netif_device_attach(tp->netdev);
3378 if (netif_running(tp->netdev)) {
3379 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3380 rtl_runtime_suspend_enable(tp, false);
3381 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
3382 set_bit(WORK_ENABLE, &tp->flags);
3383 if (netif_carrier_ok(tp->netdev))
3387 rtl8152_set_speed(tp, AUTONEG_ENABLE,
3388 tp->mii.supports_gmii ?
3389 SPEED_1000 : SPEED_100,
3391 netif_carrier_off(tp->netdev);
3392 set_bit(WORK_ENABLE, &tp->flags);
3394 usb_submit_urb(tp->intr_urb, GFP_KERNEL);
3395 } else if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3396 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
3399 mutex_unlock(&tp->control);
3404 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3406 struct r8152 *tp = netdev_priv(dev);
3408 if (usb_autopm_get_interface(tp->intf) < 0)
3411 mutex_lock(&tp->control);
3413 wol->supported = WAKE_ANY;
3414 wol->wolopts = __rtl_get_wol(tp);
3416 mutex_unlock(&tp->control);
3418 usb_autopm_put_interface(tp->intf);
3421 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3423 struct r8152 *tp = netdev_priv(dev);
3426 ret = usb_autopm_get_interface(tp->intf);
3430 mutex_lock(&tp->control);
3432 __rtl_set_wol(tp, wol->wolopts);
3433 tp->saved_wolopts = wol->wolopts & WAKE_ANY;
3435 mutex_unlock(&tp->control);
3437 usb_autopm_put_interface(tp->intf);
3443 static u32 rtl8152_get_msglevel(struct net_device *dev)
3445 struct r8152 *tp = netdev_priv(dev);
3447 return tp->msg_enable;
3450 static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
3452 struct r8152 *tp = netdev_priv(dev);
3454 tp->msg_enable = value;
3457 static void rtl8152_get_drvinfo(struct net_device *netdev,
3458 struct ethtool_drvinfo *info)
3460 struct r8152 *tp = netdev_priv(netdev);
3462 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
3463 strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
3464 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
3468 int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
3470 struct r8152 *tp = netdev_priv(netdev);
3473 if (!tp->mii.mdio_read)
3476 ret = usb_autopm_get_interface(tp->intf);
3480 mutex_lock(&tp->control);
3482 ret = mii_ethtool_gset(&tp->mii, cmd);
3484 mutex_unlock(&tp->control);
3486 usb_autopm_put_interface(tp->intf);
3492 static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
3494 struct r8152 *tp = netdev_priv(dev);
3497 ret = usb_autopm_get_interface(tp->intf);
3501 mutex_lock(&tp->control);
3503 ret = rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex);
3505 mutex_unlock(&tp->control);
3507 usb_autopm_put_interface(tp->intf);
3513 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
3520 "tx_single_collisions",
3521 "tx_multi_collisions",
3529 static int rtl8152_get_sset_count(struct net_device *dev, int sset)
3533 return ARRAY_SIZE(rtl8152_gstrings);
3539 static void rtl8152_get_ethtool_stats(struct net_device *dev,
3540 struct ethtool_stats *stats, u64 *data)
3542 struct r8152 *tp = netdev_priv(dev);
3543 struct tally_counter tally;
3545 if (usb_autopm_get_interface(tp->intf) < 0)
3548 generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
3550 usb_autopm_put_interface(tp->intf);
3552 data[0] = le64_to_cpu(tally.tx_packets);
3553 data[1] = le64_to_cpu(tally.rx_packets);
3554 data[2] = le64_to_cpu(tally.tx_errors);
3555 data[3] = le32_to_cpu(tally.rx_errors);
3556 data[4] = le16_to_cpu(tally.rx_missed);
3557 data[5] = le16_to_cpu(tally.align_errors);
3558 data[6] = le32_to_cpu(tally.tx_one_collision);
3559 data[7] = le32_to_cpu(tally.tx_multi_collision);
3560 data[8] = le64_to_cpu(tally.rx_unicast);
3561 data[9] = le64_to_cpu(tally.rx_broadcast);
3562 data[10] = le32_to_cpu(tally.rx_multicast);
3563 data[11] = le16_to_cpu(tally.tx_aborted);
3564 data[12] = le16_to_cpu(tally.tx_underrun);
3567 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
3569 switch (stringset) {
3571 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings));
3576 static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
3578 u32 ocp_data, lp, adv, supported = 0;
3581 val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
3582 supported = mmd_eee_cap_to_ethtool_sup_t(val);
3584 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
3585 adv = mmd_eee_adv_to_ethtool_adv_t(val);
3587 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
3588 lp = mmd_eee_adv_to_ethtool_adv_t(val);
3590 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3591 ocp_data &= EEE_RX_EN | EEE_TX_EN;
3593 eee->eee_enabled = !!ocp_data;
3594 eee->eee_active = !!(supported & adv & lp);
3595 eee->supported = supported;
3596 eee->advertised = adv;
3597 eee->lp_advertised = lp;
3602 static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
3604 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
3606 r8152_eee_en(tp, eee->eee_enabled);
3608 if (!eee->eee_enabled)
3611 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
3616 static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
3618 u32 ocp_data, lp, adv, supported = 0;
3621 val = ocp_reg_read(tp, OCP_EEE_ABLE);
3622 supported = mmd_eee_cap_to_ethtool_sup_t(val);
3624 val = ocp_reg_read(tp, OCP_EEE_ADV);
3625 adv = mmd_eee_adv_to_ethtool_adv_t(val);
3627 val = ocp_reg_read(tp, OCP_EEE_LPABLE);
3628 lp = mmd_eee_adv_to_ethtool_adv_t(val);
3630 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3631 ocp_data &= EEE_RX_EN | EEE_TX_EN;
3633 eee->eee_enabled = !!ocp_data;
3634 eee->eee_active = !!(supported & adv & lp);
3635 eee->supported = supported;
3636 eee->advertised = adv;
3637 eee->lp_advertised = lp;
3642 static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
3644 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
3646 r8153_eee_en(tp, eee->eee_enabled);
3648 if (!eee->eee_enabled)
3651 ocp_reg_write(tp, OCP_EEE_ADV, val);
3657 rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
3659 struct r8152 *tp = netdev_priv(net);
3662 ret = usb_autopm_get_interface(tp->intf);
3666 mutex_lock(&tp->control);
3668 ret = tp->rtl_ops.eee_get(tp, edata);
3670 mutex_unlock(&tp->control);
3672 usb_autopm_put_interface(tp->intf);
3679 rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
3681 struct r8152 *tp = netdev_priv(net);
3684 ret = usb_autopm_get_interface(tp->intf);
3688 mutex_lock(&tp->control);
3690 ret = tp->rtl_ops.eee_set(tp, edata);
3692 ret = mii_nway_restart(&tp->mii);
3694 mutex_unlock(&tp->control);
3696 usb_autopm_put_interface(tp->intf);
3702 static int rtl8152_nway_reset(struct net_device *dev)
3704 struct r8152 *tp = netdev_priv(dev);
3707 ret = usb_autopm_get_interface(tp->intf);
3711 mutex_lock(&tp->control);
3713 ret = mii_nway_restart(&tp->mii);
3715 mutex_unlock(&tp->control);
3717 usb_autopm_put_interface(tp->intf);
3723 static struct ethtool_ops ops = {
3724 .get_drvinfo = rtl8152_get_drvinfo,
3725 .get_settings = rtl8152_get_settings,
3726 .set_settings = rtl8152_set_settings,
3727 .get_link = ethtool_op_get_link,
3728 .nway_reset = rtl8152_nway_reset,
3729 .get_msglevel = rtl8152_get_msglevel,
3730 .set_msglevel = rtl8152_set_msglevel,
3731 .get_wol = rtl8152_get_wol,
3732 .set_wol = rtl8152_set_wol,
3733 .get_strings = rtl8152_get_strings,
3734 .get_sset_count = rtl8152_get_sset_count,
3735 .get_ethtool_stats = rtl8152_get_ethtool_stats,
3736 .get_eee = rtl_ethtool_get_eee,
3737 .set_eee = rtl_ethtool_set_eee,
3740 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
3742 struct r8152 *tp = netdev_priv(netdev);
3743 struct mii_ioctl_data *data = if_mii(rq);
3746 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3749 res = usb_autopm_get_interface(tp->intf);
3755 data->phy_id = R8152_PHY_ID; /* Internal PHY */
3759 mutex_lock(&tp->control);
3760 data->val_out = r8152_mdio_read(tp, data->reg_num);
3761 mutex_unlock(&tp->control);
3765 if (!capable(CAP_NET_ADMIN)) {
3769 mutex_lock(&tp->control);
3770 r8152_mdio_write(tp, data->reg_num, data->val_in);
3771 mutex_unlock(&tp->control);
3778 usb_autopm_put_interface(tp->intf);
3784 static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
3786 struct r8152 *tp = netdev_priv(dev);
3788 switch (tp->version) {
3791 return eth_change_mtu(dev, new_mtu);
3796 if (new_mtu < 68 || new_mtu > RTL8153_MAX_MTU)
3804 static const struct net_device_ops rtl8152_netdev_ops = {
3805 .ndo_open = rtl8152_open,
3806 .ndo_stop = rtl8152_close,
3807 .ndo_do_ioctl = rtl8152_ioctl,
3808 .ndo_start_xmit = rtl8152_start_xmit,
3809 .ndo_tx_timeout = rtl8152_tx_timeout,
3810 .ndo_set_features = rtl8152_set_features,
3811 .ndo_set_rx_mode = rtl8152_set_rx_mode,
3812 .ndo_set_mac_address = rtl8152_set_mac_address,
3813 .ndo_change_mtu = rtl8152_change_mtu,
3814 .ndo_validate_addr = eth_validate_addr,
3815 .ndo_features_check = rtl8152_features_check,
3818 static void r8152b_get_version(struct r8152 *tp)
3823 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
3824 version = (u16)(ocp_data & VERSION_MASK);
3828 tp->version = RTL_VER_01;
3831 tp->version = RTL_VER_02;
3834 tp->version = RTL_VER_03;
3835 tp->mii.supports_gmii = 1;
3838 tp->version = RTL_VER_04;
3839 tp->mii.supports_gmii = 1;
3842 tp->version = RTL_VER_05;
3843 tp->mii.supports_gmii = 1;
3846 netif_info(tp, probe, tp->netdev,
3847 "Unknown version 0x%04x\n", version);
3852 static void rtl8152_unload(struct r8152 *tp)
3854 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3857 if (tp->version != RTL_VER_01)
3858 r8152_power_cut_en(tp, true);
3861 static void rtl8153_unload(struct r8152 *tp)
3863 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3866 r8153_power_cut_en(tp, false);
3869 static int rtl_ops_init(struct r8152 *tp)
3871 struct rtl_ops *ops = &tp->rtl_ops;
3874 switch (tp->version) {
3877 ops->init = r8152b_init;
3878 ops->enable = rtl8152_enable;
3879 ops->disable = rtl8152_disable;
3880 ops->up = rtl8152_up;
3881 ops->down = rtl8152_down;
3882 ops->unload = rtl8152_unload;
3883 ops->eee_get = r8152_get_eee;
3884 ops->eee_set = r8152_set_eee;
3890 ops->init = r8153_init;
3891 ops->enable = rtl8153_enable;
3892 ops->disable = rtl8153_disable;
3893 ops->up = rtl8153_up;
3894 ops->down = rtl8153_down;
3895 ops->unload = rtl8153_unload;
3896 ops->eee_get = r8153_get_eee;
3897 ops->eee_set = r8153_set_eee;
3902 netif_err(tp, probe, tp->netdev, "Unknown Device\n");
3909 static int rtl8152_probe(struct usb_interface *intf,
3910 const struct usb_device_id *id)
3912 struct usb_device *udev = interface_to_usbdev(intf);
3914 struct net_device *netdev;
3917 if (udev->actconfig->desc.bConfigurationValue != 1) {
3918 usb_driver_set_configuration(udev, 1);
3922 usb_reset_device(udev);
3923 netdev = alloc_etherdev(sizeof(struct r8152));
3925 dev_err(&intf->dev, "Out of memory\n");
3929 SET_NETDEV_DEV(netdev, &intf->dev);
3930 tp = netdev_priv(netdev);
3931 tp->msg_enable = 0x7FFF;
3934 tp->netdev = netdev;
3937 r8152b_get_version(tp);
3938 ret = rtl_ops_init(tp);
3942 mutex_init(&tp->control);
3943 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
3945 netdev->netdev_ops = &rtl8152_netdev_ops;
3946 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
3948 netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
3949 NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
3950 NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
3951 NETIF_F_HW_VLAN_CTAG_TX;
3952 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
3953 NETIF_F_TSO | NETIF_F_FRAGLIST |
3954 NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
3955 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;
3956 netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3957 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
3958 NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
3960 netdev->ethtool_ops = &ops;
3961 netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
3963 tp->mii.dev = netdev;
3964 tp->mii.mdio_read = read_mii_word;
3965 tp->mii.mdio_write = write_mii_word;
3966 tp->mii.phy_id_mask = 0x3f;
3967 tp->mii.reg_num_mask = 0x1f;
3968 tp->mii.phy_id = R8152_PHY_ID;
3970 intf->needs_remote_wakeup = 1;
3972 tp->rtl_ops.init(tp);
3973 set_ethernet_addr(tp);
3975 usb_set_intfdata(intf, tp);
3976 netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT);
3978 ret = register_netdev(netdev);
3980 netif_err(tp, probe, netdev, "couldn't register the device\n");
3984 tp->saved_wolopts = __rtl_get_wol(tp);
3985 if (tp->saved_wolopts)
3986 device_set_wakeup_enable(&udev->dev, true);
3988 device_set_wakeup_enable(&udev->dev, false);
3990 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
3995 netif_napi_del(&tp->napi);
3996 usb_set_intfdata(intf, NULL);
3998 free_netdev(netdev);
4002 static void rtl8152_disconnect(struct usb_interface *intf)
4004 struct r8152 *tp = usb_get_intfdata(intf);
4006 usb_set_intfdata(intf, NULL);
4008 struct usb_device *udev = tp->udev;
4010 if (udev->state == USB_STATE_NOTATTACHED)
4011 set_bit(RTL8152_UNPLUG, &tp->flags);
4013 netif_napi_del(&tp->napi);
4014 unregister_netdev(tp->netdev);
4015 tp->rtl_ops.unload(tp);
4016 free_netdev(tp->netdev);
4020 #define REALTEK_USB_DEVICE(vend, prod) \
4021 .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \
4022 USB_DEVICE_ID_MATCH_INT_CLASS, \
4023 .idVendor = (vend), \
4024 .idProduct = (prod), \
4025 .bInterfaceClass = USB_CLASS_VENDOR_SPEC \
4028 .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \
4029 USB_DEVICE_ID_MATCH_DEVICE, \
4030 .idVendor = (vend), \
4031 .idProduct = (prod), \
4032 .bInterfaceClass = USB_CLASS_COMM, \
4033 .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \
4034 .bInterfaceProtocol = USB_CDC_PROTO_NONE
4036 /* table of devices that work with this driver */
4037 static struct usb_device_id rtl8152_table[] = {
4038 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)},
4039 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)},
4040 {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)},
4041 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205)},
4045 MODULE_DEVICE_TABLE(usb, rtl8152_table);
4047 static struct usb_driver rtl8152_driver = {
4049 .id_table = rtl8152_table,
4050 .probe = rtl8152_probe,
4051 .disconnect = rtl8152_disconnect,
4052 .suspend = rtl8152_suspend,
4053 .resume = rtl8152_resume,
4054 .reset_resume = rtl8152_resume,
4055 .supports_autosuspend = 1,
4056 .disable_hub_initiated_lpm = 1,
4059 module_usb_driver(rtl8152_driver);
4061 MODULE_AUTHOR(DRIVER_AUTHOR);
4062 MODULE_DESCRIPTION(DRIVER_DESC);
4063 MODULE_LICENSE("GPL");