1 /* tulip_core.c: A DEC 21x4x-family ethernet driver for Linux.
3 Copyright 2000,2001 The Linux Kernel Team
4 Written/copyright 1994-2001 by Donald Becker.
6 This software may be used and distributed according to the terms
7 of the GNU General Public License, incorporated herein by reference.
9 Please refer to Documentation/DocBook/tulip-user.{pdf,ps,html}
10 for more information on this driver.
12 Please submit bugs to http://bugzilla.kernel.org/ .
16 #define DRV_NAME "tulip"
17 #ifdef CONFIG_TULIP_NAPI
18 #define DRV_VERSION "1.1.15-NAPI" /* Keep at least for test */
20 #define DRV_VERSION "1.1.15"
22 #define DRV_RELDATE "Feb 27, 2007"
25 #include <linux/module.h>
26 #include <linux/pci.h>
28 #include <linux/init.h>
29 #include <linux/etherdevice.h>
30 #include <linux/delay.h>
31 #include <linux/mii.h>
32 #include <linux/ethtool.h>
33 #include <linux/crc32.h>
34 #include <asm/unaligned.h>
35 #include <asm/uaccess.h>
41 static char version[] __devinitdata =
42 "Linux Tulip driver version " DRV_VERSION " (" DRV_RELDATE ")\n";
45 /* A few user-configurable values. */
47 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
48 static unsigned int max_interrupt_work = 25;
51 /* Used to pass the full-duplex flag, etc. */
52 static int full_duplex[MAX_UNITS];
53 static int options[MAX_UNITS];
54 static int mtu[MAX_UNITS]; /* Jumbo MTU for interfaces. */
56 /* The possible media types that can be set in options[] are: */
57 const char * const medianame[32] = {
58 "10baseT", "10base2", "AUI", "100baseTx",
59 "10baseT-FDX", "100baseTx-FDX", "100baseT4", "100baseFx",
60 "100baseFx-FDX", "MII 10baseT", "MII 10baseT-FDX", "MII",
61 "10baseT(forced)", "MII 100baseTx", "MII 100baseTx-FDX", "MII 100baseT4",
62 "MII 100baseFx-HDX", "MII 100baseFx-FDX", "Home-PNA 1Mbps", "Invalid-19",
63 "","","","", "","","","", "","","","Transceiver reset",
66 /* Set the copy breakpoint for the copy-only-tiny-buffer Rx structure. */
67 #if defined(__alpha__) || defined(__arm__) || defined(__hppa__) \
68 || defined(CONFIG_SPARC) || defined(__ia64__) \
69 || defined(__sh__) || defined(__mips__)
70 static int rx_copybreak = 1518;
72 static int rx_copybreak = 100;
76 Set the bus performance register.
77 Typical: Set 16 longword cache alignment, no burst limit.
78 Cache alignment bits 15:14 Burst length 13:8
79 0000 No alignment 0x00000000 unlimited 0800 8 longwords
80 4000 8 longwords 0100 1 longword 1000 16 longwords
81 8000 16 longwords 0200 2 longwords 2000 32 longwords
82 C000 32 longwords 0400 4 longwords
83 Warning: many older 486 systems are broken and require setting 0x00A04800
84 8 longword cache alignment, 8 longword burst.
85 ToDo: Non-Intel setting could be better.
88 #if defined(__alpha__) || defined(__ia64__)
89 static int csr0 = 0x01A00000 | 0xE000;
90 #elif defined(__i386__) || defined(__powerpc__) || defined(__x86_64__)
91 static int csr0 = 0x01A00000 | 0x8000;
92 #elif defined(CONFIG_SPARC) || defined(__hppa__)
93 /* The UltraSparc PCI controllers will disconnect at every 64-byte
94 * crossing anyways so it makes no sense to tell Tulip to burst
97 static int csr0 = 0x01A00000 | 0x9000;
98 #elif defined(__arm__) || defined(__sh__)
99 static int csr0 = 0x01A00000 | 0x4800;
100 #elif defined(__mips__)
101 static int csr0 = 0x00200000 | 0x4000;
103 #warning Processor architecture undefined!
104 static int csr0 = 0x00A00000 | 0x4800;
107 /* Operational parameters that usually are not changed. */
108 /* Time in jiffies before concluding the transmitter is hung. */
109 #define TX_TIMEOUT (4*HZ)
112 MODULE_AUTHOR("The Linux Kernel Team");
113 MODULE_DESCRIPTION("Digital 21*4* Tulip ethernet driver");
114 MODULE_LICENSE("GPL");
115 MODULE_VERSION(DRV_VERSION);
116 module_param(tulip_debug, int, 0);
117 module_param(max_interrupt_work, int, 0);
118 module_param(rx_copybreak, int, 0);
119 module_param(csr0, int, 0);
120 module_param_array(options, int, NULL, 0);
121 module_param_array(full_duplex, int, NULL, 0);
123 #define PFX DRV_NAME ": "
126 int tulip_debug = TULIP_DEBUG;
131 static void tulip_timer(unsigned long data)
133 struct net_device *dev = (struct net_device *)data;
134 struct tulip_private *tp = netdev_priv(dev);
136 if (netif_running(dev))
137 schedule_work(&tp->media_work);
141 * This table use during operation for capabilities and media timer.
143 * It is indexed via the values in 'enum chips'
146 struct tulip_chip_table tulip_tbl[] = {
147 { }, /* placeholder for array, slot unused currently */
148 { }, /* placeholder for array, slot unused currently */
151 { "Digital DS21140 Tulip", 128, 0x0001ebef,
152 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | HAS_PCI_MWI, tulip_timer,
155 /* DC21142, DC21143 */
156 { "Digital DS21142/43 Tulip", 128, 0x0801fbff,
157 HAS_MII | HAS_MEDIA_TABLE | ALWAYS_CHECK_MII | HAS_ACPI | HAS_NWAY
158 | HAS_INTR_MITIGATION | HAS_PCI_MWI, tulip_timer, t21142_media_task },
161 { "Lite-On 82c168 PNIC", 256, 0x0001fbef,
162 HAS_MII | HAS_PNICNWAY, pnic_timer, },
165 { "Macronix 98713 PMAC", 128, 0x0001ebef,
166 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM, mxic_timer, },
169 { "Macronix 98715 PMAC", 256, 0x0001ebef,
170 HAS_MEDIA_TABLE, mxic_timer, },
173 { "Macronix 98725 PMAC", 256, 0x0001ebef,
174 HAS_MEDIA_TABLE, mxic_timer, },
177 { "ASIX AX88140", 128, 0x0001fbff,
178 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | MC_HASH_ONLY
179 | IS_ASIX, tulip_timer, tulip_media_task },
182 { "Lite-On PNIC-II", 256, 0x0801fbff,
183 HAS_MII | HAS_NWAY | HAS_8023X | HAS_PCI_MWI, pnic2_timer, },
186 { "ADMtek Comet", 256, 0x0001abef,
187 HAS_MII | MC_HASH_ONLY | COMET_MAC_ADDR, comet_timer, },
190 { "Compex 9881 PMAC", 128, 0x0001ebef,
191 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM, mxic_timer, },
194 { "Intel DS21145 Tulip", 128, 0x0801fbff,
195 HAS_MII | HAS_MEDIA_TABLE | ALWAYS_CHECK_MII | HAS_ACPI
196 | HAS_NWAY | HAS_PCI_MWI, tulip_timer, tulip_media_task },
199 #ifdef CONFIG_TULIP_DM910X
200 { "Davicom DM9102/DM9102A", 128, 0x0001ebef,
201 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | HAS_ACPI,
202 tulip_timer, tulip_media_task },
208 { "Conexant LANfinity", 256, 0x0001ebef,
209 HAS_MII | HAS_ACPI, tulip_timer, tulip_media_task },
214 static struct pci_device_id tulip_pci_tbl[] = {
215 { 0x1011, 0x0009, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DC21140 },
216 { 0x1011, 0x0019, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DC21143 },
217 { 0x11AD, 0x0002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, LC82C168 },
218 { 0x10d9, 0x0512, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98713 },
219 { 0x10d9, 0x0531, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98715 },
220 /* { 0x10d9, 0x0531, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98725 },*/
221 { 0x125B, 0x1400, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AX88140 },
222 { 0x11AD, 0xc115, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PNIC2 },
223 { 0x1317, 0x0981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
224 { 0x1317, 0x0985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
225 { 0x1317, 0x1985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
226 { 0x1317, 0x9511, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
227 { 0x13D1, 0xAB02, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
228 { 0x13D1, 0xAB03, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
229 { 0x13D1, 0xAB08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
230 { 0x104A, 0x0981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
231 { 0x104A, 0x2774, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
232 { 0x1259, 0xa120, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
233 { 0x11F6, 0x9881, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMPEX9881 },
234 { 0x8086, 0x0039, PCI_ANY_ID, PCI_ANY_ID, 0, 0, I21145 },
235 #ifdef CONFIG_TULIP_DM910X
236 { 0x1282, 0x9100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DM910X },
237 { 0x1282, 0x9102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DM910X },
239 { 0x1113, 0x1216, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
240 { 0x1113, 0x1217, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98715 },
241 { 0x1113, 0x9511, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
242 { 0x1186, 0x1541, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
243 { 0x1186, 0x1561, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
244 { 0x1186, 0x1591, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
245 { 0x14f1, 0x1803, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CONEXANT },
246 { 0x1626, 0x8410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
247 { 0x1737, 0xAB09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
248 { 0x1737, 0xAB08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
249 { 0x17B3, 0xAB08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
250 { 0x10b7, 0x9300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, /* 3Com 3CSOHO100B-TX */
251 { 0x14ea, 0xab08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, /* Planex FNW-3602-TX */
252 { 0x1414, 0x0002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
253 { } /* terminate list */
255 MODULE_DEVICE_TABLE(pci, tulip_pci_tbl);
258 /* A full-duplex map for media types. */
259 const char tulip_media_cap[32] =
260 {0,0,0,16, 3,19,16,24, 27,4,7,5, 0,20,23,20, 28,31,0,0, };
262 static void tulip_tx_timeout(struct net_device *dev);
263 static void tulip_init_ring(struct net_device *dev);
264 static void tulip_free_ring(struct net_device *dev);
265 static netdev_tx_t tulip_start_xmit(struct sk_buff *skb,
266 struct net_device *dev);
267 static int tulip_open(struct net_device *dev);
268 static int tulip_close(struct net_device *dev);
269 static void tulip_up(struct net_device *dev);
270 static void tulip_down(struct net_device *dev);
271 static struct net_device_stats *tulip_get_stats(struct net_device *dev);
272 static int private_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
273 static void set_rx_mode(struct net_device *dev);
274 #ifdef CONFIG_NET_POLL_CONTROLLER
275 static void poll_tulip(struct net_device *dev);
278 static void tulip_set_power_state (struct tulip_private *tp,
279 int sleep, int snooze)
281 if (tp->flags & HAS_ACPI) {
283 pci_read_config_dword (tp->pdev, CFDD, &tmp);
284 newtmp = tmp & ~(CFDD_Sleep | CFDD_Snooze);
286 newtmp |= CFDD_Sleep;
288 newtmp |= CFDD_Snooze;
290 pci_write_config_dword (tp->pdev, CFDD, newtmp);
296 static void tulip_up(struct net_device *dev)
298 struct tulip_private *tp = netdev_priv(dev);
299 void __iomem *ioaddr = tp->base_addr;
300 int next_tick = 3*HZ;
304 #ifdef CONFIG_TULIP_NAPI
305 napi_enable(&tp->napi);
308 /* Wake the chip from sleep/snooze mode. */
309 tulip_set_power_state (tp, 0, 0);
311 /* On some chip revs we must set the MII/SYM port before the reset!? */
312 if (tp->mii_cnt || (tp->mtable && tp->mtable->has_mii))
313 iowrite32(0x00040000, ioaddr + CSR6);
315 /* Reset the chip, holding bit 0 set at least 50 PCI cycles. */
316 iowrite32(0x00000001, ioaddr + CSR0);
317 pci_read_config_dword(tp->pdev, PCI_COMMAND, ®); /* flush write */
321 Wait the specified 50 PCI cycles after a reset by initializing
322 Tx and Rx queues and the address filter list. */
323 iowrite32(tp->csr0, ioaddr + CSR0);
324 pci_read_config_dword(tp->pdev, PCI_COMMAND, ®); /* flush write */
328 printk(KERN_DEBUG "%s: tulip_up(), irq==%d.\n", dev->name, dev->irq);
330 iowrite32(tp->rx_ring_dma, ioaddr + CSR3);
331 iowrite32(tp->tx_ring_dma, ioaddr + CSR4);
332 tp->cur_rx = tp->cur_tx = 0;
333 tp->dirty_rx = tp->dirty_tx = 0;
335 if (tp->flags & MC_HASH_ONLY) {
336 u32 addr_low = get_unaligned_le32(dev->dev_addr);
337 u32 addr_high = get_unaligned_le16(dev->dev_addr + 4);
338 if (tp->chip_id == AX88140) {
339 iowrite32(0, ioaddr + CSR13);
340 iowrite32(addr_low, ioaddr + CSR14);
341 iowrite32(1, ioaddr + CSR13);
342 iowrite32(addr_high, ioaddr + CSR14);
343 } else if (tp->flags & COMET_MAC_ADDR) {
344 iowrite32(addr_low, ioaddr + 0xA4);
345 iowrite32(addr_high, ioaddr + 0xA8);
346 iowrite32(0, ioaddr + 0xAC);
347 iowrite32(0, ioaddr + 0xB0);
350 /* This is set_rx_mode(), but without starting the transmitter. */
351 u16 *eaddrs = (u16 *)dev->dev_addr;
352 u16 *setup_frm = &tp->setup_frame[15*6];
355 /* 21140 bug: you must add the broadcast address. */
356 memset(tp->setup_frame, 0xff, sizeof(tp->setup_frame));
357 /* Fill the final entry of the table with our physical address. */
358 *setup_frm++ = eaddrs[0]; *setup_frm++ = eaddrs[0];
359 *setup_frm++ = eaddrs[1]; *setup_frm++ = eaddrs[1];
360 *setup_frm++ = eaddrs[2]; *setup_frm++ = eaddrs[2];
362 mapping = pci_map_single(tp->pdev, tp->setup_frame,
363 sizeof(tp->setup_frame),
365 tp->tx_buffers[tp->cur_tx].skb = NULL;
366 tp->tx_buffers[tp->cur_tx].mapping = mapping;
368 /* Put the setup frame on the Tx list. */
369 tp->tx_ring[tp->cur_tx].length = cpu_to_le32(0x08000000 | 192);
370 tp->tx_ring[tp->cur_tx].buffer1 = cpu_to_le32(mapping);
371 tp->tx_ring[tp->cur_tx].status = cpu_to_le32(DescOwned);
376 tp->saved_if_port = dev->if_port;
377 if (dev->if_port == 0)
378 dev->if_port = tp->default_port;
380 /* Allow selecting a default media. */
382 if (tp->mtable == NULL)
385 int looking_for = tulip_media_cap[dev->if_port] & MediaIsMII ? 11 :
386 (dev->if_port == 12 ? 0 : dev->if_port);
387 for (i = 0; i < tp->mtable->leafcount; i++)
388 if (tp->mtable->mleaf[i].media == looking_for) {
389 printk(KERN_INFO "%s: Using user-specified media %s.\n",
390 dev->name, medianame[dev->if_port]);
394 if ((tp->mtable->defaultmedia & 0x0800) == 0) {
395 int looking_for = tp->mtable->defaultmedia & MEDIA_MASK;
396 for (i = 0; i < tp->mtable->leafcount; i++)
397 if (tp->mtable->mleaf[i].media == looking_for) {
398 printk(KERN_INFO "%s: Using EEPROM-set media %s.\n",
399 dev->name, medianame[looking_for]);
403 /* Start sensing first non-full-duplex media. */
404 for (i = tp->mtable->leafcount - 1;
405 (tulip_media_cap[tp->mtable->mleaf[i].media] & MediaAlwaysFD) && i > 0; i--)
414 if (tp->chip_id == DC21143 &&
415 (tulip_media_cap[dev->if_port] & MediaIsMII)) {
416 /* We must reset the media CSRs when we force-select MII mode. */
417 iowrite32(0x0000, ioaddr + CSR13);
418 iowrite32(0x0000, ioaddr + CSR14);
419 iowrite32(0x0008, ioaddr + CSR15);
421 tulip_select_media(dev, 1);
422 } else if (tp->chip_id == DC21142) {
424 tulip_select_media(dev, 1);
426 printk(KERN_INFO "%s: Using MII transceiver %d, status "
428 dev->name, tp->phys[0], tulip_mdio_read(dev, tp->phys[0], 1));
429 iowrite32(csr6_mask_defstate, ioaddr + CSR6);
430 tp->csr6 = csr6_mask_hdcap;
432 iowrite32(0x0000, ioaddr + CSR13);
433 iowrite32(0x0000, ioaddr + CSR14);
435 t21142_start_nway(dev);
436 } else if (tp->chip_id == PNIC2) {
437 /* for initial startup advertise 10/100 Full and Half */
438 tp->sym_advertise = 0x01E0;
439 /* enable autonegotiate end interrupt */
440 iowrite32(ioread32(ioaddr+CSR5)| 0x00008010, ioaddr + CSR5);
441 iowrite32(ioread32(ioaddr+CSR7)| 0x00008010, ioaddr + CSR7);
442 pnic2_start_nway(dev);
443 } else if (tp->chip_id == LC82C168 && ! tp->medialock) {
446 tp->csr6 = 0x814C0000 | (tp->full_duplex ? 0x0200 : 0);
447 iowrite32(0x0001, ioaddr + CSR15);
448 } else if (ioread32(ioaddr + CSR5) & TPLnkPass)
451 /* Start with 10mbps to do autonegotiation. */
452 iowrite32(0x32, ioaddr + CSR12);
453 tp->csr6 = 0x00420000;
454 iowrite32(0x0001B078, ioaddr + 0xB8);
455 iowrite32(0x0201B078, ioaddr + 0xB8);
458 } else if ((tp->chip_id == MX98713 || tp->chip_id == COMPEX9881)
459 && ! tp->medialock) {
461 tp->csr6 = 0x01880000 | (tp->full_duplex ? 0x0200 : 0);
462 iowrite32(0x0f370000 | ioread16(ioaddr + 0x80), ioaddr + 0x80);
463 } else if (tp->chip_id == MX98715 || tp->chip_id == MX98725) {
464 /* Provided by BOLO, Macronix - 12/10/1998. */
466 tp->csr6 = 0x01a80200;
467 iowrite32(0x0f370000 | ioread16(ioaddr + 0x80), ioaddr + 0x80);
468 iowrite32(0x11000 | ioread16(ioaddr + 0xa0), ioaddr + 0xa0);
469 } else if (tp->chip_id == COMET || tp->chip_id == CONEXANT) {
470 /* Enable automatic Tx underrun recovery. */
471 iowrite32(ioread32(ioaddr + 0x88) | 1, ioaddr + 0x88);
472 dev->if_port = tp->mii_cnt ? 11 : 0;
473 tp->csr6 = 0x00040000;
474 } else if (tp->chip_id == AX88140) {
475 tp->csr6 = tp->mii_cnt ? 0x00040100 : 0x00000100;
477 tulip_select_media(dev, 1);
479 /* Start the chip's Tx to process setup frame. */
483 iowrite32(tp->csr6 | TxOn, ioaddr + CSR6);
485 /* Enable interrupts by setting the interrupt mask. */
486 iowrite32(tulip_tbl[tp->chip_id].valid_intrs, ioaddr + CSR5);
487 iowrite32(tulip_tbl[tp->chip_id].valid_intrs, ioaddr + CSR7);
488 tulip_start_rxtx(tp);
489 iowrite32(0, ioaddr + CSR2); /* Rx poll demand */
491 if (tulip_debug > 2) {
492 printk(KERN_DEBUG "%s: Done tulip_up(), CSR0 %8.8x, CSR5 %8.8x CSR6 %8.8x.\n",
493 dev->name, ioread32(ioaddr + CSR0), ioread32(ioaddr + CSR5),
494 ioread32(ioaddr + CSR6));
497 /* Set the timer to switch to check for link beat and perhaps switch
498 to an alternate media type. */
499 tp->timer.expires = RUN_AT(next_tick);
500 add_timer(&tp->timer);
501 #ifdef CONFIG_TULIP_NAPI
502 init_timer(&tp->oom_timer);
503 tp->oom_timer.data = (unsigned long)dev;
504 tp->oom_timer.function = oom_timer;
509 tulip_open(struct net_device *dev)
513 tulip_init_ring (dev);
515 retval = request_irq(dev->irq, &tulip_interrupt, IRQF_SHARED, dev->name, dev);
521 netif_start_queue (dev);
526 tulip_free_ring (dev);
531 static void tulip_tx_timeout(struct net_device *dev)
533 struct tulip_private *tp = netdev_priv(dev);
534 void __iomem *ioaddr = tp->base_addr;
537 spin_lock_irqsave (&tp->lock, flags);
539 if (tulip_media_cap[dev->if_port] & MediaIsMII) {
540 /* Do nothing -- the media monitor should handle this. */
542 printk(KERN_WARNING "%s: Transmit timeout using MII device.\n",
544 } else if (tp->chip_id == DC21140 || tp->chip_id == DC21142
545 || tp->chip_id == MX98713 || tp->chip_id == COMPEX9881
546 || tp->chip_id == DM910X) {
547 printk(KERN_WARNING "%s: 21140 transmit timed out, status %8.8x, "
548 "SIA %8.8x %8.8x %8.8x %8.8x, resetting...\n",
549 dev->name, ioread32(ioaddr + CSR5), ioread32(ioaddr + CSR12),
550 ioread32(ioaddr + CSR13), ioread32(ioaddr + CSR14), ioread32(ioaddr + CSR15));
551 tp->timeout_recovery = 1;
552 schedule_work(&tp->media_work);
554 } else if (tp->chip_id == PNIC2) {
555 printk(KERN_WARNING "%s: PNIC2 transmit timed out, status %8.8x, "
556 "CSR6/7 %8.8x / %8.8x CSR12 %8.8x, resetting...\n",
557 dev->name, (int)ioread32(ioaddr + CSR5), (int)ioread32(ioaddr + CSR6),
558 (int)ioread32(ioaddr + CSR7), (int)ioread32(ioaddr + CSR12));
560 printk(KERN_WARNING "%s: Transmit timed out, status %8.8x, CSR12 "
561 "%8.8x, resetting...\n",
562 dev->name, ioread32(ioaddr + CSR5), ioread32(ioaddr + CSR12));
566 #if defined(way_too_many_messages)
567 if (tulip_debug > 3) {
569 for (i = 0; i < RX_RING_SIZE; i++) {
570 u8 *buf = (u8 *)(tp->rx_ring[i].buffer1);
572 printk(KERN_DEBUG "%2d: %8.8x %8.8x %8.8x %8.8x "
573 "%2.2x %2.2x %2.2x.\n",
574 i, (unsigned int)tp->rx_ring[i].status,
575 (unsigned int)tp->rx_ring[i].length,
576 (unsigned int)tp->rx_ring[i].buffer1,
577 (unsigned int)tp->rx_ring[i].buffer2,
578 buf[0], buf[1], buf[2]);
579 for (j = 0; buf[j] != 0xee && j < 1600; j++)
581 printk(KERN_CONT " %2.2x", buf[j]);
582 printk(KERN_CONT " j=%d.\n", j);
584 printk(KERN_DEBUG " Rx ring %8.8x: ", (int)tp->rx_ring);
585 for (i = 0; i < RX_RING_SIZE; i++)
586 printk(KERN_CONT " %8.8x",
587 (unsigned int)tp->rx_ring[i].status);
588 printk(KERN_DEBUG " Tx ring %8.8x: ", (int)tp->tx_ring);
589 for (i = 0; i < TX_RING_SIZE; i++)
590 printk(KERN_CONT " %8.8x", (unsigned int)tp->tx_ring[i].status);
591 printk(KERN_CONT "\n");
595 tulip_tx_timeout_complete(tp, ioaddr);
598 spin_unlock_irqrestore (&tp->lock, flags);
599 dev->trans_start = jiffies;
600 netif_wake_queue (dev);
604 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
605 static void tulip_init_ring(struct net_device *dev)
607 struct tulip_private *tp = netdev_priv(dev);
614 for (i = 0; i < RX_RING_SIZE; i++) {
615 tp->rx_ring[i].status = 0x00000000;
616 tp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ);
617 tp->rx_ring[i].buffer2 = cpu_to_le32(tp->rx_ring_dma + sizeof(struct tulip_rx_desc) * (i + 1));
618 tp->rx_buffers[i].skb = NULL;
619 tp->rx_buffers[i].mapping = 0;
621 /* Mark the last entry as wrapping the ring. */
622 tp->rx_ring[i-1].length = cpu_to_le32(PKT_BUF_SZ | DESC_RING_WRAP);
623 tp->rx_ring[i-1].buffer2 = cpu_to_le32(tp->rx_ring_dma);
625 for (i = 0; i < RX_RING_SIZE; i++) {
628 /* Note the receive buffer must be longword aligned.
629 dev_alloc_skb() provides 16 byte alignment. But do *not*
630 use skb_reserve() to align the IP header! */
631 struct sk_buff *skb = dev_alloc_skb(PKT_BUF_SZ);
632 tp->rx_buffers[i].skb = skb;
635 mapping = pci_map_single(tp->pdev, skb->data,
636 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
637 tp->rx_buffers[i].mapping = mapping;
638 skb->dev = dev; /* Mark as being used by this device. */
639 tp->rx_ring[i].status = cpu_to_le32(DescOwned); /* Owned by Tulip chip */
640 tp->rx_ring[i].buffer1 = cpu_to_le32(mapping);
642 tp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
644 /* The Tx buffer descriptor is filled in as needed, but we
645 do need to clear the ownership bit. */
646 for (i = 0; i < TX_RING_SIZE; i++) {
647 tp->tx_buffers[i].skb = NULL;
648 tp->tx_buffers[i].mapping = 0;
649 tp->tx_ring[i].status = 0x00000000;
650 tp->tx_ring[i].buffer2 = cpu_to_le32(tp->tx_ring_dma + sizeof(struct tulip_tx_desc) * (i + 1));
652 tp->tx_ring[i-1].buffer2 = cpu_to_le32(tp->tx_ring_dma);
656 tulip_start_xmit(struct sk_buff *skb, struct net_device *dev)
658 struct tulip_private *tp = netdev_priv(dev);
664 spin_lock_irqsave(&tp->lock, flags);
666 /* Calculate the next Tx descriptor entry. */
667 entry = tp->cur_tx % TX_RING_SIZE;
669 tp->tx_buffers[entry].skb = skb;
670 mapping = pci_map_single(tp->pdev, skb->data,
671 skb->len, PCI_DMA_TODEVICE);
672 tp->tx_buffers[entry].mapping = mapping;
673 tp->tx_ring[entry].buffer1 = cpu_to_le32(mapping);
675 if (tp->cur_tx - tp->dirty_tx < TX_RING_SIZE/2) {/* Typical path */
676 flag = 0x60000000; /* No interrupt */
677 } else if (tp->cur_tx - tp->dirty_tx == TX_RING_SIZE/2) {
678 flag = 0xe0000000; /* Tx-done intr. */
679 } else if (tp->cur_tx - tp->dirty_tx < TX_RING_SIZE - 2) {
680 flag = 0x60000000; /* No Tx-done intr. */
681 } else { /* Leave room for set_rx_mode() to fill entries. */
682 flag = 0xe0000000; /* Tx-done intr. */
683 netif_stop_queue(dev);
685 if (entry == TX_RING_SIZE-1)
686 flag = 0xe0000000 | DESC_RING_WRAP;
688 tp->tx_ring[entry].length = cpu_to_le32(skb->len | flag);
689 /* if we were using Transmit Automatic Polling, we would need a
691 tp->tx_ring[entry].status = cpu_to_le32(DescOwned);
696 /* Trigger an immediate transmit demand. */
697 iowrite32(0, tp->base_addr + CSR1);
699 spin_unlock_irqrestore(&tp->lock, flags);
701 dev->trans_start = jiffies;
706 static void tulip_clean_tx_ring(struct tulip_private *tp)
708 unsigned int dirty_tx;
710 for (dirty_tx = tp->dirty_tx ; tp->cur_tx - dirty_tx > 0;
712 int entry = dirty_tx % TX_RING_SIZE;
713 int status = le32_to_cpu(tp->tx_ring[entry].status);
716 tp->stats.tx_errors++; /* It wasn't Txed */
717 tp->tx_ring[entry].status = 0;
720 /* Check for Tx filter setup frames. */
721 if (tp->tx_buffers[entry].skb == NULL) {
722 /* test because dummy frames not mapped */
723 if (tp->tx_buffers[entry].mapping)
724 pci_unmap_single(tp->pdev,
725 tp->tx_buffers[entry].mapping,
726 sizeof(tp->setup_frame),
731 pci_unmap_single(tp->pdev, tp->tx_buffers[entry].mapping,
732 tp->tx_buffers[entry].skb->len,
735 /* Free the original skb. */
736 dev_kfree_skb_irq(tp->tx_buffers[entry].skb);
737 tp->tx_buffers[entry].skb = NULL;
738 tp->tx_buffers[entry].mapping = 0;
742 static void tulip_down (struct net_device *dev)
744 struct tulip_private *tp = netdev_priv(dev);
745 void __iomem *ioaddr = tp->base_addr;
748 cancel_work_sync(&tp->media_work);
750 #ifdef CONFIG_TULIP_NAPI
751 napi_disable(&tp->napi);
754 del_timer_sync (&tp->timer);
755 #ifdef CONFIG_TULIP_NAPI
756 del_timer_sync (&tp->oom_timer);
758 spin_lock_irqsave (&tp->lock, flags);
760 /* Disable interrupts by clearing the interrupt mask. */
761 iowrite32 (0x00000000, ioaddr + CSR7);
763 /* Stop the Tx and Rx processes. */
766 /* prepare receive buffers */
767 tulip_refill_rx(dev);
769 /* release any unconsumed transmit buffers */
770 tulip_clean_tx_ring(tp);
772 if (ioread32 (ioaddr + CSR6) != 0xffffffff)
773 tp->stats.rx_missed_errors += ioread32 (ioaddr + CSR8) & 0xffff;
775 spin_unlock_irqrestore (&tp->lock, flags);
777 init_timer(&tp->timer);
778 tp->timer.data = (unsigned long)dev;
779 tp->timer.function = tulip_tbl[tp->chip_id].media_timer;
781 dev->if_port = tp->saved_if_port;
783 /* Leave the driver in snooze, not sleep, mode. */
784 tulip_set_power_state (tp, 0, 1);
787 static void tulip_free_ring (struct net_device *dev)
789 struct tulip_private *tp = netdev_priv(dev);
792 /* Free all the skbuffs in the Rx queue. */
793 for (i = 0; i < RX_RING_SIZE; i++) {
794 struct sk_buff *skb = tp->rx_buffers[i].skb;
795 dma_addr_t mapping = tp->rx_buffers[i].mapping;
797 tp->rx_buffers[i].skb = NULL;
798 tp->rx_buffers[i].mapping = 0;
800 tp->rx_ring[i].status = 0; /* Not owned by Tulip chip. */
801 tp->rx_ring[i].length = 0;
802 /* An invalid address. */
803 tp->rx_ring[i].buffer1 = cpu_to_le32(0xBADF00D0);
805 pci_unmap_single(tp->pdev, mapping, PKT_BUF_SZ,
811 for (i = 0; i < TX_RING_SIZE; i++) {
812 struct sk_buff *skb = tp->tx_buffers[i].skb;
815 pci_unmap_single(tp->pdev, tp->tx_buffers[i].mapping,
816 skb->len, PCI_DMA_TODEVICE);
819 tp->tx_buffers[i].skb = NULL;
820 tp->tx_buffers[i].mapping = 0;
824 static int tulip_close (struct net_device *dev)
826 struct tulip_private *tp = netdev_priv(dev);
827 void __iomem *ioaddr = tp->base_addr;
829 netif_stop_queue (dev);
834 printk (KERN_DEBUG "%s: Shutting down ethercard, status was %2.2x.\n",
835 dev->name, ioread32 (ioaddr + CSR5));
837 free_irq (dev->irq, dev);
839 tulip_free_ring (dev);
844 static struct net_device_stats *tulip_get_stats(struct net_device *dev)
846 struct tulip_private *tp = netdev_priv(dev);
847 void __iomem *ioaddr = tp->base_addr;
849 if (netif_running(dev)) {
852 spin_lock_irqsave (&tp->lock, flags);
854 tp->stats.rx_missed_errors += ioread32(ioaddr + CSR8) & 0xffff;
856 spin_unlock_irqrestore(&tp->lock, flags);
863 static void tulip_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
865 struct tulip_private *np = netdev_priv(dev);
866 strcpy(info->driver, DRV_NAME);
867 strcpy(info->version, DRV_VERSION);
868 strcpy(info->bus_info, pci_name(np->pdev));
871 static const struct ethtool_ops ops = {
872 .get_drvinfo = tulip_get_drvinfo
875 /* Provide ioctl() calls to examine the MII xcvr state. */
876 static int private_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
878 struct tulip_private *tp = netdev_priv(dev);
879 void __iomem *ioaddr = tp->base_addr;
880 struct mii_ioctl_data *data = if_mii(rq);
881 const unsigned int phy_idx = 0;
882 int phy = tp->phys[phy_idx] & 0x1f;
883 unsigned int regnum = data->reg_num;
886 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
889 else if (tp->flags & HAS_NWAY)
891 else if (tp->chip_id == COMET)
896 case SIOCGMIIREG: /* Read MII PHY register. */
897 if (data->phy_id == 32 && (tp->flags & HAS_NWAY)) {
898 int csr12 = ioread32 (ioaddr + CSR12);
899 int csr14 = ioread32 (ioaddr + CSR14);
902 if (((csr14<<5) & 0x1000) ||
903 (dev->if_port == 5 && tp->nwayset))
904 data->val_out = 0x1000;
906 data->val_out = (tulip_media_cap[dev->if_port]&MediaIs100 ? 0x2000 : 0)
907 | (tulip_media_cap[dev->if_port]&MediaIsFD ? 0x0100 : 0);
912 ((csr12&0x7000) == 0x5000 ? 0x20 : 0) +
913 ((csr12&0x06) == 6 ? 0 : 4);
914 data->val_out |= 0x6048;
917 /* Advertised value, bogus 10baseTx-FD value from CSR6. */
919 ((ioread32(ioaddr + CSR6) >> 3) & 0x0040) +
920 ((csr14 >> 1) & 0x20) + 1;
921 data->val_out |= ((csr14 >> 9) & 0x03C0);
923 case 5: data->val_out = tp->lpar; break;
924 default: data->val_out = 0; break;
927 data->val_out = tulip_mdio_read (dev, data->phy_id & 0x1f, regnum);
931 case SIOCSMIIREG: /* Write MII PHY register. */
934 if (data->phy_id == phy) {
935 u16 value = data->val_in;
937 case 0: /* Check for autonegotiation on or reset. */
938 tp->full_duplex_lock = (value & 0x9000) ? 0 : 1;
939 if (tp->full_duplex_lock)
940 tp->full_duplex = (value & 0x0100) ? 1 : 0;
943 tp->advertising[phy_idx] =
944 tp->mii_advertise = data->val_in;
948 if (data->phy_id == 32 && (tp->flags & HAS_NWAY)) {
949 u16 value = data->val_in;
951 if ((value & 0x1200) == 0x1200) {
952 if (tp->chip_id == PNIC2) {
953 pnic2_start_nway (dev);
955 t21142_start_nway (dev);
958 } else if (regnum == 4)
959 tp->sym_advertise = value;
961 tulip_mdio_write (dev, data->phy_id & 0x1f, regnum, data->val_in);
972 /* Set or clear the multicast filter for this adaptor.
973 Note that we only use exclusion around actually queueing the
974 new frame, not around filling tp->setup_frame. This is non-deterministic
975 when re-entered but still correct. */
978 #define set_bit_le(i,p) do { ((char *)(p))[(i)/8] |= (1<<((i)%8)); } while(0)
980 static void build_setup_frame_hash(u16 *setup_frm, struct net_device *dev)
982 struct tulip_private *tp = netdev_priv(dev);
984 struct dev_mc_list *mclist;
988 memset(hash_table, 0, sizeof(hash_table));
989 set_bit_le(255, hash_table); /* Broadcast entry */
990 /* This should work on big-endian machines as well. */
991 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
992 i++, mclist = mclist->next) {
993 int index = ether_crc_le(ETH_ALEN, mclist->dmi_addr) & 0x1ff;
995 set_bit_le(index, hash_table);
998 for (i = 0; i < 32; i++) {
999 *setup_frm++ = hash_table[i];
1000 *setup_frm++ = hash_table[i];
1002 setup_frm = &tp->setup_frame[13*6];
1004 /* Fill the final entry with our physical address. */
1005 eaddrs = (u16 *)dev->dev_addr;
1006 *setup_frm++ = eaddrs[0]; *setup_frm++ = eaddrs[0];
1007 *setup_frm++ = eaddrs[1]; *setup_frm++ = eaddrs[1];
1008 *setup_frm++ = eaddrs[2]; *setup_frm++ = eaddrs[2];
1011 static void build_setup_frame_perfect(u16 *setup_frm, struct net_device *dev)
1013 struct tulip_private *tp = netdev_priv(dev);
1014 struct dev_mc_list *mclist;
1018 /* We have <= 14 addresses so we can use the wonderful
1019 16 address perfect filtering of the Tulip. */
1020 for (i = 0, mclist = dev->mc_list; i < dev->mc_count;
1021 i++, mclist = mclist->next) {
1022 eaddrs = (u16 *)mclist->dmi_addr;
1023 *setup_frm++ = *eaddrs; *setup_frm++ = *eaddrs++;
1024 *setup_frm++ = *eaddrs; *setup_frm++ = *eaddrs++;
1025 *setup_frm++ = *eaddrs; *setup_frm++ = *eaddrs++;
1027 /* Fill the unused entries with the broadcast address. */
1028 memset(setup_frm, 0xff, (15-i)*12);
1029 setup_frm = &tp->setup_frame[15*6];
1031 /* Fill the final entry with our physical address. */
1032 eaddrs = (u16 *)dev->dev_addr;
1033 *setup_frm++ = eaddrs[0]; *setup_frm++ = eaddrs[0];
1034 *setup_frm++ = eaddrs[1]; *setup_frm++ = eaddrs[1];
1035 *setup_frm++ = eaddrs[2]; *setup_frm++ = eaddrs[2];
1039 static void set_rx_mode(struct net_device *dev)
1041 struct tulip_private *tp = netdev_priv(dev);
1042 void __iomem *ioaddr = tp->base_addr;
1045 csr6 = ioread32(ioaddr + CSR6) & ~0x00D5;
1047 tp->csr6 &= ~0x00D5;
1048 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1049 tp->csr6 |= AcceptAllMulticast | AcceptAllPhys;
1050 csr6 |= AcceptAllMulticast | AcceptAllPhys;
1051 } else if ((dev->mc_count > 1000) || (dev->flags & IFF_ALLMULTI)) {
1052 /* Too many to filter well -- accept all multicasts. */
1053 tp->csr6 |= AcceptAllMulticast;
1054 csr6 |= AcceptAllMulticast;
1055 } else if (tp->flags & MC_HASH_ONLY) {
1056 /* Some work-alikes have only a 64-entry hash filter table. */
1057 /* Should verify correctness on big-endian/__powerpc__ */
1058 struct dev_mc_list *mclist;
1060 if (dev->mc_count > 64) { /* Arbitrary non-effective limit. */
1061 tp->csr6 |= AcceptAllMulticast;
1062 csr6 |= AcceptAllMulticast;
1064 u32 mc_filter[2] = {0, 0}; /* Multicast hash filter */
1066 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1067 i++, mclist = mclist->next) {
1068 if (tp->flags & COMET_MAC_ADDR)
1069 filterbit = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
1071 filterbit = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
1073 mc_filter[filterbit >> 5] |= 1 << (filterbit & 31);
1074 if (tulip_debug > 2)
1075 printk(KERN_INFO "%s: Added filter for %pM"
1077 dev->name, mclist->dmi_addr,
1078 ether_crc(ETH_ALEN, mclist->dmi_addr), filterbit);
1080 if (mc_filter[0] == tp->mc_filter[0] &&
1081 mc_filter[1] == tp->mc_filter[1])
1083 else if (tp->flags & IS_ASIX) {
1084 iowrite32(2, ioaddr + CSR13);
1085 iowrite32(mc_filter[0], ioaddr + CSR14);
1086 iowrite32(3, ioaddr + CSR13);
1087 iowrite32(mc_filter[1], ioaddr + CSR14);
1088 } else if (tp->flags & COMET_MAC_ADDR) {
1089 iowrite32(mc_filter[0], ioaddr + 0xAC);
1090 iowrite32(mc_filter[1], ioaddr + 0xB0);
1092 tp->mc_filter[0] = mc_filter[0];
1093 tp->mc_filter[1] = mc_filter[1];
1096 unsigned long flags;
1097 u32 tx_flags = 0x08000000 | 192;
1099 /* Note that only the low-address shortword of setup_frame is valid!
1100 The values are doubled for big-endian architectures. */
1101 if (dev->mc_count > 14) { /* Must use a multicast hash table. */
1102 build_setup_frame_hash(tp->setup_frame, dev);
1103 tx_flags = 0x08400000 | 192;
1105 build_setup_frame_perfect(tp->setup_frame, dev);
1108 spin_lock_irqsave(&tp->lock, flags);
1110 if (tp->cur_tx - tp->dirty_tx > TX_RING_SIZE - 2) {
1111 /* Same setup recently queued, we need not add it. */
1116 /* Now add this frame to the Tx list. */
1118 entry = tp->cur_tx++ % TX_RING_SIZE;
1121 /* Avoid a chip errata by prefixing a dummy entry. */
1122 tp->tx_buffers[entry].skb = NULL;
1123 tp->tx_buffers[entry].mapping = 0;
1124 tp->tx_ring[entry].length =
1125 (entry == TX_RING_SIZE-1) ? cpu_to_le32(DESC_RING_WRAP) : 0;
1126 tp->tx_ring[entry].buffer1 = 0;
1127 /* Must set DescOwned later to avoid race with chip */
1129 entry = tp->cur_tx++ % TX_RING_SIZE;
1133 tp->tx_buffers[entry].skb = NULL;
1134 tp->tx_buffers[entry].mapping =
1135 pci_map_single(tp->pdev, tp->setup_frame,
1136 sizeof(tp->setup_frame),
1138 /* Put the setup frame on the Tx list. */
1139 if (entry == TX_RING_SIZE-1)
1140 tx_flags |= DESC_RING_WRAP; /* Wrap ring. */
1141 tp->tx_ring[entry].length = cpu_to_le32(tx_flags);
1142 tp->tx_ring[entry].buffer1 =
1143 cpu_to_le32(tp->tx_buffers[entry].mapping);
1144 tp->tx_ring[entry].status = cpu_to_le32(DescOwned);
1146 tp->tx_ring[dummy].status = cpu_to_le32(DescOwned);
1147 if (tp->cur_tx - tp->dirty_tx >= TX_RING_SIZE - 2)
1148 netif_stop_queue(dev);
1150 /* Trigger an immediate transmit demand. */
1151 iowrite32(0, ioaddr + CSR1);
1154 spin_unlock_irqrestore(&tp->lock, flags);
1157 iowrite32(csr6, ioaddr + CSR6);
1160 #ifdef CONFIG_TULIP_MWI
1161 static void __devinit tulip_mwi_config (struct pci_dev *pdev,
1162 struct net_device *dev)
1164 struct tulip_private *tp = netdev_priv(dev);
1169 if (tulip_debug > 3)
1170 printk(KERN_DEBUG "%s: tulip_mwi_config()\n", pci_name(pdev));
1172 tp->csr0 = csr0 = 0;
1174 /* if we have any cache line size at all, we can do MRM and MWI */
1177 /* Enable MWI in the standard PCI command bit.
1178 * Check for the case where MWI is desired but not available
1180 pci_try_set_mwi(pdev);
1182 /* read result from hardware (in case bit refused to enable) */
1183 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
1184 if ((csr0 & MWI) && (!(pci_command & PCI_COMMAND_INVALIDATE)))
1187 /* if cache line size hardwired to zero, no MWI */
1188 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache);
1189 if ((csr0 & MWI) && (cache == 0)) {
1191 pci_clear_mwi(pdev);
1194 /* assign per-cacheline-size cache alignment and
1195 * burst length values
1199 csr0 |= MRL | (1 << CALShift) | (16 << BurstLenShift);
1202 csr0 |= MRL | (2 << CALShift) | (16 << BurstLenShift);
1205 csr0 |= MRL | (3 << CALShift) | (32 << BurstLenShift);
1212 /* if we have a good cache line size, we by now have a good
1213 * csr0, so save it and exit
1218 /* we don't have a good csr0 or cache line size, disable MWI */
1220 pci_clear_mwi(pdev);
1224 /* sane defaults for burst length and cache alignment
1225 * originally from de4x5 driver
1227 csr0 |= (8 << BurstLenShift) | (1 << CALShift);
1231 if (tulip_debug > 2)
1232 printk(KERN_DEBUG "%s: MWI config cacheline=%d, csr0=%08x\n",
1233 pci_name(pdev), cache, csr0);
1238 * Chips that have the MRM/reserved bit quirk and the burst quirk. That
1239 * is the DM910X and the on chip ULi devices
1242 static int tulip_uli_dm_quirk(struct pci_dev *pdev)
1244 if (pdev->vendor == 0x1282 && pdev->device == 0x9102)
1249 static const struct net_device_ops tulip_netdev_ops = {
1250 .ndo_open = tulip_open,
1251 .ndo_start_xmit = tulip_start_xmit,
1252 .ndo_tx_timeout = tulip_tx_timeout,
1253 .ndo_stop = tulip_close,
1254 .ndo_get_stats = tulip_get_stats,
1255 .ndo_do_ioctl = private_ioctl,
1256 .ndo_set_multicast_list = set_rx_mode,
1257 .ndo_change_mtu = eth_change_mtu,
1258 .ndo_set_mac_address = eth_mac_addr,
1259 .ndo_validate_addr = eth_validate_addr,
1260 #ifdef CONFIG_NET_POLL_CONTROLLER
1261 .ndo_poll_controller = poll_tulip,
1265 static int __devinit tulip_init_one (struct pci_dev *pdev,
1266 const struct pci_device_id *ent)
1268 struct tulip_private *tp;
1269 /* See note below on the multiport cards. */
1270 static unsigned char last_phys_addr[6] = {0x00, 'L', 'i', 'n', 'u', 'x'};
1271 static struct pci_device_id early_486_chipsets[] = {
1272 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82424) },
1273 { PCI_DEVICE(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496) },
1276 static int last_irq;
1277 static int multiport_cnt; /* For four-port boards w/one EEPROM */
1280 unsigned char *ee_data;
1281 struct net_device *dev;
1282 void __iomem *ioaddr;
1283 static int board_idx = -1;
1284 int chip_idx = ent->driver_data;
1285 const char *chip_name = tulip_tbl[chip_idx].chip_name;
1286 unsigned int eeprom_missing = 0;
1287 unsigned int force_csr0 = 0;
1290 static int did_version; /* Already printed version info. */
1291 if (tulip_debug > 0 && did_version++ == 0)
1292 printk (KERN_INFO "%s", version);
1298 * Lan media wire a tulip chip to a wan interface. Needs a very
1299 * different driver (lmc driver)
1302 if (pdev->subsystem_vendor == PCI_VENDOR_ID_LMC) {
1303 printk (KERN_ERR PFX "skipping LMC card.\n");
1308 * DM910x chips should be handled by the dmfe driver, except
1309 * on-board chips on SPARC systems. Also, early DM9100s need
1310 * software CRC which only the dmfe driver supports.
1313 #ifdef CONFIG_TULIP_DM910X
1314 if (chip_idx == DM910X) {
1315 struct device_node *dp;
1317 if (pdev->vendor == 0x1282 && pdev->device == 0x9100 &&
1318 pdev->revision < 0x30) {
1319 printk(KERN_INFO PFX
1320 "skipping early DM9100 with Crc bug (use dmfe)\n");
1324 dp = pci_device_to_OF_node(pdev);
1325 if (!(dp && of_get_property(dp, "local-mac-address", NULL))) {
1326 printk(KERN_INFO PFX
1327 "skipping DM910x expansion card (use dmfe)\n");
1334 * Looks for early PCI chipsets where people report hangs
1335 * without the workarounds being on.
1338 /* 1. Intel Saturn. Switch to 8 long words burst, 8 long word cache
1339 aligned. Aries might need this too. The Saturn errata are not
1340 pretty reading but thankfully it's an old 486 chipset.
1342 2. The dreaded SiS496 486 chipset. Same workaround as Intel
1346 if (pci_dev_present(early_486_chipsets)) {
1347 csr0 = MRL | MRM | (8 << BurstLenShift) | (1 << CALShift);
1351 /* bugfix: the ASIX must have a burst limit or horrible things happen. */
1352 if (chip_idx == AX88140) {
1353 if ((csr0 & 0x3f00) == 0)
1357 /* PNIC doesn't have MWI/MRL/MRM... */
1358 if (chip_idx == LC82C168)
1359 csr0 &= ~0xfff10000; /* zero reserved bits 31:20, 16 */
1361 /* DM9102A has troubles with MRM & clear reserved bits 24:22, 20, 16, 7:1 */
1362 if (tulip_uli_dm_quirk(pdev)) {
1363 csr0 &= ~0x01f100ff;
1364 #if defined(CONFIG_SPARC)
1365 csr0 = (csr0 & ~0xff00) | 0xe000;
1369 * And back to business
1372 i = pci_enable_device(pdev);
1374 printk (KERN_ERR PFX
1375 "Cannot enable tulip board #%d, aborting\n",
1382 /* alloc_etherdev ensures aligned and zeroed private structures */
1383 dev = alloc_etherdev (sizeof (*tp));
1385 printk (KERN_ERR PFX "ether device alloc failed, aborting\n");
1389 SET_NETDEV_DEV(dev, &pdev->dev);
1390 if (pci_resource_len (pdev, 0) < tulip_tbl[chip_idx].io_size) {
1391 printk (KERN_ERR PFX "%s: I/O region (0x%llx@0x%llx) too small, "
1392 "aborting\n", pci_name(pdev),
1393 (unsigned long long)pci_resource_len (pdev, 0),
1394 (unsigned long long)pci_resource_start (pdev, 0));
1395 goto err_out_free_netdev;
1398 /* grab all resources from both PIO and MMIO regions, as we
1399 * don't want anyone else messing around with our hardware */
1400 if (pci_request_regions (pdev, "tulip"))
1401 goto err_out_free_netdev;
1403 ioaddr = pci_iomap(pdev, TULIP_BAR, tulip_tbl[chip_idx].io_size);
1406 goto err_out_free_res;
1409 * initialize private data structure 'tp'
1410 * it is zeroed and aligned in alloc_etherdev
1412 tp = netdev_priv(dev);
1415 tp->rx_ring = pci_alloc_consistent(pdev,
1416 sizeof(struct tulip_rx_desc) * RX_RING_SIZE +
1417 sizeof(struct tulip_tx_desc) * TX_RING_SIZE,
1420 goto err_out_mtable;
1421 tp->tx_ring = (struct tulip_tx_desc *)(tp->rx_ring + RX_RING_SIZE);
1422 tp->tx_ring_dma = tp->rx_ring_dma + sizeof(struct tulip_rx_desc) * RX_RING_SIZE;
1424 tp->chip_id = chip_idx;
1425 tp->flags = tulip_tbl[chip_idx].flags;
1427 tp->base_addr = ioaddr;
1428 tp->revision = pdev->revision;
1430 spin_lock_init(&tp->lock);
1431 spin_lock_init(&tp->mii_lock);
1432 init_timer(&tp->timer);
1433 tp->timer.data = (unsigned long)dev;
1434 tp->timer.function = tulip_tbl[tp->chip_id].media_timer;
1436 INIT_WORK(&tp->media_work, tulip_tbl[tp->chip_id].media_task);
1438 dev->base_addr = (unsigned long)ioaddr;
1440 #ifdef CONFIG_TULIP_MWI
1441 if (!force_csr0 && (tp->flags & HAS_PCI_MWI))
1442 tulip_mwi_config (pdev, dev);
1445 /* Stop the chip's Tx and Rx processes. */
1446 tulip_stop_rxtx(tp);
1448 pci_set_master(pdev);
1451 if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP) {
1452 switch (pdev->subsystem_device) {
1461 tp->flags |= HAS_SWAPPED_SEEPROM | NEEDS_FAKE_MEDIA_TABLE;
1462 chip_name = "GSC DS21140 Tulip";
1467 /* Clear the missed-packet counter. */
1468 ioread32(ioaddr + CSR8);
1470 /* The station address ROM is read byte serially. The register must
1471 be polled, waiting for the value to be read bit serially from the
1474 ee_data = tp->eeprom;
1475 memset(ee_data, 0, sizeof(tp->eeprom));
1477 if (chip_idx == LC82C168) {
1478 for (i = 0; i < 3; i++) {
1479 int value, boguscnt = 100000;
1480 iowrite32(0x600 | i, ioaddr + 0x98);
1482 value = ioread32(ioaddr + CSR9);
1483 } while (value < 0 && --boguscnt > 0);
1484 put_unaligned_le16(value, ((__le16 *)dev->dev_addr) + i);
1485 sum += value & 0xffff;
1487 } else if (chip_idx == COMET) {
1488 /* No need to read the EEPROM. */
1489 put_unaligned_le32(ioread32(ioaddr + 0xA4), dev->dev_addr);
1490 put_unaligned_le16(ioread32(ioaddr + 0xA8), dev->dev_addr + 4);
1491 for (i = 0; i < 6; i ++)
1492 sum += dev->dev_addr[i];
1494 /* A serial EEPROM interface, we read now and sort it out later. */
1496 int ee_addr_size = tulip_read_eeprom(dev, 0xff, 8) & 0x40000 ? 8 : 6;
1497 int ee_max_addr = ((1 << ee_addr_size) - 1) * sizeof(u16);
1499 if (ee_max_addr > sizeof(tp->eeprom))
1500 ee_max_addr = sizeof(tp->eeprom);
1502 for (i = 0; i < ee_max_addr ; i += sizeof(u16)) {
1503 u16 data = tulip_read_eeprom(dev, i/2, ee_addr_size);
1504 ee_data[i] = data & 0xff;
1505 ee_data[i + 1] = data >> 8;
1508 /* DEC now has a specification (see Notes) but early board makers
1509 just put the address in the first EEPROM locations. */
1510 /* This does memcmp(ee_data, ee_data+16, 8) */
1511 for (i = 0; i < 8; i ++)
1512 if (ee_data[i] != ee_data[16+i])
1514 if (chip_idx == CONEXANT) {
1515 /* Check that the tuple type and length is correct. */
1516 if (ee_data[0x198] == 0x04 && ee_data[0x199] == 6)
1518 } else if (ee_data[0] == 0xff && ee_data[1] == 0xff &&
1520 sa_offset = 2; /* Grrr, damn Matrox boards. */
1523 #ifdef CONFIG_MIPS_COBALT
1524 if ((pdev->bus->number == 0) &&
1525 ((PCI_SLOT(pdev->devfn) == 7) ||
1526 (PCI_SLOT(pdev->devfn) == 12))) {
1527 /* Cobalt MAC address in first EEPROM locations. */
1529 /* Ensure our media table fixup get's applied */
1530 memcpy(ee_data + 16, ee_data, 8);
1534 /* Check to see if we have a broken srom */
1535 if (ee_data[0] == 0x61 && ee_data[1] == 0x10) {
1536 /* pci_vendor_id and subsystem_id are swapped */
1537 ee_data[0] = ee_data[2];
1538 ee_data[1] = ee_data[3];
1542 /* HSC-PCI boards need to be byte-swaped and shifted
1543 * up 1 word. This shift needs to happen at the end
1544 * of the MAC first because of the 2 byte overlap.
1546 for (i = 4; i >= 0; i -= 2) {
1547 ee_data[17 + i + 3] = ee_data[17 + i];
1548 ee_data[16 + i + 5] = ee_data[16 + i];
1553 for (i = 0; i < 6; i ++) {
1554 dev->dev_addr[i] = ee_data[i + sa_offset];
1555 sum += ee_data[i + sa_offset];
1558 /* Lite-On boards have the address byte-swapped. */
1559 if ((dev->dev_addr[0] == 0xA0 || dev->dev_addr[0] == 0xC0 || dev->dev_addr[0] == 0x02)
1560 && dev->dev_addr[1] == 0x00)
1561 for (i = 0; i < 6; i+=2) {
1562 char tmp = dev->dev_addr[i];
1563 dev->dev_addr[i] = dev->dev_addr[i+1];
1564 dev->dev_addr[i+1] = tmp;
1566 /* On the Zynx 315 Etherarray and other multiport boards only the
1567 first Tulip has an EEPROM.
1568 On Sparc systems the mac address is held in the OBP property
1569 "local-mac-address".
1570 The addresses of the subsequent ports are derived from the first.
1571 Many PCI BIOSes also incorrectly report the IRQ line, so we correct
1572 that here as well. */
1573 if (sum == 0 || sum == 6*0xff) {
1574 #if defined(CONFIG_SPARC)
1575 struct device_node *dp = pci_device_to_OF_node(pdev);
1576 const unsigned char *addr;
1580 for (i = 0; i < 5; i++)
1581 dev->dev_addr[i] = last_phys_addr[i];
1582 dev->dev_addr[i] = last_phys_addr[i] + 1;
1583 #if defined(CONFIG_SPARC)
1584 addr = of_get_property(dp, "local-mac-address", &len);
1585 if (addr && len == 6)
1586 memcpy(dev->dev_addr, addr, 6);
1588 #if defined(__i386__) || defined(__x86_64__) /* Patch up x86 BIOS bug. */
1594 for (i = 0; i < 6; i++)
1595 last_phys_addr[i] = dev->dev_addr[i];
1599 /* The lower four bits are the media type. */
1600 if (board_idx >= 0 && board_idx < MAX_UNITS) {
1601 if (options[board_idx] & MEDIA_MASK)
1602 tp->default_port = options[board_idx] & MEDIA_MASK;
1603 if ((options[board_idx] & FullDuplex) || full_duplex[board_idx] > 0)
1604 tp->full_duplex = 1;
1605 if (mtu[board_idx] > 0)
1606 dev->mtu = mtu[board_idx];
1608 if (dev->mem_start & MEDIA_MASK)
1609 tp->default_port = dev->mem_start & MEDIA_MASK;
1610 if (tp->default_port) {
1611 printk(KERN_INFO "tulip%d: Transceiver selection forced to %s.\n",
1612 board_idx, medianame[tp->default_port & MEDIA_MASK]);
1614 if (tulip_media_cap[tp->default_port] & MediaAlwaysFD)
1615 tp->full_duplex = 1;
1617 if (tp->full_duplex)
1618 tp->full_duplex_lock = 1;
1620 if (tulip_media_cap[tp->default_port] & MediaIsMII) {
1621 u16 media2advert[] = { 0x20, 0x40, 0x03e0, 0x60, 0x80, 0x100, 0x200 };
1622 tp->mii_advertise = media2advert[tp->default_port - 9];
1623 tp->mii_advertise |= (tp->flags & HAS_8023X); /* Matching bits! */
1626 if (tp->flags & HAS_MEDIA_TABLE) {
1627 sprintf(dev->name, "tulip%d", board_idx); /* hack */
1628 tulip_parse_eeprom(dev);
1629 strcpy(dev->name, "eth%d"); /* un-hack */
1632 if ((tp->flags & ALWAYS_CHECK_MII) ||
1633 (tp->mtable && tp->mtable->has_mii) ||
1634 ( ! tp->mtable && (tp->flags & HAS_MII))) {
1635 if (tp->mtable && tp->mtable->has_mii) {
1636 for (i = 0; i < tp->mtable->leafcount; i++)
1637 if (tp->mtable->mleaf[i].media == 11) {
1639 tp->saved_if_port = dev->if_port;
1640 tulip_select_media(dev, 2);
1641 dev->if_port = tp->saved_if_port;
1646 /* Find the connected MII xcvrs.
1647 Doing this in open() would allow detecting external xcvrs
1648 later, but takes much time. */
1649 tulip_find_mii (dev, board_idx);
1652 /* The Tulip-specific entries in the device structure. */
1653 dev->netdev_ops = &tulip_netdev_ops;
1654 dev->watchdog_timeo = TX_TIMEOUT;
1655 #ifdef CONFIG_TULIP_NAPI
1656 netif_napi_add(dev, &tp->napi, tulip_poll, 16);
1658 SET_ETHTOOL_OPS(dev, &ops);
1660 if (register_netdev(dev))
1661 goto err_out_free_ring;
1663 printk(KERN_INFO "%s: %s rev %d at "
1664 #ifdef CONFIG_TULIP_MMIO
1669 " %#llx,", dev->name, chip_name, pdev->revision,
1670 (unsigned long long) pci_resource_start(pdev, TULIP_BAR));
1671 pci_set_drvdata(pdev, dev);
1674 printk(" EEPROM not present,");
1675 printk(" %pM", dev->dev_addr);
1676 printk(", IRQ %d.\n", irq);
1678 if (tp->chip_id == PNIC2)
1679 tp->link_change = pnic2_lnk_change;
1680 else if (tp->flags & HAS_NWAY)
1681 tp->link_change = t21142_lnk_change;
1682 else if (tp->flags & HAS_PNICNWAY)
1683 tp->link_change = pnic_lnk_change;
1685 /* Reset the xcvr interface and turn on heartbeat. */
1691 iowrite32(tp->mtable->csr12dir | 0x100, ioaddr + CSR12);
1694 if (tp->mii_cnt || tulip_media_cap[dev->if_port] & MediaIsMII) {
1695 iowrite32(csr6_mask_defstate, ioaddr + CSR6);
1696 iowrite32(0x0000, ioaddr + CSR13);
1697 iowrite32(0x0000, ioaddr + CSR14);
1698 iowrite32(csr6_mask_hdcap, ioaddr + CSR6);
1700 t21142_start_nway(dev);
1703 /* just do a reset for sanity sake */
1704 iowrite32(0x0000, ioaddr + CSR13);
1705 iowrite32(0x0000, ioaddr + CSR14);
1708 if ( ! tp->mii_cnt) {
1711 iowrite32(csr6_ttm | csr6_ca, ioaddr + CSR6);
1712 iowrite32(0x30, ioaddr + CSR12);
1713 iowrite32(0x0001F078, ioaddr + CSR6);
1714 iowrite32(0x0201F078, ioaddr + CSR6); /* Turn on autonegotiation. */
1719 iowrite32(0x00000000, ioaddr + CSR6);
1720 iowrite32(0x000711C0, ioaddr + CSR14); /* Turn on NWay. */
1721 iowrite32(0x00000001, ioaddr + CSR13);
1725 iowrite32(0x01a80000, ioaddr + CSR6);
1726 iowrite32(0xFFFFFFFF, ioaddr + CSR14);
1727 iowrite32(0x00001000, ioaddr + CSR12);
1730 /* No initialization necessary. */
1734 /* put the chip in snooze mode until opened */
1735 tulip_set_power_state (tp, 0, 1);
1740 pci_free_consistent (pdev,
1741 sizeof (struct tulip_rx_desc) * RX_RING_SIZE +
1742 sizeof (struct tulip_tx_desc) * TX_RING_SIZE,
1743 tp->rx_ring, tp->rx_ring_dma);
1747 pci_iounmap(pdev, ioaddr);
1750 pci_release_regions (pdev);
1752 err_out_free_netdev:
1760 static int tulip_suspend (struct pci_dev *pdev, pm_message_t state)
1762 struct net_device *dev = pci_get_drvdata(pdev);
1767 if (!netif_running(dev))
1772 netif_device_detach(dev);
1773 free_irq(dev->irq, dev);
1776 pci_save_state(pdev);
1777 pci_disable_device(pdev);
1778 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1784 static int tulip_resume(struct pci_dev *pdev)
1786 struct net_device *dev = pci_get_drvdata(pdev);
1792 pci_set_power_state(pdev, PCI_D0);
1793 pci_restore_state(pdev);
1795 if (!netif_running(dev))
1798 if ((retval = pci_enable_device(pdev))) {
1799 printk (KERN_ERR "tulip: pci_enable_device failed in resume\n");
1803 if ((retval = request_irq(dev->irq, &tulip_interrupt, IRQF_SHARED, dev->name, dev))) {
1804 printk (KERN_ERR "tulip: request_irq failed in resume\n");
1808 netif_device_attach(dev);
1810 if (netif_running(dev))
1816 #endif /* CONFIG_PM */
1819 static void __devexit tulip_remove_one (struct pci_dev *pdev)
1821 struct net_device *dev = pci_get_drvdata (pdev);
1822 struct tulip_private *tp;
1827 tp = netdev_priv(dev);
1828 unregister_netdev(dev);
1829 pci_free_consistent (pdev,
1830 sizeof (struct tulip_rx_desc) * RX_RING_SIZE +
1831 sizeof (struct tulip_tx_desc) * TX_RING_SIZE,
1832 tp->rx_ring, tp->rx_ring_dma);
1834 pci_iounmap(pdev, tp->base_addr);
1836 pci_release_regions (pdev);
1837 pci_set_drvdata (pdev, NULL);
1839 /* pci_power_off (pdev, -1); */
1842 #ifdef CONFIG_NET_POLL_CONTROLLER
1844 * Polling 'interrupt' - used by things like netconsole to send skbs
1845 * without having to re-enable interrupts. It's not called while
1846 * the interrupt routine is executing.
1849 static void poll_tulip (struct net_device *dev)
1851 /* disable_irq here is not very nice, but with the lockless
1852 interrupt handler we have no other choice. */
1853 disable_irq(dev->irq);
1854 tulip_interrupt (dev->irq, dev);
1855 enable_irq(dev->irq);
1859 static struct pci_driver tulip_driver = {
1861 .id_table = tulip_pci_tbl,
1862 .probe = tulip_init_one,
1863 .remove = __devexit_p(tulip_remove_one),
1865 .suspend = tulip_suspend,
1866 .resume = tulip_resume,
1867 #endif /* CONFIG_PM */
1871 static int __init tulip_init (void)
1874 printk (KERN_INFO "%s", version);
1877 /* copy module parms into globals */
1878 tulip_rx_copybreak = rx_copybreak;
1879 tulip_max_interrupt_work = max_interrupt_work;
1881 /* probe for and init boards */
1882 return pci_register_driver(&tulip_driver);
1886 static void __exit tulip_cleanup (void)
1888 pci_unregister_driver (&tulip_driver);
1892 module_init(tulip_init);
1893 module_exit(tulip_cleanup);