2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <linux/crc32.h>
26 #include <linux/kernel.h>
27 #include <linux/version.h>
28 #include <linux/module.h>
29 #include <linux/netdevice.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/pci.h>
36 #include <linux/tcp.h>
38 #include <linux/delay.h>
39 #include <linux/workqueue.h>
40 #include <linux/if_vlan.h>
41 #include <linux/prefetch.h>
42 #include <linux/debugfs.h>
43 #include <linux/mii.h>
47 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48 #define SKY2_VLAN_TAG_USED 1
53 #define DRV_NAME "sky2"
54 #define DRV_VERSION "1.17"
55 #define PFX DRV_NAME " "
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
63 #define RX_LE_SIZE 1024
64 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
65 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
66 #define RX_DEF_PENDING RX_MAX_PENDING
67 #define RX_SKB_ALIGN 8
69 #define TX_RING_SIZE 512
70 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
71 #define TX_MIN_PENDING 64
72 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
74 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
75 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
76 #define TX_WATCHDOG (5 * HZ)
77 #define NAPI_WEIGHT 64
78 #define PHY_RETRIES 1000
80 #define SKY2_EEPROM_MAGIC 0x9955aabb
83 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
85 static const u32 default_msg =
86 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
87 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
88 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
90 static int debug = -1; /* defaults above */
91 module_param(debug, int, 0);
92 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
94 static int copybreak __read_mostly = 128;
95 module_param(copybreak, int, 0);
96 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
98 static int disable_msi = 0;
99 module_param(disable_msi, int, 0);
100 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
102 static const struct pci_device_id sky2_id_table[] = {
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
136 MODULE_DEVICE_TABLE(pci, sky2_id_table);
138 /* Avoid conditionals by using array */
139 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
140 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
141 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
143 /* This driver supports yukon2 chipset only */
144 static const char *yukon2_name[] = {
146 "EC Ultra", /* 0xb4 */
147 "Extreme", /* 0xb5 */
152 static void sky2_set_multicast(struct net_device *dev);
154 /* Access to external PHY */
155 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
159 gma_write16(hw, port, GM_SMI_DATA, val);
160 gma_write16(hw, port, GM_SMI_CTRL,
161 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
163 for (i = 0; i < PHY_RETRIES; i++) {
164 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
169 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
173 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
177 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
178 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
180 for (i = 0; i < PHY_RETRIES; i++) {
181 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
182 *val = gma_read16(hw, port, GM_SMI_DATA);
192 static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
196 if (__gm_phy_read(hw, port, reg, &v) != 0)
197 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
202 static void sky2_power_on(struct sky2_hw *hw)
204 /* switch power to VCC (WA for VAUX problem) */
205 sky2_write8(hw, B0_POWER_CTRL,
206 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
208 /* disable Core Clock Division, */
209 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
211 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
212 /* enable bits are inverted */
213 sky2_write8(hw, B2_Y2_CLK_GATE,
214 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
215 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
216 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
218 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
220 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
223 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
225 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
226 /* set all bits to 0 except bits 15..12 and 8 */
227 reg &= P_ASPM_CONTROL_MSK;
228 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
230 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
231 /* set all bits to 0 except bits 28 & 27 */
232 reg &= P_CTL_TIM_VMAIN_AV_MSK;
233 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
235 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
237 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
238 reg = sky2_read32(hw, B2_GP_IO);
239 reg |= GLB_GPIO_STAT_RACE_DIS;
240 sky2_write32(hw, B2_GP_IO, reg);
242 sky2_read32(hw, B2_GP_IO);
246 static void sky2_power_aux(struct sky2_hw *hw)
248 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
249 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
251 /* enable bits are inverted */
252 sky2_write8(hw, B2_Y2_CLK_GATE,
253 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
254 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
255 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
257 /* switch power to VAUX */
258 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
259 sky2_write8(hw, B0_POWER_CTRL,
260 (PC_VAUX_ENA | PC_VCC_ENA |
261 PC_VAUX_ON | PC_VCC_OFF));
264 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
268 /* disable all GMAC IRQ's */
269 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
270 /* disable PHY IRQs */
271 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
273 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
274 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
275 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
276 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
278 reg = gma_read16(hw, port, GM_RX_CTRL);
279 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
280 gma_write16(hw, port, GM_RX_CTRL, reg);
283 /* flow control to advertise bits */
284 static const u16 copper_fc_adv[] = {
286 [FC_TX] = PHY_M_AN_ASP,
287 [FC_RX] = PHY_M_AN_PC,
288 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
291 /* flow control to advertise bits when using 1000BaseX */
292 static const u16 fiber_fc_adv[] = {
293 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
294 [FC_TX] = PHY_M_P_ASYM_MD_X,
295 [FC_RX] = PHY_M_P_SYM_MD_X,
296 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
299 /* flow control to GMA disable bits */
300 static const u16 gm_fc_disable[] = {
301 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
302 [FC_TX] = GM_GPCR_FC_RX_DIS,
303 [FC_RX] = GM_GPCR_FC_TX_DIS,
308 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
310 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
311 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
313 if (sky2->autoneg == AUTONEG_ENABLE &&
314 !(hw->flags & SKY2_HW_NEWER_PHY)) {
315 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
317 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
319 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
321 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
322 if (hw->chip_id == CHIP_ID_YUKON_EC)
323 /* set downshift counter to 3x and enable downshift */
324 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
326 /* set master & slave downshift counter to 1x */
327 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
329 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
332 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
333 if (sky2_is_copper(hw)) {
334 if (hw->chip_id == CHIP_ID_YUKON_FE) {
335 /* enable automatic crossover */
336 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
338 /* disable energy detect */
339 ctrl &= ~PHY_M_PC_EN_DET_MSK;
341 /* enable automatic crossover */
342 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
344 /* downshift on PHY 88E1112 and 88E1149 is changed */
345 if (sky2->autoneg == AUTONEG_ENABLE
346 && (hw->flags & SKY2_HW_NEWER_PHY)) {
347 /* set downshift counter to 3x and enable downshift */
348 ctrl &= ~PHY_M_PC_DSC_MSK;
349 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
353 /* workaround for deviation #4.88 (CRC errors) */
354 /* disable Automatic Crossover */
356 ctrl &= ~PHY_M_PC_MDIX_MSK;
359 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
361 /* special setup for PHY 88E1112 Fiber */
362 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
363 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
365 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
366 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
367 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
368 ctrl &= ~PHY_M_MAC_MD_MSK;
369 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
370 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
372 if (hw->pmd_type == 'P') {
373 /* select page 1 to access Fiber registers */
374 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
376 /* for SFP-module set SIGDET polarity to low */
377 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
378 ctrl |= PHY_M_FIB_SIGD_POL;
379 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
382 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
390 if (sky2->autoneg == AUTONEG_ENABLE) {
391 if (sky2_is_copper(hw)) {
392 if (sky2->advertising & ADVERTISED_1000baseT_Full)
393 ct1000 |= PHY_M_1000C_AFD;
394 if (sky2->advertising & ADVERTISED_1000baseT_Half)
395 ct1000 |= PHY_M_1000C_AHD;
396 if (sky2->advertising & ADVERTISED_100baseT_Full)
397 adv |= PHY_M_AN_100_FD;
398 if (sky2->advertising & ADVERTISED_100baseT_Half)
399 adv |= PHY_M_AN_100_HD;
400 if (sky2->advertising & ADVERTISED_10baseT_Full)
401 adv |= PHY_M_AN_10_FD;
402 if (sky2->advertising & ADVERTISED_10baseT_Half)
403 adv |= PHY_M_AN_10_HD;
405 adv |= copper_fc_adv[sky2->flow_mode];
406 } else { /* special defines for FIBER (88E1040S only) */
407 if (sky2->advertising & ADVERTISED_1000baseT_Full)
408 adv |= PHY_M_AN_1000X_AFD;
409 if (sky2->advertising & ADVERTISED_1000baseT_Half)
410 adv |= PHY_M_AN_1000X_AHD;
412 adv |= fiber_fc_adv[sky2->flow_mode];
415 /* Restart Auto-negotiation */
416 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
418 /* forced speed/duplex settings */
419 ct1000 = PHY_M_1000C_MSE;
421 /* Disable auto update for duplex flow control and speed */
422 reg |= GM_GPCR_AU_ALL_DIS;
424 switch (sky2->speed) {
426 ctrl |= PHY_CT_SP1000;
427 reg |= GM_GPCR_SPEED_1000;
430 ctrl |= PHY_CT_SP100;
431 reg |= GM_GPCR_SPEED_100;
435 if (sky2->duplex == DUPLEX_FULL) {
436 reg |= GM_GPCR_DUP_FULL;
437 ctrl |= PHY_CT_DUP_MD;
438 } else if (sky2->speed < SPEED_1000)
439 sky2->flow_mode = FC_NONE;
442 reg |= gm_fc_disable[sky2->flow_mode];
444 /* Forward pause packets to GMAC? */
445 if (sky2->flow_mode & FC_RX)
446 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
448 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
451 gma_write16(hw, port, GM_GP_CTRL, reg);
453 if (hw->chip_id != CHIP_ID_YUKON_FE)
454 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
456 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
457 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
459 /* Setup Phy LED's */
460 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
463 switch (hw->chip_id) {
464 case CHIP_ID_YUKON_FE:
465 /* on 88E3082 these bits are at 11..9 (shifted left) */
466 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
468 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
470 /* delete ACT LED control bits */
471 ctrl &= ~PHY_M_FELP_LED1_MSK;
472 /* change ACT LED control to blink mode */
473 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
474 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
477 case CHIP_ID_YUKON_XL:
478 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
480 /* select page 3 to access LED control register */
481 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
483 /* set LED Function Control register */
484 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
485 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
486 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
487 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
488 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
490 /* set Polarity Control register */
491 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
492 (PHY_M_POLC_LS1_P_MIX(4) |
493 PHY_M_POLC_IS0_P_MIX(4) |
494 PHY_M_POLC_LOS_CTRL(2) |
495 PHY_M_POLC_INIT_CTRL(2) |
496 PHY_M_POLC_STA1_CTRL(2) |
497 PHY_M_POLC_STA0_CTRL(2)));
499 /* restore page register */
500 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
503 case CHIP_ID_YUKON_EC_U:
504 case CHIP_ID_YUKON_EX:
505 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
507 /* select page 3 to access LED control register */
508 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
510 /* set LED Function Control register */
511 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
512 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
513 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
514 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
515 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
517 /* set Blink Rate in LED Timer Control Register */
518 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
519 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
520 /* restore page register */
521 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
525 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
526 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
527 /* turn off the Rx LED (LED_RX) */
528 ledover &= ~PHY_M_LED_MO_RX;
531 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
532 hw->chip_rev == CHIP_REV_YU_EC_U_A1) {
533 /* apply fixes in PHY AFE */
534 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
536 /* increase differential signal amplitude in 10BASE-T */
537 gm_phy_write(hw, port, 0x18, 0xaa99);
538 gm_phy_write(hw, port, 0x17, 0x2011);
540 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
541 gm_phy_write(hw, port, 0x18, 0xa204);
542 gm_phy_write(hw, port, 0x17, 0x2002);
544 /* set page register to 0 */
545 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
546 } else if (hw->chip_id != CHIP_ID_YUKON_EX) {
547 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
549 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
550 /* turn on 100 Mbps LED (LED_LINK100) */
551 ledover |= PHY_M_LED_MO_100;
555 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
559 /* Enable phy interrupt on auto-negotiation complete (or link up) */
560 if (sky2->autoneg == AUTONEG_ENABLE)
561 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
563 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
566 static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
569 static const u32 phy_power[]
570 = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
572 /* looks like this XL is back asswards .. */
573 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
576 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
577 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
579 /* Turn off phy power saving */
580 reg1 &= ~phy_power[port];
582 reg1 |= phy_power[port];
584 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
585 sky2_pci_read32(hw, PCI_DEV_REG1);
586 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
590 /* Force a renegotiation */
591 static void sky2_phy_reinit(struct sky2_port *sky2)
593 spin_lock_bh(&sky2->phy_lock);
594 sky2_phy_init(sky2->hw, sky2->port);
595 spin_unlock_bh(&sky2->phy_lock);
598 /* Put device in state to listen for Wake On Lan */
599 static void sky2_wol_init(struct sky2_port *sky2)
601 struct sky2_hw *hw = sky2->hw;
602 unsigned port = sky2->port;
603 enum flow_control save_mode;
607 /* Bring hardware out of reset */
608 sky2_write16(hw, B0_CTST, CS_RST_CLR);
609 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
611 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
612 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
615 * sky2_reset will re-enable on resume
617 save_mode = sky2->flow_mode;
618 ctrl = sky2->advertising;
620 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
621 sky2->flow_mode = FC_NONE;
622 sky2_phy_power(hw, port, 1);
623 sky2_phy_reinit(sky2);
625 sky2->flow_mode = save_mode;
626 sky2->advertising = ctrl;
628 /* Set GMAC to no flow control and auto update for speed/duplex */
629 gma_write16(hw, port, GM_GP_CTRL,
630 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
631 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
633 /* Set WOL address */
634 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
635 sky2->netdev->dev_addr, ETH_ALEN);
637 /* Turn on appropriate WOL control bits */
638 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
640 if (sky2->wol & WAKE_PHY)
641 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
643 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
645 if (sky2->wol & WAKE_MAGIC)
646 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
648 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
650 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
651 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
653 /* Turn on legacy PCI-Express PME mode */
654 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
655 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
656 reg1 |= PCI_Y2_PME_LEGACY;
657 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
658 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
661 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
665 static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
667 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev != CHIP_REV_YU_EX_A0) {
668 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
670 (hw->dev[port]->mtu > ETH_DATA_LEN) ? TX_JUMBO_ENA : TX_JUMBO_DIS);
672 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
673 /* set Tx GMAC FIFO Almost Empty Threshold */
674 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
675 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
677 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
678 TX_JUMBO_ENA | TX_STFW_DIS);
680 /* Can't do offload because of lack of store/forward */
681 hw->dev[port]->features &= ~(NETIF_F_TSO | NETIF_F_SG
684 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
685 TX_JUMBO_DIS | TX_STFW_ENA);
689 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
691 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
695 const u8 *addr = hw->dev[port]->dev_addr;
697 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
698 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
700 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
702 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
703 /* WA DEV_472 -- looks like crossed wires on port 2 */
704 /* clear GMAC 1 Control reset */
705 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
707 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
708 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
709 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
710 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
711 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
714 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
716 /* Enable Transmit FIFO Underrun */
717 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
719 spin_lock_bh(&sky2->phy_lock);
720 sky2_phy_init(hw, port);
721 spin_unlock_bh(&sky2->phy_lock);
724 reg = gma_read16(hw, port, GM_PHY_ADDR);
725 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
727 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
728 gma_read16(hw, port, i);
729 gma_write16(hw, port, GM_PHY_ADDR, reg);
731 /* transmit control */
732 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
734 /* receive control reg: unicast + multicast + no FCS */
735 gma_write16(hw, port, GM_RX_CTRL,
736 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
738 /* transmit flow control */
739 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
741 /* transmit parameter */
742 gma_write16(hw, port, GM_TX_PARAM,
743 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
744 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
745 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
746 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
748 /* serial mode register */
749 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
750 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
752 if (hw->dev[port]->mtu > ETH_DATA_LEN)
753 reg |= GM_SMOD_JUMBO_ENA;
755 gma_write16(hw, port, GM_SERIAL_MODE, reg);
757 /* virtual address for data */
758 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
760 /* physical address: used for pause frames */
761 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
763 /* ignore counter overflows */
764 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
765 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
766 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
768 /* Configure Rx MAC FIFO */
769 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
770 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
771 if (hw->chip_id == CHIP_ID_YUKON_EX)
772 rx_reg |= GMF_RX_OVER_ON;
774 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
776 /* Flush Rx MAC FIFO on any flow control or error */
777 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
779 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
780 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
782 /* Configure Tx MAC FIFO */
783 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
784 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
786 if (!(hw->flags & SKY2_HW_RAMBUFFER)) {
787 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
788 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
790 sky2_set_tx_stfwd(hw, port);
795 /* Assign Ram Buffer allocation to queue */
796 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
800 /* convert from K bytes to qwords used for hw register */
803 end = start + space - 1;
805 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
806 sky2_write32(hw, RB_ADDR(q, RB_START), start);
807 sky2_write32(hw, RB_ADDR(q, RB_END), end);
808 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
809 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
811 if (q == Q_R1 || q == Q_R2) {
812 u32 tp = space - space/4;
814 /* On receive queue's set the thresholds
815 * give receiver priority when > 3/4 full
816 * send pause when down to 2K
818 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
819 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
822 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
823 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
825 /* Enable store & forward on Tx queue's because
826 * Tx FIFO is only 1K on Yukon
828 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
831 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
832 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
835 /* Setup Bus Memory Interface */
836 static void sky2_qset(struct sky2_hw *hw, u16 q)
838 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
839 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
840 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
841 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
844 /* Setup prefetch unit registers. This is the interface between
845 * hardware and driver list elements
847 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
850 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
851 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
852 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
853 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
854 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
855 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
857 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
860 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
862 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
864 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
869 static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
870 struct sky2_tx_le *le)
872 return sky2->tx_ring + (le - sky2->tx_le);
875 /* Update chip's next pointer */
876 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
878 /* Make sure write' to descriptors are complete before we tell hardware */
880 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
882 /* Synchronize I/O on since next processor may write to tail */
887 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
889 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
890 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
895 /* Build description to hardware for one receive segment */
896 static void sky2_rx_add(struct sky2_port *sky2, u8 op,
897 dma_addr_t map, unsigned len)
899 struct sky2_rx_le *le;
900 u32 hi = upper_32_bits(map);
902 if (sky2->rx_addr64 != hi) {
903 le = sky2_next_rx(sky2);
904 le->addr = cpu_to_le32(hi);
905 le->opcode = OP_ADDR64 | HW_OWNER;
906 sky2->rx_addr64 = upper_32_bits(map + len);
909 le = sky2_next_rx(sky2);
910 le->addr = cpu_to_le32((u32) map);
911 le->length = cpu_to_le16(len);
912 le->opcode = op | HW_OWNER;
915 /* Build description to hardware for one possibly fragmented skb */
916 static void sky2_rx_submit(struct sky2_port *sky2,
917 const struct rx_ring_info *re)
921 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
923 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
924 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
928 static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
931 struct sk_buff *skb = re->skb;
934 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
935 pci_unmap_len_set(re, data_size, size);
937 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
938 re->frag_addr[i] = pci_map_page(pdev,
939 skb_shinfo(skb)->frags[i].page,
940 skb_shinfo(skb)->frags[i].page_offset,
941 skb_shinfo(skb)->frags[i].size,
945 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
947 struct sk_buff *skb = re->skb;
950 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
953 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
954 pci_unmap_page(pdev, re->frag_addr[i],
955 skb_shinfo(skb)->frags[i].size,
959 /* Tell chip where to start receive checksum.
960 * Actually has two checksums, but set both same to avoid possible byte
963 static void rx_set_checksum(struct sky2_port *sky2)
965 struct sky2_rx_le *le = sky2_next_rx(sky2);
967 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
969 le->opcode = OP_TCPSTART | HW_OWNER;
971 sky2_write32(sky2->hw,
972 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
973 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
977 * The RX Stop command will not work for Yukon-2 if the BMU does not
978 * reach the end of packet and since we can't make sure that we have
979 * incoming data, we must reset the BMU while it is not doing a DMA
980 * transfer. Since it is possible that the RX path is still active,
981 * the RX RAM buffer will be stopped first, so any possible incoming
982 * data will not trigger a DMA. After the RAM buffer is stopped, the
983 * BMU is polled until any DMA in progress is ended and only then it
986 static void sky2_rx_stop(struct sky2_port *sky2)
988 struct sky2_hw *hw = sky2->hw;
989 unsigned rxq = rxqaddr[sky2->port];
992 /* disable the RAM Buffer receive queue */
993 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
995 for (i = 0; i < 0xffff; i++)
996 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
997 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1000 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1001 sky2->netdev->name);
1003 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1005 /* reset the Rx prefetch unit */
1006 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1010 /* Clean out receive buffer area, assumes receiver hardware stopped */
1011 static void sky2_rx_clean(struct sky2_port *sky2)
1015 memset(sky2->rx_le, 0, RX_LE_BYTES);
1016 for (i = 0; i < sky2->rx_pending; i++) {
1017 struct rx_ring_info *re = sky2->rx_ring + i;
1020 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1027 /* Basic MII support */
1028 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1030 struct mii_ioctl_data *data = if_mii(ifr);
1031 struct sky2_port *sky2 = netdev_priv(dev);
1032 struct sky2_hw *hw = sky2->hw;
1033 int err = -EOPNOTSUPP;
1035 if (!netif_running(dev))
1036 return -ENODEV; /* Phy still in reset */
1040 data->phy_id = PHY_ADDR_MARV;
1046 spin_lock_bh(&sky2->phy_lock);
1047 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1048 spin_unlock_bh(&sky2->phy_lock);
1050 data->val_out = val;
1055 if (!capable(CAP_NET_ADMIN))
1058 spin_lock_bh(&sky2->phy_lock);
1059 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1061 spin_unlock_bh(&sky2->phy_lock);
1067 #ifdef SKY2_VLAN_TAG_USED
1068 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1070 struct sky2_port *sky2 = netdev_priv(dev);
1071 struct sky2_hw *hw = sky2->hw;
1072 u16 port = sky2->port;
1074 netif_tx_lock_bh(dev);
1075 netif_poll_disable(sky2->hw->dev[0]);
1079 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1081 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1084 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1086 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1090 netif_poll_enable(sky2->hw->dev[0]);
1091 netif_tx_unlock_bh(dev);
1096 * Allocate an skb for receiving. If the MTU is large enough
1097 * make the skb non-linear with a fragment list of pages.
1099 * It appears the hardware has a bug in the FIFO logic that
1100 * cause it to hang if the FIFO gets overrun and the receive buffer
1101 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1102 * aligned except if slab debugging is enabled.
1104 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
1106 struct sk_buff *skb;
1110 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + RX_SKB_ALIGN);
1114 p = (unsigned long) skb->data;
1115 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
1117 for (i = 0; i < sky2->rx_nfrags; i++) {
1118 struct page *page = alloc_page(GFP_ATOMIC);
1122 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1132 static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1134 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1138 * Allocate and setup receiver buffer pool.
1139 * Normal case this ends up creating one list element for skb
1140 * in the receive ring. Worst case if using large MTU and each
1141 * allocation falls on a different 64 bit region, that results
1142 * in 6 list elements per ring entry.
1143 * One element is used for checksum enable/disable, and one
1144 * extra to avoid wrap.
1146 static int sky2_rx_start(struct sky2_port *sky2)
1148 struct sky2_hw *hw = sky2->hw;
1149 struct rx_ring_info *re;
1150 unsigned rxq = rxqaddr[sky2->port];
1151 unsigned i, size, space, thresh;
1153 sky2->rx_put = sky2->rx_next = 0;
1156 /* On PCI express lowering the watermark gives better performance */
1157 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1158 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1160 /* These chips have no ram buffer?
1161 * MAC Rx RAM Read is controlled by hardware */
1162 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1163 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1164 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
1165 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
1167 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1169 if (!(hw->flags & SKY2_HW_NEW_LE))
1170 rx_set_checksum(sky2);
1172 /* Space needed for frame data + headers rounded up */
1173 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1175 /* Stopping point for hardware truncation */
1176 thresh = (size - 8) / sizeof(u32);
1178 /* Account for overhead of skb - to avoid order > 0 allocation */
1179 space = SKB_DATA_ALIGN(size) + NET_SKB_PAD
1180 + sizeof(struct skb_shared_info);
1182 sky2->rx_nfrags = space >> PAGE_SHIFT;
1183 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1185 if (sky2->rx_nfrags != 0) {
1186 /* Compute residue after pages */
1187 space = sky2->rx_nfrags << PAGE_SHIFT;
1194 /* Optimize to handle small packets and headers */
1195 if (size < copybreak)
1197 if (size < ETH_HLEN)
1200 sky2->rx_data_size = size;
1203 for (i = 0; i < sky2->rx_pending; i++) {
1204 re = sky2->rx_ring + i;
1206 re->skb = sky2_rx_alloc(sky2);
1210 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1211 sky2_rx_submit(sky2, re);
1215 * The receiver hangs if it receives frames larger than the
1216 * packet buffer. As a workaround, truncate oversize frames, but
1217 * the register is limited to 9 bits, so if you do frames > 2052
1218 * you better get the MTU right!
1221 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1223 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1224 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1227 /* Tell chip about available buffers */
1228 sky2_rx_update(sky2, rxq);
1231 sky2_rx_clean(sky2);
1235 /* Bring up network interface. */
1236 static int sky2_up(struct net_device *dev)
1238 struct sky2_port *sky2 = netdev_priv(dev);
1239 struct sky2_hw *hw = sky2->hw;
1240 unsigned port = sky2->port;
1242 int cap, err = -ENOMEM;
1243 struct net_device *otherdev = hw->dev[sky2->port^1];
1246 * On dual port PCI-X card, there is an problem where status
1247 * can be received out of order due to split transactions
1249 if (otherdev && netif_running(otherdev) &&
1250 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1251 struct sky2_port *osky2 = netdev_priv(otherdev);
1254 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1255 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1256 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1262 if (netif_msg_ifup(sky2))
1263 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1265 netif_carrier_off(dev);
1267 /* must be power of 2 */
1268 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1270 sizeof(struct sky2_tx_le),
1275 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
1279 sky2->tx_prod = sky2->tx_cons = 0;
1281 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1285 memset(sky2->rx_le, 0, RX_LE_BYTES);
1287 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1292 sky2_phy_power(hw, port, 1);
1294 sky2_mac_init(hw, port);
1296 if (hw->flags & SKY2_HW_RAMBUFFER) {
1297 /* Register is number of 4K blocks on internal RAM buffer. */
1298 u32 ramsize = sky2_read8(hw, B2_E_0) * 4;
1301 printk(KERN_DEBUG PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1304 rxspace = ramsize / 2;
1306 rxspace = 8 + (2*(ramsize - 16))/3;
1308 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1309 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1311 /* Make sure SyncQ is disabled */
1312 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1316 sky2_qset(hw, txqaddr[port]);
1318 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1319 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1320 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1322 /* Set almost empty threshold */
1323 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1324 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1325 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
1327 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1330 err = sky2_rx_start(sky2);
1334 /* Enable interrupts from phy/mac for port */
1335 imask = sky2_read32(hw, B0_IMSK);
1336 imask |= portirq_msk[port];
1337 sky2_write32(hw, B0_IMSK, imask);
1343 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1344 sky2->rx_le, sky2->rx_le_map);
1348 pci_free_consistent(hw->pdev,
1349 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1350 sky2->tx_le, sky2->tx_le_map);
1353 kfree(sky2->tx_ring);
1354 kfree(sky2->rx_ring);
1356 sky2->tx_ring = NULL;
1357 sky2->rx_ring = NULL;
1361 /* Modular subtraction in ring */
1362 static inline int tx_dist(unsigned tail, unsigned head)
1364 return (head - tail) & (TX_RING_SIZE - 1);
1367 /* Number of list elements available for next tx */
1368 static inline int tx_avail(const struct sky2_port *sky2)
1370 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1373 /* Estimate of number of transmit list elements required */
1374 static unsigned tx_le_req(const struct sk_buff *skb)
1378 count = sizeof(dma_addr_t) / sizeof(u32);
1379 count += skb_shinfo(skb)->nr_frags * count;
1381 if (skb_is_gso(skb))
1384 if (skb->ip_summed == CHECKSUM_PARTIAL)
1391 * Put one packet in ring for transmit.
1392 * A single packet can generate multiple list elements, and
1393 * the number of ring elements will probably be less than the number
1394 * of list elements used.
1396 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1398 struct sky2_port *sky2 = netdev_priv(dev);
1399 struct sky2_hw *hw = sky2->hw;
1400 struct sky2_tx_le *le = NULL;
1401 struct tx_ring_info *re;
1408 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1409 return NETDEV_TX_BUSY;
1411 if (unlikely(netif_msg_tx_queued(sky2)))
1412 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1413 dev->name, sky2->tx_prod, skb->len);
1415 len = skb_headlen(skb);
1416 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1417 addr64 = upper_32_bits(mapping);
1419 /* Send high bits if changed or crosses boundary */
1420 if (addr64 != sky2->tx_addr64 ||
1421 upper_32_bits(mapping + len) != sky2->tx_addr64) {
1422 le = get_tx_le(sky2);
1423 le->addr = cpu_to_le32(addr64);
1424 le->opcode = OP_ADDR64 | HW_OWNER;
1425 sky2->tx_addr64 = upper_32_bits(mapping + len);
1428 /* Check for TCP Segmentation Offload */
1429 mss = skb_shinfo(skb)->gso_size;
1432 if (!(hw->flags & SKY2_HW_NEW_LE))
1433 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1435 if (mss != sky2->tx_last_mss) {
1436 le = get_tx_le(sky2);
1437 le->addr = cpu_to_le32(mss);
1439 if (hw->flags & SKY2_HW_NEW_LE)
1440 le->opcode = OP_MSS | HW_OWNER;
1442 le->opcode = OP_LRGLEN | HW_OWNER;
1443 sky2->tx_last_mss = mss;
1448 #ifdef SKY2_VLAN_TAG_USED
1449 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1450 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1452 le = get_tx_le(sky2);
1454 le->opcode = OP_VLAN|HW_OWNER;
1456 le->opcode |= OP_VLAN;
1457 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1462 /* Handle TCP checksum offload */
1463 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1464 /* On Yukon EX (some versions) encoding change. */
1465 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
1466 ctrl |= CALSUM; /* auto checksum */
1468 const unsigned offset = skb_transport_offset(skb);
1471 tcpsum = offset << 16; /* sum start */
1472 tcpsum |= offset + skb->csum_offset; /* sum write */
1474 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1475 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1478 if (tcpsum != sky2->tx_tcpsum) {
1479 sky2->tx_tcpsum = tcpsum;
1481 le = get_tx_le(sky2);
1482 le->addr = cpu_to_le32(tcpsum);
1483 le->length = 0; /* initial checksum value */
1484 le->ctrl = 1; /* one packet */
1485 le->opcode = OP_TCPLISW | HW_OWNER;
1490 le = get_tx_le(sky2);
1491 le->addr = cpu_to_le32((u32) mapping);
1492 le->length = cpu_to_le16(len);
1494 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1496 re = tx_le_re(sky2, le);
1498 pci_unmap_addr_set(re, mapaddr, mapping);
1499 pci_unmap_len_set(re, maplen, len);
1501 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1502 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1504 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1505 frag->size, PCI_DMA_TODEVICE);
1506 addr64 = upper_32_bits(mapping);
1507 if (addr64 != sky2->tx_addr64) {
1508 le = get_tx_le(sky2);
1509 le->addr = cpu_to_le32(addr64);
1511 le->opcode = OP_ADDR64 | HW_OWNER;
1512 sky2->tx_addr64 = addr64;
1515 le = get_tx_le(sky2);
1516 le->addr = cpu_to_le32((u32) mapping);
1517 le->length = cpu_to_le16(frag->size);
1519 le->opcode = OP_BUFFER | HW_OWNER;
1521 re = tx_le_re(sky2, le);
1523 pci_unmap_addr_set(re, mapaddr, mapping);
1524 pci_unmap_len_set(re, maplen, frag->size);
1529 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1530 netif_stop_queue(dev);
1532 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1534 dev->trans_start = jiffies;
1535 return NETDEV_TX_OK;
1539 * Free ring elements from starting at tx_cons until "done"
1541 * NB: the hardware will tell us about partial completion of multi-part
1542 * buffers so make sure not to free skb to early.
1544 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1546 struct net_device *dev = sky2->netdev;
1547 struct pci_dev *pdev = sky2->hw->pdev;
1550 BUG_ON(done >= TX_RING_SIZE);
1552 for (idx = sky2->tx_cons; idx != done;
1553 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1554 struct sky2_tx_le *le = sky2->tx_le + idx;
1555 struct tx_ring_info *re = sky2->tx_ring + idx;
1557 switch(le->opcode & ~HW_OWNER) {
1560 pci_unmap_single(pdev,
1561 pci_unmap_addr(re, mapaddr),
1562 pci_unmap_len(re, maplen),
1566 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1567 pci_unmap_len(re, maplen),
1572 if (le->ctrl & EOP) {
1573 if (unlikely(netif_msg_tx_done(sky2)))
1574 printk(KERN_DEBUG "%s: tx done %u\n",
1577 sky2->net_stats.tx_packets++;
1578 sky2->net_stats.tx_bytes += re->skb->len;
1580 dev_kfree_skb_any(re->skb);
1581 sky2->tx_next = RING_NEXT(idx, TX_RING_SIZE);
1585 sky2->tx_cons = idx;
1588 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
1589 netif_wake_queue(dev);
1592 /* Cleanup all untransmitted buffers, assume transmitter not running */
1593 static void sky2_tx_clean(struct net_device *dev)
1595 struct sky2_port *sky2 = netdev_priv(dev);
1597 netif_tx_lock_bh(dev);
1598 sky2_tx_complete(sky2, sky2->tx_prod);
1599 netif_tx_unlock_bh(dev);
1602 /* Network shutdown */
1603 static int sky2_down(struct net_device *dev)
1605 struct sky2_port *sky2 = netdev_priv(dev);
1606 struct sky2_hw *hw = sky2->hw;
1607 unsigned port = sky2->port;
1611 /* Never really got started! */
1615 if (netif_msg_ifdown(sky2))
1616 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1618 if (netif_carrier_ok(dev) && --hw->active == 0)
1619 del_timer(&hw->watchdog_timer);
1621 /* Stop more packets from being queued */
1622 netif_stop_queue(dev);
1624 /* Disable port IRQ */
1625 imask = sky2_read32(hw, B0_IMSK);
1626 imask &= ~portirq_msk[port];
1627 sky2_write32(hw, B0_IMSK, imask);
1629 sky2_gmac_reset(hw, port);
1631 /* Stop transmitter */
1632 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1633 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1635 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1636 RB_RST_SET | RB_DIS_OP_MD);
1638 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1639 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1640 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1642 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1644 /* Workaround shared GMAC reset */
1645 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1646 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1647 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1649 /* Disable Force Sync bit and Enable Alloc bit */
1650 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1651 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1653 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1654 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1655 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1657 /* Reset the PCI FIFO of the async Tx queue */
1658 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1659 BMU_RST_SET | BMU_FIFO_RST);
1661 /* Reset the Tx prefetch units */
1662 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1665 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1669 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1670 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1672 sky2_phy_power(hw, port, 0);
1674 netif_carrier_off(dev);
1676 /* turn off LED's */
1677 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1679 synchronize_irq(hw->pdev->irq);
1682 sky2_rx_clean(sky2);
1684 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1685 sky2->rx_le, sky2->rx_le_map);
1686 kfree(sky2->rx_ring);
1688 pci_free_consistent(hw->pdev,
1689 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1690 sky2->tx_le, sky2->tx_le_map);
1691 kfree(sky2->tx_ring);
1696 sky2->rx_ring = NULL;
1697 sky2->tx_ring = NULL;
1702 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1704 if (hw->flags & SKY2_HW_FIBRE_PHY)
1707 if (hw->chip_id == CHIP_ID_YUKON_FE)
1708 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1710 switch (aux & PHY_M_PS_SPEED_MSK) {
1711 case PHY_M_PS_SPEED_1000:
1713 case PHY_M_PS_SPEED_100:
1720 static void sky2_link_up(struct sky2_port *sky2)
1722 struct sky2_hw *hw = sky2->hw;
1723 unsigned port = sky2->port;
1725 static const char *fc_name[] = {
1733 reg = gma_read16(hw, port, GM_GP_CTRL);
1734 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1735 gma_write16(hw, port, GM_GP_CTRL, reg);
1737 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1739 netif_carrier_on(sky2->netdev);
1741 if (hw->active++ == 0)
1742 mod_timer(&hw->watchdog_timer, jiffies + 1);
1745 /* Turn on link LED */
1746 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1747 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1749 if (hw->flags & SKY2_HW_NEWER_PHY) {
1750 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
1751 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1753 switch(sky2->speed) {
1755 led |= PHY_M_LEDC_INIT_CTRL(7);
1759 led |= PHY_M_LEDC_STA1_CTRL(7);
1763 led |= PHY_M_LEDC_STA0_CTRL(7);
1767 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
1768 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
1769 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1772 if (netif_msg_link(sky2))
1773 printk(KERN_INFO PFX
1774 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1775 sky2->netdev->name, sky2->speed,
1776 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1777 fc_name[sky2->flow_status]);
1780 static void sky2_link_down(struct sky2_port *sky2)
1782 struct sky2_hw *hw = sky2->hw;
1783 unsigned port = sky2->port;
1786 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1788 reg = gma_read16(hw, port, GM_GP_CTRL);
1789 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1790 gma_write16(hw, port, GM_GP_CTRL, reg);
1792 netif_carrier_off(sky2->netdev);
1794 /* Stop watchdog if both ports are not active */
1795 if (--hw->active == 0)
1796 del_timer(&hw->watchdog_timer);
1799 /* Turn on link LED */
1800 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1802 if (netif_msg_link(sky2))
1803 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1805 sky2_phy_init(hw, port);
1808 static enum flow_control sky2_flow(int rx, int tx)
1811 return tx ? FC_BOTH : FC_RX;
1813 return tx ? FC_TX : FC_NONE;
1816 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1818 struct sky2_hw *hw = sky2->hw;
1819 unsigned port = sky2->port;
1822 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
1823 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1824 if (lpa & PHY_M_AN_RF) {
1825 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1829 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1830 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1831 sky2->netdev->name);
1835 sky2->speed = sky2_phy_speed(hw, aux);
1836 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1838 /* Since the pause result bits seem to in different positions on
1839 * different chips. look at registers.
1841 if (hw->flags & SKY2_HW_FIBRE_PHY) {
1842 /* Shift for bits in fiber PHY */
1843 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
1844 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
1846 if (advert & ADVERTISE_1000XPAUSE)
1847 advert |= ADVERTISE_PAUSE_CAP;
1848 if (advert & ADVERTISE_1000XPSE_ASYM)
1849 advert |= ADVERTISE_PAUSE_ASYM;
1850 if (lpa & LPA_1000XPAUSE)
1851 lpa |= LPA_PAUSE_CAP;
1852 if (lpa & LPA_1000XPAUSE_ASYM)
1853 lpa |= LPA_PAUSE_ASYM;
1856 sky2->flow_status = FC_NONE;
1857 if (advert & ADVERTISE_PAUSE_CAP) {
1858 if (lpa & LPA_PAUSE_CAP)
1859 sky2->flow_status = FC_BOTH;
1860 else if (advert & ADVERTISE_PAUSE_ASYM)
1861 sky2->flow_status = FC_RX;
1862 } else if (advert & ADVERTISE_PAUSE_ASYM) {
1863 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
1864 sky2->flow_status = FC_TX;
1867 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
1868 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
1869 sky2->flow_status = FC_NONE;
1871 if (sky2->flow_status & FC_TX)
1872 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1874 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1879 /* Interrupt from PHY */
1880 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
1882 struct net_device *dev = hw->dev[port];
1883 struct sky2_port *sky2 = netdev_priv(dev);
1884 u16 istatus, phystat;
1886 if (!netif_running(dev))
1889 spin_lock(&sky2->phy_lock);
1890 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1891 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1893 if (netif_msg_intr(sky2))
1894 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1895 sky2->netdev->name, istatus, phystat);
1897 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
1898 if (sky2_autoneg_done(sky2, phystat) == 0)
1903 if (istatus & PHY_M_IS_LSP_CHANGE)
1904 sky2->speed = sky2_phy_speed(hw, phystat);
1906 if (istatus & PHY_M_IS_DUP_CHANGE)
1908 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1910 if (istatus & PHY_M_IS_LST_CHANGE) {
1911 if (phystat & PHY_M_PS_LINK_UP)
1914 sky2_link_down(sky2);
1917 spin_unlock(&sky2->phy_lock);
1920 /* Transmit timeout is only called if we are running, carrier is up
1921 * and tx queue is full (stopped).
1923 static void sky2_tx_timeout(struct net_device *dev)
1925 struct sky2_port *sky2 = netdev_priv(dev);
1926 struct sky2_hw *hw = sky2->hw;
1928 if (netif_msg_timer(sky2))
1929 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1931 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
1932 dev->name, sky2->tx_cons, sky2->tx_prod,
1933 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
1934 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
1936 /* can't restart safely under softirq */
1937 schedule_work(&hw->restart_work);
1940 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1942 struct sky2_port *sky2 = netdev_priv(dev);
1943 struct sky2_hw *hw = sky2->hw;
1944 unsigned port = sky2->port;
1949 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1952 if (new_mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_FE)
1955 if (!netif_running(dev)) {
1960 imask = sky2_read32(hw, B0_IMSK);
1961 sky2_write32(hw, B0_IMSK, 0);
1963 dev->trans_start = jiffies; /* prevent tx timeout */
1964 netif_stop_queue(dev);
1965 netif_poll_disable(hw->dev[0]);
1967 synchronize_irq(hw->pdev->irq);
1969 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX)
1970 sky2_set_tx_stfwd(hw, port);
1972 ctl = gma_read16(hw, port, GM_GP_CTRL);
1973 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1975 sky2_rx_clean(sky2);
1979 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1980 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1982 if (dev->mtu > ETH_DATA_LEN)
1983 mode |= GM_SMOD_JUMBO_ENA;
1985 gma_write16(hw, port, GM_SERIAL_MODE, mode);
1987 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
1989 err = sky2_rx_start(sky2);
1990 sky2_write32(hw, B0_IMSK, imask);
1995 gma_write16(hw, port, GM_GP_CTRL, ctl);
1997 netif_poll_enable(hw->dev[0]);
1998 netif_wake_queue(dev);
2004 /* For small just reuse existing skb for next receive */
2005 static struct sk_buff *receive_copy(struct sky2_port *sky2,
2006 const struct rx_ring_info *re,
2009 struct sk_buff *skb;
2011 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2013 skb_reserve(skb, 2);
2014 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2015 length, PCI_DMA_FROMDEVICE);
2016 skb_copy_from_linear_data(re->skb, skb->data, length);
2017 skb->ip_summed = re->skb->ip_summed;
2018 skb->csum = re->skb->csum;
2019 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2020 length, PCI_DMA_FROMDEVICE);
2021 re->skb->ip_summed = CHECKSUM_NONE;
2022 skb_put(skb, length);
2027 /* Adjust length of skb with fragments to match received data */
2028 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2029 unsigned int length)
2034 /* put header into skb */
2035 size = min(length, hdr_space);
2040 num_frags = skb_shinfo(skb)->nr_frags;
2041 for (i = 0; i < num_frags; i++) {
2042 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2045 /* don't need this page */
2046 __free_page(frag->page);
2047 --skb_shinfo(skb)->nr_frags;
2049 size = min(length, (unsigned) PAGE_SIZE);
2052 skb->data_len += size;
2053 skb->truesize += size;
2060 /* Normal packet - take skb from ring element and put in a new one */
2061 static struct sk_buff *receive_new(struct sky2_port *sky2,
2062 struct rx_ring_info *re,
2063 unsigned int length)
2065 struct sk_buff *skb, *nskb;
2066 unsigned hdr_space = sky2->rx_data_size;
2068 /* Don't be tricky about reusing pages (yet) */
2069 nskb = sky2_rx_alloc(sky2);
2070 if (unlikely(!nskb))
2074 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2076 prefetch(skb->data);
2078 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2080 if (skb_shinfo(skb)->nr_frags)
2081 skb_put_frags(skb, hdr_space, length);
2083 skb_put(skb, length);
2088 * Receive one packet.
2089 * For larger packets, get new buffer.
2091 static struct sk_buff *sky2_receive(struct net_device *dev,
2092 u16 length, u32 status)
2094 struct sky2_port *sky2 = netdev_priv(dev);
2095 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
2096 struct sk_buff *skb = NULL;
2097 u16 count = (status & GMR_FS_LEN) >> 16;
2099 #ifdef SKY2_VLAN_TAG_USED
2100 /* Account for vlan tag */
2101 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2105 if (unlikely(netif_msg_rx_status(sky2)))
2106 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
2107 dev->name, sky2->rx_next, status, length);
2109 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
2110 prefetch(sky2->rx_ring + sky2->rx_next);
2112 if (status & GMR_FS_ANY_ERR)
2115 if (!(status & GMR_FS_RX_OK))
2118 /* if length reported by DMA does not match PHY, packet was truncated */
2119 if (length != count)
2122 if (length < copybreak)
2123 skb = receive_copy(sky2, re, length);
2125 skb = receive_new(sky2, re, length);
2127 sky2_rx_submit(sky2, re);
2132 /* Truncation of overlength packets
2133 causes PHY length to not match MAC length */
2134 ++sky2->net_stats.rx_length_errors;
2135 if (netif_msg_rx_err(sky2) && net_ratelimit())
2136 pr_info(PFX "%s: rx length mismatch: length %d status %#x\n",
2137 dev->name, length, status);
2141 ++sky2->net_stats.rx_errors;
2142 if (status & GMR_FS_RX_FF_OV) {
2143 sky2->net_stats.rx_over_errors++;
2147 if (netif_msg_rx_err(sky2) && net_ratelimit())
2148 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
2149 dev->name, status, length);
2151 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
2152 sky2->net_stats.rx_length_errors++;
2153 if (status & GMR_FS_FRAGMENT)
2154 sky2->net_stats.rx_frame_errors++;
2155 if (status & GMR_FS_CRC_ERR)
2156 sky2->net_stats.rx_crc_errors++;
2161 /* Transmit complete */
2162 static inline void sky2_tx_done(struct net_device *dev, u16 last)
2164 struct sky2_port *sky2 = netdev_priv(dev);
2166 if (netif_running(dev)) {
2168 sky2_tx_complete(sky2, last);
2169 netif_tx_unlock(dev);
2173 /* Process status response ring */
2174 static int sky2_status_intr(struct sky2_hw *hw, int to_do)
2177 unsigned rx[2] = { 0, 0 };
2178 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
2182 while (hw->st_idx != hwidx) {
2183 struct sky2_port *sky2;
2184 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2185 unsigned port = le->css & CSS_LINK_BIT;
2186 struct net_device *dev;
2187 struct sk_buff *skb;
2191 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
2193 dev = hw->dev[port];
2194 sky2 = netdev_priv(dev);
2195 length = le16_to_cpu(le->length);
2196 status = le32_to_cpu(le->status);
2198 switch (le->opcode & ~HW_OWNER) {
2201 skb = sky2_receive(dev, length, status);
2202 if (unlikely(!skb)) {
2203 sky2->net_stats.rx_dropped++;
2207 /* This chip reports checksum status differently */
2208 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2209 if (sky2->rx_csum &&
2210 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2211 (le->css & CSS_TCPUDPCSOK))
2212 skb->ip_summed = CHECKSUM_UNNECESSARY;
2214 skb->ip_summed = CHECKSUM_NONE;
2217 skb->protocol = eth_type_trans(skb, dev);
2218 sky2->net_stats.rx_packets++;
2219 sky2->net_stats.rx_bytes += skb->len;
2220 dev->last_rx = jiffies;
2222 #ifdef SKY2_VLAN_TAG_USED
2223 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2224 vlan_hwaccel_receive_skb(skb,
2226 be16_to_cpu(sky2->rx_tag));
2229 netif_receive_skb(skb);
2231 /* Stop after net poll weight */
2232 if (++work_done >= to_do)
2236 #ifdef SKY2_VLAN_TAG_USED
2238 sky2->rx_tag = length;
2242 sky2->rx_tag = length;
2249 if (hw->chip_id == CHIP_ID_YUKON_EX)
2252 /* Both checksum counters are programmed to start at
2253 * the same offset, so unless there is a problem they
2254 * should match. This failure is an early indication that
2255 * hardware receive checksumming won't work.
2257 if (likely(status >> 16 == (status & 0xffff))) {
2258 skb = sky2->rx_ring[sky2->rx_next].skb;
2259 skb->ip_summed = CHECKSUM_COMPLETE;
2260 skb->csum = status & 0xffff;
2262 printk(KERN_NOTICE PFX "%s: hardware receive "
2263 "checksum problem (status = %#x)\n",
2266 sky2_write32(sky2->hw,
2267 Q_ADDR(rxqaddr[port], Q_CSR),
2273 /* TX index reports status for both ports */
2274 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2275 sky2_tx_done(hw->dev[0], status & 0xfff);
2277 sky2_tx_done(hw->dev[1],
2278 ((status >> 24) & 0xff)
2279 | (u16)(length & 0xf) << 8);
2283 if (net_ratelimit())
2284 printk(KERN_WARNING PFX
2285 "unknown status opcode 0x%x\n", le->opcode);
2289 /* Fully processed status ring so clear irq */
2290 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2294 sky2_rx_update(netdev_priv(hw->dev[0]), Q_R1);
2297 sky2_rx_update(netdev_priv(hw->dev[1]), Q_R2);
2302 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2304 struct net_device *dev = hw->dev[port];
2306 if (net_ratelimit())
2307 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2310 if (status & Y2_IS_PAR_RD1) {
2311 if (net_ratelimit())
2312 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2315 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2318 if (status & Y2_IS_PAR_WR1) {
2319 if (net_ratelimit())
2320 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2323 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2326 if (status & Y2_IS_PAR_MAC1) {
2327 if (net_ratelimit())
2328 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
2329 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2332 if (status & Y2_IS_PAR_RX1) {
2333 if (net_ratelimit())
2334 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
2335 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2338 if (status & Y2_IS_TCP_TXA1) {
2339 if (net_ratelimit())
2340 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2342 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2346 static void sky2_hw_intr(struct sky2_hw *hw)
2348 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2350 if (status & Y2_IS_TIST_OV)
2351 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2353 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2356 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2357 if (net_ratelimit())
2358 dev_err(&hw->pdev->dev, "PCI hardware error (0x%x)\n",
2361 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2362 sky2_pci_write16(hw, PCI_STATUS,
2363 pci_err | PCI_STATUS_ERROR_BITS);
2364 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2367 if (status & Y2_IS_PCI_EXP) {
2368 /* PCI-Express uncorrectable Error occurred */
2371 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
2373 if (net_ratelimit())
2374 dev_err(&hw->pdev->dev, "PCI Express error (0x%x)\n",
2377 /* clear the interrupt */
2378 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2379 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
2381 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2383 if (pex_err & PEX_FATAL_ERRORS) {
2384 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2385 hwmsk &= ~Y2_IS_PCI_EXP;
2386 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2390 if (status & Y2_HWE_L1_MASK)
2391 sky2_hw_error(hw, 0, status);
2393 if (status & Y2_HWE_L1_MASK)
2394 sky2_hw_error(hw, 1, status);
2397 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2399 struct net_device *dev = hw->dev[port];
2400 struct sky2_port *sky2 = netdev_priv(dev);
2401 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2403 if (netif_msg_intr(sky2))
2404 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2407 if (status & GM_IS_RX_CO_OV)
2408 gma_read16(hw, port, GM_RX_IRQ_SRC);
2410 if (status & GM_IS_TX_CO_OV)
2411 gma_read16(hw, port, GM_TX_IRQ_SRC);
2413 if (status & GM_IS_RX_FF_OR) {
2414 ++sky2->net_stats.rx_fifo_errors;
2415 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2418 if (status & GM_IS_TX_FF_UR) {
2419 ++sky2->net_stats.tx_fifo_errors;
2420 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2424 /* This should never happen it is a bug. */
2425 static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2426 u16 q, unsigned ring_size)
2428 struct net_device *dev = hw->dev[port];
2429 struct sky2_port *sky2 = netdev_priv(dev);
2431 const u64 *le = (q == Q_R1 || q == Q_R2)
2432 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
2434 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2435 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2436 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2437 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
2439 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
2442 /* Check for lost IRQ once a second */
2443 static void sky2_watchdog(unsigned long arg)
2445 struct sky2_hw *hw = (struct sky2_hw *) arg;
2447 if (sky2_read32(hw, B0_ISRC)) {
2448 struct net_device *dev = hw->dev[0];
2450 if (__netif_rx_schedule_prep(dev))
2451 __netif_rx_schedule(dev);
2455 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
2458 /* Hardware/software error handling */
2459 static void sky2_err_intr(struct sky2_hw *hw, u32 status)
2461 if (net_ratelimit())
2462 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
2464 if (status & Y2_IS_HW_ERR)
2467 if (status & Y2_IS_IRQ_MAC1)
2468 sky2_mac_intr(hw, 0);
2470 if (status & Y2_IS_IRQ_MAC2)
2471 sky2_mac_intr(hw, 1);
2473 if (status & Y2_IS_CHK_RX1)
2474 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
2476 if (status & Y2_IS_CHK_RX2)
2477 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
2479 if (status & Y2_IS_CHK_TXA1)
2480 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
2482 if (status & Y2_IS_CHK_TXA2)
2483 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2486 static int sky2_poll(struct net_device *dev0, int *budget)
2488 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
2490 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2492 if (unlikely(status & Y2_IS_ERROR))
2493 sky2_err_intr(hw, status);
2495 if (status & Y2_IS_IRQ_PHY1)
2496 sky2_phy_intr(hw, 0);
2498 if (status & Y2_IS_IRQ_PHY2)
2499 sky2_phy_intr(hw, 1);
2501 work_done = sky2_status_intr(hw, min(dev0->quota, *budget));
2502 *budget -= work_done;
2503 dev0->quota -= work_done;
2506 if (hw->st_idx != sky2_read16(hw, STAT_PUT_IDX))
2509 /* Bug/Errata workaround?
2510 * Need to kick the TX irq moderation timer.
2512 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) {
2513 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2514 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2516 netif_rx_complete(dev0);
2518 sky2_read32(hw, B0_Y2_SP_LISR);
2522 static irqreturn_t sky2_intr(int irq, void *dev_id)
2524 struct sky2_hw *hw = dev_id;
2525 struct net_device *dev0 = hw->dev[0];
2528 /* Reading this mask interrupts as side effect */
2529 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2530 if (status == 0 || status == ~0)
2533 prefetch(&hw->st_le[hw->st_idx]);
2534 if (likely(__netif_rx_schedule_prep(dev0)))
2535 __netif_rx_schedule(dev0);
2540 #ifdef CONFIG_NET_POLL_CONTROLLER
2541 static void sky2_netpoll(struct net_device *dev)
2543 struct sky2_port *sky2 = netdev_priv(dev);
2544 struct net_device *dev0 = sky2->hw->dev[0];
2546 if (netif_running(dev) && __netif_rx_schedule_prep(dev0))
2547 __netif_rx_schedule(dev0);
2551 /* Chip internal frequency for clock calculations */
2552 static inline u32 sky2_mhz(const struct sky2_hw *hw)
2554 switch (hw->chip_id) {
2555 case CHIP_ID_YUKON_EC:
2556 case CHIP_ID_YUKON_EC_U:
2557 case CHIP_ID_YUKON_EX:
2558 return 125; /* 125 Mhz */
2559 case CHIP_ID_YUKON_FE:
2560 return 100; /* 100 Mhz */
2561 default: /* YUKON_XL */
2562 return 156; /* 156 Mhz */
2566 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2568 return sky2_mhz(hw) * us;
2571 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2573 return clk / sky2_mhz(hw);
2577 static int __devinit sky2_init(struct sky2_hw *hw)
2581 /* Enable all clocks */
2582 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2584 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2586 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2587 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2589 switch(hw->chip_id) {
2590 case CHIP_ID_YUKON_XL:
2591 hw->flags = SKY2_HW_GIGABIT
2593 | SKY2_HW_RAMBUFFER;
2596 case CHIP_ID_YUKON_EC_U:
2597 hw->flags = SKY2_HW_GIGABIT
2599 | SKY2_HW_ADV_POWER_CTL;
2602 case CHIP_ID_YUKON_EX:
2603 hw->flags = SKY2_HW_GIGABIT
2606 | SKY2_HW_ADV_POWER_CTL;
2608 /* New transmit checksum */
2609 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2610 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2613 case CHIP_ID_YUKON_EC:
2614 /* This rev is really old, and requires untested workarounds */
2615 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2616 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2619 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_RAMBUFFER;
2622 case CHIP_ID_YUKON_FE:
2623 hw->flags = SKY2_HW_RAMBUFFER;
2627 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2632 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2633 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2634 hw->flags |= SKY2_HW_FIBRE_PHY;
2638 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2639 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2640 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2647 static void sky2_reset(struct sky2_hw *hw)
2653 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2654 status = sky2_read16(hw, HCU_CCSR);
2655 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2656 HCU_CCSR_UC_STATE_MSK);
2657 sky2_write16(hw, HCU_CCSR, status);
2659 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2660 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2663 sky2_write8(hw, B0_CTST, CS_RST_SET);
2664 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2666 /* clear PCI errors, if any */
2667 status = sky2_pci_read16(hw, PCI_STATUS);
2669 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2670 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2673 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2675 /* clear any PEX errors */
2676 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2677 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2682 for (i = 0; i < hw->ports; i++) {
2683 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2684 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2686 if (hw->chip_id == CHIP_ID_YUKON_EX)
2687 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
2688 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
2692 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2694 /* Clear I2C IRQ noise */
2695 sky2_write32(hw, B2_I2C_IRQ, 1);
2697 /* turn off hardware timer (unused) */
2698 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2699 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2701 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2703 /* Turn off descriptor polling */
2704 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
2706 /* Turn off receive timestamp */
2707 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
2708 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2710 /* enable the Tx Arbiters */
2711 for (i = 0; i < hw->ports; i++)
2712 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2714 /* Initialize ram interface */
2715 for (i = 0; i < hw->ports; i++) {
2716 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
2718 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2719 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2720 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2721 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2722 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2723 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2724 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2725 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2726 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2727 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2728 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2729 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2732 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2734 for (i = 0; i < hw->ports; i++)
2735 sky2_gmac_reset(hw, i);
2737 memset(hw->st_le, 0, STATUS_LE_BYTES);
2740 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2741 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2743 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
2744 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
2746 /* Set the list last index */
2747 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
2749 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2750 sky2_write8(hw, STAT_FIFO_WM, 16);
2752 /* set Status-FIFO ISR watermark */
2753 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2754 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2756 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
2758 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
2759 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2760 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
2762 /* enable status unit */
2763 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2765 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2766 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2767 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2770 static void sky2_restart(struct work_struct *work)
2772 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
2773 struct net_device *dev;
2777 sky2_write32(hw, B0_IMSK, 0);
2778 sky2_read32(hw, B0_IMSK);
2780 netif_poll_disable(hw->dev[0]);
2782 for (i = 0; i < hw->ports; i++) {
2784 if (netif_running(dev))
2789 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
2790 netif_poll_enable(hw->dev[0]);
2792 for (i = 0; i < hw->ports; i++) {
2794 if (netif_running(dev)) {
2797 printk(KERN_INFO PFX "%s: could not restart %d\n",
2807 static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
2809 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
2812 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2814 const struct sky2_port *sky2 = netdev_priv(dev);
2816 wol->supported = sky2_wol_supported(sky2->hw);
2817 wol->wolopts = sky2->wol;
2820 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2822 struct sky2_port *sky2 = netdev_priv(dev);
2823 struct sky2_hw *hw = sky2->hw;
2825 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
2828 sky2->wol = wol->wolopts;
2830 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX)
2831 sky2_write32(hw, B0_CTST, sky2->wol
2832 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
2834 if (!netif_running(dev))
2835 sky2_wol_init(sky2);
2839 static u32 sky2_supported_modes(const struct sky2_hw *hw)
2841 if (sky2_is_copper(hw)) {
2842 u32 modes = SUPPORTED_10baseT_Half
2843 | SUPPORTED_10baseT_Full
2844 | SUPPORTED_100baseT_Half
2845 | SUPPORTED_100baseT_Full
2846 | SUPPORTED_Autoneg | SUPPORTED_TP;
2848 if (hw->flags & SKY2_HW_GIGABIT)
2849 modes |= SUPPORTED_1000baseT_Half
2850 | SUPPORTED_1000baseT_Full;
2853 return SUPPORTED_1000baseT_Half
2854 | SUPPORTED_1000baseT_Full
2859 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2861 struct sky2_port *sky2 = netdev_priv(dev);
2862 struct sky2_hw *hw = sky2->hw;
2864 ecmd->transceiver = XCVR_INTERNAL;
2865 ecmd->supported = sky2_supported_modes(hw);
2866 ecmd->phy_address = PHY_ADDR_MARV;
2867 if (sky2_is_copper(hw)) {
2868 ecmd->port = PORT_TP;
2869 ecmd->speed = sky2->speed;
2871 ecmd->speed = SPEED_1000;
2872 ecmd->port = PORT_FIBRE;
2875 ecmd->advertising = sky2->advertising;
2876 ecmd->autoneg = sky2->autoneg;
2877 ecmd->duplex = sky2->duplex;
2881 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2883 struct sky2_port *sky2 = netdev_priv(dev);
2884 const struct sky2_hw *hw = sky2->hw;
2885 u32 supported = sky2_supported_modes(hw);
2887 if (ecmd->autoneg == AUTONEG_ENABLE) {
2888 ecmd->advertising = supported;
2894 switch (ecmd->speed) {
2896 if (ecmd->duplex == DUPLEX_FULL)
2897 setting = SUPPORTED_1000baseT_Full;
2898 else if (ecmd->duplex == DUPLEX_HALF)
2899 setting = SUPPORTED_1000baseT_Half;
2904 if (ecmd->duplex == DUPLEX_FULL)
2905 setting = SUPPORTED_100baseT_Full;
2906 else if (ecmd->duplex == DUPLEX_HALF)
2907 setting = SUPPORTED_100baseT_Half;
2913 if (ecmd->duplex == DUPLEX_FULL)
2914 setting = SUPPORTED_10baseT_Full;
2915 else if (ecmd->duplex == DUPLEX_HALF)
2916 setting = SUPPORTED_10baseT_Half;
2924 if ((setting & supported) == 0)
2927 sky2->speed = ecmd->speed;
2928 sky2->duplex = ecmd->duplex;
2931 sky2->autoneg = ecmd->autoneg;
2932 sky2->advertising = ecmd->advertising;
2934 if (netif_running(dev)) {
2935 sky2_phy_reinit(sky2);
2936 sky2_set_multicast(dev);
2942 static void sky2_get_drvinfo(struct net_device *dev,
2943 struct ethtool_drvinfo *info)
2945 struct sky2_port *sky2 = netdev_priv(dev);
2947 strcpy(info->driver, DRV_NAME);
2948 strcpy(info->version, DRV_VERSION);
2949 strcpy(info->fw_version, "N/A");
2950 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2953 static const struct sky2_stat {
2954 char name[ETH_GSTRING_LEN];
2957 { "tx_bytes", GM_TXO_OK_HI },
2958 { "rx_bytes", GM_RXO_OK_HI },
2959 { "tx_broadcast", GM_TXF_BC_OK },
2960 { "rx_broadcast", GM_RXF_BC_OK },
2961 { "tx_multicast", GM_TXF_MC_OK },
2962 { "rx_multicast", GM_RXF_MC_OK },
2963 { "tx_unicast", GM_TXF_UC_OK },
2964 { "rx_unicast", GM_RXF_UC_OK },
2965 { "tx_mac_pause", GM_TXF_MPAUSE },
2966 { "rx_mac_pause", GM_RXF_MPAUSE },
2967 { "collisions", GM_TXF_COL },
2968 { "late_collision",GM_TXF_LAT_COL },
2969 { "aborted", GM_TXF_ABO_COL },
2970 { "single_collisions", GM_TXF_SNG_COL },
2971 { "multi_collisions", GM_TXF_MUL_COL },
2973 { "rx_short", GM_RXF_SHT },
2974 { "rx_runt", GM_RXE_FRAG },
2975 { "rx_64_byte_packets", GM_RXF_64B },
2976 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2977 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2978 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2979 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2980 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2981 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
2982 { "rx_too_long", GM_RXF_LNG_ERR },
2983 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2984 { "rx_jabber", GM_RXF_JAB_PKT },
2985 { "rx_fcs_error", GM_RXF_FCS_ERR },
2987 { "tx_64_byte_packets", GM_TXF_64B },
2988 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2989 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2990 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2991 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2992 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2993 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2994 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
2997 static u32 sky2_get_rx_csum(struct net_device *dev)
2999 struct sky2_port *sky2 = netdev_priv(dev);
3001 return sky2->rx_csum;
3004 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3006 struct sky2_port *sky2 = netdev_priv(dev);
3008 sky2->rx_csum = data;
3010 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3011 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3016 static u32 sky2_get_msglevel(struct net_device *netdev)
3018 struct sky2_port *sky2 = netdev_priv(netdev);
3019 return sky2->msg_enable;
3022 static int sky2_nway_reset(struct net_device *dev)
3024 struct sky2_port *sky2 = netdev_priv(dev);
3026 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
3029 sky2_phy_reinit(sky2);
3030 sky2_set_multicast(dev);
3035 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
3037 struct sky2_hw *hw = sky2->hw;
3038 unsigned port = sky2->port;
3041 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
3042 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
3043 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
3044 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
3046 for (i = 2; i < count; i++)
3047 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3050 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3052 struct sky2_port *sky2 = netdev_priv(netdev);
3053 sky2->msg_enable = value;
3056 static int sky2_get_stats_count(struct net_device *dev)
3058 return ARRAY_SIZE(sky2_stats);
3061 static void sky2_get_ethtool_stats(struct net_device *dev,
3062 struct ethtool_stats *stats, u64 * data)
3064 struct sky2_port *sky2 = netdev_priv(dev);
3066 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
3069 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
3073 switch (stringset) {
3075 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3076 memcpy(data + i * ETH_GSTRING_LEN,
3077 sky2_stats[i].name, ETH_GSTRING_LEN);
3082 static struct net_device_stats *sky2_get_stats(struct net_device *dev)
3084 struct sky2_port *sky2 = netdev_priv(dev);
3085 return &sky2->net_stats;
3088 static int sky2_set_mac_address(struct net_device *dev, void *p)
3090 struct sky2_port *sky2 = netdev_priv(dev);
3091 struct sky2_hw *hw = sky2->hw;
3092 unsigned port = sky2->port;
3093 const struct sockaddr *addr = p;
3095 if (!is_valid_ether_addr(addr->sa_data))
3096 return -EADDRNOTAVAIL;
3098 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3099 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
3100 dev->dev_addr, ETH_ALEN);
3101 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
3102 dev->dev_addr, ETH_ALEN);
3104 /* virtual address for data */
3105 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3107 /* physical address: used for pause frames */
3108 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3113 static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3117 bit = ether_crc(ETH_ALEN, addr) & 63;
3118 filter[bit >> 3] |= 1 << (bit & 7);
3121 static void sky2_set_multicast(struct net_device *dev)
3123 struct sky2_port *sky2 = netdev_priv(dev);
3124 struct sky2_hw *hw = sky2->hw;
3125 unsigned port = sky2->port;
3126 struct dev_mc_list *list = dev->mc_list;
3130 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3132 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
3133 memset(filter, 0, sizeof(filter));
3135 reg = gma_read16(hw, port, GM_RX_CTRL);
3136 reg |= GM_RXCR_UCF_ENA;
3138 if (dev->flags & IFF_PROMISC) /* promiscuous */
3139 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3140 else if (dev->flags & IFF_ALLMULTI)
3141 memset(filter, 0xff, sizeof(filter));
3142 else if (dev->mc_count == 0 && !rx_pause)
3143 reg &= ~GM_RXCR_MCF_ENA;
3146 reg |= GM_RXCR_MCF_ENA;
3149 sky2_add_filter(filter, pause_mc_addr);
3151 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3152 sky2_add_filter(filter, list->dmi_addr);
3155 gma_write16(hw, port, GM_MC_ADDR_H1,
3156 (u16) filter[0] | ((u16) filter[1] << 8));
3157 gma_write16(hw, port, GM_MC_ADDR_H2,
3158 (u16) filter[2] | ((u16) filter[3] << 8));
3159 gma_write16(hw, port, GM_MC_ADDR_H3,
3160 (u16) filter[4] | ((u16) filter[5] << 8));
3161 gma_write16(hw, port, GM_MC_ADDR_H4,
3162 (u16) filter[6] | ((u16) filter[7] << 8));
3164 gma_write16(hw, port, GM_RX_CTRL, reg);
3167 /* Can have one global because blinking is controlled by
3168 * ethtool and that is always under RTNL mutex
3170 static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
3174 switch (hw->chip_id) {
3175 case CHIP_ID_YUKON_XL:
3176 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3177 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3178 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3179 on ? (PHY_M_LEDC_LOS_CTRL(1) |
3180 PHY_M_LEDC_INIT_CTRL(7) |
3181 PHY_M_LEDC_STA1_CTRL(7) |
3182 PHY_M_LEDC_STA0_CTRL(7))
3185 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3189 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
3190 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3191 on ? PHY_M_LED_ALL : 0);
3195 /* blink LED's for finding board */
3196 static int sky2_phys_id(struct net_device *dev, u32 data)
3198 struct sky2_port *sky2 = netdev_priv(dev);
3199 struct sky2_hw *hw = sky2->hw;
3200 unsigned port = sky2->port;
3201 u16 ledctrl, ledover = 0;
3206 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
3207 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
3211 /* save initial values */
3212 spin_lock_bh(&sky2->phy_lock);
3213 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3214 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3215 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3216 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
3217 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3219 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
3220 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
3224 while (!interrupted && ms > 0) {
3225 sky2_led(hw, port, onoff);
3228 spin_unlock_bh(&sky2->phy_lock);
3229 interrupted = msleep_interruptible(250);
3230 spin_lock_bh(&sky2->phy_lock);
3235 /* resume regularly scheduled programming */
3236 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3237 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3238 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3239 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
3240 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3242 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
3243 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
3245 spin_unlock_bh(&sky2->phy_lock);
3250 static void sky2_get_pauseparam(struct net_device *dev,
3251 struct ethtool_pauseparam *ecmd)
3253 struct sky2_port *sky2 = netdev_priv(dev);
3255 switch (sky2->flow_mode) {
3257 ecmd->tx_pause = ecmd->rx_pause = 0;
3260 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3263 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3266 ecmd->tx_pause = ecmd->rx_pause = 1;
3269 ecmd->autoneg = sky2->autoneg;
3272 static int sky2_set_pauseparam(struct net_device *dev,
3273 struct ethtool_pauseparam *ecmd)
3275 struct sky2_port *sky2 = netdev_priv(dev);
3277 sky2->autoneg = ecmd->autoneg;
3278 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
3280 if (netif_running(dev))
3281 sky2_phy_reinit(sky2);
3286 static int sky2_get_coalesce(struct net_device *dev,
3287 struct ethtool_coalesce *ecmd)
3289 struct sky2_port *sky2 = netdev_priv(dev);
3290 struct sky2_hw *hw = sky2->hw;
3292 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3293 ecmd->tx_coalesce_usecs = 0;
3295 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3296 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3298 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3300 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3301 ecmd->rx_coalesce_usecs = 0;
3303 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3304 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3306 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3308 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3309 ecmd->rx_coalesce_usecs_irq = 0;
3311 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3312 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3315 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3320 /* Note: this affect both ports */
3321 static int sky2_set_coalesce(struct net_device *dev,
3322 struct ethtool_coalesce *ecmd)
3324 struct sky2_port *sky2 = netdev_priv(dev);
3325 struct sky2_hw *hw = sky2->hw;
3326 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
3328 if (ecmd->tx_coalesce_usecs > tmax ||
3329 ecmd->rx_coalesce_usecs > tmax ||
3330 ecmd->rx_coalesce_usecs_irq > tmax)
3333 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
3335 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
3337 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
3340 if (ecmd->tx_coalesce_usecs == 0)
3341 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3343 sky2_write32(hw, STAT_TX_TIMER_INI,
3344 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3345 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3347 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3349 if (ecmd->rx_coalesce_usecs == 0)
3350 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3352 sky2_write32(hw, STAT_LEV_TIMER_INI,
3353 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3354 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3356 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3358 if (ecmd->rx_coalesce_usecs_irq == 0)
3359 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3361 sky2_write32(hw, STAT_ISR_TIMER_INI,
3362 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3363 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3365 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3369 static void sky2_get_ringparam(struct net_device *dev,
3370 struct ethtool_ringparam *ering)
3372 struct sky2_port *sky2 = netdev_priv(dev);
3374 ering->rx_max_pending = RX_MAX_PENDING;
3375 ering->rx_mini_max_pending = 0;
3376 ering->rx_jumbo_max_pending = 0;
3377 ering->tx_max_pending = TX_RING_SIZE - 1;
3379 ering->rx_pending = sky2->rx_pending;
3380 ering->rx_mini_pending = 0;
3381 ering->rx_jumbo_pending = 0;
3382 ering->tx_pending = sky2->tx_pending;
3385 static int sky2_set_ringparam(struct net_device *dev,
3386 struct ethtool_ringparam *ering)
3388 struct sky2_port *sky2 = netdev_priv(dev);
3391 if (ering->rx_pending > RX_MAX_PENDING ||
3392 ering->rx_pending < 8 ||
3393 ering->tx_pending < MAX_SKB_TX_LE ||
3394 ering->tx_pending > TX_RING_SIZE - 1)
3397 if (netif_running(dev))
3400 sky2->rx_pending = ering->rx_pending;
3401 sky2->tx_pending = ering->tx_pending;
3403 if (netif_running(dev)) {
3408 sky2_set_multicast(dev);
3414 static int sky2_get_regs_len(struct net_device *dev)
3420 * Returns copy of control register region
3421 * Note: ethtool_get_regs always provides full size (16k) buffer
3423 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3426 const struct sky2_port *sky2 = netdev_priv(dev);
3427 const void __iomem *io = sky2->hw->regs;
3430 memset(p, 0, regs->len);
3432 memcpy_fromio(p, io, B3_RAM_ADDR);
3434 /* skip diagnostic ram region */
3435 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1, 0x2000 - B3_RI_WTO_R1);
3437 /* copy GMAC registers */
3438 memcpy_fromio(p + BASE_GMAC_1, io + BASE_GMAC_1, 0x1000);
3439 if (sky2->hw->ports > 1)
3440 memcpy_fromio(p + BASE_GMAC_2, io + BASE_GMAC_2, 0x1000);
3444 /* In order to do Jumbo packets on these chips, need to turn off the
3445 * transmit store/forward. Therefore checksum offload won't work.
3447 static int no_tx_offload(struct net_device *dev)
3449 const struct sky2_port *sky2 = netdev_priv(dev);
3450 const struct sky2_hw *hw = sky2->hw;
3452 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
3455 static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3457 if (data && no_tx_offload(dev))
3460 return ethtool_op_set_tx_csum(dev, data);
3464 static int sky2_set_tso(struct net_device *dev, u32 data)
3466 if (data && no_tx_offload(dev))
3469 return ethtool_op_set_tso(dev, data);
3472 static int sky2_get_eeprom_len(struct net_device *dev)
3474 struct sky2_port *sky2 = netdev_priv(dev);
3477 reg2 = sky2_pci_read32(sky2->hw, PCI_DEV_REG2);
3478 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3481 static u32 sky2_vpd_read(struct sky2_hw *hw, int cap, u16 offset)
3483 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
3485 while (!(sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F))
3487 return sky2_pci_read32(hw, cap + PCI_VPD_DATA);
3490 static void sky2_vpd_write(struct sky2_hw *hw, int cap, u16 offset, u32 val)
3492 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
3493 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
3496 } while (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F);
3499 static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3502 struct sky2_port *sky2 = netdev_priv(dev);
3503 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3504 int length = eeprom->len;
3505 u16 offset = eeprom->offset;
3510 eeprom->magic = SKY2_EEPROM_MAGIC;
3512 while (length > 0) {
3513 u32 val = sky2_vpd_read(sky2->hw, cap, offset);
3514 int n = min_t(int, length, sizeof(val));
3516 memcpy(data, &val, n);
3524 static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3527 struct sky2_port *sky2 = netdev_priv(dev);
3528 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3529 int length = eeprom->len;
3530 u16 offset = eeprom->offset;
3535 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3538 while (length > 0) {
3540 int n = min_t(int, length, sizeof(val));
3542 if (n < sizeof(val))
3543 val = sky2_vpd_read(sky2->hw, cap, offset);
3544 memcpy(&val, data, n);
3546 sky2_vpd_write(sky2->hw, cap, offset, val);
3556 static const struct ethtool_ops sky2_ethtool_ops = {
3557 .get_settings = sky2_get_settings,
3558 .set_settings = sky2_set_settings,
3559 .get_drvinfo = sky2_get_drvinfo,
3560 .get_wol = sky2_get_wol,
3561 .set_wol = sky2_set_wol,
3562 .get_msglevel = sky2_get_msglevel,
3563 .set_msglevel = sky2_set_msglevel,
3564 .nway_reset = sky2_nway_reset,
3565 .get_regs_len = sky2_get_regs_len,
3566 .get_regs = sky2_get_regs,
3567 .get_link = ethtool_op_get_link,
3568 .get_eeprom_len = sky2_get_eeprom_len,
3569 .get_eeprom = sky2_get_eeprom,
3570 .set_eeprom = sky2_set_eeprom,
3571 .get_sg = ethtool_op_get_sg,
3572 .set_sg = ethtool_op_set_sg,
3573 .get_tx_csum = ethtool_op_get_tx_csum,
3574 .set_tx_csum = sky2_set_tx_csum,
3575 .get_tso = ethtool_op_get_tso,
3576 .set_tso = sky2_set_tso,
3577 .get_rx_csum = sky2_get_rx_csum,
3578 .set_rx_csum = sky2_set_rx_csum,
3579 .get_strings = sky2_get_strings,
3580 .get_coalesce = sky2_get_coalesce,
3581 .set_coalesce = sky2_set_coalesce,
3582 .get_ringparam = sky2_get_ringparam,
3583 .set_ringparam = sky2_set_ringparam,
3584 .get_pauseparam = sky2_get_pauseparam,
3585 .set_pauseparam = sky2_set_pauseparam,
3586 .phys_id = sky2_phys_id,
3587 .get_stats_count = sky2_get_stats_count,
3588 .get_ethtool_stats = sky2_get_ethtool_stats,
3591 #ifdef CONFIG_SKY2_DEBUG
3593 static struct dentry *sky2_debug;
3595 static int sky2_debug_show(struct seq_file *seq, void *v)
3597 struct net_device *dev = seq->private;
3598 const struct sky2_port *sky2 = netdev_priv(dev);
3599 const struct sky2_hw *hw = sky2->hw;
3600 unsigned port = sky2->port;
3604 if (!netif_running(dev))
3607 seq_printf(seq, "IRQ src=%x mask=%x control=%x\n",
3608 sky2_read32(hw, B0_ISRC),
3609 sky2_read32(hw, B0_IMSK),
3610 sky2_read32(hw, B0_Y2_SP_ICR));
3612 netif_poll_disable(hw->dev[0]);
3613 last = sky2_read16(hw, STAT_PUT_IDX);
3615 if (hw->st_idx == last)
3616 seq_puts(seq, "Status ring (empty)\n");
3618 seq_puts(seq, "Status ring\n");
3619 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
3620 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
3621 const struct sky2_status_le *le = hw->st_le + idx;
3622 seq_printf(seq, "[%d] %#x %d %#x\n",
3623 idx, le->opcode, le->length, le->status);
3625 seq_puts(seq, "\n");
3628 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
3629 sky2->tx_cons, sky2->tx_prod,
3630 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
3631 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
3633 /* Dump contents of tx ring */
3635 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < TX_RING_SIZE;
3636 idx = RING_NEXT(idx, TX_RING_SIZE)) {
3637 const struct sky2_tx_le *le = sky2->tx_le + idx;
3638 u32 a = le32_to_cpu(le->addr);
3641 seq_printf(seq, "%u:", idx);
3644 switch(le->opcode & ~HW_OWNER) {
3646 seq_printf(seq, " %#x:", a);
3649 seq_printf(seq, " mtu=%d", a);
3652 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
3655 seq_printf(seq, " csum=%#x", a);
3658 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
3661 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
3664 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
3667 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
3668 a, le16_to_cpu(le->length));
3671 if (le->ctrl & EOP) {
3672 seq_putc(seq, '\n');
3677 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
3678 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
3679 last = sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3680 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
3682 netif_poll_enable(hw->dev[0]);
3686 static int sky2_debug_open(struct inode *inode, struct file *file)
3688 return single_open(file, sky2_debug_show, inode->i_private);
3691 static const struct file_operations sky2_debug_fops = {
3692 .owner = THIS_MODULE,
3693 .open = sky2_debug_open,
3695 .llseek = seq_lseek,
3696 .release = single_release,
3700 * Use network device events to create/remove/rename
3701 * debugfs file entries
3703 static int sky2_device_event(struct notifier_block *unused,
3704 unsigned long event, void *ptr)
3706 struct net_device *dev = ptr;
3708 if (dev->open == sky2_up) {
3709 struct sky2_port *sky2 = netdev_priv(dev);
3712 case NETDEV_CHANGENAME:
3713 if (!netif_running(dev))
3717 case NETDEV_GOING_DOWN:
3718 if (sky2->debugfs) {
3719 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
3721 debugfs_remove(sky2->debugfs);
3722 sky2->debugfs = NULL;
3725 if (event != NETDEV_CHANGENAME)
3727 /* fallthrough for changename */
3731 d = debugfs_create_file(dev->name, S_IRUGO,
3734 if (d == NULL || IS_ERR(d))
3735 printk(KERN_INFO PFX
3736 "%s: debugfs create failed\n",
3748 static struct notifier_block sky2_notifier = {
3749 .notifier_call = sky2_device_event,
3753 static __init void sky2_debug_init(void)
3757 ent = debugfs_create_dir("sky2", NULL);
3758 if (!ent || IS_ERR(ent))
3762 register_netdevice_notifier(&sky2_notifier);
3765 static __exit void sky2_debug_cleanup(void)
3768 unregister_netdevice_notifier(&sky2_notifier);
3769 debugfs_remove(sky2_debug);
3775 #define sky2_debug_init()
3776 #define sky2_debug_cleanup()
3780 /* Initialize network device */
3781 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3783 int highmem, int wol)
3785 struct sky2_port *sky2;
3786 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3789 dev_err(&hw->pdev->dev, "etherdev alloc failed");
3793 SET_MODULE_OWNER(dev);
3794 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3795 dev->irq = hw->pdev->irq;
3796 dev->open = sky2_up;
3797 dev->stop = sky2_down;
3798 dev->do_ioctl = sky2_ioctl;
3799 dev->hard_start_xmit = sky2_xmit_frame;
3800 dev->get_stats = sky2_get_stats;
3801 dev->set_multicast_list = sky2_set_multicast;
3802 dev->set_mac_address = sky2_set_mac_address;
3803 dev->change_mtu = sky2_change_mtu;
3804 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3805 dev->tx_timeout = sky2_tx_timeout;
3806 dev->watchdog_timeo = TX_WATCHDOG;
3808 dev->poll = sky2_poll;
3809 dev->weight = NAPI_WEIGHT;
3810 #ifdef CONFIG_NET_POLL_CONTROLLER
3811 /* Network console (only works on port 0)
3812 * because netpoll makes assumptions about NAPI
3815 dev->poll_controller = sky2_netpoll;
3818 sky2 = netdev_priv(dev);
3821 sky2->msg_enable = netif_msg_init(debug, default_msg);
3823 /* Auto speed and flow control */
3824 sky2->autoneg = AUTONEG_ENABLE;
3825 sky2->flow_mode = FC_BOTH;
3829 sky2->advertising = sky2_supported_modes(hw);
3833 spin_lock_init(&sky2->phy_lock);
3834 sky2->tx_pending = TX_DEF_PENDING;
3835 sky2->rx_pending = RX_DEF_PENDING;
3837 hw->dev[port] = dev;
3841 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
3843 dev->features |= NETIF_F_HIGHDMA;
3845 #ifdef SKY2_VLAN_TAG_USED
3846 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3847 dev->vlan_rx_register = sky2_vlan_rx_register;
3850 /* read the mac address */
3851 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
3852 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3857 static void __devinit sky2_show_addr(struct net_device *dev)
3859 const struct sky2_port *sky2 = netdev_priv(dev);
3861 if (netif_msg_probe(sky2))
3862 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3864 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3865 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3868 /* Handle software interrupt used during MSI test */
3869 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
3871 struct sky2_hw *hw = dev_id;
3872 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3877 if (status & Y2_IS_IRQ_SW) {
3878 hw->flags |= SKY2_HW_USE_MSI;
3879 wake_up(&hw->msi_wait);
3880 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3882 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3887 /* Test interrupt path by forcing a a software IRQ */
3888 static int __devinit sky2_test_msi(struct sky2_hw *hw)
3890 struct pci_dev *pdev = hw->pdev;
3893 init_waitqueue_head (&hw->msi_wait);
3895 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3897 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
3899 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
3903 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
3904 sky2_read8(hw, B0_CTST);
3906 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
3908 if (!(hw->flags & SKY2_HW_USE_MSI)) {
3909 /* MSI test failed, go back to INTx mode */
3910 dev_info(&pdev->dev, "No interrupt generated using MSI, "
3911 "switching to INTx mode.\n");
3914 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3917 sky2_write32(hw, B0_IMSK, 0);
3918 sky2_read32(hw, B0_IMSK);
3920 free_irq(pdev->irq, hw);
3925 static int __devinit pci_wake_enabled(struct pci_dev *dev)
3927 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
3932 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
3934 return value & PCI_PM_CTRL_PME_ENABLE;
3937 static int __devinit sky2_probe(struct pci_dev *pdev,
3938 const struct pci_device_id *ent)
3940 struct net_device *dev;
3942 int err, using_dac = 0, wol_default;
3944 err = pci_enable_device(pdev);
3946 dev_err(&pdev->dev, "cannot enable PCI device\n");
3950 err = pci_request_regions(pdev, DRV_NAME);
3952 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
3953 goto err_out_disable;
3956 pci_set_master(pdev);
3958 if (sizeof(dma_addr_t) > sizeof(u32) &&
3959 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3961 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3963 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
3964 "for consistent allocations\n");
3965 goto err_out_free_regions;
3968 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3970 dev_err(&pdev->dev, "no usable DMA configuration\n");
3971 goto err_out_free_regions;
3975 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
3978 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
3980 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
3981 goto err_out_free_regions;
3986 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3988 dev_err(&pdev->dev, "cannot map device registers\n");
3989 goto err_out_free_hw;
3993 /* The sk98lin vendor driver uses hardware byte swapping but
3994 * this driver uses software swapping.
3998 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
3999 reg &= ~PCI_REV_DESC;
4000 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
4004 /* ring for status responses */
4005 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
4008 goto err_out_iounmap;
4010 err = sky2_init(hw);
4012 goto err_out_iounmap;
4014 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
4015 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
4016 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
4017 hw->chip_id, hw->chip_rev);
4021 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
4024 goto err_out_free_pci;
4027 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4028 err = sky2_test_msi(hw);
4029 if (err == -EOPNOTSUPP)
4030 pci_disable_msi(pdev);
4032 goto err_out_free_netdev;
4035 err = register_netdev(dev);
4037 dev_err(&pdev->dev, "cannot register net device\n");
4038 goto err_out_free_netdev;
4041 err = request_irq(pdev->irq, sky2_intr,
4042 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
4045 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4046 goto err_out_unregister;
4048 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4050 sky2_show_addr(dev);
4052 if (hw->ports > 1) {
4053 struct net_device *dev1;
4055 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
4057 dev_warn(&pdev->dev, "allocation for second device failed\n");
4058 else if ((err = register_netdev(dev1))) {
4059 dev_warn(&pdev->dev,
4060 "register of second port failed (%d)\n", err);
4064 sky2_show_addr(dev1);
4067 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
4068 INIT_WORK(&hw->restart_work, sky2_restart);
4070 pci_set_drvdata(pdev, hw);
4075 if (hw->flags & SKY2_HW_USE_MSI)
4076 pci_disable_msi(pdev);
4077 unregister_netdev(dev);
4078 err_out_free_netdev:
4081 sky2_write8(hw, B0_CTST, CS_RST_SET);
4082 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4087 err_out_free_regions:
4088 pci_release_regions(pdev);
4090 pci_disable_device(pdev);
4092 pci_set_drvdata(pdev, NULL);
4096 static void __devexit sky2_remove(struct pci_dev *pdev)
4098 struct sky2_hw *hw = pci_get_drvdata(pdev);
4099 struct net_device *dev0, *dev1;
4104 del_timer_sync(&hw->watchdog_timer);
4106 flush_scheduled_work();
4108 sky2_write32(hw, B0_IMSK, 0);
4109 synchronize_irq(hw->pdev->irq);
4114 unregister_netdev(dev1);
4115 unregister_netdev(dev0);
4119 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
4120 sky2_write8(hw, B0_CTST, CS_RST_SET);
4121 sky2_read8(hw, B0_CTST);
4123 free_irq(pdev->irq, hw);
4124 if (hw->flags & SKY2_HW_USE_MSI)
4125 pci_disable_msi(pdev);
4126 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4127 pci_release_regions(pdev);
4128 pci_disable_device(pdev);
4136 pci_set_drvdata(pdev, NULL);
4140 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4142 struct sky2_hw *hw = pci_get_drvdata(pdev);
4148 netif_poll_disable(hw->dev[0]);
4150 for (i = 0; i < hw->ports; i++) {
4151 struct net_device *dev = hw->dev[i];
4152 struct sky2_port *sky2 = netdev_priv(dev);
4154 if (netif_running(dev))
4158 sky2_wol_init(sky2);
4163 sky2_write32(hw, B0_IMSK, 0);
4166 pci_save_state(pdev);
4167 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
4168 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4173 static int sky2_resume(struct pci_dev *pdev)
4175 struct sky2_hw *hw = pci_get_drvdata(pdev);
4181 err = pci_set_power_state(pdev, PCI_D0);
4185 err = pci_restore_state(pdev);
4189 pci_enable_wake(pdev, PCI_D0, 0);
4191 /* Re-enable all clocks */
4192 if (hw->chip_id == CHIP_ID_YUKON_EX || hw->chip_id == CHIP_ID_YUKON_EC_U)
4193 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
4197 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4199 for (i = 0; i < hw->ports; i++) {
4200 struct net_device *dev = hw->dev[i];
4201 if (netif_running(dev)) {
4204 printk(KERN_ERR PFX "%s: could not up: %d\n",
4210 sky2_set_multicast(dev);
4214 netif_poll_enable(hw->dev[0]);
4218 dev_err(&pdev->dev, "resume failed (%d)\n", err);
4219 pci_disable_device(pdev);
4224 static void sky2_shutdown(struct pci_dev *pdev)
4226 struct sky2_hw *hw = pci_get_drvdata(pdev);
4232 netif_poll_disable(hw->dev[0]);
4234 for (i = 0; i < hw->ports; i++) {
4235 struct net_device *dev = hw->dev[i];
4236 struct sky2_port *sky2 = netdev_priv(dev);
4240 sky2_wol_init(sky2);
4247 pci_enable_wake(pdev, PCI_D3hot, wol);
4248 pci_enable_wake(pdev, PCI_D3cold, wol);
4250 pci_disable_device(pdev);
4251 pci_set_power_state(pdev, PCI_D3hot);
4255 static struct pci_driver sky2_driver = {
4257 .id_table = sky2_id_table,
4258 .probe = sky2_probe,
4259 .remove = __devexit_p(sky2_remove),
4261 .suspend = sky2_suspend,
4262 .resume = sky2_resume,
4264 .shutdown = sky2_shutdown,
4267 static int __init sky2_init_module(void)
4270 return pci_register_driver(&sky2_driver);
4273 static void __exit sky2_cleanup_module(void)
4275 pci_unregister_driver(&sky2_driver);
4276 sky2_debug_cleanup();
4279 module_init(sky2_init_module);
4280 module_exit(sky2_cleanup_module);
4282 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
4283 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
4284 MODULE_LICENSE("GPL");
4285 MODULE_VERSION(DRV_VERSION);