2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2010 QLogic Corporation
5 * See LICENSE.qlcnic for copyright and licensing details.
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/types.h>
14 #include <linux/ioport.h>
15 #include <linux/pci.h>
16 #include <linux/netdevice.h>
17 #include <linux/etherdevice.h>
20 #include <linux/tcp.h>
21 #include <linux/skbuff.h>
22 #include <linux/firmware.h>
24 #include <linux/ethtool.h>
25 #include <linux/mii.h>
26 #include <linux/timer.h>
28 #include <linux/vmalloc.h>
31 #include <asm/byteorder.h>
32 #include <linux/bitops.h>
33 #include <linux/if_vlan.h>
35 #include "qlcnic_hdr.h"
37 #define _QLCNIC_LINUX_MAJOR 5
38 #define _QLCNIC_LINUX_MINOR 0
39 #define _QLCNIC_LINUX_SUBVERSION 16
40 #define QLCNIC_LINUX_VERSIONID "5.0.16"
41 #define QLCNIC_DRV_IDC_VER 0x01
42 #define QLCNIC_DRIVER_VERSION ((_QLCNIC_LINUX_MAJOR << 16) |\
43 (_QLCNIC_LINUX_MINOR << 8) | (_QLCNIC_LINUX_SUBVERSION))
45 #define QLCNIC_VERSION_CODE(a, b, c) (((a) << 24) + ((b) << 16) + (c))
46 #define _major(v) (((v) >> 24) & 0xff)
47 #define _minor(v) (((v) >> 16) & 0xff)
48 #define _build(v) ((v) & 0xffff)
50 /* version in image has weird encoding:
53 * 31:16 - build (little endian)
55 #define QLCNIC_DECODE_VERSION(v) \
56 QLCNIC_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16))
58 #define QLCNIC_MIN_FW_VERSION QLCNIC_VERSION_CODE(4, 4, 2)
59 #define QLCNIC_NUM_FLASH_SECTORS (64)
60 #define QLCNIC_FLASH_SECTOR_SIZE (64 * 1024)
61 #define QLCNIC_FLASH_TOTAL_SIZE (QLCNIC_NUM_FLASH_SECTORS \
62 * QLCNIC_FLASH_SECTOR_SIZE)
64 #define RCV_DESC_RINGSIZE(rds_ring) \
65 (sizeof(struct rcv_desc) * (rds_ring)->num_desc)
66 #define RCV_BUFF_RINGSIZE(rds_ring) \
67 (sizeof(struct qlcnic_rx_buffer) * rds_ring->num_desc)
68 #define STATUS_DESC_RINGSIZE(sds_ring) \
69 (sizeof(struct status_desc) * (sds_ring)->num_desc)
70 #define TX_BUFF_RINGSIZE(tx_ring) \
71 (sizeof(struct qlcnic_cmd_buffer) * tx_ring->num_desc)
72 #define TX_DESC_RINGSIZE(tx_ring) \
73 (sizeof(struct cmd_desc_type0) * tx_ring->num_desc)
75 #define QLCNIC_P3P_A0 0x50
77 #define QLCNIC_IS_REVISION_P3P(REVISION) (REVISION >= QLCNIC_P3P_A0)
79 #define FIRST_PAGE_GROUP_START 0
80 #define FIRST_PAGE_GROUP_END 0x100000
82 #define P3P_MAX_MTU (9600)
83 #define P3P_MIN_MTU (68)
84 #define QLCNIC_MAX_ETHERHDR 32 /* This contains some padding */
86 #define QLCNIC_P3P_RX_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + ETH_DATA_LEN)
87 #define QLCNIC_P3P_RX_JUMBO_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + P3P_MAX_MTU)
88 #define QLCNIC_CT_DEFAULT_RX_BUF_LEN 2048
89 #define QLCNIC_LRO_BUFFER_EXTRA 2048
91 /* Opcodes to be used with the commands */
92 #define TX_ETHER_PKT 0x01
93 #define TX_TCP_PKT 0x02
94 #define TX_UDP_PKT 0x03
95 #define TX_IP_PKT 0x04
96 #define TX_TCP_LSO 0x05
97 #define TX_TCP_LSO6 0x06
98 #define TX_TCPV6_PKT 0x0b
99 #define TX_UDPV6_PKT 0x0c
102 #define QLCNIC_MAX_FRAGS_PER_TX 14
103 #define MAX_TSO_HEADER_DESC 2
104 #define MGMT_CMD_DESC_RESV 4
105 #define TX_STOP_THRESH ((MAX_SKB_FRAGS >> 2) + MAX_TSO_HEADER_DESC \
106 + MGMT_CMD_DESC_RESV)
107 #define QLCNIC_MAX_TX_TIMEOUTS 2
110 * Following are the states of the Phantom. Phantom will set them and
111 * Host will read to check if the fields are correct.
113 #define PHAN_INITIALIZE_FAILED 0xffff
114 #define PHAN_INITIALIZE_COMPLETE 0xff01
116 /* Host writes the following to notify that it has done the init-handshake */
117 #define PHAN_INITIALIZE_ACK 0xf00f
118 #define PHAN_PEG_RCV_INITIALIZED 0xff01
120 #define NUM_RCV_DESC_RINGS 3
122 #define RCV_RING_NORMAL 0
123 #define RCV_RING_JUMBO 1
125 #define MIN_CMD_DESCRIPTORS 64
126 #define MIN_RCV_DESCRIPTORS 64
127 #define MIN_JUMBO_DESCRIPTORS 32
129 #define MAX_CMD_DESCRIPTORS 1024
130 #define MAX_RCV_DESCRIPTORS_1G 4096
131 #define MAX_RCV_DESCRIPTORS_10G 8192
132 #define MAX_RCV_DESCRIPTORS_VF 2048
133 #define MAX_JUMBO_RCV_DESCRIPTORS_1G 512
134 #define MAX_JUMBO_RCV_DESCRIPTORS_10G 1024
136 #define DEFAULT_RCV_DESCRIPTORS_1G 2048
137 #define DEFAULT_RCV_DESCRIPTORS_10G 4096
138 #define DEFAULT_RCV_DESCRIPTORS_VF 1024
139 #define MAX_RDS_RINGS 2
141 #define get_next_index(index, length) \
142 (((index) + 1) & ((length) - 1))
145 * Following data structures describe the descriptors that will be used.
146 * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when
147 * we are doing LSO (above the 1500 size packet) only.
150 #define FLAGS_VLAN_TAGGED 0x10
151 #define FLAGS_VLAN_OOB 0x40
153 #define qlcnic_set_tx_vlan_tci(cmd_desc, v) \
154 (cmd_desc)->vlan_TCI = cpu_to_le16(v);
155 #define qlcnic_set_cmd_desc_port(cmd_desc, var) \
156 ((cmd_desc)->port_ctxid |= ((var) & 0x0F))
157 #define qlcnic_set_cmd_desc_ctxid(cmd_desc, var) \
158 ((cmd_desc)->port_ctxid |= ((var) << 4 & 0xF0))
160 #define qlcnic_set_tx_port(_desc, _port) \
161 ((_desc)->port_ctxid = ((_port) & 0xf) | (((_port) << 4) & 0xf0))
163 #define qlcnic_set_tx_flags_opcode(_desc, _flags, _opcode) \
164 ((_desc)->flags_opcode |= \
165 cpu_to_le16(((_flags) & 0x7f) | (((_opcode) & 0x3f) << 7)))
167 #define qlcnic_set_tx_frags_len(_desc, _frags, _len) \
168 ((_desc)->nfrags__length = \
169 cpu_to_le32(((_frags) & 0xff) | (((_len) & 0xffffff) << 8)))
171 struct cmd_desc_type0 {
172 u8 tcp_hdr_offset; /* For LSO only */
173 u8 ip_hdr_offset; /* For LSO only */
174 __le16 flags_opcode; /* 15:13 unused, 12:7 opcode, 6:0 flags */
175 __le32 nfrags__length; /* 31:8 total len, 7:0 frag count */
179 __le16 reference_handle;
181 u8 port_ctxid; /* 7:4 ctxid 3:0 port */
182 u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */
183 __le16 conn_id; /* IPSec offoad only */
188 __le16 buffer_length[4];
192 u8 eth_addr[ETH_ALEN];
195 } __attribute__ ((aligned(64)));
197 /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */
199 __le16 reference_handle;
201 __le32 buffer_length; /* allocated buffer length (usually 2K) */
205 /* opcode field in status_desc */
206 #define QLCNIC_SYN_OFFLOAD 0x03
207 #define QLCNIC_RXPKT_DESC 0x04
208 #define QLCNIC_OLD_RXPKT_DESC 0x3f
209 #define QLCNIC_RESPONSE_DESC 0x05
210 #define QLCNIC_LRO_DESC 0x12
212 /* for status field in status_desc */
213 #define STATUS_CKSUM_LOOP 0
214 #define STATUS_CKSUM_OK 2
216 /* owner bits of status_desc */
217 #define STATUS_OWNER_HOST (0x1ULL << 56)
218 #define STATUS_OWNER_PHANTOM (0x2ULL << 56)
220 /* Status descriptor:
221 0-3 port, 4-7 status, 8-11 type, 12-27 total_length
222 28-43 reference_handle, 44-47 protocol, 48-52 pkt_offset
223 53-55 desc_cnt, 56-57 owner, 58-63 opcode
225 #define qlcnic_get_sts_port(sts_data) \
227 #define qlcnic_get_sts_status(sts_data) \
228 (((sts_data) >> 4) & 0x0F)
229 #define qlcnic_get_sts_type(sts_data) \
230 (((sts_data) >> 8) & 0x0F)
231 #define qlcnic_get_sts_totallength(sts_data) \
232 (((sts_data) >> 12) & 0xFFFF)
233 #define qlcnic_get_sts_refhandle(sts_data) \
234 (((sts_data) >> 28) & 0xFFFF)
235 #define qlcnic_get_sts_prot(sts_data) \
236 (((sts_data) >> 44) & 0x0F)
237 #define qlcnic_get_sts_pkt_offset(sts_data) \
238 (((sts_data) >> 48) & 0x1F)
239 #define qlcnic_get_sts_desc_cnt(sts_data) \
240 (((sts_data) >> 53) & 0x7)
241 #define qlcnic_get_sts_opcode(sts_data) \
242 (((sts_data) >> 58) & 0x03F)
244 #define qlcnic_get_lro_sts_refhandle(sts_data) \
245 ((sts_data) & 0x0FFFF)
246 #define qlcnic_get_lro_sts_length(sts_data) \
247 (((sts_data) >> 16) & 0x0FFFF)
248 #define qlcnic_get_lro_sts_l2_hdr_offset(sts_data) \
249 (((sts_data) >> 32) & 0x0FF)
250 #define qlcnic_get_lro_sts_l4_hdr_offset(sts_data) \
251 (((sts_data) >> 40) & 0x0FF)
252 #define qlcnic_get_lro_sts_timestamp(sts_data) \
253 (((sts_data) >> 48) & 0x1)
254 #define qlcnic_get_lro_sts_type(sts_data) \
255 (((sts_data) >> 49) & 0x7)
256 #define qlcnic_get_lro_sts_push_flag(sts_data) \
257 (((sts_data) >> 52) & 0x1)
258 #define qlcnic_get_lro_sts_seq_number(sts_data) \
259 ((sts_data) & 0x0FFFFFFFF)
263 __le64 status_desc_data[2];
264 } __attribute__ ((aligned(16)));
266 /* UNIFIED ROMIMAGE */
267 #define QLCNIC_UNI_FW_MIN_SIZE 0xc8000
268 #define QLCNIC_UNI_DIR_SECT_PRODUCT_TBL 0x0
269 #define QLCNIC_UNI_DIR_SECT_BOOTLD 0x6
270 #define QLCNIC_UNI_DIR_SECT_FW 0x7
273 #define QLCNIC_UNI_CHIP_REV_OFF 10
274 #define QLCNIC_UNI_FLAGS_OFF 11
275 #define QLCNIC_UNI_BIOS_VERSION_OFF 12
276 #define QLCNIC_UNI_BOOTLD_IDX_OFF 27
277 #define QLCNIC_UNI_FIRMWARE_IDX_OFF 29
279 struct uni_table_desc{
286 struct uni_data_desc{
292 /* Flash Defines and Structures */
293 #define QLCNIC_FLT_LOCATION 0x3F1000
294 #define QLCNIC_FW_IMAGE_REGION 0x74
295 #define QLCNIC_BOOTLD_REGION 0X72
296 struct qlcnic_flt_header {
303 struct qlcnic_flt_entry {
313 /* Magic number to let user know flash is programmed */
314 #define QLCNIC_BDINFO_MAGIC 0x12345678
316 #define QLCNIC_BRDTYPE_P3P_REF_QG 0x0021
317 #define QLCNIC_BRDTYPE_P3P_HMEZ 0x0022
318 #define QLCNIC_BRDTYPE_P3P_10G_CX4_LP 0x0023
319 #define QLCNIC_BRDTYPE_P3P_4_GB 0x0024
320 #define QLCNIC_BRDTYPE_P3P_IMEZ 0x0025
321 #define QLCNIC_BRDTYPE_P3P_10G_SFP_PLUS 0x0026
322 #define QLCNIC_BRDTYPE_P3P_10000_BASE_T 0x0027
323 #define QLCNIC_BRDTYPE_P3P_XG_LOM 0x0028
324 #define QLCNIC_BRDTYPE_P3P_4_GB_MM 0x0029
325 #define QLCNIC_BRDTYPE_P3P_10G_SFP_CT 0x002a
326 #define QLCNIC_BRDTYPE_P3P_10G_SFP_QT 0x002b
327 #define QLCNIC_BRDTYPE_P3P_10G_CX4 0x0031
328 #define QLCNIC_BRDTYPE_P3P_10G_XFP 0x0032
329 #define QLCNIC_BRDTYPE_P3P_10G_TP 0x0080
331 #define QLCNIC_MSIX_TABLE_OFFSET 0x44
333 /* Flash memory map */
334 #define QLCNIC_BRDCFG_START 0x4000 /* board config */
335 #define QLCNIC_BOOTLD_START 0x10000 /* bootld */
336 #define QLCNIC_IMAGE_START 0x43000 /* compressed image */
337 #define QLCNIC_USER_START 0x3E8000 /* Firmare info */
339 #define QLCNIC_FW_VERSION_OFFSET (QLCNIC_USER_START+0x408)
340 #define QLCNIC_FW_SIZE_OFFSET (QLCNIC_USER_START+0x40c)
341 #define QLCNIC_FW_SERIAL_NUM_OFFSET (QLCNIC_USER_START+0x81c)
342 #define QLCNIC_BIOS_VERSION_OFFSET (QLCNIC_USER_START+0x83c)
344 #define QLCNIC_BRDTYPE_OFFSET (QLCNIC_BRDCFG_START+0x8)
345 #define QLCNIC_FW_MAGIC_OFFSET (QLCNIC_BRDCFG_START+0x128)
347 #define QLCNIC_FW_MIN_SIZE (0x3fffff)
348 #define QLCNIC_UNIFIED_ROMIMAGE 0
349 #define QLCNIC_FLASH_ROMIMAGE 1
350 #define QLCNIC_UNKNOWN_ROMIMAGE 0xff
352 #define QLCNIC_UNIFIED_ROMIMAGE_NAME "phanfw.bin"
353 #define QLCNIC_FLASH_ROMIMAGE_NAME "flash"
355 extern char qlcnic_driver_name[];
357 /* Number of status descriptors to handle per interrupt */
358 #define MAX_STATUS_HANDLE (64)
361 * qlcnic_skb_frag{} is to contain mapping info for each SG list. This
362 * has to be freed when DMA is complete. This is part of qlcnic_tx_buffer{}.
364 struct qlcnic_skb_frag {
369 /* Following defines are for the state of the buffers */
370 #define QLCNIC_BUFFER_FREE 0
371 #define QLCNIC_BUFFER_BUSY 1
374 * There will be one qlcnic_buffer per skb packet. These will be
375 * used to save the dma info for pci_unmap_page()
377 struct qlcnic_cmd_buffer {
379 struct qlcnic_skb_frag frag_array[MAX_SKB_FRAGS + 1];
383 /* In rx_buffer, we do not need multiple fragments as is a single buffer */
384 struct qlcnic_rx_buffer {
387 struct list_head list;
392 #define QLCNIC_GBE 0x01
393 #define QLCNIC_XGBE 0x02
396 * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is
397 * adjusted based on configured MTU.
399 #define QLCNIC_DEFAULT_INTR_COALESCE_RX_TIME_US 3
400 #define QLCNIC_DEFAULT_INTR_COALESCE_RX_PACKETS 256
402 #define QLCNIC_INTR_DEFAULT 0x04
403 #define QLCNIC_CONFIG_INTR_COALESCE 3
405 struct qlcnic_nic_intr_coalesce {
415 * One hardware_context{} per adapter
416 * contains interrupt info as well shared hardware info.
418 struct qlcnic_hardware_context {
419 void __iomem *pci_base0;
420 void __iomem *ocm_win_crb;
422 unsigned long pci_len0;
425 struct mutex mem_lock;
433 struct qlcnic_nic_intr_coalesce coal;
436 struct qlcnic_adapter_stats {
450 u64 skb_alloc_failure;
452 u64 rx_dma_map_error;
453 u64 tx_dma_map_error;
457 * Rcv Descriptor Context. One such per Rcv Descriptor. There may
458 * be one Rcv Descriptor for normal packets, one for jumbo and may be others.
460 struct qlcnic_host_rds_ring {
461 void __iomem *crb_rcv_producer;
462 struct rcv_desc *desc_head;
463 struct qlcnic_rx_buffer *rx_buf_arr;
469 struct list_head free_list;
471 dma_addr_t phys_addr;
472 } ____cacheline_internodealigned_in_smp;
474 struct qlcnic_host_sds_ring {
477 void __iomem *crb_sts_consumer;
479 struct status_desc *desc_head;
480 struct qlcnic_adapter *adapter;
481 struct napi_struct napi;
482 struct list_head free_list[NUM_RCV_DESC_RINGS];
484 void __iomem *crb_intr_mask;
487 dma_addr_t phys_addr;
488 char name[IFNAMSIZ+4];
489 } ____cacheline_internodealigned_in_smp;
491 struct qlcnic_host_tx_ring {
495 void __iomem *crb_cmd_producer;
496 struct cmd_desc_type0 *desc_head;
497 struct qlcnic_cmd_buffer *cmd_buf_arr;
500 dma_addr_t phys_addr;
501 dma_addr_t hw_cons_phys_addr;
502 struct netdev_queue *txq;
503 } ____cacheline_internodealigned_in_smp;
506 * Receive context. There is one such structure per instance of the
507 * receive processing. Any state information that is relevant to
508 * the receive, and is must be in this structure. The global data may be
511 struct qlcnic_recv_context {
512 struct qlcnic_host_rds_ring *rds_rings;
513 struct qlcnic_host_sds_ring *sds_rings;
520 /* HW context creation */
522 #define QLCNIC_OS_CRB_RETRY_COUNT 4000
523 #define QLCNIC_CDRP_SIGNATURE_MAKE(pcifn, version) \
524 (((pcifn) & 0xff) | (((version) & 0xff) << 8) | (0xcafe << 16))
526 #define QLCNIC_CDRP_CMD_BIT 0x80000000
529 * All responses must have the QLCNIC_CDRP_CMD_BIT cleared
530 * in the crb QLCNIC_CDRP_CRB_OFFSET.
532 #define QLCNIC_CDRP_FORM_RSP(rsp) (rsp)
533 #define QLCNIC_CDRP_IS_RSP(rsp) (((rsp) & QLCNIC_CDRP_CMD_BIT) == 0)
535 #define QLCNIC_CDRP_RSP_OK 0x00000001
536 #define QLCNIC_CDRP_RSP_FAIL 0x00000002
537 #define QLCNIC_CDRP_RSP_TIMEOUT 0x00000003
540 * All commands must have the QLCNIC_CDRP_CMD_BIT set in
541 * the crb QLCNIC_CDRP_CRB_OFFSET.
543 #define QLCNIC_CDRP_FORM_CMD(cmd) (QLCNIC_CDRP_CMD_BIT | (cmd))
544 #define QLCNIC_CDRP_IS_CMD(cmd) (((cmd) & QLCNIC_CDRP_CMD_BIT) != 0)
546 #define QLCNIC_CDRP_CMD_SUBMIT_CAPABILITIES 0x00000001
547 #define QLCNIC_CDRP_CMD_READ_MAX_RDS_PER_CTX 0x00000002
548 #define QLCNIC_CDRP_CMD_READ_MAX_SDS_PER_CTX 0x00000003
549 #define QLCNIC_CDRP_CMD_READ_MAX_RULES_PER_CTX 0x00000004
550 #define QLCNIC_CDRP_CMD_READ_MAX_RX_CTX 0x00000005
551 #define QLCNIC_CDRP_CMD_READ_MAX_TX_CTX 0x00000006
552 #define QLCNIC_CDRP_CMD_CREATE_RX_CTX 0x00000007
553 #define QLCNIC_CDRP_CMD_DESTROY_RX_CTX 0x00000008
554 #define QLCNIC_CDRP_CMD_CREATE_TX_CTX 0x00000009
555 #define QLCNIC_CDRP_CMD_DESTROY_TX_CTX 0x0000000a
556 #define QLCNIC_CDRP_CMD_SET_MTU 0x00000012
557 #define QLCNIC_CDRP_CMD_READ_PHY 0x00000013
558 #define QLCNIC_CDRP_CMD_WRITE_PHY 0x00000014
559 #define QLCNIC_CDRP_CMD_READ_HW_REG 0x00000015
560 #define QLCNIC_CDRP_CMD_GET_FLOW_CTL 0x00000016
561 #define QLCNIC_CDRP_CMD_SET_FLOW_CTL 0x00000017
562 #define QLCNIC_CDRP_CMD_READ_MAX_MTU 0x00000018
563 #define QLCNIC_CDRP_CMD_READ_MAX_LRO 0x00000019
564 #define QLCNIC_CDRP_CMD_MAC_ADDRESS 0x0000001f
566 #define QLCNIC_CDRP_CMD_GET_PCI_INFO 0x00000020
567 #define QLCNIC_CDRP_CMD_GET_NIC_INFO 0x00000021
568 #define QLCNIC_CDRP_CMD_SET_NIC_INFO 0x00000022
569 #define QLCNIC_CDRP_CMD_GET_ESWITCH_CAPABILITY 0x00000024
570 #define QLCNIC_CDRP_CMD_TOGGLE_ESWITCH 0x00000025
571 #define QLCNIC_CDRP_CMD_GET_ESWITCH_STATUS 0x00000026
572 #define QLCNIC_CDRP_CMD_SET_PORTMIRRORING 0x00000027
573 #define QLCNIC_CDRP_CMD_CONFIGURE_ESWITCH 0x00000028
574 #define QLCNIC_CDRP_CMD_GET_ESWITCH_PORT_CONFIG 0x00000029
575 #define QLCNIC_CDRP_CMD_GET_ESWITCH_STATS 0x0000002a
577 #define QLCNIC_RCODE_SUCCESS 0
578 #define QLCNIC_RCODE_TIMEOUT 17
579 #define QLCNIC_DESTROY_CTX_RESET 0
582 * Capabilities Announced
584 #define QLCNIC_CAP0_LEGACY_CONTEXT (1)
585 #define QLCNIC_CAP0_LEGACY_MN (1 << 2)
586 #define QLCNIC_CAP0_LSO (1 << 6)
587 #define QLCNIC_CAP0_JUMBO_CONTIGUOUS (1 << 7)
588 #define QLCNIC_CAP0_LRO_CONTIGUOUS (1 << 8)
589 #define QLCNIC_CAP0_VALIDOFF (1 << 11)
594 #define QLCNIC_HOST_CTX_STATE_FREED 0
595 #define QLCNIC_HOST_CTX_STATE_ACTIVE 2
601 struct qlcnic_hostrq_sds_ring {
602 __le64 host_phys_addr; /* Ring base addr */
603 __le32 ring_size; /* Ring entries */
605 __le16 rsvd; /* Padding */
608 struct qlcnic_hostrq_rds_ring {
609 __le64 host_phys_addr; /* Ring base addr */
610 __le64 buff_size; /* Packet buffer size */
611 __le32 ring_size; /* Ring entries */
612 __le32 ring_kind; /* Class of ring */
615 struct qlcnic_hostrq_rx_ctx {
616 __le64 host_rsp_dma_addr; /* Response dma'd here */
617 __le32 capabilities[4]; /* Flag bit vector */
618 __le32 host_int_crb_mode; /* Interrupt crb usage */
619 __le32 host_rds_crb_mode; /* RDS crb usage */
620 /* These ring offsets are relative to data[0] below */
621 __le32 rds_ring_offset; /* Offset to RDS config */
622 __le32 sds_ring_offset; /* Offset to SDS config */
623 __le16 num_rds_rings; /* Count of RDS rings */
624 __le16 num_sds_rings; /* Count of SDS rings */
625 __le16 valid_field_offset;
628 u8 reserved[128]; /* reserve space for future expansion*/
629 /* MUST BE 64-bit aligned.
630 The following is packed:
632 - N hostrq_sds_rings */
636 struct qlcnic_cardrsp_rds_ring{
637 __le32 host_producer_crb; /* Crb to use */
638 __le32 rsvd1; /* Padding */
641 struct qlcnic_cardrsp_sds_ring {
642 __le32 host_consumer_crb; /* Crb to use */
643 __le32 interrupt_crb; /* Crb to use */
646 struct qlcnic_cardrsp_rx_ctx {
647 /* These ring offsets are relative to data[0] below */
648 __le32 rds_ring_offset; /* Offset to RDS config */
649 __le32 sds_ring_offset; /* Offset to SDS config */
650 __le32 host_ctx_state; /* Starting State */
651 __le32 num_fn_per_port; /* How many PCI fn share the port */
652 __le16 num_rds_rings; /* Count of RDS rings */
653 __le16 num_sds_rings; /* Count of SDS rings */
654 __le16 context_id; /* Handle for context */
655 u8 phys_port; /* Physical id of port */
656 u8 virt_port; /* Virtual/Logical id of port */
657 u8 reserved[128]; /* save space for future expansion */
658 /* MUST BE 64-bit aligned.
659 The following is packed:
660 - N cardrsp_rds_rings
661 - N cardrs_sds_rings */
665 #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \
666 (sizeof(HOSTRQ_RX) + \
667 (rds_rings)*(sizeof(struct qlcnic_hostrq_rds_ring)) + \
668 (sds_rings)*(sizeof(struct qlcnic_hostrq_sds_ring)))
670 #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \
671 (sizeof(CARDRSP_RX) + \
672 (rds_rings)*(sizeof(struct qlcnic_cardrsp_rds_ring)) + \
673 (sds_rings)*(sizeof(struct qlcnic_cardrsp_sds_ring)))
679 struct qlcnic_hostrq_cds_ring {
680 __le64 host_phys_addr; /* Ring base addr */
681 __le32 ring_size; /* Ring entries */
682 __le32 rsvd; /* Padding */
685 struct qlcnic_hostrq_tx_ctx {
686 __le64 host_rsp_dma_addr; /* Response dma'd here */
687 __le64 cmd_cons_dma_addr; /* */
688 __le64 dummy_dma_addr; /* */
689 __le32 capabilities[4]; /* Flag bit vector */
690 __le32 host_int_crb_mode; /* Interrupt crb usage */
691 __le32 rsvd1; /* Padding */
692 __le16 rsvd2; /* Padding */
693 __le16 interrupt_ctl;
695 __le16 rsvd3; /* Padding */
696 struct qlcnic_hostrq_cds_ring cds_ring; /* Desc of cds ring */
697 u8 reserved[128]; /* future expansion */
700 struct qlcnic_cardrsp_cds_ring {
701 __le32 host_producer_crb; /* Crb to use */
702 __le32 interrupt_crb; /* Crb to use */
705 struct qlcnic_cardrsp_tx_ctx {
706 __le32 host_ctx_state; /* Starting state */
707 __le16 context_id; /* Handle for context */
708 u8 phys_port; /* Physical id of port */
709 u8 virt_port; /* Virtual/Logical id of port */
710 struct qlcnic_cardrsp_cds_ring cds_ring; /* Card cds settings */
711 u8 reserved[128]; /* future expansion */
714 #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX))
715 #define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX))
719 #define QLCNIC_HOST_RDS_CRB_MODE_UNIQUE 0
720 #define QLCNIC_HOST_RDS_CRB_MODE_SHARED 1
721 #define QLCNIC_HOST_RDS_CRB_MODE_CUSTOM 2
722 #define QLCNIC_HOST_RDS_CRB_MODE_MAX 3
724 #define QLCNIC_HOST_INT_CRB_MODE_UNIQUE 0
725 #define QLCNIC_HOST_INT_CRB_MODE_SHARED 1
726 #define QLCNIC_HOST_INT_CRB_MODE_NORX 2
727 #define QLCNIC_HOST_INT_CRB_MODE_NOTX 3
728 #define QLCNIC_HOST_INT_CRB_MODE_NORXTX 4
733 #define MC_COUNT_P3P 38
735 #define QLCNIC_MAC_NOOP 0
736 #define QLCNIC_MAC_ADD 1
737 #define QLCNIC_MAC_DEL 2
738 #define QLCNIC_MAC_VLAN_ADD 3
739 #define QLCNIC_MAC_VLAN_DEL 4
741 struct qlcnic_mac_list_s {
742 struct list_head list;
743 uint8_t mac_addr[ETH_ALEN+2];
746 #define QLCNIC_HOST_REQUEST 0x13
747 #define QLCNIC_REQUEST 0x14
749 #define QLCNIC_MAC_EVENT 0x1
751 #define QLCNIC_IP_UP 2
752 #define QLCNIC_IP_DOWN 3
755 * Driver --> Firmware
757 #define QLCNIC_H2C_OPCODE_CONFIG_RSS 0x1
758 #define QLCNIC_H2C_OPCODE_CONFIG_INTR_COALESCE 0x3
759 #define QLCNIC_H2C_OPCODE_CONFIG_LED 0x4
760 #define QLCNIC_H2C_OPCODE_LRO_REQUEST 0x7
761 #define QLCNIC_H2C_OPCODE_SET_MAC_RECEIVE_MODE 0xc
762 #define QLCNIC_H2C_OPCODE_CONFIG_IPADDR 0x12
763 #define QLCNIC_H2C_OPCODE_GET_LINKEVENT 0x15
764 #define QLCNIC_H2C_OPCODE_CONFIG_BRIDGING 0x17
765 #define QLCNIC_H2C_OPCODE_CONFIG_HW_LRO 0x18
767 * Firmware --> Driver
770 #define QLCNIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 141
772 #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */
773 #define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */
774 #define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */
776 #define QLCNIC_LRO_REQUEST_CLEANUP 4
778 /* Capabilites received */
779 #define QLCNIC_FW_CAPABILITY_TSO BIT_1
780 #define QLCNIC_FW_CAPABILITY_BDG BIT_8
781 #define QLCNIC_FW_CAPABILITY_FVLANTX BIT_9
782 #define QLCNIC_FW_CAPABILITY_HW_LRO BIT_10
785 #define LINKEVENT_MODULE_NOT_PRESENT 1
786 #define LINKEVENT_MODULE_OPTICAL_UNKNOWN 2
787 #define LINKEVENT_MODULE_OPTICAL_SRLR 3
788 #define LINKEVENT_MODULE_OPTICAL_LRM 4
789 #define LINKEVENT_MODULE_OPTICAL_SFP_1G 5
790 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE 6
791 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN 7
792 #define LINKEVENT_MODULE_TWINAX 8
794 #define LINKSPEED_10GBPS 10000
795 #define LINKSPEED_1GBPS 1000
796 #define LINKSPEED_100MBPS 100
797 #define LINKSPEED_10MBPS 10
799 #define LINKSPEED_ENCODED_10MBPS 0
800 #define LINKSPEED_ENCODED_100MBPS 1
801 #define LINKSPEED_ENCODED_1GBPS 2
803 #define LINKEVENT_AUTONEG_DISABLED 0
804 #define LINKEVENT_AUTONEG_ENABLED 1
806 #define LINKEVENT_HALF_DUPLEX 0
807 #define LINKEVENT_FULL_DUPLEX 1
809 #define LINKEVENT_LINKSPEED_MBPS 0
810 #define LINKEVENT_LINKSPEED_ENCODED 1
812 /* firmware response header:
813 * 63:58 - message type
817 * 47:40 - completion id
822 #define qlcnic_get_nic_msg_opcode(msg_hdr) \
823 ((msg_hdr >> 32) & 0xFF)
825 struct qlcnic_fw_msg {
835 struct qlcnic_nic_req {
841 struct qlcnic_mac_req {
847 struct qlcnic_vlan_req {
852 struct qlcnic_ipaddr {
857 #define QLCNIC_MSI_ENABLED 0x02
858 #define QLCNIC_MSIX_ENABLED 0x04
859 #define QLCNIC_LRO_ENABLED 0x08
860 #define QLCNIC_LRO_DISABLED 0x00
861 #define QLCNIC_BRIDGE_ENABLED 0X10
862 #define QLCNIC_DIAG_ENABLED 0x20
863 #define QLCNIC_ESWITCH_ENABLED 0x40
864 #define QLCNIC_ADAPTER_INITIALIZED 0x80
865 #define QLCNIC_TAGGING_ENABLED 0x100
866 #define QLCNIC_MACSPOOF 0x200
867 #define QLCNIC_MAC_OVERRIDE_DISABLED 0x400
868 #define QLCNIC_PROMISC_DISABLED 0x800
869 #define QLCNIC_NEED_FLR 0x1000
870 #define QLCNIC_IS_MSI_FAMILY(adapter) \
871 ((adapter)->flags & (QLCNIC_MSI_ENABLED | QLCNIC_MSIX_ENABLED))
873 #define QLCNIC_DEF_NUM_STS_DESC_RINGS 4
874 #define QLCNIC_MIN_NUM_RSS_RINGS 2
875 #define QLCNIC_MSIX_TBL_SPACE 8192
876 #define QLCNIC_PCI_REG_MSIX_TBL 0x44
877 #define QLCNIC_MSIX_TBL_PGSIZE 4096
879 #define QLCNIC_NETDEV_WEIGHT 128
880 #define QLCNIC_ADAPTER_UP_MAGIC 777
882 #define __QLCNIC_FW_ATTACHED 0
883 #define __QLCNIC_DEV_UP 1
884 #define __QLCNIC_RESETTING 2
885 #define __QLCNIC_START_FW 4
886 #define __QLCNIC_AER 5
887 #define __QLCNIC_DIAG_RES_ALLOC 6
889 #define QLCNIC_INTERRUPT_TEST 1
890 #define QLCNIC_LOOPBACK_TEST 2
891 #define QLCNIC_LED_TEST 3
893 #define QLCNIC_FILTER_AGE 80
894 #define QLCNIC_READD_AGE 20
895 #define QLCNIC_LB_MAX_FILTERS 64
897 struct qlcnic_filter {
898 struct hlist_node fnode;
904 struct qlcnic_filter_hash {
905 struct hlist_head *fhead;
910 struct qlcnic_adapter {
911 struct qlcnic_hardware_context *ahw;
912 struct qlcnic_recv_context *recv_ctx;
913 struct qlcnic_host_tx_ring *tx_ring;
914 struct net_device *netdev;
915 struct pci_dev *pdev;
973 u8 mac_addr[ETH_ALEN];
976 unsigned long vlans[BITS_TO_LONGS(VLAN_N_VID)];
978 struct qlcnic_npar_info *npars;
979 struct qlcnic_eswitch *eswitch;
980 struct qlcnic_nic_template *nic_ops;
982 struct qlcnic_adapter_stats stats;
983 struct list_head mac_list;
985 void __iomem *tgt_mask_reg;
986 void __iomem *tgt_status_reg;
987 void __iomem *crb_int_state_reg;
988 void __iomem *isr_int_vec;
990 struct msix_entry *msix_entries;
992 struct delayed_work fw_work;
995 struct qlcnic_filter_hash fhash;
997 spinlock_t tx_clean_lock;
998 spinlock_t mac_learn_lock;
999 __le32 file_prd_off; /*File fw product offset*/
1001 const struct firmware *fw;
1004 struct qlcnic_info {
1006 __le16 op_mode; /* 1 = Priv, 2 = NP, 3 = NP passthru */
1008 __le16 switch_mode; /* 0 = disabled, 1 = int, 2 = ext */
1010 __le32 capabilities;
1022 struct qlcnic_pci_info {
1023 __le16 id; /* pci function id */
1024 __le16 active; /* 1 = Enabled */
1025 __le16 type; /* 1 = NIC, 2 = FCoE, 3 = iSCSI */
1026 __le16 default_port; /* default port number */
1028 __le16 tx_min_bw; /* Multiple of 100mbpc */
1030 __le16 reserved1[2];
1036 struct qlcnic_npar_info {
1052 struct qlcnic_eswitch {
1056 u8 active_ucast_filters;
1057 u8 max_ucast_filters;
1058 u8 max_active_vlans;
1061 #define QLCNIC_SWITCH_ENABLE BIT_1
1062 #define QLCNIC_SWITCH_VLAN_FILTERING BIT_2
1063 #define QLCNIC_SWITCH_PROMISC_MODE BIT_3
1064 #define QLCNIC_SWITCH_PORT_MIRRORING BIT_4
1068 /* Return codes for Error handling */
1069 #define QL_STATUS_INVALID_PARAM -1
1071 #define MAX_BW 100 /* % of link speed */
1072 #define MAX_VLAN_ID 4095
1073 #define MIN_VLAN_ID 2
1074 #define DEFAULT_MAC_LEARN 1
1076 #define IS_VALID_VLAN(vlan) (vlan >= MIN_VLAN_ID && vlan < MAX_VLAN_ID)
1077 #define IS_VALID_BW(bw) (bw <= MAX_BW)
1079 struct qlcnic_pci_func_cfg {
1089 struct qlcnic_npar_func_cfg {
1100 struct qlcnic_pm_func_cfg {
1107 struct qlcnic_esw_func_cfg {
1121 #define QLCNIC_STATS_VERSION 1
1122 #define QLCNIC_STATS_PORT 1
1123 #define QLCNIC_STATS_ESWITCH 2
1124 #define QLCNIC_QUERY_RX_COUNTER 0
1125 #define QLCNIC_QUERY_TX_COUNTER 1
1126 #define QLCNIC_ESW_STATS_NOT_AVAIL 0xffffffffffffffffULL
1128 #define QLCNIC_ADD_ESW_STATS(VAL1, VAL2)\
1130 if (((VAL1) == QLCNIC_ESW_STATS_NOT_AVAIL) && \
1131 ((VAL2) != QLCNIC_ESW_STATS_NOT_AVAIL)) \
1133 else if (((VAL1) != QLCNIC_ESW_STATS_NOT_AVAIL) && \
1134 ((VAL2) != QLCNIC_ESW_STATS_NOT_AVAIL)) \
1138 struct __qlcnic_esw_statistics {
1143 __le64 unicast_frames;
1144 __le64 multicast_frames;
1145 __le64 broadcast_frames;
1146 __le64 dropped_frames;
1148 __le64 local_frames;
1153 struct qlcnic_esw_statistics {
1154 struct __qlcnic_esw_statistics rx;
1155 struct __qlcnic_esw_statistics tx;
1158 int qlcnic_fw_cmd_query_phy(struct qlcnic_adapter *adapter, u32 reg, u32 *val);
1159 int qlcnic_fw_cmd_set_phy(struct qlcnic_adapter *adapter, u32 reg, u32 val);
1161 u32 qlcnic_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong off);
1162 int qlcnic_hw_write_wx_2M(struct qlcnic_adapter *, ulong off, u32 data);
1163 int qlcnic_pci_mem_write_2M(struct qlcnic_adapter *, u64 off, u64 data);
1164 int qlcnic_pci_mem_read_2M(struct qlcnic_adapter *, u64 off, u64 *data);
1165 void qlcnic_pci_camqm_read_2M(struct qlcnic_adapter *, u64, u64 *);
1166 void qlcnic_pci_camqm_write_2M(struct qlcnic_adapter *, u64, u64);
1168 #define ADDR_IN_RANGE(addr, low, high) \
1169 (((addr) < (high)) && ((addr) >= (low)))
1171 #define QLCRD32(adapter, off) \
1172 (qlcnic_hw_read_wx_2M(adapter, off))
1173 #define QLCWR32(adapter, off, val) \
1174 (qlcnic_hw_write_wx_2M(adapter, off, val))
1176 int qlcnic_pcie_sem_lock(struct qlcnic_adapter *, int, u32);
1177 void qlcnic_pcie_sem_unlock(struct qlcnic_adapter *, int);
1179 #define qlcnic_rom_lock(a) \
1180 qlcnic_pcie_sem_lock((a), 2, QLCNIC_ROM_LOCK_ID)
1181 #define qlcnic_rom_unlock(a) \
1182 qlcnic_pcie_sem_unlock((a), 2)
1183 #define qlcnic_phy_lock(a) \
1184 qlcnic_pcie_sem_lock((a), 3, QLCNIC_PHY_LOCK_ID)
1185 #define qlcnic_phy_unlock(a) \
1186 qlcnic_pcie_sem_unlock((a), 3)
1187 #define qlcnic_api_lock(a) \
1188 qlcnic_pcie_sem_lock((a), 5, 0)
1189 #define qlcnic_api_unlock(a) \
1190 qlcnic_pcie_sem_unlock((a), 5)
1191 #define qlcnic_sw_lock(a) \
1192 qlcnic_pcie_sem_lock((a), 6, 0)
1193 #define qlcnic_sw_unlock(a) \
1194 qlcnic_pcie_sem_unlock((a), 6)
1195 #define crb_win_lock(a) \
1196 qlcnic_pcie_sem_lock((a), 7, QLCNIC_CRB_WIN_LOCK_ID)
1197 #define crb_win_unlock(a) \
1198 qlcnic_pcie_sem_unlock((a), 7)
1200 int qlcnic_get_board_info(struct qlcnic_adapter *adapter);
1201 int qlcnic_wol_supported(struct qlcnic_adapter *adapter);
1202 int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate);
1203 void qlcnic_prune_lb_filters(struct qlcnic_adapter *adapter);
1204 void qlcnic_delete_lb_filters(struct qlcnic_adapter *adapter);
1206 /* Functions from qlcnic_init.c */
1207 int qlcnic_load_firmware(struct qlcnic_adapter *adapter);
1208 int qlcnic_need_fw_reset(struct qlcnic_adapter *adapter);
1209 void qlcnic_request_firmware(struct qlcnic_adapter *adapter);
1210 void qlcnic_release_firmware(struct qlcnic_adapter *adapter);
1211 int qlcnic_pinit_from_rom(struct qlcnic_adapter *adapter);
1212 int qlcnic_setup_idc_param(struct qlcnic_adapter *adapter);
1213 int qlcnic_check_flash_fw_ver(struct qlcnic_adapter *adapter);
1215 int qlcnic_rom_fast_read(struct qlcnic_adapter *adapter, int addr, int *valp);
1216 int qlcnic_rom_fast_read_words(struct qlcnic_adapter *adapter, int addr,
1217 u8 *bytes, size_t size);
1218 int qlcnic_alloc_sw_resources(struct qlcnic_adapter *adapter);
1219 void qlcnic_free_sw_resources(struct qlcnic_adapter *adapter);
1221 void __iomem *qlcnic_get_ioaddr(struct qlcnic_adapter *, u32);
1223 int qlcnic_alloc_hw_resources(struct qlcnic_adapter *adapter);
1224 void qlcnic_free_hw_resources(struct qlcnic_adapter *adapter);
1226 int qlcnic_fw_create_ctx(struct qlcnic_adapter *adapter);
1227 void qlcnic_fw_destroy_ctx(struct qlcnic_adapter *adapter);
1229 void qlcnic_reset_rx_buffers_list(struct qlcnic_adapter *adapter);
1230 void qlcnic_release_rx_buffers(struct qlcnic_adapter *adapter);
1231 void qlcnic_release_tx_buffers(struct qlcnic_adapter *adapter);
1233 int qlcnic_check_fw_status(struct qlcnic_adapter *adapter);
1234 void qlcnic_watchdog_task(struct work_struct *work);
1235 void qlcnic_post_rx_buffers(struct qlcnic_adapter *adapter,
1236 struct qlcnic_host_rds_ring *rds_ring);
1237 int qlcnic_process_rcv_ring(struct qlcnic_host_sds_ring *sds_ring, int max);
1238 void qlcnic_set_multi(struct net_device *netdev);
1239 void qlcnic_free_mac_list(struct qlcnic_adapter *adapter);
1240 int qlcnic_nic_set_promisc(struct qlcnic_adapter *adapter, u32);
1241 int qlcnic_config_intr_coalesce(struct qlcnic_adapter *adapter);
1242 int qlcnic_config_rss(struct qlcnic_adapter *adapter, int enable);
1243 int qlcnic_config_ipaddr(struct qlcnic_adapter *adapter, __be32 ip, int cmd);
1244 int qlcnic_linkevent_request(struct qlcnic_adapter *adapter, int enable);
1245 void qlcnic_advert_link_change(struct qlcnic_adapter *adapter, int linkup);
1247 int qlcnic_fw_cmd_set_mtu(struct qlcnic_adapter *adapter, int mtu);
1248 int qlcnic_change_mtu(struct net_device *netdev, int new_mtu);
1249 u32 qlcnic_fix_features(struct net_device *netdev, u32 features);
1250 int qlcnic_set_features(struct net_device *netdev, u32 features);
1251 int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter, int enable);
1252 int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable);
1253 int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter);
1254 void qlcnic_update_cmd_producer(struct qlcnic_adapter *adapter,
1255 struct qlcnic_host_tx_ring *tx_ring);
1256 void qlcnic_fetch_mac(struct qlcnic_adapter *, u32, u32, u8, u8 *);
1258 /* Functions from qlcnic_main.c */
1259 int qlcnic_reset_context(struct qlcnic_adapter *);
1260 u32 qlcnic_issue_cmd(struct qlcnic_adapter *adapter,
1261 u32 pci_fn, u32 version, u32 arg1, u32 arg2, u32 arg3, u32 cmd);
1262 void qlcnic_diag_free_res(struct net_device *netdev, int max_sds_rings);
1263 int qlcnic_diag_alloc_res(struct net_device *netdev, int test);
1264 netdev_tx_t qlcnic_xmit_frame(struct sk_buff *skb, struct net_device *netdev);
1265 int qlcnic_validate_max_rss(struct net_device *netdev, u8 max_hw, u8 val);
1266 int qlcnic_set_max_rss(struct qlcnic_adapter *adapter, u8 data);
1268 /* Management functions */
1269 int qlcnic_get_mac_address(struct qlcnic_adapter *, u8*);
1270 int qlcnic_get_nic_info(struct qlcnic_adapter *, struct qlcnic_info *, u8);
1271 int qlcnic_set_nic_info(struct qlcnic_adapter *, struct qlcnic_info *);
1272 int qlcnic_get_pci_info(struct qlcnic_adapter *, struct qlcnic_pci_info*);
1274 /* eSwitch management functions */
1275 int qlcnic_config_switch_port(struct qlcnic_adapter *,
1276 struct qlcnic_esw_func_cfg *);
1277 int qlcnic_get_eswitch_port_config(struct qlcnic_adapter *,
1278 struct qlcnic_esw_func_cfg *);
1279 int qlcnic_config_port_mirroring(struct qlcnic_adapter *, u8, u8, u8);
1280 int qlcnic_get_port_stats(struct qlcnic_adapter *, const u8, const u8,
1281 struct __qlcnic_esw_statistics *);
1282 int qlcnic_get_eswitch_stats(struct qlcnic_adapter *, const u8, u8,
1283 struct __qlcnic_esw_statistics *);
1284 int qlcnic_clear_esw_stats(struct qlcnic_adapter *adapter, u8, u8, u8);
1285 extern int qlcnic_config_tso;
1288 * QLOGIC Board information
1291 #define QLCNIC_MAX_BOARD_NAME_LEN 100
1292 struct qlcnic_brdinfo {
1293 unsigned short vendor;
1294 unsigned short device;
1295 unsigned short sub_vendor;
1296 unsigned short sub_device;
1297 char short_name[QLCNIC_MAX_BOARD_NAME_LEN];
1300 static const struct qlcnic_brdinfo qlcnic_boards[] = {
1301 {0x1077, 0x8020, 0x1077, 0x203,
1302 "8200 Series Single Port 10GbE Converged Network Adapter "
1303 "(TCP/IP Networking)"},
1304 {0x1077, 0x8020, 0x1077, 0x207,
1305 "8200 Series Dual Port 10GbE Converged Network Adapter "
1306 "(TCP/IP Networking)"},
1307 {0x1077, 0x8020, 0x1077, 0x20b,
1308 "3200 Series Dual Port 10Gb Intelligent Ethernet Adapter"},
1309 {0x1077, 0x8020, 0x1077, 0x20c,
1310 "3200 Series Quad Port 1Gb Intelligent Ethernet Adapter"},
1311 {0x1077, 0x8020, 0x1077, 0x20f,
1312 "3200 Series Single Port 10Gb Intelligent Ethernet Adapter"},
1313 {0x1077, 0x8020, 0x103c, 0x3733,
1314 "NC523SFP 10Gb 2-port Server Adapter"},
1315 {0x1077, 0x8020, 0x103c, 0x3346,
1316 "CN1000Q Dual Port Converged Network Adapter"},
1317 {0x1077, 0x8020, 0x0, 0x0, "cLOM8214 1/10GbE Controller"},
1320 #define NUM_SUPPORTED_BOARDS ARRAY_SIZE(qlcnic_boards)
1322 static inline u32 qlcnic_tx_avail(struct qlcnic_host_tx_ring *tx_ring)
1324 if (likely(tx_ring->producer < tx_ring->sw_consumer))
1325 return tx_ring->sw_consumer - tx_ring->producer;
1327 return tx_ring->sw_consumer + tx_ring->num_desc -
1331 extern const struct ethtool_ops qlcnic_ethtool_ops;
1333 struct qlcnic_nic_template {
1334 int (*config_bridged_mode) (struct qlcnic_adapter *, u32);
1335 int (*config_led) (struct qlcnic_adapter *, u32, u32);
1336 int (*start_firmware) (struct qlcnic_adapter *);
1339 #define QLCDB(adapter, lvl, _fmt, _args...) do { \
1340 if (NETIF_MSG_##lvl & adapter->msg_enable) \
1341 printk(KERN_INFO "%s: %s: " _fmt, \
1342 dev_name(&adapter->pdev->dev), \
1343 __func__, ##_args); \
1346 #endif /* __QLCNIC_H_ */