drivers/net/ixgbe/ixgbe_main.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2011 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/types.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/string.h>
  34 #include <linux/in.h>
  35 #include <linux/ip.h>
  36 #include <linux/tcp.h>
  37 #include <linux/pkt_sched.h>
  38 #include <linux/ipv6.h>
  39 #include <linux/slab.h>
  40 #include <net/checksum.h>
  41 #include <net/ip6_checksum.h>
  42 #include <linux/ethtool.h>
  43 #include <linux/if_vlan.h>
  44 #include <scsi/fc/fc_fcoe.h>
  45
  46 #include "ixgbe.h"
  47 #include "ixgbe_common.h"
  48 #include "ixgbe_dcb_82599.h"
  49 #include "ixgbe_sriov.h"
  50
  51 char ixgbe_driver_name[] = "ixgbe";
  52 static const char ixgbe_driver_string[] =
  53                               "Intel(R) 10 Gigabit PCI Express Network Driver";
  54 #define MAJ 3
  55 #define MIN 3
  56 #define BUILD 8
  57 #define KFIX 2
  58 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
  59         __stringify(BUILD) "-k" __stringify(KFIX)
  60 const char ixgbe_driver_version[] = DRV_VERSION;
  61 static const char ixgbe_copyright[] =
  62                                 "Copyright (c) 1999-2011 Intel Corporation.";
  63
  64 static const struct ixgbe_info *ixgbe_info_tbl[] = {
  65         [board_82598] = &ixgbe_82598_info,
  66         [board_82599] = &ixgbe_82599_info,
  67         [board_X540] = &ixgbe_X540_info,
  68 };
  69
  70 /* ixgbe_pci_tbl - PCI Device ID Table
  71  *
  72  * Wildcard entries (PCI_ANY_ID) should come last
  73  * Last entry must be all 0s
  74  *
  75  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  76  *   Class, Class Mask, private data (not used) }
  77  */
  78 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
  79         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
  80          board_82598 },
  81         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
  82          board_82598 },
  83         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
  84          board_82598 },
  85         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
  86          board_82598 },
  87         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
  88          board_82598 },
  89         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
  90          board_82598 },
  91         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
  92          board_82598 },
  93         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
  94          board_82598 },
  95         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
  96          board_82598 },
  97         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
  98          board_82598 },
  99         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
 100          board_82598 },
 101         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
 102          board_82598 },
 103         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
 104          board_82599 },
 105         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
 106          board_82599 },
 107         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
 108          board_82599 },
 109         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
 110          board_82599 },
 111         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
 112          board_82599 },
 113         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
 114          board_82599 },
 115         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
 116          board_82599 },
 117         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE),
 118          board_82599 },
 119         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE),
 120          board_82599 },
 121         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
 122          board_82599 },
 123         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
 124          board_82599 },
 125         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T),
 126          board_X540 },
 127         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2),
 128          board_82599 },
 129
 130         /* required last entry */
 131         {0, }
 132 };
 133 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
 134
 135 #ifdef CONFIG_IXGBE_DCA
 136 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
 137                             void *p);
 138 static struct notifier_block dca_notifier = {
 139         .notifier_call = ixgbe_notify_dca,
 140         .next          = NULL,
 141         .priority      = 0
 142 };
 143 #endif
 144
 145 #ifdef CONFIG_PCI_IOV
 146 static unsigned int max_vfs;
 147 module_param(max_vfs, uint, 0);
 148 MODULE_PARM_DESC(max_vfs,
 149                  "Maximum number of virtual functions to allocate per physical function");
 150 #endif /* CONFIG_PCI_IOV */
 151
 152 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
 153 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
 154 MODULE_LICENSE("GPL");
 155 MODULE_VERSION(DRV_VERSION);
 156
 157 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
 158
 159 static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
 160 {
 161         struct ixgbe_hw *hw = &adapter->hw;
 162         u32 gcr;
 163         u32 gpie;
 164         u32 vmdctl;
 165
 166 #ifdef CONFIG_PCI_IOV
 167         /* disable iov and allow time for transactions to clear */
 168         pci_disable_sriov(adapter->pdev);
 169 #endif
 170
 171         /* turn off device IOV mode */
 172         gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
 173         gcr &= ~(IXGBE_GCR_EXT_SRIOV);
 174         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
 175         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
 176         gpie &= ~IXGBE_GPIE_VTMODE_MASK;
 177         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
 178
 179         /* set default pool back to 0 */
 180         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
 181         vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
 182         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
 183
 184         /* take a breather then clean up driver data */
 185         msleep(100);
 186
 187         kfree(adapter->vfinfo);
 188         adapter->vfinfo = NULL;
 189
 190         adapter->num_vfs = 0;
 191         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
 192 }
 193
 194 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
 195 {
 196         if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
 197             !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
 198                 schedule_work(&adapter->service_task);
 199 }
 200
 201 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
 202 {
 203         BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
 204
 205         /* flush memory to make sure state is correct before next watchog */
 206         smp_mb__before_clear_bit();
 207         clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
 208 }
 209
 210 struct ixgbe_reg_info {
 211         u32 ofs;
 212         char *name;
 213 };
 214
 215 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
 216
 217         /* General Registers */
 218         {IXGBE_CTRL, "CTRL"},
 219         {IXGBE_STATUS, "STATUS"},
 220         {IXGBE_CTRL_EXT, "CTRL_EXT"},
 221
 222         /* Interrupt Registers */
 223         {IXGBE_EICR, "EICR"},
 224
 225         /* RX Registers */
 226         {IXGBE_SRRCTL(0), "SRRCTL"},
 227         {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
 228         {IXGBE_RDLEN(0), "RDLEN"},
 229         {IXGBE_RDH(0), "RDH"},
 230         {IXGBE_RDT(0), "RDT"},
 231         {IXGBE_RXDCTL(0), "RXDCTL"},
 232         {IXGBE_RDBAL(0), "RDBAL"},
 233         {IXGBE_RDBAH(0), "RDBAH"},
 234
 235         /* TX Registers */
 236         {IXGBE_TDBAL(0), "TDBAL"},
 237         {IXGBE_TDBAH(0), "TDBAH"},
 238         {IXGBE_TDLEN(0), "TDLEN"},
 239         {IXGBE_TDH(0), "TDH"},
 240         {IXGBE_TDT(0), "TDT"},
 241         {IXGBE_TXDCTL(0), "TXDCTL"},
 242
 243         /* List Terminator */
 244         {}
 245 };
 246
 247
 248 /*
 249  * ixgbe_regdump - register printout routine
 250  */
 251 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
 252 {
 253         int i = 0, j = 0;
 254         char rname[16];
 255         u32 regs[64];
 256
 257         switch (reginfo->ofs) {
 258         case IXGBE_SRRCTL(0):
 259                 for (i = 0; i < 64; i++)
 260                         regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
 261                 break;
 262         case IXGBE_DCA_RXCTRL(0):
 263                 for (i = 0; i < 64; i++)
 264                         regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
 265                 break;
 266         case IXGBE_RDLEN(0):
 267                 for (i = 0; i < 64; i++)
 268                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
 269                 break;
 270         case IXGBE_RDH(0):
 271                 for (i = 0; i < 64; i++)
 272                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
 273                 break;
 274         case IXGBE_RDT(0):
 275                 for (i = 0; i < 64; i++)
 276                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
 277                 break;
 278         case IXGBE_RXDCTL(0):
 279                 for (i = 0; i < 64; i++)
 280                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
 281                 break;
 282         case IXGBE_RDBAL(0):
 283                 for (i = 0; i < 64; i++)
 284                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
 285                 break;
 286         case IXGBE_RDBAH(0):
 287                 for (i = 0; i < 64; i++)
 288                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
 289                 break;
 290         case IXGBE_TDBAL(0):
 291                 for (i = 0; i < 64; i++)
 292                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
 293                 break;
 294         case IXGBE_TDBAH(0):
 295                 for (i = 0; i < 64; i++)
 296                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
 297                 break;
 298         case IXGBE_TDLEN(0):
 299                 for (i = 0; i < 64; i++)
 300                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
 301                 break;
 302         case IXGBE_TDH(0):
 303                 for (i = 0; i < 64; i++)
 304                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
 305                 break;
 306         case IXGBE_TDT(0):
 307                 for (i = 0; i < 64; i++)
 308                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
 309                 break;
 310         case IXGBE_TXDCTL(0):
 311                 for (i = 0; i < 64; i++)
 312                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
 313                 break;
 314         default:
 315                 pr_info("%-15s %08x\n", reginfo->name,
 316                         IXGBE_READ_REG(hw, reginfo->ofs));
 317                 return;
 318         }
 319
 320         for (i = 0; i < 8; i++) {
 321                 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
 322                 pr_err("%-15s", rname);
 323                 for (j = 0; j < 8; j++)
 324                         pr_cont(" %08x", regs[i*8+j]);
 325                 pr_cont("\n");
 326         }
 327
 328 }
 329
 330 /*
 331  * ixgbe_dump - Print registers, tx-rings and rx-rings
 332  */
 333 static void ixgbe_dump(struct ixgbe_adapter *adapter)
 334 {
 335         struct net_device *netdev = adapter->netdev;
 336         struct ixgbe_hw *hw = &adapter->hw;
 337         struct ixgbe_reg_info *reginfo;
 338         int n = 0;
 339         struct ixgbe_ring *tx_ring;
 340         struct ixgbe_tx_buffer *tx_buffer_info;
 341         union ixgbe_adv_tx_desc *tx_desc;
 342         struct my_u0 { u64 a; u64 b; } *u0;
 343         struct ixgbe_ring *rx_ring;
 344         union ixgbe_adv_rx_desc *rx_desc;
 345         struct ixgbe_rx_buffer *rx_buffer_info;
 346         u32 staterr;
 347         int i = 0;
 348
 349         if (!netif_msg_hw(adapter))
 350                 return;
 351
 352         /* Print netdevice Info */
 353         if (netdev) {
 354                 dev_info(&adapter->pdev->dev, "Net device Info\n");
 355                 pr_info("Device Name     state            "
 356                         "trans_start      last_rx\n");
 357                 pr_info("%-15s %016lX %016lX %016lX\n",
 358                         netdev->name,
 359                         netdev->state,
 360                         netdev->trans_start,
 361                         netdev->last_rx);
 362         }
 363
 364         /* Print Registers */
 365         dev_info(&adapter->pdev->dev, "Register Dump\n");
 366         pr_info(" Register Name   Value\n");
 367         for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
 368              reginfo->name; reginfo++) {
 369                 ixgbe_regdump(hw, reginfo);
 370         }
 371
 372         /* Print TX Ring Summary */
 373         if (!netdev || !netif_running(netdev))
 374                 goto exit;
 375
 376         dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
 377         pr_info("Queue [NTU] [NTC] [bi(ntc)->dma  ] leng ntw timestamp\n");
 378         for (n = 0; n < adapter->num_tx_queues; n++) {
 379                 tx_ring = adapter->tx_ring[n];
 380                 tx_buffer_info =
 381                         &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
 382                 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
 383                            n, tx_ring->next_to_use, tx_ring->next_to_clean,
 384                            (u64)tx_buffer_info->dma,
 385                            tx_buffer_info->length,
 386                            tx_buffer_info->next_to_watch,
 387                            (u64)tx_buffer_info->time_stamp);
 388         }
 389
 390         /* Print TX Rings */
 391         if (!netif_msg_tx_done(adapter))
 392                 goto rx_ring_summary;
 393
 394         dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
 395
 396         /* Transmit Descriptor Formats
 397          *
 398          * Advanced Transmit Descriptor
 399          *   +--------------------------------------------------------------+
 400          * 0 |         Buffer Address [63:0]                                |
 401          *   +--------------------------------------------------------------+
 402          * 8 |  PAYLEN  | PORTS  | IDX | STA | DCMD  |DTYP |  RSV |  DTALEN |
 403          *   +--------------------------------------------------------------+
 404          *   63       46 45    40 39 36 35 32 31   24 23 20 19              0
 405          */
 406
 407         for (n = 0; n < adapter->num_tx_queues; n++) {
 408                 tx_ring = adapter->tx_ring[n];
 409                 pr_info("------------------------------------\n");
 410                 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
 411                 pr_info("------------------------------------\n");
 412                 pr_info("T [desc]     [address 63:0  ] "
 413                         "[PlPOIdStDDt Ln] [bi->dma       ] "
 414                         "leng  ntw timestamp        bi->skb\n");
 415
 416                 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
 417                         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 418                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 419                         u0 = (struct my_u0 *)tx_desc;
 420                         pr_info("T [0x%03X]    %016llX %016llX %016llX"
 421                                 " %04X  %3X %016llX %p", i,
 422                                 le64_to_cpu(u0->a),
 423                                 le64_to_cpu(u0->b),
 424                                 (u64)tx_buffer_info->dma,
 425                                 tx_buffer_info->length,
 426                                 tx_buffer_info->next_to_watch,
 427                                 (u64)tx_buffer_info->time_stamp,
 428                                 tx_buffer_info->skb);
 429                         if (i == tx_ring->next_to_use &&
 430                                 i == tx_ring->next_to_clean)
 431                                 pr_cont(" NTC/U\n");
 432                         else if (i == tx_ring->next_to_use)
 433                                 pr_cont(" NTU\n");
 434                         else if (i == tx_ring->next_to_clean)
 435                                 pr_cont(" NTC\n");
 436                         else
 437                                 pr_cont("\n");
 438
 439                         if (netif_msg_pktdata(adapter) &&
 440                                 tx_buffer_info->dma != 0)
 441                                 print_hex_dump(KERN_INFO, "",
 442                                         DUMP_PREFIX_ADDRESS, 16, 1,
 443                                         phys_to_virt(tx_buffer_info->dma),
 444                                         tx_buffer_info->length, true);
 445                 }
 446         }
 447
 448         /* Print RX Rings Summary */
 449 rx_ring_summary:
 450         dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
 451         pr_info("Queue [NTU] [NTC]\n");
 452         for (n = 0; n < adapter->num_rx_queues; n++) {
 453                 rx_ring = adapter->rx_ring[n];
 454                 pr_info("%5d %5X %5X\n",
 455                         n, rx_ring->next_to_use, rx_ring->next_to_clean);
 456         }
 457
 458         /* Print RX Rings */
 459         if (!netif_msg_rx_status(adapter))
 460                 goto exit;
 461
 462         dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
 463
 464         /* Advanced Receive Descriptor (Read) Format
 465          *    63                                           1        0
 466          *    +-----------------------------------------------------+
 467          *  0 |       Packet Buffer Address [63:1]           |A0/NSE|
 468          *    +----------------------------------------------+------+
 469          *  8 |       Header Buffer Address [63:1]           |  DD  |
 470          *    +-----------------------------------------------------+
 471          *
 472          *
 473          * Advanced Receive Descriptor (Write-Back) Format
 474          *
 475          *   63       48 47    32 31  30      21 20 16 15   4 3     0
 476          *   +------------------------------------------------------+
 477          * 0 | Packet     IP     |SPH| HDR_LEN   | RSV|Packet|  RSS |
 478          *   | Checksum   Ident  |   |           |    | Type | Type |
 479          *   +------------------------------------------------------+
 480          * 8 | VLAN Tag | Length | Extended Error | Extended Status |
 481          *   +------------------------------------------------------+
 482          *   63       48 47    32 31            20 19               0
 483          */
 484         for (n = 0; n < adapter->num_rx_queues; n++) {
 485                 rx_ring = adapter->rx_ring[n];
 486                 pr_info("------------------------------------\n");
 487                 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
 488                 pr_info("------------------------------------\n");
 489                 pr_info("R  [desc]      [ PktBuf     A0] "
 490                         "[  HeadBuf   DD] [bi->dma       ] [bi->skb] "
 491                         "<-- Adv Rx Read format\n");
 492                 pr_info("RWB[desc]      [PcsmIpSHl PtRs] "
 493                         "[vl er S cks ln] ---------------- [bi->skb] "
 494                         "<-- Adv Rx Write-Back format\n");
 495
 496                 for (i = 0; i < rx_ring->count; i++) {
 497                         rx_buffer_info = &rx_ring->rx_buffer_info[i];
 498                         rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
 499                         u0 = (struct my_u0 *)rx_desc;
 500                         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 501                         if (staterr & IXGBE_RXD_STAT_DD) {
 502                                 /* Descriptor Done */
 503                                 pr_info("RWB[0x%03X]     %016llX "
 504                                         "%016llX ---------------- %p", i,
 505                                         le64_to_cpu(u0->a),
 506                                         le64_to_cpu(u0->b),
 507                                         rx_buffer_info->skb);
 508                         } else {
 509                                 pr_info("R  [0x%03X]     %016llX "
 510                                         "%016llX %016llX %p", i,
 511                                         le64_to_cpu(u0->a),
 512                                         le64_to_cpu(u0->b),
 513                                         (u64)rx_buffer_info->dma,
 514                                         rx_buffer_info->skb);
 515
 516                                 if (netif_msg_pktdata(adapter)) {
 517                                         print_hex_dump(KERN_INFO, "",
 518                                            DUMP_PREFIX_ADDRESS, 16, 1,
 519                                            phys_to_virt(rx_buffer_info->dma),
 520                                            rx_ring->rx_buf_len, true);
 521
 522                                         if (rx_ring->rx_buf_len
 523                                                 < IXGBE_RXBUFFER_2048)
 524                                                 print_hex_dump(KERN_INFO, "",
 525                                                   DUMP_PREFIX_ADDRESS, 16, 1,
 526                                                   phys_to_virt(
 527                                                     rx_buffer_info->page_dma +
 528                                                     rx_buffer_info->page_offset
 529                                                   ),
 530                                                   PAGE_SIZE/2, true);
 531                                 }
 532                         }
 533
 534                         if (i == rx_ring->next_to_use)
 535                                 pr_cont(" NTU\n");
 536                         else if (i == rx_ring->next_to_clean)
 537                                 pr_cont(" NTC\n");
 538                         else
 539                                 pr_cont("\n");
 540
 541                 }
 542         }
 543
 544 exit:
 545         return;
 546 }
 547
 548 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
 549 {
 550         u32 ctrl_ext;
 551
 552         /* Let firmware take over control of h/w */
 553         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 554         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 555                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
 556 }
 557
 558 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
 559 {
 560         u32 ctrl_ext;
 561
 562         /* Let firmware know the driver has taken over */
 563         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 564         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 565                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
 566 }
 567
 568 /*
 569  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
 570  * @adapter: pointer to adapter struct
 571  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
 572  * @queue: queue to map the corresponding interrupt to
 573  * @msix_vector: the vector to map to the corresponding queue
 574  *
 575  */
 576 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
 577                            u8 queue, u8 msix_vector)
 578 {
 579         u32 ivar, index;
 580         struct ixgbe_hw *hw = &adapter->hw;
 581         switch (hw->mac.type) {
 582         case ixgbe_mac_82598EB:
 583                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 584                 if (direction == -1)
 585                         direction = 0;
 586                 index = (((direction * 64) + queue) >> 2) & 0x1F;
 587                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
 588                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
 589                 ivar |= (msix_vector << (8 * (queue & 0x3)));
 590                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
 591                 break;
 592         case ixgbe_mac_82599EB:
 593         case ixgbe_mac_X540:
 594                 if (direction == -1) {
 595                         /* other causes */
 596                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 597                         index = ((queue & 1) * 8);
 598                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
 599                         ivar &= ~(0xFF << index);
 600                         ivar |= (msix_vector << index);
 601                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
 602                         break;
 603                 } else {
 604                         /* tx or rx causes */
 605                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 606                         index = ((16 * (queue & 1)) + (8 * direction));
 607                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
 608                         ivar &= ~(0xFF << index);
 609                         ivar |= (msix_vector << index);
 610                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
 611                         break;
 612                 }
 613         default:
 614                 break;
 615         }
 616 }
 617
 618 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
 619                                           u64 qmask)
 620 {
 621         u32 mask;
 622
 623         switch (adapter->hw.mac.type) {
 624         case ixgbe_mac_82598EB:
 625                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
 626                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
 627                 break;
 628         case ixgbe_mac_82599EB:
 629         case ixgbe_mac_X540:
 630                 mask = (qmask & 0xFFFFFFFF);
 631                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
 632                 mask = (qmask >> 32);
 633                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
 634                 break;
 635         default:
 636                 break;
 637         }
 638 }
 639
 640 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
 641                                       struct ixgbe_tx_buffer *tx_buffer_info)
 642 {
 643         if (tx_buffer_info->dma) {
 644                 if (tx_buffer_info->mapped_as_page)
 645                         dma_unmap_page(tx_ring->dev,
 646                                        tx_buffer_info->dma,
 647                                        tx_buffer_info->length,
 648                                        DMA_TO_DEVICE);
 649                 else
 650                         dma_unmap_single(tx_ring->dev,
 651                                          tx_buffer_info->dma,
 652                                          tx_buffer_info->length,
 653                                          DMA_TO_DEVICE);
 654                 tx_buffer_info->dma = 0;
 655         }
 656         if (tx_buffer_info->skb) {
 657                 dev_kfree_skb_any(tx_buffer_info->skb);
 658                 tx_buffer_info->skb = NULL;
 659         }
 660         tx_buffer_info->time_stamp = 0;
 661         /* tx_buffer_info must be completely set up in the transmit path */
 662 }
 663
 664 /**
 665  * ixgbe_dcb_txq_to_tc - convert a reg index to a traffic class
 666  * @adapter: driver private struct
 667  * @index: reg idx of queue to query (0-127)
 668  *
 669  * Helper function to determine the traffic index for a particular
 670  * register index.
 671  *
 672  * Returns : a tc index for use in range 0-7, or 0-3
 673  */
 674 static u8 ixgbe_dcb_txq_to_tc(struct ixgbe_adapter *adapter, u8 reg_idx)
 675 {
 676         int tc = -1;
 677         int dcb_i = netdev_get_num_tc(adapter->netdev);
 678
 679         /* if DCB is not enabled the queues have no TC */
 680         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
 681                 return tc;
 682
 683         /* check valid range */
 684         if (reg_idx >= adapter->hw.mac.max_tx_queues)
 685                 return tc;
 686
 687         switch (adapter->hw.mac.type) {
 688         case ixgbe_mac_82598EB:
 689                 tc = reg_idx >> 2;
 690                 break;
 691         default:
 692                 if (dcb_i != 4 && dcb_i != 8)
 693                         break;
 694
 695                 /* if VMDq is enabled the lowest order bits determine TC */
 696                 if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED |
 697                                       IXGBE_FLAG_VMDQ_ENABLED)) {
 698                         tc = reg_idx & (dcb_i - 1);
 699                         break;
 700                 }
 701
 702                 /*
 703                  * Convert the reg_idx into the correct TC. This bitmask
 704                  * targets the last full 32 ring traffic class and assigns
 705                  * it a value of 1. From there the rest of the rings are
 706                  * based on shifting the mask further up to include the
 707                  * reg_idx / 16 and then reg_idx / 8. It assumes dcB_i
 708                  * will only ever be 8 or 4 and that reg_idx will never
 709                  * be greater then 128. The code without the power of 2
 710                  * optimizations would be:
 711                  * (((reg_idx % 32) + 32) * dcb_i) >> (9 - reg_idx / 32)
 712                  */
 713                 tc = ((reg_idx & 0X1F) + 0x20) * dcb_i;
 714                 tc >>= 9 - (reg_idx >> 5);
 715         }
 716
 717         return tc;
 718 }
 719
 720 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
 721 {
 722         struct ixgbe_hw *hw = &adapter->hw;
 723         struct ixgbe_hw_stats *hwstats = &adapter->stats;
 724         u32 data = 0;
 725         u32 xoff[8] = {0};
 726         int i;
 727
 728         if ((hw->fc.current_mode == ixgbe_fc_full) ||
 729             (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
 730                 switch (hw->mac.type) {
 731                 case ixgbe_mac_82598EB:
 732                         data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
 733                         break;
 734                 default:
 735                         data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
 736                 }
 737                 hwstats->lxoffrxc += data;
 738
 739                 /* refill credits (no tx hang) if we received xoff */
 740                 if (!data)
 741                         return;
 742
 743                 for (i = 0; i < adapter->num_tx_queues; i++)
 744                         clear_bit(__IXGBE_HANG_CHECK_ARMED,
 745                                   &adapter->tx_ring[i]->state);
 746                 return;
 747         } else if (!(adapter->dcb_cfg.pfc_mode_enable))
 748                 return;
 749
 750         /* update stats for each tc, only valid with PFC enabled */
 751         for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
 752                 switch (hw->mac.type) {
 753                 case ixgbe_mac_82598EB:
 754                         xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
 755                         break;
 756                 default:
 757                         xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
 758                 }
 759                 hwstats->pxoffrxc[i] += xoff[i];
 760         }
 761
 762         /* disarm tx queues that have received xoff frames */
 763         for (i = 0; i < adapter->num_tx_queues; i++) {
 764                 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
 765                 u32 tc = ixgbe_dcb_txq_to_tc(adapter, tx_ring->reg_idx);
 766
 767                 if (xoff[tc])
 768                         clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
 769         }
 770 }
 771
 772 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
 773 {
 774         return ring->tx_stats.completed;
 775 }
 776
 777 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
 778 {
 779         struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
 780         struct ixgbe_hw *hw = &adapter->hw;
 781
 782         u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
 783         u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
 784
 785         if (head != tail)
 786                 return (head < tail) ?
 787                         tail - head : (tail + ring->count - head);
 788
 789         return 0;
 790 }
 791
 792 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
 793 {
 794         u32 tx_done = ixgbe_get_tx_completed(tx_ring);
 795         u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
 796         u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
 797         bool ret = false;
 798
 799         clear_check_for_tx_hang(tx_ring);
 800
 801         /*
 802          * Check for a hung queue, but be thorough. This verifies
 803          * that a transmit has been completed since the previous
 804          * check AND there is at least one packet pending. The
 805          * ARMED bit is set to indicate a potential hang. The
 806          * bit is cleared if a pause frame is received to remove
 807          * false hang detection due to PFC or 802.3x frames. By
 808          * requiring this to fail twice we avoid races with
 809          * pfc clearing the ARMED bit and conditions where we
 810          * run the check_tx_hang logic with a transmit completion
 811          * pending but without time to complete it yet.
 812          */
 813         if ((tx_done_old == tx_done) && tx_pending) {
 814                 /* make sure it is true for two checks in a row */
 815                 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
 816                                        &tx_ring->state);
 817         } else {
 818                 /* update completed stats and continue */
 819                 tx_ring->tx_stats.tx_done_old = tx_done;
 820                 /* reset the countdown */
 821                 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
 822         }
 823
 824         return ret;
 825 }
 826
 827 #define IXGBE_MAX_TXD_PWR       14
 828 #define IXGBE_MAX_DATA_PER_TXD  (1 << IXGBE_MAX_TXD_PWR)
 829
 830 /* Tx Descriptors needed, worst case */
 831 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
 832                          (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
 833 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
 834         MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
 835
 836 /**
 837  * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
 838  * @adapter: driver private struct
 839  **/
 840 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
 841 {
 842
 843         /* Do the reset outside of interrupt context */
 844         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
 845                 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
 846                 ixgbe_service_event_schedule(adapter);
 847         }
 848 }
 849
 850 /**
 851  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
 852  * @q_vector: structure containing interrupt and ring information
 853  * @tx_ring: tx ring to clean
 854  **/
 855 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
 856                                struct ixgbe_ring *tx_ring)
 857 {
 858         struct ixgbe_adapter *adapter = q_vector->adapter;
 859         union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
 860         struct ixgbe_tx_buffer *tx_buffer_info;
 861         unsigned int total_bytes = 0, total_packets = 0;
 862         u16 i, eop, count = 0;
 863
 864         i = tx_ring->next_to_clean;
 865         eop = tx_ring->tx_buffer_info[i].next_to_watch;
 866         eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
 867
 868         while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
 869                (count < tx_ring->work_limit)) {
 870                 bool cleaned = false;
 871                 rmb(); /* read buffer_info after eop_desc */
 872                 for ( ; !cleaned; count++) {
 873                         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 874                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 875
 876                         tx_desc->wb.status = 0;
 877                         cleaned = (i == eop);
 878
 879                         i++;
 880                         if (i == tx_ring->count)
 881                                 i = 0;
 882
 883                         if (cleaned && tx_buffer_info->skb) {
 884                                 total_bytes += tx_buffer_info->bytecount;
 885                                 total_packets += tx_buffer_info->gso_segs;
 886                         }
 887
 888                         ixgbe_unmap_and_free_tx_resource(tx_ring,
 889                                                          tx_buffer_info);
 890                 }
 891
 892                 tx_ring->tx_stats.completed++;
 893                 eop = tx_ring->tx_buffer_info[i].next_to_watch;
 894                 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
 895         }
 896
 897         tx_ring->next_to_clean = i;
 898         tx_ring->total_bytes += total_bytes;
 899         tx_ring->total_packets += total_packets;
 900         u64_stats_update_begin(&tx_ring->syncp);
 901         tx_ring->stats.packets += total_packets;
 902         tx_ring->stats.bytes += total_bytes;
 903         u64_stats_update_end(&tx_ring->syncp);
 904
 905         if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
 906                 /* schedule immediate reset if we believe we hung */
 907                 struct ixgbe_hw *hw = &adapter->hw;
 908                 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
 909                 e_err(drv, "Detected Tx Unit Hang\n"
 910                         "  Tx Queue             <%d>\n"
 911                         "  TDH, TDT             <%x>, <%x>\n"
 912                         "  next_to_use          <%x>\n"
 913                         "  next_to_clean        <%x>\n"
 914                         "tx_buffer_info[next_to_clean]\n"
 915                         "  time_stamp           <%lx>\n"
 916                         "  jiffies              <%lx>\n",
 917                         tx_ring->queue_index,
 918                         IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
 919                         IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
 920                         tx_ring->next_to_use, eop,
 921                         tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
 922
 923                 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
 924
 925                 e_info(probe,
 926                        "tx hang %d detected on queue %d, resetting adapter\n",
 927                         adapter->tx_timeout_count + 1, tx_ring->queue_index);
 928
 929                 /* schedule immediate reset if we believe we hung */
 930                 ixgbe_tx_timeout_reset(adapter);
 931
 932                 /* the adapter is about to reset, no point in enabling stuff */
 933                 return true;
 934         }
 935
 936 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 937         if (unlikely(count && netif_carrier_ok(tx_ring->netdev) &&
 938                      (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 939                 /* Make sure that anybody stopping the queue after this
 940                  * sees the new next_to_clean.
 941                  */
 942                 smp_mb();
 943                 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
 944                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
 945                         netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
 946                         ++tx_ring->tx_stats.restart_queue;
 947                 }
 948         }
 949
 950         return count < tx_ring->work_limit;
 951 }
 952
 953 #ifdef CONFIG_IXGBE_DCA
 954 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
 955                                 struct ixgbe_ring *rx_ring,
 956                                 int cpu)
 957 {
 958         struct ixgbe_hw *hw = &adapter->hw;
 959         u32 rxctrl;
 960         u8 reg_idx = rx_ring->reg_idx;
 961
 962         rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
 963         switch (hw->mac.type) {
 964         case ixgbe_mac_82598EB:
 965                 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
 966                 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 967                 break;
 968         case ixgbe_mac_82599EB:
 969         case ixgbe_mac_X540:
 970                 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
 971                 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 972                            IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
 973                 break;
 974         default:
 975                 break;
 976         }
 977         rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
 978         rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
 979         rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
 980         IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
 981 }
 982
 983 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
 984                                 struct ixgbe_ring *tx_ring,
 985                                 int cpu)
 986 {
 987         struct ixgbe_hw *hw = &adapter->hw;
 988         u32 txctrl;
 989         u8 reg_idx = tx_ring->reg_idx;
 990
 991         switch (hw->mac.type) {
 992         case ixgbe_mac_82598EB:
 993                 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
 994                 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
 995                 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 996                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 997                 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
 998                 break;
 999         case ixgbe_mac_82599EB:
1000         case ixgbe_mac_X540:
1001                 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
1002                 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
1003                 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
1004                            IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
1005                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
1006                 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
1007                 break;
1008         default:
1009                 break;
1010         }
1011 }
1012
1013 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1014 {
1015         struct ixgbe_adapter *adapter = q_vector->adapter;
1016         int cpu = get_cpu();
1017         long r_idx;
1018         int i;
1019
1020         if (q_vector->cpu == cpu)
1021                 goto out_no_update;
1022
1023         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1024         for (i = 0; i < q_vector->txr_count; i++) {
1025                 ixgbe_update_tx_dca(adapter, adapter->tx_ring[r_idx], cpu);
1026                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1027                                       r_idx + 1);
1028         }
1029
1030         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1031         for (i = 0; i < q_vector->rxr_count; i++) {
1032                 ixgbe_update_rx_dca(adapter, adapter->rx_ring[r_idx], cpu);
1033                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1034                                       r_idx + 1);
1035         }
1036
1037         q_vector->cpu = cpu;
1038 out_no_update:
1039         put_cpu();
1040 }
1041
1042 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1043 {
1044         int num_q_vectors;
1045         int i;
1046
1047         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1048                 return;
1049
1050         /* always use CB2 mode, difference is masked in the CB driver */
1051         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1052
1053         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
1054                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1055         else
1056                 num_q_vectors = 1;
1057
1058         for (i = 0; i < num_q_vectors; i++) {
1059                 adapter->q_vector[i]->cpu = -1;
1060                 ixgbe_update_dca(adapter->q_vector[i]);
1061         }
1062 }
1063
1064 static int __ixgbe_notify_dca(struct device *dev, void *data)
1065 {
1066         struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
1067         unsigned long event = *(unsigned long *)data;
1068
1069         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1070                 return 0;
1071
1072         switch (event) {
1073         case DCA_PROVIDER_ADD:
1074                 /* if we're already enabled, don't do it again */
1075                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1076                         break;
1077                 if (dca_add_requester(dev) == 0) {
1078                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1079                         ixgbe_setup_dca(adapter);
1080                         break;
1081                 }
1082                 /* Fall Through since DCA is disabled. */
1083         case DCA_PROVIDER_REMOVE:
1084                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1085                         dca_remove_requester(dev);
1086                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1087                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1088                 }
1089                 break;
1090         }
1091
1092         return 0;
1093 }
1094 #endif /* CONFIG_IXGBE_DCA */
1095
1096 static inline void ixgbe_rx_hash(union ixgbe_adv_rx_desc *rx_desc,
1097                                  struct sk_buff *skb)
1098 {
1099         skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
1100 }
1101
1102 /**
1103  * ixgbe_receive_skb - Send a completed packet up the stack
1104  * @adapter: board private structure
1105  * @skb: packet to send up
1106  * @status: hardware indication of status of receive
1107  * @rx_ring: rx descriptor ring (for a specific queue) to setup
1108  * @rx_desc: rx descriptor
1109  **/
1110 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
1111                               struct sk_buff *skb, u8 status,
1112                               struct ixgbe_ring *ring,
1113                               union ixgbe_adv_rx_desc *rx_desc)
1114 {
1115         struct ixgbe_adapter *adapter = q_vector->adapter;
1116         struct napi_struct *napi = &q_vector->napi;
1117         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
1118         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
1119
1120         if (is_vlan && (tag & VLAN_VID_MASK))
1121                 __vlan_hwaccel_put_tag(skb, tag);
1122
1123         if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1124                 napi_gro_receive(napi, skb);
1125         else
1126                 netif_rx(skb);
1127 }
1128
1129 /**
1130  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1131  * @adapter: address of board private structure
1132  * @status_err: hardware indication of status of receive
1133  * @skb: skb currently being received and modified
1134  **/
1135 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
1136                                      union ixgbe_adv_rx_desc *rx_desc,
1137                                      struct sk_buff *skb)
1138 {
1139         u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
1140
1141         skb_checksum_none_assert(skb);
1142
1143         /* Rx csum disabled */
1144         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
1145                 return;
1146
1147         /* if IP and error */
1148         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1149             (status_err & IXGBE_RXDADV_ERR_IPE)) {
1150                 adapter->hw_csum_rx_error++;
1151                 return;
1152         }
1153
1154         if (!(status_err & IXGBE_RXD_STAT_L4CS))
1155                 return;
1156
1157         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
1158                 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1159
1160                 /*
1161                  * 82599 errata, UDP frames with a 0 checksum can be marked as
1162                  * checksum errors.
1163                  */
1164                 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1165                     (adapter->hw.mac.type == ixgbe_mac_82599EB))
1166                         return;
1167
1168                 adapter->hw_csum_rx_error++;
1169                 return;
1170         }
1171
1172         /* It must be a TCP or UDP packet with a valid checksum */
1173         skb->ip_summed = CHECKSUM_UNNECESSARY;
1174 }
1175
1176 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1177 {
1178         /*
1179          * Force memory writes to complete before letting h/w
1180          * know there are new descriptors to fetch.  (Only
1181          * applicable for weak-ordered memory model archs,
1182          * such as IA-64).
1183          */
1184         wmb();
1185         writel(val, rx_ring->tail);
1186 }
1187
1188 /**
1189  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1190  * @rx_ring: ring to place buffers on
1191  * @cleaned_count: number of buffers to replace
1192  **/
1193 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1194 {
1195         union ixgbe_adv_rx_desc *rx_desc;
1196         struct ixgbe_rx_buffer *bi;
1197         struct sk_buff *skb;
1198         u16 i = rx_ring->next_to_use;
1199
1200         /* do nothing if no valid netdev defined */
1201         if (!rx_ring->netdev)
1202                 return;
1203
1204         while (cleaned_count--) {
1205                 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1206                 bi = &rx_ring->rx_buffer_info[i];
1207                 skb = bi->skb;
1208
1209                 if (!skb) {
1210                         skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1211                                                         rx_ring->rx_buf_len);
1212                         if (!skb) {
1213                                 rx_ring->rx_stats.alloc_rx_buff_failed++;
1214                                 goto no_buffers;
1215                         }
1216                         /* initialize queue mapping */
1217                         skb_record_rx_queue(skb, rx_ring->queue_index);
1218                         bi->skb = skb;
1219                 }
1220
1221                 if (!bi->dma) {
1222                         bi->dma = dma_map_single(rx_ring->dev,
1223                                                  skb->data,
1224                                                  rx_ring->rx_buf_len,
1225                                                  DMA_FROM_DEVICE);
1226                         if (dma_mapping_error(rx_ring->dev, bi->dma)) {
1227                                 rx_ring->rx_stats.alloc_rx_buff_failed++;
1228                                 bi->dma = 0;
1229                                 goto no_buffers;
1230                         }
1231                 }
1232
1233                 if (ring_is_ps_enabled(rx_ring)) {
1234                         if (!bi->page) {
1235                                 bi->page = netdev_alloc_page(rx_ring->netdev);
1236                                 if (!bi->page) {
1237                                         rx_ring->rx_stats.alloc_rx_page_failed++;
1238                                         goto no_buffers;
1239                                 }
1240                         }
1241
1242                         if (!bi->page_dma) {
1243                                 /* use a half page if we're re-using */
1244                                 bi->page_offset ^= PAGE_SIZE / 2;
1245                                 bi->page_dma = dma_map_page(rx_ring->dev,
1246                                                             bi->page,
1247                                                             bi->page_offset,
1248                                                             PAGE_SIZE / 2,
1249                                                             DMA_FROM_DEVICE);
1250                                 if (dma_mapping_error(rx_ring->dev,
1251                                                       bi->page_dma)) {
1252                                         rx_ring->rx_stats.alloc_rx_page_failed++;
1253                                         bi->page_dma = 0;
1254                                         goto no_buffers;
1255                                 }
1256                         }
1257
1258                         /* Refresh the desc even if buffer_addrs didn't change
1259                          * because each write-back erases this info. */
1260                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1261                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1262                 } else {
1263                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1264                         rx_desc->read.hdr_addr = 0;
1265                 }
1266
1267                 i++;
1268                 if (i == rx_ring->count)
1269                         i = 0;
1270         }
1271
1272 no_buffers:
1273         if (rx_ring->next_to_use != i) {
1274                 rx_ring->next_to_use = i;
1275                 ixgbe_release_rx_desc(rx_ring, i);
1276         }
1277 }
1278
1279 static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
1280 {
1281         /* HW will not DMA in data larger than the given buffer, even if it
1282          * parses the (NFS, of course) header to be larger.  In that case, it
1283          * fills the header buffer and spills the rest into the page.
1284          */
1285         u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1286         u16 hlen = (hdr_info &  IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1287                     IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1288         if (hlen > IXGBE_RX_HDR_SIZE)
1289                 hlen = IXGBE_RX_HDR_SIZE;
1290         return hlen;
1291 }
1292
1293 /**
1294  * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1295  * @skb: pointer to the last skb in the rsc queue
1296  *
1297  * This function changes a queue full of hw rsc buffers into a completed
1298  * packet.  It uses the ->prev pointers to find the first packet and then
1299  * turns it into the frag list owner.
1300  **/
1301 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
1302 {
1303         unsigned int frag_list_size = 0;
1304         unsigned int skb_cnt = 1;
1305
1306         while (skb->prev) {
1307                 struct sk_buff *prev = skb->prev;
1308                 frag_list_size += skb->len;
1309                 skb->prev = NULL;
1310                 skb = prev;
1311                 skb_cnt++;
1312         }
1313
1314         skb_shinfo(skb)->frag_list = skb->next;
1315         skb->next = NULL;
1316         skb->len += frag_list_size;
1317         skb->data_len += frag_list_size;
1318         skb->truesize += frag_list_size;
1319         IXGBE_RSC_CB(skb)->skb_cnt = skb_cnt;
1320
1321         return skb;
1322 }
1323
1324 static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc *rx_desc)
1325 {
1326         return !!(le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1327                 IXGBE_RXDADV_RSCCNT_MASK);
1328 }
1329
1330 static void ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1331                                struct ixgbe_ring *rx_ring,
1332                                int *work_done, int work_to_do)
1333 {
1334         struct ixgbe_adapter *adapter = q_vector->adapter;
1335         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1336         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1337         struct sk_buff *skb;
1338         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1339         const int current_node = numa_node_id();
1340 #ifdef IXGBE_FCOE
1341         int ddp_bytes = 0;
1342 #endif /* IXGBE_FCOE */
1343         u32 staterr;
1344         u16 i;
1345         u16 cleaned_count = 0;
1346         bool pkt_is_rsc = false;
1347
1348         i = rx_ring->next_to_clean;
1349         rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1350         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1351
1352         while (staterr & IXGBE_RXD_STAT_DD) {
1353                 u32 upper_len = 0;
1354
1355                 rmb(); /* read descriptor and rx_buffer_info after status DD */
1356
1357                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1358
1359                 skb = rx_buffer_info->skb;
1360                 rx_buffer_info->skb = NULL;
1361                 prefetch(skb->data);
1362
1363                 if (ring_is_rsc_enabled(rx_ring))
1364                         pkt_is_rsc = ixgbe_get_rsc_state(rx_desc);
1365
1366                 /* if this is a skb from previous receive DMA will be 0 */
1367                 if (rx_buffer_info->dma) {
1368                         u16 hlen;
1369                         if (pkt_is_rsc &&
1370                             !(staterr & IXGBE_RXD_STAT_EOP) &&
1371                             !skb->prev) {
1372                                 /*
1373                                  * When HWRSC is enabled, delay unmapping
1374                                  * of the first packet. It carries the
1375                                  * header information, HW may still
1376                                  * access the header after the writeback.
1377                                  * Only unmap it when EOP is reached
1378                                  */
1379                                 IXGBE_RSC_CB(skb)->delay_unmap = true;
1380                                 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
1381                         } else {
1382                                 dma_unmap_single(rx_ring->dev,
1383                                                  rx_buffer_info->dma,
1384                                                  rx_ring->rx_buf_len,
1385                                                  DMA_FROM_DEVICE);
1386                         }
1387                         rx_buffer_info->dma = 0;
1388
1389                         if (ring_is_ps_enabled(rx_ring)) {
1390                                 hlen = ixgbe_get_hlen(rx_desc);
1391                                 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1392                         } else {
1393                                 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1394                         }
1395
1396                         skb_put(skb, hlen);
1397                 } else {
1398                         /* assume packet split since header is unmapped */
1399                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1400                 }
1401
1402                 if (upper_len) {
1403                         dma_unmap_page(rx_ring->dev,
1404                                        rx_buffer_info->page_dma,
1405                                        PAGE_SIZE / 2,
1406                                        DMA_FROM_DEVICE);
1407                         rx_buffer_info->page_dma = 0;
1408                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1409                                            rx_buffer_info->page,
1410                                            rx_buffer_info->page_offset,
1411                                            upper_len);
1412
1413                         if ((page_count(rx_buffer_info->page) == 1) &&
1414                             (page_to_nid(rx_buffer_info->page) == current_node))
1415                                 get_page(rx_buffer_info->page);
1416                         else
1417                                 rx_buffer_info->page = NULL;
1418
1419                         skb->len += upper_len;
1420                         skb->data_len += upper_len;
1421                         skb->truesize += upper_len;
1422                 }
1423
1424                 i++;
1425                 if (i == rx_ring->count)
1426                         i = 0;
1427
1428                 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
1429                 prefetch(next_rxd);
1430                 cleaned_count++;
1431
1432                 if (pkt_is_rsc) {
1433                         u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1434                                      IXGBE_RXDADV_NEXTP_SHIFT;
1435                         next_buffer = &rx_ring->rx_buffer_info[nextp];
1436                 } else {
1437                         next_buffer = &rx_ring->rx_buffer_info[i];
1438                 }
1439
1440                 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
1441                         if (ring_is_ps_enabled(rx_ring)) {
1442                                 rx_buffer_info->skb = next_buffer->skb;
1443                                 rx_buffer_info->dma = next_buffer->dma;
1444                                 next_buffer->skb = skb;
1445                                 next_buffer->dma = 0;
1446                         } else {
1447                                 skb->next = next_buffer->skb;
1448                                 skb->next->prev = skb;
1449                         }
1450                         rx_ring->rx_stats.non_eop_descs++;
1451                         goto next_desc;
1452                 }
1453
1454                 if (skb->prev) {
1455                         skb = ixgbe_transform_rsc_queue(skb);
1456                         /* if we got here without RSC the packet is invalid */
1457                         if (!pkt_is_rsc) {
1458                                 __pskb_trim(skb, 0);
1459                                 rx_buffer_info->skb = skb;
1460                                 goto next_desc;
1461                         }
1462                 }
1463
1464                 if (ring_is_rsc_enabled(rx_ring)) {
1465                         if (IXGBE_RSC_CB(skb)->delay_unmap) {
1466                                 dma_unmap_single(rx_ring->dev,
1467                                                  IXGBE_RSC_CB(skb)->dma,
1468                                                  rx_ring->rx_buf_len,
1469                                                  DMA_FROM_DEVICE);
1470                                 IXGBE_RSC_CB(skb)->dma = 0;
1471                                 IXGBE_RSC_CB(skb)->delay_unmap = false;
1472                         }
1473                 }
1474                 if (pkt_is_rsc) {
1475                         if (ring_is_ps_enabled(rx_ring))
1476                                 rx_ring->rx_stats.rsc_count +=
1477                                         skb_shinfo(skb)->nr_frags;
1478                         else
1479                                 rx_ring->rx_stats.rsc_count +=
1480                                         IXGBE_RSC_CB(skb)->skb_cnt;
1481                         rx_ring->rx_stats.rsc_flush++;
1482                 }
1483
1484                 /* ERR_MASK will only have valid bits if EOP set */
1485                 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
1486                         /* trim packet back to size 0 and recycle it */
1487                         __pskb_trim(skb, 0);
1488                         rx_buffer_info->skb = skb;
1489                         goto next_desc;
1490                 }
1491
1492                 ixgbe_rx_checksum(adapter, rx_desc, skb);
1493                 if (adapter->netdev->features & NETIF_F_RXHASH)
1494                         ixgbe_rx_hash(rx_desc, skb);
1495
1496                 /* probably a little skewed due to removing CRC */
1497                 total_rx_bytes += skb->len;
1498                 total_rx_packets++;
1499
1500                 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1501 #ifdef IXGBE_FCOE
1502                 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1503                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1504                         ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1505                         if (!ddp_bytes)
1506                                 goto next_desc;
1507                 }
1508 #endif /* IXGBE_FCOE */
1509                 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
1510
1511 next_desc:
1512                 rx_desc->wb.upper.status_error = 0;
1513
1514                 (*work_done)++;
1515                 if (*work_done >= work_to_do)
1516                         break;
1517
1518                 /* return some buffers to hardware, one at a time is too slow */
1519                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1520                         ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1521                         cleaned_count = 0;
1522                 }
1523
1524                 /* use prefetched values */
1525                 rx_desc = next_rxd;
1526                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1527         }
1528
1529         rx_ring->next_to_clean = i;
1530         cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1531
1532         if (cleaned_count)
1533                 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1534
1535 #ifdef IXGBE_FCOE
1536         /* include DDPed FCoE data */
1537         if (ddp_bytes > 0) {
1538                 unsigned int mss;
1539
1540                 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
1541                         sizeof(struct fc_frame_header) -
1542                         sizeof(struct fcoe_crc_eof);
1543                 if (mss > 512)
1544                         mss &= ~511;
1545                 total_rx_bytes += ddp_bytes;
1546                 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1547         }
1548 #endif /* IXGBE_FCOE */
1549
1550         rx_ring->total_packets += total_rx_packets;
1551         rx_ring->total_bytes += total_rx_bytes;
1552         u64_stats_update_begin(&rx_ring->syncp);
1553         rx_ring->stats.packets += total_rx_packets;
1554         rx_ring->stats.bytes += total_rx_bytes;
1555         u64_stats_update_end(&rx_ring->syncp);
1556 }
1557
1558 static int ixgbe_clean_rxonly(struct napi_struct *, int);
1559 /**
1560  * ixgbe_configure_msix - Configure MSI-X hardware
1561  * @adapter: board private structure
1562  *
1563  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1564  * interrupts.
1565  **/
1566 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1567 {
1568         struct ixgbe_q_vector *q_vector;
1569         int i, q_vectors, v_idx, r_idx;
1570         u32 mask;
1571
1572         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1573
1574         /*
1575          * Populate the IVAR table and set the ITR values to the
1576          * corresponding register.
1577          */
1578         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1579                 q_vector = adapter->q_vector[v_idx];
1580                 /* XXX for_each_set_bit(...) */
1581                 r_idx = find_first_bit(q_vector->rxr_idx,
1582                                        adapter->num_rx_queues);
1583
1584                 for (i = 0; i < q_vector->rxr_count; i++) {
1585                         u8 reg_idx = adapter->rx_ring[r_idx]->reg_idx;
1586                         ixgbe_set_ivar(adapter, 0, reg_idx, v_idx);
1587                         r_idx = find_next_bit(q_vector->rxr_idx,
1588                                               adapter->num_rx_queues,
1589                                               r_idx + 1);
1590                 }
1591                 r_idx = find_first_bit(q_vector->txr_idx,
1592                                        adapter->num_tx_queues);
1593
1594                 for (i = 0; i < q_vector->txr_count; i++) {
1595                         u8 reg_idx = adapter->tx_ring[r_idx]->reg_idx;
1596                         ixgbe_set_ivar(adapter, 1, reg_idx, v_idx);
1597                         r_idx = find_next_bit(q_vector->txr_idx,
1598                                               adapter->num_tx_queues,
1599                                               r_idx + 1);
1600                 }
1601
1602                 if (q_vector->txr_count && !q_vector->rxr_count)
1603                         /* tx only */
1604                         q_vector->eitr = adapter->tx_eitr_param;
1605                 else if (q_vector->rxr_count)
1606                         /* rx or mixed */
1607                         q_vector->eitr = adapter->rx_eitr_param;
1608
1609                 ixgbe_write_eitr(q_vector);
1610                 /* If Flow Director is enabled, set interrupt affinity */
1611                 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
1612                     (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
1613                         /*
1614                          * Allocate the affinity_hint cpumask, assign the mask
1615                          * for this vector, and set our affinity_hint for
1616                          * this irq.
1617                          */
1618                         if (!alloc_cpumask_var(&q_vector->affinity_mask,
1619                                                GFP_KERNEL))
1620                                 return;
1621                         cpumask_set_cpu(v_idx, q_vector->affinity_mask);
1622                         irq_set_affinity_hint(adapter->msix_entries[v_idx].vector,
1623                                               q_vector->affinity_mask);
1624                 }
1625         }
1626
1627         switch (adapter->hw.mac.type) {
1628         case ixgbe_mac_82598EB:
1629                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1630                                v_idx);
1631                 break;
1632         case ixgbe_mac_82599EB:
1633         case ixgbe_mac_X540:
1634                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1635                 break;
1636
1637         default:
1638                 break;
1639         }
1640         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1641
1642         /* set up to autoclear timer, and the vectors */
1643         mask = IXGBE_EIMS_ENABLE_MASK;
1644         if (adapter->num_vfs)
1645                 mask &= ~(IXGBE_EIMS_OTHER |
1646                           IXGBE_EIMS_MAILBOX |
1647                           IXGBE_EIMS_LSC);
1648         else
1649                 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1650         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1651 }
1652
1653 enum latency_range {
1654         lowest_latency = 0,
1655         low_latency = 1,
1656         bulk_latency = 2,
1657         latency_invalid = 255
1658 };
1659
1660 /**
1661  * ixgbe_update_itr - update the dynamic ITR value based on statistics
1662  * @adapter: pointer to adapter
1663  * @eitr: eitr setting (ints per sec) to give last timeslice
1664  * @itr_setting: current throttle rate in ints/second
1665  * @packets: the number of packets during this measurement interval
1666  * @bytes: the number of bytes during this measurement interval
1667  *
1668  *      Stores a new ITR value based on packets and byte
1669  *      counts during the last interrupt.  The advantage of per interrupt
1670  *      computation is faster updates and more accurate ITR for the current
1671  *      traffic pattern.  Constants in this function were computed
1672  *      based on theoretical maximum wire speed and thresholds were set based
1673  *      on testing data as well as attempting to minimize response time
1674  *      while increasing bulk throughput.
1675  *      this functionality is controlled by the InterruptThrottleRate module
1676  *      parameter (see ixgbe_param.c)
1677  **/
1678 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
1679                            u32 eitr, u8 itr_setting,
1680                            int packets, int bytes)
1681 {
1682         unsigned int retval = itr_setting;
1683         u32 timepassed_us;
1684         u64 bytes_perint;
1685
1686         if (packets == 0)
1687                 goto update_itr_done;
1688
1689
1690         /* simple throttlerate management
1691          *    0-20MB/s lowest (100000 ints/s)
1692          *   20-100MB/s low   (20000 ints/s)
1693          *  100-1249MB/s bulk (8000 ints/s)
1694          */
1695         /* what was last interrupt timeslice? */
1696         timepassed_us = 1000000/eitr;
1697         bytes_perint = bytes / timepassed_us; /* bytes/usec */
1698
1699         switch (itr_setting) {
1700         case lowest_latency:
1701                 if (bytes_perint > adapter->eitr_low)
1702                         retval = low_latency;
1703                 break;
1704         case low_latency:
1705                 if (bytes_perint > adapter->eitr_high)
1706                         retval = bulk_latency;
1707                 else if (bytes_perint <= adapter->eitr_low)
1708                         retval = lowest_latency;
1709                 break;
1710         case bulk_latency:
1711                 if (bytes_perint <= adapter->eitr_high)
1712                         retval = low_latency;
1713                 break;
1714         }
1715
1716 update_itr_done:
1717         return retval;
1718 }
1719
1720 /**
1721  * ixgbe_write_eitr - write EITR register in hardware specific way
1722  * @q_vector: structure containing interrupt and ring information
1723  *
1724  * This function is made to be called by ethtool and by the driver
1725  * when it needs to update EITR registers at runtime.  Hardware
1726  * specific quirks/differences are taken care of here.
1727  */
1728 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1729 {
1730         struct ixgbe_adapter *adapter = q_vector->adapter;
1731         struct ixgbe_hw *hw = &adapter->hw;
1732         int v_idx = q_vector->v_idx;
1733         u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1734
1735         switch (adapter->hw.mac.type) {
1736         case ixgbe_mac_82598EB:
1737                 /* must write high and low 16 bits to reset counter */
1738                 itr_reg |= (itr_reg << 16);
1739                 break;
1740         case ixgbe_mac_82599EB:
1741         case ixgbe_mac_X540:
1742                 /*
1743                  * 82599 and X540 can support a value of zero, so allow it for
1744                  * max interrupt rate, but there is an errata where it can
1745                  * not be zero with RSC
1746                  */
1747                 if (itr_reg == 8 &&
1748                     !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1749                         itr_reg = 0;
1750
1751                 /*
1752                  * set the WDIS bit to not clear the timer bits and cause an
1753                  * immediate assertion of the interrupt
1754                  */
1755                 itr_reg |= IXGBE_EITR_CNT_WDIS;
1756                 break;
1757         default:
1758                 break;
1759         }
1760         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1761 }
1762
1763 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1764 {
1765         struct ixgbe_adapter *adapter = q_vector->adapter;
1766         int i, r_idx;
1767         u32 new_itr;
1768         u8 current_itr, ret_itr;
1769
1770         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1771         for (i = 0; i < q_vector->txr_count; i++) {
1772                 struct ixgbe_ring *tx_ring = adapter->tx_ring[r_idx];
1773                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1774                                            q_vector->tx_itr,
1775                                            tx_ring->total_packets,
1776                                            tx_ring->total_bytes);
1777                 /* if the result for this queue would decrease interrupt
1778                  * rate for this vector then use that result */
1779                 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1780                                     q_vector->tx_itr - 1 : ret_itr);
1781                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1782                                       r_idx + 1);
1783         }
1784
1785         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1786         for (i = 0; i < q_vector->rxr_count; i++) {
1787                 struct ixgbe_ring *rx_ring = adapter->rx_ring[r_idx];
1788                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1789                                            q_vector->rx_itr,
1790                                            rx_ring->total_packets,
1791                                            rx_ring->total_bytes);
1792                 /* if the result for this queue would decrease interrupt
1793                  * rate for this vector then use that result */
1794                 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1795                                     q_vector->rx_itr - 1 : ret_itr);
1796                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1797                                       r_idx + 1);
1798         }
1799
1800         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1801
1802         switch (current_itr) {
1803         /* counts and packets in update_itr are dependent on these numbers */
1804         case lowest_latency:
1805                 new_itr = 100000;
1806                 break;
1807         case low_latency:
1808                 new_itr = 20000; /* aka hwitr = ~200 */
1809                 break;
1810         case bulk_latency:
1811         default:
1812                 new_itr = 8000;
1813                 break;
1814         }
1815
1816         if (new_itr != q_vector->eitr) {
1817                 /* do an exponential smoothing */
1818                 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
1819
1820                 /* save the algorithm value here, not the smoothed one */
1821                 q_vector->eitr = new_itr;
1822
1823                 ixgbe_write_eitr(q_vector);
1824         }
1825 }
1826
1827 /**
1828  * ixgbe_check_overtemp_task - worker thread to check over tempurature
1829  * @work: pointer to work_struct containing our data
1830  **/
1831 static void ixgbe_check_overtemp_task(struct work_struct *work)
1832 {
1833         struct ixgbe_adapter *adapter = container_of(work,
1834                                                      struct ixgbe_adapter,
1835                                                      check_overtemp_task);
1836         struct ixgbe_hw *hw = &adapter->hw;
1837         u32 eicr = adapter->interrupt_event;
1838
1839         if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
1840                 return;
1841
1842         switch (hw->device_id) {
1843         case IXGBE_DEV_ID_82599_T3_LOM: {
1844                 u32 autoneg;
1845                 bool link_up = false;
1846
1847                 if (hw->mac.ops.check_link)
1848                         hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1849
1850                 if (((eicr & IXGBE_EICR_GPI_SDP0) && (!link_up)) ||
1851                     (eicr & IXGBE_EICR_LSC))
1852                         /* Check if this is due to overtemp */
1853                         if (hw->phy.ops.check_overtemp(hw) == IXGBE_ERR_OVERTEMP)
1854                                 break;
1855                 return;
1856         }
1857         default:
1858                 if (!(eicr & IXGBE_EICR_GPI_SDP0))
1859                         return;
1860                 break;
1861         }
1862         e_crit(drv,
1863                "Network adapter has been stopped because it has over heated. "
1864                "Restart the computer. If the problem persists, "
1865                "power off the system and replace the adapter\n");
1866         /* write to clear the interrupt */
1867         IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP0);
1868 }
1869
1870 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1871 {
1872         struct ixgbe_hw *hw = &adapter->hw;
1873
1874         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1875             (eicr & IXGBE_EICR_GPI_SDP1)) {
1876                 e_crit(probe, "Fan has stopped, replace the adapter\n");
1877                 /* write to clear the interrupt */
1878                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1879         }
1880 }
1881
1882 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1883 {
1884         struct ixgbe_hw *hw = &adapter->hw;
1885
1886         if (eicr & IXGBE_EICR_GPI_SDP2) {
1887                 /* Clear the interrupt */
1888                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1889                 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1890                         adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
1891                         ixgbe_service_event_schedule(adapter);
1892                 }
1893         }
1894
1895         if (eicr & IXGBE_EICR_GPI_SDP1) {
1896                 /* Clear the interrupt */
1897                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1898                 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1899                         adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
1900                         ixgbe_service_event_schedule(adapter);
1901                 }
1902         }
1903 }
1904
1905 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1906 {
1907         struct ixgbe_hw *hw = &adapter->hw;
1908
1909         adapter->lsc_int++;
1910         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1911         adapter->link_check_timeout = jiffies;
1912         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1913                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1914                 IXGBE_WRITE_FLUSH(hw);
1915                 ixgbe_service_event_schedule(adapter);
1916         }
1917 }
1918
1919 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1920 {
1921         struct net_device *netdev = data;
1922         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1923         struct ixgbe_hw *hw = &adapter->hw;
1924         u32 eicr;
1925
1926         /*
1927          * Workaround for Silicon errata.  Use clear-by-write instead
1928          * of clear-by-read.  Reading with EICS will return the
1929          * interrupt causes without clearing, which later be done
1930          * with the write to EICR.
1931          */
1932         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1933         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1934
1935         if (eicr & IXGBE_EICR_LSC)
1936                 ixgbe_check_lsc(adapter);
1937
1938         if (eicr & IXGBE_EICR_MAILBOX)
1939                 ixgbe_msg_task(adapter);
1940
1941         switch (hw->mac.type) {
1942         case ixgbe_mac_82599EB:
1943                 ixgbe_check_sfp_event(adapter, eicr);
1944                 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1945                     ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
1946                         adapter->interrupt_event = eicr;
1947                         schedule_work(&adapter->check_overtemp_task);
1948                 }
1949                 /* now fallthrough to handle Flow Director */
1950         case ixgbe_mac_X540:
1951                 /* Handle Flow Director Full threshold interrupt */
1952                 if (eicr & IXGBE_EICR_FLOW_DIR) {
1953                         int i;
1954                         IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1955                         /* Disable transmits before FDIR Re-initialization */
1956                         netif_tx_stop_all_queues(netdev);
1957                         for (i = 0; i < adapter->num_tx_queues; i++) {
1958                                 struct ixgbe_ring *tx_ring =
1959                                                             adapter->tx_ring[i];
1960                                 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
1961                                                        &tx_ring->state))
1962                                         schedule_work(&adapter->fdir_reinit_task);
1963                         }
1964                 }
1965                 break;
1966         default:
1967                 break;
1968         }
1969
1970         ixgbe_check_fan_failure(adapter, eicr);
1971
1972         /* re-enable the original interrupt state, no lsc, no queues */
1973         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1974                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, eicr &
1975                                 ~(IXGBE_EIMS_LSC | IXGBE_EIMS_RTX_QUEUE));
1976
1977         return IRQ_HANDLED;
1978 }
1979
1980 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1981                                            u64 qmask)
1982 {
1983         u32 mask;
1984         struct ixgbe_hw *hw = &adapter->hw;
1985
1986         switch (hw->mac.type) {
1987         case ixgbe_mac_82598EB:
1988                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1989                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
1990                 break;
1991         case ixgbe_mac_82599EB:
1992         case ixgbe_mac_X540:
1993                 mask = (qmask & 0xFFFFFFFF);
1994                 if (mask)
1995                         IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
1996                 mask = (qmask >> 32);
1997                 if (mask)
1998                         IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
1999                 break;
2000         default:
2001                 break;
2002         }
2003         /* skip the flush */
2004 }
2005
2006 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
2007                                             u64 qmask)
2008 {
2009         u32 mask;
2010         struct ixgbe_hw *hw = &adapter->hw;
2011
2012         switch (hw->mac.type) {
2013         case ixgbe_mac_82598EB:
2014                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2015                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2016                 break;
2017         case ixgbe_mac_82599EB:
2018         case ixgbe_mac_X540:
2019                 mask = (qmask & 0xFFFFFFFF);
2020                 if (mask)
2021                         IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
2022                 mask = (qmask >> 32);
2023                 if (mask)
2024                         IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2025                 break;
2026         default:
2027                 break;
2028         }
2029         /* skip the flush */
2030 }
2031
2032 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
2033 {
2034         struct ixgbe_q_vector *q_vector = data;
2035         struct ixgbe_adapter  *adapter = q_vector->adapter;
2036         struct ixgbe_ring     *tx_ring;
2037         int i, r_idx;
2038
2039         if (!q_vector->txr_count)
2040                 return IRQ_HANDLED;
2041
2042         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2043         for (i = 0; i < q_vector->txr_count; i++) {
2044                 tx_ring = adapter->tx_ring[r_idx];
2045                 tx_ring->total_bytes = 0;
2046                 tx_ring->total_packets = 0;
2047                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
2048                                       r_idx + 1);
2049         }
2050
2051         /* EIAM disabled interrupts (on this vector) for us */
2052         napi_schedule(&q_vector->napi);
2053
2054         return IRQ_HANDLED;
2055 }
2056
2057 /**
2058  * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
2059  * @irq: unused
2060  * @data: pointer to our q_vector struct for this interrupt vector
2061  **/
2062 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
2063 {
2064         struct ixgbe_q_vector *q_vector = data;
2065         struct ixgbe_adapter  *adapter = q_vector->adapter;
2066         struct ixgbe_ring  *rx_ring;
2067         int r_idx;
2068         int i;
2069
2070 #ifdef CONFIG_IXGBE_DCA
2071         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2072                 ixgbe_update_dca(q_vector);
2073 #endif
2074
2075         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2076         for (i = 0; i < q_vector->rxr_count; i++) {
2077                 rx_ring = adapter->rx_ring[r_idx];
2078                 rx_ring->total_bytes = 0;
2079                 rx_ring->total_packets = 0;
2080                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
2081                                       r_idx + 1);
2082         }
2083
2084         if (!q_vector->rxr_count)
2085                 return IRQ_HANDLED;
2086
2087         /* EIAM disabled interrupts (on this vector) for us */
2088         napi_schedule(&q_vector->napi);
2089
2090         return IRQ_HANDLED;
2091 }
2092
2093 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
2094 {
2095         struct ixgbe_q_vector *q_vector = data;
2096         struct ixgbe_adapter  *adapter = q_vector->adapter;
2097         struct ixgbe_ring  *ring;
2098         int r_idx;
2099         int i;
2100
2101         if (!q_vector->txr_count && !q_vector->rxr_count)
2102                 return IRQ_HANDLED;
2103
2104         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2105         for (i = 0; i < q_vector->txr_count; i++) {
2106                 ring = adapter->tx_ring[r_idx];
2107                 ring->total_bytes = 0;
2108                 ring->total_packets = 0;
2109                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
2110                                       r_idx + 1);
2111         }
2112
2113         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2114         for (i = 0; i < q_vector->rxr_count; i++) {
2115                 ring = adapter->rx_ring[r_idx];
2116                 ring->total_bytes = 0;
2117                 ring->total_packets = 0;
2118                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
2119                                       r_idx + 1);
2120         }
2121
2122         /* EIAM disabled interrupts (on this vector) for us */
2123         napi_schedule(&q_vector->napi);
2124
2125         return IRQ_HANDLED;
2126 }
2127
2128 /**
2129  * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
2130  * @napi: napi struct with our devices info in it
2131  * @budget: amount of work driver is allowed to do this pass, in packets
2132  *
2133  * This function is optimized for cleaning one queue only on a single
2134  * q_vector!!!
2135  **/
2136 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
2137 {
2138         struct ixgbe_q_vector *q_vector =
2139                                container_of(napi, struct ixgbe_q_vector, napi);
2140         struct ixgbe_adapter *adapter = q_vector->adapter;
2141         struct ixgbe_ring *rx_ring = NULL;
2142         int work_done = 0;
2143         long r_idx;
2144
2145 #ifdef CONFIG_IXGBE_DCA
2146         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2147                 ixgbe_update_dca(q_vector);
2148 #endif
2149
2150         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2151         rx_ring = adapter->rx_ring[r_idx];
2152
2153         ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
2154
2155         /* If all Rx work done, exit the polling mode */
2156         if (work_done < budget) {
2157                 napi_complete(napi);
2158                 if (adapter->rx_itr_setting & 1)
2159                         ixgbe_set_itr_msix(q_vector);
2160                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2161                         ixgbe_irq_enable_queues(adapter,
2162                                                 ((u64)1 << q_vector->v_idx));
2163         }
2164
2165         return work_done;
2166 }
2167
2168 /**
2169  * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
2170  * @napi: napi struct with our devices info in it
2171  * @budget: amount of work driver is allowed to do this pass, in packets
2172  *
2173  * This function will clean more than one rx queue associated with a
2174  * q_vector.
2175  **/
2176 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
2177 {
2178         struct ixgbe_q_vector *q_vector =
2179                                container_of(napi, struct ixgbe_q_vector, napi);
2180         struct ixgbe_adapter *adapter = q_vector->adapter;
2181         struct ixgbe_ring *ring = NULL;
2182         int work_done = 0, i;
2183         long r_idx;
2184         bool tx_clean_complete = true;
2185
2186 #ifdef CONFIG_IXGBE_DCA
2187         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2188                 ixgbe_update_dca(q_vector);
2189 #endif
2190
2191         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2192         for (i = 0; i < q_vector->txr_count; i++) {
2193                 ring = adapter->tx_ring[r_idx];
2194                 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
2195                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
2196                                       r_idx + 1);
2197         }
2198
2199         /* attempt to distribute budget to each queue fairly, but don't allow
2200          * the budget to go below 1 because we'll exit polling */
2201         budget /= (q_vector->rxr_count ?: 1);
2202         budget = max(budget, 1);
2203         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2204         for (i = 0; i < q_vector->rxr_count; i++) {
2205                 ring = adapter->rx_ring[r_idx];
2206                 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
2207                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
2208                                       r_idx + 1);
2209         }
2210
2211         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2212         ring = adapter->rx_ring[r_idx];
2213         /* If all Rx work done, exit the polling mode */
2214         if (work_done < budget) {
2215                 napi_complete(napi);
2216                 if (adapter->rx_itr_setting & 1)
2217                         ixgbe_set_itr_msix(q_vector);
2218                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2219                         ixgbe_irq_enable_queues(adapter,
2220                                                 ((u64)1 << q_vector->v_idx));
2221                 return 0;
2222         }
2223
2224         return work_done;
2225 }
2226
2227 /**
2228  * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
2229  * @napi: napi struct with our devices info in it
2230  * @budget: amount of work driver is allowed to do this pass, in packets
2231  *
2232  * This function is optimized for cleaning one queue only on a single
2233  * q_vector!!!
2234  **/
2235 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
2236 {
2237         struct ixgbe_q_vector *q_vector =
2238                                container_of(napi, struct ixgbe_q_vector, napi);
2239         struct ixgbe_adapter *adapter = q_vector->adapter;
2240         struct ixgbe_ring *tx_ring = NULL;
2241         int work_done = 0;
2242         long r_idx;
2243
2244 #ifdef CONFIG_IXGBE_DCA
2245         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2246                 ixgbe_update_dca(q_vector);
2247 #endif
2248
2249         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2250         tx_ring = adapter->tx_ring[r_idx];
2251
2252         if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2253                 work_done = budget;
2254
2255         /* If all Tx work done, exit the polling mode */
2256         if (work_done < budget) {
2257                 napi_complete(napi);
2258                 if (adapter->tx_itr_setting & 1)
2259                         ixgbe_set_itr_msix(q_vector);
2260                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2261                         ixgbe_irq_enable_queues(adapter,
2262                                                 ((u64)1 << q_vector->v_idx));
2263         }
2264
2265         return work_done;
2266 }
2267
2268 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
2269                                      int r_idx)
2270 {
2271         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2272         struct ixgbe_ring *rx_ring = a->rx_ring[r_idx];
2273
2274         set_bit(r_idx, q_vector->rxr_idx);
2275         q_vector->rxr_count++;
2276         rx_ring->q_vector = q_vector;
2277 }
2278
2279 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
2280                                      int t_idx)
2281 {
2282         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2283         struct ixgbe_ring *tx_ring = a->tx_ring[t_idx];
2284
2285         set_bit(t_idx, q_vector->txr_idx);
2286         q_vector->txr_count++;
2287         tx_ring->q_vector = q_vector;
2288 }
2289
2290 /**
2291  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2292  * @adapter: board private structure to initialize
2293  *
2294  * This function maps descriptor rings to the queue-specific vectors
2295  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
2296  * one vector per ring/queue, but on a constrained vector budget, we
2297  * group the rings as "efficiently" as possible.  You would add new
2298  * mapping configurations in here.
2299  **/
2300 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter)
2301 {
2302         int q_vectors;
2303         int v_start = 0;
2304         int rxr_idx = 0, txr_idx = 0;
2305         int rxr_remaining = adapter->num_rx_queues;
2306         int txr_remaining = adapter->num_tx_queues;
2307         int i, j;
2308         int rqpv, tqpv;
2309         int err = 0;
2310
2311         /* No mapping required if MSI-X is disabled. */
2312         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2313                 goto out;
2314
2315         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2316
2317         /*
2318          * The ideal configuration...
2319          * We have enough vectors to map one per queue.
2320          */
2321         if (q_vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
2322                 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2323                         map_vector_to_rxq(adapter, v_start, rxr_idx);
2324
2325                 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2326                         map_vector_to_txq(adapter, v_start, txr_idx);
2327
2328                 goto out;
2329         }
2330
2331         /*
2332          * If we don't have enough vectors for a 1-to-1
2333          * mapping, we'll have to group them so there are
2334          * multiple queues per vector.
2335          */
2336         /* Re-adjusting *qpv takes care of the remainder. */
2337         for (i = v_start; i < q_vectors; i++) {
2338                 rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - i);
2339                 for (j = 0; j < rqpv; j++) {
2340                         map_vector_to_rxq(adapter, i, rxr_idx);
2341                         rxr_idx++;
2342                         rxr_remaining--;
2343                 }
2344                 tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - i);
2345                 for (j = 0; j < tqpv; j++) {
2346                         map_vector_to_txq(adapter, i, txr_idx);
2347                         txr_idx++;
2348                         txr_remaining--;
2349                 }
2350         }
2351 out:
2352         return err;
2353 }
2354
2355 /**
2356  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2357  * @adapter: board private structure
2358  *
2359  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2360  * interrupts from the kernel.
2361  **/
2362 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2363 {
2364         struct net_device *netdev = adapter->netdev;
2365         irqreturn_t (*handler)(int, void *);
2366         int i, vector, q_vectors, err;
2367         int ri = 0, ti = 0;
2368
2369         /* Decrement for Other and TCP Timer vectors */
2370         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2371
2372         err = ixgbe_map_rings_to_vectors(adapter);
2373         if (err)
2374                 return err;
2375
2376 #define SET_HANDLER(_v) (((_v)->rxr_count && (_v)->txr_count)        \
2377                                           ? &ixgbe_msix_clean_many : \
2378                           (_v)->rxr_count ? &ixgbe_msix_clean_rx   : \
2379                           (_v)->txr_count ? &ixgbe_msix_clean_tx   : \
2380                           NULL)
2381         for (vector = 0; vector < q_vectors; vector++) {
2382                 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2383                 handler = SET_HANDLER(q_vector);
2384
2385                 if (handler == &ixgbe_msix_clean_rx) {
2386                         snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2387                                  "%s-%s-%d", netdev->name, "rx", ri++);
2388                 } else if (handler == &ixgbe_msix_clean_tx) {
2389                         snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2390                                  "%s-%s-%d", netdev->name, "tx", ti++);
2391                 } else if (handler == &ixgbe_msix_clean_many) {
2392                         snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2393                                  "%s-%s-%d", netdev->name, "TxRx", ri++);
2394                         ti++;
2395                 } else {
2396                         /* skip this unused q_vector */
2397                         continue;
2398                 }
2399                 err = request_irq(adapter->msix_entries[vector].vector,
2400                                   handler, 0, q_vector->name,
2401                                   q_vector);
2402                 if (err) {
2403                         e_err(probe, "request_irq failed for MSIX interrupt "
2404                               "Error: %d\n", err);
2405                         goto free_queue_irqs;
2406                 }
2407         }
2408
2409         sprintf(adapter->lsc_int_name, "%s:lsc", netdev->name);
2410         err = request_irq(adapter->msix_entries[vector].vector,
2411                           ixgbe_msix_lsc, 0, adapter->lsc_int_name, netdev);
2412         if (err) {
2413                 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
2414                 goto free_queue_irqs;
2415         }
2416
2417         return 0;
2418
2419 free_queue_irqs:
2420         for (i = vector - 1; i >= 0; i--)
2421                 free_irq(adapter->msix_entries[--vector].vector,
2422                          adapter->q_vector[i]);
2423         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2424         pci_disable_msix(adapter->pdev);
2425         kfree(adapter->msix_entries);
2426         adapter->msix_entries = NULL;
2427         return err;
2428 }
2429
2430 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2431 {
2432         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2433         struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2434         struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
2435         u32 new_itr = q_vector->eitr;
2436         u8 current_itr;
2437
2438         q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
2439                                             q_vector->tx_itr,
2440                                             tx_ring->total_packets,
2441                                             tx_ring->total_bytes);
2442         q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
2443                                             q_vector->rx_itr,
2444                                             rx_ring->total_packets,
2445                                             rx_ring->total_bytes);
2446
2447         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
2448
2449         switch (current_itr) {
2450         /* counts and packets in update_itr are dependent on these numbers */
2451         case lowest_latency:
2452                 new_itr = 100000;
2453                 break;
2454         case low_latency:
2455                 new_itr = 20000; /* aka hwitr = ~200 */
2456                 break;
2457         case bulk_latency:
2458                 new_itr = 8000;
2459                 break;
2460         default:
2461                 break;
2462         }
2463
2464         if (new_itr != q_vector->eitr) {
2465                 /* do an exponential smoothing */
2466                 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
2467
2468                 /* save the algorithm value here */
2469                 q_vector->eitr = new_itr;
2470
2471                 ixgbe_write_eitr(q_vector);
2472         }
2473 }
2474
2475 /**
2476  * ixgbe_irq_enable - Enable default interrupt generation settings
2477  * @adapter: board private structure
2478  **/
2479 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2480                                     bool flush)
2481 {
2482         u32 mask;
2483
2484         mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2485         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2486                 mask |= IXGBE_EIMS_GPI_SDP0;
2487         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2488                 mask |= IXGBE_EIMS_GPI_SDP1;
2489         switch (adapter->hw.mac.type) {
2490         case ixgbe_mac_82599EB:
2491         case ixgbe_mac_X540:
2492                 mask |= IXGBE_EIMS_ECC;
2493                 mask |= IXGBE_EIMS_GPI_SDP1;
2494                 mask |= IXGBE_EIMS_GPI_SDP2;
2495                 if (adapter->num_vfs)
2496                         mask |= IXGBE_EIMS_MAILBOX;
2497                 break;
2498         default:
2499                 break;
2500         }
2501         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2502             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2503                 mask |= IXGBE_EIMS_FLOW_DIR;
2504
2505         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2506         if (queues)
2507                 ixgbe_irq_enable_queues(adapter, ~0);
2508         if (flush)
2509                 IXGBE_WRITE_FLUSH(&adapter->hw);
2510
2511         if (adapter->num_vfs > 32) {
2512                 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2513                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2514         }
2515 }
2516
2517 /**
2518  * ixgbe_intr - legacy mode Interrupt Handler
2519  * @irq: interrupt number
2520  * @data: pointer to a network interface device structure
2521  **/
2522 static irqreturn_t ixgbe_intr(int irq, void *data)
2523 {
2524         struct net_device *netdev = data;
2525         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2526         struct ixgbe_hw *hw = &adapter->hw;
2527         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2528         u32 eicr;
2529
2530         /*
2531          * Workaround for silicon errata on 82598.  Mask the interrupts
2532          * before the read of EICR.
2533          */
2534         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2535
2536         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2537          * therefore no explict interrupt disable is necessary */
2538         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2539         if (!eicr) {
2540                 /*
2541                  * shared interrupt alert!
2542                  * make sure interrupts are enabled because the read will
2543                  * have disabled interrupts due to EIAM
2544                  * finish the workaround of silicon errata on 82598.  Unmask
2545                  * the interrupt that we masked before the EICR read.
2546                  */
2547                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2548                         ixgbe_irq_enable(adapter, true, true);
2549                 return IRQ_NONE;        /* Not our interrupt */
2550         }
2551
2552         if (eicr & IXGBE_EICR_LSC)
2553                 ixgbe_check_lsc(adapter);
2554
2555         switch (hw->mac.type) {
2556         case ixgbe_mac_82599EB:
2557                 ixgbe_check_sfp_event(adapter, eicr);
2558                 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2559                     ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
2560                         adapter->interrupt_event = eicr;
2561                         schedule_work(&adapter->check_overtemp_task);
2562                 }
2563                 break;
2564         default:
2565                 break;
2566         }
2567
2568         ixgbe_check_fan_failure(adapter, eicr);
2569
2570         if (napi_schedule_prep(&(q_vector->napi))) {
2571                 adapter->tx_ring[0]->total_packets = 0;
2572                 adapter->tx_ring[0]->total_bytes = 0;
2573                 adapter->rx_ring[0]->total_packets = 0;
2574                 adapter->rx_ring[0]->total_bytes = 0;
2575                 /* would disable interrupts here but EIAM disabled it */
2576                 __napi_schedule(&(q_vector->napi));
2577         }
2578
2579         /*
2580          * re-enable link(maybe) and non-queue interrupts, no flush.
2581          * ixgbe_poll will re-enable the queue interrupts
2582          */
2583
2584         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2585                 ixgbe_irq_enable(adapter, false, false);
2586
2587         return IRQ_HANDLED;
2588 }
2589
2590 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2591 {
2592         int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2593
2594         for (i = 0; i < q_vectors; i++) {
2595                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
2596                 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2597                 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2598                 q_vector->rxr_count = 0;
2599                 q_vector->txr_count = 0;
2600         }
2601 }
2602
2603 /**
2604  * ixgbe_request_irq - initialize interrupts
2605  * @adapter: board private structure
2606  *
2607  * Attempts to configure interrupts using the best available
2608  * capabilities of the hardware and kernel.
2609  **/
2610 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2611 {
2612         struct net_device *netdev = adapter->netdev;
2613         int err;
2614
2615         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2616                 err = ixgbe_request_msix_irqs(adapter);
2617         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2618                 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2619                                   netdev->name, netdev);
2620         } else {
2621                 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2622                                   netdev->name, netdev);
2623         }
2624
2625         if (err)
2626                 e_err(probe, "request_irq failed, Error %d\n", err);
2627
2628         return err;
2629 }
2630
2631 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2632 {
2633         struct net_device *netdev = adapter->netdev;
2634
2635         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2636                 int i, q_vectors;
2637
2638                 q_vectors = adapter->num_msix_vectors;
2639
2640                 i = q_vectors - 1;
2641                 free_irq(adapter->msix_entries[i].vector, netdev);
2642
2643                 i--;
2644                 for (; i >= 0; i--) {
2645                         /* free only the irqs that were actually requested */
2646                         if (!adapter->q_vector[i]->rxr_count &&
2647                             !adapter->q_vector[i]->txr_count)
2648                                 continue;
2649
2650                         free_irq(adapter->msix_entries[i].vector,
2651                                  adapter->q_vector[i]);
2652                 }
2653
2654                 ixgbe_reset_q_vectors(adapter);
2655         } else {
2656                 free_irq(adapter->pdev->irq, netdev);
2657         }
2658 }
2659
2660 /**
2661  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2662  * @adapter: board private structure
2663  **/
2664 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2665 {
2666         switch (adapter->hw.mac.type) {
2667         case ixgbe_mac_82598EB:
2668                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2669                 break;
2670         case ixgbe_mac_82599EB:
2671         case ixgbe_mac_X540:
2672                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2673                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2674                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2675                 if (adapter->num_vfs > 32)
2676                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
2677                 break;
2678         default:
2679                 break;
2680         }
2681         IXGBE_WRITE_FLUSH(&adapter->hw);
2682         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2683                 int i;
2684                 for (i = 0; i < adapter->num_msix_vectors; i++)
2685                         synchronize_irq(adapter->msix_entries[i].vector);
2686         } else {
2687                 synchronize_irq(adapter->pdev->irq);
2688         }
2689 }
2690
2691 /**
2692  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2693  *
2694  **/
2695 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2696 {
2697         struct ixgbe_hw *hw = &adapter->hw;
2698
2699         IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
2700                         EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
2701
2702         ixgbe_set_ivar(adapter, 0, 0, 0);
2703         ixgbe_set_ivar(adapter, 1, 0, 0);
2704
2705         map_vector_to_rxq(adapter, 0, 0);
2706         map_vector_to_txq(adapter, 0, 0);
2707
2708         e_info(hw, "Legacy interrupt IVAR setup done\n");
2709 }
2710
2711 /**
2712  * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2713  * @adapter: board private structure
2714  * @ring: structure containing ring specific data
2715  *
2716  * Configure the Tx descriptor ring after a reset.
2717  **/
2718 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2719                              struct ixgbe_ring *ring)
2720 {
2721         struct ixgbe_hw *hw = &adapter->hw;
2722         u64 tdba = ring->dma;
2723         int wait_loop = 10;
2724         u32 txdctl;
2725         u8 reg_idx = ring->reg_idx;
2726
2727         /* disable queue to avoid issues while updating state */
2728         txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2729         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
2730                         txdctl & ~IXGBE_TXDCTL_ENABLE);
2731         IXGBE_WRITE_FLUSH(hw);
2732
2733         IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2734                         (tdba & DMA_BIT_MASK(32)));
2735         IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2736         IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2737                         ring->count * sizeof(union ixgbe_adv_tx_desc));
2738         IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2739         IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2740         ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2741
2742         /* configure fetching thresholds */
2743         if (adapter->rx_itr_setting == 0) {
2744                 /* cannot set wthresh when itr==0 */
2745                 txdctl &= ~0x007F0000;
2746         } else {
2747                 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2748                 txdctl |= (8 << 16);
2749         }
2750         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2751                 /* PThresh workaround for Tx hang with DFP enabled. */
2752                 txdctl |= 32;
2753         }
2754
2755         /* reinitialize flowdirector state */
2756         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2757             adapter->atr_sample_rate) {
2758                 ring->atr_sample_rate = adapter->atr_sample_rate;
2759                 ring->atr_count = 0;
2760                 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2761         } else {
2762                 ring->atr_sample_rate = 0;
2763         }
2764
2765         clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2766
2767         /* enable queue */
2768         txdctl |= IXGBE_TXDCTL_ENABLE;
2769         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2770
2771         /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2772         if (hw->mac.type == ixgbe_mac_82598EB &&
2773             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2774                 return;
2775
2776         /* poll to verify queue is enabled */
2777         do {
2778                 usleep_range(1000, 2000);
2779                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2780         } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2781         if (!wait_loop)
2782                 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2783 }
2784
2785 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2786 {
2787         struct ixgbe_hw *hw = &adapter->hw;
2788         u32 rttdcs;
2789         u32 mask;
2790
2791         if (hw->mac.type == ixgbe_mac_82598EB)
2792                 return;
2793
2794         /* disable the arbiter while setting MTQC */
2795         rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2796         rttdcs |= IXGBE_RTTDCS_ARBDIS;
2797         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2798
2799         /* set transmit pool layout */
2800         mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2801         switch (adapter->flags & mask) {
2802
2803         case (IXGBE_FLAG_SRIOV_ENABLED):
2804                 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2805                                 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2806                 break;
2807
2808         case (IXGBE_FLAG_DCB_ENABLED):
2809                 /* We enable 8 traffic classes, DCB only */
2810                 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2811                               (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2812                 break;
2813
2814         default:
2815                 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2816                 break;
2817         }
2818
2819         /* re-enable the arbiter */
2820         rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2821         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2822 }
2823
2824 /**
2825  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2826  * @adapter: board private structure
2827  *
2828  * Configure the Tx unit of the MAC after a reset.
2829  **/
2830 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2831 {
2832         struct ixgbe_hw *hw = &adapter->hw;
2833         u32 dmatxctl;
2834         u32 i;
2835
2836         ixgbe_setup_mtqc(adapter);
2837
2838         if (hw->mac.type != ixgbe_mac_82598EB) {
2839                 /* DMATXCTL.EN must be before Tx queues are enabled */
2840                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2841                 dmatxctl |= IXGBE_DMATXCTL_TE;
2842                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2843         }
2844
2845         /* Setup the HW Tx Head and Tail descriptor pointers */
2846         for (i = 0; i < adapter->num_tx_queues; i++)
2847                 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2848 }
2849
2850 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2851
2852 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2853                                    struct ixgbe_ring *rx_ring)
2854 {
2855         u32 srrctl;
2856         u8 reg_idx = rx_ring->reg_idx;
2857
2858         switch (adapter->hw.mac.type) {
2859         case ixgbe_mac_82598EB: {
2860                 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2861                 const int mask = feature[RING_F_RSS].mask;
2862                 reg_idx = reg_idx & mask;
2863         }
2864                 break;
2865         case ixgbe_mac_82599EB:
2866         case ixgbe_mac_X540:
2867         default:
2868                 break;
2869         }
2870
2871         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
2872
2873         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2874         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2875         if (adapter->num_vfs)
2876                 srrctl |= IXGBE_SRRCTL_DROP_EN;
2877
2878         srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2879                   IXGBE_SRRCTL_BSIZEHDR_MASK;
2880
2881         if (ring_is_ps_enabled(rx_ring)) {
2882 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2883                 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2884 #else
2885                 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2886 #endif
2887                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2888         } else {
2889                 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2890                           IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2891                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2892         }
2893
2894         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
2895 }
2896
2897 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2898 {
2899         struct ixgbe_hw *hw = &adapter->hw;
2900         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2901                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2902                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
2903         u32 mrqc = 0, reta = 0;
2904         u32 rxcsum;
2905         int i, j;
2906         int mask;
2907
2908         /* Fill out hash function seeds */
2909         for (i = 0; i < 10; i++)
2910                 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2911
2912         /* Fill out redirection table */
2913         for (i = 0, j = 0; i < 128; i++, j++) {
2914                 if (j == adapter->ring_feature[RING_F_RSS].indices)
2915                         j = 0;
2916                 /* reta = 4-byte sliding window of
2917                  * 0x00..(indices-1)(indices-1)00..etc. */
2918                 reta = (reta << 8) | (j * 0x11);
2919                 if ((i & 3) == 3)
2920                         IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2921         }
2922
2923         /* Disable indicating checksum in descriptor, enables RSS hash */
2924         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2925         rxcsum |= IXGBE_RXCSUM_PCSD;
2926         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2927
2928         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
2929                 mask = adapter->flags & IXGBE_FLAG_RSS_ENABLED;
2930         else
2931                 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2932 #ifdef CONFIG_IXGBE_DCB
2933                                          | IXGBE_FLAG_DCB_ENABLED
2934 #endif
2935                                          | IXGBE_FLAG_SRIOV_ENABLED
2936                                         );
2937
2938         switch (mask) {
2939 #ifdef CONFIG_IXGBE_DCB
2940         case (IXGBE_FLAG_DCB_ENABLED | IXGBE_FLAG_RSS_ENABLED):
2941                 mrqc = IXGBE_MRQC_RTRSS8TCEN;
2942                 break;
2943         case (IXGBE_FLAG_DCB_ENABLED):
2944                 mrqc = IXGBE_MRQC_RT8TCEN;
2945                 break;
2946 #endif /* CONFIG_IXGBE_DCB */
2947         case (IXGBE_FLAG_RSS_ENABLED):
2948                 mrqc = IXGBE_MRQC_RSSEN;
2949                 break;
2950         case (IXGBE_FLAG_SRIOV_ENABLED):
2951                 mrqc = IXGBE_MRQC_VMDQEN;
2952                 break;
2953         default:
2954                 break;
2955         }
2956
2957         /* Perform hash on these packet types */
2958         mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2959               | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2960               | IXGBE_MRQC_RSS_FIELD_IPV6
2961               | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2962
2963         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2964 }
2965
2966 /**
2967  * ixgbe_clear_rscctl - disable RSC for the indicated ring
2968  * @adapter: address of board private structure
2969  * @ring: structure containing ring specific data
2970  **/
2971 void ixgbe_clear_rscctl(struct ixgbe_adapter *adapter,
2972                         struct ixgbe_ring *ring)
2973 {
2974         struct ixgbe_hw *hw = &adapter->hw;
2975         u32 rscctrl;
2976         u8 reg_idx = ring->reg_idx;
2977
2978         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2979         rscctrl &= ~IXGBE_RSCCTL_RSCEN;
2980         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2981 }
2982
2983 /**
2984  * ixgbe_configure_rscctl - enable RSC for the indicated ring
2985  * @adapter:    address of board private structure
2986  * @index:      index of ring to set
2987  **/
2988 void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2989                                    struct ixgbe_ring *ring)
2990 {
2991         struct ixgbe_hw *hw = &adapter->hw;
2992         u32 rscctrl;
2993         int rx_buf_len;
2994         u8 reg_idx = ring->reg_idx;
2995
2996         if (!ring_is_rsc_enabled(ring))
2997                 return;
2998
2999         rx_buf_len = ring->rx_buf_len;
3000         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
3001         rscctrl |= IXGBE_RSCCTL_RSCEN;
3002         /*
3003          * we must limit the number of descriptors so that the
3004          * total size of max desc * buf_len is not greater
3005          * than 65535
3006          */
3007         if (ring_is_ps_enabled(ring)) {
3008 #if (MAX_SKB_FRAGS > 16)
3009                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
3010 #elif (MAX_SKB_FRAGS > 8)
3011                 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
3012 #elif (MAX_SKB_FRAGS > 4)
3013                 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
3014 #else
3015                 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
3016 #endif
3017         } else {
3018                 if (rx_buf_len < IXGBE_RXBUFFER_4096)
3019                         rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
3020                 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
3021                         rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
3022                 else
3023                         rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
3024         }
3025         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
3026 }
3027
3028 /**
3029  *  ixgbe_set_uta - Set unicast filter table address
3030  *  @adapter: board private structure
3031  *
3032  *  The unicast table address is a register array of 32-bit registers.
3033  *  The table is meant to be used in a way similar to how the MTA is used
3034  *  however due to certain limitations in the hardware it is necessary to
3035  *  set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
3036  *  enable bit to allow vlan tag stripping when promiscuous mode is enabled
3037  **/
3038 static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
3039 {
3040         struct ixgbe_hw *hw = &adapter->hw;
3041         int i;
3042
3043         /* The UTA table only exists on 82599 hardware and newer */
3044         if (hw->mac.type < ixgbe_mac_82599EB)
3045                 return;
3046
3047         /* we only need to do this if VMDq is enabled */
3048         if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3049                 return;
3050
3051         for (i = 0; i < 128; i++)
3052                 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
3053 }
3054
3055 #define IXGBE_MAX_RX_DESC_POLL 10
3056 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3057                                        struct ixgbe_ring *ring)
3058 {
3059         struct ixgbe_hw *hw = &adapter->hw;
3060         int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3061         u32 rxdctl;
3062         u8 reg_idx = ring->reg_idx;
3063
3064         /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3065         if (hw->mac.type == ixgbe_mac_82598EB &&
3066             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3067                 return;
3068
3069         do {
3070                 usleep_range(1000, 2000);
3071                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3072         } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3073
3074         if (!wait_loop) {
3075                 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3076                       "the polling period\n", reg_idx);
3077         }
3078 }
3079
3080 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3081                             struct ixgbe_ring *ring)
3082 {
3083         struct ixgbe_hw *hw = &adapter->hw;
3084         int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3085         u32 rxdctl;
3086         u8 reg_idx = ring->reg_idx;
3087
3088         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3089         rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3090
3091         /* write value back with RXDCTL.ENABLE bit cleared */
3092         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3093
3094         if (hw->mac.type == ixgbe_mac_82598EB &&
3095             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3096                 return;
3097
3098         /* the hardware may take up to 100us to really disable the rx queue */
3099         do {
3100                 udelay(10);
3101                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3102         } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3103
3104         if (!wait_loop) {
3105                 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3106                       "the polling period\n", reg_idx);
3107         }
3108 }
3109
3110 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3111                              struct ixgbe_ring *ring)
3112 {
3113         struct ixgbe_hw *hw = &adapter->hw;
3114         u64 rdba = ring->dma;
3115         u32 rxdctl;
3116         u8 reg_idx = ring->reg_idx;
3117
3118         /* disable queue to avoid issues while updating state */
3119         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3120         ixgbe_disable_rx_queue(adapter, ring);
3121
3122         IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3123         IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3124         IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3125                         ring->count * sizeof(union ixgbe_adv_rx_desc));
3126         IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3127         IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
3128         ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
3129
3130         ixgbe_configure_srrctl(adapter, ring);
3131         ixgbe_configure_rscctl(adapter, ring);
3132
3133         /* If operating in IOV mode set RLPML for X540 */
3134         if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
3135             hw->mac.type == ixgbe_mac_X540) {
3136                 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
3137                 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
3138                             ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
3139         }
3140
3141         if (hw->mac.type == ixgbe_mac_82598EB) {
3142                 /*
3143                  * enable cache line friendly hardware writes:
3144                  * PTHRESH=32 descriptors (half the internal cache),
3145                  * this also removes ugly rx_no_buffer_count increment
3146                  * HTHRESH=4 descriptors (to minimize latency on fetch)
3147                  * WTHRESH=8 burst writeback up to two cache lines
3148                  */
3149                 rxdctl &= ~0x3FFFFF;
3150                 rxdctl |=  0x080420;
3151         }
3152
3153         /* enable receive descriptor ring */
3154         rxdctl |= IXGBE_RXDCTL_ENABLE;
3155         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3156
3157         ixgbe_rx_desc_queue_enable(adapter, ring);
3158         ixgbe_alloc_rx_buffers(ring, IXGBE_DESC_UNUSED(ring));
3159 }
3160
3161 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3162 {
3163         struct ixgbe_hw *hw = &adapter->hw;
3164         int p;
3165
3166         /* PSRTYPE must be initialized in non 82598 adapters */
3167         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
3168                       IXGBE_PSRTYPE_UDPHDR |
3169                       IXGBE_PSRTYPE_IPV4HDR |
3170                       IXGBE_PSRTYPE_L2HDR |
3171                       IXGBE_PSRTYPE_IPV6HDR;
3172
3173         if (hw->mac.type == ixgbe_mac_82598EB)
3174                 return;
3175
3176         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
3177                 psrtype |= (adapter->num_rx_queues_per_pool << 29);
3178
3179         for (p = 0; p < adapter->num_rx_pools; p++)
3180                 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
3181                                 psrtype);
3182 }
3183
3184 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3185 {
3186         struct ixgbe_hw *hw = &adapter->hw;
3187         u32 gcr_ext;
3188         u32 vt_reg_bits;
3189         u32 reg_offset, vf_shift;
3190         u32 vmdctl;
3191
3192         if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3193                 return;
3194
3195         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3196         vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
3197         vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
3198         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
3199
3200         vf_shift = adapter->num_vfs % 32;
3201         reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
3202
3203         /* Enable only the PF's pool for Tx/Rx */
3204         IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
3205         IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
3206         IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
3207         IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
3208         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3209
3210         /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3211         hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
3212
3213         /*
3214          * Set up VF register offsets for selected VT Mode,
3215          * i.e. 32 or 64 VFs for SR-IOV
3216          */
3217         gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3218         gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
3219         gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
3220         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3221
3222         /* enable Tx loopback for VF/PF communication */
3223         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3224         /* Enable MAC Anti-Spoofing */
3225         hw->mac.ops.set_mac_anti_spoofing(hw,
3226                                           (adapter->antispoofing_enabled =
3227                                            (adapter->num_vfs != 0)),
3228                                           adapter->num_vfs);
3229 }
3230
3231 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
3232 {
3233         struct ixgbe_hw *hw = &adapter->hw;
3234         struct net_device *netdev = adapter->netdev;
3235         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3236         int rx_buf_len;
3237         struct ixgbe_ring *rx_ring;
3238         int i;
3239         u32 mhadd, hlreg0;
3240
3241         /* Decide whether to use packet split mode or not */
3242         /* On by default */
3243         adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
3244
3245         /* Do not use packet split if we're in SR-IOV Mode */
3246         if (adapter->num_vfs)
3247                 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
3248
3249         /* Disable packet split due to 82599 erratum #45 */
3250         if (hw->mac.type == ixgbe_mac_82599EB)
3251                 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
3252
3253         /* Set the RX buffer length according to the mode */
3254         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
3255                 rx_buf_len = IXGBE_RX_HDR_SIZE;
3256         } else {
3257                 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
3258                     (netdev->mtu <= ETH_DATA_LEN))
3259                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3260                 else
3261                         rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
3262         }
3263
3264 #ifdef IXGBE_FCOE
3265         /* adjust max frame to be able to do baby jumbo for FCoE */
3266         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3267             (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3268                 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3269
3270 #endif /* IXGBE_FCOE */
3271         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3272         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3273                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3274                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3275
3276                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3277         }
3278
3279         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3280         /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3281         hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3282         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3283
3284         /*
3285          * Setup the HW Rx Head and Tail Descriptor Pointers and
3286          * the Base and Length of the Rx Descriptor Ring
3287          */
3288         for (i = 0; i < adapter->num_rx_queues; i++) {
3289                 rx_ring = adapter->rx_ring[i];
3290                 rx_ring->rx_buf_len = rx_buf_len;
3291
3292                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
3293                         set_ring_ps_enabled(rx_ring);
3294                 else
3295                         clear_ring_ps_enabled(rx_ring);
3296
3297                 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3298                         set_ring_rsc_enabled(rx_ring);
3299                 else
3300                         clear_ring_rsc_enabled(rx_ring);
3301
3302 #ifdef IXGBE_FCOE
3303                 if (netdev->features & NETIF_F_FCOE_MTU) {
3304                         struct ixgbe_ring_feature *f;
3305                         f = &adapter->ring_feature[RING_F_FCOE];
3306                         if ((i >= f->mask) && (i < f->mask + f->indices)) {
3307                                 clear_ring_ps_enabled(rx_ring);
3308                                 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3309                                         rx_ring->rx_buf_len =
3310                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
3311                         } else if (!ring_is_rsc_enabled(rx_ring) &&
3312                                    !ring_is_ps_enabled(rx_ring)) {
3313                                 rx_ring->rx_buf_len =
3314                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
3315                         }
3316                 }
3317 #endif /* IXGBE_FCOE */
3318         }
3319 }
3320
3321 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3322 {
3323         struct ixgbe_hw *hw = &adapter->hw;
3324         u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3325
3326         switch (hw->mac.type) {
3327         case ixgbe_mac_82598EB:
3328                 /*
3329                  * For VMDq support of different descriptor types or
3330                  * buffer sizes through the use of multiple SRRCTL
3331                  * registers, RDRXCTL.MVMEN must be set to 1
3332                  *
3333                  * also, the manual doesn't mention it clearly but DCA hints
3334                  * will only use queue 0's tags unless this bit is set.  Side
3335                  * effects of setting this bit are only that SRRCTL must be
3336                  * fully programmed [0..15]
3337                  */
3338                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3339                 break;
3340         case ixgbe_mac_82599EB:
3341         case ixgbe_mac_X540:
3342                 /* Disable RSC for ACK packets */
3343                 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3344                    (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3345                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3346                 /* hardware requires some bits to be set by default */
3347                 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3348                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3349                 break;
3350         default:
3351                 /* We should do nothing since we don't know this hardware */
3352                 return;
3353         }
3354
3355         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3356 }
3357
3358 /**
3359  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3360  * @adapter: board private structure
3361  *
3362  * Configure the Rx unit of the MAC after a reset.
3363  **/
3364 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3365 {
3366         struct ixgbe_hw *hw = &adapter->hw;
3367         int i;
3368         u32 rxctrl;
3369
3370         /* disable receives while setting up the descriptors */
3371         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3372         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3373
3374         ixgbe_setup_psrtype(adapter);
3375         ixgbe_setup_rdrxctl(adapter);
3376
3377         /* Program registers for the distribution of queues */
3378         ixgbe_setup_mrqc(adapter);
3379
3380         ixgbe_set_uta(adapter);
3381
3382         /* set_rx_buffer_len must be called before ring initialization */
3383         ixgbe_set_rx_buffer_len(adapter);
3384
3385         /*
3386          * Setup the HW Rx Head and Tail Descriptor Pointers and
3387          * the Base and Length of the Rx Descriptor Ring
3388          */
3389         for (i = 0; i < adapter->num_rx_queues; i++)
3390                 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3391
3392         /* disable drop enable for 82598 parts */
3393         if (hw->mac.type == ixgbe_mac_82598EB)
3394                 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3395
3396         /* enable all receives */
3397         rxctrl |= IXGBE_RXCTRL_RXEN;
3398         hw->mac.ops.enable_rx_dma(hw, rxctrl);
3399 }
3400
3401 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3402 {
3403         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3404         struct ixgbe_hw *hw = &adapter->hw;
3405         int pool_ndx = adapter->num_vfs;
3406
3407         /* add VID to filter table */
3408         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
3409         set_bit(vid, adapter->active_vlans);
3410 }
3411
3412 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3413 {
3414         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3415         struct ixgbe_hw *hw = &adapter->hw;
3416         int pool_ndx = adapter->num_vfs;
3417
3418         /* remove VID from filter table */
3419         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
3420         clear_bit(vid, adapter->active_vlans);
3421 }
3422
3423 /**
3424  * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3425  * @adapter: driver data
3426  */
3427 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3428 {
3429         struct ixgbe_hw *hw = &adapter->hw;
3430         u32 vlnctrl;
3431
3432         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3433         vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3434         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3435 }
3436
3437 /**
3438  * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3439  * @adapter: driver data
3440  */
3441 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3442 {
3443         struct ixgbe_hw *hw = &adapter->hw;
3444         u32 vlnctrl;
3445
3446         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3447         vlnctrl |= IXGBE_VLNCTRL_VFE;
3448         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3449         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3450 }
3451
3452 /**
3453  * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3454  * @adapter: driver data
3455  */
3456 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3457 {
3458         struct ixgbe_hw *hw = &adapter->hw;
3459         u32 vlnctrl;
3460         int i, j;
3461
3462         switch (hw->mac.type) {
3463         case ixgbe_mac_82598EB:
3464                 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3465                 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3466                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3467                 break;
3468         case ixgbe_mac_82599EB:
3469         case ixgbe_mac_X540:
3470                 for (i = 0; i < adapter->num_rx_queues; i++) {
3471                         j = adapter->rx_ring[i]->reg_idx;
3472                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3473                         vlnctrl &= ~IXGBE_RXDCTL_VME;
3474                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3475                 }
3476                 break;
3477         default:
3478                 break;
3479         }
3480 }
3481
3482 /**
3483  * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3484  * @adapter: driver data
3485  */
3486 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3487 {
3488         struct ixgbe_hw *hw = &adapter->hw;
3489         u32 vlnctrl;
3490         int i, j;
3491
3492         switch (hw->mac.type) {
3493         case ixgbe_mac_82598EB:
3494                 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3495                 vlnctrl |= IXGBE_VLNCTRL_VME;
3496                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3497                 break;
3498         case ixgbe_mac_82599EB:
3499         case ixgbe_mac_X540:
3500                 for (i = 0; i < adapter->num_rx_queues; i++) {
3501                         j = adapter->rx_ring[i]->reg_idx;
3502                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3503                         vlnctrl |= IXGBE_RXDCTL_VME;
3504                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3505                 }
3506                 break;
3507         default:
3508                 break;
3509         }
3510 }
3511
3512 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3513 {
3514         u16 vid;
3515
3516         ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3517
3518         for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3519                 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3520 }
3521
3522 /**
3523  * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3524  * @netdev: network interface device structure
3525  *
3526  * Writes unicast address list to the RAR table.
3527  * Returns: -ENOMEM on failure/insufficient address space
3528  *                0 on no addresses written
3529  *                X on writing X addresses to the RAR table
3530  **/
3531 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3532 {
3533         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3534         struct ixgbe_hw *hw = &adapter->hw;
3535         unsigned int vfn = adapter->num_vfs;
3536         unsigned int rar_entries = IXGBE_MAX_PF_MACVLANS;
3537         int count = 0;
3538
3539         /* return ENOMEM indicating insufficient memory for addresses */
3540         if (netdev_uc_count(netdev) > rar_entries)
3541                 return -ENOMEM;
3542
3543         if (!netdev_uc_empty(netdev) && rar_entries) {
3544                 struct netdev_hw_addr *ha;
3545                 /* return error if we do not support writing to RAR table */
3546                 if (!hw->mac.ops.set_rar)
3547                         return -ENOMEM;
3548
3549                 netdev_for_each_uc_addr(ha, netdev) {
3550                         if (!rar_entries)
3551                                 break;
3552                         hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3553                                             vfn, IXGBE_RAH_AV);
3554                         count++;
3555                 }
3556         }
3557         /* write the addresses in reverse order to avoid write combining */
3558         for (; rar_entries > 0 ; rar_entries--)
3559                 hw->mac.ops.clear_rar(hw, rar_entries);
3560
3561         return count;
3562 }
3563
3564 /**
3565  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3566  * @netdev: network interface device structure
3567  *
3568  * The set_rx_method entry point is called whenever the unicast/multicast
3569  * address list or the network interface flags are updated.  This routine is
3570  * responsible for configuring the hardware for proper unicast, multicast and
3571  * promiscuous mode.
3572  **/
3573 void ixgbe_set_rx_mode(struct net_device *netdev)
3574 {
3575         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3576         struct ixgbe_hw *hw = &adapter->hw;
3577         u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3578         int count;
3579
3580         /* Check for Promiscuous and All Multicast modes */
3581
3582         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3583
3584         /* set all bits that we expect to always be set */
3585         fctrl |= IXGBE_FCTRL_BAM;
3586         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3587         fctrl |= IXGBE_FCTRL_PMCF;
3588
3589         /* clear the bits we are changing the status of */
3590         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3591
3592         if (netdev->flags & IFF_PROMISC) {
3593                 hw->addr_ctrl.user_set_promisc = true;
3594                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3595                 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3596                 /* don't hardware filter vlans in promisc mode */
3597                 ixgbe_vlan_filter_disable(adapter);
3598         } else {
3599                 if (netdev->flags & IFF_ALLMULTI) {
3600                         fctrl |= IXGBE_FCTRL_MPE;
3601                         vmolr |= IXGBE_VMOLR_MPE;
3602                 } else {
3603                         /*
3604                          * Write addresses to the MTA, if the attempt fails
3605                          * then we should just turn on promiscuous mode so
3606                          * that we can at least receive multicast traffic
3607                          */
3608                         hw->mac.ops.update_mc_addr_list(hw, netdev);
3609                         vmolr |= IXGBE_VMOLR_ROMPE;
3610                 }
3611                 ixgbe_vlan_filter_enable(adapter);
3612                 hw->addr_ctrl.user_set_promisc = false;
3613                 /*
3614                  * Write addresses to available RAR registers, if there is not
3615                  * sufficient space to store all the addresses then enable
3616                  * unicast promiscuous mode
3617                  */
3618                 count = ixgbe_write_uc_addr_list(netdev);
3619                 if (count < 0) {
3620                         fctrl |= IXGBE_FCTRL_UPE;
3621                         vmolr |= IXGBE_VMOLR_ROPE;
3622                 }
3623         }
3624
3625         if (adapter->num_vfs) {
3626                 ixgbe_restore_vf_multicasts(adapter);
3627                 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3628                          ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3629                            IXGBE_VMOLR_ROPE);
3630                 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3631         }
3632
3633         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3634
3635         if (netdev->features & NETIF_F_HW_VLAN_RX)
3636                 ixgbe_vlan_strip_enable(adapter);
3637         else
3638                 ixgbe_vlan_strip_disable(adapter);
3639 }
3640
3641 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3642 {
3643         int q_idx;
3644         struct ixgbe_q_vector *q_vector;
3645         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3646
3647         /* legacy and MSI only use one vector */
3648         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3649                 q_vectors = 1;
3650
3651         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3652                 struct napi_struct *napi;
3653                 q_vector = adapter->q_vector[q_idx];
3654                 napi = &q_vector->napi;
3655                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3656                         if (!q_vector->rxr_count || !q_vector->txr_count) {
3657                                 if (q_vector->txr_count == 1)
3658                                         napi->poll = &ixgbe_clean_txonly;
3659                                 else if (q_vector->rxr_count == 1)
3660                                         napi->poll = &ixgbe_clean_rxonly;
3661                         }
3662                 }
3663
3664                 napi_enable(napi);
3665         }
3666 }
3667
3668 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3669 {
3670         int q_idx;
3671         struct ixgbe_q_vector *q_vector;
3672         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3673
3674         /* legacy and MSI only use one vector */
3675         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3676                 q_vectors = 1;
3677
3678         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3679                 q_vector = adapter->q_vector[q_idx];
3680                 napi_disable(&q_vector->napi);
3681         }
3682 }
3683
3684 #ifdef CONFIG_IXGBE_DCB
3685 /*
3686  * ixgbe_configure_dcb - Configure DCB hardware
3687  * @adapter: ixgbe adapter struct
3688  *
3689  * This is called by the driver on open to configure the DCB hardware.
3690  * This is also called by the gennetlink interface when reconfiguring
3691  * the DCB state.
3692  */
3693 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3694 {
3695         struct ixgbe_hw *hw = &adapter->hw;
3696         int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3697
3698         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3699                 if (hw->mac.type == ixgbe_mac_82598EB)
3700                         netif_set_gso_max_size(adapter->netdev, 65536);
3701                 return;
3702         }
3703
3704         if (hw->mac.type == ixgbe_mac_82598EB)
3705                 netif_set_gso_max_size(adapter->netdev, 32768);
3706
3707
3708         /* Enable VLAN tag insert/strip */
3709         adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
3710
3711         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3712
3713         /* reconfigure the hardware */
3714         if (adapter->dcbx_cap & (DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE)) {
3715 #ifdef CONFIG_FCOE
3716                 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3717                         max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3718 #endif
3719                 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3720                                                 DCB_TX_CONFIG);
3721                 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3722                                                 DCB_RX_CONFIG);
3723                 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3724         } else {
3725                 struct net_device *dev = adapter->netdev;
3726
3727                 if (adapter->ixgbe_ieee_ets)
3728                         dev->dcbnl_ops->ieee_setets(dev,
3729                                                     adapter->ixgbe_ieee_ets);
3730                 if (adapter->ixgbe_ieee_pfc)
3731                         dev->dcbnl_ops->ieee_setpfc(dev,
3732                                                     adapter->ixgbe_ieee_pfc);
3733         }
3734
3735         /* Enable RSS Hash per TC */
3736         if (hw->mac.type != ixgbe_mac_82598EB) {
3737                 int i;
3738                 u32 reg = 0;
3739
3740                 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
3741                         u8 msb = 0;
3742                         u8 cnt = adapter->netdev->tc_to_txq[i].count;
3743
3744                         while (cnt >>= 1)
3745                                 msb++;
3746
3747                         reg |= msb << IXGBE_RQTC_SHIFT_TC(i);
3748                 }
3749                 IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg);
3750         }
3751 }
3752
3753 #endif
3754 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3755 {
3756         struct net_device *netdev = adapter->netdev;
3757         struct ixgbe_hw *hw = &adapter->hw;
3758         int i;
3759
3760 #ifdef CONFIG_IXGBE_DCB
3761         ixgbe_configure_dcb(adapter);
3762 #endif
3763
3764         ixgbe_set_rx_mode(netdev);
3765         ixgbe_restore_vlan(adapter);
3766
3767 #ifdef IXGBE_FCOE
3768         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3769                 ixgbe_configure_fcoe(adapter);
3770
3771 #endif /* IXGBE_FCOE */
3772         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3773                 for (i = 0; i < adapter->num_tx_queues; i++)
3774                         adapter->tx_ring[i]->atr_sample_rate =
3775                                                        adapter->atr_sample_rate;
3776                 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3777         } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3778                 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
3779         }
3780         ixgbe_configure_virtualization(adapter);
3781
3782         ixgbe_configure_tx(adapter);
3783         ixgbe_configure_rx(adapter);
3784 }
3785
3786 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3787 {
3788         switch (hw->phy.type) {
3789         case ixgbe_phy_sfp_avago:
3790         case ixgbe_phy_sfp_ftl:
3791         case ixgbe_phy_sfp_intel:
3792         case ixgbe_phy_sfp_unknown:
3793         case ixgbe_phy_sfp_passive_tyco:
3794         case ixgbe_phy_sfp_passive_unknown:
3795         case ixgbe_phy_sfp_active_unknown:
3796         case ixgbe_phy_sfp_ftl_active:
3797                 return true;
3798         default:
3799                 return false;
3800         }
3801 }
3802
3803 /**
3804  * ixgbe_sfp_link_config - set up SFP+ link
3805  * @adapter: pointer to private adapter struct
3806  **/
3807 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3808 {
3809         /*
3810          * We are assuming the worst case scenerio here, and that
3811          * is that an SFP was inserted/removed after the reset
3812          * but before SFP detection was enabled.  As such the best
3813          * solution is to just start searching as soon as we start
3814          */
3815         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3816                 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
3817
3818         adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
3819 }
3820
3821 /**
3822  * ixgbe_non_sfp_link_config - set up non-SFP+ link
3823  * @hw: pointer to private hardware struct
3824  *
3825  * Returns 0 on success, negative on failure
3826  **/
3827 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3828 {
3829         u32 autoneg;
3830         bool negotiation, link_up = false;
3831         u32 ret = IXGBE_ERR_LINK_SETUP;
3832
3833         if (hw->mac.ops.check_link)
3834                 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3835
3836         if (ret)
3837                 goto link_cfg_out;
3838
3839         autoneg = hw->phy.autoneg_advertised;
3840         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
3841                 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3842                                                         &negotiation);
3843         if (ret)
3844                 goto link_cfg_out;
3845
3846         if (hw->mac.ops.setup_link)
3847                 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3848 link_cfg_out:
3849         return ret;
3850 }
3851
3852 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
3853 {
3854         struct ixgbe_hw *hw = &adapter->hw;
3855         u32 gpie = 0;
3856
3857         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3858                 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3859                        IXGBE_GPIE_OCD;
3860                 gpie |= IXGBE_GPIE_EIAME;
3861                 /*
3862                  * use EIAM to auto-mask when MSI-X interrupt is asserted
3863                  * this saves a register write for every interrupt
3864                  */
3865                 switch (hw->mac.type) {
3866                 case ixgbe_mac_82598EB:
3867                         IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3868                         break;
3869                 case ixgbe_mac_82599EB:
3870                 case ixgbe_mac_X540:
3871                 default:
3872                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3873                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3874                         break;
3875                 }
3876         } else {
3877                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3878                  * specifically only auto mask tx and rx interrupts */
3879                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3880         }
3881
3882         /* XXX: to interrupt immediately for EICS writes, enable this */
3883         /* gpie |= IXGBE_GPIE_EIMEN; */
3884
3885         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3886                 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3887                 gpie |= IXGBE_GPIE_VTMODE_64;
3888         }
3889
3890         /* Enable fan failure interrupt */
3891         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3892                 gpie |= IXGBE_SDP1_GPIEN;
3893
3894         if (hw->mac.type == ixgbe_mac_82599EB) {
3895                 gpie |= IXGBE_SDP1_GPIEN;
3896                 gpie |= IXGBE_SDP2_GPIEN;
3897         }
3898
3899         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3900 }
3901
3902 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3903 {
3904         struct ixgbe_hw *hw = &adapter->hw;
3905         int err;
3906         u32 ctrl_ext;
3907
3908         ixgbe_get_hw_control(adapter);
3909         ixgbe_setup_gpie(adapter);
3910
3911         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3912                 ixgbe_configure_msix(adapter);
3913         else
3914                 ixgbe_configure_msi_and_legacy(adapter);
3915
3916         /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3917         if (hw->mac.ops.enable_tx_laser &&
3918             ((hw->phy.multispeed_fiber) ||
3919              ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
3920               (hw->mac.type == ixgbe_mac_82599EB))))
3921                 hw->mac.ops.enable_tx_laser(hw);
3922
3923         clear_bit(__IXGBE_DOWN, &adapter->state);
3924         ixgbe_napi_enable_all(adapter);
3925
3926         if (ixgbe_is_sfp(hw)) {
3927                 ixgbe_sfp_link_config(adapter);
3928         } else {
3929                 err = ixgbe_non_sfp_link_config(hw);
3930                 if (err)
3931                         e_err(probe, "link_config FAILED %d\n", err);
3932         }
3933
3934         /* clear any pending interrupts, may auto mask */
3935         IXGBE_READ_REG(hw, IXGBE_EICR);
3936         ixgbe_irq_enable(adapter, true, true);
3937
3938         /*
3939          * If this adapter has a fan, check to see if we had a failure
3940          * before we enabled the interrupt.
3941          */
3942         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3943                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3944                 if (esdp & IXGBE_ESDP_SDP1)
3945                         e_crit(drv, "Fan has stopped, replace the adapter\n");
3946         }
3947
3948         /* enable transmits */
3949         netif_tx_start_all_queues(adapter->netdev);
3950
3951         /* bring the link up in the watchdog, this could race with our first
3952          * link up interrupt but shouldn't be a problem */
3953         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3954         adapter->link_check_timeout = jiffies;
3955         mod_timer(&adapter->service_timer, jiffies);
3956
3957         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3958         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3959         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3960         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3961
3962         return 0;
3963 }
3964
3965 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3966 {
3967         WARN_ON(in_interrupt());
3968         /* put off any impending NetWatchDogTimeout */
3969         adapter->netdev->trans_start = jiffies;
3970
3971         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3972                 usleep_range(1000, 2000);
3973         ixgbe_down(adapter);
3974         /*
3975          * If SR-IOV enabled then wait a bit before bringing the adapter
3976          * back up to give the VFs time to respond to the reset.  The
3977          * two second wait is based upon the watchdog timer cycle in
3978          * the VF driver.
3979          */
3980         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3981                 msleep(2000);
3982         ixgbe_up(adapter);
3983         clear_bit(__IXGBE_RESETTING, &adapter->state);
3984 }
3985
3986 int ixgbe_up(struct ixgbe_adapter *adapter)
3987 {
3988         /* hardware has been reset, we need to reload some things */
3989         ixgbe_configure(adapter);
3990
3991         return ixgbe_up_complete(adapter);
3992 }
3993
3994 void ixgbe_reset(struct ixgbe_adapter *adapter)
3995 {
3996         struct ixgbe_hw *hw = &adapter->hw;
3997         int err;
3998
3999         /* lock SFP init bit to prevent race conditions with the watchdog */
4000         while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4001                 usleep_range(1000, 2000);
4002
4003         /* clear all SFP and link config related flags while holding SFP_INIT */
4004         adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4005                              IXGBE_FLAG2_SFP_NEEDS_RESET);
4006         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4007
4008         err = hw->mac.ops.init_hw(hw);
4009         switch (err) {
4010         case 0:
4011         case IXGBE_ERR_SFP_NOT_PRESENT:
4012         case IXGBE_ERR_SFP_NOT_SUPPORTED:
4013                 break;
4014         case IXGBE_ERR_MASTER_REQUESTS_PENDING:
4015                 e_dev_err("master disable timed out\n");
4016                 break;
4017         case IXGBE_ERR_EEPROM_VERSION:
4018                 /* We are running on a pre-production device, log a warning */
4019                 e_dev_warn("This device is a pre-production adapter/LOM. "
4020                            "Please be aware there may be issuesassociated with "
4021                            "your hardware.  If you are experiencing problems "
4022                            "please contact your Intel or hardware "
4023                            "representative who provided you with this "
4024                            "hardware.\n");
4025                 break;
4026         default:
4027                 e_dev_err("Hardware Error: %d\n", err);
4028         }
4029
4030         clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
4031
4032         /* reprogram the RAR[0] in case user changed it. */
4033         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
4034                             IXGBE_RAH_AV);
4035 }
4036
4037 /**
4038  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4039  * @rx_ring: ring to free buffers from
4040  **/
4041 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4042 {
4043         struct device *dev = rx_ring->dev;
4044         unsigned long size;
4045         u16 i;
4046
4047         /* ring already cleared, nothing to do */
4048         if (!rx_ring->rx_buffer_info)
4049                 return;
4050
4051         /* Free all the Rx ring sk_buffs */
4052         for (i = 0; i < rx_ring->count; i++) {
4053                 struct ixgbe_rx_buffer *rx_buffer_info;
4054
4055                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
4056                 if (rx_buffer_info->dma) {
4057                         dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
4058                                          rx_ring->rx_buf_len,
4059                                          DMA_FROM_DEVICE);
4060                         rx_buffer_info->dma = 0;
4061                 }
4062                 if (rx_buffer_info->skb) {
4063                         struct sk_buff *skb = rx_buffer_info->skb;
4064                         rx_buffer_info->skb = NULL;
4065                         do {
4066                                 struct sk_buff *this = skb;
4067                                 if (IXGBE_RSC_CB(this)->delay_unmap) {
4068                                         dma_unmap_single(dev,
4069                                                          IXGBE_RSC_CB(this)->dma,
4070                                                          rx_ring->rx_buf_len,
4071                                                          DMA_FROM_DEVICE);
4072                                         IXGBE_RSC_CB(this)->dma = 0;
4073                                         IXGBE_RSC_CB(skb)->delay_unmap = false;
4074                                 }
4075                                 skb = skb->prev;
4076                                 dev_kfree_skb(this);
4077                         } while (skb);
4078                 }
4079                 if (!rx_buffer_info->page)
4080                         continue;
4081                 if (rx_buffer_info->page_dma) {
4082                         dma_unmap_page(dev, rx_buffer_info->page_dma,
4083                                        PAGE_SIZE / 2, DMA_FROM_DEVICE);
4084                         rx_buffer_info->page_dma = 0;
4085                 }
4086                 put_page(rx_buffer_info->page);
4087                 rx_buffer_info->page = NULL;
4088                 rx_buffer_info->page_offset = 0;
4089         }
4090
4091         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4092         memset(rx_ring->rx_buffer_info, 0, size);
4093
4094         /* Zero out the descriptor ring */
4095         memset(rx_ring->desc, 0, rx_ring->size);
4096
4097         rx_ring->next_to_clean = 0;
4098         rx_ring->next_to_use = 0;
4099 }
4100
4101 /**
4102  * ixgbe_clean_tx_ring - Free Tx Buffers
4103  * @tx_ring: ring to be cleaned
4104  **/
4105 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
4106 {
4107         struct ixgbe_tx_buffer *tx_buffer_info;
4108         unsigned long size;
4109         u16 i;
4110
4111         /* ring already cleared, nothing to do */
4112         if (!tx_ring->tx_buffer_info)
4113                 return;
4114
4115         /* Free all the Tx ring sk_buffs */
4116         for (i = 0; i < tx_ring->count; i++) {
4117                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4118                 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
4119         }
4120
4121         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4122         memset(tx_ring->tx_buffer_info, 0, size);
4123
4124         /* Zero out the descriptor ring */
4125         memset(tx_ring->desc, 0, tx_ring->size);
4126
4127         tx_ring->next_to_use = 0;
4128         tx_ring->next_to_clean = 0;
4129 }
4130
4131 /**
4132  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
4133  * @adapter: board private structure
4134  **/
4135 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
4136 {
4137         int i;
4138
4139         for (i = 0; i < adapter->num_rx_queues; i++)
4140                 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
4141 }
4142
4143 /**
4144  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
4145  * @adapter: board private structure
4146  **/
4147 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
4148 {
4149         int i;
4150
4151         for (i = 0; i < adapter->num_tx_queues; i++)
4152                 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
4153 }
4154
4155 void ixgbe_down(struct ixgbe_adapter *adapter)
4156 {
4157         struct net_device *netdev = adapter->netdev;
4158         struct ixgbe_hw *hw = &adapter->hw;
4159         u32 rxctrl;
4160         u32 txdctl;
4161         int i;
4162         int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4163
4164         /* signal that we are down to the interrupt handler */
4165         set_bit(__IXGBE_DOWN, &adapter->state);
4166
4167         /* disable receive for all VFs and wait one second */
4168         if (adapter->num_vfs) {
4169                 /* ping all the active vfs to let them know we are going down */
4170                 ixgbe_ping_all_vfs(adapter);
4171
4172                 /* Disable all VFTE/VFRE TX/RX */
4173                 ixgbe_disable_tx_rx(adapter);
4174
4175                 /* Mark all the VFs as inactive */
4176                 for (i = 0 ; i < adapter->num_vfs; i++)
4177                         adapter->vfinfo[i].clear_to_send = 0;
4178         }
4179
4180         /* disable receives */
4181         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4182         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
4183
4184         /* disable all enabled rx queues */
4185         for (i = 0; i < adapter->num_rx_queues; i++)
4186                 /* this call also flushes the previous write */
4187                 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4188
4189         usleep_range(10000, 20000);
4190
4191         netif_tx_stop_all_queues(netdev);
4192
4193         /* call carrier off first to avoid false dev_watchdog timeouts */
4194         netif_carrier_off(netdev);
4195         netif_tx_disable(netdev);
4196
4197         ixgbe_irq_disable(adapter);
4198
4199         ixgbe_napi_disable_all(adapter);
4200
4201         adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
4202         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4203
4204         del_timer_sync(&adapter->service_timer);
4205
4206         /* Cleanup the affinity_hint CPU mask memory and callback */
4207         for (i = 0; i < num_q_vectors; i++) {
4208                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
4209                 /* clear the affinity_mask in the IRQ descriptor */
4210                 irq_set_affinity_hint(adapter->msix_entries[i]. vector, NULL);
4211                 /* release the CPU mask memory */
4212                 free_cpumask_var(q_vector->affinity_mask);
4213         }
4214
4215         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4216             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
4217                 cancel_work_sync(&adapter->fdir_reinit_task);
4218
4219         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4220                 cancel_work_sync(&adapter->check_overtemp_task);
4221
4222         /* disable transmits in the hardware now that interrupts are off */
4223         for (i = 0; i < adapter->num_tx_queues; i++) {
4224                 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
4225                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
4226                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
4227                                 (txdctl & ~IXGBE_TXDCTL_ENABLE));
4228         }
4229         /* Disable the Tx DMA engine on 82599 */
4230         switch (hw->mac.type) {
4231         case ixgbe_mac_82599EB:
4232         case ixgbe_mac_X540:
4233                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
4234                                 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4235                                  ~IXGBE_DMATXCTL_TE));
4236                 break;
4237         default:
4238                 break;
4239         }
4240
4241         if (!pci_channel_offline(adapter->pdev))
4242                 ixgbe_reset(adapter);
4243
4244         /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4245         if (hw->mac.ops.disable_tx_laser &&
4246             ((hw->phy.multispeed_fiber) ||
4247              ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
4248               (hw->mac.type == ixgbe_mac_82599EB))))
4249                 hw->mac.ops.disable_tx_laser(hw);
4250
4251         ixgbe_clean_all_tx_rings(adapter);
4252         ixgbe_clean_all_rx_rings(adapter);
4253
4254 #ifdef CONFIG_IXGBE_DCA
4255         /* since we reset the hardware DCA settings were cleared */
4256         ixgbe_setup_dca(adapter);
4257 #endif
4258 }
4259
4260 /**
4261  * ixgbe_poll - NAPI Rx polling callback
4262  * @napi: structure for representing this polling device
4263  * @budget: how many packets driver is allowed to clean
4264  *
4265  * This function is used for legacy and MSI, NAPI mode
4266  **/
4267 static int ixgbe_poll(struct napi_struct *napi, int budget)
4268 {
4269         struct ixgbe_q_vector *q_vector =
4270                                 container_of(napi, struct ixgbe_q_vector, napi);
4271         struct ixgbe_adapter *adapter = q_vector->adapter;
4272         int tx_clean_complete, work_done = 0;
4273
4274 #ifdef CONFIG_IXGBE_DCA
4275         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
4276                 ixgbe_update_dca(q_vector);
4277 #endif
4278
4279         tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
4280         ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
4281
4282         if (!tx_clean_complete)
4283                 work_done = budget;
4284
4285         /* If budget not fully consumed, exit the polling mode */
4286         if (work_done < budget) {
4287                 napi_complete(napi);
4288                 if (adapter->rx_itr_setting & 1)
4289                         ixgbe_set_itr(adapter);
4290                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
4291                         ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
4292         }
4293         return work_done;
4294 }
4295
4296 /**
4297  * ixgbe_tx_timeout - Respond to a Tx Hang
4298  * @netdev: network interface device structure
4299  **/
4300 static void ixgbe_tx_timeout(struct net_device *netdev)
4301 {
4302         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4303
4304         /* Do the reset outside of interrupt context */
4305         ixgbe_tx_timeout_reset(adapter);
4306 }
4307
4308 /**
4309  * ixgbe_set_rss_queues: Allocate queues for RSS
4310  * @adapter: board private structure to initialize
4311  *
4312  * This is our "base" multiqueue mode.  RSS (Receive Side Scaling) will try
4313  * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4314  *
4315  **/
4316 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4317 {
4318         bool ret = false;
4319         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
4320
4321         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4322                 f->mask = 0xF;
4323                 adapter->num_rx_queues = f->indices;
4324                 adapter->num_tx_queues = f->indices;
4325                 ret = true;
4326         } else {
4327                 ret = false;
4328         }
4329
4330         return ret;
4331 }
4332
4333 /**
4334  * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4335  * @adapter: board private structure to initialize
4336  *
4337  * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4338  * to the original CPU that initiated the Tx session.  This runs in addition
4339  * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4340  * Rx load across CPUs using RSS.
4341  *
4342  **/
4343 static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
4344 {
4345         bool ret = false;
4346         struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4347
4348         f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4349         f_fdir->mask = 0;
4350
4351         /* Flow Director must have RSS enabled */
4352         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4353             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4354              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
4355                 adapter->num_tx_queues = f_fdir->indices;
4356                 adapter->num_rx_queues = f_fdir->indices;
4357                 ret = true;
4358         } else {
4359                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4360                 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4361         }
4362         return ret;
4363 }
4364
4365 #ifdef IXGBE_FCOE
4366 /**
4367  * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4368  * @adapter: board private structure to initialize
4369  *
4370  * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4371  * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4372  * rx queues out of the max number of rx queues, instead, it is used as the
4373  * index of the first rx queue used by FCoE.
4374  *
4375  **/
4376 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4377 {
4378         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4379
4380         if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4381                 return false;
4382
4383         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4384 #ifdef CONFIG_IXGBE_DCB
4385                 int tc;
4386                 struct net_device *dev = adapter->netdev;
4387
4388                 tc = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
4389                 f->indices = dev->tc_to_txq[tc].count;
4390                 f->mask = dev->tc_to_txq[tc].offset;
4391 #endif
4392         } else {
4393                 f->indices = min((int)num_online_cpus(), f->indices);
4394
4395                 adapter->num_rx_queues = 1;
4396                 adapter->num_tx_queues = 1;
4397
4398                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4399                         e_info(probe, "FCoE enabled with RSS\n");
4400                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4401                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4402                                 ixgbe_set_fdir_queues(adapter);
4403                         else
4404                                 ixgbe_set_rss_queues(adapter);
4405                 }
4406                 /* adding FCoE rx rings to the end */
4407                 f->mask = adapter->num_rx_queues;
4408                 adapter->num_rx_queues += f->indices;
4409                 adapter->num_tx_queues += f->indices;
4410         }
4411
4412         return true;
4413 }
4414 #endif /* IXGBE_FCOE */
4415
4416 #ifdef CONFIG_IXGBE_DCB
4417 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4418 {
4419         bool ret = false;
4420         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
4421         int i, q;
4422
4423         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
4424                 return ret;
4425
4426         f->indices = 0;
4427         for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
4428                 q = min((int)num_online_cpus(), MAX_TRAFFIC_CLASS);
4429                 f->indices += q;
4430         }
4431
4432         f->mask = 0x7 << 3;
4433         adapter->num_rx_queues = f->indices;
4434         adapter->num_tx_queues = f->indices;
4435         ret = true;
4436
4437 #ifdef IXGBE_FCOE
4438         /* FCoE enabled queues require special configuration done through
4439          * configure_fcoe() and others. Here we map FCoE indices onto the
4440          * DCB queue pairs allowing FCoE to own configuration later.
4441          */
4442         ixgbe_set_fcoe_queues(adapter);
4443 #endif
4444
4445         return ret;
4446 }
4447 #endif
4448
4449 /**
4450  * ixgbe_set_sriov_queues: Allocate queues for IOV use
4451  * @adapter: board private structure to initialize
4452  *
4453  * IOV doesn't actually use anything, so just NAK the
4454  * request for now and let the other queue routines
4455  * figure out what to do.
4456  */
4457 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4458 {
4459         return false;
4460 }
4461
4462 /*
4463  * ixgbe_set_num_queues: Allocate queues for device, feature dependent
4464  * @adapter: board private structure to initialize
4465  *
4466  * This is the top level queue allocation routine.  The order here is very
4467  * important, starting with the "most" number of features turned on at once,
4468  * and ending with the smallest set of features.  This way large combinations
4469  * can be allocated if they're turned on, and smaller combinations are the
4470  * fallthrough conditions.
4471  *
4472  **/
4473 static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
4474 {
4475         /* Start with base case */
4476         adapter->num_rx_queues = 1;
4477         adapter->num_tx_queues = 1;
4478         adapter->num_rx_pools = adapter->num_rx_queues;
4479         adapter->num_rx_queues_per_pool = 1;
4480
4481         if (ixgbe_set_sriov_queues(adapter))
4482                 goto done;
4483
4484 #ifdef CONFIG_IXGBE_DCB
4485         if (ixgbe_set_dcb_queues(adapter))
4486                 goto done;
4487
4488 #endif
4489 #ifdef IXGBE_FCOE
4490         if (ixgbe_set_fcoe_queues(adapter))
4491                 goto done;
4492
4493 #endif /* IXGBE_FCOE */
4494         if (ixgbe_set_fdir_queues(adapter))
4495                 goto done;
4496
4497         if (ixgbe_set_rss_queues(adapter))
4498                 goto done;
4499
4500         /* fallback to base case */
4501         adapter->num_rx_queues = 1;
4502         adapter->num_tx_queues = 1;
4503
4504 done:
4505         /* Notify the stack of the (possibly) reduced queue counts. */
4506         netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
4507         return netif_set_real_num_rx_queues(adapter->netdev,
4508                                             adapter->num_rx_queues);
4509 }
4510
4511 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
4512                                        int vectors)
4513 {
4514         int err, vector_threshold;
4515
4516         /* We'll want at least 3 (vector_threshold):
4517          * 1) TxQ[0] Cleanup
4518          * 2) RxQ[0] Cleanup
4519          * 3) Other (Link Status Change, etc.)
4520          * 4) TCP Timer (optional)
4521          */
4522         vector_threshold = MIN_MSIX_COUNT;
4523
4524         /* The more we get, the more we will assign to Tx/Rx Cleanup
4525          * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4526          * Right now, we simply care about how many we'll get; we'll
4527          * set them up later while requesting irq's.
4528          */
4529         while (vectors >= vector_threshold) {
4530                 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
4531                                       vectors);
4532                 if (!err) /* Success in acquiring all requested vectors. */
4533                         break;
4534                 else if (err < 0)
4535                         vectors = 0; /* Nasty failure, quit now */
4536                 else /* err == number of vectors we should try again with */
4537                         vectors = err;
4538         }
4539
4540         if (vectors < vector_threshold) {
4541                 /* Can't allocate enough MSI-X interrupts?  Oh well.
4542                  * This just means we'll go with either a single MSI
4543                  * vector or fall back to legacy interrupts.
4544                  */
4545                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4546                              "Unable to allocate MSI-X interrupts\n");
4547                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4548                 kfree(adapter->msix_entries);
4549                 adapter->msix_entries = NULL;
4550         } else {
4551                 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
4552                 /*
4553                  * Adjust for only the vectors we'll use, which is minimum
4554                  * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4555                  * vectors we were allocated.
4556                  */
4557                 adapter->num_msix_vectors = min(vectors,
4558                                    adapter->max_msix_q_vectors + NON_Q_VECTORS);
4559         }
4560 }
4561
4562 /**
4563  * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4564  * @adapter: board private structure to initialize
4565  *
4566  * Cache the descriptor ring offsets for RSS to the assigned rings.
4567  *
4568  **/
4569 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
4570 {
4571         int i;
4572
4573         if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
4574                 return false;
4575
4576         for (i = 0; i < adapter->num_rx_queues; i++)
4577                 adapter->rx_ring[i]->reg_idx = i;
4578         for (i = 0; i < adapter->num_tx_queues; i++)
4579                 adapter->tx_ring[i]->reg_idx = i;
4580
4581         return true;
4582 }
4583
4584 #ifdef CONFIG_IXGBE_DCB
4585
4586 /* ixgbe_get_first_reg_idx - Return first register index associated with ring */
4587 static void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc,
4588                                     unsigned int *tx, unsigned int *rx)
4589 {
4590         struct net_device *dev = adapter->netdev;
4591         struct ixgbe_hw *hw = &adapter->hw;
4592         u8 num_tcs = netdev_get_num_tc(dev);
4593
4594         *tx = 0;
4595         *rx = 0;
4596
4597         switch (hw->mac.type) {
4598         case ixgbe_mac_82598EB:
4599                 *tx = tc << 3;
4600                 *rx = tc << 2;
4601                 break;
4602         case ixgbe_mac_82599EB:
4603         case ixgbe_mac_X540:
4604                 if (num_tcs == 8) {
4605                         if (tc < 3) {
4606                                 *tx = tc << 5;
4607                                 *rx = tc << 4;
4608                         } else if (tc <  5) {
4609                                 *tx = ((tc + 2) << 4);
4610                                 *rx = tc << 4;
4611                         } else if (tc < num_tcs) {
4612                                 *tx = ((tc + 8) << 3);
4613                                 *rx = tc << 4;
4614                         }
4615                 } else if (num_tcs == 4) {
4616                         *rx =  tc << 5;
4617                         switch (tc) {
4618                         case 0:
4619                                 *tx =  0;
4620                                 break;
4621                         case 1:
4622                                 *tx = 64;
4623                                 break;
4624                         case 2:
4625                                 *tx = 96;
4626                                 break;
4627                         case 3:
4628                                 *tx = 112;
4629                                 break;
4630                         default:
4631                                 break;
4632                         }
4633                 }
4634                 break;
4635         default:
4636                 break;
4637         }
4638 }
4639
4640 #define IXGBE_MAX_Q_PER_TC      (IXGBE_MAX_DCB_INDICES / MAX_TRAFFIC_CLASS)
4641
4642 /* ixgbe_setup_tc - routine to configure net_device for multiple traffic
4643  * classes.
4644  *
4645  * @netdev: net device to configure
4646  * @tc: number of traffic classes to enable
4647  */
4648 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
4649 {
4650         int i;
4651         unsigned int q, offset = 0;
4652
4653         if (!tc) {
4654                 netdev_reset_tc(dev);
4655         } else {
4656                 struct ixgbe_adapter *adapter = netdev_priv(dev);
4657
4658                 /* Hardware supports up to 8 traffic classes */
4659                 if (tc > MAX_TRAFFIC_CLASS || netdev_set_num_tc(dev, tc))
4660                         return -EINVAL;
4661
4662                 /* Partition Tx queues evenly amongst traffic classes */
4663                 for (i = 0; i < tc; i++) {
4664                         q = min((int)num_online_cpus(), IXGBE_MAX_Q_PER_TC);
4665                         netdev_set_prio_tc_map(dev, i, i);
4666                         netdev_set_tc_queue(dev, i, q, offset);
4667                         offset += q;
4668                 }
4669
4670                 /* This enables multiple traffic class support in the hardware
4671                  * which defaults to strict priority transmission by default.
4672                  * If traffic classes are already enabled perhaps through DCB
4673                  * code path then existing configuration will be used.
4674                  */
4675                 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
4676                     dev->dcbnl_ops && dev->dcbnl_ops->setdcbx) {
4677                         struct ieee_ets ets = {
4678                                         .prio_tc = {0, 1, 2, 3, 4, 5, 6, 7},
4679                                               };
4680                         u8 mode = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_IEEE;
4681
4682                         dev->dcbnl_ops->setdcbx(dev, mode);
4683                         dev->dcbnl_ops->ieee_setets(dev, &ets);
4684                 }
4685         }
4686         return 0;
4687 }
4688
4689 /**
4690  * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4691  * @adapter: board private structure to initialize
4692  *
4693  * Cache the descriptor ring offsets for DCB to the assigned rings.
4694  *
4695  **/
4696 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4697 {
4698         struct net_device *dev = adapter->netdev;
4699         int i, j, k;
4700         u8 num_tcs = netdev_get_num_tc(dev);
4701
4702         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
4703                 return false;
4704
4705         for (i = 0, k = 0; i < num_tcs; i++) {
4706                 unsigned int tx_s, rx_s;
4707                 u16 count = dev->tc_to_txq[i].count;
4708
4709                 ixgbe_get_first_reg_idx(adapter, i, &tx_s, &rx_s);
4710                 for (j = 0; j < count; j++, k++) {
4711                         adapter->tx_ring[k]->reg_idx = tx_s + j;
4712                         adapter->rx_ring[k]->reg_idx = rx_s + j;
4713                         adapter->tx_ring[k]->dcb_tc = i;
4714                         adapter->rx_ring[k]->dcb_tc = i;
4715                 }
4716         }
4717
4718         return true;
4719 }
4720 #endif
4721
4722 /**
4723  * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4724  * @adapter: board private structure to initialize
4725  *
4726  * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4727  *
4728  **/
4729 static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4730 {
4731         int i;
4732         bool ret = false;
4733
4734         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4735             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4736              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
4737                 for (i = 0; i < adapter->num_rx_queues; i++)
4738                         adapter->rx_ring[i]->reg_idx = i;
4739                 for (i = 0; i < adapter->num_tx_queues; i++)
4740                         adapter->tx_ring[i]->reg_idx = i;
4741                 ret = true;
4742         }
4743
4744         return ret;
4745 }
4746
4747 #ifdef IXGBE_FCOE
4748 /**
4749  * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4750  * @adapter: board private structure to initialize
4751  *
4752  * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4753  *
4754  */
4755 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4756 {
4757         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4758         int i;
4759         u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
4760
4761         if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4762                 return false;
4763
4764         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4765                 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4766                     (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4767                         ixgbe_cache_ring_fdir(adapter);
4768                 else
4769                         ixgbe_cache_ring_rss(adapter);
4770
4771                 fcoe_rx_i = f->mask;
4772                 fcoe_tx_i = f->mask;
4773         }
4774         for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4775                 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4776                 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4777         }
4778         return true;
4779 }
4780
4781 #endif /* IXGBE_FCOE */
4782 /**
4783  * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4784  * @adapter: board private structure to initialize
4785  *
4786  * SR-IOV doesn't use any descriptor rings but changes the default if
4787  * no other mapping is used.
4788  *
4789  */
4790 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4791 {
4792         adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4793         adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
4794         if (adapter->num_vfs)
4795                 return true;
4796         else
4797                 return false;
4798 }
4799
4800 /**
4801  * ixgbe_cache_ring_register - Descriptor ring to register mapping
4802  * @adapter: board private structure to initialize
4803  *
4804  * Once we know the feature-set enabled for the device, we'll cache
4805  * the register offset the descriptor ring is assigned to.
4806  *
4807  * Note, the order the various feature calls is important.  It must start with
4808  * the "most" features enabled at the same time, then trickle down to the
4809  * least amount of features turned on at once.
4810  **/
4811 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4812 {
4813         /* start with default case */
4814         adapter->rx_ring[0]->reg_idx = 0;
4815         adapter->tx_ring[0]->reg_idx = 0;
4816
4817         if (ixgbe_cache_ring_sriov(adapter))
4818                 return;
4819
4820 #ifdef CONFIG_IXGBE_DCB
4821         if (ixgbe_cache_ring_dcb(adapter))
4822                 return;
4823 #endif
4824
4825 #ifdef IXGBE_FCOE
4826         if (ixgbe_cache_ring_fcoe(adapter))
4827                 return;
4828 #endif /* IXGBE_FCOE */
4829
4830         if (ixgbe_cache_ring_fdir(adapter))
4831                 return;
4832
4833         if (ixgbe_cache_ring_rss(adapter))
4834                 return;
4835 }
4836
4837 /**
4838  * ixgbe_alloc_queues - Allocate memory for all rings
4839  * @adapter: board private structure to initialize
4840  *
4841  * We allocate one ring per queue at run-time since we don't know the
4842  * number of queues at compile-time.  The polling_netdev array is
4843  * intended for Multiqueue, but should work fine with a single queue.
4844  **/
4845 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
4846 {
4847         int rx = 0, tx = 0, nid = adapter->node;
4848
4849         if (nid < 0 || !node_online(nid))
4850                 nid = first_online_node;
4851
4852         for (; tx < adapter->num_tx_queues; tx++) {
4853                 struct ixgbe_ring *ring;
4854
4855                 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4856                 if (!ring)
4857                         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4858                 if (!ring)
4859                         goto err_allocation;
4860                 ring->count = adapter->tx_ring_count;
4861                 ring->queue_index = tx;
4862                 ring->numa_node = nid;
4863                 ring->dev = &adapter->pdev->dev;
4864                 ring->netdev = adapter->netdev;
4865
4866                 adapter->tx_ring[tx] = ring;
4867         }
4868
4869         for (; rx < adapter->num_rx_queues; rx++) {
4870                 struct ixgbe_ring *ring;
4871
4872                 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4873                 if (!ring)
4874                         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4875                 if (!ring)
4876                         goto err_allocation;
4877                 ring->count = adapter->rx_ring_count;
4878                 ring->queue_index = rx;
4879                 ring->numa_node = nid;
4880                 ring->dev = &adapter->pdev->dev;
4881                 ring->netdev = adapter->netdev;
4882
4883                 adapter->rx_ring[rx] = ring;
4884         }
4885
4886         ixgbe_cache_ring_register(adapter);
4887
4888         return 0;
4889
4890 err_allocation:
4891         while (tx)
4892                 kfree(adapter->tx_ring[--tx]);
4893
4894         while (rx)
4895                 kfree(adapter->rx_ring[--rx]);
4896         return -ENOMEM;
4897 }
4898
4899 /**
4900  * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4901  * @adapter: board private structure to initialize
4902  *
4903  * Attempt to configure the interrupts using the best available
4904  * capabilities of the hardware and the kernel.
4905  **/
4906 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
4907 {
4908         struct ixgbe_hw *hw = &adapter->hw;
4909         int err = 0;
4910         int vector, v_budget;
4911
4912         /*
4913          * It's easy to be greedy for MSI-X vectors, but it really
4914          * doesn't do us much good if we have a lot more vectors
4915          * than CPU's.  So let's be conservative and only ask for
4916          * (roughly) the same number of vectors as there are CPU's.
4917          */
4918         v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
4919                        (int)num_online_cpus()) + NON_Q_VECTORS;
4920
4921         /*
4922          * At the same time, hardware can only support a maximum of
4923          * hw.mac->max_msix_vectors vectors.  With features
4924          * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4925          * descriptor queues supported by our device.  Thus, we cap it off in
4926          * those rare cases where the cpu count also exceeds our vector limit.
4927          */
4928         v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
4929
4930         /* A failure in MSI-X entry allocation isn't fatal, but it does
4931          * mean we disable MSI-X capabilities of the adapter. */
4932         adapter->msix_entries = kcalloc(v_budget,
4933                                         sizeof(struct msix_entry), GFP_KERNEL);
4934         if (adapter->msix_entries) {
4935                 for (vector = 0; vector < v_budget; vector++)
4936                         adapter->msix_entries[vector].entry = vector;
4937
4938                 ixgbe_acquire_msix_vectors(adapter, v_budget);
4939
4940                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4941                         goto out;
4942         }
4943
4944         adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4945         adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4946         if (adapter->flags & (IXGBE_FLAG_FDIR_HASH_CAPABLE |
4947                               IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
4948                 e_err(probe,
4949                       "Flow Director is not supported while multiple "
4950                       "queues are disabled.  Disabling Flow Director\n");
4951         }
4952         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4953         adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4954         adapter->atr_sample_rate = 0;
4955         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4956                 ixgbe_disable_sriov(adapter);
4957
4958         err = ixgbe_set_num_queues(adapter);
4959         if (err)
4960                 return err;
4961
4962         err = pci_enable_msi(adapter->pdev);
4963         if (!err) {
4964                 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4965         } else {
4966                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4967                              "Unable to allocate MSI interrupt, "
4968                              "falling back to legacy.  Error: %d\n", err);
4969                 /* reset err */
4970                 err = 0;
4971         }
4972
4973 out:
4974         return err;
4975 }
4976
4977 /**
4978  * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4979  * @adapter: board private structure to initialize
4980  *
4981  * We allocate one q_vector per queue interrupt.  If allocation fails we
4982  * return -ENOMEM.
4983  **/
4984 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4985 {
4986         int q_idx, num_q_vectors;
4987         struct ixgbe_q_vector *q_vector;
4988         int (*poll)(struct napi_struct *, int);
4989
4990         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4991                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4992                 poll = &ixgbe_clean_rxtx_many;
4993         } else {
4994                 num_q_vectors = 1;
4995                 poll = &ixgbe_poll;
4996         }
4997
4998         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4999                 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
5000                                         GFP_KERNEL, adapter->node);
5001                 if (!q_vector)
5002                         q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
5003                                            GFP_KERNEL);
5004                 if (!q_vector)
5005                         goto err_out;
5006                 q_vector->adapter = adapter;
5007                 if (q_vector->txr_count && !q_vector->rxr_count)
5008                         q_vector->eitr = adapter->tx_eitr_param;
5009                 else
5010                         q_vector->eitr = adapter->rx_eitr_param;
5011                 q_vector->v_idx = q_idx;
5012                 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
5013                 adapter->q_vector[q_idx] = q_vector;
5014         }
5015
5016         return 0;
5017
5018 err_out:
5019         while (q_idx) {
5020                 q_idx--;
5021                 q_vector = adapter->q_vector[q_idx];
5022                 netif_napi_del(&q_vector->napi);
5023                 kfree(q_vector);
5024                 adapter->q_vector[q_idx] = NULL;
5025         }
5026         return -ENOMEM;
5027 }
5028
5029 /**
5030  * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
5031  * @adapter: board private structure to initialize
5032  *
5033  * This function frees the memory allocated to the q_vectors.  In addition if
5034  * NAPI is enabled it will delete any references to the NAPI struct prior
5035  * to freeing the q_vector.
5036  **/
5037 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
5038 {
5039         int q_idx, num_q_vectors;
5040
5041         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
5042                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
5043         else
5044                 num_q_vectors = 1;
5045
5046         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
5047                 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
5048                 adapter->q_vector[q_idx] = NULL;
5049                 netif_napi_del(&q_vector->napi);
5050                 kfree(q_vector);
5051         }
5052 }
5053
5054 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
5055 {
5056         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5057                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
5058                 pci_disable_msix(adapter->pdev);
5059                 kfree(adapter->msix_entries);
5060                 adapter->msix_entries = NULL;
5061         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
5062                 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
5063                 pci_disable_msi(adapter->pdev);
5064         }
5065 }
5066
5067 /**
5068  * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
5069  * @adapter: board private structure to initialize
5070  *
5071  * We determine which interrupt scheme to use based on...
5072  * - Kernel support (MSI, MSI-X)
5073  *   - which can be user-defined (via MODULE_PARAM)
5074  * - Hardware queue count (num_*_queues)
5075  *   - defined by miscellaneous hardware support/features (RSS, etc.)
5076  **/
5077 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
5078 {
5079         int err;
5080
5081         /* Number of supported queues */
5082         err = ixgbe_set_num_queues(adapter);
5083         if (err)
5084                 return err;
5085
5086         err = ixgbe_set_interrupt_capability(adapter);
5087         if (err) {
5088                 e_dev_err("Unable to setup interrupt capabilities\n");
5089                 goto err_set_interrupt;
5090         }
5091
5092         err = ixgbe_alloc_q_vectors(adapter);
5093         if (err) {
5094                 e_dev_err("Unable to allocate memory for queue vectors\n");
5095                 goto err_alloc_q_vectors;
5096         }
5097
5098         err = ixgbe_alloc_queues(adapter);
5099         if (err) {
5100                 e_dev_err("Unable to allocate memory for queues\n");
5101                 goto err_alloc_queues;
5102         }
5103
5104         e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
5105                    (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
5106                    adapter->num_rx_queues, adapter->num_tx_queues);
5107
5108         set_bit(__IXGBE_DOWN, &adapter->state);
5109
5110         return 0;
5111
5112 err_alloc_queues:
5113         ixgbe_free_q_vectors(adapter);
5114 err_alloc_q_vectors:
5115         ixgbe_reset_interrupt_capability(adapter);
5116 err_set_interrupt:
5117         return err;
5118 }
5119
5120 static void ring_free_rcu(struct rcu_head *head)
5121 {
5122         kfree(container_of(head, struct ixgbe_ring, rcu));
5123 }
5124
5125 /**
5126  * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
5127  * @adapter: board private structure to clear interrupt scheme on
5128  *
5129  * We go through and clear interrupt specific resources and reset the structure
5130  * to pre-load conditions
5131  **/
5132 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
5133 {
5134         int i;
5135
5136         for (i = 0; i < adapter->num_tx_queues; i++) {
5137                 kfree(adapter->tx_ring[i]);
5138                 adapter->tx_ring[i] = NULL;
5139         }
5140         for (i = 0; i < adapter->num_rx_queues; i++) {
5141                 struct ixgbe_ring *ring = adapter->rx_ring[i];
5142
5143                 /* ixgbe_get_stats64() might access this ring, we must wait
5144                  * a grace period before freeing it.
5145                  */
5146                 call_rcu(&ring->rcu, ring_free_rcu);
5147                 adapter->rx_ring[i] = NULL;
5148         }
5149
5150         adapter->num_tx_queues = 0;
5151         adapter->num_rx_queues = 0;
5152
5153         ixgbe_free_q_vectors(adapter);
5154         ixgbe_reset_interrupt_capability(adapter);
5155 }
5156
5157 /**
5158  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5159  * @adapter: board private structure to initialize
5160  *
5161  * ixgbe_sw_init initializes the Adapter private data structure.
5162  * Fields are initialized based on PCI device information and
5163  * OS network device settings (MTU size).
5164  **/
5165 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
5166 {
5167         struct ixgbe_hw *hw = &adapter->hw;
5168         struct pci_dev *pdev = adapter->pdev;
5169         struct net_device *dev = adapter->netdev;
5170         unsigned int rss;
5171 #ifdef CONFIG_IXGBE_DCB
5172         int j;
5173         struct tc_configuration *tc;
5174 #endif
5175         int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
5176
5177         /* PCI config space info */
5178
5179         hw->vendor_id = pdev->vendor;
5180         hw->device_id = pdev->device;
5181         hw->revision_id = pdev->revision;
5182         hw->subsystem_vendor_id = pdev->subsystem_vendor;
5183         hw->subsystem_device_id = pdev->subsystem_device;
5184
5185         /* Set capability flags */
5186         rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
5187         adapter->ring_feature[RING_F_RSS].indices = rss;
5188         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
5189         adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
5190         switch (hw->mac.type) {
5191         case ixgbe_mac_82598EB:
5192                 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5193                         adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
5194                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
5195                 break;
5196         case ixgbe_mac_82599EB:
5197         case ixgbe_mac_X540:
5198                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
5199                 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5200                 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
5201                 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5202                         adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
5203                 /* n-tuple support exists, always init our spinlock */
5204                 spin_lock_init(&adapter->fdir_perfect_lock);
5205                 /* Flow Director hash filters enabled */
5206                 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
5207                 adapter->atr_sample_rate = 20;
5208                 adapter->ring_feature[RING_F_FDIR].indices =
5209                                                          IXGBE_MAX_FDIR_INDICES;
5210                 adapter->fdir_pballoc = 0;
5211 #ifdef IXGBE_FCOE
5212                 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5213                 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5214                 adapter->ring_feature[RING_F_FCOE].indices = 0;
5215 #ifdef CONFIG_IXGBE_DCB
5216                 /* Default traffic class to use for FCoE */
5217                 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
5218                 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
5219 #endif
5220 #endif /* IXGBE_FCOE */
5221                 break;
5222         default:
5223                 break;
5224         }
5225
5226 #ifdef CONFIG_IXGBE_DCB
5227         /* Configure DCB traffic classes */
5228         for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5229                 tc = &adapter->dcb_cfg.tc_config[j];
5230                 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5231                 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5232                 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5233                 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5234                 tc->dcb_pfc = pfc_disabled;
5235         }
5236         adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5237         adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
5238         adapter->dcb_cfg.rx_pba_cfg = pba_equal;
5239         adapter->dcb_cfg.pfc_mode_enable = false;
5240         adapter->dcb_set_bitmap = 0x00;
5241         adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
5242         ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
5243                            MAX_TRAFFIC_CLASS);
5244
5245 #endif
5246
5247         /* default flow control settings */
5248         hw->fc.requested_mode = ixgbe_fc_full;
5249         hw->fc.current_mode = ixgbe_fc_full;    /* init for ethtool output */
5250 #ifdef CONFIG_DCB
5251         adapter->last_lfc_mode = hw->fc.current_mode;
5252 #endif
5253         hw->fc.high_water = FC_HIGH_WATER(max_frame);
5254         hw->fc.low_water = FC_LOW_WATER(max_frame);
5255         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5256         hw->fc.send_xon = true;
5257         hw->fc.disable_fc_autoneg = false;
5258
5259         /* enable itr by default in dynamic mode */
5260         adapter->rx_itr_setting = 1;
5261         adapter->rx_eitr_param = 20000;
5262         adapter->tx_itr_setting = 1;
5263         adapter->tx_eitr_param = 10000;
5264
5265         /* set defaults for eitr in MegaBytes */
5266         adapter->eitr_low = 10;
5267         adapter->eitr_high = 20;
5268
5269         /* set default ring sizes */
5270         adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5271         adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5272
5273         /* initialize eeprom parameters */
5274         if (ixgbe_init_eeprom_params_generic(hw)) {
5275                 e_dev_err("EEPROM initialization failed\n");
5276                 return -EIO;
5277         }
5278
5279         /* enable rx csum by default */
5280         adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
5281
5282         /* get assigned NUMA node */
5283         adapter->node = dev_to_node(&pdev->dev);
5284
5285         set_bit(__IXGBE_DOWN, &adapter->state);
5286
5287         return 0;
5288 }
5289
5290 /**
5291  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
5292  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
5293  *
5294  * Return 0 on success, negative on failure
5295  **/
5296 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
5297 {
5298         struct device *dev = tx_ring->dev;
5299         int size;
5300
5301         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5302         tx_ring->tx_buffer_info = vzalloc_node(size, tx_ring->numa_node);
5303         if (!tx_ring->tx_buffer_info)
5304                 tx_ring->tx_buffer_info = vzalloc(size);
5305         if (!tx_ring->tx_buffer_info)
5306                 goto err;
5307
5308         /* round up to nearest 4K */
5309         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
5310         tx_ring->size = ALIGN(tx_ring->size, 4096);
5311
5312         tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5313                                            &tx_ring->dma, GFP_KERNEL);
5314         if (!tx_ring->desc)
5315                 goto err;
5316
5317         tx_ring->next_to_use = 0;
5318         tx_ring->next_to_clean = 0;
5319         tx_ring->work_limit = tx_ring->count;
5320         return 0;
5321
5322 err:
5323         vfree(tx_ring->tx_buffer_info);
5324         tx_ring->tx_buffer_info = NULL;
5325         dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
5326         return -ENOMEM;
5327 }
5328
5329 /**
5330  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5331  * @adapter: board private structure
5332  *
5333  * If this function returns with an error, then it's possible one or
5334  * more of the rings is populated (while the rest are not).  It is the
5335  * callers duty to clean those orphaned rings.
5336  *
5337  * Return 0 on success, negative on failure
5338  **/
5339 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5340 {
5341         int i, err = 0;
5342
5343         for (i = 0; i < adapter->num_tx_queues; i++) {
5344                 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
5345                 if (!err)
5346                         continue;
5347                 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
5348                 break;
5349         }
5350
5351         return err;
5352 }
5353
5354 /**
5355  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5356  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
5357  *
5358  * Returns 0 on success, negative on failure
5359  **/
5360 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
5361 {
5362         struct device *dev = rx_ring->dev;
5363         int size;
5364
5365         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
5366         rx_ring->rx_buffer_info = vzalloc_node(size, rx_ring->numa_node);
5367         if (!rx_ring->rx_buffer_info)
5368                 rx_ring->rx_buffer_info = vzalloc(size);
5369         if (!rx_ring->rx_buffer_info)
5370                 goto err;
5371
5372         /* Round up to nearest 4K */
5373         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5374         rx_ring->size = ALIGN(rx_ring->size, 4096);
5375
5376         rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5377                                            &rx_ring->dma, GFP_KERNEL);
5378
5379         if (!rx_ring->desc)
5380                 goto err;
5381
5382         rx_ring->next_to_clean = 0;
5383         rx_ring->next_to_use = 0;
5384
5385         return 0;
5386 err:
5387         vfree(rx_ring->rx_buffer_info);
5388         rx_ring->rx_buffer_info = NULL;
5389         dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
5390         return -ENOMEM;
5391 }
5392
5393 /**
5394  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5395  * @adapter: board private structure
5396  *
5397  * If this function returns with an error, then it's possible one or
5398  * more of the rings is populated (while the rest are not).  It is the
5399  * callers duty to clean those orphaned rings.
5400  *
5401  * Return 0 on success, negative on failure
5402  **/
5403 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5404 {
5405         int i, err = 0;
5406
5407         for (i = 0; i < adapter->num_rx_queues; i++) {
5408                 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
5409                 if (!err)
5410                         continue;
5411                 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
5412                 break;
5413         }
5414
5415         return err;
5416 }
5417
5418 /**
5419  * ixgbe_free_tx_resources - Free Tx Resources per Queue
5420  * @tx_ring: Tx descriptor ring for a specific queue
5421  *
5422  * Free all transmit software resources
5423  **/
5424 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
5425 {
5426         ixgbe_clean_tx_ring(tx_ring);
5427
5428         vfree(tx_ring->tx_buffer_info);
5429         tx_ring->tx_buffer_info = NULL;
5430
5431         /* if not set, then don't free */
5432         if (!tx_ring->desc)
5433                 return;
5434
5435         dma_free_coherent(tx_ring->dev, tx_ring->size,
5436                           tx_ring->desc, tx_ring->dma);
5437
5438         tx_ring->desc = NULL;
5439 }
5440
5441 /**
5442  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5443  * @adapter: board private structure
5444  *
5445  * Free all transmit software resources
5446  **/
5447 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5448 {
5449         int i;
5450
5451         for (i = 0; i < adapter->num_tx_queues; i++)
5452                 if (adapter->tx_ring[i]->desc)
5453                         ixgbe_free_tx_resources(adapter->tx_ring[i]);
5454 }
5455
5456 /**
5457  * ixgbe_free_rx_resources - Free Rx Resources
5458  * @rx_ring: ring to clean the resources from
5459  *
5460  * Free all receive software resources
5461  **/
5462 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
5463 {
5464         ixgbe_clean_rx_ring(rx_ring);
5465
5466         vfree(rx_ring->rx_buffer_info);
5467         rx_ring->rx_buffer_info = NULL;
5468
5469         /* if not set, then don't free */
5470         if (!rx_ring->desc)
5471                 return;
5472
5473         dma_free_coherent(rx_ring->dev, rx_ring->size,
5474                           rx_ring->desc, rx_ring->dma);
5475
5476         rx_ring->desc = NULL;
5477 }
5478
5479 /**
5480  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5481  * @adapter: board private structure
5482  *
5483  * Free all receive software resources
5484  **/
5485 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5486 {
5487         int i;
5488
5489         for (i = 0; i < adapter->num_rx_queues; i++)
5490                 if (adapter->rx_ring[i]->desc)
5491                         ixgbe_free_rx_resources(adapter->rx_ring[i]);
5492 }
5493
5494 /**
5495  * ixgbe_change_mtu - Change the Maximum Transfer Unit
5496  * @netdev: network interface device structure
5497  * @new_mtu: new value for maximum frame size
5498  *
5499  * Returns 0 on success, negative on failure
5500  **/
5501 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5502 {
5503         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5504         struct ixgbe_hw *hw = &adapter->hw;
5505         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5506
5507         /* MTU < 68 is an error and causes problems on some kernels */
5508         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED &&
5509             hw->mac.type != ixgbe_mac_X540) {
5510                 if ((new_mtu < 68) || (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
5511                         return -EINVAL;
5512         } else {
5513                 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5514                         return -EINVAL;
5515         }
5516
5517         e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5518         /* must set new MTU before calling down or up */
5519         netdev->mtu = new_mtu;
5520
5521         hw->fc.high_water = FC_HIGH_WATER(max_frame);
5522         hw->fc.low_water = FC_LOW_WATER(max_frame);
5523
5524         if (netif_running(netdev))
5525                 ixgbe_reinit_locked(adapter);
5526
5527         return 0;
5528 }
5529
5530 /**
5531  * ixgbe_open - Called when a network interface is made active
5532  * @netdev: network interface device structure
5533  *
5534  * Returns 0 on success, negative value on failure
5535  *
5536  * The open entry point is called when a network interface is made
5537  * active by the system (IFF_UP).  At this point all resources needed
5538  * for transmit and receive operations are allocated, the interrupt
5539  * handler is registered with the OS, the watchdog timer is started,
5540  * and the stack is notified that the interface is ready.
5541  **/
5542 static int ixgbe_open(struct net_device *netdev)
5543 {
5544         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5545         int err;
5546
5547         /* disallow open during test */
5548         if (test_bit(__IXGBE_TESTING, &adapter->state))
5549                 return -EBUSY;
5550
5551         netif_carrier_off(netdev);
5552
5553         /* allocate transmit descriptors */
5554         err = ixgbe_setup_all_tx_resources(adapter);
5555         if (err)
5556                 goto err_setup_tx;
5557
5558         /* allocate receive descriptors */
5559         err = ixgbe_setup_all_rx_resources(adapter);
5560         if (err)
5561                 goto err_setup_rx;
5562
5563         ixgbe_configure(adapter);
5564
5565         err = ixgbe_request_irq(adapter);
5566         if (err)
5567                 goto err_req_irq;
5568
5569         err = ixgbe_up_complete(adapter);
5570         if (err)
5571                 goto err_up;
5572
5573         netif_tx_start_all_queues(netdev);
5574
5575         return 0;
5576
5577 err_up:
5578         ixgbe_release_hw_control(adapter);
5579         ixgbe_free_irq(adapter);
5580 err_req_irq:
5581 err_setup_rx:
5582         ixgbe_free_all_rx_resources(adapter);
5583 err_setup_tx:
5584         ixgbe_free_all_tx_resources(adapter);
5585         ixgbe_reset(adapter);
5586
5587         return err;
5588 }
5589
5590 /**
5591  * ixgbe_close - Disables a network interface
5592  * @netdev: network interface device structure
5593  *
5594  * Returns 0, this is not allowed to fail
5595  *
5596  * The close entry point is called when an interface is de-activated
5597  * by the OS.  The hardware is still under the drivers control, but
5598  * needs to be disabled.  A global MAC reset is issued to stop the
5599  * hardware, and all transmit and receive resources are freed.
5600  **/
5601 static int ixgbe_close(struct net_device *netdev)
5602 {
5603         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5604
5605         ixgbe_down(adapter);
5606         ixgbe_free_irq(adapter);
5607
5608         ixgbe_free_all_tx_resources(adapter);
5609         ixgbe_free_all_rx_resources(adapter);
5610
5611         ixgbe_release_hw_control(adapter);
5612
5613         return 0;
5614 }
5615
5616 #ifdef CONFIG_PM
5617 static int ixgbe_resume(struct pci_dev *pdev)
5618 {
5619         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5620         struct net_device *netdev = adapter->netdev;
5621         u32 err;
5622
5623         pci_set_power_state(pdev, PCI_D0);
5624         pci_restore_state(pdev);
5625         /*
5626          * pci_restore_state clears dev->state_saved so call
5627          * pci_save_state to restore it.
5628          */
5629         pci_save_state(pdev);
5630
5631         err = pci_enable_device_mem(pdev);
5632         if (err) {
5633                 e_dev_err("Cannot enable PCI device from suspend\n");
5634                 return err;
5635         }
5636         pci_set_master(pdev);
5637
5638         pci_wake_from_d3(pdev, false);
5639
5640         err = ixgbe_init_interrupt_scheme(adapter);
5641         if (err) {
5642                 e_dev_err("Cannot initialize interrupts for device\n");
5643                 return err;
5644         }
5645
5646         ixgbe_reset(adapter);
5647
5648         IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5649
5650         if (netif_running(netdev)) {
5651                 err = ixgbe_open(netdev);
5652                 if (err)
5653                         return err;
5654         }
5655
5656         netif_device_attach(netdev);
5657
5658         return 0;
5659 }
5660 #endif /* CONFIG_PM */
5661
5662 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5663 {
5664         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5665         struct net_device *netdev = adapter->netdev;
5666         struct ixgbe_hw *hw = &adapter->hw;
5667         u32 ctrl, fctrl;
5668         u32 wufc = adapter->wol;
5669 #ifdef CONFIG_PM
5670         int retval = 0;
5671 #endif
5672
5673         netif_device_detach(netdev);
5674
5675         if (netif_running(netdev)) {
5676                 ixgbe_down(adapter);
5677                 ixgbe_free_irq(adapter);
5678                 ixgbe_free_all_tx_resources(adapter);
5679                 ixgbe_free_all_rx_resources(adapter);
5680         }
5681
5682         ixgbe_clear_interrupt_scheme(adapter);
5683 #ifdef CONFIG_DCB
5684         kfree(adapter->ixgbe_ieee_pfc);
5685         kfree(adapter->ixgbe_ieee_ets);
5686 #endif
5687
5688 #ifdef CONFIG_PM
5689         retval = pci_save_state(pdev);
5690         if (retval)
5691                 return retval;
5692
5693 #endif
5694         if (wufc) {
5695                 ixgbe_set_rx_mode(netdev);
5696
5697                 /* turn on all-multi mode if wake on multicast is enabled */
5698                 if (wufc & IXGBE_WUFC_MC) {
5699                         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5700                         fctrl |= IXGBE_FCTRL_MPE;
5701                         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5702                 }
5703
5704                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5705                 ctrl |= IXGBE_CTRL_GIO_DIS;
5706                 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5707
5708                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5709         } else {
5710                 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5711                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5712         }
5713
5714         switch (hw->mac.type) {
5715         case ixgbe_mac_82598EB:
5716                 pci_wake_from_d3(pdev, false);
5717                 break;
5718         case ixgbe_mac_82599EB:
5719         case ixgbe_mac_X540:
5720                 pci_wake_from_d3(pdev, !!wufc);
5721                 break;
5722         default:
5723                 break;
5724         }
5725
5726         *enable_wake = !!wufc;
5727
5728         ixgbe_release_hw_control(adapter);
5729
5730         pci_disable_device(pdev);
5731
5732         return 0;
5733 }
5734
5735 #ifdef CONFIG_PM
5736 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5737 {
5738         int retval;
5739         bool wake;
5740
5741         retval = __ixgbe_shutdown(pdev, &wake);
5742         if (retval)
5743                 return retval;
5744
5745         if (wake) {
5746                 pci_prepare_to_sleep(pdev);
5747         } else {
5748                 pci_wake_from_d3(pdev, false);
5749                 pci_set_power_state(pdev, PCI_D3hot);
5750         }
5751
5752         return 0;
5753 }
5754 #endif /* CONFIG_PM */
5755
5756 static void ixgbe_shutdown(struct pci_dev *pdev)
5757 {
5758         bool wake;
5759
5760         __ixgbe_shutdown(pdev, &wake);
5761
5762         if (system_state == SYSTEM_POWER_OFF) {
5763                 pci_wake_from_d3(pdev, wake);
5764                 pci_set_power_state(pdev, PCI_D3hot);
5765         }
5766 }
5767
5768 /**
5769  * ixgbe_update_stats - Update the board statistics counters.
5770  * @adapter: board private structure
5771  **/
5772 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5773 {
5774         struct net_device *netdev = adapter->netdev;
5775         struct ixgbe_hw *hw = &adapter->hw;
5776         struct ixgbe_hw_stats *hwstats = &adapter->stats;
5777         u64 total_mpc = 0;
5778         u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5779         u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5780         u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5781         u64 bytes = 0, packets = 0;
5782
5783         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5784             test_bit(__IXGBE_RESETTING, &adapter->state))
5785                 return;
5786
5787         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5788                 u64 rsc_count = 0;
5789                 u64 rsc_flush = 0;
5790                 for (i = 0; i < 16; i++)
5791                         adapter->hw_rx_no_dma_resources +=
5792                                 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5793                 for (i = 0; i < adapter->num_rx_queues; i++) {
5794                         rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5795                         rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5796                 }
5797                 adapter->rsc_total_count = rsc_count;
5798                 adapter->rsc_total_flush = rsc_flush;
5799         }
5800
5801         for (i = 0; i < adapter->num_rx_queues; i++) {
5802                 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5803                 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5804                 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5805                 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5806                 bytes += rx_ring->stats.bytes;
5807                 packets += rx_ring->stats.packets;
5808         }
5809         adapter->non_eop_descs = non_eop_descs;
5810         adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5811         adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5812         netdev->stats.rx_bytes = bytes;
5813         netdev->stats.rx_packets = packets;
5814
5815         bytes = 0;
5816         packets = 0;
5817         /* gather some stats to the adapter struct that are per queue */
5818         for (i = 0; i < adapter->num_tx_queues; i++) {
5819                 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5820                 restart_queue += tx_ring->tx_stats.restart_queue;
5821                 tx_busy += tx_ring->tx_stats.tx_busy;
5822                 bytes += tx_ring->stats.bytes;
5823                 packets += tx_ring->stats.packets;
5824         }
5825         adapter->restart_queue = restart_queue;
5826         adapter->tx_busy = tx_busy;
5827         netdev->stats.tx_bytes = bytes;
5828         netdev->stats.tx_packets = packets;
5829
5830         hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5831         for (i = 0; i < 8; i++) {
5832                 /* for packet buffers not used, the register should read 0 */
5833                 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5834                 missed_rx += mpc;
5835                 hwstats->mpc[i] += mpc;
5836                 total_mpc += hwstats->mpc[i];
5837                 if (hw->mac.type == ixgbe_mac_82598EB)
5838                         hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5839                 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5840                 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5841                 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5842                 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5843                 switch (hw->mac.type) {
5844                 case ixgbe_mac_82598EB:
5845                         hwstats->pxonrxc[i] +=
5846                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5847                         break;
5848                 case ixgbe_mac_82599EB:
5849                 case ixgbe_mac_X540:
5850                         hwstats->pxonrxc[i] +=
5851                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5852                         break;
5853                 default:
5854                         break;
5855                 }
5856                 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5857                 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5858         }
5859         hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5860         /* work around hardware counting issue */
5861         hwstats->gprc -= missed_rx;
5862
5863         ixgbe_update_xoff_received(adapter);
5864
5865         /* 82598 hardware only has a 32 bit counter in the high register */
5866         switch (hw->mac.type) {
5867         case ixgbe_mac_82598EB:
5868                 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5869                 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5870                 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5871                 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5872                 break;
5873         case ixgbe_mac_X540:
5874                 /* OS2BMC stats are X540 only*/
5875                 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5876                 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5877                 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5878                 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5879         case ixgbe_mac_82599EB:
5880                 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5881                 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
5882                 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5883                 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
5884                 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5885                 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5886                 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5887                 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5888                 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5889 #ifdef IXGBE_FCOE
5890                 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5891                 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5892                 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5893                 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5894                 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5895                 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5896 #endif /* IXGBE_FCOE */
5897                 break;
5898         default:
5899                 break;
5900         }
5901         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5902         hwstats->bprc += bprc;
5903         hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5904         if (hw->mac.type == ixgbe_mac_82598EB)
5905                 hwstats->mprc -= bprc;
5906         hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5907         hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5908         hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5909         hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5910         hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5911         hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5912         hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5913         hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5914         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5915         hwstats->lxontxc += lxon;
5916         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5917         hwstats->lxofftxc += lxoff;
5918         hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5919         hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5920         hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5921         /*
5922          * 82598 errata - tx of flow control packets is included in tx counters
5923          */
5924         xon_off_tot = lxon + lxoff;
5925         hwstats->gptc -= xon_off_tot;
5926         hwstats->mptc -= xon_off_tot;
5927         hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5928         hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5929         hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5930         hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5931         hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5932         hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5933         hwstats->ptc64 -= xon_off_tot;
5934         hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5935         hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5936         hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5937         hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5938         hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5939         hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5940
5941         /* Fill out the OS statistics structure */
5942         netdev->stats.multicast = hwstats->mprc;
5943
5944         /* Rx Errors */
5945         netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5946         netdev->stats.rx_dropped = 0;
5947         netdev->stats.rx_length_errors = hwstats->rlec;
5948         netdev->stats.rx_crc_errors = hwstats->crcerrs;
5949         netdev->stats.rx_missed_errors = total_mpc;
5950 }
5951
5952 /**
5953  * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5954  * @work: pointer to work_struct containing our data
5955  **/
5956 static void ixgbe_fdir_reinit_task(struct work_struct *work)
5957 {
5958         struct ixgbe_adapter *adapter = container_of(work,
5959                                                      struct ixgbe_adapter,
5960                                                      fdir_reinit_task);
5961         struct ixgbe_hw *hw = &adapter->hw;
5962         int i;
5963
5964         if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5965                 for (i = 0; i < adapter->num_tx_queues; i++)
5966                         set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5967                                 &(adapter->tx_ring[i]->state));
5968         } else {
5969                 e_err(probe, "failed to finish FDIR re-initialization, "
5970                       "ignored adding FDIR ATR filters\n");
5971         }
5972         /* Done FDIR Re-initialization, enable transmits */
5973         netif_tx_start_all_queues(adapter->netdev);
5974 }
5975
5976 /**
5977  * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5978  * @adapter - pointer to the device adapter structure
5979  *
5980  * This function serves two purposes.  First it strobes the interrupt lines
5981  * in order to make certain interrupts are occuring.  Secondly it sets the
5982  * bits needed to check for TX hangs.  As a result we should immediately
5983  * determine if a hang has occured.
5984  */
5985 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
5986 {
5987         struct ixgbe_hw *hw = &adapter->hw;
5988         u64 eics = 0;
5989         int i;
5990
5991         /* If we're down or resetting, just bail */
5992         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5993             test_bit(__IXGBE_RESETTING, &adapter->state))
5994                 return;
5995
5996         /* Force detection of hung controller */
5997         if (netif_carrier_ok(adapter->netdev)) {
5998                 for (i = 0; i < adapter->num_tx_queues; i++)
5999                         set_check_for_tx_hang(adapter->tx_ring[i]);
6000         }
6001
6002         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
6003                 /*
6004                  * for legacy and MSI interrupts don't set any bits
6005                  * that are enabled for EIAM, because this operation
6006                  * would set *both* EIMS and EICS for any bit in EIAM
6007                  */
6008                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
6009                         (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
6010         } else {
6011                 /* get one bit for every active tx/rx interrupt vector */
6012                 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
6013                         struct ixgbe_q_vector *qv = adapter->q_vector[i];
6014                         if (qv->rxr_count || qv->txr_count)
6015                                 eics |= ((u64)1 << i);
6016                 }
6017         }
6018
6019         /* Cause software interrupt to ensure rings are cleaned */
6020         ixgbe_irq_rearm_queues(adapter, eics);
6021
6022 }
6023
6024 /**
6025  * ixgbe_watchdog_update_link - update the link status
6026  * @adapter - pointer to the device adapter structure
6027  * @link_speed - pointer to a u32 to store the link_speed
6028  **/
6029 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
6030 {
6031         struct ixgbe_hw *hw = &adapter->hw;
6032         u32 link_speed = adapter->link_speed;
6033         bool link_up = adapter->link_up;
6034         int i;
6035
6036         if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
6037                 return;
6038
6039         if (hw->mac.ops.check_link) {
6040                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
6041         } else {
6042                 /* always assume link is up, if no check link function */
6043                 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
6044                 link_up = true;
6045         }
6046         if (link_up) {
6047                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6048                         for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
6049                                 hw->mac.ops.fc_enable(hw, i);
6050                 } else {
6051                         hw->mac.ops.fc_enable(hw, 0);
6052                 }
6053         }
6054
6055         if (link_up ||
6056             time_after(jiffies, (adapter->link_check_timeout +
6057                                  IXGBE_TRY_LINK_TIMEOUT))) {
6058                 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6059                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
6060                 IXGBE_WRITE_FLUSH(hw);
6061         }
6062
6063         adapter->link_up = link_up;
6064         adapter->link_speed = link_speed;
6065 }
6066
6067 /**
6068  * ixgbe_watchdog_link_is_up - update netif_carrier status and
6069  *                             print link up message
6070  * @adapter - pointer to the device adapter structure
6071  **/
6072 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
6073 {
6074         struct net_device *netdev = adapter->netdev;
6075         struct ixgbe_hw *hw = &adapter->hw;
6076         u32 link_speed = adapter->link_speed;
6077         bool flow_rx, flow_tx;
6078
6079         /* only continue if link was previously down */
6080         if (netif_carrier_ok(netdev))
6081                 return;
6082
6083         adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
6084
6085         switch (hw->mac.type) {
6086         case ixgbe_mac_82598EB: {
6087                 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6088                 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
6089                 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6090                 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
6091         }
6092                 break;
6093         case ixgbe_mac_X540:
6094         case ixgbe_mac_82599EB: {
6095                 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6096                 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6097                 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6098                 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6099         }
6100                 break;
6101         default:
6102                 flow_tx = false;
6103                 flow_rx = false;
6104                 break;
6105         }
6106         e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
6107                (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
6108                "10 Gbps" :
6109                (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
6110                "1 Gbps" :
6111                (link_speed == IXGBE_LINK_SPEED_100_FULL ?
6112                "100 Mbps" :
6113                "unknown speed"))),
6114                ((flow_rx && flow_tx) ? "RX/TX" :
6115                (flow_rx ? "RX" :
6116                (flow_tx ? "TX" : "None"))));
6117
6118         netif_carrier_on(netdev);
6119 #ifdef HAVE_IPLINK_VF_CONFIG
6120         ixgbe_check_vf_rate_limit(adapter);
6121 #endif /* HAVE_IPLINK_VF_CONFIG */
6122 }
6123
6124 /**
6125  * ixgbe_watchdog_link_is_down - update netif_carrier status and
6126  *                               print link down message
6127  * @adapter - pointer to the adapter structure
6128  **/
6129 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter* adapter)
6130 {
6131         struct net_device *netdev = adapter->netdev;
6132         struct ixgbe_hw *hw = &adapter->hw;
6133
6134         adapter->link_up = false;
6135         adapter->link_speed = 0;
6136
6137         /* only continue if link was up previously */
6138         if (!netif_carrier_ok(netdev))
6139                 return;
6140
6141         /* poll for SFP+ cable when link is down */
6142         if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
6143                 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
6144
6145         e_info(drv, "NIC Link is Down\n");
6146         netif_carrier_off(netdev);
6147 }
6148
6149 /**
6150  * ixgbe_watchdog_flush_tx - flush queues on link down
6151  * @adapter - pointer to the device adapter structure
6152  **/
6153 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
6154 {
6155         int i;
6156         int some_tx_pending = 0;
6157
6158         if (!netif_carrier_ok(adapter->netdev)) {
6159                 for (i = 0; i < adapter->num_tx_queues; i++) {
6160                         struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
6161                         if (tx_ring->next_to_use != tx_ring->next_to_clean) {
6162                                 some_tx_pending = 1;
6163                                 break;
6164                         }
6165                 }
6166
6167                 if (some_tx_pending) {
6168                         /* We've lost link, so the controller stops DMA,
6169                          * but we've got queued Tx work that's never going
6170                          * to get done, so reset controller to flush Tx.
6171                          * (Do the reset outside of interrupt context).
6172                          */
6173                         adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
6174                 }
6175         }
6176 }
6177
6178 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6179 {
6180         u32 ssvpc;
6181
6182         /* Do not perform spoof check for 82598 */
6183         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6184                 return;
6185
6186         ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6187
6188         /*
6189          * ssvpc register is cleared on read, if zero then no
6190          * spoofed packets in the last interval.
6191          */
6192         if (!ssvpc)
6193                 return;
6194
6195         e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
6196 }
6197
6198 /**
6199  * ixgbe_watchdog_subtask - check and bring link up
6200  * @adapter - pointer to the device adapter structure
6201  **/
6202 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6203 {
6204         /* if interface is down do nothing */
6205         if (test_bit(__IXGBE_DOWN, &adapter->state))
6206                 return;
6207
6208         ixgbe_watchdog_update_link(adapter);
6209
6210         if (adapter->link_up)
6211                 ixgbe_watchdog_link_is_up(adapter);
6212         else
6213                 ixgbe_watchdog_link_is_down(adapter);
6214
6215         ixgbe_spoof_check(adapter);
6216         ixgbe_update_stats(adapter);
6217
6218         ixgbe_watchdog_flush_tx(adapter);
6219 }
6220
6221 /**
6222  * ixgbe_sfp_detection_subtask - poll for SFP+ cable
6223  * @adapter - the ixgbe adapter structure
6224  **/
6225 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
6226 {
6227         struct ixgbe_hw *hw = &adapter->hw;
6228         s32 err;
6229
6230         /* not searching for SFP so there is nothing to do here */
6231         if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6232             !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6233                 return;
6234
6235         /* someone else is in init, wait until next service event */
6236         if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6237                 return;
6238
6239         err = hw->phy.ops.identify_sfp(hw);
6240         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6241                 goto sfp_out;
6242
6243         if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6244                 /* If no cable is present, then we need to reset
6245                  * the next time we find a good cable. */
6246                 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
6247         }
6248
6249         /* exit on error */
6250         if (err)
6251                 goto sfp_out;
6252
6253         /* exit if reset not needed */
6254         if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6255                 goto sfp_out;
6256
6257         adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
6258
6259         /*
6260          * A module may be identified correctly, but the EEPROM may not have
6261          * support for that module.  setup_sfp() will fail in that case, so
6262          * we should not allow that module to load.
6263          */
6264         if (hw->mac.type == ixgbe_mac_82598EB)
6265                 err = hw->phy.ops.reset(hw);
6266         else
6267                 err = hw->mac.ops.setup_sfp(hw);
6268
6269         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6270                 goto sfp_out;
6271
6272         adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6273         e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6274
6275 sfp_out:
6276         clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6277
6278         if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6279             (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6280                 e_dev_err("failed to initialize because an unsupported "
6281                           "SFP+ module type was detected.\n");
6282                 e_dev_err("Reload the driver after installing a "
6283                           "supported module.\n");
6284                 unregister_netdev(adapter->netdev);
6285         }
6286 }
6287
6288 /**
6289  * ixgbe_sfp_link_config_subtask - set up link SFP after module install
6290  * @adapter - the ixgbe adapter structure
6291  **/
6292 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6293 {
6294         struct ixgbe_hw *hw = &adapter->hw;
6295         u32 autoneg;
6296         bool negotiation;
6297
6298         if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6299                 return;
6300
6301         /* someone else is in init, wait until next service event */
6302         if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6303                 return;
6304
6305         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6306
6307         autoneg = hw->phy.autoneg_advertised;
6308         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
6309                 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
6310         hw->mac.autotry_restart = false;
6311         if (hw->mac.ops.setup_link)
6312                 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
6313
6314         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6315         adapter->link_check_timeout = jiffies;
6316         clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6317 }
6318
6319 /**
6320  * ixgbe_service_timer - Timer Call-back
6321  * @data: pointer to adapter cast into an unsigned long
6322  **/
6323 static void ixgbe_service_timer(unsigned long data)
6324 {
6325         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6326         unsigned long next_event_offset;
6327
6328         /* poll faster when waiting for link */
6329         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6330                 next_event_offset = HZ / 10;
6331         else
6332                 next_event_offset = HZ * 2;
6333
6334         /* Reset the timer */
6335         mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6336
6337         ixgbe_service_event_schedule(adapter);
6338 }
6339
6340 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6341 {
6342         if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6343                 return;
6344
6345         adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6346
6347         /* If we're already down or resetting, just bail */
6348         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6349             test_bit(__IXGBE_RESETTING, &adapter->state))
6350                 return;
6351
6352         ixgbe_dump(adapter);
6353         netdev_err(adapter->netdev, "Reset adapter\n");
6354         adapter->tx_timeout_count++;
6355
6356         ixgbe_reinit_locked(adapter);
6357 }
6358
6359 /**
6360  * ixgbe_service_task - manages and runs subtasks
6361  * @work: pointer to work_struct containing our data
6362  **/
6363 static void ixgbe_service_task(struct work_struct *work)
6364 {
6365         struct ixgbe_adapter *adapter = container_of(work,
6366                                                      struct ixgbe_adapter,
6367                                                      service_task);
6368
6369         ixgbe_reset_subtask(adapter);
6370         ixgbe_sfp_detection_subtask(adapter);
6371         ixgbe_sfp_link_config_subtask(adapter);
6372         ixgbe_watchdog_subtask(adapter);
6373         ixgbe_check_hang_subtask(adapter);
6374
6375         ixgbe_service_event_complete(adapter);
6376 }
6377
6378 static int ixgbe_tso(struct ixgbe_adapter *adapter,
6379                      struct ixgbe_ring *tx_ring, struct sk_buff *skb,
6380                      u32 tx_flags, u8 *hdr_len, __be16 protocol)
6381 {
6382         struct ixgbe_adv_tx_context_desc *context_desc;
6383         unsigned int i;
6384         int err;
6385         struct ixgbe_tx_buffer *tx_buffer_info;
6386         u32 vlan_macip_lens = 0, type_tucmd_mlhl;
6387         u32 mss_l4len_idx, l4len;
6388
6389         if (skb_is_gso(skb)) {
6390                 if (skb_header_cloned(skb)) {
6391                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6392                         if (err)
6393                                 return err;
6394                 }
6395                 l4len = tcp_hdrlen(skb);
6396                 *hdr_len += l4len;
6397
6398                 if (protocol == htons(ETH_P_IP)) {
6399                         struct iphdr *iph = ip_hdr(skb);
6400                         iph->tot_len = 0;
6401                         iph->check = 0;
6402                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6403                                                                  iph->daddr, 0,
6404                                                                  IPPROTO_TCP,
6405                                                                  0);
6406                 } else if (skb_is_gso_v6(skb)) {
6407                         ipv6_hdr(skb)->payload_len = 0;
6408                         tcp_hdr(skb)->check =
6409                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6410                                              &ipv6_hdr(skb)->daddr,
6411                                              0, IPPROTO_TCP, 0);
6412                 }
6413
6414                 i = tx_ring->next_to_use;
6415
6416                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6417                 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
6418
6419                 /* VLAN MACLEN IPLEN */
6420                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6421                         vlan_macip_lens |=
6422                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
6423                 vlan_macip_lens |= ((skb_network_offset(skb)) <<
6424                                     IXGBE_ADVTXD_MACLEN_SHIFT);
6425                 *hdr_len += skb_network_offset(skb);
6426                 vlan_macip_lens |=
6427                     (skb_transport_header(skb) - skb_network_header(skb));
6428                 *hdr_len +=
6429                     (skb_transport_header(skb) - skb_network_header(skb));
6430                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6431                 context_desc->seqnum_seed = 0;
6432
6433                 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6434                 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
6435                                    IXGBE_ADVTXD_DTYP_CTXT);
6436
6437                 if (protocol == htons(ETH_P_IP))
6438                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
6439                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6440                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
6441
6442                 /* MSS L4LEN IDX */
6443                 mss_l4len_idx =
6444                     (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
6445                 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
6446                 /* use index 1 for TSO */
6447                 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6448                 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
6449
6450                 tx_buffer_info->time_stamp = jiffies;
6451                 tx_buffer_info->next_to_watch = i;
6452
6453                 i++;
6454                 if (i == tx_ring->count)
6455                         i = 0;
6456                 tx_ring->next_to_use = i;
6457
6458                 return true;
6459         }
6460         return false;
6461 }
6462
6463 static u32 ixgbe_psum(struct ixgbe_adapter *adapter, struct sk_buff *skb,
6464                       __be16 protocol)
6465 {
6466         u32 rtn = 0;
6467
6468         switch (protocol) {
6469         case cpu_to_be16(ETH_P_IP):
6470                 rtn |= IXGBE_ADVTXD_TUCMD_IPV4;
6471                 switch (ip_hdr(skb)->protocol) {
6472                 case IPPROTO_TCP:
6473                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6474                         break;
6475                 case IPPROTO_SCTP:
6476                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6477                         break;
6478                 }
6479                 break;
6480         case cpu_to_be16(ETH_P_IPV6):
6481                 /* XXX what about other V6 headers?? */
6482                 switch (ipv6_hdr(skb)->nexthdr) {
6483                 case IPPROTO_TCP:
6484                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6485                         break;
6486                 case IPPROTO_SCTP:
6487                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6488                         break;
6489                 }
6490                 break;
6491         default:
6492                 if (unlikely(net_ratelimit()))
6493                         e_warn(probe, "partial checksum but proto=%x!\n",
6494                                protocol);
6495                 break;
6496         }
6497
6498         return rtn;
6499 }
6500
6501 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
6502                           struct ixgbe_ring *tx_ring,
6503                           struct sk_buff *skb, u32 tx_flags,
6504                           __be16 protocol)
6505 {
6506         struct ixgbe_adv_tx_context_desc *context_desc;
6507         unsigned int i;
6508         struct ixgbe_tx_buffer *tx_buffer_info;
6509         u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
6510
6511         if (skb->ip_summed == CHECKSUM_PARTIAL ||
6512             (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
6513                 i = tx_ring->next_to_use;
6514                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6515                 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
6516
6517                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6518                         vlan_macip_lens |=
6519                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
6520                 vlan_macip_lens |= (skb_network_offset(skb) <<
6521                                     IXGBE_ADVTXD_MACLEN_SHIFT);
6522                 if (skb->ip_summed == CHECKSUM_PARTIAL)
6523                         vlan_macip_lens |= (skb_transport_header(skb) -
6524                                             skb_network_header(skb));
6525
6526                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6527                 context_desc->seqnum_seed = 0;
6528
6529                 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
6530                                     IXGBE_ADVTXD_DTYP_CTXT);
6531
6532                 if (skb->ip_summed == CHECKSUM_PARTIAL)
6533                         type_tucmd_mlhl |= ixgbe_psum(adapter, skb, protocol);
6534
6535                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
6536                 /* use index zero for tx checksum offload */
6537                 context_desc->mss_l4len_idx = 0;
6538
6539                 tx_buffer_info->time_stamp = jiffies;
6540                 tx_buffer_info->next_to_watch = i;
6541
6542                 i++;
6543                 if (i == tx_ring->count)
6544                         i = 0;
6545                 tx_ring->next_to_use = i;
6546
6547                 return true;
6548         }
6549
6550         return false;
6551 }
6552
6553 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
6554                         struct ixgbe_ring *tx_ring,
6555                         struct sk_buff *skb, u32 tx_flags,
6556                         unsigned int first, const u8 hdr_len)
6557 {
6558         struct device *dev = tx_ring->dev;
6559         struct ixgbe_tx_buffer *tx_buffer_info;
6560         unsigned int len;
6561         unsigned int total = skb->len;
6562         unsigned int offset = 0, size, count = 0, i;
6563         unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
6564         unsigned int f;
6565         unsigned int bytecount = skb->len;
6566         u16 gso_segs = 1;
6567
6568         i = tx_ring->next_to_use;
6569
6570         if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6571                 /* excluding fcoe_crc_eof for FCoE */
6572                 total -= sizeof(struct fcoe_crc_eof);
6573
6574         len = min(skb_headlen(skb), total);
6575         while (len) {
6576                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6577                 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6578
6579                 tx_buffer_info->length = size;
6580                 tx_buffer_info->mapped_as_page = false;
6581                 tx_buffer_info->dma = dma_map_single(dev,
6582                                                      skb->data + offset,
6583                                                      size, DMA_TO_DEVICE);
6584                 if (dma_mapping_error(dev, tx_buffer_info->dma))
6585                         goto dma_error;
6586                 tx_buffer_info->time_stamp = jiffies;
6587                 tx_buffer_info->next_to_watch = i;
6588
6589                 len -= size;
6590                 total -= size;
6591                 offset += size;
6592                 count++;
6593
6594                 if (len) {
6595                         i++;
6596                         if (i == tx_ring->count)
6597                                 i = 0;
6598                 }
6599         }
6600
6601         for (f = 0; f < nr_frags; f++) {
6602                 struct skb_frag_struct *frag;
6603
6604                 frag = &skb_shinfo(skb)->frags[f];
6605                 len = min((unsigned int)frag->size, total);
6606                 offset = frag->page_offset;
6607
6608                 while (len) {
6609                         i++;
6610                         if (i == tx_ring->count)
6611                                 i = 0;
6612
6613                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
6614                         size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6615
6616                         tx_buffer_info->length = size;
6617                         tx_buffer_info->dma = dma_map_page(dev,
6618                                                            frag->page,
6619                                                            offset, size,
6620                                                            DMA_TO_DEVICE);
6621                         tx_buffer_info->mapped_as_page = true;
6622                         if (dma_mapping_error(dev, tx_buffer_info->dma))
6623                                 goto dma_error;
6624                         tx_buffer_info->time_stamp = jiffies;
6625                         tx_buffer_info->next_to_watch = i;
6626
6627                         len -= size;
6628                         total -= size;
6629                         offset += size;
6630                         count++;
6631                 }
6632                 if (total == 0)
6633                         break;
6634         }
6635
6636         if (tx_flags & IXGBE_TX_FLAGS_TSO)
6637                 gso_segs = skb_shinfo(skb)->gso_segs;
6638 #ifdef IXGBE_FCOE
6639         /* adjust for FCoE Sequence Offload */
6640         else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6641                 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6642                                         skb_shinfo(skb)->gso_size);
6643 #endif /* IXGBE_FCOE */
6644         bytecount += (gso_segs - 1) * hdr_len;
6645
6646         /* multiply data chunks by size of headers */
6647         tx_ring->tx_buffer_info[i].bytecount = bytecount;
6648         tx_ring->tx_buffer_info[i].gso_segs = gso_segs;
6649         tx_ring->tx_buffer_info[i].skb = skb;
6650         tx_ring->tx_buffer_info[first].next_to_watch = i;
6651
6652         return count;
6653
6654 dma_error:
6655         e_dev_err("TX DMA map failed\n");
6656
6657         /* clear timestamp and dma mappings for failed tx_buffer_info map */
6658         tx_buffer_info->dma = 0;
6659         tx_buffer_info->time_stamp = 0;
6660         tx_buffer_info->next_to_watch = 0;
6661         if (count)
6662                 count--;
6663
6664         /* clear timestamp and dma mappings for remaining portion of packet */
6665         while (count--) {
6666                 if (i == 0)
6667                         i += tx_ring->count;
6668                 i--;
6669                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6670                 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
6671         }
6672
6673         return 0;
6674 }
6675
6676 static void ixgbe_tx_queue(struct ixgbe_ring *tx_ring,
6677                            int tx_flags, int count, u32 paylen, u8 hdr_len)
6678 {
6679         union ixgbe_adv_tx_desc *tx_desc = NULL;
6680         struct ixgbe_tx_buffer *tx_buffer_info;
6681         u32 olinfo_status = 0, cmd_type_len = 0;
6682         unsigned int i;
6683         u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
6684
6685         cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
6686
6687         cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
6688
6689         if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6690                 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
6691
6692         if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6693                 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6694
6695                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6696                                  IXGBE_ADVTXD_POPTS_SHIFT;
6697
6698                 /* use index 1 context for tso */
6699                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6700                 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6701                         olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
6702                                          IXGBE_ADVTXD_POPTS_SHIFT;
6703
6704         } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6705                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6706                                  IXGBE_ADVTXD_POPTS_SHIFT;
6707
6708         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6709                 olinfo_status |= IXGBE_ADVTXD_CC;
6710                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6711                 if (tx_flags & IXGBE_TX_FLAGS_FSO)
6712                         cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6713         }
6714
6715         olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
6716
6717         i = tx_ring->next_to_use;
6718         while (count--) {
6719                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6720                 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
6721                 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6722                 tx_desc->read.cmd_type_len =
6723                         cpu_to_le32(cmd_type_len | tx_buffer_info->length);
6724                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6725                 i++;
6726                 if (i == tx_ring->count)
6727                         i = 0;
6728         }
6729
6730         tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6731
6732         /*
6733          * Force memory writes to complete before letting h/w
6734          * know there are new descriptors to fetch.  (Only
6735          * applicable for weak-ordered memory model archs,
6736          * such as IA-64).
6737          */
6738         wmb();
6739
6740         tx_ring->next_to_use = i;
6741         writel(i, tx_ring->tail);
6742 }
6743
6744 static void ixgbe_atr(struct ixgbe_ring *ring, struct sk_buff *skb,
6745                       u32 tx_flags, __be16 protocol)
6746 {
6747         struct ixgbe_q_vector *q_vector = ring->q_vector;
6748         union ixgbe_atr_hash_dword input = { .dword = 0 };
6749         union ixgbe_atr_hash_dword common = { .dword = 0 };
6750         union {
6751                 unsigned char *network;
6752                 struct iphdr *ipv4;
6753                 struct ipv6hdr *ipv6;
6754         } hdr;
6755         struct tcphdr *th;
6756         __be16 vlan_id;
6757
6758         /* if ring doesn't have a interrupt vector, cannot perform ATR */
6759         if (!q_vector)
6760                 return;
6761
6762         /* do nothing if sampling is disabled */
6763         if (!ring->atr_sample_rate)
6764                 return;
6765
6766         ring->atr_count++;
6767
6768         /* snag network header to get L4 type and address */
6769         hdr.network = skb_network_header(skb);
6770
6771         /* Currently only IPv4/IPv6 with TCP is supported */
6772         if ((protocol != __constant_htons(ETH_P_IPV6) ||
6773              hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6774             (protocol != __constant_htons(ETH_P_IP) ||
6775              hdr.ipv4->protocol != IPPROTO_TCP))
6776                 return;
6777
6778         th = tcp_hdr(skb);
6779
6780         /* skip this packet since the socket is closing */
6781         if (th->fin)
6782                 return;
6783
6784         /* sample on all syn packets or once every atr sample count */
6785         if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6786                 return;
6787
6788         /* reset sample count */
6789         ring->atr_count = 0;
6790
6791         vlan_id = htons(tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6792
6793         /*
6794          * src and dst are inverted, think how the receiver sees them
6795          *
6796          * The input is broken into two sections, a non-compressed section
6797          * containing vm_pool, vlan_id, and flow_type.  The rest of the data
6798          * is XORed together and stored in the compressed dword.
6799          */
6800         input.formatted.vlan_id = vlan_id;
6801
6802         /*
6803          * since src port and flex bytes occupy the same word XOR them together
6804          * and write the value to source port portion of compressed dword
6805          */
6806         if (vlan_id)
6807                 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6808         else
6809                 common.port.src ^= th->dest ^ protocol;
6810         common.port.dst ^= th->source;
6811
6812         if (protocol == __constant_htons(ETH_P_IP)) {
6813                 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6814                 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6815         } else {
6816                 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6817                 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6818                              hdr.ipv6->saddr.s6_addr32[1] ^
6819                              hdr.ipv6->saddr.s6_addr32[2] ^
6820                              hdr.ipv6->saddr.s6_addr32[3] ^
6821                              hdr.ipv6->daddr.s6_addr32[0] ^
6822                              hdr.ipv6->daddr.s6_addr32[1] ^
6823                              hdr.ipv6->daddr.s6_addr32[2] ^
6824                              hdr.ipv6->daddr.s6_addr32[3];
6825         }
6826
6827         /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6828         ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6829                                               input, common, ring->queue_index);
6830 }
6831
6832 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
6833 {
6834         netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6835         /* Herbert's original patch had:
6836          *  smp_mb__after_netif_stop_queue();
6837          * but since that doesn't exist yet, just open code it. */
6838         smp_mb();
6839
6840         /* We need to check again in a case another CPU has just
6841          * made room available. */
6842         if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
6843                 return -EBUSY;
6844
6845         /* A reprieve! - use start_queue because it doesn't call schedule */
6846         netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6847         ++tx_ring->tx_stats.restart_queue;
6848         return 0;
6849 }
6850
6851 static int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
6852 {
6853         if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
6854                 return 0;
6855         return __ixgbe_maybe_stop_tx(tx_ring, size);
6856 }
6857
6858 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6859 {
6860         struct ixgbe_adapter *adapter = netdev_priv(dev);
6861         int txq = smp_processor_id();
6862 #ifdef IXGBE_FCOE
6863         __be16 protocol;
6864
6865         protocol = vlan_get_protocol(skb);
6866
6867         if (((protocol == htons(ETH_P_FCOE)) ||
6868             (protocol == htons(ETH_P_FIP))) &&
6869             (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6870                 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6871                 txq += adapter->ring_feature[RING_F_FCOE].mask;
6872                 return txq;
6873         }
6874 #endif
6875
6876         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6877                 while (unlikely(txq >= dev->real_num_tx_queues))
6878                         txq -= dev->real_num_tx_queues;
6879                 return txq;
6880         }
6881
6882         return skb_tx_hash(dev, skb);
6883 }
6884
6885 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6886                           struct ixgbe_adapter *adapter,
6887                           struct ixgbe_ring *tx_ring)
6888 {
6889         unsigned int first;
6890         unsigned int tx_flags = 0;
6891         u8 hdr_len = 0;
6892         int tso;
6893         int count = 0;
6894         unsigned int f;
6895         __be16 protocol;
6896
6897         protocol = vlan_get_protocol(skb);
6898
6899         if (vlan_tx_tag_present(skb)) {
6900                 tx_flags |= vlan_tx_tag_get(skb);
6901                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6902                         tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6903                         tx_flags |= tx_ring->dcb_tc << 13;
6904                 }
6905                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6906                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6907         } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6908                    skb->priority != TC_PRIO_CONTROL) {
6909                 tx_flags |= tx_ring->dcb_tc << 13;
6910                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6911                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6912         }
6913
6914 #ifdef IXGBE_FCOE
6915         /* for FCoE with DCB, we force the priority to what
6916          * was specified by the switch */
6917         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
6918             (protocol == htons(ETH_P_FCOE)))
6919                 tx_flags |= IXGBE_TX_FLAGS_FCOE;
6920 #endif
6921
6922         /* four things can cause us to need a context descriptor */
6923         if (skb_is_gso(skb) ||
6924             (skb->ip_summed == CHECKSUM_PARTIAL) ||
6925             (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
6926             (tx_flags & IXGBE_TX_FLAGS_FCOE))
6927                 count++;
6928
6929         count += TXD_USE_COUNT(skb_headlen(skb));
6930         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6931                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6932
6933         if (ixgbe_maybe_stop_tx(tx_ring, count)) {
6934                 tx_ring->tx_stats.tx_busy++;
6935                 return NETDEV_TX_BUSY;
6936         }
6937
6938         first = tx_ring->next_to_use;
6939         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6940 #ifdef IXGBE_FCOE
6941                 /* setup tx offload for FCoE */
6942                 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6943                 if (tso < 0) {
6944                         dev_kfree_skb_any(skb);
6945                         return NETDEV_TX_OK;
6946                 }
6947                 if (tso)
6948                         tx_flags |= IXGBE_TX_FLAGS_FSO;
6949 #endif /* IXGBE_FCOE */
6950         } else {
6951                 if (protocol == htons(ETH_P_IP))
6952                         tx_flags |= IXGBE_TX_FLAGS_IPV4;
6953                 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len,
6954                                 protocol);
6955                 if (tso < 0) {
6956                         dev_kfree_skb_any(skb);
6957                         return NETDEV_TX_OK;
6958                 }
6959
6960                 if (tso)
6961                         tx_flags |= IXGBE_TX_FLAGS_TSO;
6962                 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags,
6963                                        protocol) &&
6964                          (skb->ip_summed == CHECKSUM_PARTIAL))
6965                         tx_flags |= IXGBE_TX_FLAGS_CSUM;
6966         }
6967
6968         count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first, hdr_len);
6969         if (count) {
6970                 /* add the ATR filter if ATR is on */
6971                 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6972                         ixgbe_atr(tx_ring, skb, tx_flags, protocol);
6973                 ixgbe_tx_queue(tx_ring, tx_flags, count, skb->len, hdr_len);
6974                 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6975
6976         } else {
6977                 dev_kfree_skb_any(skb);
6978                 tx_ring->tx_buffer_info[first].time_stamp = 0;
6979                 tx_ring->next_to_use = first;
6980         }
6981
6982         return NETDEV_TX_OK;
6983 }
6984
6985 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6986 {
6987         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6988         struct ixgbe_ring *tx_ring;
6989
6990         tx_ring = adapter->tx_ring[skb->queue_mapping];
6991         return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
6992 }
6993
6994 /**
6995  * ixgbe_set_mac - Change the Ethernet Address of the NIC
6996  * @netdev: network interface device structure
6997  * @p: pointer to an address structure
6998  *
6999  * Returns 0 on success, negative on failure
7000  **/
7001 static int ixgbe_set_mac(struct net_device *netdev, void *p)
7002 {
7003         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7004         struct ixgbe_hw *hw = &adapter->hw;
7005         struct sockaddr *addr = p;
7006
7007         if (!is_valid_ether_addr(addr->sa_data))
7008                 return -EADDRNOTAVAIL;
7009
7010         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
7011         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
7012
7013         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
7014                             IXGBE_RAH_AV);
7015
7016         return 0;
7017 }
7018
7019 static int
7020 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
7021 {
7022         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7023         struct ixgbe_hw *hw = &adapter->hw;
7024         u16 value;
7025         int rc;
7026
7027         if (prtad != hw->phy.mdio.prtad)
7028                 return -EINVAL;
7029         rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
7030         if (!rc)
7031                 rc = value;
7032         return rc;
7033 }
7034
7035 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
7036                             u16 addr, u16 value)
7037 {
7038         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7039         struct ixgbe_hw *hw = &adapter->hw;
7040
7041         if (prtad != hw->phy.mdio.prtad)
7042                 return -EINVAL;
7043         return hw->phy.ops.write_reg(hw, addr, devad, value);
7044 }
7045
7046 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
7047 {
7048         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7049
7050         return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
7051 }
7052
7053 /**
7054  * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
7055  * netdev->dev_addrs
7056  * @netdev: network interface device structure
7057  *
7058  * Returns non-zero on failure
7059  **/
7060 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
7061 {
7062         int err = 0;
7063         struct ixgbe_adapter *adapter = netdev_priv(dev);
7064         struct ixgbe_mac_info *mac = &adapter->hw.mac;
7065
7066         if (is_valid_ether_addr(mac->san_addr)) {
7067                 rtnl_lock();
7068                 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7069                 rtnl_unlock();
7070         }
7071         return err;
7072 }
7073
7074 /**
7075  * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
7076  * netdev->dev_addrs
7077  * @netdev: network interface device structure
7078  *
7079  * Returns non-zero on failure
7080  **/
7081 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
7082 {
7083         int err = 0;
7084         struct ixgbe_adapter *adapter = netdev_priv(dev);
7085         struct ixgbe_mac_info *mac = &adapter->hw.mac;
7086
7087         if (is_valid_ether_addr(mac->san_addr)) {
7088                 rtnl_lock();
7089                 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7090                 rtnl_unlock();
7091         }
7092         return err;
7093 }
7094
7095 #ifdef CONFIG_NET_POLL_CONTROLLER
7096 /*
7097  * Polling 'interrupt' - used by things like netconsole to send skbs
7098  * without having to re-enable interrupts. It's not called while
7099  * the interrupt routine is executing.
7100  */
7101 static void ixgbe_netpoll(struct net_device *netdev)
7102 {
7103         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7104         int i;
7105
7106         /* if interface is down do nothing */
7107         if (test_bit(__IXGBE_DOWN, &adapter->state))
7108                 return;
7109
7110         adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
7111         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
7112                 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
7113                 for (i = 0; i < num_q_vectors; i++) {
7114                         struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
7115                         ixgbe_msix_clean_many(0, q_vector);
7116                 }
7117         } else {
7118                 ixgbe_intr(adapter->pdev->irq, netdev);
7119         }
7120         adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
7121 }
7122 #endif
7123
7124 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
7125                                                    struct rtnl_link_stats64 *stats)
7126 {
7127         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7128         int i;
7129
7130         rcu_read_lock();
7131         for (i = 0; i < adapter->num_rx_queues; i++) {
7132                 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
7133                 u64 bytes, packets;
7134                 unsigned int start;
7135
7136                 if (ring) {
7137                         do {
7138                                 start = u64_stats_fetch_begin_bh(&ring->syncp);
7139                                 packets = ring->stats.packets;
7140                                 bytes   = ring->stats.bytes;
7141                         } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7142                         stats->rx_packets += packets;
7143                         stats->rx_bytes   += bytes;
7144                 }
7145         }
7146
7147         for (i = 0; i < adapter->num_tx_queues; i++) {
7148                 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
7149                 u64 bytes, packets;
7150                 unsigned int start;
7151
7152                 if (ring) {
7153                         do {
7154                                 start = u64_stats_fetch_begin_bh(&ring->syncp);
7155                                 packets = ring->stats.packets;
7156                                 bytes   = ring->stats.bytes;
7157                         } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7158                         stats->tx_packets += packets;
7159                         stats->tx_bytes   += bytes;
7160                 }
7161         }
7162         rcu_read_unlock();
7163         /* following stats updated by ixgbe_watchdog_task() */
7164         stats->multicast        = netdev->stats.multicast;
7165         stats->rx_errors        = netdev->stats.rx_errors;
7166         stats->rx_length_errors = netdev->stats.rx_length_errors;
7167         stats->rx_crc_errors    = netdev->stats.rx_crc_errors;
7168         stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7169         return stats;
7170 }
7171
7172
7173 static const struct net_device_ops ixgbe_netdev_ops = {
7174         .ndo_open               = ixgbe_open,
7175         .ndo_stop               = ixgbe_close,
7176         .ndo_start_xmit         = ixgbe_xmit_frame,
7177         .ndo_select_queue       = ixgbe_select_queue,
7178         .ndo_set_rx_mode        = ixgbe_set_rx_mode,
7179         .ndo_set_multicast_list = ixgbe_set_rx_mode,
7180         .ndo_validate_addr      = eth_validate_addr,
7181         .ndo_set_mac_address    = ixgbe_set_mac,
7182         .ndo_change_mtu         = ixgbe_change_mtu,
7183         .ndo_tx_timeout         = ixgbe_tx_timeout,
7184         .ndo_vlan_rx_add_vid    = ixgbe_vlan_rx_add_vid,
7185         .ndo_vlan_rx_kill_vid   = ixgbe_vlan_rx_kill_vid,
7186         .ndo_do_ioctl           = ixgbe_ioctl,
7187         .ndo_set_vf_mac         = ixgbe_ndo_set_vf_mac,
7188         .ndo_set_vf_vlan        = ixgbe_ndo_set_vf_vlan,
7189         .ndo_set_vf_tx_rate     = ixgbe_ndo_set_vf_bw,
7190         .ndo_get_vf_config      = ixgbe_ndo_get_vf_config,
7191         .ndo_get_stats64        = ixgbe_get_stats64,
7192 #ifdef CONFIG_IXGBE_DCB
7193         .ndo_setup_tc           = ixgbe_setup_tc,
7194 #endif
7195 #ifdef CONFIG_NET_POLL_CONTROLLER
7196         .ndo_poll_controller    = ixgbe_netpoll,
7197 #endif
7198 #ifdef IXGBE_FCOE
7199         .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
7200         .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
7201         .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
7202         .ndo_fcoe_enable = ixgbe_fcoe_enable,
7203         .ndo_fcoe_disable = ixgbe_fcoe_disable,
7204         .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
7205 #endif /* IXGBE_FCOE */
7206 };
7207
7208 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
7209                            const struct ixgbe_info *ii)
7210 {
7211 #ifdef CONFIG_PCI_IOV
7212         struct ixgbe_hw *hw = &adapter->hw;
7213         int err;
7214         int num_vf_macvlans, i;
7215         struct vf_macvlans *mv_list;
7216
7217         if (hw->mac.type == ixgbe_mac_82598EB || !max_vfs)
7218                 return;
7219
7220         /* The 82599 supports up to 64 VFs per physical function
7221          * but this implementation limits allocation to 63 so that
7222          * basic networking resources are still available to the
7223          * physical function
7224          */
7225         adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
7226         adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
7227         err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
7228         if (err) {
7229                 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
7230                 goto err_novfs;
7231         }
7232
7233         num_vf_macvlans = hw->mac.num_rar_entries -
7234                 (IXGBE_MAX_PF_MACVLANS + 1 + adapter->num_vfs);
7235
7236         adapter->mv_list = mv_list = kcalloc(num_vf_macvlans,
7237                                              sizeof(struct vf_macvlans),
7238                                              GFP_KERNEL);
7239         if (mv_list) {
7240                 /* Initialize list of VF macvlans */
7241                 INIT_LIST_HEAD(&adapter->vf_mvs.l);
7242                 for (i = 0; i < num_vf_macvlans; i++) {
7243                         mv_list->vf = -1;
7244                         mv_list->free = true;
7245                         mv_list->rar_entry = hw->mac.num_rar_entries -
7246                                 (i + adapter->num_vfs + 1);
7247                         list_add(&mv_list->l, &adapter->vf_mvs.l);
7248                         mv_list++;
7249                 }
7250         }
7251
7252         /* If call to enable VFs succeeded then allocate memory
7253          * for per VF control structures.
7254          */
7255         adapter->vfinfo =
7256                 kcalloc(adapter->num_vfs,
7257                         sizeof(struct vf_data_storage), GFP_KERNEL);
7258         if (adapter->vfinfo) {
7259                 /* Now that we're sure SR-IOV is enabled
7260                  * and memory allocated set up the mailbox parameters
7261                  */
7262                 ixgbe_init_mbx_params_pf(hw);
7263                 memcpy(&hw->mbx.ops, ii->mbx_ops,
7264                        sizeof(hw->mbx.ops));
7265
7266                 /* Disable RSC when in SR-IOV mode */
7267                 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
7268                                      IXGBE_FLAG2_RSC_ENABLED);
7269                 return;
7270         }
7271
7272         /* Oh oh */
7273         e_err(probe, "Unable to allocate memory for VF Data Storage - "
7274               "SRIOV disabled\n");
7275         pci_disable_sriov(adapter->pdev);
7276
7277 err_novfs:
7278         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
7279         adapter->num_vfs = 0;
7280 #endif /* CONFIG_PCI_IOV */
7281 }
7282
7283 /**
7284  * ixgbe_probe - Device Initialization Routine
7285  * @pdev: PCI device information struct
7286  * @ent: entry in ixgbe_pci_tbl
7287  *
7288  * Returns 0 on success, negative on failure
7289  *
7290  * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7291  * The OS initialization, configuring of the adapter private structure,
7292  * and a hardware reset occur.
7293  **/
7294 static int __devinit ixgbe_probe(struct pci_dev *pdev,
7295                                  const struct pci_device_id *ent)
7296 {
7297         struct net_device *netdev;
7298         struct ixgbe_adapter *adapter = NULL;
7299         struct ixgbe_hw *hw;
7300         const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
7301         static int cards_found;
7302         int i, err, pci_using_dac;
7303         u8 part_str[IXGBE_PBANUM_LENGTH];
7304         unsigned int indices = num_possible_cpus();
7305 #ifdef IXGBE_FCOE
7306         u16 device_caps;
7307 #endif
7308         u32 eec;
7309
7310         /* Catch broken hardware that put the wrong VF device ID in
7311          * the PCIe SR-IOV capability.
7312          */
7313         if (pdev->is_virtfn) {
7314                 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7315                      pci_name(pdev), pdev->vendor, pdev->device);
7316                 return -EINVAL;
7317         }
7318
7319         err = pci_enable_device_mem(pdev);
7320         if (err)
7321                 return err;
7322
7323         if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7324             !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
7325                 pci_using_dac = 1;
7326         } else {
7327                 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
7328                 if (err) {
7329                         err = dma_set_coherent_mask(&pdev->dev,
7330                                                     DMA_BIT_MASK(32));
7331                         if (err) {
7332                                 dev_err(&pdev->dev,
7333                                         "No usable DMA configuration, aborting\n");
7334                                 goto err_dma;
7335                         }
7336                 }
7337                 pci_using_dac = 0;
7338         }
7339
7340         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
7341                                            IORESOURCE_MEM), ixgbe_driver_name);
7342         if (err) {
7343                 dev_err(&pdev->dev,
7344                         "pci_request_selected_regions failed 0x%x\n", err);
7345                 goto err_pci_reg;
7346         }
7347
7348         pci_enable_pcie_error_reporting(pdev);
7349
7350         pci_set_master(pdev);
7351         pci_save_state(pdev);
7352
7353         if (ii->mac == ixgbe_mac_82598EB)
7354                 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7355         else
7356                 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7357
7358 #if defined(CONFIG_DCB)
7359         indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
7360 #elif defined(IXGBE_FCOE)
7361         indices += min_t(unsigned int, num_possible_cpus(),
7362                          IXGBE_MAX_FCOE_INDICES);
7363 #endif
7364         netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
7365         if (!netdev) {
7366                 err = -ENOMEM;
7367                 goto err_alloc_etherdev;
7368         }
7369
7370         SET_NETDEV_DEV(netdev, &pdev->dev);
7371
7372         adapter = netdev_priv(netdev);
7373         pci_set_drvdata(pdev, adapter);
7374
7375         adapter->netdev = netdev;
7376         adapter->pdev = pdev;
7377         hw = &adapter->hw;
7378         hw->back = adapter;
7379         adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
7380
7381         hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
7382                               pci_resource_len(pdev, 0));
7383         if (!hw->hw_addr) {
7384                 err = -EIO;
7385                 goto err_ioremap;
7386         }
7387
7388         for (i = 1; i <= 5; i++) {
7389                 if (pci_resource_len(pdev, i) == 0)
7390                         continue;
7391         }
7392
7393         netdev->netdev_ops = &ixgbe_netdev_ops;
7394         ixgbe_set_ethtool_ops(netdev);
7395         netdev->watchdog_timeo = 5 * HZ;
7396         strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
7397
7398         adapter->bd_number = cards_found;
7399
7400         /* Setup hw api */
7401         memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
7402         hw->mac.type  = ii->mac;
7403
7404         /* EEPROM */
7405         memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7406         eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7407         /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7408         if (!(eec & (1 << 8)))
7409                 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7410
7411         /* PHY */
7412         memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
7413         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
7414         /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7415         hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7416         hw->phy.mdio.mmds = 0;
7417         hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7418         hw->phy.mdio.dev = netdev;
7419         hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7420         hw->phy.mdio.mdio_write = ixgbe_mdio_write;
7421
7422         ii->get_invariants(hw);
7423
7424         /* setup the private structure */
7425         err = ixgbe_sw_init(adapter);
7426         if (err)
7427                 goto err_sw_init;
7428
7429         /* Make it possible the adapter to be woken up via WOL */
7430         switch (adapter->hw.mac.type) {
7431         case ixgbe_mac_82599EB:
7432         case ixgbe_mac_X540:
7433                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7434                 break;
7435         default:
7436                 break;
7437         }
7438
7439         /*
7440          * If there is a fan on this device and it has failed log the
7441          * failure.
7442          */
7443         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7444                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7445                 if (esdp & IXGBE_ESDP_SDP1)
7446                         e_crit(probe, "Fan has stopped, replace the adapter\n");
7447         }
7448
7449         /* reset_hw fills in the perm_addr as well */
7450         hw->phy.reset_if_overtemp = true;
7451         err = hw->mac.ops.reset_hw(hw);
7452         hw->phy.reset_if_overtemp = false;
7453         if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7454             hw->mac.type == ixgbe_mac_82598EB) {
7455                 err = 0;
7456         } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7457                 e_dev_err("failed to load because an unsupported SFP+ "
7458                           "module type was detected.\n");
7459                 e_dev_err("Reload the driver after installing a supported "
7460                           "module.\n");
7461                 goto err_sw_init;
7462         } else if (err) {
7463                 e_dev_err("HW Init failed: %d\n", err);
7464                 goto err_sw_init;
7465         }
7466
7467         ixgbe_probe_vf(adapter, ii);
7468
7469         netdev->features = NETIF_F_SG |
7470                            NETIF_F_IP_CSUM |
7471                            NETIF_F_HW_VLAN_TX |
7472                            NETIF_F_HW_VLAN_RX |
7473                            NETIF_F_HW_VLAN_FILTER;
7474
7475         netdev->features |= NETIF_F_IPV6_CSUM;
7476         netdev->features |= NETIF_F_TSO;
7477         netdev->features |= NETIF_F_TSO6;
7478         netdev->features |= NETIF_F_GRO;
7479         netdev->features |= NETIF_F_RXHASH;
7480
7481         switch (adapter->hw.mac.type) {
7482         case ixgbe_mac_82599EB:
7483         case ixgbe_mac_X540:
7484                 netdev->features |= NETIF_F_SCTP_CSUM;
7485                 break;
7486         default:
7487                 break;
7488         }
7489
7490         netdev->vlan_features |= NETIF_F_TSO;
7491         netdev->vlan_features |= NETIF_F_TSO6;
7492         netdev->vlan_features |= NETIF_F_IP_CSUM;
7493         netdev->vlan_features |= NETIF_F_IPV6_CSUM;
7494         netdev->vlan_features |= NETIF_F_SG;
7495
7496         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7497                 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7498                                     IXGBE_FLAG_DCB_ENABLED);
7499
7500 #ifdef CONFIG_IXGBE_DCB
7501         netdev->dcbnl_ops = &dcbnl_ops;
7502 #endif
7503
7504 #ifdef IXGBE_FCOE
7505         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7506                 if (hw->mac.ops.get_device_caps) {
7507                         hw->mac.ops.get_device_caps(hw, &device_caps);
7508                         if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7509                                 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
7510                 }
7511         }
7512         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7513                 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7514                 netdev->vlan_features |= NETIF_F_FSO;
7515                 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7516         }
7517 #endif /* IXGBE_FCOE */
7518         if (pci_using_dac) {
7519                 netdev->features |= NETIF_F_HIGHDMA;
7520                 netdev->vlan_features |= NETIF_F_HIGHDMA;
7521         }
7522
7523         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7524                 netdev->features |= NETIF_F_LRO;
7525
7526         /* make sure the EEPROM is good */
7527         if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
7528                 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7529                 err = -EIO;
7530                 goto err_eeprom;
7531         }
7532
7533         memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7534         memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7535
7536         if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
7537                 e_dev_err("invalid MAC address\n");
7538                 err = -EIO;
7539                 goto err_eeprom;
7540         }
7541
7542         /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7543         if (hw->mac.ops.disable_tx_laser &&
7544             ((hw->phy.multispeed_fiber) ||
7545              ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
7546               (hw->mac.type == ixgbe_mac_82599EB))))
7547                 hw->mac.ops.disable_tx_laser(hw);
7548
7549         setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7550                     (unsigned long) adapter);
7551
7552         INIT_WORK(&adapter->service_task, ixgbe_service_task);
7553         clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
7554
7555         err = ixgbe_init_interrupt_scheme(adapter);
7556         if (err)
7557                 goto err_sw_init;
7558
7559         if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
7560                 netdev->features &= ~NETIF_F_RXHASH;
7561
7562         switch (pdev->device) {
7563         case IXGBE_DEV_ID_82599_SFP:
7564                 /* Only this subdevice supports WOL */
7565                 if (pdev->subsystem_device == IXGBE_SUBDEV_ID_82599_SFP)
7566                         adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7567                                         IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7568                 break;
7569         case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7570                 /* All except this subdevice support WOL */
7571                 if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7572                         adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7573                                         IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7574                 break;
7575         case IXGBE_DEV_ID_82599_KX4:
7576                 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7577                                 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7578                 break;
7579         default:
7580                 adapter->wol = 0;
7581                 break;
7582         }
7583         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7584
7585         /* pick up the PCI bus settings for reporting later */
7586         hw->mac.ops.get_bus_info(hw);
7587
7588         /* print bus type/speed/width info */
7589         e_dev_info("(PCI Express:%s:%s) %pM\n",
7590                    (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7591                     hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
7592                     "Unknown"),
7593                    (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7594                     hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7595                     hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7596                     "Unknown"),
7597                    netdev->dev_addr);
7598
7599         err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7600         if (err)
7601                 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
7602         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
7603                 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
7604                            hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7605                            part_str);
7606         else
7607                 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7608                            hw->mac.type, hw->phy.type, part_str);
7609
7610         if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
7611                 e_dev_warn("PCI-Express bandwidth available for this card is "
7612                            "not sufficient for optimal performance.\n");
7613                 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7614                            "is required.\n");
7615         }
7616
7617         /* save off EEPROM version number */
7618         hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
7619
7620         /* reset the hardware with the new settings */
7621         err = hw->mac.ops.start_hw(hw);
7622
7623         if (err == IXGBE_ERR_EEPROM_VERSION) {
7624                 /* We are running on a pre-production device, log a warning */
7625                 e_dev_warn("This device is a pre-production adapter/LOM. "
7626                            "Please be aware there may be issues associated "
7627                            "with your hardware.  If you are experiencing "
7628                            "problems please contact your Intel or hardware "
7629                            "representative who provided you with this "
7630                            "hardware.\n");
7631         }
7632         strcpy(netdev->name, "eth%d");
7633         err = register_netdev(netdev);
7634         if (err)
7635                 goto err_register;
7636
7637         /* carrier off reporting is important to ethtool even BEFORE open */
7638         netif_carrier_off(netdev);
7639
7640         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7641             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7642                 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
7643
7644         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
7645                 INIT_WORK(&adapter->check_overtemp_task,
7646                           ixgbe_check_overtemp_task);
7647 #ifdef CONFIG_IXGBE_DCA
7648         if (dca_add_requester(&pdev->dev) == 0) {
7649                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7650                 ixgbe_setup_dca(adapter);
7651         }
7652 #endif
7653         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7654                 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7655                 for (i = 0; i < adapter->num_vfs; i++)
7656                         ixgbe_vf_configuration(pdev, (i | 0x10000000));
7657         }
7658
7659         /* add san mac addr to netdev */
7660         ixgbe_add_sanmac_netdev(netdev);
7661
7662         e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
7663         cards_found++;
7664         return 0;
7665
7666 err_register:
7667         ixgbe_release_hw_control(adapter);
7668         ixgbe_clear_interrupt_scheme(adapter);
7669 err_sw_init:
7670 err_eeprom:
7671         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7672                 ixgbe_disable_sriov(adapter);
7673         adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
7674         iounmap(hw->hw_addr);
7675 err_ioremap:
7676         free_netdev(netdev);
7677 err_alloc_etherdev:
7678         pci_release_selected_regions(pdev,
7679                                      pci_select_bars(pdev, IORESOURCE_MEM));
7680 err_pci_reg:
7681 err_dma:
7682         pci_disable_device(pdev);
7683         return err;
7684 }
7685
7686 /**
7687  * ixgbe_remove - Device Removal Routine
7688  * @pdev: PCI device information struct
7689  *
7690  * ixgbe_remove is called by the PCI subsystem to alert the driver
7691  * that it should release a PCI device.  The could be caused by a
7692  * Hot-Plug event, or because the driver is going to be removed from
7693  * memory.
7694  **/
7695 static void __devexit ixgbe_remove(struct pci_dev *pdev)
7696 {
7697         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7698         struct net_device *netdev = adapter->netdev;
7699
7700         set_bit(__IXGBE_DOWN, &adapter->state);
7701         cancel_work_sync(&adapter->service_task);
7702
7703         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7704             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7705                 cancel_work_sync(&adapter->fdir_reinit_task);
7706         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
7707                 cancel_work_sync(&adapter->check_overtemp_task);
7708
7709 #ifdef CONFIG_IXGBE_DCA
7710         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7711                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7712                 dca_remove_requester(&pdev->dev);
7713                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7714         }
7715
7716 #endif
7717 #ifdef IXGBE_FCOE
7718         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7719                 ixgbe_cleanup_fcoe(adapter);
7720
7721 #endif /* IXGBE_FCOE */
7722
7723         /* remove the added san mac */
7724         ixgbe_del_sanmac_netdev(netdev);
7725
7726         if (netdev->reg_state == NETREG_REGISTERED)
7727                 unregister_netdev(netdev);
7728
7729         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7730                 ixgbe_disable_sriov(adapter);
7731
7732         ixgbe_clear_interrupt_scheme(adapter);
7733
7734         ixgbe_release_hw_control(adapter);
7735
7736         iounmap(adapter->hw.hw_addr);
7737         pci_release_selected_regions(pdev, pci_select_bars(pdev,
7738                                      IORESOURCE_MEM));
7739
7740         e_dev_info("complete\n");
7741
7742         free_netdev(netdev);
7743
7744         pci_disable_pcie_error_reporting(pdev);
7745
7746         pci_disable_device(pdev);
7747 }
7748
7749 /**
7750  * ixgbe_io_error_detected - called when PCI error is detected
7751  * @pdev: Pointer to PCI device
7752  * @state: The current pci connection state
7753  *
7754  * This function is called after a PCI bus error affecting
7755  * this device has been detected.
7756  */
7757 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7758                                                 pci_channel_state_t state)
7759 {
7760         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7761         struct net_device *netdev = adapter->netdev;
7762
7763         netif_device_detach(netdev);
7764
7765         if (state == pci_channel_io_perm_failure)
7766                 return PCI_ERS_RESULT_DISCONNECT;
7767
7768         if (netif_running(netdev))
7769                 ixgbe_down(adapter);
7770         pci_disable_device(pdev);
7771
7772         /* Request a slot reset. */
7773         return PCI_ERS_RESULT_NEED_RESET;
7774 }
7775
7776 /**
7777  * ixgbe_io_slot_reset - called after the pci bus has been reset.
7778  * @pdev: Pointer to PCI device
7779  *
7780  * Restart the card from scratch, as if from a cold-boot.
7781  */
7782 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7783 {
7784         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7785         pci_ers_result_t result;
7786         int err;
7787
7788         if (pci_enable_device_mem(pdev)) {
7789                 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7790                 result = PCI_ERS_RESULT_DISCONNECT;
7791         } else {
7792                 pci_set_master(pdev);
7793                 pci_restore_state(pdev);
7794                 pci_save_state(pdev);
7795
7796                 pci_wake_from_d3(pdev, false);
7797
7798                 ixgbe_reset(adapter);
7799                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7800                 result = PCI_ERS_RESULT_RECOVERED;
7801         }
7802
7803         err = pci_cleanup_aer_uncorrect_error_status(pdev);
7804         if (err) {
7805                 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7806                           "failed 0x%0x\n", err);
7807                 /* non-fatal, continue */
7808         }
7809
7810         return result;
7811 }
7812
7813 /**
7814  * ixgbe_io_resume - called when traffic can start flowing again.
7815  * @pdev: Pointer to PCI device
7816  *
7817  * This callback is called when the error recovery driver tells us that
7818  * its OK to resume normal operation.
7819  */
7820 static void ixgbe_io_resume(struct pci_dev *pdev)
7821 {
7822         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7823         struct net_device *netdev = adapter->netdev;
7824
7825         if (netif_running(netdev)) {
7826                 if (ixgbe_up(adapter)) {
7827                         e_info(probe, "ixgbe_up failed after reset\n");
7828                         return;
7829                 }
7830         }
7831
7832         netif_device_attach(netdev);
7833 }
7834
7835 static struct pci_error_handlers ixgbe_err_handler = {
7836         .error_detected = ixgbe_io_error_detected,
7837         .slot_reset = ixgbe_io_slot_reset,
7838         .resume = ixgbe_io_resume,
7839 };
7840
7841 static struct pci_driver ixgbe_driver = {
7842         .name     = ixgbe_driver_name,
7843         .id_table = ixgbe_pci_tbl,
7844         .probe    = ixgbe_probe,
7845         .remove   = __devexit_p(ixgbe_remove),
7846 #ifdef CONFIG_PM
7847         .suspend  = ixgbe_suspend,
7848         .resume   = ixgbe_resume,
7849 #endif
7850         .shutdown = ixgbe_shutdown,
7851         .err_handler = &ixgbe_err_handler
7852 };
7853
7854 /**
7855  * ixgbe_init_module - Driver Registration Routine
7856  *
7857  * ixgbe_init_module is the first routine called when the driver is
7858  * loaded. All it does is register with the PCI subsystem.
7859  **/
7860 static int __init ixgbe_init_module(void)
7861 {
7862         int ret;
7863         pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
7864         pr_info("%s\n", ixgbe_copyright);
7865
7866 #ifdef CONFIG_IXGBE_DCA
7867         dca_register_notify(&dca_notifier);
7868 #endif
7869
7870         ret = pci_register_driver(&ixgbe_driver);
7871         return ret;
7872 }
7873
7874 module_init(ixgbe_init_module);
7875
7876 /**
7877  * ixgbe_exit_module - Driver Exit Cleanup Routine
7878  *
7879  * ixgbe_exit_module is called just before the driver is removed
7880  * from memory.
7881  **/
7882 static void __exit ixgbe_exit_module(void)
7883 {
7884 #ifdef CONFIG_IXGBE_DCA
7885         dca_unregister_notify(&dca_notifier);
7886 #endif
7887         pci_unregister_driver(&ixgbe_driver);
7888         rcu_barrier(); /* Wait for completion of call_rcu()'s */
7889 }
7890
7891 #ifdef CONFIG_IXGBE_DCA
7892 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7893                             void *p)
7894 {
7895         int ret_val;
7896
7897         ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7898                                          __ixgbe_notify_dca);
7899
7900         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7901 }
7902
7903 #endif /* CONFIG_IXGBE_DCA */
7904
7905 module_exit(ixgbe_exit_module);
7906
7907 /* ixgbe_main.c */