drivers/net/ixgbe/ixgbe_main.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/types.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/string.h>
  34 #include <linux/in.h>
  35 #include <linux/ip.h>
  36 #include <linux/tcp.h>
  37 #include <linux/pkt_sched.h>
  38 #include <linux/ipv6.h>
  39 #include <net/checksum.h>
  40 #include <net/ip6_checksum.h>
  41 #include <linux/ethtool.h>
  42 #include <linux/if_vlan.h>
  43 #include <scsi/fc/fc_fcoe.h>
  44
  45 #include "ixgbe.h"
  46 #include "ixgbe_common.h"
  47 #include "ixgbe_dcb_82599.h"
  48
  49 char ixgbe_driver_name[] = "ixgbe";
  50 static const char ixgbe_driver_string[] =
  51                               "Intel(R) 10 Gigabit PCI Express Network Driver";
  52
  53 #define DRV_VERSION "2.0.44-k2"
  54 const char ixgbe_driver_version[] = DRV_VERSION;
  55 static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation.";
  56
  57 static const struct ixgbe_info *ixgbe_info_tbl[] = {
  58         [board_82598] = &ixgbe_82598_info,
  59         [board_82599] = &ixgbe_82599_info,
  60 };
  61
  62 /* ixgbe_pci_tbl - PCI Device ID Table
  63  *
  64  * Wildcard entries (PCI_ANY_ID) should come last
  65  * Last entry must be all 0s
  66  *
  67  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  68  *   Class, Class Mask, private data (not used) }
  69  */
  70 static struct pci_device_id ixgbe_pci_tbl[] = {
  71         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
  72          board_82598 },
  73         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
  74          board_82598 },
  75         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
  76          board_82598 },
  77         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
  78          board_82598 },
  79         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
  80          board_82598 },
  81         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
  82          board_82598 },
  83         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
  84          board_82598 },
  85         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
  86          board_82598 },
  87         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
  88          board_82598 },
  89         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
  90          board_82598 },
  91         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
  92          board_82598 },
  93         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
  94          board_82598 },
  95         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
  96          board_82599 },
  97         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
  98          board_82599 },
  99         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
 100          board_82599 },
 101         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
 102          board_82599 },
 103         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
 104          board_82599 },
 105         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
 106          board_82599 },
 107         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
 108          board_82599 },
 109         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
 110          board_82599 },
 111
 112         /* required last entry */
 113         {0, }
 114 };
 115 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
 116
 117 #ifdef CONFIG_IXGBE_DCA
 118 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
 119                             void *p);
 120 static struct notifier_block dca_notifier = {
 121         .notifier_call = ixgbe_notify_dca,
 122         .next          = NULL,
 123         .priority      = 0
 124 };
 125 #endif
 126
 127 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
 128 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
 129 MODULE_LICENSE("GPL");
 130 MODULE_VERSION(DRV_VERSION);
 131
 132 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
 133
 134 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
 135 {
 136         u32 ctrl_ext;
 137
 138         /* Let firmware take over control of h/w */
 139         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 140         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 141                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
 142 }
 143
 144 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
 145 {
 146         u32 ctrl_ext;
 147
 148         /* Let firmware know the driver has taken over */
 149         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 150         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 151                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
 152 }
 153
 154 /*
 155  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
 156  * @adapter: pointer to adapter struct
 157  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
 158  * @queue: queue to map the corresponding interrupt to
 159  * @msix_vector: the vector to map to the corresponding queue
 160  *
 161  */
 162 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
 163                            u8 queue, u8 msix_vector)
 164 {
 165         u32 ivar, index;
 166         struct ixgbe_hw *hw = &adapter->hw;
 167         switch (hw->mac.type) {
 168         case ixgbe_mac_82598EB:
 169                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 170                 if (direction == -1)
 171                         direction = 0;
 172                 index = (((direction * 64) + queue) >> 2) & 0x1F;
 173                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
 174                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
 175                 ivar |= (msix_vector << (8 * (queue & 0x3)));
 176                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
 177                 break;
 178         case ixgbe_mac_82599EB:
 179                 if (direction == -1) {
 180                         /* other causes */
 181                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 182                         index = ((queue & 1) * 8);
 183                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
 184                         ivar &= ~(0xFF << index);
 185                         ivar |= (msix_vector << index);
 186                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
 187                         break;
 188                 } else {
 189                         /* tx or rx causes */
 190                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 191                         index = ((16 * (queue & 1)) + (8 * direction));
 192                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
 193                         ivar &= ~(0xFF << index);
 194                         ivar |= (msix_vector << index);
 195                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
 196                         break;
 197                 }
 198         default:
 199                 break;
 200         }
 201 }
 202
 203 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
 204                                           u64 qmask)
 205 {
 206         u32 mask;
 207
 208         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 209                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
 210                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
 211         } else {
 212                 mask = (qmask & 0xFFFFFFFF);
 213                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
 214                 mask = (qmask >> 32);
 215                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
 216         }
 217 }
 218
 219 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
 220                                              struct ixgbe_tx_buffer
 221                                              *tx_buffer_info)
 222 {
 223         tx_buffer_info->dma = 0;
 224         if (tx_buffer_info->skb) {
 225                 skb_dma_unmap(&adapter->pdev->dev, tx_buffer_info->skb,
 226                               DMA_TO_DEVICE);
 227                 dev_kfree_skb_any(tx_buffer_info->skb);
 228                 tx_buffer_info->skb = NULL;
 229         }
 230         tx_buffer_info->time_stamp = 0;
 231         /* tx_buffer_info must be completely set up in the transmit path */
 232 }
 233
 234 /**
 235  * ixgbe_tx_is_paused - check if the tx ring is paused
 236  * @adapter: the ixgbe adapter
 237  * @tx_ring: the corresponding tx_ring
 238  *
 239  * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
 240  * corresponding TC of this tx_ring when checking TFCS.
 241  *
 242  * Returns : true if paused
 243  */
 244 static inline bool ixgbe_tx_is_paused(struct ixgbe_adapter *adapter,
 245                                       struct ixgbe_ring *tx_ring)
 246 {
 247         u32 txoff = IXGBE_TFCS_TXOFF;
 248
 249 #ifdef CONFIG_IXGBE_DCB
 250         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
 251                 int tc;
 252                 int reg_idx = tx_ring->reg_idx;
 253                 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
 254
 255                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 256                         tc = reg_idx >> 2;
 257                         txoff = IXGBE_TFCS_TXOFF0;
 258                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 259                         tc = 0;
 260                         txoff = IXGBE_TFCS_TXOFF;
 261                         if (dcb_i == 8) {
 262                                 /* TC0, TC1 */
 263                                 tc = reg_idx >> 5;
 264                                 if (tc == 2) /* TC2, TC3 */
 265                                         tc += (reg_idx - 64) >> 4;
 266                                 else if (tc == 3) /* TC4, TC5, TC6, TC7 */
 267                                         tc += 1 + ((reg_idx - 96) >> 3);
 268                         } else if (dcb_i == 4) {
 269                                 /* TC0, TC1 */
 270                                 tc = reg_idx >> 6;
 271                                 if (tc == 1) {
 272                                         tc += (reg_idx - 64) >> 5;
 273                                         if (tc == 2) /* TC2, TC3 */
 274                                                 tc += (reg_idx - 96) >> 4;
 275                                 }
 276                         }
 277                 }
 278                 txoff <<= tc;
 279         }
 280 #endif
 281         return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff;
 282 }
 283
 284 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
 285                                        struct ixgbe_ring *tx_ring,
 286                                        unsigned int eop)
 287 {
 288         struct ixgbe_hw *hw = &adapter->hw;
 289
 290         /* Detect a transmit hang in hardware, this serializes the
 291          * check with the clearing of time_stamp and movement of eop */
 292         adapter->detect_tx_hung = false;
 293         if (tx_ring->tx_buffer_info[eop].time_stamp &&
 294             time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
 295             !ixgbe_tx_is_paused(adapter, tx_ring)) {
 296                 /* detected Tx unit hang */
 297                 union ixgbe_adv_tx_desc *tx_desc;
 298                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 299                 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
 300                         "  Tx Queue             <%d>\n"
 301                         "  TDH, TDT             <%x>, <%x>\n"
 302                         "  next_to_use          <%x>\n"
 303                         "  next_to_clean        <%x>\n"
 304                         "tx_buffer_info[next_to_clean]\n"
 305                         "  time_stamp           <%lx>\n"
 306                         "  jiffies              <%lx>\n",
 307                         tx_ring->queue_index,
 308                         IXGBE_READ_REG(hw, tx_ring->head),
 309                         IXGBE_READ_REG(hw, tx_ring->tail),
 310                         tx_ring->next_to_use, eop,
 311                         tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
 312                 return true;
 313         }
 314
 315         return false;
 316 }
 317
 318 #define IXGBE_MAX_TXD_PWR       14
 319 #define IXGBE_MAX_DATA_PER_TXD  (1 << IXGBE_MAX_TXD_PWR)
 320
 321 /* Tx Descriptors needed, worst case */
 322 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
 323                          (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
 324 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
 325         MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
 326
 327 static void ixgbe_tx_timeout(struct net_device *netdev);
 328
 329 /**
 330  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
 331  * @q_vector: structure containing interrupt and ring information
 332  * @tx_ring: tx ring to clean
 333  **/
 334 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
 335                                struct ixgbe_ring *tx_ring)
 336 {
 337         struct ixgbe_adapter *adapter = q_vector->adapter;
 338         struct net_device *netdev = adapter->netdev;
 339         union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
 340         struct ixgbe_tx_buffer *tx_buffer_info;
 341         unsigned int i, eop, count = 0;
 342         unsigned int total_bytes = 0, total_packets = 0;
 343
 344         i = tx_ring->next_to_clean;
 345         eop = tx_ring->tx_buffer_info[i].next_to_watch;
 346         eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 347
 348         while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
 349                (count < tx_ring->work_limit)) {
 350                 bool cleaned = false;
 351                 for ( ; !cleaned; count++) {
 352                         struct sk_buff *skb;
 353                         tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
 354                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 355                         cleaned = (i == eop);
 356                         skb = tx_buffer_info->skb;
 357
 358                         if (cleaned && skb) {
 359                                 unsigned int segs, bytecount;
 360                                 unsigned int hlen = skb_headlen(skb);
 361
 362                                 /* gso_segs is currently only valid for tcp */
 363                                 segs = skb_shinfo(skb)->gso_segs ?: 1;
 364 #ifdef IXGBE_FCOE
 365                                 /* adjust for FCoE Sequence Offload */
 366                                 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
 367                                     && (skb->protocol == htons(ETH_P_FCOE)) &&
 368                                     skb_is_gso(skb)) {
 369                                         hlen = skb_transport_offset(skb) +
 370                                                 sizeof(struct fc_frame_header) +
 371                                                 sizeof(struct fcoe_crc_eof);
 372                                         segs = DIV_ROUND_UP(skb->len - hlen,
 373                                                 skb_shinfo(skb)->gso_size);
 374                                 }
 375 #endif /* IXGBE_FCOE */
 376                                 /* multiply data chunks by size of headers */
 377                                 bytecount = ((segs - 1) * hlen) + skb->len;
 378                                 total_packets += segs;
 379                                 total_bytes += bytecount;
 380                         }
 381
 382                         ixgbe_unmap_and_free_tx_resource(adapter,
 383                                                          tx_buffer_info);
 384
 385                         tx_desc->wb.status = 0;
 386
 387                         i++;
 388                         if (i == tx_ring->count)
 389                                 i = 0;
 390                 }
 391
 392                 eop = tx_ring->tx_buffer_info[i].next_to_watch;
 393                 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 394         }
 395
 396         tx_ring->next_to_clean = i;
 397
 398 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 399         if (unlikely(count && netif_carrier_ok(netdev) &&
 400                      (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 401                 /* Make sure that anybody stopping the queue after this
 402                  * sees the new next_to_clean.
 403                  */
 404                 smp_mb();
 405                 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
 406                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
 407                         netif_wake_subqueue(netdev, tx_ring->queue_index);
 408                         ++adapter->restart_queue;
 409                 }
 410         }
 411
 412         if (adapter->detect_tx_hung) {
 413                 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
 414                         /* schedule immediate reset if we believe we hung */
 415                         DPRINTK(PROBE, INFO,
 416                                 "tx hang %d detected, resetting adapter\n",
 417                                 adapter->tx_timeout_count + 1);
 418                         ixgbe_tx_timeout(adapter->netdev);
 419                 }
 420         }
 421
 422         /* re-arm the interrupt */
 423         if (count >= tx_ring->work_limit)
 424                 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
 425
 426         tx_ring->total_bytes += total_bytes;
 427         tx_ring->total_packets += total_packets;
 428         tx_ring->stats.packets += total_packets;
 429         tx_ring->stats.bytes += total_bytes;
 430         adapter->net_stats.tx_bytes += total_bytes;
 431         adapter->net_stats.tx_packets += total_packets;
 432         return (count < tx_ring->work_limit);
 433 }
 434
 435 #ifdef CONFIG_IXGBE_DCA
 436 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
 437                                 struct ixgbe_ring *rx_ring)
 438 {
 439         u32 rxctrl;
 440         int cpu = get_cpu();
 441         int q = rx_ring - adapter->rx_ring;
 442
 443         if (rx_ring->cpu != cpu) {
 444                 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
 445                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 446                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
 447                         rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 448                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 449                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
 450                         rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 451                                    IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
 452                 }
 453                 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
 454                 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
 455                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
 456                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
 457                             IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
 458                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
 459                 rx_ring->cpu = cpu;
 460         }
 461         put_cpu();
 462 }
 463
 464 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
 465                                 struct ixgbe_ring *tx_ring)
 466 {
 467         u32 txctrl;
 468         int cpu = get_cpu();
 469         int q = tx_ring - adapter->tx_ring;
 470         struct ixgbe_hw *hw = &adapter->hw;
 471
 472         if (tx_ring->cpu != cpu) {
 473                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 474                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(q));
 475                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
 476                         txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 477                         txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 478                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(q), txctrl);
 479                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 480                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(q));
 481                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
 482                         txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 483                                   IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
 484                         txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 485                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(q), txctrl);
 486                 }
 487                 tx_ring->cpu = cpu;
 488         }
 489         put_cpu();
 490 }
 491
 492 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
 493 {
 494         int i;
 495
 496         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
 497                 return;
 498
 499         /* always use CB2 mode, difference is masked in the CB driver */
 500         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
 501
 502         for (i = 0; i < adapter->num_tx_queues; i++) {
 503                 adapter->tx_ring[i].cpu = -1;
 504                 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
 505         }
 506         for (i = 0; i < adapter->num_rx_queues; i++) {
 507                 adapter->rx_ring[i].cpu = -1;
 508                 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
 509         }
 510 }
 511
 512 static int __ixgbe_notify_dca(struct device *dev, void *data)
 513 {
 514         struct net_device *netdev = dev_get_drvdata(dev);
 515         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 516         unsigned long event = *(unsigned long *)data;
 517
 518         switch (event) {
 519         case DCA_PROVIDER_ADD:
 520                 /* if we're already enabled, don't do it again */
 521                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
 522                         break;
 523                 if (dca_add_requester(dev) == 0) {
 524                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
 525                         ixgbe_setup_dca(adapter);
 526                         break;
 527                 }
 528                 /* Fall Through since DCA is disabled. */
 529         case DCA_PROVIDER_REMOVE:
 530                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
 531                         dca_remove_requester(dev);
 532                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
 533                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
 534                 }
 535                 break;
 536         }
 537
 538         return 0;
 539 }
 540
 541 #endif /* CONFIG_IXGBE_DCA */
 542 /**
 543  * ixgbe_receive_skb - Send a completed packet up the stack
 544  * @adapter: board private structure
 545  * @skb: packet to send up
 546  * @status: hardware indication of status of receive
 547  * @rx_ring: rx descriptor ring (for a specific queue) to setup
 548  * @rx_desc: rx descriptor
 549  **/
 550 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
 551                               struct sk_buff *skb, u8 status,
 552                               struct ixgbe_ring *ring,
 553                               union ixgbe_adv_rx_desc *rx_desc)
 554 {
 555         struct ixgbe_adapter *adapter = q_vector->adapter;
 556         struct napi_struct *napi = &q_vector->napi;
 557         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
 558         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
 559
 560         skb_record_rx_queue(skb, ring->queue_index);
 561         if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
 562                 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
 563                         vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
 564                 else
 565                         napi_gro_receive(napi, skb);
 566         } else {
 567                 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
 568                         vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
 569                 else
 570                         netif_rx(skb);
 571         }
 572 }
 573
 574 /**
 575  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
 576  * @adapter: address of board private structure
 577  * @status_err: hardware indication of status of receive
 578  * @skb: skb currently being received and modified
 579  **/
 580 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
 581                                      union ixgbe_adv_rx_desc *rx_desc,
 582                                      struct sk_buff *skb)
 583 {
 584         u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
 585
 586         skb->ip_summed = CHECKSUM_NONE;
 587
 588         /* Rx csum disabled */
 589         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
 590                 return;
 591
 592         /* if IP and error */
 593         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
 594             (status_err & IXGBE_RXDADV_ERR_IPE)) {
 595                 adapter->hw_csum_rx_error++;
 596                 return;
 597         }
 598
 599         if (!(status_err & IXGBE_RXD_STAT_L4CS))
 600                 return;
 601
 602         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
 603                 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
 604
 605                 /*
 606                  * 82599 errata, UDP frames with a 0 checksum can be marked as
 607                  * checksum errors.
 608                  */
 609                 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
 610                     (adapter->hw.mac.type == ixgbe_mac_82599EB))
 611                         return;
 612
 613                 adapter->hw_csum_rx_error++;
 614                 return;
 615         }
 616
 617         /* It must be a TCP or UDP packet with a valid checksum */
 618         skb->ip_summed = CHECKSUM_UNNECESSARY;
 619         adapter->hw_csum_rx_good++;
 620 }
 621
 622 static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
 623                                          struct ixgbe_ring *rx_ring, u32 val)
 624 {
 625         /*
 626          * Force memory writes to complete before letting h/w
 627          * know there are new descriptors to fetch.  (Only
 628          * applicable for weak-ordered memory model archs,
 629          * such as IA-64).
 630          */
 631         wmb();
 632         IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
 633 }
 634
 635 /**
 636  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
 637  * @adapter: address of board private structure
 638  **/
 639 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
 640                                    struct ixgbe_ring *rx_ring,
 641                                    int cleaned_count)
 642 {
 643         struct pci_dev *pdev = adapter->pdev;
 644         union ixgbe_adv_rx_desc *rx_desc;
 645         struct ixgbe_rx_buffer *bi;
 646         unsigned int i;
 647
 648         i = rx_ring->next_to_use;
 649         bi = &rx_ring->rx_buffer_info[i];
 650
 651         while (cleaned_count--) {
 652                 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
 653
 654                 if (!bi->page_dma &&
 655                     (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
 656                         if (!bi->page) {
 657                                 bi->page = alloc_page(GFP_ATOMIC);
 658                                 if (!bi->page) {
 659                                         adapter->alloc_rx_page_failed++;
 660                                         goto no_buffers;
 661                                 }
 662                                 bi->page_offset = 0;
 663                         } else {
 664                                 /* use a half page if we're re-using */
 665                                 bi->page_offset ^= (PAGE_SIZE / 2);
 666                         }
 667
 668                         bi->page_dma = pci_map_page(pdev, bi->page,
 669                                                     bi->page_offset,
 670                                                     (PAGE_SIZE / 2),
 671                                                     PCI_DMA_FROMDEVICE);
 672                 }
 673
 674                 if (!bi->skb) {
 675                         struct sk_buff *skb;
 676                         skb = netdev_alloc_skb(adapter->netdev,
 677                                                (rx_ring->rx_buf_len +
 678                                                 NET_IP_ALIGN));
 679
 680                         if (!skb) {
 681                                 adapter->alloc_rx_buff_failed++;
 682                                 goto no_buffers;
 683                         }
 684
 685                         /*
 686                          * Make buffer alignment 2 beyond a 16 byte boundary
 687                          * this will result in a 16 byte aligned IP header after
 688                          * the 14 byte MAC header is removed
 689                          */
 690                         skb_reserve(skb, NET_IP_ALIGN);
 691
 692                         bi->skb = skb;
 693                         bi->dma = pci_map_single(pdev, skb->data,
 694                                                  rx_ring->rx_buf_len,
 695                                                  PCI_DMA_FROMDEVICE);
 696                 }
 697                 /* Refresh the desc even if buffer_addrs didn't change because
 698                  * each write-back erases this info. */
 699                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
 700                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
 701                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
 702                 } else {
 703                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
 704                 }
 705
 706                 i++;
 707                 if (i == rx_ring->count)
 708                         i = 0;
 709                 bi = &rx_ring->rx_buffer_info[i];
 710         }
 711
 712 no_buffers:
 713         if (rx_ring->next_to_use != i) {
 714                 rx_ring->next_to_use = i;
 715                 if (i-- == 0)
 716                         i = (rx_ring->count - 1);
 717
 718                 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
 719         }
 720 }
 721
 722 static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
 723 {
 724         return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
 725 }
 726
 727 static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
 728 {
 729         return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
 730 }
 731
 732 static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
 733 {
 734         return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
 735                 IXGBE_RXDADV_RSCCNT_MASK) >>
 736                 IXGBE_RXDADV_RSCCNT_SHIFT;
 737 }
 738
 739 /**
 740  * ixgbe_transform_rsc_queue - change rsc queue into a full packet
 741  * @skb: pointer to the last skb in the rsc queue
 742  *
 743  * This function changes a queue full of hw rsc buffers into a completed
 744  * packet.  It uses the ->prev pointers to find the first packet and then
 745  * turns it into the frag list owner.
 746  **/
 747 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
 748 {
 749         unsigned int frag_list_size = 0;
 750
 751         while (skb->prev) {
 752                 struct sk_buff *prev = skb->prev;
 753                 frag_list_size += skb->len;
 754                 skb->prev = NULL;
 755                 skb = prev;
 756         }
 757
 758         skb_shinfo(skb)->frag_list = skb->next;
 759         skb->next = NULL;
 760         skb->len += frag_list_size;
 761         skb->data_len += frag_list_size;
 762         skb->truesize += frag_list_size;
 763         return skb;
 764 }
 765
 766 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
 767                                struct ixgbe_ring *rx_ring,
 768                                int *work_done, int work_to_do)
 769 {
 770         struct ixgbe_adapter *adapter = q_vector->adapter;
 771         struct pci_dev *pdev = adapter->pdev;
 772         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
 773         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
 774         struct sk_buff *skb;
 775         unsigned int i, rsc_count = 0;
 776         u32 len, staterr;
 777         u16 hdr_info;
 778         bool cleaned = false;
 779         int cleaned_count = 0;
 780         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
 781 #ifdef IXGBE_FCOE
 782         int ddp_bytes = 0;
 783 #endif /* IXGBE_FCOE */
 784
 785         i = rx_ring->next_to_clean;
 786         rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
 787         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 788         rx_buffer_info = &rx_ring->rx_buffer_info[i];
 789
 790         while (staterr & IXGBE_RXD_STAT_DD) {
 791                 u32 upper_len = 0;
 792                 if (*work_done >= work_to_do)
 793                         break;
 794                 (*work_done)++;
 795
 796                 rmb(); /* read descriptor and rx_buffer_info after status DD */
 797                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
 798                         hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
 799                         len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
 800                                IXGBE_RXDADV_HDRBUFLEN_SHIFT;
 801                         if (hdr_info & IXGBE_RXDADV_SPH)
 802                                 adapter->rx_hdr_split++;
 803                         if (len > IXGBE_RX_HDR_SIZE)
 804                                 len = IXGBE_RX_HDR_SIZE;
 805                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
 806                 } else {
 807                         len = le16_to_cpu(rx_desc->wb.upper.length);
 808                 }
 809
 810                 cleaned = true;
 811                 skb = rx_buffer_info->skb;
 812                 prefetch(skb->data - NET_IP_ALIGN);
 813                 rx_buffer_info->skb = NULL;
 814
 815                 if (rx_buffer_info->dma) {
 816                         pci_unmap_single(pdev, rx_buffer_info->dma,
 817                                          rx_ring->rx_buf_len,
 818                                          PCI_DMA_FROMDEVICE);
 819                         rx_buffer_info->dma = 0;
 820                         skb_put(skb, len);
 821                 }
 822
 823                 if (upper_len) {
 824                         pci_unmap_page(pdev, rx_buffer_info->page_dma,
 825                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
 826                         rx_buffer_info->page_dma = 0;
 827                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
 828                                            rx_buffer_info->page,
 829                                            rx_buffer_info->page_offset,
 830                                            upper_len);
 831
 832                         if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
 833                             (page_count(rx_buffer_info->page) != 1))
 834                                 rx_buffer_info->page = NULL;
 835                         else
 836                                 get_page(rx_buffer_info->page);
 837
 838                         skb->len += upper_len;
 839                         skb->data_len += upper_len;
 840                         skb->truesize += upper_len;
 841                 }
 842
 843                 i++;
 844                 if (i == rx_ring->count)
 845                         i = 0;
 846
 847                 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
 848                 prefetch(next_rxd);
 849                 cleaned_count++;
 850
 851                 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
 852                         rsc_count = ixgbe_get_rsc_count(rx_desc);
 853
 854                 if (rsc_count) {
 855                         u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
 856                                      IXGBE_RXDADV_NEXTP_SHIFT;
 857                         next_buffer = &rx_ring->rx_buffer_info[nextp];
 858                         rx_ring->rsc_count += (rsc_count - 1);
 859                 } else {
 860                         next_buffer = &rx_ring->rx_buffer_info[i];
 861                 }
 862
 863                 if (staterr & IXGBE_RXD_STAT_EOP) {
 864                         if (skb->prev)
 865                                 skb = ixgbe_transform_rsc_queue(skb);
 866                         rx_ring->stats.packets++;
 867                         rx_ring->stats.bytes += skb->len;
 868                 } else {
 869                         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
 870                                 rx_buffer_info->skb = next_buffer->skb;
 871                                 rx_buffer_info->dma = next_buffer->dma;
 872                                 next_buffer->skb = skb;
 873                                 next_buffer->dma = 0;
 874                         } else {
 875                                 skb->next = next_buffer->skb;
 876                                 skb->next->prev = skb;
 877                         }
 878                         adapter->non_eop_descs++;
 879                         goto next_desc;
 880                 }
 881
 882                 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
 883                         dev_kfree_skb_irq(skb);
 884                         goto next_desc;
 885                 }
 886
 887                 ixgbe_rx_checksum(adapter, rx_desc, skb);
 888
 889                 /* probably a little skewed due to removing CRC */
 890                 total_rx_bytes += skb->len;
 891                 total_rx_packets++;
 892
 893                 skb->protocol = eth_type_trans(skb, adapter->netdev);
 894 #ifdef IXGBE_FCOE
 895                 /* if ddp, not passing to ULD unless for FCP_RSP or error */
 896                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
 897                         ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
 898                         if (!ddp_bytes)
 899                                 goto next_desc;
 900                 }
 901 #endif /* IXGBE_FCOE */
 902                 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
 903
 904 next_desc:
 905                 rx_desc->wb.upper.status_error = 0;
 906
 907                 /* return some buffers to hardware, one at a time is too slow */
 908                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
 909                         ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
 910                         cleaned_count = 0;
 911                 }
 912
 913                 /* use prefetched values */
 914                 rx_desc = next_rxd;
 915                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
 916
 917                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 918         }
 919
 920         rx_ring->next_to_clean = i;
 921         cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
 922
 923         if (cleaned_count)
 924                 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
 925
 926 #ifdef IXGBE_FCOE
 927         /* include DDPed FCoE data */
 928         if (ddp_bytes > 0) {
 929                 unsigned int mss;
 930
 931                 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
 932                         sizeof(struct fc_frame_header) -
 933                         sizeof(struct fcoe_crc_eof);
 934                 if (mss > 512)
 935                         mss &= ~511;
 936                 total_rx_bytes += ddp_bytes;
 937                 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
 938         }
 939 #endif /* IXGBE_FCOE */
 940
 941         rx_ring->total_packets += total_rx_packets;
 942         rx_ring->total_bytes += total_rx_bytes;
 943         adapter->net_stats.rx_bytes += total_rx_bytes;
 944         adapter->net_stats.rx_packets += total_rx_packets;
 945
 946         return cleaned;
 947 }
 948
 949 static int ixgbe_clean_rxonly(struct napi_struct *, int);
 950 /**
 951  * ixgbe_configure_msix - Configure MSI-X hardware
 952  * @adapter: board private structure
 953  *
 954  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
 955  * interrupts.
 956  **/
 957 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
 958 {
 959         struct ixgbe_q_vector *q_vector;
 960         int i, j, q_vectors, v_idx, r_idx;
 961         u32 mask;
 962
 963         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
 964
 965         /*
 966          * Populate the IVAR table and set the ITR values to the
 967          * corresponding register.
 968          */
 969         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
 970                 q_vector = adapter->q_vector[v_idx];
 971                 /* XXX for_each_bit(...) */
 972                 r_idx = find_first_bit(q_vector->rxr_idx,
 973                                        adapter->num_rx_queues);
 974
 975                 for (i = 0; i < q_vector->rxr_count; i++) {
 976                         j = adapter->rx_ring[r_idx].reg_idx;
 977                         ixgbe_set_ivar(adapter, 0, j, v_idx);
 978                         r_idx = find_next_bit(q_vector->rxr_idx,
 979                                               adapter->num_rx_queues,
 980                                               r_idx + 1);
 981                 }
 982                 r_idx = find_first_bit(q_vector->txr_idx,
 983                                        adapter->num_tx_queues);
 984
 985                 for (i = 0; i < q_vector->txr_count; i++) {
 986                         j = adapter->tx_ring[r_idx].reg_idx;
 987                         ixgbe_set_ivar(adapter, 1, j, v_idx);
 988                         r_idx = find_next_bit(q_vector->txr_idx,
 989                                               adapter->num_tx_queues,
 990                                               r_idx + 1);
 991                 }
 992
 993                 if (q_vector->txr_count && !q_vector->rxr_count)
 994                         /* tx only */
 995                         q_vector->eitr = adapter->tx_eitr_param;
 996                 else if (q_vector->rxr_count)
 997                         /* rx or mixed */
 998                         q_vector->eitr = adapter->rx_eitr_param;
 999
1000                 ixgbe_write_eitr(q_vector);
1001         }
1002
1003         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1004                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1005                                v_idx);
1006         else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1007                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1008         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1009
1010         /* set up to autoclear timer, and the vectors */
1011         mask = IXGBE_EIMS_ENABLE_MASK;
1012         mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1013         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1014 }
1015
1016 enum latency_range {
1017         lowest_latency = 0,
1018         low_latency = 1,
1019         bulk_latency = 2,
1020         latency_invalid = 255
1021 };
1022
1023 /**
1024  * ixgbe_update_itr - update the dynamic ITR value based on statistics
1025  * @adapter: pointer to adapter
1026  * @eitr: eitr setting (ints per sec) to give last timeslice
1027  * @itr_setting: current throttle rate in ints/second
1028  * @packets: the number of packets during this measurement interval
1029  * @bytes: the number of bytes during this measurement interval
1030  *
1031  *      Stores a new ITR value based on packets and byte
1032  *      counts during the last interrupt.  The advantage of per interrupt
1033  *      computation is faster updates and more accurate ITR for the current
1034  *      traffic pattern.  Constants in this function were computed
1035  *      based on theoretical maximum wire speed and thresholds were set based
1036  *      on testing data as well as attempting to minimize response time
1037  *      while increasing bulk throughput.
1038  *      this functionality is controlled by the InterruptThrottleRate module
1039  *      parameter (see ixgbe_param.c)
1040  **/
1041 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
1042                            u32 eitr, u8 itr_setting,
1043                            int packets, int bytes)
1044 {
1045         unsigned int retval = itr_setting;
1046         u32 timepassed_us;
1047         u64 bytes_perint;
1048
1049         if (packets == 0)
1050                 goto update_itr_done;
1051
1052
1053         /* simple throttlerate management
1054          *    0-20MB/s lowest (100000 ints/s)
1055          *   20-100MB/s low   (20000 ints/s)
1056          *  100-1249MB/s bulk (8000 ints/s)
1057          */
1058         /* what was last interrupt timeslice? */
1059         timepassed_us = 1000000/eitr;
1060         bytes_perint = bytes / timepassed_us; /* bytes/usec */
1061
1062         switch (itr_setting) {
1063         case lowest_latency:
1064                 if (bytes_perint > adapter->eitr_low)
1065                         retval = low_latency;
1066                 break;
1067         case low_latency:
1068                 if (bytes_perint > adapter->eitr_high)
1069                         retval = bulk_latency;
1070                 else if (bytes_perint <= adapter->eitr_low)
1071                         retval = lowest_latency;
1072                 break;
1073         case bulk_latency:
1074                 if (bytes_perint <= adapter->eitr_high)
1075                         retval = low_latency;
1076                 break;
1077         }
1078
1079 update_itr_done:
1080         return retval;
1081 }
1082
1083 /**
1084  * ixgbe_write_eitr - write EITR register in hardware specific way
1085  * @q_vector: structure containing interrupt and ring information
1086  *
1087  * This function is made to be called by ethtool and by the driver
1088  * when it needs to update EITR registers at runtime.  Hardware
1089  * specific quirks/differences are taken care of here.
1090  */
1091 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1092 {
1093         struct ixgbe_adapter *adapter = q_vector->adapter;
1094         struct ixgbe_hw *hw = &adapter->hw;
1095         int v_idx = q_vector->v_idx;
1096         u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1097
1098         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1099                 /* must write high and low 16 bits to reset counter */
1100                 itr_reg |= (itr_reg << 16);
1101         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1102                 /*
1103                  * set the WDIS bit to not clear the timer bits and cause an
1104                  * immediate assertion of the interrupt
1105                  */
1106                 itr_reg |= IXGBE_EITR_CNT_WDIS;
1107         }
1108         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1109 }
1110
1111 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1112 {
1113         struct ixgbe_adapter *adapter = q_vector->adapter;
1114         u32 new_itr;
1115         u8 current_itr, ret_itr;
1116         int i, r_idx;
1117         struct ixgbe_ring *rx_ring, *tx_ring;
1118
1119         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1120         for (i = 0; i < q_vector->txr_count; i++) {
1121                 tx_ring = &(adapter->tx_ring[r_idx]);
1122                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1123                                            q_vector->tx_itr,
1124                                            tx_ring->total_packets,
1125                                            tx_ring->total_bytes);
1126                 /* if the result for this queue would decrease interrupt
1127                  * rate for this vector then use that result */
1128                 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1129                                     q_vector->tx_itr - 1 : ret_itr);
1130                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1131                                       r_idx + 1);
1132         }
1133
1134         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1135         for (i = 0; i < q_vector->rxr_count; i++) {
1136                 rx_ring = &(adapter->rx_ring[r_idx]);
1137                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1138                                            q_vector->rx_itr,
1139                                            rx_ring->total_packets,
1140                                            rx_ring->total_bytes);
1141                 /* if the result for this queue would decrease interrupt
1142                  * rate for this vector then use that result */
1143                 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1144                                     q_vector->rx_itr - 1 : ret_itr);
1145                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1146                                       r_idx + 1);
1147         }
1148
1149         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1150
1151         switch (current_itr) {
1152         /* counts and packets in update_itr are dependent on these numbers */
1153         case lowest_latency:
1154                 new_itr = 100000;
1155                 break;
1156         case low_latency:
1157                 new_itr = 20000; /* aka hwitr = ~200 */
1158                 break;
1159         case bulk_latency:
1160         default:
1161                 new_itr = 8000;
1162                 break;
1163         }
1164
1165         if (new_itr != q_vector->eitr) {
1166                 /* do an exponential smoothing */
1167                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1168
1169                 /* save the algorithm value here, not the smoothed one */
1170                 q_vector->eitr = new_itr;
1171
1172                 ixgbe_write_eitr(q_vector);
1173         }
1174
1175         return;
1176 }
1177
1178 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1179 {
1180         struct ixgbe_hw *hw = &adapter->hw;
1181
1182         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1183             (eicr & IXGBE_EICR_GPI_SDP1)) {
1184                 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1185                 /* write to clear the interrupt */
1186                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1187         }
1188 }
1189
1190 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1191 {
1192         struct ixgbe_hw *hw = &adapter->hw;
1193
1194         if (eicr & IXGBE_EICR_GPI_SDP1) {
1195                 /* Clear the interrupt */
1196                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1197                 schedule_work(&adapter->multispeed_fiber_task);
1198         } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1199                 /* Clear the interrupt */
1200                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1201                 schedule_work(&adapter->sfp_config_module_task);
1202         } else {
1203                 /* Interrupt isn't for us... */
1204                 return;
1205         }
1206 }
1207
1208 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1209 {
1210         struct ixgbe_hw *hw = &adapter->hw;
1211
1212         adapter->lsc_int++;
1213         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1214         adapter->link_check_timeout = jiffies;
1215         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1216                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1217                 schedule_work(&adapter->watchdog_task);
1218         }
1219 }
1220
1221 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1222 {
1223         struct net_device *netdev = data;
1224         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1225         struct ixgbe_hw *hw = &adapter->hw;
1226         u32 eicr;
1227
1228         /*
1229          * Workaround for Silicon errata.  Use clear-by-write instead
1230          * of clear-by-read.  Reading with EICS will return the
1231          * interrupt causes without clearing, which later be done
1232          * with the write to EICR.
1233          */
1234         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1235         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1236
1237         if (eicr & IXGBE_EICR_LSC)
1238                 ixgbe_check_lsc(adapter);
1239
1240         if (hw->mac.type == ixgbe_mac_82598EB)
1241                 ixgbe_check_fan_failure(adapter, eicr);
1242
1243         if (hw->mac.type == ixgbe_mac_82599EB) {
1244                 ixgbe_check_sfp_event(adapter, eicr);
1245
1246                 /* Handle Flow Director Full threshold interrupt */
1247                 if (eicr & IXGBE_EICR_FLOW_DIR) {
1248                         int i;
1249                         IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1250                         /* Disable transmits before FDIR Re-initialization */
1251                         netif_tx_stop_all_queues(netdev);
1252                         for (i = 0; i < adapter->num_tx_queues; i++) {
1253                                 struct ixgbe_ring *tx_ring =
1254                                                            &adapter->tx_ring[i];
1255                                 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1256                                                        &tx_ring->reinit_state))
1257                                         schedule_work(&adapter->fdir_reinit_task);
1258                         }
1259                 }
1260         }
1261         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1262                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1263
1264         return IRQ_HANDLED;
1265 }
1266
1267 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1268                                            u64 qmask)
1269 {
1270         u32 mask;
1271
1272         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1273                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1274                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1275         } else {
1276                 mask = (qmask & 0xFFFFFFFF);
1277                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1278                 mask = (qmask >> 32);
1279                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1280         }
1281         /* skip the flush */
1282 }
1283
1284 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1285                                             u64 qmask)
1286 {
1287         u32 mask;
1288
1289         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1290                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1291                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1292         } else {
1293                 mask = (qmask & 0xFFFFFFFF);
1294                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1295                 mask = (qmask >> 32);
1296                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1297         }
1298         /* skip the flush */
1299 }
1300
1301 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1302 {
1303         struct ixgbe_q_vector *q_vector = data;
1304         struct ixgbe_adapter  *adapter = q_vector->adapter;
1305         struct ixgbe_ring     *tx_ring;
1306         int i, r_idx;
1307
1308         if (!q_vector->txr_count)
1309                 return IRQ_HANDLED;
1310
1311         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1312         for (i = 0; i < q_vector->txr_count; i++) {
1313                 tx_ring = &(adapter->tx_ring[r_idx]);
1314                 tx_ring->total_bytes = 0;
1315                 tx_ring->total_packets = 0;
1316                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1317                                       r_idx + 1);
1318         }
1319
1320         /* disable interrupts on this vector only */
1321         ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1322         napi_schedule(&q_vector->napi);
1323
1324         return IRQ_HANDLED;
1325 }
1326
1327 /**
1328  * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1329  * @irq: unused
1330  * @data: pointer to our q_vector struct for this interrupt vector
1331  **/
1332 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1333 {
1334         struct ixgbe_q_vector *q_vector = data;
1335         struct ixgbe_adapter  *adapter = q_vector->adapter;
1336         struct ixgbe_ring  *rx_ring;
1337         int r_idx;
1338         int i;
1339
1340         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1341         for (i = 0;  i < q_vector->rxr_count; i++) {
1342                 rx_ring = &(adapter->rx_ring[r_idx]);
1343                 rx_ring->total_bytes = 0;
1344                 rx_ring->total_packets = 0;
1345                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1346                                       r_idx + 1);
1347         }
1348
1349         if (!q_vector->rxr_count)
1350                 return IRQ_HANDLED;
1351
1352         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1353         rx_ring = &(adapter->rx_ring[r_idx]);
1354         /* disable interrupts on this vector only */
1355         ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1356         napi_schedule(&q_vector->napi);
1357
1358         return IRQ_HANDLED;
1359 }
1360
1361 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1362 {
1363         struct ixgbe_q_vector *q_vector = data;
1364         struct ixgbe_adapter  *adapter = q_vector->adapter;
1365         struct ixgbe_ring  *ring;
1366         int r_idx;
1367         int i;
1368
1369         if (!q_vector->txr_count && !q_vector->rxr_count)
1370                 return IRQ_HANDLED;
1371
1372         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1373         for (i = 0; i < q_vector->txr_count; i++) {
1374                 ring = &(adapter->tx_ring[r_idx]);
1375                 ring->total_bytes = 0;
1376                 ring->total_packets = 0;
1377                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1378                                       r_idx + 1);
1379         }
1380
1381         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1382         for (i = 0; i < q_vector->rxr_count; i++) {
1383                 ring = &(adapter->rx_ring[r_idx]);
1384                 ring->total_bytes = 0;
1385                 ring->total_packets = 0;
1386                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1387                                       r_idx + 1);
1388         }
1389
1390         /* disable interrupts on this vector only */
1391         ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1392         napi_schedule(&q_vector->napi);
1393
1394         return IRQ_HANDLED;
1395 }
1396
1397 /**
1398  * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1399  * @napi: napi struct with our devices info in it
1400  * @budget: amount of work driver is allowed to do this pass, in packets
1401  *
1402  * This function is optimized for cleaning one queue only on a single
1403  * q_vector!!!
1404  **/
1405 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1406 {
1407         struct ixgbe_q_vector *q_vector =
1408                                container_of(napi, struct ixgbe_q_vector, napi);
1409         struct ixgbe_adapter *adapter = q_vector->adapter;
1410         struct ixgbe_ring *rx_ring = NULL;
1411         int work_done = 0;
1412         long r_idx;
1413
1414         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1415         rx_ring = &(adapter->rx_ring[r_idx]);
1416 #ifdef CONFIG_IXGBE_DCA
1417         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1418                 ixgbe_update_rx_dca(adapter, rx_ring);
1419 #endif
1420
1421         ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1422
1423         /* If all Rx work done, exit the polling mode */
1424         if (work_done < budget) {
1425                 napi_complete(napi);
1426                 if (adapter->rx_itr_setting & 1)
1427                         ixgbe_set_itr_msix(q_vector);
1428                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1429                         ixgbe_irq_enable_queues(adapter,
1430                                                 ((u64)1 << q_vector->v_idx));
1431         }
1432
1433         return work_done;
1434 }
1435
1436 /**
1437  * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
1438  * @napi: napi struct with our devices info in it
1439  * @budget: amount of work driver is allowed to do this pass, in packets
1440  *
1441  * This function will clean more than one rx queue associated with a
1442  * q_vector.
1443  **/
1444 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
1445 {
1446         struct ixgbe_q_vector *q_vector =
1447                                container_of(napi, struct ixgbe_q_vector, napi);
1448         struct ixgbe_adapter *adapter = q_vector->adapter;
1449         struct ixgbe_ring *ring = NULL;
1450         int work_done = 0, i;
1451         long r_idx;
1452         bool tx_clean_complete = true;
1453
1454         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1455         for (i = 0; i < q_vector->txr_count; i++) {
1456                 ring = &(adapter->tx_ring[r_idx]);
1457 #ifdef CONFIG_IXGBE_DCA
1458                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1459                         ixgbe_update_tx_dca(adapter, ring);
1460 #endif
1461                 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1462                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1463                                       r_idx + 1);
1464         }
1465
1466         /* attempt to distribute budget to each queue fairly, but don't allow
1467          * the budget to go below 1 because we'll exit polling */
1468         budget /= (q_vector->rxr_count ?: 1);
1469         budget = max(budget, 1);
1470         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1471         for (i = 0; i < q_vector->rxr_count; i++) {
1472                 ring = &(adapter->rx_ring[r_idx]);
1473 #ifdef CONFIG_IXGBE_DCA
1474                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1475                         ixgbe_update_rx_dca(adapter, ring);
1476 #endif
1477                 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
1478                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1479                                       r_idx + 1);
1480         }
1481
1482         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1483         ring = &(adapter->rx_ring[r_idx]);
1484         /* If all Rx work done, exit the polling mode */
1485         if (work_done < budget) {
1486                 napi_complete(napi);
1487                 if (adapter->rx_itr_setting & 1)
1488                         ixgbe_set_itr_msix(q_vector);
1489                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1490                         ixgbe_irq_enable_queues(adapter,
1491                                                 ((u64)1 << q_vector->v_idx));
1492                 return 0;
1493         }
1494
1495         return work_done;
1496 }
1497
1498 /**
1499  * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1500  * @napi: napi struct with our devices info in it
1501  * @budget: amount of work driver is allowed to do this pass, in packets
1502  *
1503  * This function is optimized for cleaning one queue only on a single
1504  * q_vector!!!
1505  **/
1506 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1507 {
1508         struct ixgbe_q_vector *q_vector =
1509                                container_of(napi, struct ixgbe_q_vector, napi);
1510         struct ixgbe_adapter *adapter = q_vector->adapter;
1511         struct ixgbe_ring *tx_ring = NULL;
1512         int work_done = 0;
1513         long r_idx;
1514
1515         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1516         tx_ring = &(adapter->tx_ring[r_idx]);
1517 #ifdef CONFIG_IXGBE_DCA
1518         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1519                 ixgbe_update_tx_dca(adapter, tx_ring);
1520 #endif
1521
1522         if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
1523                 work_done = budget;
1524
1525         /* If all Tx work done, exit the polling mode */
1526         if (work_done < budget) {
1527                 napi_complete(napi);
1528                 if (adapter->tx_itr_setting & 1)
1529                         ixgbe_set_itr_msix(q_vector);
1530                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1531                         ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
1532         }
1533
1534         return work_done;
1535 }
1536
1537 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
1538                                      int r_idx)
1539 {
1540         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1541
1542         set_bit(r_idx, q_vector->rxr_idx);
1543         q_vector->rxr_count++;
1544 }
1545
1546 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
1547                                      int t_idx)
1548 {
1549         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1550
1551         set_bit(t_idx, q_vector->txr_idx);
1552         q_vector->txr_count++;
1553 }
1554
1555 /**
1556  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1557  * @adapter: board private structure to initialize
1558  * @vectors: allotted vector count for descriptor rings
1559  *
1560  * This function maps descriptor rings to the queue-specific vectors
1561  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
1562  * one vector per ring/queue, but on a constrained vector budget, we
1563  * group the rings as "efficiently" as possible.  You would add new
1564  * mapping configurations in here.
1565  **/
1566 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
1567                                       int vectors)
1568 {
1569         int v_start = 0;
1570         int rxr_idx = 0, txr_idx = 0;
1571         int rxr_remaining = adapter->num_rx_queues;
1572         int txr_remaining = adapter->num_tx_queues;
1573         int i, j;
1574         int rqpv, tqpv;
1575         int err = 0;
1576
1577         /* No mapping required if MSI-X is disabled. */
1578         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1579                 goto out;
1580
1581         /*
1582          * The ideal configuration...
1583          * We have enough vectors to map one per queue.
1584          */
1585         if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1586                 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1587                         map_vector_to_rxq(adapter, v_start, rxr_idx);
1588
1589                 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1590                         map_vector_to_txq(adapter, v_start, txr_idx);
1591
1592                 goto out;
1593         }
1594
1595         /*
1596          * If we don't have enough vectors for a 1-to-1
1597          * mapping, we'll have to group them so there are
1598          * multiple queues per vector.
1599          */
1600         /* Re-adjusting *qpv takes care of the remainder. */
1601         for (i = v_start; i < vectors; i++) {
1602                 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1603                 for (j = 0; j < rqpv; j++) {
1604                         map_vector_to_rxq(adapter, i, rxr_idx);
1605                         rxr_idx++;
1606                         rxr_remaining--;
1607                 }
1608         }
1609         for (i = v_start; i < vectors; i++) {
1610                 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1611                 for (j = 0; j < tqpv; j++) {
1612                         map_vector_to_txq(adapter, i, txr_idx);
1613                         txr_idx++;
1614                         txr_remaining--;
1615                 }
1616         }
1617
1618 out:
1619         return err;
1620 }
1621
1622 /**
1623  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1624  * @adapter: board private structure
1625  *
1626  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1627  * interrupts from the kernel.
1628  **/
1629 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1630 {
1631         struct net_device *netdev = adapter->netdev;
1632         irqreturn_t (*handler)(int, void *);
1633         int i, vector, q_vectors, err;
1634         int ri=0, ti=0;
1635
1636         /* Decrement for Other and TCP Timer vectors */
1637         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1638
1639         /* Map the Tx/Rx rings to the vectors we were allotted. */
1640         err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1641         if (err)
1642                 goto out;
1643
1644 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
1645                          (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1646                          &ixgbe_msix_clean_many)
1647         for (vector = 0; vector < q_vectors; vector++) {
1648                 handler = SET_HANDLER(adapter->q_vector[vector]);
1649
1650                 if(handler == &ixgbe_msix_clean_rx) {
1651                         sprintf(adapter->name[vector], "%s-%s-%d",
1652                                 netdev->name, "rx", ri++);
1653                 }
1654                 else if(handler == &ixgbe_msix_clean_tx) {
1655                         sprintf(adapter->name[vector], "%s-%s-%d",
1656                                 netdev->name, "tx", ti++);
1657                 }
1658                 else
1659                         sprintf(adapter->name[vector], "%s-%s-%d",
1660                                 netdev->name, "TxRx", vector);
1661
1662                 err = request_irq(adapter->msix_entries[vector].vector,
1663                                   handler, 0, adapter->name[vector],
1664                                   adapter->q_vector[vector]);
1665                 if (err) {
1666                         DPRINTK(PROBE, ERR,
1667                                 "request_irq failed for MSIX interrupt "
1668                                 "Error: %d\n", err);
1669                         goto free_queue_irqs;
1670                 }
1671         }
1672
1673         sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1674         err = request_irq(adapter->msix_entries[vector].vector,
1675                           &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
1676         if (err) {
1677                 DPRINTK(PROBE, ERR,
1678                         "request_irq for msix_lsc failed: %d\n", err);
1679                 goto free_queue_irqs;
1680         }
1681
1682         return 0;
1683
1684 free_queue_irqs:
1685         for (i = vector - 1; i >= 0; i--)
1686                 free_irq(adapter->msix_entries[--vector].vector,
1687                          adapter->q_vector[i]);
1688         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1689         pci_disable_msix(adapter->pdev);
1690         kfree(adapter->msix_entries);
1691         adapter->msix_entries = NULL;
1692 out:
1693         return err;
1694 }
1695
1696 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1697 {
1698         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1699         u8 current_itr;
1700         u32 new_itr = q_vector->eitr;
1701         struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1702         struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1703
1704         q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
1705                                             q_vector->tx_itr,
1706                                             tx_ring->total_packets,
1707                                             tx_ring->total_bytes);
1708         q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
1709                                             q_vector->rx_itr,
1710                                             rx_ring->total_packets,
1711                                             rx_ring->total_bytes);
1712
1713         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1714
1715         switch (current_itr) {
1716         /* counts and packets in update_itr are dependent on these numbers */
1717         case lowest_latency:
1718                 new_itr = 100000;
1719                 break;
1720         case low_latency:
1721                 new_itr = 20000; /* aka hwitr = ~200 */
1722                 break;
1723         case bulk_latency:
1724                 new_itr = 8000;
1725                 break;
1726         default:
1727                 break;
1728         }
1729
1730         if (new_itr != q_vector->eitr) {
1731                 /* do an exponential smoothing */
1732                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1733
1734                 /* save the algorithm value here, not the smoothed one */
1735                 q_vector->eitr = new_itr;
1736
1737                 ixgbe_write_eitr(q_vector);
1738         }
1739
1740         return;
1741 }
1742
1743 /**
1744  * ixgbe_irq_enable - Enable default interrupt generation settings
1745  * @adapter: board private structure
1746  **/
1747 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1748 {
1749         u32 mask;
1750
1751         mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
1752         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1753                 mask |= IXGBE_EIMS_GPI_SDP1;
1754         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1755                 mask |= IXGBE_EIMS_ECC;
1756                 mask |= IXGBE_EIMS_GPI_SDP1;
1757                 mask |= IXGBE_EIMS_GPI_SDP2;
1758         }
1759         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
1760             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
1761                 mask |= IXGBE_EIMS_FLOW_DIR;
1762
1763         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1764         ixgbe_irq_enable_queues(adapter, ~0);
1765         IXGBE_WRITE_FLUSH(&adapter->hw);
1766 }
1767
1768 /**
1769  * ixgbe_intr - legacy mode Interrupt Handler
1770  * @irq: interrupt number
1771  * @data: pointer to a network interface device structure
1772  **/
1773 static irqreturn_t ixgbe_intr(int irq, void *data)
1774 {
1775         struct net_device *netdev = data;
1776         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1777         struct ixgbe_hw *hw = &adapter->hw;
1778         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1779         u32 eicr;
1780
1781         /*
1782          * Workaround for silicon errata.  Mask the interrupts
1783          * before the read of EICR.
1784          */
1785         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1786
1787         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1788          * therefore no explict interrupt disable is necessary */
1789         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1790         if (!eicr) {
1791                 /* shared interrupt alert!
1792                  * make sure interrupts are enabled because the read will
1793                  * have disabled interrupts due to EIAM */
1794                 ixgbe_irq_enable(adapter);
1795                 return IRQ_NONE;        /* Not our interrupt */
1796         }
1797
1798         if (eicr & IXGBE_EICR_LSC)
1799                 ixgbe_check_lsc(adapter);
1800
1801         if (hw->mac.type == ixgbe_mac_82599EB)
1802                 ixgbe_check_sfp_event(adapter, eicr);
1803
1804         ixgbe_check_fan_failure(adapter, eicr);
1805
1806         if (napi_schedule_prep(&(q_vector->napi))) {
1807                 adapter->tx_ring[0].total_packets = 0;
1808                 adapter->tx_ring[0].total_bytes = 0;
1809                 adapter->rx_ring[0].total_packets = 0;
1810                 adapter->rx_ring[0].total_bytes = 0;
1811                 /* would disable interrupts here but EIAM disabled it */
1812                 __napi_schedule(&(q_vector->napi));
1813         }
1814
1815         return IRQ_HANDLED;
1816 }
1817
1818 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1819 {
1820         int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1821
1822         for (i = 0; i < q_vectors; i++) {
1823                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
1824                 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1825                 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1826                 q_vector->rxr_count = 0;
1827                 q_vector->txr_count = 0;
1828         }
1829 }
1830
1831 /**
1832  * ixgbe_request_irq - initialize interrupts
1833  * @adapter: board private structure
1834  *
1835  * Attempts to configure interrupts using the best available
1836  * capabilities of the hardware and kernel.
1837  **/
1838 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
1839 {
1840         struct net_device *netdev = adapter->netdev;
1841         int err;
1842
1843         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1844                 err = ixgbe_request_msix_irqs(adapter);
1845         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1846                 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
1847                                   netdev->name, netdev);
1848         } else {
1849                 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
1850                                   netdev->name, netdev);
1851         }
1852
1853         if (err)
1854                 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1855
1856         return err;
1857 }
1858
1859 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1860 {
1861         struct net_device *netdev = adapter->netdev;
1862
1863         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1864                 int i, q_vectors;
1865
1866                 q_vectors = adapter->num_msix_vectors;
1867
1868                 i = q_vectors - 1;
1869                 free_irq(adapter->msix_entries[i].vector, netdev);
1870
1871                 i--;
1872                 for (; i >= 0; i--) {
1873                         free_irq(adapter->msix_entries[i].vector,
1874                                  adapter->q_vector[i]);
1875                 }
1876
1877                 ixgbe_reset_q_vectors(adapter);
1878         } else {
1879                 free_irq(adapter->pdev->irq, netdev);
1880         }
1881 }
1882
1883 /**
1884  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1885  * @adapter: board private structure
1886  **/
1887 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1888 {
1889         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1890                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1891         } else {
1892                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
1893                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
1894                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1895         }
1896         IXGBE_WRITE_FLUSH(&adapter->hw);
1897         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1898                 int i;
1899                 for (i = 0; i < adapter->num_msix_vectors; i++)
1900                         synchronize_irq(adapter->msix_entries[i].vector);
1901         } else {
1902                 synchronize_irq(adapter->pdev->irq);
1903         }
1904 }
1905
1906 /**
1907  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1908  *
1909  **/
1910 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1911 {
1912         struct ixgbe_hw *hw = &adapter->hw;
1913
1914         IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
1915                         EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
1916
1917         ixgbe_set_ivar(adapter, 0, 0, 0);
1918         ixgbe_set_ivar(adapter, 1, 0, 0);
1919
1920         map_vector_to_rxq(adapter, 0, 0);
1921         map_vector_to_txq(adapter, 0, 0);
1922
1923         DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
1924 }
1925
1926 /**
1927  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
1928  * @adapter: board private structure
1929  *
1930  * Configure the Tx unit of the MAC after a reset.
1931  **/
1932 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1933 {
1934         u64 tdba;
1935         struct ixgbe_hw *hw = &adapter->hw;
1936         u32 i, j, tdlen, txctrl;
1937
1938         /* Setup the HW Tx Head and Tail descriptor pointers */
1939         for (i = 0; i < adapter->num_tx_queues; i++) {
1940                 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1941                 j = ring->reg_idx;
1942                 tdba = ring->dma;
1943                 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
1944                 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
1945                                 (tdba & DMA_BIT_MASK(32)));
1946                 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
1947                 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1948                 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1949                 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1950                 adapter->tx_ring[i].head = IXGBE_TDH(j);
1951                 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1952                 /*
1953                  * Disable Tx Head Writeback RO bit, since this hoses
1954                  * bookkeeping if things aren't delivered in order.
1955                  */
1956                 switch (hw->mac.type) {
1957                 case ixgbe_mac_82598EB:
1958                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
1959                         break;
1960                 case ixgbe_mac_82599EB:
1961                 default:
1962                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(j));
1963                         break;
1964                 }
1965                 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
1966                 switch (hw->mac.type) {
1967                 case ixgbe_mac_82598EB:
1968                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
1969                         break;
1970                 case ixgbe_mac_82599EB:
1971                 default:
1972                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(j), txctrl);
1973                         break;
1974                 }
1975         }
1976
1977         if (hw->mac.type == ixgbe_mac_82599EB) {
1978                 u32 rttdcs;
1979
1980                 /* disable the arbiter while setting MTQC */
1981                 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
1982                 rttdcs |= IXGBE_RTTDCS_ARBDIS;
1983                 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
1984
1985                 /* We enable 8 traffic classes, DCB only */
1986                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
1987                         IXGBE_WRITE_REG(hw, IXGBE_MTQC, (IXGBE_MTQC_RT_ENA |
1988                                         IXGBE_MTQC_8TC_8TQ));
1989                 else
1990                         IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
1991
1992                 /* re-eable the arbiter */
1993                 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
1994                 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
1995         }
1996 }
1997
1998 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
1999
2000 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2001                                    struct ixgbe_ring *rx_ring)
2002 {
2003         u32 srrctl;
2004         int index;
2005         struct ixgbe_ring_feature *feature = adapter->ring_feature;
2006
2007         index = rx_ring->reg_idx;
2008         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2009                 unsigned long mask;
2010                 mask = (unsigned long) feature[RING_F_RSS].mask;
2011                 index = index & mask;
2012         }
2013         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
2014
2015         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2016         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2017
2018         srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2019                   IXGBE_SRRCTL_BSIZEHDR_MASK;
2020
2021         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2022 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2023                 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2024 #else
2025                 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2026 #endif
2027                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2028         } else {
2029                 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2030                           IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2031                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2032         }
2033
2034         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
2035 }
2036
2037 static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2038 {
2039         u32 mrqc = 0;
2040         int mask;
2041
2042         if (!(adapter->hw.mac.type == ixgbe_mac_82599EB))
2043                 return mrqc;
2044
2045         mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2046 #ifdef CONFIG_IXGBE_DCB
2047                                  | IXGBE_FLAG_DCB_ENABLED
2048 #endif
2049                                 );
2050
2051         switch (mask) {
2052         case (IXGBE_FLAG_RSS_ENABLED):
2053                 mrqc = IXGBE_MRQC_RSSEN;
2054                 break;
2055 #ifdef CONFIG_IXGBE_DCB
2056         case (IXGBE_FLAG_DCB_ENABLED):
2057                 mrqc = IXGBE_MRQC_RT8TCEN;
2058                 break;
2059 #endif /* CONFIG_IXGBE_DCB */
2060         default:
2061                 break;
2062         }
2063
2064         return mrqc;
2065 }
2066
2067 /**
2068  * ixgbe_configure_rscctl - enable RSC for the indicated ring
2069  * @adapter:    address of board private structure
2070  * @index:      index of ring to set
2071  * @rx_buf_len: rx buffer length
2072  **/
2073 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, int index,
2074                                    int rx_buf_len)
2075 {
2076         struct ixgbe_ring *rx_ring;
2077         struct ixgbe_hw *hw = &adapter->hw;
2078         int j;
2079         u32 rscctrl;
2080
2081         rx_ring = &adapter->rx_ring[index];
2082         j = rx_ring->reg_idx;
2083         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
2084         rscctrl |= IXGBE_RSCCTL_RSCEN;
2085         /*
2086          * we must limit the number of descriptors so that the
2087          * total size of max desc * buf_len is not greater
2088          * than 65535
2089          */
2090         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2091 #if (MAX_SKB_FRAGS > 16)
2092                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2093 #elif (MAX_SKB_FRAGS > 8)
2094                 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2095 #elif (MAX_SKB_FRAGS > 4)
2096                 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2097 #else
2098                 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2099 #endif
2100         } else {
2101                 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2102                         rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2103                 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2104                         rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2105                 else
2106                         rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2107         }
2108         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
2109 }
2110
2111 /**
2112  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
2113  * @adapter: board private structure
2114  *
2115  * Configure the Rx unit of the MAC after a reset.
2116  **/
2117 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
2118 {
2119         u64 rdba;
2120         struct ixgbe_hw *hw = &adapter->hw;
2121         struct ixgbe_ring *rx_ring;
2122         struct net_device *netdev = adapter->netdev;
2123         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2124         int i, j;
2125         u32 rdlen, rxctrl, rxcsum;
2126         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2127                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2128                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
2129         u32 fctrl, hlreg0;
2130         u32 reta = 0, mrqc = 0;
2131         u32 rdrxctl;
2132         int rx_buf_len;
2133
2134         /* Decide whether to use packet split mode or not */
2135         adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2136
2137         /* Disable packet split due to 82599 erratum #45 */
2138         if (hw->mac.type == ixgbe_mac_82599EB)
2139                 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
2140
2141         /* Set the RX buffer length according to the mode */
2142         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2143                 rx_buf_len = IXGBE_RX_HDR_SIZE;
2144                 if (hw->mac.type == ixgbe_mac_82599EB) {
2145                         /* PSRTYPE must be initialized in 82599 */
2146                         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2147                                       IXGBE_PSRTYPE_UDPHDR |
2148                                       IXGBE_PSRTYPE_IPV4HDR |
2149                                       IXGBE_PSRTYPE_IPV6HDR |
2150                                       IXGBE_PSRTYPE_L2HDR;
2151                         IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype);
2152                 }
2153         } else {
2154                 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2155                     (netdev->mtu <= ETH_DATA_LEN))
2156                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2157                 else
2158                         rx_buf_len = ALIGN(max_frame, 1024);
2159         }
2160
2161         fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
2162         fctrl |= IXGBE_FCTRL_BAM;
2163         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
2164         fctrl |= IXGBE_FCTRL_PMCF;
2165         IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
2166
2167         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2168         if (adapter->netdev->mtu <= ETH_DATA_LEN)
2169                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2170         else
2171                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2172 #ifdef IXGBE_FCOE
2173         if (netdev->features & NETIF_F_FCOE_MTU)
2174                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2175 #endif
2176         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2177
2178         rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
2179         /* disable receives while setting up the descriptors */
2180         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2181         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2182
2183         /*
2184          * Setup the HW Rx Head and Tail Descriptor Pointers and
2185          * the Base and Length of the Rx Descriptor Ring
2186          */
2187         for (i = 0; i < adapter->num_rx_queues; i++) {
2188                 rx_ring = &adapter->rx_ring[i];
2189                 rdba = rx_ring->dma;
2190                 j = rx_ring->reg_idx;
2191                 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
2192                 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
2193                 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
2194                 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
2195                 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
2196                 rx_ring->head = IXGBE_RDH(j);
2197                 rx_ring->tail = IXGBE_RDT(j);
2198                 rx_ring->rx_buf_len = rx_buf_len;
2199
2200                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2201                         rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
2202                 else
2203                         rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2204
2205 #ifdef IXGBE_FCOE
2206                 if (netdev->features & NETIF_F_FCOE_MTU) {
2207                         struct ixgbe_ring_feature *f;
2208                         f = &adapter->ring_feature[RING_F_FCOE];
2209                         if ((i >= f->mask) && (i < f->mask + f->indices)) {
2210                                 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2211                                 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2212                                         rx_ring->rx_buf_len =
2213                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2214                         }
2215                 }
2216
2217 #endif /* IXGBE_FCOE */
2218                 ixgbe_configure_srrctl(adapter, rx_ring);
2219         }
2220
2221         if (hw->mac.type == ixgbe_mac_82598EB) {
2222                 /*
2223                  * For VMDq support of different descriptor types or
2224                  * buffer sizes through the use of multiple SRRCTL
2225                  * registers, RDRXCTL.MVMEN must be set to 1
2226                  *
2227                  * also, the manual doesn't mention it clearly but DCA hints
2228                  * will only use queue 0's tags unless this bit is set.  Side
2229                  * effects of setting this bit are only that SRRCTL must be
2230                  * fully programmed [0..15]
2231                  */
2232                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2233                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2234                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2235         }
2236
2237         /* Program MRQC for the distribution of queues */
2238         mrqc = ixgbe_setup_mrqc(adapter);
2239
2240         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2241                 /* Fill out redirection table */
2242                 for (i = 0, j = 0; i < 128; i++, j++) {
2243                         if (j == adapter->ring_feature[RING_F_RSS].indices)
2244                                 j = 0;
2245                         /* reta = 4-byte sliding window of
2246                          * 0x00..(indices-1)(indices-1)00..etc. */
2247                         reta = (reta << 8) | (j * 0x11);
2248                         if ((i & 3) == 3)
2249                                 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2250                 }
2251
2252                 /* Fill out hash function seeds */
2253                 for (i = 0; i < 10; i++)
2254                         IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2255
2256                 if (hw->mac.type == ixgbe_mac_82598EB)
2257                         mrqc |= IXGBE_MRQC_RSSEN;
2258                     /* Perform hash on these packet types */
2259                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2260                       | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2261                       | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
2262                       | IXGBE_MRQC_RSS_FIELD_IPV6
2263                       | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
2264                       | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2265         }
2266         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2267
2268         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2269
2270         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
2271             adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
2272                 /* Disable indicating checksum in descriptor, enables
2273                  * RSS hash */
2274                 rxcsum |= IXGBE_RXCSUM_PCSD;
2275         }
2276         if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
2277                 /* Enable IPv4 payload checksum for UDP fragments
2278                  * if PCSD is not set */
2279                 rxcsum |= IXGBE_RXCSUM_IPPCSE;
2280         }
2281
2282         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2283
2284         if (hw->mac.type == ixgbe_mac_82599EB) {
2285                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2286                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
2287                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2288                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2289         }
2290
2291         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
2292                 /* Enable 82599 HW-RSC */
2293                 for (i = 0; i < adapter->num_rx_queues; i++)
2294                         ixgbe_configure_rscctl(adapter, i, rx_buf_len);
2295
2296                 /* Disable RSC for ACK packets */
2297                 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2298                    (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2299         }
2300 }
2301
2302 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2303 {
2304         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2305         struct ixgbe_hw *hw = &adapter->hw;
2306
2307         /* add VID to filter table */
2308         hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true);
2309 }
2310
2311 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2312 {
2313         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2314         struct ixgbe_hw *hw = &adapter->hw;
2315
2316         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2317                 ixgbe_irq_disable(adapter);
2318
2319         vlan_group_set_device(adapter->vlgrp, vid, NULL);
2320
2321         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2322                 ixgbe_irq_enable(adapter);
2323
2324         /* remove VID from filter table */
2325         hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false);
2326 }
2327
2328 static void ixgbe_vlan_rx_register(struct net_device *netdev,
2329                                    struct vlan_group *grp)
2330 {
2331         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2332         u32 ctrl;
2333         int i, j;
2334
2335         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2336                 ixgbe_irq_disable(adapter);
2337         adapter->vlgrp = grp;
2338
2339         /*
2340          * For a DCB driver, always enable VLAN tag stripping so we can
2341          * still receive traffic from a DCB-enabled host even if we're
2342          * not in DCB mode.
2343          */
2344         ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
2345         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2346                 ctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2347                 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2348                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2349         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2350                 ctrl |= IXGBE_VLNCTRL_VFE;
2351                 /* enable VLAN tag insert/strip */
2352                 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
2353                 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2354                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2355                 for (i = 0; i < adapter->num_rx_queues; i++) {
2356                         j = adapter->rx_ring[i].reg_idx;
2357                         ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j));
2358                         ctrl |= IXGBE_RXDCTL_VME;
2359                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl);
2360                 }
2361         }
2362         ixgbe_vlan_rx_add_vid(netdev, 0);
2363
2364         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2365                 ixgbe_irq_enable(adapter);
2366 }
2367
2368 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2369 {
2370         ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2371
2372         if (adapter->vlgrp) {
2373                 u16 vid;
2374                 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2375                         if (!vlan_group_get_device(adapter->vlgrp, vid))
2376                                 continue;
2377                         ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2378                 }
2379         }
2380 }
2381
2382 static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
2383 {
2384         struct dev_mc_list *mc_ptr;
2385         u8 *addr = *mc_addr_ptr;
2386         *vmdq = 0;
2387
2388         mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
2389         if (mc_ptr->next)
2390                 *mc_addr_ptr = mc_ptr->next->dmi_addr;
2391         else
2392                 *mc_addr_ptr = NULL;
2393
2394         return addr;
2395 }
2396
2397 /**
2398  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
2399  * @netdev: network interface device structure
2400  *
2401  * The set_rx_method entry point is called whenever the unicast/multicast
2402  * address list or the network interface flags are updated.  This routine is
2403  * responsible for configuring the hardware for proper unicast, multicast and
2404  * promiscuous mode.
2405  **/
2406 static void ixgbe_set_rx_mode(struct net_device *netdev)
2407 {
2408         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2409         struct ixgbe_hw *hw = &adapter->hw;
2410         u32 fctrl, vlnctrl;
2411         u8 *addr_list = NULL;
2412         int addr_count = 0;
2413
2414         /* Check for Promiscuous and All Multicast modes */
2415
2416         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2417         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2418
2419         if (netdev->flags & IFF_PROMISC) {
2420                 hw->addr_ctrl.user_set_promisc = 1;
2421                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2422                 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2423         } else {
2424                 if (netdev->flags & IFF_ALLMULTI) {
2425                         fctrl |= IXGBE_FCTRL_MPE;
2426                         fctrl &= ~IXGBE_FCTRL_UPE;
2427                 } else {
2428                         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2429                 }
2430                 vlnctrl |= IXGBE_VLNCTRL_VFE;
2431                 hw->addr_ctrl.user_set_promisc = 0;
2432         }
2433
2434         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2435         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2436
2437         /* reprogram secondary unicast list */
2438         hw->mac.ops.update_uc_addr_list(hw, &netdev->uc.list);
2439
2440         /* reprogram multicast list */
2441         addr_count = netdev->mc_count;
2442         if (addr_count)
2443                 addr_list = netdev->mc_list->dmi_addr;
2444         hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
2445                                         ixgbe_addr_list_itr);
2446 }
2447
2448 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2449 {
2450         int q_idx;
2451         struct ixgbe_q_vector *q_vector;
2452         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2453
2454         /* legacy and MSI only use one vector */
2455         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2456                 q_vectors = 1;
2457
2458         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2459                 struct napi_struct *napi;
2460                 q_vector = adapter->q_vector[q_idx];
2461                 napi = &q_vector->napi;
2462                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2463                         if (!q_vector->rxr_count || !q_vector->txr_count) {
2464                                 if (q_vector->txr_count == 1)
2465                                         napi->poll = &ixgbe_clean_txonly;
2466                                 else if (q_vector->rxr_count == 1)
2467                                         napi->poll = &ixgbe_clean_rxonly;
2468                         }
2469                 }
2470
2471                 napi_enable(napi);
2472         }
2473 }
2474
2475 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2476 {
2477         int q_idx;
2478         struct ixgbe_q_vector *q_vector;
2479         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2480
2481         /* legacy and MSI only use one vector */
2482         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2483                 q_vectors = 1;
2484
2485         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2486                 q_vector = adapter->q_vector[q_idx];
2487                 napi_disable(&q_vector->napi);
2488         }
2489 }
2490
2491 #ifdef CONFIG_IXGBE_DCB
2492 /*
2493  * ixgbe_configure_dcb - Configure DCB hardware
2494  * @adapter: ixgbe adapter struct
2495  *
2496  * This is called by the driver on open to configure the DCB hardware.
2497  * This is also called by the gennetlink interface when reconfiguring
2498  * the DCB state.
2499  */
2500 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2501 {
2502         struct ixgbe_hw *hw = &adapter->hw;
2503         u32 txdctl, vlnctrl;
2504         int i, j;
2505
2506         ixgbe_dcb_check_config(&adapter->dcb_cfg);
2507         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2508         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2509
2510         /* reconfigure the hardware */
2511         ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2512
2513         for (i = 0; i < adapter->num_tx_queues; i++) {
2514                 j = adapter->tx_ring[i].reg_idx;
2515                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2516                 /* PThresh workaround for Tx hang with DFP enabled. */
2517                 txdctl |= 32;
2518                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2519         }
2520         /* Enable VLAN tag insert/strip */
2521         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2522         if (hw->mac.type == ixgbe_mac_82598EB) {
2523                 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2524                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2525                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2526         } else if (hw->mac.type == ixgbe_mac_82599EB) {
2527                 vlnctrl |= IXGBE_VLNCTRL_VFE;
2528                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2529                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2530                 for (i = 0; i < adapter->num_rx_queues; i++) {
2531                         j = adapter->rx_ring[i].reg_idx;
2532                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2533                         vlnctrl |= IXGBE_RXDCTL_VME;
2534                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2535                 }
2536         }
2537         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2538 }
2539
2540 #endif
2541 static void ixgbe_configure(struct ixgbe_adapter *adapter)
2542 {
2543         struct net_device *netdev = adapter->netdev;
2544         struct ixgbe_hw *hw = &adapter->hw;
2545         int i;
2546
2547         ixgbe_set_rx_mode(netdev);
2548
2549         ixgbe_restore_vlan(adapter);
2550 #ifdef CONFIG_IXGBE_DCB
2551         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2552                 if (hw->mac.type == ixgbe_mac_82598EB)
2553                         netif_set_gso_max_size(netdev, 32768);
2554                 else
2555                         netif_set_gso_max_size(netdev, 65536);
2556                 ixgbe_configure_dcb(adapter);
2557         } else {
2558                 netif_set_gso_max_size(netdev, 65536);
2559         }
2560 #else
2561         netif_set_gso_max_size(netdev, 65536);
2562 #endif
2563
2564 #ifdef IXGBE_FCOE
2565         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2566                 ixgbe_configure_fcoe(adapter);
2567
2568 #endif /* IXGBE_FCOE */
2569         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2570                 for (i = 0; i < adapter->num_tx_queues; i++)
2571                         adapter->tx_ring[i].atr_sample_rate =
2572                                                        adapter->atr_sample_rate;
2573                 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
2574         } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
2575                 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
2576         }
2577
2578         ixgbe_configure_tx(adapter);
2579         ixgbe_configure_rx(adapter);
2580         for (i = 0; i < adapter->num_rx_queues; i++)
2581                 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
2582                                        (adapter->rx_ring[i].count - 1));
2583 }
2584
2585 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2586 {
2587         switch (hw->phy.type) {
2588         case ixgbe_phy_sfp_avago:
2589         case ixgbe_phy_sfp_ftl:
2590         case ixgbe_phy_sfp_intel:
2591         case ixgbe_phy_sfp_unknown:
2592         case ixgbe_phy_tw_tyco:
2593         case ixgbe_phy_tw_unknown:
2594                 return true;
2595         default:
2596                 return false;
2597         }
2598 }
2599
2600 /**
2601  * ixgbe_sfp_link_config - set up SFP+ link
2602  * @adapter: pointer to private adapter struct
2603  **/
2604 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2605 {
2606         struct ixgbe_hw *hw = &adapter->hw;
2607
2608                 if (hw->phy.multispeed_fiber) {
2609                         /*
2610                          * In multispeed fiber setups, the device may not have
2611                          * had a physical connection when the driver loaded.
2612                          * If that's the case, the initial link configuration
2613                          * couldn't get the MAC into 10G or 1G mode, so we'll
2614                          * never have a link status change interrupt fire.
2615                          * We need to try and force an autonegotiation
2616                          * session, then bring up link.
2617                          */
2618                         hw->mac.ops.setup_sfp(hw);
2619                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2620                                 schedule_work(&adapter->multispeed_fiber_task);
2621                 } else {
2622                         /*
2623                          * Direct Attach Cu and non-multispeed fiber modules
2624                          * still need to be configured properly prior to
2625                          * attempting link.
2626                          */
2627                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2628                                 schedule_work(&adapter->sfp_config_module_task);
2629                 }
2630 }
2631
2632 /**
2633  * ixgbe_non_sfp_link_config - set up non-SFP+ link
2634  * @hw: pointer to private hardware struct
2635  *
2636  * Returns 0 on success, negative on failure
2637  **/
2638 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
2639 {
2640         u32 autoneg;
2641         bool negotiation, link_up = false;
2642         u32 ret = IXGBE_ERR_LINK_SETUP;
2643
2644         if (hw->mac.ops.check_link)
2645                 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2646
2647         if (ret)
2648                 goto link_cfg_out;
2649
2650         if (hw->mac.ops.get_link_capabilities)
2651                 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
2652         if (ret)
2653                 goto link_cfg_out;
2654
2655         if (hw->mac.ops.setup_link)
2656                 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
2657 link_cfg_out:
2658         return ret;
2659 }
2660
2661 #define IXGBE_MAX_RX_DESC_POLL 10
2662 static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2663                                               int rxr)
2664 {
2665         int j = adapter->rx_ring[rxr].reg_idx;
2666         int k;
2667
2668         for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2669                 if (IXGBE_READ_REG(&adapter->hw,
2670                                    IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2671                         break;
2672                 else
2673                         msleep(1);
2674         }
2675         if (k >= IXGBE_MAX_RX_DESC_POLL) {
2676                 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2677                         "not set within the polling period\n", rxr);
2678         }
2679         ixgbe_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr],
2680                               (adapter->rx_ring[rxr].count - 1));
2681 }
2682
2683 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2684 {
2685         struct net_device *netdev = adapter->netdev;
2686         struct ixgbe_hw *hw = &adapter->hw;
2687         int i, j = 0;
2688         int num_rx_rings = adapter->num_rx_queues;
2689         int err;
2690         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2691         u32 txdctl, rxdctl, mhadd;
2692         u32 dmatxctl;
2693         u32 gpie;
2694
2695         ixgbe_get_hw_control(adapter);
2696
2697         if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2698             (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
2699                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2700                         gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
2701                                 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
2702                 } else {
2703                         /* MSI only */
2704                         gpie = 0;
2705                 }
2706                 /* XXX: to interrupt immediately for EICS writes, enable this */
2707                 /* gpie |= IXGBE_GPIE_EIMEN; */
2708                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2709         }
2710
2711         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2712                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2713                  * specifically only auto mask tx and rx interrupts */
2714                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2715         }
2716
2717         /* Enable fan failure interrupt if media type is copper */
2718         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2719                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2720                 gpie |= IXGBE_SDP1_GPIEN;
2721                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2722         }
2723
2724         if (hw->mac.type == ixgbe_mac_82599EB) {
2725                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2726                 gpie |= IXGBE_SDP1_GPIEN;
2727                 gpie |= IXGBE_SDP2_GPIEN;
2728                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2729         }
2730
2731 #ifdef IXGBE_FCOE
2732         /* adjust max frame to be able to do baby jumbo for FCoE */
2733         if ((netdev->features & NETIF_F_FCOE_MTU) &&
2734             (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2735                 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2736
2737 #endif /* IXGBE_FCOE */
2738         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2739         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2740                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2741                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2742
2743                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2744         }
2745
2746         for (i = 0; i < adapter->num_tx_queues; i++) {
2747                 j = adapter->tx_ring[i].reg_idx;
2748                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2749                 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2750                 txdctl |= (8 << 16);
2751                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2752         }
2753
2754         if (hw->mac.type == ixgbe_mac_82599EB) {
2755                 /* DMATXCTL.EN must be set after all Tx queue config is done */
2756                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2757                 dmatxctl |= IXGBE_DMATXCTL_TE;
2758                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2759         }
2760         for (i = 0; i < adapter->num_tx_queues; i++) {
2761                 j = adapter->tx_ring[i].reg_idx;
2762                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2763                 txdctl |= IXGBE_TXDCTL_ENABLE;
2764                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2765         }
2766
2767         for (i = 0; i < num_rx_rings; i++) {
2768                 j = adapter->rx_ring[i].reg_idx;
2769                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2770                 /* enable PTHRESH=32 descriptors (half the internal cache)
2771                  * and HTHRESH=0 descriptors (to minimize latency on fetch),
2772                  * this also removes a pesky rx_no_buffer_count increment */
2773                 rxdctl |= 0x0020;
2774                 rxdctl |= IXGBE_RXDCTL_ENABLE;
2775                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
2776                 if (hw->mac.type == ixgbe_mac_82599EB)
2777                         ixgbe_rx_desc_queue_enable(adapter, i);
2778         }
2779         /* enable all receives */
2780         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2781         if (hw->mac.type == ixgbe_mac_82598EB)
2782                 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2783         else
2784                 rxdctl |= IXGBE_RXCTRL_RXEN;
2785         hw->mac.ops.enable_rx_dma(hw, rxdctl);
2786
2787         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2788                 ixgbe_configure_msix(adapter);
2789         else
2790                 ixgbe_configure_msi_and_legacy(adapter);
2791
2792         clear_bit(__IXGBE_DOWN, &adapter->state);
2793         ixgbe_napi_enable_all(adapter);
2794
2795         /* clear any pending interrupts, may auto mask */
2796         IXGBE_READ_REG(hw, IXGBE_EICR);
2797
2798         ixgbe_irq_enable(adapter);
2799
2800         /*
2801          * If this adapter has a fan, check to see if we had a failure
2802          * before we enabled the interrupt.
2803          */
2804         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2805                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2806                 if (esdp & IXGBE_ESDP_SDP1)
2807                         DPRINTK(DRV, CRIT,
2808                                 "Fan has stopped, replace the adapter\n");
2809         }
2810
2811         /*
2812          * For hot-pluggable SFP+ devices, a new SFP+ module may have
2813          * arrived before interrupts were enabled but after probe.  Such
2814          * devices wouldn't have their type identified yet. We need to
2815          * kick off the SFP+ module setup first, then try to bring up link.
2816          * If we're not hot-pluggable SFP+, we just need to configure link
2817          * and bring it up.
2818          */
2819         if (hw->phy.type == ixgbe_phy_unknown) {
2820                 err = hw->phy.ops.identify(hw);
2821                 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
2822                         /*
2823                          * Take the device down and schedule the sfp tasklet
2824                          * which will unregister_netdev and log it.
2825                          */
2826                         ixgbe_down(adapter);
2827                         schedule_work(&adapter->sfp_config_module_task);
2828                         return err;
2829                 }
2830         }
2831
2832         if (ixgbe_is_sfp(hw)) {
2833                 ixgbe_sfp_link_config(adapter);
2834         } else {
2835                 err = ixgbe_non_sfp_link_config(hw);
2836                 if (err)
2837                         DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
2838         }
2839
2840         for (i = 0; i < adapter->num_tx_queues; i++)
2841                 set_bit(__IXGBE_FDIR_INIT_DONE,
2842                         &(adapter->tx_ring[i].reinit_state));
2843
2844         /* enable transmits */
2845         netif_tx_start_all_queues(netdev);
2846
2847         /* bring the link up in the watchdog, this could race with our first
2848          * link up interrupt but shouldn't be a problem */
2849         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2850         adapter->link_check_timeout = jiffies;
2851         mod_timer(&adapter->watchdog_timer, jiffies);
2852         return 0;
2853 }
2854
2855 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
2856 {
2857         WARN_ON(in_interrupt());
2858         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
2859                 msleep(1);
2860         ixgbe_down(adapter);
2861         ixgbe_up(adapter);
2862         clear_bit(__IXGBE_RESETTING, &adapter->state);
2863 }
2864
2865 int ixgbe_up(struct ixgbe_adapter *adapter)
2866 {
2867         /* hardware has been reset, we need to reload some things */
2868         ixgbe_configure(adapter);
2869
2870         return ixgbe_up_complete(adapter);
2871 }
2872
2873 void ixgbe_reset(struct ixgbe_adapter *adapter)
2874 {
2875         struct ixgbe_hw *hw = &adapter->hw;
2876         int err;
2877
2878         err = hw->mac.ops.init_hw(hw);
2879         switch (err) {
2880         case 0:
2881         case IXGBE_ERR_SFP_NOT_PRESENT:
2882                 break;
2883         case IXGBE_ERR_MASTER_REQUESTS_PENDING:
2884                 dev_err(&adapter->pdev->dev, "master disable timed out\n");
2885                 break;
2886         case IXGBE_ERR_EEPROM_VERSION:
2887                 /* We are running on a pre-production device, log a warning */
2888                 dev_warn(&adapter->pdev->dev, "This device is a pre-production "
2889                          "adapter/LOM.  Please be aware there may be issues "
2890                          "associated with your hardware.  If you are "
2891                          "experiencing problems please contact your Intel or "
2892                          "hardware representative who provided you with this "
2893                          "hardware.\n");
2894                 break;
2895         default:
2896                 dev_err(&adapter->pdev->dev, "Hardware Error: %d\n", err);
2897         }
2898
2899         /* reprogram the RAR[0] in case user changed it. */
2900         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2901 }
2902
2903 /**
2904  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2905  * @adapter: board private structure
2906  * @rx_ring: ring to free buffers from
2907  **/
2908 static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
2909                                 struct ixgbe_ring *rx_ring)
2910 {
2911         struct pci_dev *pdev = adapter->pdev;
2912         unsigned long size;
2913         unsigned int i;
2914
2915         /* Free all the Rx ring sk_buffs */
2916
2917         for (i = 0; i < rx_ring->count; i++) {
2918                 struct ixgbe_rx_buffer *rx_buffer_info;
2919
2920                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
2921                 if (rx_buffer_info->dma) {
2922                         pci_unmap_single(pdev, rx_buffer_info->dma,
2923                                          rx_ring->rx_buf_len,
2924                                          PCI_DMA_FROMDEVICE);
2925                         rx_buffer_info->dma = 0;
2926                 }
2927                 if (rx_buffer_info->skb) {
2928                         struct sk_buff *skb = rx_buffer_info->skb;
2929                         rx_buffer_info->skb = NULL;
2930                         do {
2931                                 struct sk_buff *this = skb;
2932                                 skb = skb->prev;
2933                                 dev_kfree_skb(this);
2934                         } while (skb);
2935                 }
2936                 if (!rx_buffer_info->page)
2937                         continue;
2938                 if (rx_buffer_info->page_dma) {
2939                         pci_unmap_page(pdev, rx_buffer_info->page_dma,
2940                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
2941                         rx_buffer_info->page_dma = 0;
2942                 }
2943                 put_page(rx_buffer_info->page);
2944                 rx_buffer_info->page = NULL;
2945                 rx_buffer_info->page_offset = 0;
2946         }
2947
2948         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2949         memset(rx_ring->rx_buffer_info, 0, size);
2950
2951         /* Zero out the descriptor ring */
2952         memset(rx_ring->desc, 0, rx_ring->size);
2953
2954         rx_ring->next_to_clean = 0;
2955         rx_ring->next_to_use = 0;
2956
2957         if (rx_ring->head)
2958                 writel(0, adapter->hw.hw_addr + rx_ring->head);
2959         if (rx_ring->tail)
2960                 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2961 }
2962
2963 /**
2964  * ixgbe_clean_tx_ring - Free Tx Buffers
2965  * @adapter: board private structure
2966  * @tx_ring: ring to be cleaned
2967  **/
2968 static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
2969                                 struct ixgbe_ring *tx_ring)
2970 {
2971         struct ixgbe_tx_buffer *tx_buffer_info;
2972         unsigned long size;
2973         unsigned int i;
2974
2975         /* Free all the Tx ring sk_buffs */
2976
2977         for (i = 0; i < tx_ring->count; i++) {
2978                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2979                 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2980         }
2981
2982         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2983         memset(tx_ring->tx_buffer_info, 0, size);
2984
2985         /* Zero out the descriptor ring */
2986         memset(tx_ring->desc, 0, tx_ring->size);
2987
2988         tx_ring->next_to_use = 0;
2989         tx_ring->next_to_clean = 0;
2990
2991         if (tx_ring->head)
2992                 writel(0, adapter->hw.hw_addr + tx_ring->head);
2993         if (tx_ring->tail)
2994                 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2995 }
2996
2997 /**
2998  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
2999  * @adapter: board private structure
3000  **/
3001 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
3002 {
3003         int i;
3004
3005         for (i = 0; i < adapter->num_rx_queues; i++)
3006                 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
3007 }
3008
3009 /**
3010  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
3011  * @adapter: board private structure
3012  **/
3013 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
3014 {
3015         int i;
3016
3017         for (i = 0; i < adapter->num_tx_queues; i++)
3018                 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
3019 }
3020
3021 void ixgbe_down(struct ixgbe_adapter *adapter)
3022 {
3023         struct net_device *netdev = adapter->netdev;
3024         struct ixgbe_hw *hw = &adapter->hw;
3025         u32 rxctrl;
3026         u32 txdctl;
3027         int i, j;
3028
3029         /* signal that we are down to the interrupt handler */
3030         set_bit(__IXGBE_DOWN, &adapter->state);
3031
3032         /* disable receives */
3033         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3034         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3035
3036         netif_tx_disable(netdev);
3037
3038         IXGBE_WRITE_FLUSH(hw);
3039         msleep(10);
3040
3041         netif_tx_stop_all_queues(netdev);
3042
3043         ixgbe_irq_disable(adapter);
3044
3045         ixgbe_napi_disable_all(adapter);
3046
3047         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3048         del_timer_sync(&adapter->sfp_timer);
3049         del_timer_sync(&adapter->watchdog_timer);
3050         cancel_work_sync(&adapter->watchdog_task);
3051
3052         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3053             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3054                 cancel_work_sync(&adapter->fdir_reinit_task);
3055
3056         /* disable transmits in the hardware now that interrupts are off */
3057         for (i = 0; i < adapter->num_tx_queues; i++) {
3058                 j = adapter->tx_ring[i].reg_idx;
3059                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3060                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
3061                                 (txdctl & ~IXGBE_TXDCTL_ENABLE));
3062         }
3063         /* Disable the Tx DMA engine on 82599 */
3064         if (hw->mac.type == ixgbe_mac_82599EB)
3065                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
3066                                 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3067                                  ~IXGBE_DMATXCTL_TE));
3068
3069         netif_carrier_off(netdev);
3070
3071         if (!pci_channel_offline(adapter->pdev))
3072                 ixgbe_reset(adapter);
3073         ixgbe_clean_all_tx_rings(adapter);
3074         ixgbe_clean_all_rx_rings(adapter);
3075
3076 #ifdef CONFIG_IXGBE_DCA
3077         /* since we reset the hardware DCA settings were cleared */
3078         ixgbe_setup_dca(adapter);
3079 #endif
3080 }
3081
3082 /**
3083  * ixgbe_poll - NAPI Rx polling callback
3084  * @napi: structure for representing this polling device
3085  * @budget: how many packets driver is allowed to clean
3086  *
3087  * This function is used for legacy and MSI, NAPI mode
3088  **/
3089 static int ixgbe_poll(struct napi_struct *napi, int budget)
3090 {
3091         struct ixgbe_q_vector *q_vector =
3092                                 container_of(napi, struct ixgbe_q_vector, napi);
3093         struct ixgbe_adapter *adapter = q_vector->adapter;
3094         int tx_clean_complete, work_done = 0;
3095
3096 #ifdef CONFIG_IXGBE_DCA
3097         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
3098                 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
3099                 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
3100         }
3101 #endif
3102
3103         tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring);
3104         ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget);
3105
3106         if (!tx_clean_complete)
3107                 work_done = budget;
3108
3109         /* If budget not fully consumed, exit the polling mode */
3110         if (work_done < budget) {
3111                 napi_complete(napi);
3112                 if (adapter->rx_itr_setting & 1)
3113                         ixgbe_set_itr(adapter);
3114                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3115                         ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
3116         }
3117         return work_done;
3118 }
3119
3120 /**
3121  * ixgbe_tx_timeout - Respond to a Tx Hang
3122  * @netdev: network interface device structure
3123  **/
3124 static void ixgbe_tx_timeout(struct net_device *netdev)
3125 {
3126         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3127
3128         /* Do the reset outside of interrupt context */
3129         schedule_work(&adapter->reset_task);
3130 }
3131
3132 static void ixgbe_reset_task(struct work_struct *work)
3133 {
3134         struct ixgbe_adapter *adapter;
3135         adapter = container_of(work, struct ixgbe_adapter, reset_task);
3136
3137         /* If we're already down or resetting, just bail */
3138         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3139             test_bit(__IXGBE_RESETTING, &adapter->state))
3140                 return;
3141
3142         adapter->tx_timeout_count++;
3143
3144         ixgbe_reinit_locked(adapter);
3145 }
3146
3147 #ifdef CONFIG_IXGBE_DCB
3148 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
3149 {
3150         bool ret = false;
3151         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
3152
3153         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3154                 return ret;
3155
3156         f->mask = 0x7 << 3;
3157         adapter->num_rx_queues = f->indices;
3158         adapter->num_tx_queues = f->indices;
3159         ret = true;
3160
3161         return ret;
3162 }
3163 #endif
3164
3165 /**
3166  * ixgbe_set_rss_queues: Allocate queues for RSS
3167  * @adapter: board private structure to initialize
3168  *
3169  * This is our "base" multiqueue mode.  RSS (Receive Side Scaling) will try
3170  * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3171  *
3172  **/
3173 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3174 {
3175         bool ret = false;
3176         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
3177
3178         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3179                 f->mask = 0xF;
3180                 adapter->num_rx_queues = f->indices;
3181                 adapter->num_tx_queues = f->indices;
3182                 ret = true;
3183         } else {
3184                 ret = false;
3185         }
3186
3187         return ret;
3188 }
3189
3190 /**
3191  * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3192  * @adapter: board private structure to initialize
3193  *
3194  * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3195  * to the original CPU that initiated the Tx session.  This runs in addition
3196  * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3197  * Rx load across CPUs using RSS.
3198  *
3199  **/
3200 static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
3201 {
3202         bool ret = false;
3203         struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
3204
3205         f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
3206         f_fdir->mask = 0;
3207
3208         /* Flow Director must have RSS enabled */
3209         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3210             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3211              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
3212                 adapter->num_tx_queues = f_fdir->indices;
3213                 adapter->num_rx_queues = f_fdir->indices;
3214                 ret = true;
3215         } else {
3216                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3217                 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3218         }
3219         return ret;
3220 }
3221
3222 #ifdef IXGBE_FCOE
3223 /**
3224  * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3225  * @adapter: board private structure to initialize
3226  *
3227  * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3228  * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3229  * rx queues out of the max number of rx queues, instead, it is used as the
3230  * index of the first rx queue used by FCoE.
3231  *
3232  **/
3233 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
3234 {
3235         bool ret = false;
3236         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3237
3238         f->indices = min((int)num_online_cpus(), f->indices);
3239         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3240                 adapter->num_rx_queues = 1;
3241                 adapter->num_tx_queues = 1;
3242 #ifdef CONFIG_IXGBE_DCB
3243                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3244                         DPRINTK(PROBE, INFO, "FCoE enabled with DCB \n");
3245                         ixgbe_set_dcb_queues(adapter);
3246                 }
3247 #endif
3248                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3249                         DPRINTK(PROBE, INFO, "FCoE enabled with RSS \n");
3250                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3251                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3252                                 ixgbe_set_fdir_queues(adapter);
3253                         else
3254                                 ixgbe_set_rss_queues(adapter);
3255                 }
3256                 /* adding FCoE rx rings to the end */
3257                 f->mask = adapter->num_rx_queues;
3258                 adapter->num_rx_queues += f->indices;
3259                 adapter->num_tx_queues += f->indices;
3260
3261                 ret = true;
3262         }
3263
3264         return ret;
3265 }
3266
3267 #endif /* IXGBE_FCOE */
3268 /*
3269  * ixgbe_set_num_queues: Allocate queues for device, feature dependant
3270  * @adapter: board private structure to initialize
3271  *
3272  * This is the top level queue allocation routine.  The order here is very
3273  * important, starting with the "most" number of features turned on at once,
3274  * and ending with the smallest set of features.  This way large combinations
3275  * can be allocated if they're turned on, and smaller combinations are the
3276  * fallthrough conditions.
3277  *
3278  **/
3279 static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
3280 {
3281 #ifdef IXGBE_FCOE
3282         if (ixgbe_set_fcoe_queues(adapter))
3283                 goto done;
3284
3285 #endif /* IXGBE_FCOE */
3286 #ifdef CONFIG_IXGBE_DCB
3287         if (ixgbe_set_dcb_queues(adapter))
3288                 goto done;
3289
3290 #endif
3291         if (ixgbe_set_fdir_queues(adapter))
3292                 goto done;
3293
3294         if (ixgbe_set_rss_queues(adapter))
3295                 goto done;
3296
3297         /* fallback to base case */
3298         adapter->num_rx_queues = 1;
3299         adapter->num_tx_queues = 1;
3300
3301 done:
3302         /* Notify the stack of the (possibly) reduced Tx Queue count. */
3303         adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
3304 }
3305
3306 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
3307                                        int vectors)
3308 {
3309         int err, vector_threshold;
3310
3311         /* We'll want at least 3 (vector_threshold):
3312          * 1) TxQ[0] Cleanup
3313          * 2) RxQ[0] Cleanup
3314          * 3) Other (Link Status Change, etc.)
3315          * 4) TCP Timer (optional)
3316          */
3317         vector_threshold = MIN_MSIX_COUNT;
3318
3319         /* The more we get, the more we will assign to Tx/Rx Cleanup
3320          * for the separate queues...where Rx Cleanup >= Tx Cleanup.
3321          * Right now, we simply care about how many we'll get; we'll
3322          * set them up later while requesting irq's.
3323          */
3324         while (vectors >= vector_threshold) {
3325                 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
3326                                       vectors);
3327                 if (!err) /* Success in acquiring all requested vectors. */
3328                         break;
3329                 else if (err < 0)
3330                         vectors = 0; /* Nasty failure, quit now */
3331                 else /* err == number of vectors we should try again with */
3332                         vectors = err;
3333         }
3334
3335         if (vectors < vector_threshold) {
3336                 /* Can't allocate enough MSI-X interrupts?  Oh well.
3337                  * This just means we'll go with either a single MSI
3338                  * vector or fall back to legacy interrupts.
3339                  */
3340                 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
3341                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3342                 kfree(adapter->msix_entries);
3343                 adapter->msix_entries = NULL;
3344         } else {
3345                 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
3346                 /*
3347                  * Adjust for only the vectors we'll use, which is minimum
3348                  * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
3349                  * vectors we were allocated.
3350                  */
3351                 adapter->num_msix_vectors = min(vectors,
3352                                    adapter->max_msix_q_vectors + NON_Q_VECTORS);
3353         }
3354 }
3355
3356 /**
3357  * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
3358  * @adapter: board private structure to initialize
3359  *
3360  * Cache the descriptor ring offsets for RSS to the assigned rings.
3361  *
3362  **/
3363 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
3364 {
3365         int i;
3366         bool ret = false;
3367
3368         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3369                 for (i = 0; i < adapter->num_rx_queues; i++)
3370                         adapter->rx_ring[i].reg_idx = i;
3371                 for (i = 0; i < adapter->num_tx_queues; i++)
3372                         adapter->tx_ring[i].reg_idx = i;
3373                 ret = true;
3374         } else {
3375                 ret = false;
3376         }
3377
3378         return ret;
3379 }
3380
3381 #ifdef CONFIG_IXGBE_DCB
3382 /**
3383  * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
3384  * @adapter: board private structure to initialize
3385  *
3386  * Cache the descriptor ring offsets for DCB to the assigned rings.
3387  *
3388  **/
3389 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
3390 {
3391         int i;
3392         bool ret = false;
3393         int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
3394
3395         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3396                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3397                         /* the number of queues is assumed to be symmetric */
3398                         for (i = 0; i < dcb_i; i++) {
3399                                 adapter->rx_ring[i].reg_idx = i << 3;
3400                                 adapter->tx_ring[i].reg_idx = i << 2;
3401                         }
3402                         ret = true;
3403                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
3404                         if (dcb_i == 8) {
3405                                 /*
3406                                  * Tx TC0 starts at: descriptor queue 0
3407                                  * Tx TC1 starts at: descriptor queue 32
3408                                  * Tx TC2 starts at: descriptor queue 64
3409                                  * Tx TC3 starts at: descriptor queue 80
3410                                  * Tx TC4 starts at: descriptor queue 96
3411                                  * Tx TC5 starts at: descriptor queue 104
3412                                  * Tx TC6 starts at: descriptor queue 112
3413                                  * Tx TC7 starts at: descriptor queue 120
3414                                  *
3415                                  * Rx TC0-TC7 are offset by 16 queues each
3416                                  */
3417                                 for (i = 0; i < 3; i++) {
3418                                         adapter->tx_ring[i].reg_idx = i << 5;
3419                                         adapter->rx_ring[i].reg_idx = i << 4;
3420                                 }
3421                                 for ( ; i < 5; i++) {
3422                                         adapter->tx_ring[i].reg_idx =
3423                                                                  ((i + 2) << 4);
3424                                         adapter->rx_ring[i].reg_idx = i << 4;
3425                                 }
3426                                 for ( ; i < dcb_i; i++) {
3427                                         adapter->tx_ring[i].reg_idx =
3428                                                                  ((i + 8) << 3);
3429                                         adapter->rx_ring[i].reg_idx = i << 4;
3430                                 }
3431
3432                                 ret = true;
3433                         } else if (dcb_i == 4) {
3434                                 /*
3435                                  * Tx TC0 starts at: descriptor queue 0
3436                                  * Tx TC1 starts at: descriptor queue 64
3437                                  * Tx TC2 starts at: descriptor queue 96
3438                                  * Tx TC3 starts at: descriptor queue 112
3439                                  *
3440                                  * Rx TC0-TC3 are offset by 32 queues each
3441                                  */
3442                                 adapter->tx_ring[0].reg_idx = 0;
3443                                 adapter->tx_ring[1].reg_idx = 64;
3444                                 adapter->tx_ring[2].reg_idx = 96;
3445                                 adapter->tx_ring[3].reg_idx = 112;
3446                                 for (i = 0 ; i < dcb_i; i++)
3447                                         adapter->rx_ring[i].reg_idx = i << 5;
3448
3449                                 ret = true;
3450                         } else {
3451                                 ret = false;
3452                         }
3453                 } else {
3454                         ret = false;
3455                 }
3456         } else {
3457                 ret = false;
3458         }
3459
3460         return ret;
3461 }
3462 #endif
3463
3464 /**
3465  * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
3466  * @adapter: board private structure to initialize
3467  *
3468  * Cache the descriptor ring offsets for Flow Director to the assigned rings.
3469  *
3470  **/
3471 static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
3472 {
3473         int i;
3474         bool ret = false;
3475
3476         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3477             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3478              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
3479                 for (i = 0; i < adapter->num_rx_queues; i++)
3480                         adapter->rx_ring[i].reg_idx = i;
3481                 for (i = 0; i < adapter->num_tx_queues; i++)
3482                         adapter->tx_ring[i].reg_idx = i;
3483                 ret = true;
3484         }
3485
3486         return ret;
3487 }
3488
3489 #ifdef IXGBE_FCOE
3490 /**
3491  * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
3492  * @adapter: board private structure to initialize
3493  *
3494  * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
3495  *
3496  */
3497 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
3498 {
3499         int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
3500         bool ret = false;
3501         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3502
3503         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3504 #ifdef CONFIG_IXGBE_DCB
3505                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3506                         struct ixgbe_fcoe *fcoe = &adapter->fcoe;
3507
3508                         ixgbe_cache_ring_dcb(adapter);
3509                         /* find out queues in TC for FCoE */
3510                         fcoe_rx_i = adapter->rx_ring[fcoe->tc].reg_idx + 1;
3511                         fcoe_tx_i = adapter->tx_ring[fcoe->tc].reg_idx + 1;
3512                         /*
3513                          * In 82599, the number of Tx queues for each traffic
3514                          * class for both 8-TC and 4-TC modes are:
3515                          * TCs  : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
3516                          * 8 TCs:  32  32  16  16   8   8   8   8
3517                          * 4 TCs:  64  64  32  32
3518                          * We have max 8 queues for FCoE, where 8 the is
3519                          * FCoE redirection table size. If TC for FCoE is
3520                          * less than or equal to TC3, we have enough queues
3521                          * to add max of 8 queues for FCoE, so we start FCoE
3522                          * tx descriptor from the next one, i.e., reg_idx + 1.
3523                          * If TC for FCoE is above TC3, implying 8 TC mode,
3524                          * and we need 8 for FCoE, we have to take all queues
3525                          * in that traffic class for FCoE.
3526                          */
3527                         if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
3528                                 fcoe_tx_i--;
3529                 }
3530 #endif /* CONFIG_IXGBE_DCB */
3531                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3532                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3533                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3534                                 ixgbe_cache_ring_fdir(adapter);
3535                         else
3536                                 ixgbe_cache_ring_rss(adapter);
3537
3538                         fcoe_rx_i = f->mask;
3539                         fcoe_tx_i = f->mask;
3540                 }
3541                 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
3542                         adapter->rx_ring[f->mask + i].reg_idx = fcoe_rx_i;
3543                         adapter->tx_ring[f->mask + i].reg_idx = fcoe_tx_i;
3544                 }
3545                 ret = true;
3546         }
3547         return ret;
3548 }
3549
3550 #endif /* IXGBE_FCOE */
3551 /**
3552  * ixgbe_cache_ring_register - Descriptor ring to register mapping
3553  * @adapter: board private structure to initialize
3554  *
3555  * Once we know the feature-set enabled for the device, we'll cache
3556  * the register offset the descriptor ring is assigned to.
3557  *
3558  * Note, the order the various feature calls is important.  It must start with
3559  * the "most" features enabled at the same time, then trickle down to the
3560  * least amount of features turned on at once.
3561  **/
3562 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
3563 {
3564         /* start with default case */
3565         adapter->rx_ring[0].reg_idx = 0;
3566         adapter->tx_ring[0].reg_idx = 0;
3567
3568 #ifdef IXGBE_FCOE
3569         if (ixgbe_cache_ring_fcoe(adapter))
3570                 return;
3571
3572 #endif /* IXGBE_FCOE */
3573 #ifdef CONFIG_IXGBE_DCB
3574         if (ixgbe_cache_ring_dcb(adapter))
3575                 return;
3576
3577 #endif
3578         if (ixgbe_cache_ring_fdir(adapter))
3579                 return;
3580
3581         if (ixgbe_cache_ring_rss(adapter))
3582                 return;
3583 }
3584
3585 /**
3586  * ixgbe_alloc_queues - Allocate memory for all rings
3587  * @adapter: board private structure to initialize
3588  *
3589  * We allocate one ring per queue at run-time since we don't know the
3590  * number of queues at compile-time.  The polling_netdev array is
3591  * intended for Multiqueue, but should work fine with a single queue.
3592  **/
3593 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
3594 {
3595         int i;
3596
3597         adapter->tx_ring = kcalloc(adapter->num_tx_queues,
3598                                    sizeof(struct ixgbe_ring), GFP_KERNEL);
3599         if (!adapter->tx_ring)
3600                 goto err_tx_ring_allocation;
3601
3602         adapter->rx_ring = kcalloc(adapter->num_rx_queues,
3603                                    sizeof(struct ixgbe_ring), GFP_KERNEL);
3604         if (!adapter->rx_ring)
3605                 goto err_rx_ring_allocation;
3606
3607         for (i = 0; i < adapter->num_tx_queues; i++) {
3608                 adapter->tx_ring[i].count = adapter->tx_ring_count;
3609                 adapter->tx_ring[i].queue_index = i;
3610         }
3611
3612         for (i = 0; i < adapter->num_rx_queues; i++) {
3613                 adapter->rx_ring[i].count = adapter->rx_ring_count;
3614                 adapter->rx_ring[i].queue_index = i;
3615         }
3616
3617         ixgbe_cache_ring_register(adapter);
3618
3619         return 0;
3620
3621 err_rx_ring_allocation:
3622         kfree(adapter->tx_ring);
3623 err_tx_ring_allocation:
3624         return -ENOMEM;
3625 }
3626
3627 /**
3628  * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
3629  * @adapter: board private structure to initialize
3630  *
3631  * Attempt to configure the interrupts using the best available
3632  * capabilities of the hardware and the kernel.
3633  **/
3634 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
3635 {
3636         struct ixgbe_hw *hw = &adapter->hw;
3637         int err = 0;
3638         int vector, v_budget;
3639
3640         /*
3641          * It's easy to be greedy for MSI-X vectors, but it really
3642          * doesn't do us much good if we have a lot more vectors
3643          * than CPU's.  So let's be conservative and only ask for
3644          * (roughly) twice the number of vectors as there are CPU's.
3645          */
3646         v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
3647                        (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
3648
3649         /*
3650          * At the same time, hardware can only support a maximum of
3651          * hw.mac->max_msix_vectors vectors.  With features
3652          * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
3653          * descriptor queues supported by our device.  Thus, we cap it off in
3654          * those rare cases where the cpu count also exceeds our vector limit.
3655          */
3656         v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
3657
3658         /* A failure in MSI-X entry allocation isn't fatal, but it does
3659          * mean we disable MSI-X capabilities of the adapter. */
3660         adapter->msix_entries = kcalloc(v_budget,
3661                                         sizeof(struct msix_entry), GFP_KERNEL);
3662         if (adapter->msix_entries) {
3663                 for (vector = 0; vector < v_budget; vector++)
3664                         adapter->msix_entries[vector].entry = vector;
3665
3666                 ixgbe_acquire_msix_vectors(adapter, v_budget);
3667
3668                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3669                         goto out;
3670         }
3671
3672         adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
3673         adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
3674         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3675         adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3676         adapter->atr_sample_rate = 0;
3677         ixgbe_set_num_queues(adapter);
3678
3679         err = pci_enable_msi(adapter->pdev);
3680         if (!err) {
3681                 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
3682         } else {
3683                 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
3684                         "falling back to legacy.  Error: %d\n", err);
3685                 /* reset err */
3686                 err = 0;
3687         }
3688
3689 out:
3690         return err;
3691 }
3692
3693 /**
3694  * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
3695  * @adapter: board private structure to initialize
3696  *
3697  * We allocate one q_vector per queue interrupt.  If allocation fails we
3698  * return -ENOMEM.
3699  **/
3700 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
3701 {
3702         int q_idx, num_q_vectors;
3703         struct ixgbe_q_vector *q_vector;
3704         int napi_vectors;
3705         int (*poll)(struct napi_struct *, int);
3706
3707         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3708                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3709                 napi_vectors = adapter->num_rx_queues;
3710                 poll = &ixgbe_clean_rxtx_many;
3711         } else {
3712                 num_q_vectors = 1;
3713                 napi_vectors = 1;
3714                 poll = &ixgbe_poll;
3715         }
3716
3717         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3718                 q_vector = kzalloc(sizeof(struct ixgbe_q_vector), GFP_KERNEL);
3719                 if (!q_vector)
3720                         goto err_out;
3721                 q_vector->adapter = adapter;
3722                 if (q_vector->txr_count && !q_vector->rxr_count)
3723                         q_vector->eitr = adapter->tx_eitr_param;
3724                 else
3725                         q_vector->eitr = adapter->rx_eitr_param;
3726                 q_vector->v_idx = q_idx;
3727                 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
3728                 adapter->q_vector[q_idx] = q_vector;
3729         }
3730
3731         return 0;
3732
3733 err_out:
3734         while (q_idx) {
3735                 q_idx--;
3736                 q_vector = adapter->q_vector[q_idx];
3737                 netif_napi_del(&q_vector->napi);
3738                 kfree(q_vector);
3739                 adapter->q_vector[q_idx] = NULL;
3740         }
3741         return -ENOMEM;
3742 }
3743
3744 /**
3745  * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
3746  * @adapter: board private structure to initialize
3747  *
3748  * This function frees the memory allocated to the q_vectors.  In addition if
3749  * NAPI is enabled it will delete any references to the NAPI struct prior
3750  * to freeing the q_vector.
3751  **/
3752 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
3753 {
3754         int q_idx, num_q_vectors;
3755
3756         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3757                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3758         else
3759                 num_q_vectors = 1;
3760
3761         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3762                 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
3763                 adapter->q_vector[q_idx] = NULL;
3764                 netif_napi_del(&q_vector->napi);
3765                 kfree(q_vector);
3766         }
3767 }
3768
3769 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
3770 {
3771         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3772                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3773                 pci_disable_msix(adapter->pdev);
3774                 kfree(adapter->msix_entries);
3775                 adapter->msix_entries = NULL;
3776         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
3777                 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
3778                 pci_disable_msi(adapter->pdev);
3779         }
3780         return;
3781 }
3782
3783 /**
3784  * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
3785  * @adapter: board private structure to initialize
3786  *
3787  * We determine which interrupt scheme to use based on...
3788  * - Kernel support (MSI, MSI-X)
3789  *   - which can be user-defined (via MODULE_PARAM)
3790  * - Hardware queue count (num_*_queues)
3791  *   - defined by miscellaneous hardware support/features (RSS, etc.)
3792  **/
3793 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
3794 {
3795         int err;
3796
3797         /* Number of supported queues */
3798         ixgbe_set_num_queues(adapter);
3799
3800         err = ixgbe_set_interrupt_capability(adapter);
3801         if (err) {
3802                 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
3803                 goto err_set_interrupt;
3804         }
3805
3806         err = ixgbe_alloc_q_vectors(adapter);
3807         if (err) {
3808                 DPRINTK(PROBE, ERR, "Unable to allocate memory for queue "
3809                         "vectors\n");
3810                 goto err_alloc_q_vectors;
3811         }
3812
3813         err = ixgbe_alloc_queues(adapter);
3814         if (err) {
3815                 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
3816                 goto err_alloc_queues;
3817         }
3818
3819         DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
3820                 "Tx Queue count = %u\n",
3821                 (adapter->num_rx_queues > 1) ? "Enabled" :
3822                 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
3823
3824         set_bit(__IXGBE_DOWN, &adapter->state);
3825
3826         return 0;
3827
3828 err_alloc_queues:
3829         ixgbe_free_q_vectors(adapter);
3830 err_alloc_q_vectors:
3831         ixgbe_reset_interrupt_capability(adapter);
3832 err_set_interrupt:
3833         return err;
3834 }
3835
3836 /**
3837  * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
3838  * @adapter: board private structure to clear interrupt scheme on
3839  *
3840  * We go through and clear interrupt specific resources and reset the structure
3841  * to pre-load conditions
3842  **/
3843 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
3844 {
3845         kfree(adapter->tx_ring);
3846         kfree(adapter->rx_ring);
3847         adapter->tx_ring = NULL;
3848         adapter->rx_ring = NULL;
3849
3850         ixgbe_free_q_vectors(adapter);
3851         ixgbe_reset_interrupt_capability(adapter);
3852 }
3853
3854 /**
3855  * ixgbe_sfp_timer - worker thread to find a missing module
3856  * @data: pointer to our adapter struct
3857  **/
3858 static void ixgbe_sfp_timer(unsigned long data)
3859 {
3860         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
3861
3862         /*
3863          * Do the sfp_timer outside of interrupt context due to the
3864          * delays that sfp+ detection requires
3865          */
3866         schedule_work(&adapter->sfp_task);
3867 }
3868
3869 /**
3870  * ixgbe_sfp_task - worker thread to find a missing module
3871  * @work: pointer to work_struct containing our data
3872  **/
3873 static void ixgbe_sfp_task(struct work_struct *work)
3874 {
3875         struct ixgbe_adapter *adapter = container_of(work,
3876                                                      struct ixgbe_adapter,
3877                                                      sfp_task);
3878         struct ixgbe_hw *hw = &adapter->hw;
3879
3880         if ((hw->phy.type == ixgbe_phy_nl) &&
3881             (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
3882                 s32 ret = hw->phy.ops.identify_sfp(hw);
3883                 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
3884                         goto reschedule;
3885                 ret = hw->phy.ops.reset(hw);
3886                 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3887                         dev_err(&adapter->pdev->dev, "failed to initialize "
3888                                 "because an unsupported SFP+ module type "
3889                                 "was detected.\n"
3890                                 "Reload the driver after installing a "
3891                                 "supported module.\n");
3892                         unregister_netdev(adapter->netdev);
3893                 } else {
3894                         DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
3895                                 hw->phy.sfp_type);
3896                 }
3897                 /* don't need this routine any more */
3898                 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3899         }
3900         return;
3901 reschedule:
3902         if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
3903                 mod_timer(&adapter->sfp_timer,
3904                           round_jiffies(jiffies + (2 * HZ)));
3905 }
3906
3907 /**
3908  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
3909  * @adapter: board private structure to initialize
3910  *
3911  * ixgbe_sw_init initializes the Adapter private data structure.
3912  * Fields are initialized based on PCI device information and
3913  * OS network device settings (MTU size).
3914  **/
3915 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
3916 {
3917         struct ixgbe_hw *hw = &adapter->hw;
3918         struct pci_dev *pdev = adapter->pdev;
3919         unsigned int rss;
3920 #ifdef CONFIG_IXGBE_DCB
3921         int j;
3922         struct tc_configuration *tc;
3923 #endif
3924
3925         /* PCI config space info */
3926
3927         hw->vendor_id = pdev->vendor;
3928         hw->device_id = pdev->device;
3929         hw->revision_id = pdev->revision;
3930         hw->subsystem_vendor_id = pdev->subsystem_vendor;
3931         hw->subsystem_device_id = pdev->subsystem_device;
3932
3933         /* Set capability flags */
3934         rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
3935         adapter->ring_feature[RING_F_RSS].indices = rss;
3936         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
3937         adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
3938         if (hw->mac.type == ixgbe_mac_82598EB) {
3939                 if (hw->device_id == IXGBE_DEV_ID_82598AT)
3940                         adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
3941                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
3942         } else if (hw->mac.type == ixgbe_mac_82599EB) {
3943                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
3944                 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
3945                 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
3946                 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
3947                 adapter->ring_feature[RING_F_FDIR].indices =
3948                                                          IXGBE_MAX_FDIR_INDICES;
3949                 adapter->atr_sample_rate = 20;
3950                 adapter->fdir_pballoc = 0;
3951 #ifdef IXGBE_FCOE
3952                 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
3953                 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
3954                 adapter->ring_feature[RING_F_FCOE].indices = 0;
3955                 /* Default traffic class to use for FCoE */
3956                 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
3957 #endif /* IXGBE_FCOE */
3958         }
3959
3960 #ifdef CONFIG_IXGBE_DCB
3961         /* Configure DCB traffic classes */
3962         for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
3963                 tc = &adapter->dcb_cfg.tc_config[j];
3964                 tc->path[DCB_TX_CONFIG].bwg_id = 0;
3965                 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
3966                 tc->path[DCB_RX_CONFIG].bwg_id = 0;
3967                 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
3968                 tc->dcb_pfc = pfc_disabled;
3969         }
3970         adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
3971         adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
3972         adapter->dcb_cfg.rx_pba_cfg = pba_equal;
3973         adapter->dcb_cfg.pfc_mode_enable = false;
3974         adapter->dcb_cfg.round_robin_enable = false;
3975         adapter->dcb_set_bitmap = 0x00;
3976         ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
3977                            adapter->ring_feature[RING_F_DCB].indices);
3978
3979 #endif
3980
3981         /* default flow control settings */
3982         hw->fc.requested_mode = ixgbe_fc_full;
3983         hw->fc.current_mode = ixgbe_fc_full;    /* init for ethtool output */
3984 #ifdef CONFIG_DCB
3985         adapter->last_lfc_mode = hw->fc.current_mode;
3986 #endif
3987         hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
3988         hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
3989         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
3990         hw->fc.send_xon = true;
3991         hw->fc.disable_fc_autoneg = false;
3992
3993         /* enable itr by default in dynamic mode */
3994         adapter->rx_itr_setting = 1;
3995         adapter->rx_eitr_param = 20000;
3996         adapter->tx_itr_setting = 1;
3997         adapter->tx_eitr_param = 10000;
3998
3999         /* set defaults for eitr in MegaBytes */
4000         adapter->eitr_low = 10;
4001         adapter->eitr_high = 20;
4002
4003         /* set default ring sizes */
4004         adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4005         adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4006
4007         /* initialize eeprom parameters */
4008         if (ixgbe_init_eeprom_params_generic(hw)) {
4009                 dev_err(&pdev->dev, "EEPROM initialization failed\n");
4010                 return -EIO;
4011         }
4012
4013         /* enable rx csum by default */
4014         adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
4015
4016         set_bit(__IXGBE_DOWN, &adapter->state);
4017
4018         return 0;
4019 }
4020
4021 /**
4022  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4023  * @adapter: board private structure
4024  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
4025  *
4026  * Return 0 on success, negative on failure
4027  **/
4028 int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
4029                              struct ixgbe_ring *tx_ring)
4030 {
4031         struct pci_dev *pdev = adapter->pdev;
4032         int size;
4033
4034         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4035         tx_ring->tx_buffer_info = vmalloc(size);
4036         if (!tx_ring->tx_buffer_info)
4037                 goto err;
4038         memset(tx_ring->tx_buffer_info, 0, size);
4039
4040         /* round up to nearest 4K */
4041         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
4042         tx_ring->size = ALIGN(tx_ring->size, 4096);
4043
4044         tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
4045                                              &tx_ring->dma);
4046         if (!tx_ring->desc)
4047                 goto err;
4048
4049         tx_ring->next_to_use = 0;
4050         tx_ring->next_to_clean = 0;
4051         tx_ring->work_limit = tx_ring->count;
4052         return 0;
4053
4054 err:
4055         vfree(tx_ring->tx_buffer_info);
4056         tx_ring->tx_buffer_info = NULL;
4057         DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
4058                             "descriptor ring\n");
4059         return -ENOMEM;
4060 }
4061
4062 /**
4063  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4064  * @adapter: board private structure
4065  *
4066  * If this function returns with an error, then it's possible one or
4067  * more of the rings is populated (while the rest are not).  It is the
4068  * callers duty to clean those orphaned rings.
4069  *
4070  * Return 0 on success, negative on failure
4071  **/
4072 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4073 {
4074         int i, err = 0;
4075
4076         for (i = 0; i < adapter->num_tx_queues; i++) {
4077                 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
4078                 if (!err)
4079                         continue;
4080                 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
4081                 break;
4082         }
4083
4084         return err;
4085 }
4086
4087 /**
4088  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4089  * @adapter: board private structure
4090  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
4091  *
4092  * Returns 0 on success, negative on failure
4093  **/
4094 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
4095                              struct ixgbe_ring *rx_ring)
4096 {
4097         struct pci_dev *pdev = adapter->pdev;
4098         int size;
4099
4100         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4101         rx_ring->rx_buffer_info = vmalloc(size);
4102         if (!rx_ring->rx_buffer_info) {
4103                 DPRINTK(PROBE, ERR,
4104                         "vmalloc allocation failed for the rx desc ring\n");
4105                 goto alloc_failed;
4106         }
4107         memset(rx_ring->rx_buffer_info, 0, size);
4108
4109         /* Round up to nearest 4K */
4110         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4111         rx_ring->size = ALIGN(rx_ring->size, 4096);
4112
4113         rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
4114
4115         if (!rx_ring->desc) {
4116                 DPRINTK(PROBE, ERR,
4117                         "Memory allocation failed for the rx desc ring\n");
4118                 vfree(rx_ring->rx_buffer_info);
4119                 goto alloc_failed;
4120         }
4121
4122         rx_ring->next_to_clean = 0;
4123         rx_ring->next_to_use = 0;
4124
4125         return 0;
4126
4127 alloc_failed:
4128         return -ENOMEM;
4129 }
4130
4131 /**
4132  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4133  * @adapter: board private structure
4134  *
4135  * If this function returns with an error, then it's possible one or
4136  * more of the rings is populated (while the rest are not).  It is the
4137  * callers duty to clean those orphaned rings.
4138  *
4139  * Return 0 on success, negative on failure
4140  **/
4141
4142 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4143 {
4144         int i, err = 0;
4145
4146         for (i = 0; i < adapter->num_rx_queues; i++) {
4147                 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
4148                 if (!err)
4149                         continue;
4150                 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
4151                 break;
4152         }
4153
4154         return err;
4155 }
4156
4157 /**
4158  * ixgbe_free_tx_resources - Free Tx Resources per Queue
4159  * @adapter: board private structure
4160  * @tx_ring: Tx descriptor ring for a specific queue
4161  *
4162  * Free all transmit software resources
4163  **/
4164 void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
4165                              struct ixgbe_ring *tx_ring)
4166 {
4167         struct pci_dev *pdev = adapter->pdev;
4168
4169         ixgbe_clean_tx_ring(adapter, tx_ring);
4170
4171         vfree(tx_ring->tx_buffer_info);
4172         tx_ring->tx_buffer_info = NULL;
4173
4174         pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
4175
4176         tx_ring->desc = NULL;
4177 }
4178
4179 /**
4180  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4181  * @adapter: board private structure
4182  *
4183  * Free all transmit software resources
4184  **/
4185 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4186 {
4187         int i;
4188
4189         for (i = 0; i < adapter->num_tx_queues; i++)
4190                 if (adapter->tx_ring[i].desc)
4191                         ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
4192 }
4193
4194 /**
4195  * ixgbe_free_rx_resources - Free Rx Resources
4196  * @adapter: board private structure
4197  * @rx_ring: ring to clean the resources from
4198  *
4199  * Free all receive software resources
4200  **/
4201 void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
4202                              struct ixgbe_ring *rx_ring)
4203 {
4204         struct pci_dev *pdev = adapter->pdev;
4205
4206         ixgbe_clean_rx_ring(adapter, rx_ring);
4207
4208         vfree(rx_ring->rx_buffer_info);
4209         rx_ring->rx_buffer_info = NULL;
4210
4211         pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
4212
4213         rx_ring->desc = NULL;
4214 }
4215
4216 /**
4217  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4218  * @adapter: board private structure
4219  *
4220  * Free all receive software resources
4221  **/
4222 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4223 {
4224         int i;
4225
4226         for (i = 0; i < adapter->num_rx_queues; i++)
4227                 if (adapter->rx_ring[i].desc)
4228                         ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
4229 }
4230
4231 /**
4232  * ixgbe_change_mtu - Change the Maximum Transfer Unit
4233  * @netdev: network interface device structure
4234  * @new_mtu: new value for maximum frame size
4235  *
4236  * Returns 0 on success, negative on failure
4237  **/
4238 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4239 {
4240         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4241         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4242
4243         /* MTU < 68 is an error and causes problems on some kernels */
4244         if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
4245                 return -EINVAL;
4246
4247         DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
4248                 netdev->mtu, new_mtu);
4249         /* must set new MTU before calling down or up */
4250         netdev->mtu = new_mtu;
4251
4252         if (netif_running(netdev))
4253                 ixgbe_reinit_locked(adapter);
4254
4255         return 0;
4256 }
4257
4258 /**
4259  * ixgbe_open - Called when a network interface is made active
4260  * @netdev: network interface device structure
4261  *
4262  * Returns 0 on success, negative value on failure
4263  *
4264  * The open entry point is called when a network interface is made
4265  * active by the system (IFF_UP).  At this point all resources needed
4266  * for transmit and receive operations are allocated, the interrupt
4267  * handler is registered with the OS, the watchdog timer is started,
4268  * and the stack is notified that the interface is ready.
4269  **/
4270 static int ixgbe_open(struct net_device *netdev)
4271 {
4272         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4273         int err;
4274
4275         /* disallow open during test */
4276         if (test_bit(__IXGBE_TESTING, &adapter->state))
4277                 return -EBUSY;
4278
4279         netif_carrier_off(netdev);
4280
4281         /* allocate transmit descriptors */
4282         err = ixgbe_setup_all_tx_resources(adapter);
4283         if (err)
4284                 goto err_setup_tx;
4285
4286         /* allocate receive descriptors */
4287         err = ixgbe_setup_all_rx_resources(adapter);
4288         if (err)
4289                 goto err_setup_rx;
4290
4291         ixgbe_configure(adapter);
4292
4293         err = ixgbe_request_irq(adapter);
4294         if (err)
4295                 goto err_req_irq;
4296
4297         err = ixgbe_up_complete(adapter);
4298         if (err)
4299                 goto err_up;
4300
4301         netif_tx_start_all_queues(netdev);
4302
4303         return 0;
4304
4305 err_up:
4306         ixgbe_release_hw_control(adapter);
4307         ixgbe_free_irq(adapter);
4308 err_req_irq:
4309 err_setup_rx:
4310         ixgbe_free_all_rx_resources(adapter);
4311 err_setup_tx:
4312         ixgbe_free_all_tx_resources(adapter);
4313         ixgbe_reset(adapter);
4314
4315         return err;
4316 }
4317
4318 /**
4319  * ixgbe_close - Disables a network interface
4320  * @netdev: network interface device structure
4321  *
4322  * Returns 0, this is not allowed to fail
4323  *
4324  * The close entry point is called when an interface is de-activated
4325  * by the OS.  The hardware is still under the drivers control, but
4326  * needs to be disabled.  A global MAC reset is issued to stop the
4327  * hardware, and all transmit and receive resources are freed.
4328  **/
4329 static int ixgbe_close(struct net_device *netdev)
4330 {
4331         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4332
4333         ixgbe_down(adapter);
4334         ixgbe_free_irq(adapter);
4335
4336         ixgbe_free_all_tx_resources(adapter);
4337         ixgbe_free_all_rx_resources(adapter);
4338
4339         ixgbe_release_hw_control(adapter);
4340
4341         return 0;
4342 }
4343
4344 #ifdef CONFIG_PM
4345 static int ixgbe_resume(struct pci_dev *pdev)
4346 {
4347         struct net_device *netdev = pci_get_drvdata(pdev);
4348         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4349         u32 err;
4350
4351         pci_set_power_state(pdev, PCI_D0);
4352         pci_restore_state(pdev);
4353
4354         err = pci_enable_device_mem(pdev);
4355         if (err) {
4356                 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
4357                                 "suspend\n");
4358                 return err;
4359         }
4360         pci_set_master(pdev);
4361
4362         pci_wake_from_d3(pdev, false);
4363
4364         err = ixgbe_init_interrupt_scheme(adapter);
4365         if (err) {
4366                 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
4367                                 "device\n");
4368                 return err;
4369         }
4370
4371         ixgbe_reset(adapter);
4372
4373         IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
4374
4375         if (netif_running(netdev)) {
4376                 err = ixgbe_open(adapter->netdev);
4377                 if (err)
4378                         return err;
4379         }
4380
4381         netif_device_attach(netdev);
4382
4383         return 0;
4384 }
4385 #endif /* CONFIG_PM */
4386
4387 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
4388 {
4389         struct net_device *netdev = pci_get_drvdata(pdev);
4390         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4391         struct ixgbe_hw *hw = &adapter->hw;
4392         u32 ctrl, fctrl;
4393         u32 wufc = adapter->wol;
4394 #ifdef CONFIG_PM
4395         int retval = 0;
4396 #endif
4397
4398         netif_device_detach(netdev);
4399
4400         if (netif_running(netdev)) {
4401                 ixgbe_down(adapter);
4402                 ixgbe_free_irq(adapter);
4403                 ixgbe_free_all_tx_resources(adapter);
4404                 ixgbe_free_all_rx_resources(adapter);
4405         }
4406         ixgbe_clear_interrupt_scheme(adapter);
4407
4408 #ifdef CONFIG_PM
4409         retval = pci_save_state(pdev);
4410         if (retval)
4411                 return retval;
4412
4413 #endif
4414         if (wufc) {
4415                 ixgbe_set_rx_mode(netdev);
4416
4417                 /* turn on all-multi mode if wake on multicast is enabled */
4418                 if (wufc & IXGBE_WUFC_MC) {
4419                         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4420                         fctrl |= IXGBE_FCTRL_MPE;
4421                         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4422                 }
4423
4424                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
4425                 ctrl |= IXGBE_CTRL_GIO_DIS;
4426                 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
4427
4428                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
4429         } else {
4430                 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
4431                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
4432         }
4433
4434         if (wufc && hw->mac.type == ixgbe_mac_82599EB)
4435                 pci_wake_from_d3(pdev, true);
4436         else
4437                 pci_wake_from_d3(pdev, false);
4438
4439         *enable_wake = !!wufc;
4440
4441         ixgbe_release_hw_control(adapter);
4442
4443         pci_disable_device(pdev);
4444
4445         return 0;
4446 }
4447
4448 #ifdef CONFIG_PM
4449 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
4450 {
4451         int retval;
4452         bool wake;
4453
4454         retval = __ixgbe_shutdown(pdev, &wake);
4455         if (retval)
4456                 return retval;
4457
4458         if (wake) {
4459                 pci_prepare_to_sleep(pdev);
4460         } else {
4461                 pci_wake_from_d3(pdev, false);
4462                 pci_set_power_state(pdev, PCI_D3hot);
4463         }
4464
4465         return 0;
4466 }
4467 #endif /* CONFIG_PM */
4468
4469 static void ixgbe_shutdown(struct pci_dev *pdev)
4470 {
4471         bool wake;
4472
4473         __ixgbe_shutdown(pdev, &wake);
4474
4475         if (system_state == SYSTEM_POWER_OFF) {
4476                 pci_wake_from_d3(pdev, wake);
4477                 pci_set_power_state(pdev, PCI_D3hot);
4478         }
4479 }
4480
4481 /**
4482  * ixgbe_update_stats - Update the board statistics counters.
4483  * @adapter: board private structure
4484  **/
4485 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
4486 {
4487         struct ixgbe_hw *hw = &adapter->hw;
4488         u64 total_mpc = 0;
4489         u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
4490
4491         if (hw->mac.type == ixgbe_mac_82599EB) {
4492                 u64 rsc_count = 0;
4493                 for (i = 0; i < 16; i++)
4494                         adapter->hw_rx_no_dma_resources +=
4495                                              IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
4496                 for (i = 0; i < adapter->num_rx_queues; i++)
4497                         rsc_count += adapter->rx_ring[i].rsc_count;
4498                 adapter->rsc_count = rsc_count;
4499         }
4500
4501         adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
4502         for (i = 0; i < 8; i++) {
4503                 /* for packet buffers not used, the register should read 0 */
4504                 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
4505                 missed_rx += mpc;
4506                 adapter->stats.mpc[i] += mpc;
4507                 total_mpc += adapter->stats.mpc[i];
4508                 if (hw->mac.type == ixgbe_mac_82598EB)
4509                         adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
4510                 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
4511                 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
4512                 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
4513                 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
4514                 if (hw->mac.type == ixgbe_mac_82599EB) {
4515                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4516                                                             IXGBE_PXONRXCNT(i));
4517                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4518                                                            IXGBE_PXOFFRXCNT(i));
4519                         adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
4520                 } else {
4521                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4522                                                               IXGBE_PXONRXC(i));
4523                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4524                                                              IXGBE_PXOFFRXC(i));
4525                 }
4526                 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
4527                                                             IXGBE_PXONTXC(i));
4528                 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
4529                                                              IXGBE_PXOFFTXC(i));
4530         }
4531         adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
4532         /* work around hardware counting issue */
4533         adapter->stats.gprc -= missed_rx;
4534
4535         /* 82598 hardware only has a 32 bit counter in the high register */
4536         if (hw->mac.type == ixgbe_mac_82599EB) {
4537                 u64 tmp;
4538                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
4539                 tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF; /* 4 high bits of GORC */
4540                 adapter->stats.gorc += (tmp << 32);
4541                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
4542                 tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF; /* 4 high bits of GOTC */
4543                 adapter->stats.gotc += (tmp << 32);
4544                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
4545                 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
4546                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
4547                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
4548                 adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
4549                 adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
4550 #ifdef IXGBE_FCOE
4551                 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
4552                 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
4553                 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
4554                 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
4555                 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
4556                 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
4557 #endif /* IXGBE_FCOE */
4558         } else {
4559                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
4560                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
4561                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
4562                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
4563                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
4564         }
4565         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
4566         adapter->stats.bprc += bprc;
4567         adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
4568         if (hw->mac.type == ixgbe_mac_82598EB)
4569                 adapter->stats.mprc -= bprc;
4570         adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
4571         adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
4572         adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
4573         adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
4574         adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
4575         adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
4576         adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
4577         adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
4578         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
4579         adapter->stats.lxontxc += lxon;
4580         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
4581         adapter->stats.lxofftxc += lxoff;
4582         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4583         adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
4584         adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
4585         /*
4586          * 82598 errata - tx of flow control packets is included in tx counters
4587          */
4588         xon_off_tot = lxon + lxoff;
4589         adapter->stats.gptc -= xon_off_tot;
4590         adapter->stats.mptc -= xon_off_tot;
4591         adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
4592         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4593         adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
4594         adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
4595         adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
4596         adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
4597         adapter->stats.ptc64 -= xon_off_tot;
4598         adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
4599         adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
4600         adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
4601         adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
4602         adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
4603         adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
4604
4605         /* Fill out the OS statistics structure */
4606         adapter->net_stats.multicast = adapter->stats.mprc;
4607
4608         /* Rx Errors */
4609         adapter->net_stats.rx_errors = adapter->stats.crcerrs +
4610                                        adapter->stats.rlec;
4611         adapter->net_stats.rx_dropped = 0;
4612         adapter->net_stats.rx_length_errors = adapter->stats.rlec;
4613         adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
4614         adapter->net_stats.rx_missed_errors = total_mpc;
4615 }
4616
4617 /**
4618  * ixgbe_watchdog - Timer Call-back
4619  * @data: pointer to adapter cast into an unsigned long
4620  **/
4621 static void ixgbe_watchdog(unsigned long data)
4622 {
4623         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4624         struct ixgbe_hw *hw = &adapter->hw;
4625         u64 eics = 0;
4626         int i;
4627
4628         /*
4629          *  Do the watchdog outside of interrupt context due to the lovely
4630          * delays that some of the newer hardware requires
4631          */
4632
4633         if (test_bit(__IXGBE_DOWN, &adapter->state))
4634                 goto watchdog_short_circuit;
4635
4636         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
4637                 /*
4638                  * for legacy and MSI interrupts don't set any bits
4639                  * that are enabled for EIAM, because this operation
4640                  * would set *both* EIMS and EICS for any bit in EIAM
4641                  */
4642                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4643                         (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
4644                 goto watchdog_reschedule;
4645         }
4646
4647         /* get one bit for every active tx/rx interrupt vector */
4648         for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
4649                 struct ixgbe_q_vector *qv = adapter->q_vector[i];
4650                 if (qv->rxr_count || qv->txr_count)
4651                         eics |= ((u64)1 << i);
4652         }
4653
4654         /* Cause software interrupt to ensure rx rings are cleaned */
4655         ixgbe_irq_rearm_queues(adapter, eics);
4656
4657 watchdog_reschedule:
4658         /* Reset the timer */
4659         mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
4660
4661 watchdog_short_circuit:
4662         schedule_work(&adapter->watchdog_task);
4663 }
4664
4665 /**
4666  * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
4667  * @work: pointer to work_struct containing our data
4668  **/
4669 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
4670 {
4671         struct ixgbe_adapter *adapter = container_of(work,
4672                                                      struct ixgbe_adapter,
4673                                                      multispeed_fiber_task);
4674         struct ixgbe_hw *hw = &adapter->hw;
4675         u32 autoneg;
4676         bool negotiation;
4677
4678         adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
4679         autoneg = hw->phy.autoneg_advertised;
4680         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
4681                 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
4682         if (hw->mac.ops.setup_link)
4683                 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
4684         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4685         adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
4686 }
4687
4688 /**
4689  * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
4690  * @work: pointer to work_struct containing our data
4691  **/
4692 static void ixgbe_sfp_config_module_task(struct work_struct *work)
4693 {
4694         struct ixgbe_adapter *adapter = container_of(work,
4695                                                      struct ixgbe_adapter,
4696                                                      sfp_config_module_task);
4697         struct ixgbe_hw *hw = &adapter->hw;
4698         u32 err;
4699
4700         adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
4701
4702         /* Time for electrical oscillations to settle down */
4703         msleep(100);
4704         err = hw->phy.ops.identify_sfp(hw);
4705
4706         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4707                 dev_err(&adapter->pdev->dev, "failed to initialize because "
4708                         "an unsupported SFP+ module type was detected.\n"
4709                         "Reload the driver after installing a supported "
4710                         "module.\n");
4711                 unregister_netdev(adapter->netdev);
4712                 return;
4713         }
4714         hw->mac.ops.setup_sfp(hw);
4715
4716         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
4717                 /* This will also work for DA Twinax connections */
4718                 schedule_work(&adapter->multispeed_fiber_task);
4719         adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
4720 }
4721
4722 /**
4723  * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
4724  * @work: pointer to work_struct containing our data
4725  **/
4726 static void ixgbe_fdir_reinit_task(struct work_struct *work)
4727 {
4728         struct ixgbe_adapter *adapter = container_of(work,
4729                                                      struct ixgbe_adapter,
4730                                                      fdir_reinit_task);
4731         struct ixgbe_hw *hw = &adapter->hw;
4732         int i;
4733
4734         if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
4735                 for (i = 0; i < adapter->num_tx_queues; i++)
4736                         set_bit(__IXGBE_FDIR_INIT_DONE,
4737                                 &(adapter->tx_ring[i].reinit_state));
4738         } else {
4739                 DPRINTK(PROBE, ERR, "failed to finish FDIR re-initialization, "
4740                         "ignored adding FDIR ATR filters \n");
4741         }
4742         /* Done FDIR Re-initialization, enable transmits */
4743         netif_tx_start_all_queues(adapter->netdev);
4744 }
4745
4746 /**
4747  * ixgbe_watchdog_task - worker thread to bring link up
4748  * @work: pointer to work_struct containing our data
4749  **/
4750 static void ixgbe_watchdog_task(struct work_struct *work)
4751 {
4752         struct ixgbe_adapter *adapter = container_of(work,
4753                                                      struct ixgbe_adapter,
4754                                                      watchdog_task);
4755         struct net_device *netdev = adapter->netdev;
4756         struct ixgbe_hw *hw = &adapter->hw;
4757         u32 link_speed = adapter->link_speed;
4758         bool link_up = adapter->link_up;
4759         int i;
4760         struct ixgbe_ring *tx_ring;
4761         int some_tx_pending = 0;
4762
4763         adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
4764
4765         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4766                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
4767                 if (link_up) {
4768 #ifdef CONFIG_DCB
4769                         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4770                                 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
4771                                         hw->mac.ops.fc_enable(hw, i);
4772                         } else {
4773                                 hw->mac.ops.fc_enable(hw, 0);
4774                         }
4775 #else
4776                         hw->mac.ops.fc_enable(hw, 0);
4777 #endif
4778                 }
4779
4780                 if (link_up ||
4781                     time_after(jiffies, (adapter->link_check_timeout +
4782                                          IXGBE_TRY_LINK_TIMEOUT))) {
4783                         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4784                         IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
4785                 }
4786                 adapter->link_up = link_up;
4787                 adapter->link_speed = link_speed;
4788         }
4789
4790         if (link_up) {
4791                 if (!netif_carrier_ok(netdev)) {
4792                         bool flow_rx, flow_tx;
4793
4794                         if (hw->mac.type == ixgbe_mac_82599EB) {
4795                                 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4796                                 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4797                                 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
4798                                 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
4799                         } else {
4800                                 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4801                                 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
4802                                 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
4803                                 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
4804                         }
4805
4806                         printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
4807                                "Flow Control: %s\n",
4808                                netdev->name,
4809                                (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
4810                                 "10 Gbps" :
4811                                 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
4812                                  "1 Gbps" : "unknown speed")),
4813                                ((flow_rx && flow_tx) ? "RX/TX" :
4814                                 (flow_rx ? "RX" :
4815                                 (flow_tx ? "TX" : "None"))));
4816
4817                         netif_carrier_on(netdev);
4818                 } else {
4819                         /* Force detection of hung controller */
4820                         adapter->detect_tx_hung = true;
4821                 }
4822         } else {
4823                 adapter->link_up = false;
4824                 adapter->link_speed = 0;
4825                 if (netif_carrier_ok(netdev)) {
4826                         printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
4827                                netdev->name);
4828                         netif_carrier_off(netdev);
4829                 }
4830         }
4831
4832         if (!netif_carrier_ok(netdev)) {
4833                 for (i = 0; i < adapter->num_tx_queues; i++) {
4834                         tx_ring = &adapter->tx_ring[i];
4835                         if (tx_ring->next_to_use != tx_ring->next_to_clean) {
4836                                 some_tx_pending = 1;
4837                                 break;
4838                         }
4839                 }
4840
4841                 if (some_tx_pending) {
4842                         /* We've lost link, so the controller stops DMA,
4843                          * but we've got queued Tx work that's never going
4844                          * to get done, so reset controller to flush Tx.
4845                          * (Do the reset outside of interrupt context).
4846                          */
4847                          schedule_work(&adapter->reset_task);
4848                 }
4849         }
4850
4851         ixgbe_update_stats(adapter);
4852         adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
4853 }
4854
4855 static int ixgbe_tso(struct ixgbe_adapter *adapter,
4856                      struct ixgbe_ring *tx_ring, struct sk_buff *skb,
4857                      u32 tx_flags, u8 *hdr_len)
4858 {
4859         struct ixgbe_adv_tx_context_desc *context_desc;
4860         unsigned int i;
4861         int err;
4862         struct ixgbe_tx_buffer *tx_buffer_info;
4863         u32 vlan_macip_lens = 0, type_tucmd_mlhl;
4864         u32 mss_l4len_idx, l4len;
4865
4866         if (skb_is_gso(skb)) {
4867                 if (skb_header_cloned(skb)) {
4868                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4869                         if (err)
4870                                 return err;
4871                 }
4872                 l4len = tcp_hdrlen(skb);
4873                 *hdr_len += l4len;
4874
4875                 if (skb->protocol == htons(ETH_P_IP)) {
4876                         struct iphdr *iph = ip_hdr(skb);
4877                         iph->tot_len = 0;
4878                         iph->check = 0;
4879                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4880                                                                  iph->daddr, 0,
4881                                                                  IPPROTO_TCP,
4882                                                                  0);
4883                         adapter->hw_tso_ctxt++;
4884                 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
4885                         ipv6_hdr(skb)->payload_len = 0;
4886                         tcp_hdr(skb)->check =
4887                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4888                                              &ipv6_hdr(skb)->daddr,
4889                                              0, IPPROTO_TCP, 0);
4890                         adapter->hw_tso6_ctxt++;
4891                 }
4892
4893                 i = tx_ring->next_to_use;
4894
4895                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4896                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4897
4898                 /* VLAN MACLEN IPLEN */
4899                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4900                         vlan_macip_lens |=
4901                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4902                 vlan_macip_lens |= ((skb_network_offset(skb)) <<
4903                                     IXGBE_ADVTXD_MACLEN_SHIFT);
4904                 *hdr_len += skb_network_offset(skb);
4905                 vlan_macip_lens |=
4906                     (skb_transport_header(skb) - skb_network_header(skb));
4907                 *hdr_len +=
4908                     (skb_transport_header(skb) - skb_network_header(skb));
4909                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4910                 context_desc->seqnum_seed = 0;
4911
4912                 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4913                 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
4914                                    IXGBE_ADVTXD_DTYP_CTXT);
4915
4916                 if (skb->protocol == htons(ETH_P_IP))
4917                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4918                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
4919                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4920
4921                 /* MSS L4LEN IDX */
4922                 mss_l4len_idx =
4923                     (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
4924                 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4925                 /* use index 1 for TSO */
4926                 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
4927                 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4928
4929                 tx_buffer_info->time_stamp = jiffies;
4930                 tx_buffer_info->next_to_watch = i;
4931
4932                 i++;
4933                 if (i == tx_ring->count)
4934                         i = 0;
4935                 tx_ring->next_to_use = i;
4936
4937                 return true;
4938         }
4939         return false;
4940 }
4941
4942 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
4943                           struct ixgbe_ring *tx_ring,
4944                           struct sk_buff *skb, u32 tx_flags)
4945 {
4946         struct ixgbe_adv_tx_context_desc *context_desc;
4947         unsigned int i;
4948         struct ixgbe_tx_buffer *tx_buffer_info;
4949         u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
4950
4951         if (skb->ip_summed == CHECKSUM_PARTIAL ||
4952             (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
4953                 i = tx_ring->next_to_use;
4954                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4955                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4956
4957                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4958                         vlan_macip_lens |=
4959                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4960                 vlan_macip_lens |= (skb_network_offset(skb) <<
4961                                     IXGBE_ADVTXD_MACLEN_SHIFT);
4962                 if (skb->ip_summed == CHECKSUM_PARTIAL)
4963                         vlan_macip_lens |= (skb_transport_header(skb) -
4964                                             skb_network_header(skb));
4965
4966                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4967                 context_desc->seqnum_seed = 0;
4968
4969                 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
4970                                     IXGBE_ADVTXD_DTYP_CTXT);
4971
4972                 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4973                         switch (skb->protocol) {
4974                         case cpu_to_be16(ETH_P_IP):
4975                                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4976                                 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
4977                                         type_tucmd_mlhl |=
4978                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
4979                                 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
4980                                         type_tucmd_mlhl |=
4981                                                 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
4982                                 break;
4983                         case cpu_to_be16(ETH_P_IPV6):
4984                                 /* XXX what about other V6 headers?? */
4985                                 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
4986                                         type_tucmd_mlhl |=
4987                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
4988                                 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
4989                                         type_tucmd_mlhl |=
4990                                                 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
4991                                 break;
4992                         default:
4993                                 if (unlikely(net_ratelimit())) {
4994                                         DPRINTK(PROBE, WARNING,
4995                                          "partial checksum but proto=%x!\n",
4996                                          skb->protocol);
4997                                 }
4998                                 break;
4999                         }
5000                 }
5001
5002                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5003                 /* use index zero for tx checksum offload */
5004                 context_desc->mss_l4len_idx = 0;
5005
5006                 tx_buffer_info->time_stamp = jiffies;
5007                 tx_buffer_info->next_to_watch = i;
5008
5009                 adapter->hw_csum_tx_good++;
5010                 i++;
5011                 if (i == tx_ring->count)
5012                         i = 0;
5013                 tx_ring->next_to_use = i;
5014
5015                 return true;
5016         }
5017
5018         return false;
5019 }
5020
5021 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
5022                         struct ixgbe_ring *tx_ring,
5023                         struct sk_buff *skb, u32 tx_flags,
5024                         unsigned int first)
5025 {
5026         struct ixgbe_tx_buffer *tx_buffer_info;
5027         unsigned int len;
5028         unsigned int total = skb->len;
5029         unsigned int offset = 0, size, count = 0, i;
5030         unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
5031         unsigned int f;
5032         dma_addr_t *map;
5033
5034         i = tx_ring->next_to_use;
5035
5036         if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) {
5037                 dev_err(&adapter->pdev->dev, "TX DMA map failed\n");
5038                 return 0;
5039         }
5040
5041         map = skb_shinfo(skb)->dma_maps;
5042
5043         if (tx_flags & IXGBE_TX_FLAGS_FCOE)
5044                 /* excluding fcoe_crc_eof for FCoE */
5045                 total -= sizeof(struct fcoe_crc_eof);
5046
5047         len = min(skb_headlen(skb), total);
5048         while (len) {
5049                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5050                 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5051
5052                 tx_buffer_info->length = size;
5053                 tx_buffer_info->dma = skb_shinfo(skb)->dma_head + offset;
5054                 tx_buffer_info->time_stamp = jiffies;
5055                 tx_buffer_info->next_to_watch = i;
5056
5057                 len -= size;
5058                 total -= size;
5059                 offset += size;
5060                 count++;
5061
5062                 if (len) {
5063                         i++;
5064                         if (i == tx_ring->count)
5065                                 i = 0;
5066                 }
5067         }
5068
5069         for (f = 0; f < nr_frags; f++) {
5070                 struct skb_frag_struct *frag;
5071
5072                 frag = &skb_shinfo(skb)->frags[f];
5073                 len = min((unsigned int)frag->size, total);
5074                 offset = 0;
5075
5076                 while (len) {
5077                         i++;
5078                         if (i == tx_ring->count)
5079                                 i = 0;
5080
5081                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
5082                         size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5083
5084                         tx_buffer_info->length = size;
5085                         tx_buffer_info->dma = map[f] + offset;
5086                         tx_buffer_info->time_stamp = jiffies;
5087                         tx_buffer_info->next_to_watch = i;
5088
5089                         len -= size;
5090                         total -= size;
5091                         offset += size;
5092                         count++;
5093                 }
5094                 if (total == 0)
5095                         break;
5096         }
5097
5098         tx_ring->tx_buffer_info[i].skb = skb;
5099         tx_ring->tx_buffer_info[first].next_to_watch = i;
5100
5101         return count;
5102 }
5103
5104 static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
5105                            struct ixgbe_ring *tx_ring,
5106                            int tx_flags, int count, u32 paylen, u8 hdr_len)
5107 {
5108         union ixgbe_adv_tx_desc *tx_desc = NULL;
5109         struct ixgbe_tx_buffer *tx_buffer_info;
5110         u32 olinfo_status = 0, cmd_type_len = 0;
5111         unsigned int i;
5112         u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
5113
5114         cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
5115
5116         cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
5117
5118         if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5119                 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
5120
5121         if (tx_flags & IXGBE_TX_FLAGS_TSO) {
5122                 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5123
5124                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
5125                                  IXGBE_ADVTXD_POPTS_SHIFT;
5126
5127                 /* use index 1 context for tso */
5128                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5129                 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
5130                         olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
5131                                          IXGBE_ADVTXD_POPTS_SHIFT;
5132
5133         } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
5134                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
5135                                  IXGBE_ADVTXD_POPTS_SHIFT;
5136
5137         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5138                 olinfo_status |= IXGBE_ADVTXD_CC;
5139                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5140                 if (tx_flags & IXGBE_TX_FLAGS_FSO)
5141                         cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5142         }
5143
5144         olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
5145
5146         i = tx_ring->next_to_use;
5147         while (count--) {
5148                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5149                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
5150                 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
5151                 tx_desc->read.cmd_type_len =
5152                         cpu_to_le32(cmd_type_len | tx_buffer_info->length);
5153                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
5154                 i++;
5155                 if (i == tx_ring->count)
5156                         i = 0;
5157         }
5158
5159         tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
5160
5161         /*
5162          * Force memory writes to complete before letting h/w
5163          * know there are new descriptors to fetch.  (Only
5164          * applicable for weak-ordered memory model archs,
5165          * such as IA-64).
5166          */
5167         wmb();
5168
5169         tx_ring->next_to_use = i;
5170         writel(i, adapter->hw.hw_addr + tx_ring->tail);
5171 }
5172
5173 static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
5174                       int queue, u32 tx_flags)
5175 {
5176         /* Right now, we support IPv4 only */
5177         struct ixgbe_atr_input atr_input;
5178         struct tcphdr *th;
5179         struct iphdr *iph = ip_hdr(skb);
5180         struct ethhdr *eth = (struct ethhdr *)skb->data;
5181         u16 vlan_id, src_port, dst_port, flex_bytes;
5182         u32 src_ipv4_addr, dst_ipv4_addr;
5183         u8 l4type = 0;
5184
5185         /* check if we're UDP or TCP */
5186         if (iph->protocol == IPPROTO_TCP) {
5187                 th = tcp_hdr(skb);
5188                 src_port = th->source;
5189                 dst_port = th->dest;
5190                 l4type |= IXGBE_ATR_L4TYPE_TCP;
5191                 /* l4type IPv4 type is 0, no need to assign */
5192         } else {
5193                 /* Unsupported L4 header, just bail here */
5194                 return;
5195         }
5196
5197         memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
5198
5199         vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
5200                    IXGBE_TX_FLAGS_VLAN_SHIFT;
5201         src_ipv4_addr = iph->saddr;
5202         dst_ipv4_addr = iph->daddr;
5203         flex_bytes = eth->h_proto;
5204
5205         ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
5206         ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
5207         ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
5208         ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
5209         ixgbe_atr_set_l4type_82599(&atr_input, l4type);
5210         /* src and dst are inverted, think how the receiver sees them */
5211         ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
5212         ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
5213
5214         /* This assumes the Rx queue and Tx queue are bound to the same CPU */
5215         ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
5216 }
5217
5218 static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
5219                                  struct ixgbe_ring *tx_ring, int size)
5220 {
5221         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5222
5223         netif_stop_subqueue(netdev, tx_ring->queue_index);
5224         /* Herbert's original patch had:
5225          *  smp_mb__after_netif_stop_queue();
5226          * but since that doesn't exist yet, just open code it. */
5227         smp_mb();
5228
5229         /* We need to check again in a case another CPU has just
5230          * made room available. */
5231         if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
5232                 return -EBUSY;
5233
5234         /* A reprieve! - use start_queue because it doesn't call schedule */
5235         netif_start_subqueue(netdev, tx_ring->queue_index);
5236         ++adapter->restart_queue;
5237         return 0;
5238 }
5239
5240 static int ixgbe_maybe_stop_tx(struct net_device *netdev,
5241                               struct ixgbe_ring *tx_ring, int size)
5242 {
5243         if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
5244                 return 0;
5245         return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
5246 }
5247
5248 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
5249 {
5250         struct ixgbe_adapter *adapter = netdev_priv(dev);
5251         int txq = smp_processor_id();
5252
5253         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
5254                 while (unlikely(txq >= dev->real_num_tx_queues))
5255                         txq -= dev->real_num_tx_queues;
5256                 return txq;
5257         }
5258
5259         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
5260                 return (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK) >> 13;
5261
5262         return skb_tx_hash(dev, skb);
5263 }
5264
5265 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
5266                                     struct net_device *netdev)
5267 {
5268         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5269         struct ixgbe_ring *tx_ring;
5270         unsigned int first;
5271         unsigned int tx_flags = 0;
5272         u8 hdr_len = 0;
5273         int r_idx = 0, tso;
5274         int count = 0;
5275         unsigned int f;
5276
5277         if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
5278                 tx_flags |= vlan_tx_tag_get(skb);
5279                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5280                         tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
5281                         tx_flags |= (skb->queue_mapping << 13);
5282                 }
5283                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5284                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5285         } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5286                 if (skb->priority != TC_PRIO_CONTROL) {
5287                         tx_flags |= (skb->queue_mapping << 13);
5288                         tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5289                         tx_flags |= IXGBE_TX_FLAGS_VLAN;
5290                 } else {
5291                         skb->queue_mapping =
5292                                 adapter->ring_feature[RING_F_DCB].indices-1;
5293                 }
5294         }
5295
5296         r_idx = skb->queue_mapping;
5297         tx_ring = &adapter->tx_ring[r_idx];
5298
5299         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
5300             (skb->protocol == htons(ETH_P_FCOE))) {
5301                 tx_flags |= IXGBE_TX_FLAGS_FCOE;
5302 #ifdef IXGBE_FCOE
5303                 r_idx = smp_processor_id();
5304                 r_idx &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
5305                 r_idx += adapter->ring_feature[RING_F_FCOE].mask;
5306                 tx_ring = &adapter->tx_ring[r_idx];
5307 #endif
5308         }
5309         /* four things can cause us to need a context descriptor */
5310         if (skb_is_gso(skb) ||
5311             (skb->ip_summed == CHECKSUM_PARTIAL) ||
5312             (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
5313             (tx_flags & IXGBE_TX_FLAGS_FCOE))
5314                 count++;
5315
5316         count += TXD_USE_COUNT(skb_headlen(skb));
5317         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
5318                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
5319
5320         if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
5321                 adapter->tx_busy++;
5322                 return NETDEV_TX_BUSY;
5323         }
5324
5325         first = tx_ring->next_to_use;
5326         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5327 #ifdef IXGBE_FCOE
5328                 /* setup tx offload for FCoE */
5329                 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5330                 if (tso < 0) {
5331                         dev_kfree_skb_any(skb);
5332                         return NETDEV_TX_OK;
5333                 }
5334                 if (tso)
5335                         tx_flags |= IXGBE_TX_FLAGS_FSO;
5336 #endif /* IXGBE_FCOE */
5337         } else {
5338                 if (skb->protocol == htons(ETH_P_IP))
5339                         tx_flags |= IXGBE_TX_FLAGS_IPV4;
5340                 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5341                 if (tso < 0) {
5342                         dev_kfree_skb_any(skb);
5343                         return NETDEV_TX_OK;
5344                 }
5345
5346                 if (tso)
5347                         tx_flags |= IXGBE_TX_FLAGS_TSO;
5348                 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
5349                          (skb->ip_summed == CHECKSUM_PARTIAL))
5350                         tx_flags |= IXGBE_TX_FLAGS_CSUM;
5351         }
5352
5353         count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
5354         if (count) {
5355                 /* add the ATR filter if ATR is on */
5356                 if (tx_ring->atr_sample_rate) {
5357                         ++tx_ring->atr_count;
5358                         if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
5359                              test_bit(__IXGBE_FDIR_INIT_DONE,
5360                                       &tx_ring->reinit_state)) {
5361                                 ixgbe_atr(adapter, skb, tx_ring->queue_index,
5362                                           tx_flags);
5363                                 tx_ring->atr_count = 0;
5364                         }
5365                 }
5366                 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
5367                                hdr_len);
5368                 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
5369
5370         } else {
5371                 dev_kfree_skb_any(skb);
5372                 tx_ring->tx_buffer_info[first].time_stamp = 0;
5373                 tx_ring->next_to_use = first;
5374         }
5375
5376         return NETDEV_TX_OK;
5377 }
5378
5379 /**
5380  * ixgbe_get_stats - Get System Network Statistics
5381  * @netdev: network interface device structure
5382  *
5383  * Returns the address of the device statistics structure.
5384  * The statistics are actually updated from the timer callback.
5385  **/
5386 static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
5387 {
5388         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5389
5390         /* only return the current stats */
5391         return &adapter->net_stats;
5392 }
5393
5394 /**
5395  * ixgbe_set_mac - Change the Ethernet Address of the NIC
5396  * @netdev: network interface device structure
5397  * @p: pointer to an address structure
5398  *
5399  * Returns 0 on success, negative on failure
5400  **/
5401 static int ixgbe_set_mac(struct net_device *netdev, void *p)
5402 {
5403         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5404         struct ixgbe_hw *hw = &adapter->hw;
5405         struct sockaddr *addr = p;
5406
5407         if (!is_valid_ether_addr(addr->sa_data))
5408                 return -EADDRNOTAVAIL;
5409
5410         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
5411         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
5412
5413         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
5414
5415         return 0;
5416 }
5417
5418 static int
5419 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
5420 {
5421         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5422         struct ixgbe_hw *hw = &adapter->hw;
5423         u16 value;
5424         int rc;
5425
5426         if (prtad != hw->phy.mdio.prtad)
5427                 return -EINVAL;
5428         rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
5429         if (!rc)
5430                 rc = value;
5431         return rc;
5432 }
5433
5434 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
5435                             u16 addr, u16 value)
5436 {
5437         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5438         struct ixgbe_hw *hw = &adapter->hw;
5439
5440         if (prtad != hw->phy.mdio.prtad)
5441                 return -EINVAL;
5442         return hw->phy.ops.write_reg(hw, addr, devad, value);
5443 }
5444
5445 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
5446 {
5447         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5448
5449         return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
5450 }
5451
5452 /**
5453  * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
5454  * netdev->dev_addrs
5455  * @netdev: network interface device structure
5456  *
5457  * Returns non-zero on failure
5458  **/
5459 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
5460 {
5461         int err = 0;
5462         struct ixgbe_adapter *adapter = netdev_priv(dev);
5463         struct ixgbe_mac_info *mac = &adapter->hw.mac;
5464
5465         if (is_valid_ether_addr(mac->san_addr)) {
5466                 rtnl_lock();
5467                 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5468                 rtnl_unlock();
5469         }
5470         return err;
5471 }
5472
5473 /**
5474  * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
5475  * netdev->dev_addrs
5476  * @netdev: network interface device structure
5477  *
5478  * Returns non-zero on failure
5479  **/
5480 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
5481 {
5482         int err = 0;
5483         struct ixgbe_adapter *adapter = netdev_priv(dev);
5484         struct ixgbe_mac_info *mac = &adapter->hw.mac;
5485
5486         if (is_valid_ether_addr(mac->san_addr)) {
5487                 rtnl_lock();
5488                 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5489                 rtnl_unlock();
5490         }
5491         return err;
5492 }
5493
5494 #ifdef CONFIG_NET_POLL_CONTROLLER
5495 /*
5496  * Polling 'interrupt' - used by things like netconsole to send skbs
5497  * without having to re-enable interrupts. It's not called while
5498  * the interrupt routine is executing.
5499  */
5500 static void ixgbe_netpoll(struct net_device *netdev)
5501 {
5502         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5503         int i;
5504
5505         adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
5506         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5507                 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
5508                 for (i = 0; i < num_q_vectors; i++) {
5509                         struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
5510                         ixgbe_msix_clean_many(0, q_vector);
5511                 }
5512         } else {
5513                 ixgbe_intr(adapter->pdev->irq, netdev);
5514         }
5515         adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
5516 }
5517 #endif
5518
5519 static const struct net_device_ops ixgbe_netdev_ops = {
5520         .ndo_open               = ixgbe_open,
5521         .ndo_stop               = ixgbe_close,
5522         .ndo_start_xmit         = ixgbe_xmit_frame,
5523         .ndo_select_queue       = ixgbe_select_queue,
5524         .ndo_get_stats          = ixgbe_get_stats,
5525         .ndo_set_rx_mode        = ixgbe_set_rx_mode,
5526         .ndo_set_multicast_list = ixgbe_set_rx_mode,
5527         .ndo_validate_addr      = eth_validate_addr,
5528         .ndo_set_mac_address    = ixgbe_set_mac,
5529         .ndo_change_mtu         = ixgbe_change_mtu,
5530         .ndo_tx_timeout         = ixgbe_tx_timeout,
5531         .ndo_vlan_rx_register   = ixgbe_vlan_rx_register,
5532         .ndo_vlan_rx_add_vid    = ixgbe_vlan_rx_add_vid,
5533         .ndo_vlan_rx_kill_vid   = ixgbe_vlan_rx_kill_vid,
5534         .ndo_do_ioctl           = ixgbe_ioctl,
5535 #ifdef CONFIG_NET_POLL_CONTROLLER
5536         .ndo_poll_controller    = ixgbe_netpoll,
5537 #endif
5538 #ifdef IXGBE_FCOE
5539         .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
5540         .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
5541         .ndo_fcoe_enable = ixgbe_fcoe_enable,
5542         .ndo_fcoe_disable = ixgbe_fcoe_disable,
5543 #endif /* IXGBE_FCOE */
5544 };
5545
5546 /**
5547  * ixgbe_probe - Device Initialization Routine
5548  * @pdev: PCI device information struct
5549  * @ent: entry in ixgbe_pci_tbl
5550  *
5551  * Returns 0 on success, negative on failure
5552  *
5553  * ixgbe_probe initializes an adapter identified by a pci_dev structure.
5554  * The OS initialization, configuring of the adapter private structure,
5555  * and a hardware reset occur.
5556  **/
5557 static int __devinit ixgbe_probe(struct pci_dev *pdev,
5558                                  const struct pci_device_id *ent)
5559 {
5560         struct net_device *netdev;
5561         struct ixgbe_adapter *adapter = NULL;
5562         struct ixgbe_hw *hw;
5563         const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
5564         static int cards_found;
5565         int i, err, pci_using_dac;
5566 #ifdef IXGBE_FCOE
5567         u16 device_caps;
5568 #endif
5569         u32 part_num, eec;
5570
5571         err = pci_enable_device_mem(pdev);
5572         if (err)
5573                 return err;
5574
5575         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
5576             !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
5577                 pci_using_dac = 1;
5578         } else {
5579                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
5580                 if (err) {
5581                         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
5582                         if (err) {
5583                                 dev_err(&pdev->dev, "No usable DMA "
5584                                         "configuration, aborting\n");
5585                                 goto err_dma;
5586                         }
5587                 }
5588                 pci_using_dac = 0;
5589         }
5590
5591         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
5592                                            IORESOURCE_MEM), ixgbe_driver_name);
5593         if (err) {
5594                 dev_err(&pdev->dev,
5595                         "pci_request_selected_regions failed 0x%x\n", err);
5596                 goto err_pci_reg;
5597         }
5598
5599         pci_enable_pcie_error_reporting(pdev);
5600
5601         pci_set_master(pdev);
5602         pci_save_state(pdev);
5603
5604         netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
5605         if (!netdev) {
5606                 err = -ENOMEM;
5607                 goto err_alloc_etherdev;
5608         }
5609
5610         SET_NETDEV_DEV(netdev, &pdev->dev);
5611
5612         pci_set_drvdata(pdev, netdev);
5613         adapter = netdev_priv(netdev);
5614
5615         adapter->netdev = netdev;
5616         adapter->pdev = pdev;
5617         hw = &adapter->hw;
5618         hw->back = adapter;
5619         adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
5620
5621         hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
5622                               pci_resource_len(pdev, 0));
5623         if (!hw->hw_addr) {
5624                 err = -EIO;
5625                 goto err_ioremap;
5626         }
5627
5628         for (i = 1; i <= 5; i++) {
5629                 if (pci_resource_len(pdev, i) == 0)
5630                         continue;
5631         }
5632
5633         netdev->netdev_ops = &ixgbe_netdev_ops;
5634         ixgbe_set_ethtool_ops(netdev);
5635         netdev->watchdog_timeo = 5 * HZ;
5636         strcpy(netdev->name, pci_name(pdev));
5637
5638         adapter->bd_number = cards_found;
5639
5640         /* Setup hw api */
5641         memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
5642         hw->mac.type  = ii->mac;
5643
5644         /* EEPROM */
5645         memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
5646         eec = IXGBE_READ_REG(hw, IXGBE_EEC);
5647         /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
5648         if (!(eec & (1 << 8)))
5649                 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
5650
5651         /* PHY */
5652         memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
5653         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
5654         /* ixgbe_identify_phy_generic will set prtad and mmds properly */
5655         hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
5656         hw->phy.mdio.mmds = 0;
5657         hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
5658         hw->phy.mdio.dev = netdev;
5659         hw->phy.mdio.mdio_read = ixgbe_mdio_read;
5660         hw->phy.mdio.mdio_write = ixgbe_mdio_write;
5661
5662         /* set up this timer and work struct before calling get_invariants
5663          * which might start the timer
5664          */
5665         init_timer(&adapter->sfp_timer);
5666         adapter->sfp_timer.function = &ixgbe_sfp_timer;
5667         adapter->sfp_timer.data = (unsigned long) adapter;
5668
5669         INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
5670
5671         /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
5672         INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
5673
5674         /* a new SFP+ module arrival, called from GPI SDP2 context */
5675         INIT_WORK(&adapter->sfp_config_module_task,
5676                   ixgbe_sfp_config_module_task);
5677
5678         ii->get_invariants(hw);
5679
5680         /* setup the private structure */
5681         err = ixgbe_sw_init(adapter);
5682         if (err)
5683                 goto err_sw_init;
5684
5685         /*
5686          * If there is a fan on this device and it has failed log the
5687          * failure.
5688          */
5689         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
5690                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
5691                 if (esdp & IXGBE_ESDP_SDP1)
5692                         DPRINTK(PROBE, CRIT,
5693                                 "Fan has stopped, replace the adapter\n");
5694         }
5695
5696         /* reset_hw fills in the perm_addr as well */
5697         err = hw->mac.ops.reset_hw(hw);
5698         if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
5699             hw->mac.type == ixgbe_mac_82598EB) {
5700                 /*
5701                  * Start a kernel thread to watch for a module to arrive.
5702                  * Only do this for 82598, since 82599 will generate
5703                  * interrupts on module arrival.
5704                  */
5705                 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5706                 mod_timer(&adapter->sfp_timer,
5707                           round_jiffies(jiffies + (2 * HZ)));
5708                 err = 0;
5709         } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5710                 dev_err(&adapter->pdev->dev, "failed to initialize because "
5711                         "an unsupported SFP+ module type was detected.\n"
5712                         "Reload the driver after installing a supported "
5713                         "module.\n");
5714                 goto err_sw_init;
5715         } else if (err) {
5716                 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
5717                 goto err_sw_init;
5718         }
5719
5720         netdev->features = NETIF_F_SG |
5721                            NETIF_F_IP_CSUM |
5722                            NETIF_F_HW_VLAN_TX |
5723                            NETIF_F_HW_VLAN_RX |
5724                            NETIF_F_HW_VLAN_FILTER;
5725
5726         netdev->features |= NETIF_F_IPV6_CSUM;
5727         netdev->features |= NETIF_F_TSO;
5728         netdev->features |= NETIF_F_TSO6;
5729         netdev->features |= NETIF_F_GRO;
5730
5731         if (adapter->hw.mac.type == ixgbe_mac_82599EB)
5732                 netdev->features |= NETIF_F_SCTP_CSUM;
5733
5734         netdev->vlan_features |= NETIF_F_TSO;
5735         netdev->vlan_features |= NETIF_F_TSO6;
5736         netdev->vlan_features |= NETIF_F_IP_CSUM;
5737         netdev->vlan_features |= NETIF_F_IPV6_CSUM;
5738         netdev->vlan_features |= NETIF_F_SG;
5739
5740         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
5741                 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
5742
5743 #ifdef CONFIG_IXGBE_DCB
5744         netdev->dcbnl_ops = &dcbnl_ops;
5745 #endif
5746
5747 #ifdef IXGBE_FCOE
5748         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
5749                 if (hw->mac.ops.get_device_caps) {
5750                         hw->mac.ops.get_device_caps(hw, &device_caps);
5751                         if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
5752                                 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
5753                 }
5754         }
5755 #endif /* IXGBE_FCOE */
5756         if (pci_using_dac)
5757                 netdev->features |= NETIF_F_HIGHDMA;
5758
5759         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
5760                 netdev->features |= NETIF_F_LRO;
5761
5762         /* make sure the EEPROM is good */
5763         if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
5764                 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
5765                 err = -EIO;
5766                 goto err_eeprom;
5767         }
5768
5769         memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
5770         memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
5771
5772         if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
5773                 dev_err(&pdev->dev, "invalid MAC address\n");
5774                 err = -EIO;
5775                 goto err_eeprom;
5776         }
5777
5778         init_timer(&adapter->watchdog_timer);
5779         adapter->watchdog_timer.function = &ixgbe_watchdog;
5780         adapter->watchdog_timer.data = (unsigned long)adapter;
5781
5782         INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
5783         INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
5784
5785         err = ixgbe_init_interrupt_scheme(adapter);
5786         if (err)
5787                 goto err_sw_init;
5788
5789         switch (pdev->device) {
5790         case IXGBE_DEV_ID_82599_KX4:
5791                 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
5792                                 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
5793                 /* Enable ACPI wakeup in GRC */
5794                 IXGBE_WRITE_REG(hw, IXGBE_GRC,
5795                              (IXGBE_READ_REG(hw, IXGBE_GRC) & ~IXGBE_GRC_APME));
5796                 break;
5797         default:
5798                 adapter->wol = 0;
5799                 break;
5800         }
5801         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
5802
5803         /* pick up the PCI bus settings for reporting later */
5804         hw->mac.ops.get_bus_info(hw);
5805
5806         /* print bus type/speed/width info */
5807         dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
5808                 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
5809                  (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
5810                 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
5811                  (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
5812                  (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
5813                  "Unknown"),
5814                 netdev->dev_addr);
5815         ixgbe_read_pba_num_generic(hw, &part_num);
5816         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
5817                 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
5818                          hw->mac.type, hw->phy.type, hw->phy.sfp_type,
5819                          (part_num >> 8), (part_num & 0xff));
5820         else
5821                 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
5822                          hw->mac.type, hw->phy.type,
5823                          (part_num >> 8), (part_num & 0xff));
5824
5825         if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
5826                 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
5827                          "this card is not sufficient for optimal "
5828                          "performance.\n");
5829                 dev_warn(&pdev->dev, "For optimal performance a x8 "
5830                          "PCI-Express slot is required.\n");
5831         }
5832
5833         /* save off EEPROM version number */
5834         hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
5835
5836         /* reset the hardware with the new settings */
5837         err = hw->mac.ops.start_hw(hw);
5838
5839         if (err == IXGBE_ERR_EEPROM_VERSION) {
5840                 /* We are running on a pre-production device, log a warning */
5841                 dev_warn(&pdev->dev, "This device is a pre-production "
5842                          "adapter/LOM.  Please be aware there may be issues "
5843                          "associated with your hardware.  If you are "
5844                          "experiencing problems please contact your Intel or "
5845                          "hardware representative who provided you with this "
5846                          "hardware.\n");
5847         }
5848         strcpy(netdev->name, "eth%d");
5849         err = register_netdev(netdev);
5850         if (err)
5851                 goto err_register;
5852
5853         /* carrier off reporting is important to ethtool even BEFORE open */
5854         netif_carrier_off(netdev);
5855
5856         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5857             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5858                 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
5859
5860 #ifdef CONFIG_IXGBE_DCA
5861         if (dca_add_requester(&pdev->dev) == 0) {
5862                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
5863                 ixgbe_setup_dca(adapter);
5864         }
5865 #endif
5866         /* add san mac addr to netdev */
5867         ixgbe_add_sanmac_netdev(netdev);
5868
5869         dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
5870         cards_found++;
5871         return 0;
5872
5873 err_register:
5874         ixgbe_release_hw_control(adapter);
5875         ixgbe_clear_interrupt_scheme(adapter);
5876 err_sw_init:
5877 err_eeprom:
5878         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5879         del_timer_sync(&adapter->sfp_timer);
5880         cancel_work_sync(&adapter->sfp_task);
5881         cancel_work_sync(&adapter->multispeed_fiber_task);
5882         cancel_work_sync(&adapter->sfp_config_module_task);
5883         iounmap(hw->hw_addr);
5884 err_ioremap:
5885         free_netdev(netdev);
5886 err_alloc_etherdev:
5887         pci_release_selected_regions(pdev, pci_select_bars(pdev,
5888                                      IORESOURCE_MEM));
5889 err_pci_reg:
5890 err_dma:
5891         pci_disable_device(pdev);
5892         return err;
5893 }
5894
5895 /**
5896  * ixgbe_remove - Device Removal Routine
5897  * @pdev: PCI device information struct
5898  *
5899  * ixgbe_remove is called by the PCI subsystem to alert the driver
5900  * that it should release a PCI device.  The could be caused by a
5901  * Hot-Plug event, or because the driver is going to be removed from
5902  * memory.
5903  **/
5904 static void __devexit ixgbe_remove(struct pci_dev *pdev)
5905 {
5906         struct net_device *netdev = pci_get_drvdata(pdev);
5907         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5908
5909         set_bit(__IXGBE_DOWN, &adapter->state);
5910         /* clear the module not found bit to make sure the worker won't
5911          * reschedule
5912          */
5913         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5914         del_timer_sync(&adapter->watchdog_timer);
5915
5916         del_timer_sync(&adapter->sfp_timer);
5917         cancel_work_sync(&adapter->watchdog_task);
5918         cancel_work_sync(&adapter->sfp_task);
5919         cancel_work_sync(&adapter->multispeed_fiber_task);
5920         cancel_work_sync(&adapter->sfp_config_module_task);
5921         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5922             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5923                 cancel_work_sync(&adapter->fdir_reinit_task);
5924         flush_scheduled_work();
5925
5926 #ifdef CONFIG_IXGBE_DCA
5927         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
5928                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
5929                 dca_remove_requester(&pdev->dev);
5930                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
5931         }
5932
5933 #endif
5934 #ifdef IXGBE_FCOE
5935         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
5936                 ixgbe_cleanup_fcoe(adapter);
5937
5938 #endif /* IXGBE_FCOE */
5939
5940         /* remove the added san mac */
5941         ixgbe_del_sanmac_netdev(netdev);
5942
5943         if (netdev->reg_state == NETREG_REGISTERED)
5944                 unregister_netdev(netdev);
5945
5946         ixgbe_clear_interrupt_scheme(adapter);
5947
5948         ixgbe_release_hw_control(adapter);
5949
5950         iounmap(adapter->hw.hw_addr);
5951         pci_release_selected_regions(pdev, pci_select_bars(pdev,
5952                                      IORESOURCE_MEM));
5953
5954         DPRINTK(PROBE, INFO, "complete\n");
5955
5956         free_netdev(netdev);
5957
5958         pci_disable_pcie_error_reporting(pdev);
5959
5960         pci_disable_device(pdev);
5961 }
5962
5963 /**
5964  * ixgbe_io_error_detected - called when PCI error is detected
5965  * @pdev: Pointer to PCI device
5966  * @state: The current pci connection state
5967  *
5968  * This function is called after a PCI bus error affecting
5969  * this device has been detected.
5970  */
5971 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
5972                                                 pci_channel_state_t state)
5973 {
5974         struct net_device *netdev = pci_get_drvdata(pdev);
5975         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5976
5977         netif_device_detach(netdev);
5978
5979         if (state == pci_channel_io_perm_failure)
5980                 return PCI_ERS_RESULT_DISCONNECT;
5981
5982         if (netif_running(netdev))
5983                 ixgbe_down(adapter);
5984         pci_disable_device(pdev);
5985
5986         /* Request a slot reset. */
5987         return PCI_ERS_RESULT_NEED_RESET;
5988 }
5989
5990 /**
5991  * ixgbe_io_slot_reset - called after the pci bus has been reset.
5992  * @pdev: Pointer to PCI device
5993  *
5994  * Restart the card from scratch, as if from a cold-boot.
5995  */
5996 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
5997 {
5998         struct net_device *netdev = pci_get_drvdata(pdev);
5999         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6000         pci_ers_result_t result;
6001         int err;
6002
6003         if (pci_enable_device_mem(pdev)) {
6004                 DPRINTK(PROBE, ERR,
6005                         "Cannot re-enable PCI device after reset.\n");
6006                 result = PCI_ERS_RESULT_DISCONNECT;
6007         } else {
6008                 pci_set_master(pdev);
6009                 pci_restore_state(pdev);
6010                 pci_save_state(pdev);
6011
6012                 pci_wake_from_d3(pdev, false);
6013
6014                 ixgbe_reset(adapter);
6015                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6016                 result = PCI_ERS_RESULT_RECOVERED;
6017         }
6018
6019         err = pci_cleanup_aer_uncorrect_error_status(pdev);
6020         if (err) {
6021                 dev_err(&pdev->dev,
6022                   "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
6023                 /* non-fatal, continue */
6024         }
6025
6026         return result;
6027 }
6028
6029 /**
6030  * ixgbe_io_resume - called when traffic can start flowing again.
6031  * @pdev: Pointer to PCI device
6032  *
6033  * This callback is called when the error recovery driver tells us that
6034  * its OK to resume normal operation.
6035  */
6036 static void ixgbe_io_resume(struct pci_dev *pdev)
6037 {
6038         struct net_device *netdev = pci_get_drvdata(pdev);
6039         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6040
6041         if (netif_running(netdev)) {
6042                 if (ixgbe_up(adapter)) {
6043                         DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
6044                         return;
6045                 }
6046         }
6047
6048         netif_device_attach(netdev);
6049 }
6050
6051 static struct pci_error_handlers ixgbe_err_handler = {
6052         .error_detected = ixgbe_io_error_detected,
6053         .slot_reset = ixgbe_io_slot_reset,
6054         .resume = ixgbe_io_resume,
6055 };
6056
6057 static struct pci_driver ixgbe_driver = {
6058         .name     = ixgbe_driver_name,
6059         .id_table = ixgbe_pci_tbl,
6060         .probe    = ixgbe_probe,
6061         .remove   = __devexit_p(ixgbe_remove),
6062 #ifdef CONFIG_PM
6063         .suspend  = ixgbe_suspend,
6064         .resume   = ixgbe_resume,
6065 #endif
6066         .shutdown = ixgbe_shutdown,
6067         .err_handler = &ixgbe_err_handler
6068 };
6069
6070 /**
6071  * ixgbe_init_module - Driver Registration Routine
6072  *
6073  * ixgbe_init_module is the first routine called when the driver is
6074  * loaded. All it does is register with the PCI subsystem.
6075  **/
6076 static int __init ixgbe_init_module(void)
6077 {
6078         int ret;
6079         printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
6080                ixgbe_driver_string, ixgbe_driver_version);
6081
6082         printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
6083
6084 #ifdef CONFIG_IXGBE_DCA
6085         dca_register_notify(&dca_notifier);
6086 #endif
6087
6088         ret = pci_register_driver(&ixgbe_driver);
6089         return ret;
6090 }
6091
6092 module_init(ixgbe_init_module);
6093
6094 /**
6095  * ixgbe_exit_module - Driver Exit Cleanup Routine
6096  *
6097  * ixgbe_exit_module is called just before the driver is removed
6098  * from memory.
6099  **/
6100 static void __exit ixgbe_exit_module(void)
6101 {
6102 #ifdef CONFIG_IXGBE_DCA
6103         dca_unregister_notify(&dca_notifier);
6104 #endif
6105         pci_unregister_driver(&ixgbe_driver);
6106 }
6107
6108 #ifdef CONFIG_IXGBE_DCA
6109 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
6110                             void *p)
6111 {
6112         int ret_val;
6113
6114         ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
6115                                          __ixgbe_notify_dca);
6116
6117         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
6118 }
6119
6120 #endif /* CONFIG_IXGBE_DCA */
6121 #ifdef DEBUG
6122 /**
6123  * ixgbe_get_hw_dev_name - return device name string
6124  * used by hardware layer to print debugging information
6125  **/
6126 char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
6127 {
6128         struct ixgbe_adapter *adapter = hw->back;
6129         return adapter->netdev->name;
6130 }
6131
6132 #endif
6133 module_exit(ixgbe_exit_module);
6134
6135 /* ixgbe_main.c */