1 /* Driver for TI CC2520 802.15.4 Wireless-PAN Networking controller
3 * Copyright (C) 2014 Varka Bhadram <varkab@cdac.in>
4 * Md.Jamal Mohiuddin <mjmohiuddin@cdac.in>
5 * P Sowjanya <sowjanyap@cdac.in>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/gpio.h>
16 #include <linux/delay.h>
17 #include <linux/spi/spi.h>
18 #include <linux/spi/cc2520.h>
19 #include <linux/workqueue.h>
20 #include <linux/interrupt.h>
21 #include <linux/skbuff.h>
22 #include <linux/of_gpio.h>
23 #include <linux/ieee802154.h>
25 #include <net/mac802154.h>
26 #include <net/cfg802154.h>
28 #define SPI_COMMAND_BUFFER 3
33 #define RSSI_OFFSET 78
35 #define CC2520_RAM_SIZE 640
36 #define CC2520_FIFO_SIZE 128
38 #define CC2520RAM_TXFIFO 0x100
39 #define CC2520RAM_RXFIFO 0x180
40 #define CC2520RAM_IEEEADDR 0x3EA
41 #define CC2520RAM_PANID 0x3F2
42 #define CC2520RAM_SHORTADDR 0x3F4
44 #define CC2520_FREG_MASK 0x3F
46 /* status byte values */
47 #define CC2520_STATUS_XOSC32M_STABLE BIT(7)
48 #define CC2520_STATUS_RSSI_VALID BIT(6)
49 #define CC2520_STATUS_TX_UNDERFLOW BIT(3)
51 /* IEEE-802.15.4 defined constants (2.4 GHz logical channels) */
52 #define CC2520_MINCHANNEL 11
53 #define CC2520_MAXCHANNEL 26
54 #define CC2520_CHANNEL_SPACING 5
57 #define CC2520_CMD_SNOP 0x00
58 #define CC2520_CMD_IBUFLD 0x02
59 #define CC2520_CMD_SIBUFEX 0x03
60 #define CC2520_CMD_SSAMPLECCA 0x04
61 #define CC2520_CMD_SRES 0x0f
62 #define CC2520_CMD_MEMORY_MASK 0x0f
63 #define CC2520_CMD_MEMORY_READ 0x10
64 #define CC2520_CMD_MEMORY_WRITE 0x20
65 #define CC2520_CMD_RXBUF 0x30
66 #define CC2520_CMD_RXBUFCP 0x38
67 #define CC2520_CMD_RXBUFMOV 0x32
68 #define CC2520_CMD_TXBUF 0x3A
69 #define CC2520_CMD_TXBUFCP 0x3E
70 #define CC2520_CMD_RANDOM 0x3C
71 #define CC2520_CMD_SXOSCON 0x40
72 #define CC2520_CMD_STXCAL 0x41
73 #define CC2520_CMD_SRXON 0x42
74 #define CC2520_CMD_STXON 0x43
75 #define CC2520_CMD_STXONCCA 0x44
76 #define CC2520_CMD_SRFOFF 0x45
77 #define CC2520_CMD_SXOSCOFF 0x46
78 #define CC2520_CMD_SFLUSHRX 0x47
79 #define CC2520_CMD_SFLUSHTX 0x48
80 #define CC2520_CMD_SACK 0x49
81 #define CC2520_CMD_SACKPEND 0x4A
82 #define CC2520_CMD_SNACK 0x4B
83 #define CC2520_CMD_SRXMASKBITSET 0x4C
84 #define CC2520_CMD_SRXMASKBITCLR 0x4D
85 #define CC2520_CMD_RXMASKAND 0x4E
86 #define CC2520_CMD_RXMASKOR 0x4F
87 #define CC2520_CMD_MEMCP 0x50
88 #define CC2520_CMD_MEMCPR 0x52
89 #define CC2520_CMD_MEMXCP 0x54
90 #define CC2520_CMD_MEMXWR 0x56
91 #define CC2520_CMD_BCLR 0x58
92 #define CC2520_CMD_BSET 0x59
93 #define CC2520_CMD_CTR_UCTR 0x60
94 #define CC2520_CMD_CBCMAC 0x64
95 #define CC2520_CMD_UCBCMAC 0x66
96 #define CC2520_CMD_CCM 0x68
97 #define CC2520_CMD_UCCM 0x6A
98 #define CC2520_CMD_ECB 0x70
99 #define CC2520_CMD_ECBO 0x72
100 #define CC2520_CMD_ECBX 0x74
101 #define CC2520_CMD_INC 0x78
102 #define CC2520_CMD_ABORT 0x7F
103 #define CC2520_CMD_REGISTER_READ 0x80
104 #define CC2520_CMD_REGISTER_WRITE 0xC0
106 /* status registers */
107 #define CC2520_CHIPID 0x40
108 #define CC2520_VERSION 0x42
109 #define CC2520_EXTCLOCK 0x44
110 #define CC2520_MDMCTRL0 0x46
111 #define CC2520_MDMCTRL1 0x47
112 #define CC2520_FREQEST 0x48
113 #define CC2520_RXCTRL 0x4A
114 #define CC2520_FSCTRL 0x4C
115 #define CC2520_FSCAL0 0x4E
116 #define CC2520_FSCAL1 0x4F
117 #define CC2520_FSCAL2 0x50
118 #define CC2520_FSCAL3 0x51
119 #define CC2520_AGCCTRL0 0x52
120 #define CC2520_AGCCTRL1 0x53
121 #define CC2520_AGCCTRL2 0x54
122 #define CC2520_AGCCTRL3 0x55
123 #define CC2520_ADCTEST0 0x56
124 #define CC2520_ADCTEST1 0x57
125 #define CC2520_ADCTEST2 0x58
126 #define CC2520_MDMTEST0 0x5A
127 #define CC2520_MDMTEST1 0x5B
128 #define CC2520_DACTEST0 0x5C
129 #define CC2520_DACTEST1 0x5D
130 #define CC2520_ATEST 0x5E
131 #define CC2520_DACTEST2 0x5F
132 #define CC2520_PTEST0 0x60
133 #define CC2520_PTEST1 0x61
134 #define CC2520_RESERVED 0x62
135 #define CC2520_DPUBIST 0x7A
136 #define CC2520_ACTBIST 0x7C
137 #define CC2520_RAMBIST 0x7E
139 /* frame registers */
140 #define CC2520_FRMFILT0 0x00
141 #define CC2520_FRMFILT1 0x01
142 #define CC2520_SRCMATCH 0x02
143 #define CC2520_SRCSHORTEN0 0x04
144 #define CC2520_SRCSHORTEN1 0x05
145 #define CC2520_SRCSHORTEN2 0x06
146 #define CC2520_SRCEXTEN0 0x08
147 #define CC2520_SRCEXTEN1 0x09
148 #define CC2520_SRCEXTEN2 0x0A
149 #define CC2520_FRMCTRL0 0x0C
150 #define CC2520_FRMCTRL1 0x0D
151 #define CC2520_RXENABLE0 0x0E
152 #define CC2520_RXENABLE1 0x0F
153 #define CC2520_EXCFLAG0 0x10
154 #define CC2520_EXCFLAG1 0x11
155 #define CC2520_EXCFLAG2 0x12
156 #define CC2520_EXCMASKA0 0x14
157 #define CC2520_EXCMASKA1 0x15
158 #define CC2520_EXCMASKA2 0x16
159 #define CC2520_EXCMASKB0 0x18
160 #define CC2520_EXCMASKB1 0x19
161 #define CC2520_EXCMASKB2 0x1A
162 #define CC2520_EXCBINDX0 0x1C
163 #define CC2520_EXCBINDX1 0x1D
164 #define CC2520_EXCBINDY0 0x1E
165 #define CC2520_EXCBINDY1 0x1F
166 #define CC2520_GPIOCTRL0 0x20
167 #define CC2520_GPIOCTRL1 0x21
168 #define CC2520_GPIOCTRL2 0x22
169 #define CC2520_GPIOCTRL3 0x23
170 #define CC2520_GPIOCTRL4 0x24
171 #define CC2520_GPIOCTRL5 0x25
172 #define CC2520_GPIOPOLARITY 0x26
173 #define CC2520_GPIOCTRL 0x28
174 #define CC2520_DPUCON 0x2A
175 #define CC2520_DPUSTAT 0x2C
176 #define CC2520_FREQCTRL 0x2E
177 #define CC2520_FREQTUNE 0x2F
178 #define CC2520_TXPOWER 0x30
179 #define CC2520_TXCTRL 0x31
180 #define CC2520_FSMSTAT0 0x32
181 #define CC2520_FSMSTAT1 0x33
182 #define CC2520_FIFOPCTRL 0x34
183 #define CC2520_FSMCTRL 0x35
184 #define CC2520_CCACTRL0 0x36
185 #define CC2520_CCACTRL1 0x37
186 #define CC2520_RSSI 0x38
187 #define CC2520_RSSISTAT 0x39
188 #define CC2520_RXFIRST 0x3C
189 #define CC2520_RXFIFOCNT 0x3E
190 #define CC2520_TXFIFOCNT 0x3F
192 /* Driver private information */
193 struct cc2520_private {
194 struct spi_device *spi; /* SPI device structure */
195 struct ieee802154_hw *hw; /* IEEE-802.15.4 device */
196 u8 *buf; /* SPI TX/Rx data buffer */
197 struct mutex buffer_mutex; /* SPI buffer mutex */
198 bool is_tx; /* Flag for sync b/w Tx and Rx */
199 bool amplified; /* Flag for CC2591 */
200 int fifo_pin; /* FIFO GPIO pin number */
201 struct work_struct fifop_irqwork;/* Workqueue for FIFOP */
202 spinlock_t lock; /* Lock for is_tx*/
203 struct completion tx_complete; /* Work completion for Tx */
206 /* Generic Functions */
208 cc2520_cmd_strobe(struct cc2520_private *priv, u8 cmd)
212 struct spi_message msg;
213 struct spi_transfer xfer = {
219 spi_message_init(&msg);
220 spi_message_add_tail(&xfer, &msg);
222 mutex_lock(&priv->buffer_mutex);
223 priv->buf[xfer.len++] = cmd;
224 dev_vdbg(&priv->spi->dev,
225 "command strobe buf[0] = %02x\n",
228 ret = spi_sync(priv->spi, &msg);
230 status = priv->buf[0];
231 dev_vdbg(&priv->spi->dev,
232 "buf[0] = %02x\n", priv->buf[0]);
233 mutex_unlock(&priv->buffer_mutex);
239 cc2520_get_status(struct cc2520_private *priv, u8 *status)
242 struct spi_message msg;
243 struct spi_transfer xfer = {
249 spi_message_init(&msg);
250 spi_message_add_tail(&xfer, &msg);
252 mutex_lock(&priv->buffer_mutex);
253 priv->buf[xfer.len++] = CC2520_CMD_SNOP;
254 dev_vdbg(&priv->spi->dev,
255 "get status command buf[0] = %02x\n", priv->buf[0]);
257 ret = spi_sync(priv->spi, &msg);
259 *status = priv->buf[0];
260 dev_vdbg(&priv->spi->dev,
261 "buf[0] = %02x\n", priv->buf[0]);
262 mutex_unlock(&priv->buffer_mutex);
268 cc2520_write_register(struct cc2520_private *priv, u8 reg, u8 value)
271 struct spi_message msg;
272 struct spi_transfer xfer = {
278 spi_message_init(&msg);
279 spi_message_add_tail(&xfer, &msg);
281 mutex_lock(&priv->buffer_mutex);
283 if (reg <= CC2520_FREG_MASK) {
284 priv->buf[xfer.len++] = CC2520_CMD_REGISTER_WRITE | reg;
285 priv->buf[xfer.len++] = value;
287 priv->buf[xfer.len++] = CC2520_CMD_MEMORY_WRITE;
288 priv->buf[xfer.len++] = reg;
289 priv->buf[xfer.len++] = value;
291 status = spi_sync(priv->spi, &msg);
295 mutex_unlock(&priv->buffer_mutex);
301 cc2520_write_ram(struct cc2520_private *priv, u16 reg, u8 len, u8 *data)
304 struct spi_message msg;
305 struct spi_transfer xfer_head = {
311 struct spi_transfer xfer_buf = {
316 mutex_lock(&priv->buffer_mutex);
317 priv->buf[xfer_head.len++] = (CC2520_CMD_MEMORY_WRITE |
318 ((reg >> 8) & 0xff));
319 priv->buf[xfer_head.len++] = reg & 0xff;
321 spi_message_init(&msg);
322 spi_message_add_tail(&xfer_head, &msg);
323 spi_message_add_tail(&xfer_buf, &msg);
325 status = spi_sync(priv->spi, &msg);
326 dev_dbg(&priv->spi->dev, "spi status = %d\n", status);
330 mutex_unlock(&priv->buffer_mutex);
335 cc2520_read_register(struct cc2520_private *priv, u8 reg, u8 *data)
338 struct spi_message msg;
339 struct spi_transfer xfer1 = {
345 struct spi_transfer xfer2 = {
350 spi_message_init(&msg);
351 spi_message_add_tail(&xfer1, &msg);
352 spi_message_add_tail(&xfer2, &msg);
354 mutex_lock(&priv->buffer_mutex);
355 priv->buf[xfer1.len++] = CC2520_CMD_MEMORY_READ;
356 priv->buf[xfer1.len++] = reg;
358 status = spi_sync(priv->spi, &msg);
359 dev_dbg(&priv->spi->dev,
360 "spi status = %d\n", status);
364 mutex_unlock(&priv->buffer_mutex);
370 cc2520_write_txfifo(struct cc2520_private *priv, u8 *data, u8 len)
374 /* length byte must include FCS even
375 * if it is calculated in the hardware
377 int len_byte = len + 2;
379 struct spi_message msg;
381 struct spi_transfer xfer_head = {
386 struct spi_transfer xfer_len = {
390 struct spi_transfer xfer_buf = {
395 spi_message_init(&msg);
396 spi_message_add_tail(&xfer_head, &msg);
397 spi_message_add_tail(&xfer_len, &msg);
398 spi_message_add_tail(&xfer_buf, &msg);
400 mutex_lock(&priv->buffer_mutex);
401 priv->buf[xfer_head.len++] = CC2520_CMD_TXBUF;
402 dev_vdbg(&priv->spi->dev,
403 "TX_FIFO cmd buf[0] = %02x\n", priv->buf[0]);
405 status = spi_sync(priv->spi, &msg);
406 dev_vdbg(&priv->spi->dev, "status = %d\n", status);
409 dev_vdbg(&priv->spi->dev, "status = %d\n", status);
410 dev_vdbg(&priv->spi->dev, "buf[0] = %02x\n", priv->buf[0]);
411 mutex_unlock(&priv->buffer_mutex);
417 cc2520_read_rxfifo(struct cc2520_private *priv, u8 *data, u8 len, u8 *lqi)
420 struct spi_message msg;
422 struct spi_transfer xfer_head = {
427 struct spi_transfer xfer_buf = {
432 spi_message_init(&msg);
433 spi_message_add_tail(&xfer_head, &msg);
434 spi_message_add_tail(&xfer_buf, &msg);
436 mutex_lock(&priv->buffer_mutex);
437 priv->buf[xfer_head.len++] = CC2520_CMD_RXBUF;
439 dev_vdbg(&priv->spi->dev, "read rxfifo buf[0] = %02x\n", priv->buf[0]);
440 dev_vdbg(&priv->spi->dev, "buf[1] = %02x\n", priv->buf[1]);
442 status = spi_sync(priv->spi, &msg);
443 dev_vdbg(&priv->spi->dev, "status = %d\n", status);
446 dev_vdbg(&priv->spi->dev, "status = %d\n", status);
447 dev_vdbg(&priv->spi->dev,
448 "return status buf[0] = %02x\n", priv->buf[0]);
449 dev_vdbg(&priv->spi->dev, "length buf[1] = %02x\n", priv->buf[1]);
451 mutex_unlock(&priv->buffer_mutex);
456 static int cc2520_start(struct ieee802154_hw *hw)
458 return cc2520_cmd_strobe(hw->priv, CC2520_CMD_SRXON);
461 static void cc2520_stop(struct ieee802154_hw *hw)
463 cc2520_cmd_strobe(hw->priv, CC2520_CMD_SRFOFF);
467 cc2520_tx(struct ieee802154_hw *hw, struct sk_buff *skb)
469 struct cc2520_private *priv = hw->priv;
474 rc = cc2520_cmd_strobe(priv, CC2520_CMD_SFLUSHTX);
478 rc = cc2520_write_txfifo(priv, skb->data, skb->len);
482 rc = cc2520_get_status(priv, &status);
486 if (status & CC2520_STATUS_TX_UNDERFLOW) {
487 dev_err(&priv->spi->dev, "cc2520 tx underflow exception\n");
491 spin_lock_irqsave(&priv->lock, flags);
494 spin_unlock_irqrestore(&priv->lock, flags);
496 rc = cc2520_cmd_strobe(priv, CC2520_CMD_STXONCCA);
500 rc = wait_for_completion_interruptible(&priv->tx_complete);
504 cc2520_cmd_strobe(priv, CC2520_CMD_SFLUSHTX);
505 cc2520_cmd_strobe(priv, CC2520_CMD_SRXON);
509 spin_lock_irqsave(&priv->lock, flags);
511 spin_unlock_irqrestore(&priv->lock, flags);
516 static int cc2520_rx(struct cc2520_private *priv)
518 u8 len = 0, lqi = 0, bytes = 1;
521 cc2520_read_rxfifo(priv, &len, bytes, &lqi);
523 if (len < 2 || len > IEEE802154_MTU)
526 skb = dev_alloc_skb(len);
530 if (cc2520_read_rxfifo(priv, skb_put(skb, len), len, &lqi)) {
531 dev_dbg(&priv->spi->dev, "frame reception failed\n");
536 skb_trim(skb, skb->len - 2);
538 ieee802154_rx_irqsafe(priv->hw, skb, lqi);
540 dev_vdbg(&priv->spi->dev, "RXFIFO: %x %x\n", len, lqi);
546 cc2520_ed(struct ieee802154_hw *hw, u8 *level)
548 struct cc2520_private *priv = hw->priv;
553 ret = cc2520_read_register(priv, CC2520_RSSISTAT, &status);
557 if (status != RSSI_VALID)
560 ret = cc2520_read_register(priv, CC2520_RSSI, &rssi);
564 /* level = RSSI(rssi) - OFFSET [dBm] : offset is 76dBm */
565 *level = rssi - RSSI_OFFSET;
571 cc2520_set_channel(struct ieee802154_hw *hw, u8 page, u8 channel)
573 struct cc2520_private *priv = hw->priv;
576 dev_dbg(&priv->spi->dev, "trying to set channel\n");
579 BUG_ON(channel < CC2520_MINCHANNEL);
580 BUG_ON(channel > CC2520_MAXCHANNEL);
582 ret = cc2520_write_register(priv, CC2520_FREQCTRL,
583 11 + 5*(channel - 11));
589 cc2520_filter(struct ieee802154_hw *hw,
590 struct ieee802154_hw_addr_filt *filt, unsigned long changed)
592 struct cc2520_private *priv = hw->priv;
594 if (changed & IEEE802154_AFILT_PANID_CHANGED) {
595 u16 panid = le16_to_cpu(filt->pan_id);
597 dev_vdbg(&priv->spi->dev,
598 "cc2520_filter called for pan id\n");
599 cc2520_write_ram(priv, CC2520RAM_PANID,
600 sizeof(panid), (u8 *)&panid);
603 if (changed & IEEE802154_AFILT_IEEEADDR_CHANGED) {
604 dev_vdbg(&priv->spi->dev,
605 "cc2520_filter called for IEEE addr\n");
606 cc2520_write_ram(priv, CC2520RAM_IEEEADDR,
607 sizeof(filt->ieee_addr),
608 (u8 *)&filt->ieee_addr);
611 if (changed & IEEE802154_AFILT_SADDR_CHANGED) {
612 u16 addr = le16_to_cpu(filt->short_addr);
614 dev_vdbg(&priv->spi->dev,
615 "cc2520_filter called for saddr\n");
616 cc2520_write_ram(priv, CC2520RAM_SHORTADDR,
617 sizeof(addr), (u8 *)&addr);
620 if (changed & IEEE802154_AFILT_PANC_CHANGED) {
621 dev_vdbg(&priv->spi->dev,
622 "cc2520_filter called for panc change\n");
624 cc2520_write_register(priv, CC2520_FRMFILT0, 0x02);
626 cc2520_write_register(priv, CC2520_FRMFILT0, 0x00);
632 static inline int cc2520_set_tx_power(struct cc2520_private *priv, s32 mbm)
668 return cc2520_write_register(priv, CC2520_TXPOWER, power);
671 static inline int cc2520_cc2591_set_tx_power(struct cc2520_private *priv,
699 return cc2520_write_register(priv, CC2520_TXPOWER, power);
702 #define CC2520_MAX_TX_POWERS 0x8
703 static const s32 cc2520_powers[CC2520_MAX_TX_POWERS + 1] = {
704 500, 300, 200, 100, 0, -200, -400, -700, -1800,
707 #define CC2520_CC2591_MAX_TX_POWERS 0x5
708 static const s32 cc2520_cc2591_powers[CC2520_CC2591_MAX_TX_POWERS + 1] = {
709 1700, 1600, 1400, 1100, -100, -800,
713 cc2520_set_txpower(struct ieee802154_hw *hw, s32 mbm)
715 struct cc2520_private *priv = hw->priv;
717 if (!priv->amplified)
718 return cc2520_set_tx_power(priv, mbm);
720 return cc2520_cc2591_set_tx_power(priv, mbm);
723 static const struct ieee802154_ops cc2520_ops = {
724 .owner = THIS_MODULE,
725 .start = cc2520_start,
727 .xmit_sync = cc2520_tx,
729 .set_channel = cc2520_set_channel,
730 .set_hw_addr_filt = cc2520_filter,
731 .set_txpower = cc2520_set_txpower,
734 static int cc2520_register(struct cc2520_private *priv)
738 priv->hw = ieee802154_alloc_hw(sizeof(*priv), &cc2520_ops);
742 priv->hw->priv = priv;
743 priv->hw->parent = &priv->spi->dev;
744 priv->hw->extra_tx_headroom = 0;
745 priv->hw->vif_data_size = sizeof(*priv);
746 ieee802154_random_extended_addr(&priv->hw->phy->perm_extended_addr);
748 /* We do support only 2.4 Ghz */
749 priv->hw->phy->supported.channels[0] = 0x7FFF800;
750 priv->hw->flags = IEEE802154_HW_OMIT_CKSUM | IEEE802154_HW_AACK |
753 priv->hw->phy->flags = WPAN_PHY_FLAG_TXPOWER;
755 if (!priv->amplified) {
756 priv->hw->phy->supported.tx_powers = cc2520_powers;
757 priv->hw->phy->supported.tx_powers_size = ARRAY_SIZE(cc2520_powers);
758 priv->hw->phy->transmit_power = priv->hw->phy->supported.tx_powers[4];
760 priv->hw->phy->supported.tx_powers = cc2520_cc2591_powers;
761 priv->hw->phy->supported.tx_powers_size = ARRAY_SIZE(cc2520_cc2591_powers);
762 priv->hw->phy->transmit_power = priv->hw->phy->supported.tx_powers[0];
765 dev_vdbg(&priv->spi->dev, "registered cc2520\n");
766 ret = ieee802154_register_hw(priv->hw);
768 goto err_free_device;
773 ieee802154_free_hw(priv->hw);
778 static void cc2520_fifop_irqwork(struct work_struct *work)
780 struct cc2520_private *priv
781 = container_of(work, struct cc2520_private, fifop_irqwork);
783 dev_dbg(&priv->spi->dev, "fifop interrupt received\n");
785 if (gpio_get_value(priv->fifo_pin))
788 dev_dbg(&priv->spi->dev, "rxfifo overflow\n");
790 cc2520_cmd_strobe(priv, CC2520_CMD_SFLUSHRX);
791 cc2520_cmd_strobe(priv, CC2520_CMD_SFLUSHRX);
794 static irqreturn_t cc2520_fifop_isr(int irq, void *data)
796 struct cc2520_private *priv = data;
798 schedule_work(&priv->fifop_irqwork);
803 static irqreturn_t cc2520_sfd_isr(int irq, void *data)
805 struct cc2520_private *priv = data;
808 spin_lock_irqsave(&priv->lock, flags);
811 spin_unlock_irqrestore(&priv->lock, flags);
812 dev_dbg(&priv->spi->dev, "SFD for TX\n");
813 complete(&priv->tx_complete);
815 spin_unlock_irqrestore(&priv->lock, flags);
816 dev_dbg(&priv->spi->dev, "SFD for RX\n");
822 static int cc2520_get_platform_data(struct spi_device *spi,
823 struct cc2520_platform_data *pdata)
825 struct device_node *np = spi->dev.of_node;
826 struct cc2520_private *priv = spi_get_drvdata(spi);
829 struct cc2520_platform_data *spi_pdata = spi->dev.platform_data;
836 pdata->fifo = of_get_named_gpio(np, "fifo-gpio", 0);
837 priv->fifo_pin = pdata->fifo;
839 pdata->fifop = of_get_named_gpio(np, "fifop-gpio", 0);
841 pdata->sfd = of_get_named_gpio(np, "sfd-gpio", 0);
842 pdata->cca = of_get_named_gpio(np, "cca-gpio", 0);
843 pdata->vreg = of_get_named_gpio(np, "vreg-gpio", 0);
844 pdata->reset = of_get_named_gpio(np, "reset-gpio", 0);
846 /* CC2591 front end for CC2520 */
847 if (of_property_read_bool(np, "amplified"))
848 priv->amplified = true;
853 static int cc2520_hw_init(struct cc2520_private *priv)
855 u8 status = 0, state = 0xff;
858 struct cc2520_platform_data pdata;
860 ret = cc2520_get_platform_data(priv->spi, &pdata);
864 ret = cc2520_read_register(priv, CC2520_FSMSTAT1, &state);
868 if (state != STATE_IDLE)
872 ret = cc2520_get_status(priv, &status);
876 if (timeout-- <= 0) {
877 dev_err(&priv->spi->dev, "oscillator start failed!\n");
881 } while (!(status & CC2520_STATUS_XOSC32M_STABLE));
883 dev_vdbg(&priv->spi->dev, "oscillator brought up\n");
885 /* If the CC2520 is connected to a CC2591 amplifier, we must both
886 * configure GPIOs on the CC2520 to correctly configure the CC2591
887 * and change a couple settings of the CC2520 to work with the
888 * amplifier. See section 8 page 17 of TI application note AN065.
889 * http://www.ti.com/lit/an/swra229a/swra229a.pdf
891 if (priv->amplified) {
892 ret = cc2520_write_register(priv, CC2520_AGCCTRL1, 0x16);
896 ret = cc2520_write_register(priv, CC2520_GPIOCTRL0, 0x46);
900 ret = cc2520_write_register(priv, CC2520_GPIOCTRL5, 0x47);
904 ret = cc2520_write_register(priv, CC2520_GPIOPOLARITY, 0x1e);
908 ret = cc2520_write_register(priv, CC2520_TXCTRL, 0xc1);
912 ret = cc2520_write_register(priv, CC2520_AGCCTRL1, 0x11);
917 /* Registers default value: section 28.1 in Datasheet */
918 ret = cc2520_write_register(priv, CC2520_CCACTRL0, 0x1A);
922 ret = cc2520_write_register(priv, CC2520_MDMCTRL0, 0x85);
926 ret = cc2520_write_register(priv, CC2520_MDMCTRL1, 0x14);
930 ret = cc2520_write_register(priv, CC2520_RXCTRL, 0x3f);
934 ret = cc2520_write_register(priv, CC2520_FSCTRL, 0x5a);
938 ret = cc2520_write_register(priv, CC2520_FSCAL1, 0x2b);
942 ret = cc2520_write_register(priv, CC2520_ADCTEST0, 0x10);
946 ret = cc2520_write_register(priv, CC2520_ADCTEST1, 0x0e);
950 ret = cc2520_write_register(priv, CC2520_ADCTEST2, 0x03);
954 ret = cc2520_write_register(priv, CC2520_FRMCTRL0, 0x60);
958 ret = cc2520_write_register(priv, CC2520_FRMCTRL1, 0x03);
962 ret = cc2520_write_register(priv, CC2520_FRMFILT0, 0x00);
966 ret = cc2520_write_register(priv, CC2520_FIFOPCTRL, 127);
976 static int cc2520_probe(struct spi_device *spi)
978 struct cc2520_private *priv;
979 struct cc2520_platform_data pdata;
982 priv = devm_kzalloc(&spi->dev, sizeof(*priv), GFP_KERNEL);
986 spi_set_drvdata(spi, priv);
988 ret = cc2520_get_platform_data(spi, &pdata);
990 dev_err(&spi->dev, "no platform data\n");
996 priv->buf = devm_kzalloc(&spi->dev,
997 SPI_COMMAND_BUFFER, GFP_KERNEL);
1001 mutex_init(&priv->buffer_mutex);
1002 INIT_WORK(&priv->fifop_irqwork, cc2520_fifop_irqwork);
1003 spin_lock_init(&priv->lock);
1004 init_completion(&priv->tx_complete);
1006 /* Assumption that CC2591 is not connected */
1007 priv->amplified = false;
1009 /* Request all the gpio's */
1010 if (!gpio_is_valid(pdata.fifo)) {
1011 dev_err(&spi->dev, "fifo gpio is not valid\n");
1016 ret = devm_gpio_request_one(&spi->dev, pdata.fifo,
1021 if (!gpio_is_valid(pdata.cca)) {
1022 dev_err(&spi->dev, "cca gpio is not valid\n");
1027 ret = devm_gpio_request_one(&spi->dev, pdata.cca,
1032 if (!gpio_is_valid(pdata.fifop)) {
1033 dev_err(&spi->dev, "fifop gpio is not valid\n");
1038 ret = devm_gpio_request_one(&spi->dev, pdata.fifop,
1043 if (!gpio_is_valid(pdata.sfd)) {
1044 dev_err(&spi->dev, "sfd gpio is not valid\n");
1049 ret = devm_gpio_request_one(&spi->dev, pdata.sfd,
1054 if (!gpio_is_valid(pdata.reset)) {
1055 dev_err(&spi->dev, "reset gpio is not valid\n");
1060 ret = devm_gpio_request_one(&spi->dev, pdata.reset,
1061 GPIOF_OUT_INIT_LOW, "reset");
1065 if (!gpio_is_valid(pdata.vreg)) {
1066 dev_err(&spi->dev, "vreg gpio is not valid\n");
1071 ret = devm_gpio_request_one(&spi->dev, pdata.vreg,
1072 GPIOF_OUT_INIT_LOW, "vreg");
1076 gpio_set_value(pdata.vreg, HIGH);
1077 usleep_range(100, 150);
1079 gpio_set_value(pdata.reset, HIGH);
1080 usleep_range(200, 250);
1082 ret = cc2520_hw_init(priv);
1086 /* Set up fifop interrupt */
1087 ret = devm_request_irq(&spi->dev,
1088 gpio_to_irq(pdata.fifop),
1090 IRQF_TRIGGER_RISING,
1091 dev_name(&spi->dev),
1094 dev_err(&spi->dev, "could not get fifop irq\n");
1098 /* Set up sfd interrupt */
1099 ret = devm_request_irq(&spi->dev,
1100 gpio_to_irq(pdata.sfd),
1102 IRQF_TRIGGER_FALLING,
1103 dev_name(&spi->dev),
1106 dev_err(&spi->dev, "could not get sfd irq\n");
1110 ret = cc2520_register(priv);
1117 mutex_destroy(&priv->buffer_mutex);
1118 flush_work(&priv->fifop_irqwork);
1122 static int cc2520_remove(struct spi_device *spi)
1124 struct cc2520_private *priv = spi_get_drvdata(spi);
1126 mutex_destroy(&priv->buffer_mutex);
1127 flush_work(&priv->fifop_irqwork);
1129 ieee802154_unregister_hw(priv->hw);
1130 ieee802154_free_hw(priv->hw);
1135 static const struct spi_device_id cc2520_ids[] = {
1139 MODULE_DEVICE_TABLE(spi, cc2520_ids);
1141 static const struct of_device_id cc2520_of_ids[] = {
1142 {.compatible = "ti,cc2520", },
1145 MODULE_DEVICE_TABLE(of, cc2520_of_ids);
1147 /* SPI driver structure */
1148 static struct spi_driver cc2520_driver = {
1151 .bus = &spi_bus_type,
1152 .owner = THIS_MODULE,
1153 .of_match_table = of_match_ptr(cc2520_of_ids),
1155 .id_table = cc2520_ids,
1156 .probe = cc2520_probe,
1157 .remove = cc2520_remove,
1159 module_spi_driver(cc2520_driver);
1161 MODULE_AUTHOR("Varka Bhadram <varkab@cdac.in>");
1162 MODULE_DESCRIPTION("CC2520 Transceiver Driver");
1163 MODULE_LICENSE("GPL v2");