2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/string.h>
25 #include <linux/ptrace.h>
26 #include <linux/errno.h>
27 #include <linux/ioport.h>
28 #include <linux/slab.h>
29 #include <linux/interrupt.h>
30 #include <linux/pci.h>
31 #include <linux/init.h>
32 #include <linux/delay.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/skbuff.h>
36 #include <linux/spinlock.h>
37 #include <linux/workqueue.h>
38 #include <linux/bitops.h>
40 #include <linux/irq.h>
41 #include <linux/clk.h>
43 #include <asm/cacheflush.h>
45 #ifndef CONFIG_ARCH_MXC
46 #include <asm/coldfire.h>
47 #include <asm/mcfsim.h>
52 #if defined(CONFIG_FEC2)
53 #define FEC_MAX_PORTS 2
55 #define FEC_MAX_PORTS 1
58 #ifdef CONFIG_ARCH_MXC
59 #include <mach/hardware.h>
60 #define FEC_ALIGNMENT 0xf
62 #define FEC_ALIGNMENT 0x3
65 #if defined(CONFIG_M5272)
66 #define HAVE_mii_link_interrupt
70 * Define the fixed address of the FEC hardware.
72 static unsigned int fec_hw[] = {
73 #if defined(CONFIG_M5272)
75 #elif defined(CONFIG_M527x)
78 #elif defined(CONFIG_M523x) || defined(CONFIG_M528x)
80 #elif defined(CONFIG_M520x)
82 #elif defined(CONFIG_M532x)
83 (MCF_MBAR+0xfc030000),
87 static unsigned char fec_mac_default[] = {
88 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
92 * Some hardware gets it MAC address out of local flash memory.
93 * if this is non-zero then assume it is the address to get MAC from.
95 #if defined(CONFIG_NETtel)
96 #define FEC_FLASHMAC 0xf0006006
97 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
98 #define FEC_FLASHMAC 0xf0006000
99 #elif defined(CONFIG_CANCam)
100 #define FEC_FLASHMAC 0xf0020000
101 #elif defined (CONFIG_M5272C3)
102 #define FEC_FLASHMAC (0xffe04000 + 4)
103 #elif defined(CONFIG_MOD5272)
104 #define FEC_FLASHMAC 0xffc0406b
106 #define FEC_FLASHMAC 0
109 /* Forward declarations of some structures to support different PHYs
114 void (*funct)(uint mii_reg, struct net_device *dev);
121 const phy_cmd_t *config;
122 const phy_cmd_t *startup;
123 const phy_cmd_t *ack_int;
124 const phy_cmd_t *shutdown;
127 /* The number of Tx and Rx buffers. These are allocated from the page
128 * pool. The code may assume these are power of two, so it it best
129 * to keep them that size.
130 * We don't need to allocate pages for the transmitter. We just use
131 * the skbuffer directly.
133 #define FEC_ENET_RX_PAGES 8
134 #define FEC_ENET_RX_FRSIZE 2048
135 #define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE)
136 #define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
137 #define FEC_ENET_TX_FRSIZE 2048
138 #define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE)
139 #define TX_RING_SIZE 16 /* Must be power of two */
140 #define TX_RING_MOD_MASK 15 /* for this to work */
142 #if (((RX_RING_SIZE + TX_RING_SIZE) * 8) > PAGE_SIZE)
143 #error "FEC: descriptor ring size constants too large"
146 /* Interrupt events/masks.
148 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
149 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
150 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
151 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
152 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
153 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
154 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
155 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
156 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
157 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
159 /* The FEC stores dest/src/type, data, and checksum for receive packets.
161 #define PKT_MAXBUF_SIZE 1518
162 #define PKT_MINBUF_SIZE 64
163 #define PKT_MAXBLR_SIZE 1520
167 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
168 * size bits. Other FEC hardware does not, so we need to take that into
169 * account when setting it.
171 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
172 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARCH_MXC)
173 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
175 #define OPT_FRAME_SIZE 0
178 /* The FEC buffer descriptors track the ring buffers. The rx_bd_base and
179 * tx_bd_base always point to the base of the buffer descriptors. The
180 * cur_rx and cur_tx point to the currently available buffer.
181 * The dirty_tx tracks the current buffer that is being sent by the
182 * controller. The cur_tx and dirty_tx are equal under both completely
183 * empty and completely full conditions. The empty/ready indicator in
184 * the buffer descriptor determines the actual condition.
186 struct fec_enet_private {
187 /* Hardware registers of the FEC device */
190 struct net_device *netdev;
192 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
193 unsigned char *tx_bounce[TX_RING_SIZE];
194 struct sk_buff* tx_skbuff[TX_RING_SIZE];
198 /* CPM dual port RAM relative addresses.
201 cbd_t *rx_bd_base; /* Address of Rx and Tx buffers. */
203 cbd_t *cur_rx, *cur_tx; /* The next free ring entry */
204 cbd_t *dirty_tx; /* The ring entries to be free()ed. */
206 /* hold while accessing the HW like ringbuffer for tx/rx but not MAC */
208 /* hold while accessing the mii_list_t() elements */
215 phy_info_t const *phy;
216 struct work_struct phy_task;
219 uint mii_phy_task_queued;
230 static int fec_enet_open(struct net_device *dev);
231 static int fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev);
232 static void fec_enet_mii(struct net_device *dev);
233 static irqreturn_t fec_enet_interrupt(int irq, void * dev_id);
234 static void fec_enet_tx(struct net_device *dev);
235 static void fec_enet_rx(struct net_device *dev);
236 static int fec_enet_close(struct net_device *dev);
237 static void set_multicast_list(struct net_device *dev);
238 static void fec_restart(struct net_device *dev, int duplex);
239 static void fec_stop(struct net_device *dev);
240 static void fec_set_mac_address(struct net_device *dev);
243 /* MII processing. We keep this as simple as possible. Requests are
244 * placed on the list (if there is room). When the request is finished
245 * by the MII, an optional function may be called.
247 typedef struct mii_list {
249 void (*mii_func)(uint val, struct net_device *dev);
250 struct mii_list *mii_next;
254 static mii_list_t mii_cmds[NMII];
255 static mii_list_t *mii_free;
256 static mii_list_t *mii_head;
257 static mii_list_t *mii_tail;
259 static int mii_queue(struct net_device *dev, int request,
260 void (*func)(uint, struct net_device *));
262 /* Make MII read/write commands for the FEC.
264 #define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18))
265 #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | \
269 /* Transmitter timeout.
271 #define TX_TIMEOUT (2*HZ)
273 /* Register definitions for the PHY.
276 #define MII_REG_CR 0 /* Control Register */
277 #define MII_REG_SR 1 /* Status Register */
278 #define MII_REG_PHYIR1 2 /* PHY Identification Register 1 */
279 #define MII_REG_PHYIR2 3 /* PHY Identification Register 2 */
280 #define MII_REG_ANAR 4 /* A-N Advertisement Register */
281 #define MII_REG_ANLPAR 5 /* A-N Link Partner Ability Register */
282 #define MII_REG_ANER 6 /* A-N Expansion Register */
283 #define MII_REG_ANNPTR 7 /* A-N Next Page Transmit Register */
284 #define MII_REG_ANLPRNPR 8 /* A-N Link Partner Received Next Page Reg. */
286 /* values for phy_status */
288 #define PHY_CONF_ANE 0x0001 /* 1 auto-negotiation enabled */
289 #define PHY_CONF_LOOP 0x0002 /* 1 loopback mode enabled */
290 #define PHY_CONF_SPMASK 0x00f0 /* mask for speed */
291 #define PHY_CONF_10HDX 0x0010 /* 10 Mbit half duplex supported */
292 #define PHY_CONF_10FDX 0x0020 /* 10 Mbit full duplex supported */
293 #define PHY_CONF_100HDX 0x0040 /* 100 Mbit half duplex supported */
294 #define PHY_CONF_100FDX 0x0080 /* 100 Mbit full duplex supported */
296 #define PHY_STAT_LINK 0x0100 /* 1 up - 0 down */
297 #define PHY_STAT_FAULT 0x0200 /* 1 remote fault */
298 #define PHY_STAT_ANC 0x0400 /* 1 auto-negotiation complete */
299 #define PHY_STAT_SPMASK 0xf000 /* mask for speed */
300 #define PHY_STAT_10HDX 0x1000 /* 10 Mbit half duplex selected */
301 #define PHY_STAT_10FDX 0x2000 /* 10 Mbit full duplex selected */
302 #define PHY_STAT_100HDX 0x4000 /* 100 Mbit half duplex selected */
303 #define PHY_STAT_100FDX 0x8000 /* 100 Mbit full duplex selected */
307 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
309 struct fec_enet_private *fep;
310 volatile fec_t *fecp;
312 unsigned short status;
315 fep = netdev_priv(dev);
316 fecp = (volatile fec_t*)dev->base_addr;
319 /* Link is down or autonegotiation is in progress. */
323 spin_lock_irqsave(&fep->hw_lock, flags);
324 /* Fill in a Tx ring entry */
327 status = bdp->cbd_sc;
328 #ifndef final_version
329 if (status & BD_ENET_TX_READY) {
330 /* Ooops. All transmit buffers are full. Bail out.
331 * This should not happen, since dev->tbusy should be set.
333 printk("%s: tx queue full!.\n", dev->name);
334 spin_unlock_irqrestore(&fep->hw_lock, flags);
339 /* Clear all of the status flags.
341 status &= ~BD_ENET_TX_STATS;
343 /* Set buffer length and buffer pointer.
345 bdp->cbd_bufaddr = __pa(skb->data);
346 bdp->cbd_datlen = skb->len;
349 * On some FEC implementations data must be aligned on
350 * 4-byte boundaries. Use bounce buffers to copy data
351 * and get it aligned. Ugh.
353 if (bdp->cbd_bufaddr & FEC_ALIGNMENT) {
355 index = bdp - fep->tx_bd_base;
356 memcpy(fep->tx_bounce[index], (void *)skb->data, skb->len);
357 bdp->cbd_bufaddr = __pa(fep->tx_bounce[index]);
362 fep->tx_skbuff[fep->skb_cur] = skb;
364 dev->stats.tx_bytes += skb->len;
365 fep->skb_cur = (fep->skb_cur+1) & TX_RING_MOD_MASK;
367 /* Push the data cache so the CPM does not get stale memory
370 dma_sync_single(NULL, bdp->cbd_bufaddr,
371 bdp->cbd_datlen, DMA_TO_DEVICE);
373 /* Send it on its way. Tell FEC it's ready, interrupt when done,
374 * it's the last BD of the frame, and to put the CRC on the end.
377 status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR
378 | BD_ENET_TX_LAST | BD_ENET_TX_TC);
379 bdp->cbd_sc = status;
381 dev->trans_start = jiffies;
383 /* Trigger transmission start */
384 fecp->fec_x_des_active = 0;
386 /* If this was the last BD in the ring, start at the beginning again.
388 if (status & BD_ENET_TX_WRAP) {
389 bdp = fep->tx_bd_base;
394 if (bdp == fep->dirty_tx) {
396 netif_stop_queue(dev);
399 fep->cur_tx = (cbd_t *)bdp;
401 spin_unlock_irqrestore(&fep->hw_lock, flags);
407 fec_timeout(struct net_device *dev)
409 struct fec_enet_private *fep = netdev_priv(dev);
411 printk("%s: transmit timed out.\n", dev->name);
412 dev->stats.tx_errors++;
413 #ifndef final_version
418 printk("Ring data dump: cur_tx %lx%s, dirty_tx %lx cur_rx: %lx\n",
419 (unsigned long)fep->cur_tx, fep->tx_full ? " (full)" : "",
420 (unsigned long)fep->dirty_tx,
421 (unsigned long)fep->cur_rx);
423 bdp = fep->tx_bd_base;
424 printk(" tx: %u buffers\n", TX_RING_SIZE);
425 for (i = 0 ; i < TX_RING_SIZE; i++) {
426 printk(" %08x: %04x %04x %08x\n",
430 (int) bdp->cbd_bufaddr);
434 bdp = fep->rx_bd_base;
435 printk(" rx: %lu buffers\n", (unsigned long) RX_RING_SIZE);
436 for (i = 0 ; i < RX_RING_SIZE; i++) {
437 printk(" %08x: %04x %04x %08x\n",
441 (int) bdp->cbd_bufaddr);
446 fec_restart(dev, fep->full_duplex);
447 netif_wake_queue(dev);
450 /* The interrupt handler.
451 * This is called from the MPC core interrupt.
454 fec_enet_interrupt(int irq, void * dev_id)
456 struct net_device *dev = dev_id;
457 volatile fec_t *fecp;
459 irqreturn_t ret = IRQ_NONE;
461 fecp = (volatile fec_t*)dev->base_addr;
463 /* Get the interrupt events that caused us to be here.
466 int_events = fecp->fec_ievent;
467 fecp->fec_ievent = int_events;
469 /* Handle receive event in its own function.
471 if (int_events & FEC_ENET_RXF) {
476 /* Transmit OK, or non-fatal error. Update the buffer
477 descriptors. FEC handles all errors, we just discover
478 them as part of the transmit process.
480 if (int_events & FEC_ENET_TXF) {
485 if (int_events & FEC_ENET_MII) {
490 } while (int_events);
497 fec_enet_tx(struct net_device *dev)
499 struct fec_enet_private *fep;
501 unsigned short status;
504 fep = netdev_priv(dev);
505 spin_lock_irq(&fep->hw_lock);
508 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
509 if (bdp == fep->cur_tx && fep->tx_full == 0) break;
511 skb = fep->tx_skbuff[fep->skb_dirty];
512 /* Check for errors. */
513 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
514 BD_ENET_TX_RL | BD_ENET_TX_UN |
516 dev->stats.tx_errors++;
517 if (status & BD_ENET_TX_HB) /* No heartbeat */
518 dev->stats.tx_heartbeat_errors++;
519 if (status & BD_ENET_TX_LC) /* Late collision */
520 dev->stats.tx_window_errors++;
521 if (status & BD_ENET_TX_RL) /* Retrans limit */
522 dev->stats.tx_aborted_errors++;
523 if (status & BD_ENET_TX_UN) /* Underrun */
524 dev->stats.tx_fifo_errors++;
525 if (status & BD_ENET_TX_CSL) /* Carrier lost */
526 dev->stats.tx_carrier_errors++;
528 dev->stats.tx_packets++;
531 #ifndef final_version
532 if (status & BD_ENET_TX_READY)
533 printk("HEY! Enet xmit interrupt and TX_READY.\n");
535 /* Deferred means some collisions occurred during transmit,
536 * but we eventually sent the packet OK.
538 if (status & BD_ENET_TX_DEF)
539 dev->stats.collisions++;
541 /* Free the sk buffer associated with this last transmit.
543 dev_kfree_skb_any(skb);
544 fep->tx_skbuff[fep->skb_dirty] = NULL;
545 fep->skb_dirty = (fep->skb_dirty + 1) & TX_RING_MOD_MASK;
547 /* Update pointer to next buffer descriptor to be transmitted.
549 if (status & BD_ENET_TX_WRAP)
550 bdp = fep->tx_bd_base;
554 /* Since we have freed up a buffer, the ring is no longer
559 if (netif_queue_stopped(dev))
560 netif_wake_queue(dev);
563 fep->dirty_tx = (cbd_t *)bdp;
564 spin_unlock_irq(&fep->hw_lock);
568 /* During a receive, the cur_rx points to the current incoming buffer.
569 * When we update through the ring, if the next incoming buffer has
570 * not been given to the system, we just set the empty indicator,
571 * effectively tossing the packet.
574 fec_enet_rx(struct net_device *dev)
576 struct fec_enet_private *fep;
577 volatile fec_t *fecp;
579 unsigned short status;
588 fep = netdev_priv(dev);
589 fecp = (volatile fec_t*)dev->base_addr;
591 spin_lock_irq(&fep->hw_lock);
593 /* First, grab all of the stats for the incoming packet.
594 * These get messed up if we get called due to a busy condition.
598 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
600 #ifndef final_version
601 /* Since we have allocated space to hold a complete frame,
602 * the last indicator should be set.
604 if ((status & BD_ENET_RX_LAST) == 0)
605 printk("FEC ENET: rcv is not +last\n");
609 goto rx_processing_done;
611 /* Check for errors. */
612 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
613 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
614 dev->stats.rx_errors++;
615 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
616 /* Frame too long or too short. */
617 dev->stats.rx_length_errors++;
619 if (status & BD_ENET_RX_NO) /* Frame alignment */
620 dev->stats.rx_frame_errors++;
621 if (status & BD_ENET_RX_CR) /* CRC Error */
622 dev->stats.rx_crc_errors++;
623 if (status & BD_ENET_RX_OV) /* FIFO overrun */
624 dev->stats.rx_fifo_errors++;
627 /* Report late collisions as a frame error.
628 * On this error, the BD is closed, but we don't know what we
629 * have in the buffer. So, just drop this frame on the floor.
631 if (status & BD_ENET_RX_CL) {
632 dev->stats.rx_errors++;
633 dev->stats.rx_frame_errors++;
634 goto rx_processing_done;
637 /* Process the incoming frame.
639 dev->stats.rx_packets++;
640 pkt_len = bdp->cbd_datlen;
641 dev->stats.rx_bytes += pkt_len;
642 data = (__u8*)__va(bdp->cbd_bufaddr);
644 dma_sync_single(NULL, (unsigned long)__pa(data),
645 pkt_len - 4, DMA_FROM_DEVICE);
647 /* This does 16 byte alignment, exactly what we need.
648 * The packet length includes FCS, but we don't want to
649 * include that when passing upstream as it messes up
650 * bridging applications.
652 skb = dev_alloc_skb(pkt_len-4);
655 printk("%s: Memory squeeze, dropping packet.\n", dev->name);
656 dev->stats.rx_dropped++;
658 skb_put(skb,pkt_len-4); /* Make room */
659 skb_copy_to_linear_data(skb, data, pkt_len-4);
660 skb->protocol=eth_type_trans(skb,dev);
665 /* Clear the status flags for this buffer.
667 status &= ~BD_ENET_RX_STATS;
669 /* Mark the buffer empty.
671 status |= BD_ENET_RX_EMPTY;
672 bdp->cbd_sc = status;
674 /* Update BD pointer to next entry.
676 if (status & BD_ENET_RX_WRAP)
677 bdp = fep->rx_bd_base;
682 /* Doing this here will keep the FEC running while we process
683 * incoming frames. On a heavily loaded network, we should be
684 * able to keep up at the expense of system resources.
686 fecp->fec_r_des_active = 0;
688 } /* while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) */
689 fep->cur_rx = (cbd_t *)bdp;
692 /* Doing this here will allow us to process all frames in the
693 * ring before the FEC is allowed to put more there. On a heavily
694 * loaded network, some frames may be lost. Unfortunately, this
695 * increases the interrupt overhead since we can potentially work
696 * our way back to the interrupt return only to come right back
699 fecp->fec_r_des_active = 0;
702 spin_unlock_irq(&fep->hw_lock);
706 /* called from interrupt context */
708 fec_enet_mii(struct net_device *dev)
710 struct fec_enet_private *fep;
715 fep = netdev_priv(dev);
716 spin_lock_irq(&fep->mii_lock);
719 mii_reg = ep->fec_mii_data;
721 if ((mip = mii_head) == NULL) {
722 printk("MII and no head!\n");
726 if (mip->mii_func != NULL)
727 (*(mip->mii_func))(mii_reg, dev);
729 mii_head = mip->mii_next;
730 mip->mii_next = mii_free;
733 if ((mip = mii_head) != NULL)
734 ep->fec_mii_data = mip->mii_regval;
737 spin_unlock_irq(&fep->mii_lock);
741 mii_queue(struct net_device *dev, int regval, void (*func)(uint, struct net_device *))
743 struct fec_enet_private *fep;
748 /* Add PHY address to register command.
750 fep = netdev_priv(dev);
751 spin_lock_irqsave(&fep->mii_lock, flags);
753 regval |= fep->phy_addr << 23;
756 if ((mip = mii_free) != NULL) {
757 mii_free = mip->mii_next;
758 mip->mii_regval = regval;
759 mip->mii_func = func;
760 mip->mii_next = NULL;
762 mii_tail->mii_next = mip;
765 mii_head = mii_tail = mip;
766 fep->hwp->fec_mii_data = regval;
772 spin_unlock_irqrestore(&fep->mii_lock, flags);
776 static void mii_do_cmd(struct net_device *dev, const phy_cmd_t *c)
781 for (; c->mii_data != mk_mii_end; c++)
782 mii_queue(dev, c->mii_data, c->funct);
785 static void mii_parse_sr(uint mii_reg, struct net_device *dev)
787 struct fec_enet_private *fep = netdev_priv(dev);
788 volatile uint *s = &(fep->phy_status);
791 status = *s & ~(PHY_STAT_LINK | PHY_STAT_FAULT | PHY_STAT_ANC);
793 if (mii_reg & 0x0004)
794 status |= PHY_STAT_LINK;
795 if (mii_reg & 0x0010)
796 status |= PHY_STAT_FAULT;
797 if (mii_reg & 0x0020)
798 status |= PHY_STAT_ANC;
802 static void mii_parse_cr(uint mii_reg, struct net_device *dev)
804 struct fec_enet_private *fep = netdev_priv(dev);
805 volatile uint *s = &(fep->phy_status);
808 status = *s & ~(PHY_CONF_ANE | PHY_CONF_LOOP);
810 if (mii_reg & 0x1000)
811 status |= PHY_CONF_ANE;
812 if (mii_reg & 0x4000)
813 status |= PHY_CONF_LOOP;
817 static void mii_parse_anar(uint mii_reg, struct net_device *dev)
819 struct fec_enet_private *fep = netdev_priv(dev);
820 volatile uint *s = &(fep->phy_status);
823 status = *s & ~(PHY_CONF_SPMASK);
825 if (mii_reg & 0x0020)
826 status |= PHY_CONF_10HDX;
827 if (mii_reg & 0x0040)
828 status |= PHY_CONF_10FDX;
829 if (mii_reg & 0x0080)
830 status |= PHY_CONF_100HDX;
831 if (mii_reg & 0x00100)
832 status |= PHY_CONF_100FDX;
836 /* ------------------------------------------------------------------------- */
837 /* The Level one LXT970 is used by many boards */
839 #define MII_LXT970_MIRROR 16 /* Mirror register */
840 #define MII_LXT970_IER 17 /* Interrupt Enable Register */
841 #define MII_LXT970_ISR 18 /* Interrupt Status Register */
842 #define MII_LXT970_CONFIG 19 /* Configuration Register */
843 #define MII_LXT970_CSR 20 /* Chip Status Register */
845 static void mii_parse_lxt970_csr(uint mii_reg, struct net_device *dev)
847 struct fec_enet_private *fep = netdev_priv(dev);
848 volatile uint *s = &(fep->phy_status);
851 status = *s & ~(PHY_STAT_SPMASK);
852 if (mii_reg & 0x0800) {
853 if (mii_reg & 0x1000)
854 status |= PHY_STAT_100FDX;
856 status |= PHY_STAT_100HDX;
858 if (mii_reg & 0x1000)
859 status |= PHY_STAT_10FDX;
861 status |= PHY_STAT_10HDX;
866 static phy_cmd_t const phy_cmd_lxt970_config[] = {
867 { mk_mii_read(MII_REG_CR), mii_parse_cr },
868 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
871 static phy_cmd_t const phy_cmd_lxt970_startup[] = { /* enable interrupts */
872 { mk_mii_write(MII_LXT970_IER, 0x0002), NULL },
873 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
876 static phy_cmd_t const phy_cmd_lxt970_ack_int[] = {
877 /* read SR and ISR to acknowledge */
878 { mk_mii_read(MII_REG_SR), mii_parse_sr },
879 { mk_mii_read(MII_LXT970_ISR), NULL },
881 /* find out the current status */
882 { mk_mii_read(MII_LXT970_CSR), mii_parse_lxt970_csr },
885 static phy_cmd_t const phy_cmd_lxt970_shutdown[] = { /* disable interrupts */
886 { mk_mii_write(MII_LXT970_IER, 0x0000), NULL },
889 static phy_info_t const phy_info_lxt970 = {
892 .config = phy_cmd_lxt970_config,
893 .startup = phy_cmd_lxt970_startup,
894 .ack_int = phy_cmd_lxt970_ack_int,
895 .shutdown = phy_cmd_lxt970_shutdown
898 /* ------------------------------------------------------------------------- */
899 /* The Level one LXT971 is used on some of my custom boards */
901 /* register definitions for the 971 */
903 #define MII_LXT971_PCR 16 /* Port Control Register */
904 #define MII_LXT971_SR2 17 /* Status Register 2 */
905 #define MII_LXT971_IER 18 /* Interrupt Enable Register */
906 #define MII_LXT971_ISR 19 /* Interrupt Status Register */
907 #define MII_LXT971_LCR 20 /* LED Control Register */
908 #define MII_LXT971_TCR 30 /* Transmit Control Register */
911 * I had some nice ideas of running the MDIO faster...
912 * The 971 should support 8MHz and I tried it, but things acted really
913 * weird, so 2.5 MHz ought to be enough for anyone...
916 static void mii_parse_lxt971_sr2(uint mii_reg, struct net_device *dev)
918 struct fec_enet_private *fep = netdev_priv(dev);
919 volatile uint *s = &(fep->phy_status);
922 status = *s & ~(PHY_STAT_SPMASK | PHY_STAT_LINK | PHY_STAT_ANC);
924 if (mii_reg & 0x0400) {
926 status |= PHY_STAT_LINK;
930 if (mii_reg & 0x0080)
931 status |= PHY_STAT_ANC;
932 if (mii_reg & 0x4000) {
933 if (mii_reg & 0x0200)
934 status |= PHY_STAT_100FDX;
936 status |= PHY_STAT_100HDX;
938 if (mii_reg & 0x0200)
939 status |= PHY_STAT_10FDX;
941 status |= PHY_STAT_10HDX;
943 if (mii_reg & 0x0008)
944 status |= PHY_STAT_FAULT;
949 static phy_cmd_t const phy_cmd_lxt971_config[] = {
950 /* limit to 10MBit because my prototype board
951 * doesn't work with 100. */
952 { mk_mii_read(MII_REG_CR), mii_parse_cr },
953 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
954 { mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 },
957 static phy_cmd_t const phy_cmd_lxt971_startup[] = { /* enable interrupts */
958 { mk_mii_write(MII_LXT971_IER, 0x00f2), NULL },
959 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
960 { mk_mii_write(MII_LXT971_LCR, 0xd422), NULL }, /* LED config */
961 /* Somehow does the 971 tell me that the link is down
962 * the first read after power-up.
963 * read here to get a valid value in ack_int */
964 { mk_mii_read(MII_REG_SR), mii_parse_sr },
967 static phy_cmd_t const phy_cmd_lxt971_ack_int[] = {
968 /* acknowledge the int before reading status ! */
969 { mk_mii_read(MII_LXT971_ISR), NULL },
970 /* find out the current status */
971 { mk_mii_read(MII_REG_SR), mii_parse_sr },
972 { mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 },
975 static phy_cmd_t const phy_cmd_lxt971_shutdown[] = { /* disable interrupts */
976 { mk_mii_write(MII_LXT971_IER, 0x0000), NULL },
979 static phy_info_t const phy_info_lxt971 = {
982 .config = phy_cmd_lxt971_config,
983 .startup = phy_cmd_lxt971_startup,
984 .ack_int = phy_cmd_lxt971_ack_int,
985 .shutdown = phy_cmd_lxt971_shutdown
988 /* ------------------------------------------------------------------------- */
989 /* The Quality Semiconductor QS6612 is used on the RPX CLLF */
991 /* register definitions */
993 #define MII_QS6612_MCR 17 /* Mode Control Register */
994 #define MII_QS6612_FTR 27 /* Factory Test Register */
995 #define MII_QS6612_MCO 28 /* Misc. Control Register */
996 #define MII_QS6612_ISR 29 /* Interrupt Source Register */
997 #define MII_QS6612_IMR 30 /* Interrupt Mask Register */
998 #define MII_QS6612_PCR 31 /* 100BaseTx PHY Control Reg. */
1000 static void mii_parse_qs6612_pcr(uint mii_reg, struct net_device *dev)
1002 struct fec_enet_private *fep = netdev_priv(dev);
1003 volatile uint *s = &(fep->phy_status);
1006 status = *s & ~(PHY_STAT_SPMASK);
1008 switch((mii_reg >> 2) & 7) {
1009 case 1: status |= PHY_STAT_10HDX; break;
1010 case 2: status |= PHY_STAT_100HDX; break;
1011 case 5: status |= PHY_STAT_10FDX; break;
1012 case 6: status |= PHY_STAT_100FDX; break;
1018 static phy_cmd_t const phy_cmd_qs6612_config[] = {
1019 /* The PHY powers up isolated on the RPX,
1020 * so send a command to allow operation.
1022 { mk_mii_write(MII_QS6612_PCR, 0x0dc0), NULL },
1024 /* parse cr and anar to get some info */
1025 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1026 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1029 static phy_cmd_t const phy_cmd_qs6612_startup[] = { /* enable interrupts */
1030 { mk_mii_write(MII_QS6612_IMR, 0x003a), NULL },
1031 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1034 static phy_cmd_t const phy_cmd_qs6612_ack_int[] = {
1035 /* we need to read ISR, SR and ANER to acknowledge */
1036 { mk_mii_read(MII_QS6612_ISR), NULL },
1037 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1038 { mk_mii_read(MII_REG_ANER), NULL },
1040 /* read pcr to get info */
1041 { mk_mii_read(MII_QS6612_PCR), mii_parse_qs6612_pcr },
1044 static phy_cmd_t const phy_cmd_qs6612_shutdown[] = { /* disable interrupts */
1045 { mk_mii_write(MII_QS6612_IMR, 0x0000), NULL },
1048 static phy_info_t const phy_info_qs6612 = {
1051 .config = phy_cmd_qs6612_config,
1052 .startup = phy_cmd_qs6612_startup,
1053 .ack_int = phy_cmd_qs6612_ack_int,
1054 .shutdown = phy_cmd_qs6612_shutdown
1057 /* ------------------------------------------------------------------------- */
1058 /* AMD AM79C874 phy */
1060 /* register definitions for the 874 */
1062 #define MII_AM79C874_MFR 16 /* Miscellaneous Feature Register */
1063 #define MII_AM79C874_ICSR 17 /* Interrupt/Status Register */
1064 #define MII_AM79C874_DR 18 /* Diagnostic Register */
1065 #define MII_AM79C874_PMLR 19 /* Power and Loopback Register */
1066 #define MII_AM79C874_MCR 21 /* ModeControl Register */
1067 #define MII_AM79C874_DC 23 /* Disconnect Counter */
1068 #define MII_AM79C874_REC 24 /* Recieve Error Counter */
1070 static void mii_parse_am79c874_dr(uint mii_reg, struct net_device *dev)
1072 struct fec_enet_private *fep = netdev_priv(dev);
1073 volatile uint *s = &(fep->phy_status);
1076 status = *s & ~(PHY_STAT_SPMASK | PHY_STAT_ANC);
1078 if (mii_reg & 0x0080)
1079 status |= PHY_STAT_ANC;
1080 if (mii_reg & 0x0400)
1081 status |= ((mii_reg & 0x0800) ? PHY_STAT_100FDX : PHY_STAT_100HDX);
1083 status |= ((mii_reg & 0x0800) ? PHY_STAT_10FDX : PHY_STAT_10HDX);
1088 static phy_cmd_t const phy_cmd_am79c874_config[] = {
1089 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1090 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1091 { mk_mii_read(MII_AM79C874_DR), mii_parse_am79c874_dr },
1094 static phy_cmd_t const phy_cmd_am79c874_startup[] = { /* enable interrupts */
1095 { mk_mii_write(MII_AM79C874_ICSR, 0xff00), NULL },
1096 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1097 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1100 static phy_cmd_t const phy_cmd_am79c874_ack_int[] = {
1101 /* find out the current status */
1102 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1103 { mk_mii_read(MII_AM79C874_DR), mii_parse_am79c874_dr },
1104 /* we only need to read ISR to acknowledge */
1105 { mk_mii_read(MII_AM79C874_ICSR), NULL },
1108 static phy_cmd_t const phy_cmd_am79c874_shutdown[] = { /* disable interrupts */
1109 { mk_mii_write(MII_AM79C874_ICSR, 0x0000), NULL },
1112 static phy_info_t const phy_info_am79c874 = {
1115 .config = phy_cmd_am79c874_config,
1116 .startup = phy_cmd_am79c874_startup,
1117 .ack_int = phy_cmd_am79c874_ack_int,
1118 .shutdown = phy_cmd_am79c874_shutdown
1122 /* ------------------------------------------------------------------------- */
1123 /* Kendin KS8721BL phy */
1125 /* register definitions for the 8721 */
1127 #define MII_KS8721BL_RXERCR 21
1128 #define MII_KS8721BL_ICSR 27
1129 #define MII_KS8721BL_PHYCR 31
1131 static phy_cmd_t const phy_cmd_ks8721bl_config[] = {
1132 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1133 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1136 static phy_cmd_t const phy_cmd_ks8721bl_startup[] = { /* enable interrupts */
1137 { mk_mii_write(MII_KS8721BL_ICSR, 0xff00), NULL },
1138 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1139 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1142 static phy_cmd_t const phy_cmd_ks8721bl_ack_int[] = {
1143 /* find out the current status */
1144 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1145 /* we only need to read ISR to acknowledge */
1146 { mk_mii_read(MII_KS8721BL_ICSR), NULL },
1149 static phy_cmd_t const phy_cmd_ks8721bl_shutdown[] = { /* disable interrupts */
1150 { mk_mii_write(MII_KS8721BL_ICSR, 0x0000), NULL },
1153 static phy_info_t const phy_info_ks8721bl = {
1156 .config = phy_cmd_ks8721bl_config,
1157 .startup = phy_cmd_ks8721bl_startup,
1158 .ack_int = phy_cmd_ks8721bl_ack_int,
1159 .shutdown = phy_cmd_ks8721bl_shutdown
1162 /* ------------------------------------------------------------------------- */
1163 /* register definitions for the DP83848 */
1165 #define MII_DP8384X_PHYSTST 16 /* PHY Status Register */
1167 static void mii_parse_dp8384x_sr2(uint mii_reg, struct net_device *dev)
1169 struct fec_enet_private *fep = netdev_priv(dev);
1170 volatile uint *s = &(fep->phy_status);
1172 *s &= ~(PHY_STAT_SPMASK | PHY_STAT_LINK | PHY_STAT_ANC);
1175 if (mii_reg & 0x0001) {
1177 *s |= PHY_STAT_LINK;
1180 /* Status of link */
1181 if (mii_reg & 0x0010) /* Autonegotioation complete */
1183 if (mii_reg & 0x0002) { /* 10MBps? */
1184 if (mii_reg & 0x0004) /* Full Duplex? */
1185 *s |= PHY_STAT_10FDX;
1187 *s |= PHY_STAT_10HDX;
1188 } else { /* 100 Mbps? */
1189 if (mii_reg & 0x0004) /* Full Duplex? */
1190 *s |= PHY_STAT_100FDX;
1192 *s |= PHY_STAT_100HDX;
1194 if (mii_reg & 0x0008)
1195 *s |= PHY_STAT_FAULT;
1198 static phy_info_t phy_info_dp83848= {
1202 (const phy_cmd_t []) { /* config */
1203 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1204 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1205 { mk_mii_read(MII_DP8384X_PHYSTST), mii_parse_dp8384x_sr2 },
1208 (const phy_cmd_t []) { /* startup - enable interrupts */
1209 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1210 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1213 (const phy_cmd_t []) { /* ack_int - never happens, no interrupt */
1216 (const phy_cmd_t []) { /* shutdown */
1221 /* ------------------------------------------------------------------------- */
1223 static phy_info_t const * const phy_info[] = {
1233 /* ------------------------------------------------------------------------- */
1234 #ifdef HAVE_mii_link_interrupt
1236 mii_link_interrupt(int irq, void * dev_id);
1239 #if defined(CONFIG_M5272)
1241 * Code specific to Coldfire 5272 setup.
1243 static void __inline__ fec_request_intrs(struct net_device *dev)
1245 volatile unsigned long *icrp;
1246 static const struct idesc {
1249 irq_handler_t handler;
1251 { "fec(RX)", 86, fec_enet_interrupt },
1252 { "fec(TX)", 87, fec_enet_interrupt },
1253 { "fec(OTHER)", 88, fec_enet_interrupt },
1254 { "fec(MII)", 66, mii_link_interrupt },
1258 /* Setup interrupt handlers. */
1259 for (idp = id; idp->name; idp++) {
1260 if (request_irq(idp->irq, idp->handler, IRQF_DISABLED, idp->name, dev) != 0)
1261 printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, idp->irq);
1264 /* Unmask interrupt at ColdFire 5272 SIM */
1265 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR3);
1267 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
1271 static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1273 volatile fec_t *fecp;
1276 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
1277 fecp->fec_x_cntrl = 0x00;
1280 * Set MII speed to 2.5 MHz
1281 * See 5272 manual section 11.5.8: MSCR
1283 fep->phy_speed = ((((MCF_CLK / 4) / (2500000 / 10)) + 5) / 10) * 2;
1284 fecp->fec_mii_speed = fep->phy_speed;
1286 fec_restart(dev, 0);
1289 static void __inline__ fec_get_mac(struct net_device *dev)
1291 struct fec_enet_private *fep = netdev_priv(dev);
1292 volatile fec_t *fecp;
1293 unsigned char *iap, tmpaddr[ETH_ALEN];
1299 * Get MAC address from FLASH.
1300 * If it is all 1's or 0's, use the default.
1302 iap = (unsigned char *)FEC_FLASHMAC;
1303 if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
1304 (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
1305 iap = fec_mac_default;
1306 if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
1307 (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
1308 iap = fec_mac_default;
1310 *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
1311 *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
1315 memcpy(dev->dev_addr, iap, ETH_ALEN);
1317 /* Adjust MAC if using default MAC address */
1318 if (iap == fec_mac_default)
1319 dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
1322 static void __inline__ fec_disable_phy_intr(void)
1324 volatile unsigned long *icrp;
1325 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
1329 static void __inline__ fec_phy_ack_intr(void)
1331 volatile unsigned long *icrp;
1332 /* Acknowledge the interrupt */
1333 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
1337 /* ------------------------------------------------------------------------- */
1339 #elif defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x)
1342 * Code specific to Coldfire 5230/5231/5232/5234/5235,
1343 * the 5270/5271/5274/5275 and 5280/5282 setups.
1345 static void __inline__ fec_request_intrs(struct net_device *dev)
1347 struct fec_enet_private *fep;
1349 static const struct idesc {
1359 fep = netdev_priv(dev);
1360 b = (fep->index) ? 128 : 64;
1362 /* Setup interrupt handlers. */
1363 for (idp = id; idp->name; idp++) {
1364 if (request_irq(b+idp->irq, fec_enet_interrupt, IRQF_DISABLED, idp->name, dev) != 0)
1365 printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, b+idp->irq);
1368 /* Unmask interrupts at ColdFire 5280/5282 interrupt controller */
1370 volatile unsigned char *icrp;
1371 volatile unsigned long *imrp;
1374 b = (fep->index) ? MCFICM_INTC1 : MCFICM_INTC0;
1375 icrp = (volatile unsigned char *) (MCF_IPSBAR + b +
1377 for (i = 23, ilip = 0x28; (i < 36); i++)
1380 imrp = (volatile unsigned long *) (MCF_IPSBAR + b +
1382 *imrp &= ~0x0000000f;
1383 imrp = (volatile unsigned long *) (MCF_IPSBAR + b +
1385 *imrp &= ~0xff800001;
1388 #if defined(CONFIG_M528x)
1389 /* Set up gpio outputs for MII lines */
1391 volatile u16 *gpio_paspar;
1392 volatile u8 *gpio_pehlpar;
1394 gpio_paspar = (volatile u16 *) (MCF_IPSBAR + 0x100056);
1395 gpio_pehlpar = (volatile u16 *) (MCF_IPSBAR + 0x100058);
1396 *gpio_paspar |= 0x0f00;
1397 *gpio_pehlpar = 0xc0;
1401 #if defined(CONFIG_M527x)
1402 /* Set up gpio outputs for MII lines */
1404 volatile u8 *gpio_par_fec;
1405 volatile u16 *gpio_par_feci2c;
1407 gpio_par_feci2c = (volatile u16 *)(MCF_IPSBAR + 0x100082);
1408 /* Set up gpio outputs for FEC0 MII lines */
1409 gpio_par_fec = (volatile u8 *)(MCF_IPSBAR + 0x100078);
1411 *gpio_par_feci2c |= 0x0f00;
1412 *gpio_par_fec |= 0xc0;
1414 #if defined(CONFIG_FEC2)
1415 /* Set up gpio outputs for FEC1 MII lines */
1416 gpio_par_fec = (volatile u8 *)(MCF_IPSBAR + 0x100079);
1418 *gpio_par_feci2c |= 0x00a0;
1419 *gpio_par_fec |= 0xc0;
1420 #endif /* CONFIG_FEC2 */
1422 #endif /* CONFIG_M527x */
1425 static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1427 volatile fec_t *fecp;
1430 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
1431 fecp->fec_x_cntrl = 0x00;
1434 * Set MII speed to 2.5 MHz
1435 * See 5282 manual section 17.5.4.7: MSCR
1437 fep->phy_speed = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2;
1438 fecp->fec_mii_speed = fep->phy_speed;
1440 fec_restart(dev, 0);
1443 static void __inline__ fec_get_mac(struct net_device *dev)
1445 struct fec_enet_private *fep = netdev_priv(dev);
1446 volatile fec_t *fecp;
1447 unsigned char *iap, tmpaddr[ETH_ALEN];
1453 * Get MAC address from FLASH.
1454 * If it is all 1's or 0's, use the default.
1457 if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
1458 (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
1459 iap = fec_mac_default;
1460 if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
1461 (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
1462 iap = fec_mac_default;
1464 *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
1465 *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
1469 memcpy(dev->dev_addr, iap, ETH_ALEN);
1471 /* Adjust MAC if using default MAC address */
1472 if (iap == fec_mac_default)
1473 dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
1476 static void __inline__ fec_disable_phy_intr(void)
1480 static void __inline__ fec_phy_ack_intr(void)
1484 /* ------------------------------------------------------------------------- */
1486 #elif defined(CONFIG_M520x)
1489 * Code specific to Coldfire 520x
1491 static void __inline__ fec_request_intrs(struct net_device *dev)
1493 struct fec_enet_private *fep;
1495 static const struct idesc {
1505 fep = netdev_priv(dev);
1508 /* Setup interrupt handlers. */
1509 for (idp = id; idp->name; idp++) {
1510 if (request_irq(b+idp->irq, fec_enet_interrupt, IRQF_DISABLED, idp->name,dev) != 0)
1511 printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, b+idp->irq);
1514 /* Unmask interrupts at ColdFire interrupt controller */
1516 volatile unsigned char *icrp;
1517 volatile unsigned long *imrp;
1519 icrp = (volatile unsigned char *) (MCF_IPSBAR + MCFICM_INTC0 +
1521 for (b = 36; (b < 49); b++)
1523 imrp = (volatile unsigned long *) (MCF_IPSBAR + MCFICM_INTC0 +
1525 *imrp &= ~0x0001FFF0;
1527 *(volatile unsigned char *)(MCF_IPSBAR + MCF_GPIO_PAR_FEC) |= 0xf0;
1528 *(volatile unsigned char *)(MCF_IPSBAR + MCF_GPIO_PAR_FECI2C) |= 0x0f;
1531 static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1533 volatile fec_t *fecp;
1536 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
1537 fecp->fec_x_cntrl = 0x00;
1540 * Set MII speed to 2.5 MHz
1541 * See 5282 manual section 17.5.4.7: MSCR
1543 fep->phy_speed = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2;
1544 fecp->fec_mii_speed = fep->phy_speed;
1546 fec_restart(dev, 0);
1549 static void __inline__ fec_get_mac(struct net_device *dev)
1551 struct fec_enet_private *fep = netdev_priv(dev);
1552 volatile fec_t *fecp;
1553 unsigned char *iap, tmpaddr[ETH_ALEN];
1559 * Get MAC address from FLASH.
1560 * If it is all 1's or 0's, use the default.
1563 if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
1564 (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
1565 iap = fec_mac_default;
1566 if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
1567 (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
1568 iap = fec_mac_default;
1570 *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
1571 *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
1575 memcpy(dev->dev_addr, iap, ETH_ALEN);
1577 /* Adjust MAC if using default MAC address */
1578 if (iap == fec_mac_default)
1579 dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
1582 static void __inline__ fec_disable_phy_intr(void)
1586 static void __inline__ fec_phy_ack_intr(void)
1590 /* ------------------------------------------------------------------------- */
1592 #elif defined(CONFIG_M532x)
1594 * Code specific for M532x
1596 static void __inline__ fec_request_intrs(struct net_device *dev)
1598 struct fec_enet_private *fep;
1600 static const struct idesc {
1610 fep = netdev_priv(dev);
1611 b = (fep->index) ? 128 : 64;
1613 /* Setup interrupt handlers. */
1614 for (idp = id; idp->name; idp++) {
1615 if (request_irq(b+idp->irq, fec_enet_interrupt, IRQF_DISABLED, idp->name,dev) != 0)
1616 printk("FEC: Could not allocate %s IRQ(%d)!\n",
1617 idp->name, b+idp->irq);
1620 /* Unmask interrupts */
1621 MCF_INTC0_ICR36 = 0x2;
1622 MCF_INTC0_ICR37 = 0x2;
1623 MCF_INTC0_ICR38 = 0x2;
1624 MCF_INTC0_ICR39 = 0x2;
1625 MCF_INTC0_ICR40 = 0x2;
1626 MCF_INTC0_ICR41 = 0x2;
1627 MCF_INTC0_ICR42 = 0x2;
1628 MCF_INTC0_ICR43 = 0x2;
1629 MCF_INTC0_ICR44 = 0x2;
1630 MCF_INTC0_ICR45 = 0x2;
1631 MCF_INTC0_ICR46 = 0x2;
1632 MCF_INTC0_ICR47 = 0x2;
1633 MCF_INTC0_ICR48 = 0x2;
1635 MCF_INTC0_IMRH &= ~(
1636 MCF_INTC_IMRH_INT_MASK36 |
1637 MCF_INTC_IMRH_INT_MASK37 |
1638 MCF_INTC_IMRH_INT_MASK38 |
1639 MCF_INTC_IMRH_INT_MASK39 |
1640 MCF_INTC_IMRH_INT_MASK40 |
1641 MCF_INTC_IMRH_INT_MASK41 |
1642 MCF_INTC_IMRH_INT_MASK42 |
1643 MCF_INTC_IMRH_INT_MASK43 |
1644 MCF_INTC_IMRH_INT_MASK44 |
1645 MCF_INTC_IMRH_INT_MASK45 |
1646 MCF_INTC_IMRH_INT_MASK46 |
1647 MCF_INTC_IMRH_INT_MASK47 |
1648 MCF_INTC_IMRH_INT_MASK48 );
1650 /* Set up gpio outputs for MII lines */
1651 MCF_GPIO_PAR_FECI2C |= (0 |
1652 MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC |
1653 MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO);
1654 MCF_GPIO_PAR_FEC = (0 |
1655 MCF_GPIO_PAR_FEC_PAR_FEC_7W_FEC |
1656 MCF_GPIO_PAR_FEC_PAR_FEC_MII_FEC);
1659 static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1661 volatile fec_t *fecp;
1664 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
1665 fecp->fec_x_cntrl = 0x00;
1668 * Set MII speed to 2.5 MHz
1670 fep->phy_speed = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2;
1671 fecp->fec_mii_speed = fep->phy_speed;
1673 fec_restart(dev, 0);
1676 static void __inline__ fec_get_mac(struct net_device *dev)
1678 struct fec_enet_private *fep = netdev_priv(dev);
1679 volatile fec_t *fecp;
1680 unsigned char *iap, tmpaddr[ETH_ALEN];
1686 * Get MAC address from FLASH.
1687 * If it is all 1's or 0's, use the default.
1690 if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
1691 (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
1692 iap = fec_mac_default;
1693 if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
1694 (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
1695 iap = fec_mac_default;
1697 *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
1698 *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
1702 memcpy(dev->dev_addr, iap, ETH_ALEN);
1704 /* Adjust MAC if using default MAC address */
1705 if (iap == fec_mac_default)
1706 dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
1709 static void __inline__ fec_disable_phy_intr(void)
1713 static void __inline__ fec_phy_ack_intr(void)
1719 /* ------------------------------------------------------------------------- */
1721 static void mii_display_status(struct net_device *dev)
1723 struct fec_enet_private *fep = netdev_priv(dev);
1724 volatile uint *s = &(fep->phy_status);
1726 if (!fep->link && !fep->old_link) {
1727 /* Link is still down - don't print anything */
1731 printk("%s: status: ", dev->name);
1734 printk("link down");
1738 switch(*s & PHY_STAT_SPMASK) {
1739 case PHY_STAT_100FDX: printk(", 100MBit Full Duplex"); break;
1740 case PHY_STAT_100HDX: printk(", 100MBit Half Duplex"); break;
1741 case PHY_STAT_10FDX: printk(", 10MBit Full Duplex"); break;
1742 case PHY_STAT_10HDX: printk(", 10MBit Half Duplex"); break;
1744 printk(", Unknown speed/duplex");
1747 if (*s & PHY_STAT_ANC)
1748 printk(", auto-negotiation complete");
1751 if (*s & PHY_STAT_FAULT)
1752 printk(", remote fault");
1757 static void mii_display_config(struct work_struct *work)
1759 struct fec_enet_private *fep = container_of(work, struct fec_enet_private, phy_task);
1760 struct net_device *dev = fep->netdev;
1761 uint status = fep->phy_status;
1764 ** When we get here, phy_task is already removed from
1765 ** the workqueue. It is thus safe to allow to reuse it.
1767 fep->mii_phy_task_queued = 0;
1768 printk("%s: config: auto-negotiation ", dev->name);
1770 if (status & PHY_CONF_ANE)
1775 if (status & PHY_CONF_100FDX)
1777 if (status & PHY_CONF_100HDX)
1779 if (status & PHY_CONF_10FDX)
1781 if (status & PHY_CONF_10HDX)
1783 if (!(status & PHY_CONF_SPMASK))
1784 printk(", No speed/duplex selected?");
1786 if (status & PHY_CONF_LOOP)
1787 printk(", loopback enabled");
1791 fep->sequence_done = 1;
1794 static void mii_relink(struct work_struct *work)
1796 struct fec_enet_private *fep = container_of(work, struct fec_enet_private, phy_task);
1797 struct net_device *dev = fep->netdev;
1801 ** When we get here, phy_task is already removed from
1802 ** the workqueue. It is thus safe to allow to reuse it.
1804 fep->mii_phy_task_queued = 0;
1805 fep->link = (fep->phy_status & PHY_STAT_LINK) ? 1 : 0;
1806 mii_display_status(dev);
1807 fep->old_link = fep->link;
1812 & (PHY_STAT_100FDX | PHY_STAT_10FDX))
1814 fec_restart(dev, duplex);
1819 enable_irq(fep->mii_irq);
1824 /* mii_queue_relink is called in interrupt context from mii_link_interrupt */
1825 static void mii_queue_relink(uint mii_reg, struct net_device *dev)
1827 struct fec_enet_private *fep = netdev_priv(dev);
1830 ** We cannot queue phy_task twice in the workqueue. It
1831 ** would cause an endless loop in the workqueue.
1832 ** Fortunately, if the last mii_relink entry has not yet been
1833 ** executed now, it will do the job for the current interrupt,
1834 ** which is just what we want.
1836 if (fep->mii_phy_task_queued)
1839 fep->mii_phy_task_queued = 1;
1840 INIT_WORK(&fep->phy_task, mii_relink);
1841 schedule_work(&fep->phy_task);
1844 /* mii_queue_config is called in interrupt context from fec_enet_mii */
1845 static void mii_queue_config(uint mii_reg, struct net_device *dev)
1847 struct fec_enet_private *fep = netdev_priv(dev);
1849 if (fep->mii_phy_task_queued)
1852 fep->mii_phy_task_queued = 1;
1853 INIT_WORK(&fep->phy_task, mii_display_config);
1854 schedule_work(&fep->phy_task);
1857 phy_cmd_t const phy_cmd_relink[] = {
1858 { mk_mii_read(MII_REG_CR), mii_queue_relink },
1861 phy_cmd_t const phy_cmd_config[] = {
1862 { mk_mii_read(MII_REG_CR), mii_queue_config },
1866 /* Read remainder of PHY ID.
1869 mii_discover_phy3(uint mii_reg, struct net_device *dev)
1871 struct fec_enet_private *fep;
1874 fep = netdev_priv(dev);
1875 fep->phy_id |= (mii_reg & 0xffff);
1876 printk("fec: PHY @ 0x%x, ID 0x%08x", fep->phy_addr, fep->phy_id);
1878 for(i = 0; phy_info[i]; i++) {
1879 if(phy_info[i]->id == (fep->phy_id >> 4))
1884 printk(" -- %s\n", phy_info[i]->name);
1886 printk(" -- unknown PHY!\n");
1888 fep->phy = phy_info[i];
1889 fep->phy_id_done = 1;
1892 /* Scan all of the MII PHY addresses looking for someone to respond
1893 * with a valid ID. This usually happens quickly.
1896 mii_discover_phy(uint mii_reg, struct net_device *dev)
1898 struct fec_enet_private *fep;
1899 volatile fec_t *fecp;
1902 fep = netdev_priv(dev);
1905 if (fep->phy_addr < 32) {
1906 if ((phytype = (mii_reg & 0xffff)) != 0xffff && phytype != 0) {
1908 /* Got first part of ID, now get remainder.
1910 fep->phy_id = phytype << 16;
1911 mii_queue(dev, mk_mii_read(MII_REG_PHYIR2),
1915 mii_queue(dev, mk_mii_read(MII_REG_PHYIR1),
1919 printk("FEC: No PHY device found.\n");
1920 /* Disable external MII interface */
1921 fecp->fec_mii_speed = fep->phy_speed = 0;
1922 fec_disable_phy_intr();
1926 /* This interrupt occurs when the PHY detects a link change.
1928 #ifdef HAVE_mii_link_interrupt
1930 mii_link_interrupt(int irq, void * dev_id)
1932 struct net_device *dev = dev_id;
1933 struct fec_enet_private *fep = netdev_priv(dev);
1938 disable_irq(fep->mii_irq); /* disable now, enable later */
1941 mii_do_cmd(dev, fep->phy->ack_int);
1942 mii_do_cmd(dev, phy_cmd_relink); /* restart and display status */
1949 fec_enet_open(struct net_device *dev)
1951 struct fec_enet_private *fep = netdev_priv(dev);
1953 /* I should reset the ring buffers here, but I don't yet know
1954 * a simple way to do that.
1956 fec_set_mac_address(dev);
1958 fep->sequence_done = 0;
1962 mii_do_cmd(dev, fep->phy->ack_int);
1963 mii_do_cmd(dev, fep->phy->config);
1964 mii_do_cmd(dev, phy_cmd_config); /* display configuration */
1966 /* Poll until the PHY tells us its configuration
1968 * Request is initiated by mii_do_cmd above, but answer
1969 * comes by interrupt.
1970 * This should take about 25 usec per register at 2.5 MHz,
1971 * and we read approximately 5 registers.
1973 while(!fep->sequence_done)
1976 mii_do_cmd(dev, fep->phy->startup);
1978 /* Set the initial link state to true. A lot of hardware
1979 * based on this device does not implement a PHY interrupt,
1980 * so we are never notified of link change.
1984 fep->link = 1; /* lets just try it and see */
1985 /* no phy, go full duplex, it's most likely a hub chip */
1986 fec_restart(dev, 1);
1989 netif_start_queue(dev);
1991 return 0; /* Success */
1995 fec_enet_close(struct net_device *dev)
1997 struct fec_enet_private *fep = netdev_priv(dev);
1999 /* Don't know what to do yet.
2002 netif_stop_queue(dev);
2008 /* Set or clear the multicast filter for this adaptor.
2009 * Skeleton taken from sunlance driver.
2010 * The CPM Ethernet implementation allows Multicast as well as individual
2011 * MAC address filtering. Some of the drivers check to make sure it is
2012 * a group multicast address, and discard those that are not. I guess I
2013 * will do the same for now, but just remove the test if you want
2014 * individual filtering as well (do the upper net layers want or support
2015 * this kind of feature?).
2018 #define HASH_BITS 6 /* #bits in hash */
2019 #define CRC32_POLY 0xEDB88320
2021 static void set_multicast_list(struct net_device *dev)
2023 struct fec_enet_private *fep;
2025 struct dev_mc_list *dmi;
2026 unsigned int i, j, bit, data, crc;
2029 fep = netdev_priv(dev);
2032 if (dev->flags&IFF_PROMISC) {
2033 ep->fec_r_cntrl |= 0x0008;
2036 ep->fec_r_cntrl &= ~0x0008;
2038 if (dev->flags & IFF_ALLMULTI) {
2039 /* Catch all multicast addresses, so set the
2040 * filter to all 1's.
2042 ep->fec_grp_hash_table_high = 0xffffffff;
2043 ep->fec_grp_hash_table_low = 0xffffffff;
2045 /* Clear filter and add the addresses in hash register.
2047 ep->fec_grp_hash_table_high = 0;
2048 ep->fec_grp_hash_table_low = 0;
2052 for (j = 0; j < dev->mc_count; j++, dmi = dmi->next)
2054 /* Only support group multicast for now.
2056 if (!(dmi->dmi_addr[0] & 1))
2059 /* calculate crc32 value of mac address
2063 for (i = 0; i < dmi->dmi_addrlen; i++)
2065 data = dmi->dmi_addr[i];
2066 for (bit = 0; bit < 8; bit++, data >>= 1)
2069 (((crc ^ data) & 1) ? CRC32_POLY : 0);
2073 /* only upper 6 bits (HASH_BITS) are used
2074 which point to specific bit in he hash registers
2076 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
2079 ep->fec_grp_hash_table_high |= 1 << (hash - 32);
2081 ep->fec_grp_hash_table_low |= 1 << hash;
2087 /* Set a MAC change in hardware.
2090 fec_set_mac_address(struct net_device *dev)
2092 volatile fec_t *fecp;
2094 fecp = ((struct fec_enet_private *)netdev_priv(dev))->hwp;
2096 /* Set station address. */
2097 fecp->fec_addr_low = dev->dev_addr[3] | (dev->dev_addr[2] << 8) |
2098 (dev->dev_addr[1] << 16) | (dev->dev_addr[0] << 24);
2099 fecp->fec_addr_high = (dev->dev_addr[5] << 16) |
2100 (dev->dev_addr[4] << 24);
2104 /* Initialize the FEC Ethernet on 860T (or ColdFire 5272).
2107 * XXX: We need to clean up on failure exits here.
2109 int __init fec_enet_init(struct net_device *dev)
2111 struct fec_enet_private *fep = netdev_priv(dev);
2112 unsigned long mem_addr;
2113 volatile cbd_t *bdp;
2115 volatile fec_t *fecp;
2117 static int index = 0;
2119 /* Only allow us to be probed once. */
2120 if (index >= FEC_MAX_PORTS)
2123 /* Allocate memory for buffer descriptors.
2125 mem_addr = (unsigned long)dma_alloc_coherent(NULL, PAGE_SIZE,
2126 &fep->bd_dma, GFP_KERNEL);
2127 if (mem_addr == 0) {
2128 printk("FEC: allocate descriptor memory failed?\n");
2132 spin_lock_init(&fep->hw_lock);
2133 spin_lock_init(&fep->mii_lock);
2135 /* Create an Ethernet device instance.
2137 fecp = (volatile fec_t *) fec_hw[index];
2143 /* Whack a reset. We should wait for this.
2145 fecp->fec_ecntrl = 1;
2148 /* Set the Ethernet address. If using multiple Enets on the 8xx,
2149 * this needs some work to get unique addresses.
2151 * This is our default MAC address unless the user changes
2152 * it via eth_mac_addr (our dev->set_mac_addr handler).
2156 cbd_base = (cbd_t *)mem_addr;
2157 /* XXX: missing check for allocation failure */
2159 /* Set receive and transmit descriptor base.
2161 fep->rx_bd_base = cbd_base;
2162 fep->tx_bd_base = cbd_base + RX_RING_SIZE;
2164 fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
2165 fep->cur_rx = fep->rx_bd_base;
2167 fep->skb_cur = fep->skb_dirty = 0;
2169 /* Initialize the receive buffer descriptors.
2171 bdp = fep->rx_bd_base;
2172 for (i=0; i<FEC_ENET_RX_PAGES; i++) {
2176 mem_addr = __get_free_page(GFP_KERNEL);
2177 /* XXX: missing check for allocation failure */
2179 /* Initialize the BD for every fragment in the page.
2181 for (j=0; j<FEC_ENET_RX_FRPPG; j++) {
2182 bdp->cbd_sc = BD_ENET_RX_EMPTY;
2183 bdp->cbd_bufaddr = __pa(mem_addr);
2184 mem_addr += FEC_ENET_RX_FRSIZE;
2189 /* Set the last buffer to wrap.
2192 bdp->cbd_sc |= BD_SC_WRAP;
2194 /* ...and the same for transmmit.
2196 bdp = fep->tx_bd_base;
2197 for (i=0, j=FEC_ENET_TX_FRPPG; i<TX_RING_SIZE; i++) {
2198 if (j >= FEC_ENET_TX_FRPPG) {
2199 mem_addr = __get_free_page(GFP_KERNEL);
2202 mem_addr += FEC_ENET_TX_FRSIZE;
2205 fep->tx_bounce[i] = (unsigned char *) mem_addr;
2207 /* Initialize the BD for every fragment in the page.
2210 bdp->cbd_bufaddr = 0;
2214 /* Set the last buffer to wrap.
2217 bdp->cbd_sc |= BD_SC_WRAP;
2219 /* Set receive and transmit descriptor base.
2221 fecp->fec_r_des_start = fep->bd_dma;
2222 fecp->fec_x_des_start = (unsigned long)fep->bd_dma + sizeof(cbd_t)
2225 /* Install our interrupt handlers. This varies depending on
2228 fec_request_intrs(dev);
2230 fecp->fec_grp_hash_table_high = 0;
2231 fecp->fec_grp_hash_table_low = 0;
2232 fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
2233 fecp->fec_ecntrl = 2;
2234 fecp->fec_r_des_active = 0;
2235 #ifndef CONFIG_M5272
2236 fecp->fec_hash_table_high = 0;
2237 fecp->fec_hash_table_low = 0;
2240 dev->base_addr = (unsigned long)fecp;
2242 /* The FEC Ethernet specific entries in the device structure. */
2243 dev->open = fec_enet_open;
2244 dev->hard_start_xmit = fec_enet_start_xmit;
2245 dev->tx_timeout = fec_timeout;
2246 dev->watchdog_timeo = TX_TIMEOUT;
2247 dev->stop = fec_enet_close;
2248 dev->set_multicast_list = set_multicast_list;
2250 for (i=0; i<NMII-1; i++)
2251 mii_cmds[i].mii_next = &mii_cmds[i+1];
2252 mii_free = mii_cmds;
2254 /* setup MII interface */
2255 fec_set_mii(dev, fep);
2257 /* Clear and enable interrupts */
2258 fecp->fec_ievent = 0xffc00000;
2259 fecp->fec_imask = (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII);
2261 /* Queue up command to detect the PHY and initialize the
2262 * remainder of the interface.
2264 fep->phy_id_done = 0;
2266 mii_queue(dev, mk_mii_read(MII_REG_PHYIR1), mii_discover_phy);
2272 /* This function is called to start or restart the FEC during a link
2273 * change. This only happens when switching between half and full
2277 fec_restart(struct net_device *dev, int duplex)
2279 struct fec_enet_private *fep;
2280 volatile cbd_t *bdp;
2281 volatile fec_t *fecp;
2284 fep = netdev_priv(dev);
2287 /* Whack a reset. We should wait for this.
2289 fecp->fec_ecntrl = 1;
2292 /* Clear any outstanding interrupt.
2294 fecp->fec_ievent = 0xffc00000;
2296 /* Set station address.
2298 fec_set_mac_address(dev);
2300 /* Reset all multicast.
2302 fecp->fec_grp_hash_table_high = 0;
2303 fecp->fec_grp_hash_table_low = 0;
2305 /* Set maximum receive buffer size.
2307 fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
2309 /* Set receive and transmit descriptor base.
2311 fecp->fec_r_des_start = fep->bd_dma;
2312 fecp->fec_x_des_start = (unsigned long)fep->bd_dma + sizeof(cbd_t)
2315 fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
2316 fep->cur_rx = fep->rx_bd_base;
2318 /* Reset SKB transmit buffers.
2320 fep->skb_cur = fep->skb_dirty = 0;
2321 for (i=0; i<=TX_RING_MOD_MASK; i++) {
2322 if (fep->tx_skbuff[i] != NULL) {
2323 dev_kfree_skb_any(fep->tx_skbuff[i]);
2324 fep->tx_skbuff[i] = NULL;
2328 /* Initialize the receive buffer descriptors.
2330 bdp = fep->rx_bd_base;
2331 for (i=0; i<RX_RING_SIZE; i++) {
2333 /* Initialize the BD for every fragment in the page.
2335 bdp->cbd_sc = BD_ENET_RX_EMPTY;
2339 /* Set the last buffer to wrap.
2342 bdp->cbd_sc |= BD_SC_WRAP;
2344 /* ...and the same for transmmit.
2346 bdp = fep->tx_bd_base;
2347 for (i=0; i<TX_RING_SIZE; i++) {
2349 /* Initialize the BD for every fragment in the page.
2352 bdp->cbd_bufaddr = 0;
2356 /* Set the last buffer to wrap.
2359 bdp->cbd_sc |= BD_SC_WRAP;
2364 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;/* MII enable */
2365 fecp->fec_x_cntrl = 0x04; /* FD enable */
2367 /* MII enable|No Rcv on Xmit */
2368 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x06;
2369 fecp->fec_x_cntrl = 0x00;
2371 fep->full_duplex = duplex;
2375 fecp->fec_mii_speed = fep->phy_speed;
2377 /* And last, enable the transmit and receive processing.
2379 fecp->fec_ecntrl = 2;
2380 fecp->fec_r_des_active = 0;
2382 /* Enable interrupts we wish to service.
2384 fecp->fec_imask = (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII);
2388 fec_stop(struct net_device *dev)
2390 volatile fec_t *fecp;
2391 struct fec_enet_private *fep;
2393 fep = netdev_priv(dev);
2397 ** We cannot expect a graceful transmit stop without link !!!
2401 fecp->fec_x_cntrl = 0x01; /* Graceful transmit stop */
2403 if (!(fecp->fec_ievent & FEC_ENET_GRA))
2404 printk("fec_stop : Graceful transmit stop did not complete !\n");
2407 /* Whack a reset. We should wait for this.
2409 fecp->fec_ecntrl = 1;
2412 /* Clear outstanding MII command interrupts.
2414 fecp->fec_ievent = FEC_ENET_MII;
2416 fecp->fec_imask = FEC_ENET_MII;
2417 fecp->fec_mii_speed = fep->phy_speed;
2420 static int __init fec_enet_module_init(void)
2422 struct net_device *dev;
2425 printk("FEC ENET Version 0.2\n");
2427 for (i = 0; (i < FEC_MAX_PORTS); i++) {
2428 dev = alloc_etherdev(sizeof(struct fec_enet_private));
2431 err = fec_enet_init(dev);
2436 if (register_netdev(dev) != 0) {
2437 /* XXX: missing cleanup here */
2442 printk("%s: ethernet %pM\n", dev->name, dev->dev_addr);
2447 module_init(fec_enet_module_init);
2449 MODULE_LICENSE("GPL");