drivers/net/ethernet/ti/cpsw.c

   1 /*
   2  * Texas Instruments Ethernet Switch Driver
   3  *
   4  * Copyright (C) 2012 Texas Instruments
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation version 2.
   9  *
  10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11  * kind, whether express or implied; without even the implied warranty
  12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/io.h>
  18 #include <linux/clk.h>
  19 #include <linux/timer.h>
  20 #include <linux/module.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/irqreturn.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/if_ether.h>
  25 #include <linux/etherdevice.h>
  26 #include <linux/netdevice.h>
  27 #include <linux/net_tstamp.h>
  28 #include <linux/phy.h>
  29 #include <linux/workqueue.h>
  30 #include <linux/delay.h>
  31 #include <linux/pm_runtime.h>
  32 #include <linux/of.h>
  33 #include <linux/of_net.h>
  34 #include <linux/of_device.h>
  35 #include <linux/if_vlan.h>
  36 #include <linux/mfd/syscon.h>
  37 #include <linux/regmap.h>
  38
  39 #include <linux/pinctrl/consumer.h>
  40
  41 #include "cpsw.h"
  42 #include "cpsw_ale.h"
  43 #include "cpts.h"
  44 #include "davinci_cpdma.h"
  45
  46 #define CPSW_DEBUG      (NETIF_MSG_HW           | NETIF_MSG_WOL         | \
  47                          NETIF_MSG_DRV          | NETIF_MSG_LINK        | \
  48                          NETIF_MSG_IFUP         | NETIF_MSG_INTR        | \
  49                          NETIF_MSG_PROBE        | NETIF_MSG_TIMER       | \
  50                          NETIF_MSG_IFDOWN       | NETIF_MSG_RX_ERR      | \
  51                          NETIF_MSG_TX_ERR       | NETIF_MSG_TX_DONE     | \
  52                          NETIF_MSG_PKTDATA      | NETIF_MSG_TX_QUEUED   | \
  53                          NETIF_MSG_RX_STATUS)
  54
  55 #define cpsw_info(priv, type, format, ...)              \
  56 do {                                                            \
  57         if (netif_msg_##type(priv) && net_ratelimit())          \
  58                 dev_info(priv->dev, format, ## __VA_ARGS__);    \
  59 } while (0)
  60
  61 #define cpsw_err(priv, type, format, ...)               \
  62 do {                                                            \
  63         if (netif_msg_##type(priv) && net_ratelimit())          \
  64                 dev_err(priv->dev, format, ## __VA_ARGS__);     \
  65 } while (0)
  66
  67 #define cpsw_dbg(priv, type, format, ...)               \
  68 do {                                                            \
  69         if (netif_msg_##type(priv) && net_ratelimit())          \
  70                 dev_dbg(priv->dev, format, ## __VA_ARGS__);     \
  71 } while (0)
  72
  73 #define cpsw_notice(priv, type, format, ...)            \
  74 do {                                                            \
  75         if (netif_msg_##type(priv) && net_ratelimit())          \
  76                 dev_notice(priv->dev, format, ## __VA_ARGS__);  \
  77 } while (0)
  78
  79 #define ALE_ALL_PORTS           0x7
  80
  81 #define CPSW_MAJOR_VERSION(reg)         (reg >> 8 & 0x7)
  82 #define CPSW_MINOR_VERSION(reg)         (reg & 0xff)
  83 #define CPSW_RTL_VERSION(reg)           ((reg >> 11) & 0x1f)
  84
  85 #define CPSW_VERSION_1          0x19010a
  86 #define CPSW_VERSION_2          0x19010c
  87 #define CPSW_VERSION_3          0x19010f
  88 #define CPSW_VERSION_4          0x190112
  89
  90 #define HOST_PORT_NUM           0
  91 #define SLIVER_SIZE             0x40
  92
  93 #define CPSW1_HOST_PORT_OFFSET  0x028
  94 #define CPSW1_SLAVE_OFFSET      0x050
  95 #define CPSW1_SLAVE_SIZE        0x040
  96 #define CPSW1_CPDMA_OFFSET      0x100
  97 #define CPSW1_STATERAM_OFFSET   0x200
  98 #define CPSW1_HW_STATS          0x400
  99 #define CPSW1_CPTS_OFFSET       0x500
 100 #define CPSW1_ALE_OFFSET        0x600
 101 #define CPSW1_SLIVER_OFFSET     0x700
 102
 103 #define CPSW2_HOST_PORT_OFFSET  0x108
 104 #define CPSW2_SLAVE_OFFSET      0x200
 105 #define CPSW2_SLAVE_SIZE        0x100
 106 #define CPSW2_CPDMA_OFFSET      0x800
 107 #define CPSW2_HW_STATS          0x900
 108 #define CPSW2_STATERAM_OFFSET   0xa00
 109 #define CPSW2_CPTS_OFFSET       0xc00
 110 #define CPSW2_ALE_OFFSET        0xd00
 111 #define CPSW2_SLIVER_OFFSET     0xd80
 112 #define CPSW2_BD_OFFSET         0x2000
 113
 114 #define CPDMA_RXTHRESH          0x0c0
 115 #define CPDMA_RXFREE            0x0e0
 116 #define CPDMA_TXHDP             0x00
 117 #define CPDMA_RXHDP             0x20
 118 #define CPDMA_TXCP              0x40
 119 #define CPDMA_RXCP              0x60
 120
 121 #define CPSW_POLL_WEIGHT        64
 122 #define CPSW_MIN_PACKET_SIZE    60
 123 #define CPSW_MAX_PACKET_SIZE    (1500 + 14 + 4 + 4)
 124
 125 #define RX_PRIORITY_MAPPING     0x76543210
 126 #define TX_PRIORITY_MAPPING     0x33221100
 127 #define CPDMA_TX_PRIORITY_MAP   0x76543210
 128
 129 #define CPSW_VLAN_AWARE         BIT(1)
 130 #define CPSW_ALE_VLAN_AWARE     1
 131
 132 #define CPSW_FIFO_NORMAL_MODE           (0 << 16)
 133 #define CPSW_FIFO_DUAL_MAC_MODE         (1 << 16)
 134 #define CPSW_FIFO_RATE_LIMIT_MODE       (2 << 16)
 135
 136 #define CPSW_INTPACEEN          (0x3f << 16)
 137 #define CPSW_INTPRESCALE_MASK   (0x7FF << 0)
 138 #define CPSW_CMINTMAX_CNT       63
 139 #define CPSW_CMINTMIN_CNT       2
 140 #define CPSW_CMINTMAX_INTVL     (1000 / CPSW_CMINTMIN_CNT)
 141 #define CPSW_CMINTMIN_INTVL     ((1000 / CPSW_CMINTMAX_CNT) + 1)
 142
 143 #define cpsw_enable_irq(priv)   \
 144         do {                    \
 145                 u32 i;          \
 146                 for (i = 0; i < priv->num_irqs; i++) \
 147                         enable_irq(priv->irqs_table[i]); \
 148         } while (0)
 149 #define cpsw_disable_irq(priv)  \
 150         do {                    \
 151                 u32 i;          \
 152                 for (i = 0; i < priv->num_irqs; i++) \
 153                         disable_irq_nosync(priv->irqs_table[i]); \
 154         } while (0)
 155
 156 #define cpsw_slave_index(priv)                          \
 157                 ((priv->data.dual_emac) ? priv->emac_port :     \
 158                 priv->data.active_slave)
 159
 160 static int debug_level;
 161 module_param(debug_level, int, 0);
 162 MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
 163
 164 static int ale_ageout = 10;
 165 module_param(ale_ageout, int, 0);
 166 MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
 167
 168 static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
 169 module_param(rx_packet_max, int, 0);
 170 MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
 171
 172 struct cpsw_wr_regs {
 173         u32     id_ver;
 174         u32     soft_reset;
 175         u32     control;
 176         u32     int_control;
 177         u32     rx_thresh_en;
 178         u32     rx_en;
 179         u32     tx_en;
 180         u32     misc_en;
 181         u32     mem_allign1[8];
 182         u32     rx_thresh_stat;
 183         u32     rx_stat;
 184         u32     tx_stat;
 185         u32     misc_stat;
 186         u32     mem_allign2[8];
 187         u32     rx_imax;
 188         u32     tx_imax;
 189
 190 };
 191
 192 struct cpsw_ss_regs {
 193         u32     id_ver;
 194         u32     control;
 195         u32     soft_reset;
 196         u32     stat_port_en;
 197         u32     ptype;
 198         u32     soft_idle;
 199         u32     thru_rate;
 200         u32     gap_thresh;
 201         u32     tx_start_wds;
 202         u32     flow_control;
 203         u32     vlan_ltype;
 204         u32     ts_ltype;
 205         u32     dlr_ltype;
 206 };
 207
 208 /* CPSW_PORT_V1 */
 209 #define CPSW1_MAX_BLKS      0x00 /* Maximum FIFO Blocks */
 210 #define CPSW1_BLK_CNT       0x04 /* FIFO Block Usage Count (Read Only) */
 211 #define CPSW1_TX_IN_CTL     0x08 /* Transmit FIFO Control */
 212 #define CPSW1_PORT_VLAN     0x0c /* VLAN Register */
 213 #define CPSW1_TX_PRI_MAP    0x10 /* Tx Header Priority to Switch Pri Mapping */
 214 #define CPSW1_TS_CTL        0x14 /* Time Sync Control */
 215 #define CPSW1_TS_SEQ_LTYPE  0x18 /* Time Sync Sequence ID Offset and Msg Type */
 216 #define CPSW1_TS_VLAN       0x1c /* Time Sync VLAN1 and VLAN2 */
 217
 218 /* CPSW_PORT_V2 */
 219 #define CPSW2_CONTROL       0x00 /* Control Register */
 220 #define CPSW2_MAX_BLKS      0x08 /* Maximum FIFO Blocks */
 221 #define CPSW2_BLK_CNT       0x0c /* FIFO Block Usage Count (Read Only) */
 222 #define CPSW2_TX_IN_CTL     0x10 /* Transmit FIFO Control */
 223 #define CPSW2_PORT_VLAN     0x14 /* VLAN Register */
 224 #define CPSW2_TX_PRI_MAP    0x18 /* Tx Header Priority to Switch Pri Mapping */
 225 #define CPSW2_TS_SEQ_MTYPE  0x1c /* Time Sync Sequence ID Offset and Msg Type */
 226
 227 /* CPSW_PORT_V1 and V2 */
 228 #define SA_LO               0x20 /* CPGMAC_SL Source Address Low */
 229 #define SA_HI               0x24 /* CPGMAC_SL Source Address High */
 230 #define SEND_PERCENT        0x28 /* Transmit Queue Send Percentages */
 231
 232 /* CPSW_PORT_V2 only */
 233 #define RX_DSCP_PRI_MAP0    0x30 /* Rx DSCP Priority to Rx Packet Mapping */
 234 #define RX_DSCP_PRI_MAP1    0x34 /* Rx DSCP Priority to Rx Packet Mapping */
 235 #define RX_DSCP_PRI_MAP2    0x38 /* Rx DSCP Priority to Rx Packet Mapping */
 236 #define RX_DSCP_PRI_MAP3    0x3c /* Rx DSCP Priority to Rx Packet Mapping */
 237 #define RX_DSCP_PRI_MAP4    0x40 /* Rx DSCP Priority to Rx Packet Mapping */
 238 #define RX_DSCP_PRI_MAP5    0x44 /* Rx DSCP Priority to Rx Packet Mapping */
 239 #define RX_DSCP_PRI_MAP6    0x48 /* Rx DSCP Priority to Rx Packet Mapping */
 240 #define RX_DSCP_PRI_MAP7    0x4c /* Rx DSCP Priority to Rx Packet Mapping */
 241
 242 /* Bit definitions for the CPSW2_CONTROL register */
 243 #define PASS_PRI_TAGGED     (1<<24) /* Pass Priority Tagged */
 244 #define VLAN_LTYPE2_EN      (1<<21) /* VLAN LTYPE 2 enable */
 245 #define VLAN_LTYPE1_EN      (1<<20) /* VLAN LTYPE 1 enable */
 246 #define DSCP_PRI_EN         (1<<16) /* DSCP Priority Enable */
 247 #define TS_320              (1<<14) /* Time Sync Dest Port 320 enable */
 248 #define TS_319              (1<<13) /* Time Sync Dest Port 319 enable */
 249 #define TS_132              (1<<12) /* Time Sync Dest IP Addr 132 enable */
 250 #define TS_131              (1<<11) /* Time Sync Dest IP Addr 131 enable */
 251 #define TS_130              (1<<10) /* Time Sync Dest IP Addr 130 enable */
 252 #define TS_129              (1<<9)  /* Time Sync Dest IP Addr 129 enable */
 253 #define TS_TTL_NONZERO      (1<<8)  /* Time Sync Time To Live Non-zero enable */
 254 #define TS_ANNEX_F_EN       (1<<6)  /* Time Sync Annex F enable */
 255 #define TS_ANNEX_D_EN       (1<<4)  /* Time Sync Annex D enable */
 256 #define TS_LTYPE2_EN        (1<<3)  /* Time Sync LTYPE 2 enable */
 257 #define TS_LTYPE1_EN        (1<<2)  /* Time Sync LTYPE 1 enable */
 258 #define TS_TX_EN            (1<<1)  /* Time Sync Transmit Enable */
 259 #define TS_RX_EN            (1<<0)  /* Time Sync Receive Enable */
 260
 261 #define CTRL_V2_TS_BITS \
 262         (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
 263          TS_TTL_NONZERO  | TS_ANNEX_D_EN | TS_LTYPE1_EN)
 264
 265 #define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
 266 #define CTRL_V2_TX_TS_BITS  (CTRL_V2_TS_BITS | TS_TX_EN)
 267 #define CTRL_V2_RX_TS_BITS  (CTRL_V2_TS_BITS | TS_RX_EN)
 268
 269
 270 #define CTRL_V3_TS_BITS \
 271         (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
 272          TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
 273          TS_LTYPE1_EN)
 274
 275 #define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
 276 #define CTRL_V3_TX_TS_BITS  (CTRL_V3_TS_BITS | TS_TX_EN)
 277 #define CTRL_V3_RX_TS_BITS  (CTRL_V3_TS_BITS | TS_RX_EN)
 278
 279 /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
 280 #define TS_SEQ_ID_OFFSET_SHIFT   (16)    /* Time Sync Sequence ID Offset */
 281 #define TS_SEQ_ID_OFFSET_MASK    (0x3f)
 282 #define TS_MSG_TYPE_EN_SHIFT     (0)     /* Time Sync Message Type Enable */
 283 #define TS_MSG_TYPE_EN_MASK      (0xffff)
 284
 285 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
 286 #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
 287
 288 /* Bit definitions for the CPSW1_TS_CTL register */
 289 #define CPSW_V1_TS_RX_EN                BIT(0)
 290 #define CPSW_V1_TS_TX_EN                BIT(4)
 291 #define CPSW_V1_MSG_TYPE_OFS            16
 292
 293 /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
 294 #define CPSW_V1_SEQ_ID_OFS_SHIFT        16
 295
 296 struct cpsw_host_regs {
 297         u32     max_blks;
 298         u32     blk_cnt;
 299         u32     tx_in_ctl;
 300         u32     port_vlan;
 301         u32     tx_pri_map;
 302         u32     cpdma_tx_pri_map;
 303         u32     cpdma_rx_chan_map;
 304 };
 305
 306 struct cpsw_sliver_regs {
 307         u32     id_ver;
 308         u32     mac_control;
 309         u32     mac_status;
 310         u32     soft_reset;
 311         u32     rx_maxlen;
 312         u32     __reserved_0;
 313         u32     rx_pause;
 314         u32     tx_pause;
 315         u32     __reserved_1;
 316         u32     rx_pri_map;
 317 };
 318
 319 struct cpsw_hw_stats {
 320         u32     rxgoodframes;
 321         u32     rxbroadcastframes;
 322         u32     rxmulticastframes;
 323         u32     rxpauseframes;
 324         u32     rxcrcerrors;
 325         u32     rxaligncodeerrors;
 326         u32     rxoversizedframes;
 327         u32     rxjabberframes;
 328         u32     rxundersizedframes;
 329         u32     rxfragments;
 330         u32     __pad_0[2];
 331         u32     rxoctets;
 332         u32     txgoodframes;
 333         u32     txbroadcastframes;
 334         u32     txmulticastframes;
 335         u32     txpauseframes;
 336         u32     txdeferredframes;
 337         u32     txcollisionframes;
 338         u32     txsinglecollframes;
 339         u32     txmultcollframes;
 340         u32     txexcessivecollisions;
 341         u32     txlatecollisions;
 342         u32     txunderrun;
 343         u32     txcarriersenseerrors;
 344         u32     txoctets;
 345         u32     octetframes64;
 346         u32     octetframes65t127;
 347         u32     octetframes128t255;
 348         u32     octetframes256t511;
 349         u32     octetframes512t1023;
 350         u32     octetframes1024tup;
 351         u32     netoctets;
 352         u32     rxsofoverruns;
 353         u32     rxmofoverruns;
 354         u32     rxdmaoverruns;
 355 };
 356
 357 struct cpsw_slave {
 358         void __iomem                    *regs;
 359         struct cpsw_sliver_regs __iomem *sliver;
 360         int                             slave_num;
 361         u32                             mac_control;
 362         struct cpsw_slave_data          *data;
 363         struct phy_device               *phy;
 364         struct net_device               *ndev;
 365         u32                             port_vlan;
 366         u32                             open_stat;
 367 };
 368
 369 static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
 370 {
 371         return __raw_readl(slave->regs + offset);
 372 }
 373
 374 static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
 375 {
 376         __raw_writel(val, slave->regs + offset);
 377 }
 378
 379 struct cpsw_priv {
 380         spinlock_t                      lock;
 381         struct platform_device          *pdev;
 382         struct net_device               *ndev;
 383         struct napi_struct              napi;
 384         struct device                   *dev;
 385         struct cpsw_platform_data       data;
 386         struct cpsw_ss_regs __iomem     *regs;
 387         struct cpsw_wr_regs __iomem     *wr_regs;
 388         u8 __iomem                      *hw_stats;
 389         struct cpsw_host_regs __iomem   *host_port_regs;
 390         u32                             msg_enable;
 391         u32                             version;
 392         u32                             coal_intvl;
 393         u32                             bus_freq_mhz;
 394         int                             rx_packet_max;
 395         int                             host_port;
 396         struct clk                      *clk;
 397         u8                              mac_addr[ETH_ALEN];
 398         struct cpsw_slave               *slaves;
 399         struct cpdma_ctlr               *dma;
 400         struct cpdma_chan               *txch, *rxch;
 401         struct cpsw_ale                 *ale;
 402         bool                            rx_pause;
 403         bool                            tx_pause;
 404         /* snapshot of IRQ numbers */
 405         u32 irqs_table[4];
 406         u32 num_irqs;
 407         bool irq_enabled;
 408         struct cpts *cpts;
 409         u32 emac_port;
 410 };
 411
 412 struct cpsw_stats {
 413         char stat_string[ETH_GSTRING_LEN];
 414         int type;
 415         int sizeof_stat;
 416         int stat_offset;
 417 };
 418
 419 enum {
 420         CPSW_STATS,
 421         CPDMA_RX_STATS,
 422         CPDMA_TX_STATS,
 423 };
 424
 425 #define CPSW_STAT(m)            CPSW_STATS,                             \
 426                                 sizeof(((struct cpsw_hw_stats *)0)->m), \
 427                                 offsetof(struct cpsw_hw_stats, m)
 428 #define CPDMA_RX_STAT(m)        CPDMA_RX_STATS,                            \
 429                                 sizeof(((struct cpdma_chan_stats *)0)->m), \
 430                                 offsetof(struct cpdma_chan_stats, m)
 431 #define CPDMA_TX_STAT(m)        CPDMA_TX_STATS,                            \
 432                                 sizeof(((struct cpdma_chan_stats *)0)->m), \
 433                                 offsetof(struct cpdma_chan_stats, m)
 434
 435 static const struct cpsw_stats cpsw_gstrings_stats[] = {
 436         { "Good Rx Frames", CPSW_STAT(rxgoodframes) },
 437         { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },
 438         { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },
 439         { "Pause Rx Frames", CPSW_STAT(rxpauseframes) },
 440         { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },
 441         { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },
 442         { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },
 443         { "Rx Jabbers", CPSW_STAT(rxjabberframes) },
 444         { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },
 445         { "Rx Fragments", CPSW_STAT(rxfragments) },
 446         { "Rx Octets", CPSW_STAT(rxoctets) },
 447         { "Good Tx Frames", CPSW_STAT(txgoodframes) },
 448         { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },
 449         { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },
 450         { "Pause Tx Frames", CPSW_STAT(txpauseframes) },
 451         { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },
 452         { "Collisions", CPSW_STAT(txcollisionframes) },
 453         { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },
 454         { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },
 455         { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },
 456         { "Late Collisions", CPSW_STAT(txlatecollisions) },
 457         { "Tx Underrun", CPSW_STAT(txunderrun) },
 458         { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },
 459         { "Tx Octets", CPSW_STAT(txoctets) },
 460         { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },
 461         { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },
 462         { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },
 463         { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },
 464         { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },
 465         { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },
 466         { "Net Octets", CPSW_STAT(netoctets) },
 467         { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },
 468         { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },
 469         { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },
 470         { "Rx DMA chan: head_enqueue", CPDMA_RX_STAT(head_enqueue) },
 471         { "Rx DMA chan: tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },
 472         { "Rx DMA chan: pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },
 473         { "Rx DMA chan: misqueued", CPDMA_RX_STAT(misqueued) },
 474         { "Rx DMA chan: desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },
 475         { "Rx DMA chan: pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },
 476         { "Rx DMA chan: runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },
 477         { "Rx DMA chan: runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },
 478         { "Rx DMA chan: empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },
 479         { "Rx DMA chan: busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },
 480         { "Rx DMA chan: good_dequeue", CPDMA_RX_STAT(good_dequeue) },
 481         { "Rx DMA chan: requeue", CPDMA_RX_STAT(requeue) },
 482         { "Rx DMA chan: teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },
 483         { "Tx DMA chan: head_enqueue", CPDMA_TX_STAT(head_enqueue) },
 484         { "Tx DMA chan: tail_enqueue", CPDMA_TX_STAT(tail_enqueue) },
 485         { "Tx DMA chan: pad_enqueue", CPDMA_TX_STAT(pad_enqueue) },
 486         { "Tx DMA chan: misqueued", CPDMA_TX_STAT(misqueued) },
 487         { "Tx DMA chan: desc_alloc_fail", CPDMA_TX_STAT(desc_alloc_fail) },
 488         { "Tx DMA chan: pad_alloc_fail", CPDMA_TX_STAT(pad_alloc_fail) },
 489         { "Tx DMA chan: runt_receive_buf", CPDMA_TX_STAT(runt_receive_buff) },
 490         { "Tx DMA chan: runt_transmit_buf", CPDMA_TX_STAT(runt_transmit_buff) },
 491         { "Tx DMA chan: empty_dequeue", CPDMA_TX_STAT(empty_dequeue) },
 492         { "Tx DMA chan: busy_dequeue", CPDMA_TX_STAT(busy_dequeue) },
 493         { "Tx DMA chan: good_dequeue", CPDMA_TX_STAT(good_dequeue) },
 494         { "Tx DMA chan: requeue", CPDMA_TX_STAT(requeue) },
 495         { "Tx DMA chan: teardown_dequeue", CPDMA_TX_STAT(teardown_dequeue) },
 496 };
 497
 498 #define CPSW_STATS_LEN  ARRAY_SIZE(cpsw_gstrings_stats)
 499
 500 #define napi_to_priv(napi)      container_of(napi, struct cpsw_priv, napi)
 501 #define for_each_slave(priv, func, arg...)                              \
 502         do {                                                            \
 503                 struct cpsw_slave *slave;                               \
 504                 int n;                                                  \
 505                 if (priv->data.dual_emac)                               \
 506                         (func)((priv)->slaves + priv->emac_port, ##arg);\
 507                 else                                                    \
 508                         for (n = (priv)->data.slaves,                   \
 509                                         slave = (priv)->slaves;         \
 510                                         n; n--)                         \
 511                                 (func)(slave++, ##arg);                 \
 512         } while (0)
 513 #define cpsw_get_slave_ndev(priv, __slave_no__)                         \
 514         (priv->slaves[__slave_no__].ndev)
 515 #define cpsw_get_slave_priv(priv, __slave_no__)                         \
 516         ((priv->slaves[__slave_no__].ndev) ?                            \
 517                 netdev_priv(priv->slaves[__slave_no__].ndev) : NULL)    \
 518
 519 #define cpsw_dual_emac_src_port_detect(status, priv, ndev, skb)         \
 520         do {                                                            \
 521                 if (!priv->data.dual_emac)                              \
 522                         break;                                          \
 523                 if (CPDMA_RX_SOURCE_PORT(status) == 1) {                \
 524                         ndev = cpsw_get_slave_ndev(priv, 0);            \
 525                         priv = netdev_priv(ndev);                       \
 526                         skb->dev = ndev;                                \
 527                 } else if (CPDMA_RX_SOURCE_PORT(status) == 2) {         \
 528                         ndev = cpsw_get_slave_ndev(priv, 1);            \
 529                         priv = netdev_priv(ndev);                       \
 530                         skb->dev = ndev;                                \
 531                 }                                                       \
 532         } while (0)
 533 #define cpsw_add_mcast(priv, addr)                                      \
 534         do {                                                            \
 535                 if (priv->data.dual_emac) {                             \
 536                         struct cpsw_slave *slave = priv->slaves +       \
 537                                                 priv->emac_port;        \
 538                         int slave_port = cpsw_get_slave_port(priv,      \
 539                                                 slave->slave_num);      \
 540                         cpsw_ale_add_mcast(priv->ale, addr,             \
 541                                 1 << slave_port | 1 << priv->host_port, \
 542                                 ALE_VLAN, slave->port_vlan, 0);         \
 543                 } else {                                                \
 544                         cpsw_ale_add_mcast(priv->ale, addr,             \
 545                                 ALE_ALL_PORTS << priv->host_port,       \
 546                                 0, 0, 0);                               \
 547                 }                                                       \
 548         } while (0)
 549
 550 static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
 551 {
 552         if (priv->host_port == 0)
 553                 return slave_num + 1;
 554         else
 555                 return slave_num;
 556 }
 557
 558 static void cpsw_set_promiscious(struct net_device *ndev, bool enable)
 559 {
 560         struct cpsw_priv *priv = netdev_priv(ndev);
 561         struct cpsw_ale *ale = priv->ale;
 562         int i;
 563
 564         if (priv->data.dual_emac) {
 565                 bool flag = false;
 566
 567                 /* Enabling promiscuous mode for one interface will be
 568                  * common for both the interface as the interface shares
 569                  * the same hardware resource.
 570                  */
 571                 for (i = 0; i < priv->data.slaves; i++)
 572                         if (priv->slaves[i].ndev->flags & IFF_PROMISC)
 573                                 flag = true;
 574
 575                 if (!enable && flag) {
 576                         enable = true;
 577                         dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n");
 578                 }
 579
 580                 if (enable) {
 581                         /* Enable Bypass */
 582                         cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1);
 583
 584                         dev_dbg(&ndev->dev, "promiscuity enabled\n");
 585                 } else {
 586                         /* Disable Bypass */
 587                         cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0);
 588                         dev_dbg(&ndev->dev, "promiscuity disabled\n");
 589                 }
 590         } else {
 591                 if (enable) {
 592                         unsigned long timeout = jiffies + HZ;
 593
 594                         /* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */
 595                         for (i = 0; i <= priv->data.slaves; i++) {
 596                                 cpsw_ale_control_set(ale, i,
 597                                                      ALE_PORT_NOLEARN, 1);
 598                                 cpsw_ale_control_set(ale, i,
 599                                                      ALE_PORT_NO_SA_UPDATE, 1);
 600                         }
 601
 602                         /* Clear All Untouched entries */
 603                         cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
 604                         do {
 605                                 cpu_relax();
 606                                 if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT))
 607                                         break;
 608                         } while (time_after(timeout, jiffies));
 609                         cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
 610
 611                         /* Clear all mcast from ALE */
 612                         cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS <<
 613                                                  priv->host_port);
 614
 615                         /* Flood All Unicast Packets to Host port */
 616                         cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1);
 617                         dev_dbg(&ndev->dev, "promiscuity enabled\n");
 618                 } else {
 619                         /* Don't Flood All Unicast Packets to Host port */
 620                         cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0);
 621
 622                         /* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */
 623                         for (i = 0; i <= priv->data.slaves; i++) {
 624                                 cpsw_ale_control_set(ale, i,
 625                                                      ALE_PORT_NOLEARN, 0);
 626                                 cpsw_ale_control_set(ale, i,
 627                                                      ALE_PORT_NO_SA_UPDATE, 0);
 628                         }
 629                         dev_dbg(&ndev->dev, "promiscuity disabled\n");
 630                 }
 631         }
 632 }
 633
 634 static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
 635 {
 636         struct cpsw_priv *priv = netdev_priv(ndev);
 637
 638         if (ndev->flags & IFF_PROMISC) {
 639                 /* Enable promiscuous mode */
 640                 cpsw_set_promiscious(ndev, true);
 641                 cpsw_ale_set_allmulti(priv->ale, IFF_ALLMULTI);
 642                 return;
 643         } else {
 644                 /* Disable promiscuous mode */
 645                 cpsw_set_promiscious(ndev, false);
 646         }
 647
 648         /* Restore allmulti on vlans if necessary */
 649         cpsw_ale_set_allmulti(priv->ale, priv->ndev->flags & IFF_ALLMULTI);
 650
 651         /* Clear all mcast from ALE */
 652         cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port);
 653
 654         if (!netdev_mc_empty(ndev)) {
 655                 struct netdev_hw_addr *ha;
 656
 657                 /* program multicast address list into ALE register */
 658                 netdev_for_each_mc_addr(ha, ndev) {
 659                         cpsw_add_mcast(priv, (u8 *)ha->addr);
 660                 }
 661         }
 662 }
 663
 664 static void cpsw_intr_enable(struct cpsw_priv *priv)
 665 {
 666         __raw_writel(0xFF, &priv->wr_regs->tx_en);
 667         __raw_writel(0xFF, &priv->wr_regs->rx_en);
 668
 669         cpdma_ctlr_int_ctrl(priv->dma, true);
 670         return;
 671 }
 672
 673 static void cpsw_intr_disable(struct cpsw_priv *priv)
 674 {
 675         __raw_writel(0, &priv->wr_regs->tx_en);
 676         __raw_writel(0, &priv->wr_regs->rx_en);
 677
 678         cpdma_ctlr_int_ctrl(priv->dma, false);
 679         return;
 680 }
 681
 682 static void cpsw_tx_handler(void *token, int len, int status)
 683 {
 684         struct sk_buff          *skb = token;
 685         struct net_device       *ndev = skb->dev;
 686         struct cpsw_priv        *priv = netdev_priv(ndev);
 687
 688         /* Check whether the queue is stopped due to stalled tx dma, if the
 689          * queue is stopped then start the queue as we have free desc for tx
 690          */
 691         if (unlikely(netif_queue_stopped(ndev)))
 692                 netif_wake_queue(ndev);
 693         cpts_tx_timestamp(priv->cpts, skb);
 694         ndev->stats.tx_packets++;
 695         ndev->stats.tx_bytes += len;
 696         dev_kfree_skb_any(skb);
 697 }
 698
 699 static void cpsw_rx_handler(void *token, int len, int status)
 700 {
 701         struct sk_buff          *skb = token;
 702         struct sk_buff          *new_skb;
 703         struct net_device       *ndev = skb->dev;
 704         struct cpsw_priv        *priv = netdev_priv(ndev);
 705         int                     ret = 0;
 706
 707         cpsw_dual_emac_src_port_detect(status, priv, ndev, skb);
 708
 709         if (unlikely(status < 0) || unlikely(!netif_running(ndev))) {
 710                 bool ndev_status = false;
 711                 struct cpsw_slave *slave = priv->slaves;
 712                 int n;
 713
 714                 if (priv->data.dual_emac) {
 715                         /* In dual emac mode check for all interfaces */
 716                         for (n = priv->data.slaves; n; n--, slave++)
 717                                 if (netif_running(slave->ndev))
 718                                         ndev_status = true;
 719                 }
 720
 721                 if (ndev_status && (status >= 0)) {
 722                         /* The packet received is for the interface which
 723                          * is already down and the other interface is up
 724                          * and running, intead of freeing which results
 725                          * in reducing of the number of rx descriptor in
 726                          * DMA engine, requeue skb back to cpdma.
 727                          */
 728                         new_skb = skb;
 729                         goto requeue;
 730                 }
 731
 732                 /* the interface is going down, skbs are purged */
 733                 dev_kfree_skb_any(skb);
 734                 return;
 735         }
 736
 737         new_skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max);
 738         if (new_skb) {
 739                 skb_put(skb, len);
 740                 cpts_rx_timestamp(priv->cpts, skb);
 741                 skb->protocol = eth_type_trans(skb, ndev);
 742                 netif_receive_skb(skb);
 743                 ndev->stats.rx_bytes += len;
 744                 ndev->stats.rx_packets++;
 745         } else {
 746                 ndev->stats.rx_dropped++;
 747                 new_skb = skb;
 748         }
 749
 750 requeue:
 751         ret = cpdma_chan_submit(priv->rxch, new_skb, new_skb->data,
 752                         skb_tailroom(new_skb), 0);
 753         if (WARN_ON(ret < 0))
 754                 dev_kfree_skb_any(new_skb);
 755 }
 756
 757 static irqreturn_t cpsw_interrupt(int irq, void *dev_id)
 758 {
 759         struct cpsw_priv *priv = dev_id;
 760         int value = irq - priv->irqs_table[0];
 761
 762         /* NOTICE: Ending IRQ here. The trick with the 'value' variable above
 763          * is to make sure we will always write the correct value to the EOI
 764          * register. Namely 0 for RX_THRESH Interrupt, 1 for RX Interrupt, 2
 765          * for TX Interrupt and 3 for MISC Interrupt.
 766          */
 767         cpdma_ctlr_eoi(priv->dma, value);
 768
 769         cpsw_intr_disable(priv);
 770         if (priv->irq_enabled == true) {
 771                 cpsw_disable_irq(priv);
 772                 priv->irq_enabled = false;
 773         }
 774
 775         if (netif_running(priv->ndev)) {
 776                 napi_schedule(&priv->napi);
 777                 return IRQ_HANDLED;
 778         }
 779
 780         priv = cpsw_get_slave_priv(priv, 1);
 781         if (!priv)
 782                 return IRQ_NONE;
 783
 784         if (netif_running(priv->ndev)) {
 785                 napi_schedule(&priv->napi);
 786                 return IRQ_HANDLED;
 787         }
 788         return IRQ_NONE;
 789 }
 790
 791 static int cpsw_poll(struct napi_struct *napi, int budget)
 792 {
 793         struct cpsw_priv        *priv = napi_to_priv(napi);
 794         int                     num_tx, num_rx;
 795
 796         num_tx = cpdma_chan_process(priv->txch, 128);
 797
 798         num_rx = cpdma_chan_process(priv->rxch, budget);
 799         if (num_rx < budget) {
 800                 struct cpsw_priv *prim_cpsw;
 801
 802                 napi_complete(napi);
 803                 cpsw_intr_enable(priv);
 804                 prim_cpsw = cpsw_get_slave_priv(priv, 0);
 805                 if (prim_cpsw->irq_enabled == false) {
 806                         prim_cpsw->irq_enabled = true;
 807                         cpsw_enable_irq(priv);
 808                 }
 809         }
 810
 811         if (num_rx || num_tx)
 812                 cpsw_dbg(priv, intr, "poll %d rx, %d tx pkts\n",
 813                          num_rx, num_tx);
 814
 815         return num_rx;
 816 }
 817
 818 static inline void soft_reset(const char *module, void __iomem *reg)
 819 {
 820         unsigned long timeout = jiffies + HZ;
 821
 822         __raw_writel(1, reg);
 823         do {
 824                 cpu_relax();
 825         } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));
 826
 827         WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);
 828 }
 829
 830 #define mac_hi(mac)     (((mac)[0] << 0) | ((mac)[1] << 8) |    \
 831                          ((mac)[2] << 16) | ((mac)[3] << 24))
 832 #define mac_lo(mac)     (((mac)[4] << 0) | ((mac)[5] << 8))
 833
 834 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
 835                                struct cpsw_priv *priv)
 836 {
 837         slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
 838         slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
 839 }
 840
 841 static void _cpsw_adjust_link(struct cpsw_slave *slave,
 842                               struct cpsw_priv *priv, bool *link)
 843 {
 844         struct phy_device       *phy = slave->phy;
 845         u32                     mac_control = 0;
 846         u32                     slave_port;
 847
 848         if (!phy)
 849                 return;
 850
 851         slave_port = cpsw_get_slave_port(priv, slave->slave_num);
 852
 853         if (phy->link) {
 854                 mac_control = priv->data.mac_control;
 855
 856                 /* enable forwarding */
 857                 cpsw_ale_control_set(priv->ale, slave_port,
 858                                      ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
 859
 860                 if (phy->speed == 1000)
 861                         mac_control |= BIT(7);  /* GIGABITEN    */
 862                 if (phy->duplex)
 863                         mac_control |= BIT(0);  /* FULLDUPLEXEN */
 864
 865                 /* set speed_in input in case RMII mode is used in 100Mbps */
 866                 if (phy->speed == 100)
 867                         mac_control |= BIT(15);
 868                 else if (phy->speed == 10)
 869                         mac_control |= BIT(18); /* In Band mode */
 870
 871                 if (priv->rx_pause)
 872                         mac_control |= BIT(3);
 873
 874                 if (priv->tx_pause)
 875                         mac_control |= BIT(4);
 876
 877                 *link = true;
 878         } else {
 879                 mac_control = 0;
 880                 /* disable forwarding */
 881                 cpsw_ale_control_set(priv->ale, slave_port,
 882                                      ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
 883         }
 884
 885         if (mac_control != slave->mac_control) {
 886                 phy_print_status(phy);
 887                 __raw_writel(mac_control, &slave->sliver->mac_control);
 888         }
 889
 890         slave->mac_control = mac_control;
 891 }
 892
 893 static void cpsw_adjust_link(struct net_device *ndev)
 894 {
 895         struct cpsw_priv        *priv = netdev_priv(ndev);
 896         bool                    link = false;
 897
 898         for_each_slave(priv, _cpsw_adjust_link, priv, &link);
 899
 900         if (link) {
 901                 netif_carrier_on(ndev);
 902                 if (netif_running(ndev))
 903                         netif_wake_queue(ndev);
 904         } else {
 905                 netif_carrier_off(ndev);
 906                 netif_stop_queue(ndev);
 907         }
 908 }
 909
 910 static int cpsw_get_coalesce(struct net_device *ndev,
 911                                 struct ethtool_coalesce *coal)
 912 {
 913         struct cpsw_priv *priv = netdev_priv(ndev);
 914
 915         coal->rx_coalesce_usecs = priv->coal_intvl;
 916         return 0;
 917 }
 918
 919 static int cpsw_set_coalesce(struct net_device *ndev,
 920                                 struct ethtool_coalesce *coal)
 921 {
 922         struct cpsw_priv *priv = netdev_priv(ndev);
 923         u32 int_ctrl;
 924         u32 num_interrupts = 0;
 925         u32 prescale = 0;
 926         u32 addnl_dvdr = 1;
 927         u32 coal_intvl = 0;
 928
 929         coal_intvl = coal->rx_coalesce_usecs;
 930
 931         int_ctrl =  readl(&priv->wr_regs->int_control);
 932         prescale = priv->bus_freq_mhz * 4;
 933
 934         if (!coal->rx_coalesce_usecs) {
 935                 int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN);
 936                 goto update_return;
 937         }
 938
 939         if (coal_intvl < CPSW_CMINTMIN_INTVL)
 940                 coal_intvl = CPSW_CMINTMIN_INTVL;
 941
 942         if (coal_intvl > CPSW_CMINTMAX_INTVL) {
 943                 /* Interrupt pacer works with 4us Pulse, we can
 944                  * throttle further by dilating the 4us pulse.
 945                  */
 946                 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
 947
 948                 if (addnl_dvdr > 1) {
 949                         prescale *= addnl_dvdr;
 950                         if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
 951                                 coal_intvl = (CPSW_CMINTMAX_INTVL
 952                                                 * addnl_dvdr);
 953                 } else {
 954                         addnl_dvdr = 1;
 955                         coal_intvl = CPSW_CMINTMAX_INTVL;
 956                 }
 957         }
 958
 959         num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
 960         writel(num_interrupts, &priv->wr_regs->rx_imax);
 961         writel(num_interrupts, &priv->wr_regs->tx_imax);
 962
 963         int_ctrl |= CPSW_INTPACEEN;
 964         int_ctrl &= (~CPSW_INTPRESCALE_MASK);
 965         int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
 966
 967 update_return:
 968         writel(int_ctrl, &priv->wr_regs->int_control);
 969
 970         cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
 971         if (priv->data.dual_emac) {
 972                 int i;
 973
 974                 for (i = 0; i < priv->data.slaves; i++) {
 975                         priv = netdev_priv(priv->slaves[i].ndev);
 976                         priv->coal_intvl = coal_intvl;
 977                 }
 978         } else {
 979                 priv->coal_intvl = coal_intvl;
 980         }
 981
 982         return 0;
 983 }
 984
 985 static int cpsw_get_sset_count(struct net_device *ndev, int sset)
 986 {
 987         switch (sset) {
 988         case ETH_SS_STATS:
 989                 return CPSW_STATS_LEN;
 990         default:
 991                 return -EOPNOTSUPP;
 992         }
 993 }
 994
 995 static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
 996 {
 997         u8 *p = data;
 998         int i;
 999
1000         switch (stringset) {
1001         case ETH_SS_STATS:
1002                 for (i = 0; i < CPSW_STATS_LEN; i++) {
1003                         memcpy(p, cpsw_gstrings_stats[i].stat_string,
1004                                ETH_GSTRING_LEN);
1005                         p += ETH_GSTRING_LEN;
1006                 }
1007                 break;
1008         }
1009 }
1010
1011 static void cpsw_get_ethtool_stats(struct net_device *ndev,
1012                                     struct ethtool_stats *stats, u64 *data)
1013 {
1014         struct cpsw_priv *priv = netdev_priv(ndev);
1015         struct cpdma_chan_stats rx_stats;
1016         struct cpdma_chan_stats tx_stats;
1017         u32 val;
1018         u8 *p;
1019         int i;
1020
1021         /* Collect Davinci CPDMA stats for Rx and Tx Channel */
1022         cpdma_chan_get_stats(priv->rxch, &rx_stats);
1023         cpdma_chan_get_stats(priv->txch, &tx_stats);
1024
1025         for (i = 0; i < CPSW_STATS_LEN; i++) {
1026                 switch (cpsw_gstrings_stats[i].type) {
1027                 case CPSW_STATS:
1028                         val = readl(priv->hw_stats +
1029                                     cpsw_gstrings_stats[i].stat_offset);
1030                         data[i] = val;
1031                         break;
1032
1033                 case CPDMA_RX_STATS:
1034                         p = (u8 *)&rx_stats +
1035                                 cpsw_gstrings_stats[i].stat_offset;
1036                         data[i] = *(u32 *)p;
1037                         break;
1038
1039                 case CPDMA_TX_STATS:
1040                         p = (u8 *)&tx_stats +
1041                                 cpsw_gstrings_stats[i].stat_offset;
1042                         data[i] = *(u32 *)p;
1043                         break;
1044                 }
1045         }
1046 }
1047
1048 static int cpsw_common_res_usage_state(struct cpsw_priv *priv)
1049 {
1050         u32 i;
1051         u32 usage_count = 0;
1052
1053         if (!priv->data.dual_emac)
1054                 return 0;
1055
1056         for (i = 0; i < priv->data.slaves; i++)
1057                 if (priv->slaves[i].open_stat)
1058                         usage_count++;
1059
1060         return usage_count;
1061 }
1062
1063 static inline int cpsw_tx_packet_submit(struct net_device *ndev,
1064                         struct cpsw_priv *priv, struct sk_buff *skb)
1065 {
1066         if (!priv->data.dual_emac)
1067                 return cpdma_chan_submit(priv->txch, skb, skb->data,
1068                                   skb->len, 0);
1069
1070         if (ndev == cpsw_get_slave_ndev(priv, 0))
1071                 return cpdma_chan_submit(priv->txch, skb, skb->data,
1072                                   skb->len, 1);
1073         else
1074                 return cpdma_chan_submit(priv->txch, skb, skb->data,
1075                                   skb->len, 2);
1076 }
1077
1078 static inline void cpsw_add_dual_emac_def_ale_entries(
1079                 struct cpsw_priv *priv, struct cpsw_slave *slave,
1080                 u32 slave_port)
1081 {
1082         u32 port_mask = 1 << slave_port | 1 << priv->host_port;
1083
1084         if (priv->version == CPSW_VERSION_1)
1085                 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
1086         else
1087                 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
1088         cpsw_ale_add_vlan(priv->ale, slave->port_vlan, port_mask,
1089                           port_mask, port_mask, 0);
1090         cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1091                            port_mask, ALE_VLAN, slave->port_vlan, 0);
1092         cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
1093                 priv->host_port, ALE_VLAN, slave->port_vlan);
1094 }
1095
1096 static void soft_reset_slave(struct cpsw_slave *slave)
1097 {
1098         char name[32];
1099
1100         snprintf(name, sizeof(name), "slave-%d", slave->slave_num);
1101         soft_reset(name, &slave->sliver->soft_reset);
1102 }
1103
1104 static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
1105 {
1106         u32 slave_port;
1107
1108         soft_reset_slave(slave);
1109
1110         /* setup priority mapping */
1111         __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
1112
1113         switch (priv->version) {
1114         case CPSW_VERSION_1:
1115                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
1116                 break;
1117         case CPSW_VERSION_2:
1118         case CPSW_VERSION_3:
1119         case CPSW_VERSION_4:
1120                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
1121                 break;
1122         }
1123
1124         /* setup max packet size, and mac address */
1125         __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen);
1126         cpsw_set_slave_mac(slave, priv);
1127
1128         slave->mac_control = 0; /* no link yet */
1129
1130         slave_port = cpsw_get_slave_port(priv, slave->slave_num);
1131
1132         if (priv->data.dual_emac)
1133                 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
1134         else
1135                 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1136                                    1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
1137
1138         slave->phy = phy_connect(priv->ndev, slave->data->phy_id,
1139                                  &cpsw_adjust_link, slave->data->phy_if);
1140         if (IS_ERR(slave->phy)) {
1141                 dev_err(priv->dev, "phy %s not found on slave %d\n",
1142                         slave->data->phy_id, slave->slave_num);
1143                 slave->phy = NULL;
1144         } else {
1145                 dev_info(priv->dev, "phy found : id is : 0x%x\n",
1146                          slave->phy->phy_id);
1147                 phy_start(slave->phy);
1148
1149                 /* Configure GMII_SEL register */
1150                 cpsw_phy_sel(&priv->pdev->dev, slave->phy->interface,
1151                              slave->slave_num);
1152         }
1153 }
1154
1155 static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
1156 {
1157         const int vlan = priv->data.default_vlan;
1158         const int port = priv->host_port;
1159         u32 reg;
1160         int i;
1161         int unreg_mcast_mask;
1162
1163         reg = (priv->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
1164                CPSW2_PORT_VLAN;
1165
1166         writel(vlan, &priv->host_port_regs->port_vlan);
1167
1168         for (i = 0; i < priv->data.slaves; i++)
1169                 slave_write(priv->slaves + i, vlan, reg);
1170
1171         if (priv->ndev->flags & IFF_ALLMULTI)
1172                 unreg_mcast_mask = ALE_ALL_PORTS;
1173         else
1174                 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1175
1176         cpsw_ale_add_vlan(priv->ale, vlan, ALE_ALL_PORTS << port,
1177                           ALE_ALL_PORTS << port, ALE_ALL_PORTS << port,
1178                           unreg_mcast_mask << port);
1179 }
1180
1181 static void cpsw_init_host_port(struct cpsw_priv *priv)
1182 {
1183         u32 control_reg;
1184         u32 fifo_mode;
1185
1186         /* soft reset the controller and initialize ale */
1187         soft_reset("cpsw", &priv->regs->soft_reset);
1188         cpsw_ale_start(priv->ale);
1189
1190         /* switch to vlan unaware mode */
1191         cpsw_ale_control_set(priv->ale, priv->host_port, ALE_VLAN_AWARE,
1192                              CPSW_ALE_VLAN_AWARE);
1193         control_reg = readl(&priv->regs->control);
1194         control_reg |= CPSW_VLAN_AWARE;
1195         writel(control_reg, &priv->regs->control);
1196         fifo_mode = (priv->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
1197                      CPSW_FIFO_NORMAL_MODE;
1198         writel(fifo_mode, &priv->host_port_regs->tx_in_ctl);
1199
1200         /* setup host port priority mapping */
1201         __raw_writel(CPDMA_TX_PRIORITY_MAP,
1202                      &priv->host_port_regs->cpdma_tx_pri_map);
1203         __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
1204
1205         cpsw_ale_control_set(priv->ale, priv->host_port,
1206                              ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1207
1208         if (!priv->data.dual_emac) {
1209                 cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port,
1210                                    0, 0);
1211                 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1212                                    1 << priv->host_port, 0, 0, ALE_MCAST_FWD_2);
1213         }
1214 }
1215
1216 static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv)
1217 {
1218         u32 slave_port;
1219
1220         slave_port = cpsw_get_slave_port(priv, slave->slave_num);
1221
1222         if (!slave->phy)
1223                 return;
1224         phy_stop(slave->phy);
1225         phy_disconnect(slave->phy);
1226         slave->phy = NULL;
1227         cpsw_ale_control_set(priv->ale, slave_port,
1228                              ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1229 }
1230
1231 static int cpsw_ndo_open(struct net_device *ndev)
1232 {
1233         struct cpsw_priv *priv = netdev_priv(ndev);
1234         struct cpsw_priv *prim_cpsw;
1235         int i, ret;
1236         u32 reg;
1237
1238         if (!cpsw_common_res_usage_state(priv))
1239                 cpsw_intr_disable(priv);
1240         netif_carrier_off(ndev);
1241
1242         pm_runtime_get_sync(&priv->pdev->dev);
1243
1244         reg = priv->version;
1245
1246         dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
1247                  CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
1248                  CPSW_RTL_VERSION(reg));
1249
1250         /* initialize host and slave ports */
1251         if (!cpsw_common_res_usage_state(priv))
1252                 cpsw_init_host_port(priv);
1253         for_each_slave(priv, cpsw_slave_open, priv);
1254
1255         /* Add default VLAN */
1256         if (!priv->data.dual_emac)
1257                 cpsw_add_default_vlan(priv);
1258         else
1259                 cpsw_ale_add_vlan(priv->ale, priv->data.default_vlan,
1260                                   ALE_ALL_PORTS << priv->host_port,
1261                                   ALE_ALL_PORTS << priv->host_port, 0, 0);
1262
1263         if (!cpsw_common_res_usage_state(priv)) {
1264                 /* setup tx dma to fixed prio and zero offset */
1265                 cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1);
1266                 cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0);
1267
1268                 /* disable priority elevation */
1269                 __raw_writel(0, &priv->regs->ptype);
1270
1271                 /* enable statistics collection only on all ports */
1272                 __raw_writel(0x7, &priv->regs->stat_port_en);
1273
1274                 /* Enable internal fifo flow control */
1275                 writel(0x7, &priv->regs->flow_control);
1276
1277                 if (WARN_ON(!priv->data.rx_descs))
1278                         priv->data.rx_descs = 128;
1279
1280                 for (i = 0; i < priv->data.rx_descs; i++) {
1281                         struct sk_buff *skb;
1282
1283                         ret = -ENOMEM;
1284                         skb = __netdev_alloc_skb_ip_align(priv->ndev,
1285                                         priv->rx_packet_max, GFP_KERNEL);
1286                         if (!skb)
1287                                 goto err_cleanup;
1288                         ret = cpdma_chan_submit(priv->rxch, skb, skb->data,
1289                                         skb_tailroom(skb), 0);
1290                         if (ret < 0) {
1291                                 kfree_skb(skb);
1292                                 goto err_cleanup;
1293                         }
1294                 }
1295                 /* continue even if we didn't manage to submit all
1296                  * receive descs
1297                  */
1298                 cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i);
1299
1300                 if (cpts_register(&priv->pdev->dev, priv->cpts,
1301                                   priv->data.cpts_clock_mult,
1302                                   priv->data.cpts_clock_shift))
1303                         dev_err(priv->dev, "error registering cpts device\n");
1304
1305         }
1306
1307         /* Enable Interrupt pacing if configured */
1308         if (priv->coal_intvl != 0) {
1309                 struct ethtool_coalesce coal;
1310
1311                 coal.rx_coalesce_usecs = (priv->coal_intvl << 4);
1312                 cpsw_set_coalesce(ndev, &coal);
1313         }
1314
1315         napi_enable(&priv->napi);
1316         cpdma_ctlr_start(priv->dma);
1317         cpsw_intr_enable(priv);
1318
1319         prim_cpsw = cpsw_get_slave_priv(priv, 0);
1320         if (prim_cpsw->irq_enabled == false) {
1321                 if ((priv == prim_cpsw) || !netif_running(prim_cpsw->ndev)) {
1322                         prim_cpsw->irq_enabled = true;
1323                         cpsw_enable_irq(prim_cpsw);
1324                 }
1325         }
1326
1327         if (priv->data.dual_emac)
1328                 priv->slaves[priv->emac_port].open_stat = true;
1329         return 0;
1330
1331 err_cleanup:
1332         cpdma_ctlr_stop(priv->dma);
1333         for_each_slave(priv, cpsw_slave_stop, priv);
1334         pm_runtime_put_sync(&priv->pdev->dev);
1335         netif_carrier_off(priv->ndev);
1336         return ret;
1337 }
1338
1339 static int cpsw_ndo_stop(struct net_device *ndev)
1340 {
1341         struct cpsw_priv *priv = netdev_priv(ndev);
1342
1343         cpsw_info(priv, ifdown, "shutting down cpsw device\n");
1344         netif_stop_queue(priv->ndev);
1345         napi_disable(&priv->napi);
1346         netif_carrier_off(priv->ndev);
1347
1348         if (cpsw_common_res_usage_state(priv) <= 1) {
1349                 cpts_unregister(priv->cpts);
1350                 cpsw_intr_disable(priv);
1351                 cpdma_ctlr_int_ctrl(priv->dma, false);
1352                 cpdma_ctlr_stop(priv->dma);
1353                 cpsw_ale_stop(priv->ale);
1354         }
1355         for_each_slave(priv, cpsw_slave_stop, priv);
1356         pm_runtime_put_sync(&priv->pdev->dev);
1357         if (priv->data.dual_emac)
1358                 priv->slaves[priv->emac_port].open_stat = false;
1359         return 0;
1360 }
1361
1362 static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
1363                                        struct net_device *ndev)
1364 {
1365         struct cpsw_priv *priv = netdev_priv(ndev);
1366         int ret;
1367
1368         ndev->trans_start = jiffies;
1369
1370         if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
1371                 cpsw_err(priv, tx_err, "packet pad failed\n");
1372                 ndev->stats.tx_dropped++;
1373                 return NETDEV_TX_OK;
1374         }
1375
1376         if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
1377                                 priv->cpts->tx_enable)
1378                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1379
1380         skb_tx_timestamp(skb);
1381
1382         ret = cpsw_tx_packet_submit(ndev, priv, skb);
1383         if (unlikely(ret != 0)) {
1384                 cpsw_err(priv, tx_err, "desc submit failed\n");
1385                 goto fail;
1386         }
1387
1388         /* If there is no more tx desc left free then we need to
1389          * tell the kernel to stop sending us tx frames.
1390          */
1391         if (unlikely(!cpdma_check_free_tx_desc(priv->txch)))
1392                 netif_stop_queue(ndev);
1393
1394         return NETDEV_TX_OK;
1395 fail:
1396         ndev->stats.tx_dropped++;
1397         netif_stop_queue(ndev);
1398         return NETDEV_TX_BUSY;
1399 }
1400
1401 #ifdef CONFIG_TI_CPTS
1402
1403 static void cpsw_hwtstamp_v1(struct cpsw_priv *priv)
1404 {
1405         struct cpsw_slave *slave = &priv->slaves[priv->data.active_slave];
1406         u32 ts_en, seq_id;
1407
1408         if (!priv->cpts->tx_enable && !priv->cpts->rx_enable) {
1409                 slave_write(slave, 0, CPSW1_TS_CTL);
1410                 return;
1411         }
1412
1413         seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
1414         ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
1415
1416         if (priv->cpts->tx_enable)
1417                 ts_en |= CPSW_V1_TS_TX_EN;
1418
1419         if (priv->cpts->rx_enable)
1420                 ts_en |= CPSW_V1_TS_RX_EN;
1421
1422         slave_write(slave, ts_en, CPSW1_TS_CTL);
1423         slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
1424 }
1425
1426 static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
1427 {
1428         struct cpsw_slave *slave;
1429         u32 ctrl, mtype;
1430
1431         if (priv->data.dual_emac)
1432                 slave = &priv->slaves[priv->emac_port];
1433         else
1434                 slave = &priv->slaves[priv->data.active_slave];
1435
1436         ctrl = slave_read(slave, CPSW2_CONTROL);
1437         switch (priv->version) {
1438         case CPSW_VERSION_2:
1439                 ctrl &= ~CTRL_V2_ALL_TS_MASK;
1440
1441                 if (priv->cpts->tx_enable)
1442                         ctrl |= CTRL_V2_TX_TS_BITS;
1443
1444                 if (priv->cpts->rx_enable)
1445                         ctrl |= CTRL_V2_RX_TS_BITS;
1446         break;
1447         case CPSW_VERSION_3:
1448         default:
1449                 ctrl &= ~CTRL_V3_ALL_TS_MASK;
1450
1451                 if (priv->cpts->tx_enable)
1452                         ctrl |= CTRL_V3_TX_TS_BITS;
1453
1454                 if (priv->cpts->rx_enable)
1455                         ctrl |= CTRL_V3_RX_TS_BITS;
1456         break;
1457         }
1458
1459         mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
1460
1461         slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
1462         slave_write(slave, ctrl, CPSW2_CONTROL);
1463         __raw_writel(ETH_P_1588, &priv->regs->ts_ltype);
1464 }
1465
1466 static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
1467 {
1468         struct cpsw_priv *priv = netdev_priv(dev);
1469         struct cpts *cpts = priv->cpts;
1470         struct hwtstamp_config cfg;
1471
1472         if (priv->version != CPSW_VERSION_1 &&
1473             priv->version != CPSW_VERSION_2 &&
1474             priv->version != CPSW_VERSION_3)
1475                 return -EOPNOTSUPP;
1476
1477         if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1478                 return -EFAULT;
1479
1480         /* reserved for future extensions */
1481         if (cfg.flags)
1482                 return -EINVAL;
1483
1484         if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
1485                 return -ERANGE;
1486
1487         switch (cfg.rx_filter) {
1488         case HWTSTAMP_FILTER_NONE:
1489                 cpts->rx_enable = 0;
1490                 break;
1491         case HWTSTAMP_FILTER_ALL:
1492         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1493         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1494         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1495                 return -ERANGE;
1496         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1497         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1498         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1499         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1500         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1501         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1502         case HWTSTAMP_FILTER_PTP_V2_EVENT:
1503         case HWTSTAMP_FILTER_PTP_V2_SYNC:
1504         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1505                 cpts->rx_enable = 1;
1506                 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1507                 break;
1508         default:
1509                 return -ERANGE;
1510         }
1511
1512         cpts->tx_enable = cfg.tx_type == HWTSTAMP_TX_ON;
1513
1514         switch (priv->version) {
1515         case CPSW_VERSION_1:
1516                 cpsw_hwtstamp_v1(priv);
1517                 break;
1518         case CPSW_VERSION_2:
1519         case CPSW_VERSION_3:
1520                 cpsw_hwtstamp_v2(priv);
1521                 break;
1522         default:
1523                 WARN_ON(1);
1524         }
1525
1526         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1527 }
1528
1529 static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1530 {
1531         struct cpsw_priv *priv = netdev_priv(dev);
1532         struct cpts *cpts = priv->cpts;
1533         struct hwtstamp_config cfg;
1534
1535         if (priv->version != CPSW_VERSION_1 &&
1536             priv->version != CPSW_VERSION_2 &&
1537             priv->version != CPSW_VERSION_3)
1538                 return -EOPNOTSUPP;
1539
1540         cfg.flags = 0;
1541         cfg.tx_type = cpts->tx_enable ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
1542         cfg.rx_filter = (cpts->rx_enable ?
1543                          HWTSTAMP_FILTER_PTP_V2_EVENT : HWTSTAMP_FILTER_NONE);
1544
1545         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1546 }
1547
1548 #endif /*CONFIG_TI_CPTS*/
1549
1550 static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
1551 {
1552         struct cpsw_priv *priv = netdev_priv(dev);
1553         int slave_no = cpsw_slave_index(priv);
1554
1555         if (!netif_running(dev))
1556                 return -EINVAL;
1557
1558         switch (cmd) {
1559 #ifdef CONFIG_TI_CPTS
1560         case SIOCSHWTSTAMP:
1561                 return cpsw_hwtstamp_set(dev, req);
1562         case SIOCGHWTSTAMP:
1563                 return cpsw_hwtstamp_get(dev, req);
1564 #endif
1565         }
1566
1567         if (!priv->slaves[slave_no].phy)
1568                 return -EOPNOTSUPP;
1569         return phy_mii_ioctl(priv->slaves[slave_no].phy, req, cmd);
1570 }
1571
1572 static void cpsw_ndo_tx_timeout(struct net_device *ndev)
1573 {
1574         struct cpsw_priv *priv = netdev_priv(ndev);
1575
1576         cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
1577         ndev->stats.tx_errors++;
1578         cpsw_intr_disable(priv);
1579         cpdma_ctlr_int_ctrl(priv->dma, false);
1580         cpdma_chan_stop(priv->txch);
1581         cpdma_chan_start(priv->txch);
1582         cpdma_ctlr_int_ctrl(priv->dma, true);
1583         cpsw_intr_enable(priv);
1584 }
1585
1586 static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
1587 {
1588         struct cpsw_priv *priv = netdev_priv(ndev);
1589         struct sockaddr *addr = (struct sockaddr *)p;
1590         int flags = 0;
1591         u16 vid = 0;
1592
1593         if (!is_valid_ether_addr(addr->sa_data))
1594                 return -EADDRNOTAVAIL;
1595
1596         if (priv->data.dual_emac) {
1597                 vid = priv->slaves[priv->emac_port].port_vlan;
1598                 flags = ALE_VLAN;
1599         }
1600
1601         cpsw_ale_del_ucast(priv->ale, priv->mac_addr, priv->host_port,
1602                            flags, vid);
1603         cpsw_ale_add_ucast(priv->ale, addr->sa_data, priv->host_port,
1604                            flags, vid);
1605
1606         memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN);
1607         memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
1608         for_each_slave(priv, cpsw_set_slave_mac, priv);
1609
1610         return 0;
1611 }
1612
1613 #ifdef CONFIG_NET_POLL_CONTROLLER
1614 static void cpsw_ndo_poll_controller(struct net_device *ndev)
1615 {
1616         struct cpsw_priv *priv = netdev_priv(ndev);
1617
1618         cpsw_intr_disable(priv);
1619         cpdma_ctlr_int_ctrl(priv->dma, false);
1620         cpsw_interrupt(ndev->irq, priv);
1621         cpdma_ctlr_int_ctrl(priv->dma, true);
1622         cpsw_intr_enable(priv);
1623 }
1624 #endif
1625
1626 static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
1627                                 unsigned short vid)
1628 {
1629         int ret;
1630         int unreg_mcast_mask;
1631
1632         if (priv->ndev->flags & IFF_ALLMULTI)
1633                 unreg_mcast_mask = ALE_ALL_PORTS;
1634         else
1635                 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1636
1637         ret = cpsw_ale_add_vlan(priv->ale, vid,
1638                                 ALE_ALL_PORTS << priv->host_port,
1639                                 0, ALE_ALL_PORTS << priv->host_port,
1640                                 unreg_mcast_mask << priv->host_port);
1641         if (ret != 0)
1642                 return ret;
1643
1644         ret = cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
1645                                  priv->host_port, ALE_VLAN, vid);
1646         if (ret != 0)
1647                 goto clean_vid;
1648
1649         ret = cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1650                                  ALE_ALL_PORTS << priv->host_port,
1651                                  ALE_VLAN, vid, 0);
1652         if (ret != 0)
1653                 goto clean_vlan_ucast;
1654         return 0;
1655
1656 clean_vlan_ucast:
1657         cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1658                             priv->host_port, ALE_VLAN, vid);
1659 clean_vid:
1660         cpsw_ale_del_vlan(priv->ale, vid, 0);
1661         return ret;
1662 }
1663
1664 static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
1665                                     __be16 proto, u16 vid)
1666 {
1667         struct cpsw_priv *priv = netdev_priv(ndev);
1668
1669         if (vid == priv->data.default_vlan)
1670                 return 0;
1671
1672         dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
1673         return cpsw_add_vlan_ale_entry(priv, vid);
1674 }
1675
1676 static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
1677                                      __be16 proto, u16 vid)
1678 {
1679         struct cpsw_priv *priv = netdev_priv(ndev);
1680         int ret;
1681
1682         if (vid == priv->data.default_vlan)
1683                 return 0;
1684
1685         dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
1686         ret = cpsw_ale_del_vlan(priv->ale, vid, 0);
1687         if (ret != 0)
1688                 return ret;
1689
1690         ret = cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1691                                  priv->host_port, ALE_VLAN, vid);
1692         if (ret != 0)
1693                 return ret;
1694
1695         return cpsw_ale_del_mcast(priv->ale, priv->ndev->broadcast,
1696                                   0, ALE_VLAN, vid);
1697 }
1698
1699 static const struct net_device_ops cpsw_netdev_ops = {
1700         .ndo_open               = cpsw_ndo_open,
1701         .ndo_stop               = cpsw_ndo_stop,
1702         .ndo_start_xmit         = cpsw_ndo_start_xmit,
1703         .ndo_set_mac_address    = cpsw_ndo_set_mac_address,
1704         .ndo_do_ioctl           = cpsw_ndo_ioctl,
1705         .ndo_validate_addr      = eth_validate_addr,
1706         .ndo_change_mtu         = eth_change_mtu,
1707         .ndo_tx_timeout         = cpsw_ndo_tx_timeout,
1708         .ndo_set_rx_mode        = cpsw_ndo_set_rx_mode,
1709 #ifdef CONFIG_NET_POLL_CONTROLLER
1710         .ndo_poll_controller    = cpsw_ndo_poll_controller,
1711 #endif
1712         .ndo_vlan_rx_add_vid    = cpsw_ndo_vlan_rx_add_vid,
1713         .ndo_vlan_rx_kill_vid   = cpsw_ndo_vlan_rx_kill_vid,
1714 };
1715
1716 static int cpsw_get_regs_len(struct net_device *ndev)
1717 {
1718         struct cpsw_priv *priv = netdev_priv(ndev);
1719
1720         return priv->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32);
1721 }
1722
1723 static void cpsw_get_regs(struct net_device *ndev,
1724                           struct ethtool_regs *regs, void *p)
1725 {
1726         struct cpsw_priv *priv = netdev_priv(ndev);
1727         u32 *reg = p;
1728
1729         /* update CPSW IP version */
1730         regs->version = priv->version;
1731
1732         cpsw_ale_dump(priv->ale, reg);
1733 }
1734
1735 static void cpsw_get_drvinfo(struct net_device *ndev,
1736                              struct ethtool_drvinfo *info)
1737 {
1738         struct cpsw_priv *priv = netdev_priv(ndev);
1739
1740         strlcpy(info->driver, "cpsw", sizeof(info->driver));
1741         strlcpy(info->version, "1.0", sizeof(info->version));
1742         strlcpy(info->bus_info, priv->pdev->name, sizeof(info->bus_info));
1743         info->regdump_len = cpsw_get_regs_len(ndev);
1744 }
1745
1746 static u32 cpsw_get_msglevel(struct net_device *ndev)
1747 {
1748         struct cpsw_priv *priv = netdev_priv(ndev);
1749         return priv->msg_enable;
1750 }
1751
1752 static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
1753 {
1754         struct cpsw_priv *priv = netdev_priv(ndev);
1755         priv->msg_enable = value;
1756 }
1757
1758 static int cpsw_get_ts_info(struct net_device *ndev,
1759                             struct ethtool_ts_info *info)
1760 {
1761 #ifdef CONFIG_TI_CPTS
1762         struct cpsw_priv *priv = netdev_priv(ndev);
1763
1764         info->so_timestamping =
1765                 SOF_TIMESTAMPING_TX_HARDWARE |
1766                 SOF_TIMESTAMPING_TX_SOFTWARE |
1767                 SOF_TIMESTAMPING_RX_HARDWARE |
1768                 SOF_TIMESTAMPING_RX_SOFTWARE |
1769                 SOF_TIMESTAMPING_SOFTWARE |
1770                 SOF_TIMESTAMPING_RAW_HARDWARE;
1771         info->phc_index = priv->cpts->phc_index;
1772         info->tx_types =
1773                 (1 << HWTSTAMP_TX_OFF) |
1774                 (1 << HWTSTAMP_TX_ON);
1775         info->rx_filters =
1776                 (1 << HWTSTAMP_FILTER_NONE) |
1777                 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
1778 #else
1779         info->so_timestamping =
1780                 SOF_TIMESTAMPING_TX_SOFTWARE |
1781                 SOF_TIMESTAMPING_RX_SOFTWARE |
1782                 SOF_TIMESTAMPING_SOFTWARE;
1783         info->phc_index = -1;
1784         info->tx_types = 0;
1785         info->rx_filters = 0;
1786 #endif
1787         return 0;
1788 }
1789
1790 static int cpsw_get_settings(struct net_device *ndev,
1791                              struct ethtool_cmd *ecmd)
1792 {
1793         struct cpsw_priv *priv = netdev_priv(ndev);
1794         int slave_no = cpsw_slave_index(priv);
1795
1796         if (priv->slaves[slave_no].phy)
1797                 return phy_ethtool_gset(priv->slaves[slave_no].phy, ecmd);
1798         else
1799                 return -EOPNOTSUPP;
1800 }
1801
1802 static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1803 {
1804         struct cpsw_priv *priv = netdev_priv(ndev);
1805         int slave_no = cpsw_slave_index(priv);
1806
1807         if (priv->slaves[slave_no].phy)
1808                 return phy_ethtool_sset(priv->slaves[slave_no].phy, ecmd);
1809         else
1810                 return -EOPNOTSUPP;
1811 }
1812
1813 static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1814 {
1815         struct cpsw_priv *priv = netdev_priv(ndev);
1816         int slave_no = cpsw_slave_index(priv);
1817
1818         wol->supported = 0;
1819         wol->wolopts = 0;
1820
1821         if (priv->slaves[slave_no].phy)
1822                 phy_ethtool_get_wol(priv->slaves[slave_no].phy, wol);
1823 }
1824
1825 static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1826 {
1827         struct cpsw_priv *priv = netdev_priv(ndev);
1828         int slave_no = cpsw_slave_index(priv);
1829
1830         if (priv->slaves[slave_no].phy)
1831                 return phy_ethtool_set_wol(priv->slaves[slave_no].phy, wol);
1832         else
1833                 return -EOPNOTSUPP;
1834 }
1835
1836 static void cpsw_get_pauseparam(struct net_device *ndev,
1837                                 struct ethtool_pauseparam *pause)
1838 {
1839         struct cpsw_priv *priv = netdev_priv(ndev);
1840
1841         pause->autoneg = AUTONEG_DISABLE;
1842         pause->rx_pause = priv->rx_pause ? true : false;
1843         pause->tx_pause = priv->tx_pause ? true : false;
1844 }
1845
1846 static int cpsw_set_pauseparam(struct net_device *ndev,
1847                                struct ethtool_pauseparam *pause)
1848 {
1849         struct cpsw_priv *priv = netdev_priv(ndev);
1850         bool link;
1851
1852         priv->rx_pause = pause->rx_pause ? true : false;
1853         priv->tx_pause = pause->tx_pause ? true : false;
1854
1855         for_each_slave(priv, _cpsw_adjust_link, priv, &link);
1856
1857         return 0;
1858 }
1859
1860 static const struct ethtool_ops cpsw_ethtool_ops = {
1861         .get_drvinfo    = cpsw_get_drvinfo,
1862         .get_msglevel   = cpsw_get_msglevel,
1863         .set_msglevel   = cpsw_set_msglevel,
1864         .get_link       = ethtool_op_get_link,
1865         .get_ts_info    = cpsw_get_ts_info,
1866         .get_settings   = cpsw_get_settings,
1867         .set_settings   = cpsw_set_settings,
1868         .get_coalesce   = cpsw_get_coalesce,
1869         .set_coalesce   = cpsw_set_coalesce,
1870         .get_sset_count         = cpsw_get_sset_count,
1871         .get_strings            = cpsw_get_strings,
1872         .get_ethtool_stats      = cpsw_get_ethtool_stats,
1873         .get_pauseparam         = cpsw_get_pauseparam,
1874         .set_pauseparam         = cpsw_set_pauseparam,
1875         .get_wol        = cpsw_get_wol,
1876         .set_wol        = cpsw_set_wol,
1877         .get_regs_len   = cpsw_get_regs_len,
1878         .get_regs       = cpsw_get_regs,
1879 };
1880
1881 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv,
1882                             u32 slave_reg_ofs, u32 sliver_reg_ofs)
1883 {
1884         void __iomem            *regs = priv->regs;
1885         int                     slave_num = slave->slave_num;
1886         struct cpsw_slave_data  *data = priv->data.slave_data + slave_num;
1887
1888         slave->data     = data;
1889         slave->regs     = regs + slave_reg_ofs;
1890         slave->sliver   = regs + sliver_reg_ofs;
1891         slave->port_vlan = data->dual_emac_res_vlan;
1892 }
1893
1894 #define AM33XX_CTRL_MAC_LO_REG(id) (0x630 + 0x8 * id)
1895 #define AM33XX_CTRL_MAC_HI_REG(id) (0x630 + 0x8 * id + 0x4)
1896
1897 static int cpsw_am33xx_cm_get_macid(struct device *dev, int slave,
1898                 u8 *mac_addr)
1899 {
1900         u32 macid_lo;
1901         u32 macid_hi;
1902         struct regmap *syscon;
1903
1904         syscon = syscon_regmap_lookup_by_phandle(dev->of_node, "syscon");
1905         if (IS_ERR(syscon)) {
1906                 if (PTR_ERR(syscon) == -ENODEV)
1907                         return 0;
1908                 return PTR_ERR(syscon);
1909         }
1910
1911         regmap_read(syscon, AM33XX_CTRL_MAC_LO_REG(slave), &macid_lo);
1912         regmap_read(syscon, AM33XX_CTRL_MAC_HI_REG(slave), &macid_hi);
1913
1914         mac_addr[5] = (macid_lo >> 8) & 0xff;
1915         mac_addr[4] = macid_lo & 0xff;
1916         mac_addr[3] = (macid_hi >> 24) & 0xff;
1917         mac_addr[2] = (macid_hi >> 16) & 0xff;
1918         mac_addr[1] = (macid_hi >> 8) & 0xff;
1919         mac_addr[0] = macid_hi & 0xff;
1920
1921         return 0;
1922 }
1923
1924 static int cpsw_probe_dt(struct cpsw_platform_data *data,
1925                          struct platform_device *pdev)
1926 {
1927         struct device_node *node = pdev->dev.of_node;
1928         struct device_node *slave_node;
1929         int i = 0, ret;
1930         u32 prop;
1931
1932         if (!node)
1933                 return -EINVAL;
1934
1935         if (of_property_read_u32(node, "slaves", &prop)) {
1936                 dev_err(&pdev->dev, "Missing slaves property in the DT.\n");
1937                 return -EINVAL;
1938         }
1939         data->slaves = prop;
1940
1941         if (of_property_read_u32(node, "active_slave", &prop)) {
1942                 dev_err(&pdev->dev, "Missing active_slave property in the DT.\n");
1943                 return -EINVAL;
1944         }
1945         data->active_slave = prop;
1946
1947         if (of_property_read_u32(node, "cpts_clock_mult", &prop)) {
1948                 dev_err(&pdev->dev, "Missing cpts_clock_mult property in the DT.\n");
1949                 return -EINVAL;
1950         }
1951         data->cpts_clock_mult = prop;
1952
1953         if (of_property_read_u32(node, "cpts_clock_shift", &prop)) {
1954                 dev_err(&pdev->dev, "Missing cpts_clock_shift property in the DT.\n");
1955                 return -EINVAL;
1956         }
1957         data->cpts_clock_shift = prop;
1958
1959         data->slave_data = devm_kzalloc(&pdev->dev, data->slaves
1960                                         * sizeof(struct cpsw_slave_data),
1961                                         GFP_KERNEL);
1962         if (!data->slave_data)
1963                 return -ENOMEM;
1964
1965         if (of_property_read_u32(node, "cpdma_channels", &prop)) {
1966                 dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n");
1967                 return -EINVAL;
1968         }
1969         data->channels = prop;
1970
1971         if (of_property_read_u32(node, "ale_entries", &prop)) {
1972                 dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n");
1973                 return -EINVAL;
1974         }
1975         data->ale_entries = prop;
1976
1977         if (of_property_read_u32(node, "bd_ram_size", &prop)) {
1978                 dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n");
1979                 return -EINVAL;
1980         }
1981         data->bd_ram_size = prop;
1982
1983         if (of_property_read_u32(node, "rx_descs", &prop)) {
1984                 dev_err(&pdev->dev, "Missing rx_descs property in the DT.\n");
1985                 return -EINVAL;
1986         }
1987         data->rx_descs = prop;
1988
1989         if (of_property_read_u32(node, "mac_control", &prop)) {
1990                 dev_err(&pdev->dev, "Missing mac_control property in the DT.\n");
1991                 return -EINVAL;
1992         }
1993         data->mac_control = prop;
1994
1995         if (of_property_read_bool(node, "dual_emac"))
1996                 data->dual_emac = 1;
1997
1998         /*
1999          * Populate all the child nodes here...
2000          */
2001         ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
2002         /* We do not want to force this, as in some cases may not have child */
2003         if (ret)
2004                 dev_warn(&pdev->dev, "Doesn't have any child node\n");
2005
2006         for_each_child_of_node(node, slave_node) {
2007                 struct cpsw_slave_data *slave_data = data->slave_data + i;
2008                 const void *mac_addr = NULL;
2009                 u32 phyid;
2010                 int lenp;
2011                 const __be32 *parp;
2012                 struct device_node *mdio_node;
2013                 struct platform_device *mdio;
2014
2015                 /* This is no slave child node, continue */
2016                 if (strcmp(slave_node->name, "slave"))
2017                         continue;
2018
2019                 parp = of_get_property(slave_node, "phy_id", &lenp);
2020                 if ((parp == NULL) || (lenp != (sizeof(void *) * 2))) {
2021                         dev_err(&pdev->dev, "Missing slave[%d] phy_id property\n", i);
2022                         goto no_phy_slave;
2023                 }
2024                 mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
2025                 phyid = be32_to_cpup(parp+1);
2026                 mdio = of_find_device_by_node(mdio_node);
2027                 of_node_put(mdio_node);
2028                 if (!mdio) {
2029                         dev_err(&pdev->dev, "Missing mdio platform device\n");
2030                         return -EINVAL;
2031                 }
2032                 snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
2033                          PHY_ID_FMT, mdio->name, phyid);
2034
2035                 slave_data->phy_if = of_get_phy_mode(slave_node);
2036                 if (slave_data->phy_if < 0) {
2037                         dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n",
2038                                 i);
2039                         return slave_data->phy_if;
2040                 }
2041
2042 no_phy_slave:
2043                 mac_addr = of_get_mac_address(slave_node);
2044                 if (mac_addr) {
2045                         memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
2046                 } else {
2047                         if (of_machine_is_compatible("ti,am33xx")) {
2048                                 ret = cpsw_am33xx_cm_get_macid(&pdev->dev, i,
2049                                                         slave_data->mac_addr);
2050                                 if (ret)
2051                                         return ret;
2052                         }
2053                 }
2054                 if (data->dual_emac) {
2055                         if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
2056                                                  &prop)) {
2057                                 dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n");
2058                                 slave_data->dual_emac_res_vlan = i+1;
2059                                 dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n",
2060                                         slave_data->dual_emac_res_vlan, i);
2061                         } else {
2062                                 slave_data->dual_emac_res_vlan = prop;
2063                         }
2064                 }
2065
2066                 i++;
2067                 if (i == data->slaves)
2068                         break;
2069         }
2070
2071         return 0;
2072 }
2073
2074 static int cpsw_probe_dual_emac(struct platform_device *pdev,
2075                                 struct cpsw_priv *priv)
2076 {
2077         struct cpsw_platform_data       *data = &priv->data;
2078         struct net_device               *ndev;
2079         struct cpsw_priv                *priv_sl2;
2080         int ret = 0, i;
2081
2082         ndev = alloc_etherdev(sizeof(struct cpsw_priv));
2083         if (!ndev) {
2084                 dev_err(&pdev->dev, "cpsw: error allocating net_device\n");
2085                 return -ENOMEM;
2086         }
2087
2088         priv_sl2 = netdev_priv(ndev);
2089         spin_lock_init(&priv_sl2->lock);
2090         priv_sl2->data = *data;
2091         priv_sl2->pdev = pdev;
2092         priv_sl2->ndev = ndev;
2093         priv_sl2->dev  = &ndev->dev;
2094         priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2095         priv_sl2->rx_packet_max = max(rx_packet_max, 128);
2096
2097         if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
2098                 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
2099                         ETH_ALEN);
2100                 dev_info(&pdev->dev, "cpsw: Detected MACID = %pM\n", priv_sl2->mac_addr);
2101         } else {
2102                 random_ether_addr(priv_sl2->mac_addr);
2103                 dev_info(&pdev->dev, "cpsw: Random MACID = %pM\n", priv_sl2->mac_addr);
2104         }
2105         memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
2106
2107         priv_sl2->slaves = priv->slaves;
2108         priv_sl2->clk = priv->clk;
2109
2110         priv_sl2->coal_intvl = 0;
2111         priv_sl2->bus_freq_mhz = priv->bus_freq_mhz;
2112
2113         priv_sl2->regs = priv->regs;
2114         priv_sl2->host_port = priv->host_port;
2115         priv_sl2->host_port_regs = priv->host_port_regs;
2116         priv_sl2->wr_regs = priv->wr_regs;
2117         priv_sl2->hw_stats = priv->hw_stats;
2118         priv_sl2->dma = priv->dma;
2119         priv_sl2->txch = priv->txch;
2120         priv_sl2->rxch = priv->rxch;
2121         priv_sl2->ale = priv->ale;
2122         priv_sl2->emac_port = 1;
2123         priv->slaves[1].ndev = ndev;
2124         priv_sl2->cpts = priv->cpts;
2125         priv_sl2->version = priv->version;
2126
2127         for (i = 0; i < priv->num_irqs; i++) {
2128                 priv_sl2->irqs_table[i] = priv->irqs_table[i];
2129                 priv_sl2->num_irqs = priv->num_irqs;
2130         }
2131         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2132
2133         ndev->netdev_ops = &cpsw_netdev_ops;
2134         ndev->ethtool_ops = &cpsw_ethtool_ops;
2135         netif_napi_add(ndev, &priv_sl2->napi, cpsw_poll, CPSW_POLL_WEIGHT);
2136
2137         /* register the network device */
2138         SET_NETDEV_DEV(ndev, &pdev->dev);
2139         ret = register_netdev(ndev);
2140         if (ret) {
2141                 dev_err(&pdev->dev, "cpsw: error registering net device\n");
2142                 free_netdev(ndev);
2143                 ret = -ENODEV;
2144         }
2145
2146         return ret;
2147 }
2148
2149 static int cpsw_probe(struct platform_device *pdev)
2150 {
2151         struct cpsw_platform_data       *data;
2152         struct net_device               *ndev;
2153         struct cpsw_priv                *priv;
2154         struct cpdma_params             dma_params;
2155         struct cpsw_ale_params          ale_params;
2156         void __iomem                    *ss_regs;
2157         struct resource                 *res, *ss_res;
2158         u32 slave_offset, sliver_offset, slave_size;
2159         int ret = 0, i, k = 0;
2160
2161         ndev = alloc_etherdev(sizeof(struct cpsw_priv));
2162         if (!ndev) {
2163                 dev_err(&pdev->dev, "error allocating net_device\n");
2164                 return -ENOMEM;
2165         }
2166
2167         platform_set_drvdata(pdev, ndev);
2168         priv = netdev_priv(ndev);
2169         spin_lock_init(&priv->lock);
2170         priv->pdev = pdev;
2171         priv->ndev = ndev;
2172         priv->dev  = &ndev->dev;
2173         priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2174         priv->rx_packet_max = max(rx_packet_max, 128);
2175         priv->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL);
2176         priv->irq_enabled = true;
2177         if (!priv->cpts) {
2178                 dev_err(&pdev->dev, "error allocating cpts\n");
2179                 ret = -ENOMEM;
2180                 goto clean_ndev_ret;
2181         }
2182
2183         /*
2184          * This may be required here for child devices.
2185          */
2186         pm_runtime_enable(&pdev->dev);
2187
2188         /* Select default pin state */
2189         pinctrl_pm_select_default_state(&pdev->dev);
2190
2191         if (cpsw_probe_dt(&priv->data, pdev)) {
2192                 dev_err(&pdev->dev, "cpsw: platform data missing\n");
2193                 ret = -ENODEV;
2194                 goto clean_runtime_disable_ret;
2195         }
2196         data = &priv->data;
2197
2198         if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
2199                 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
2200                 dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr);
2201         } else {
2202                 eth_random_addr(priv->mac_addr);
2203                 dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr);
2204         }
2205
2206         memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
2207
2208         priv->slaves = devm_kzalloc(&pdev->dev,
2209                                     sizeof(struct cpsw_slave) * data->slaves,
2210                                     GFP_KERNEL);
2211         if (!priv->slaves) {
2212                 ret = -ENOMEM;
2213                 goto clean_runtime_disable_ret;
2214         }
2215         for (i = 0; i < data->slaves; i++)
2216                 priv->slaves[i].slave_num = i;
2217
2218         priv->slaves[0].ndev = ndev;
2219         priv->emac_port = 0;
2220
2221         priv->clk = devm_clk_get(&pdev->dev, "fck");
2222         if (IS_ERR(priv->clk)) {
2223                 dev_err(priv->dev, "fck is not found\n");
2224                 ret = -ENODEV;
2225                 goto clean_runtime_disable_ret;
2226         }
2227         priv->coal_intvl = 0;
2228         priv->bus_freq_mhz = clk_get_rate(priv->clk) / 1000000;
2229
2230         ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2231         ss_regs = devm_ioremap_resource(&pdev->dev, ss_res);
2232         if (IS_ERR(ss_regs)) {
2233                 ret = PTR_ERR(ss_regs);
2234                 goto clean_runtime_disable_ret;
2235         }
2236         priv->regs = ss_regs;
2237         priv->host_port = HOST_PORT_NUM;
2238
2239         /* Need to enable clocks with runtime PM api to access module
2240          * registers
2241          */
2242         pm_runtime_get_sync(&pdev->dev);
2243         priv->version = readl(&priv->regs->id_ver);
2244         pm_runtime_put_sync(&pdev->dev);
2245
2246         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2247         priv->wr_regs = devm_ioremap_resource(&pdev->dev, res);
2248         if (IS_ERR(priv->wr_regs)) {
2249                 ret = PTR_ERR(priv->wr_regs);
2250                 goto clean_runtime_disable_ret;
2251         }
2252
2253         memset(&dma_params, 0, sizeof(dma_params));
2254         memset(&ale_params, 0, sizeof(ale_params));
2255
2256         switch (priv->version) {
2257         case CPSW_VERSION_1:
2258                 priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
2259                 priv->cpts->reg      = ss_regs + CPSW1_CPTS_OFFSET;
2260                 priv->hw_stats       = ss_regs + CPSW1_HW_STATS;
2261                 dma_params.dmaregs   = ss_regs + CPSW1_CPDMA_OFFSET;
2262                 dma_params.txhdp     = ss_regs + CPSW1_STATERAM_OFFSET;
2263                 ale_params.ale_regs  = ss_regs + CPSW1_ALE_OFFSET;
2264                 slave_offset         = CPSW1_SLAVE_OFFSET;
2265                 slave_size           = CPSW1_SLAVE_SIZE;
2266                 sliver_offset        = CPSW1_SLIVER_OFFSET;
2267                 dma_params.desc_mem_phys = 0;
2268                 break;
2269         case CPSW_VERSION_2:
2270         case CPSW_VERSION_3:
2271         case CPSW_VERSION_4:
2272                 priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
2273                 priv->cpts->reg      = ss_regs + CPSW2_CPTS_OFFSET;
2274                 priv->hw_stats       = ss_regs + CPSW2_HW_STATS;
2275                 dma_params.dmaregs   = ss_regs + CPSW2_CPDMA_OFFSET;
2276                 dma_params.txhdp     = ss_regs + CPSW2_STATERAM_OFFSET;
2277                 ale_params.ale_regs  = ss_regs + CPSW2_ALE_OFFSET;
2278                 slave_offset         = CPSW2_SLAVE_OFFSET;
2279                 slave_size           = CPSW2_SLAVE_SIZE;
2280                 sliver_offset        = CPSW2_SLIVER_OFFSET;
2281                 dma_params.desc_mem_phys =
2282                         (u32 __force) ss_res->start + CPSW2_BD_OFFSET;
2283                 break;
2284         default:
2285                 dev_err(priv->dev, "unknown version 0x%08x\n", priv->version);
2286                 ret = -ENODEV;
2287                 goto clean_runtime_disable_ret;
2288         }
2289         for (i = 0; i < priv->data.slaves; i++) {
2290                 struct cpsw_slave *slave = &priv->slaves[i];
2291                 cpsw_slave_init(slave, priv, slave_offset, sliver_offset);
2292                 slave_offset  += slave_size;
2293                 sliver_offset += SLIVER_SIZE;
2294         }
2295
2296         dma_params.dev          = &pdev->dev;
2297         dma_params.rxthresh     = dma_params.dmaregs + CPDMA_RXTHRESH;
2298         dma_params.rxfree       = dma_params.dmaregs + CPDMA_RXFREE;
2299         dma_params.rxhdp        = dma_params.txhdp + CPDMA_RXHDP;
2300         dma_params.txcp         = dma_params.txhdp + CPDMA_TXCP;
2301         dma_params.rxcp         = dma_params.txhdp + CPDMA_RXCP;
2302
2303         dma_params.num_chan             = data->channels;
2304         dma_params.has_soft_reset       = true;
2305         dma_params.min_packet_size      = CPSW_MIN_PACKET_SIZE;
2306         dma_params.desc_mem_size        = data->bd_ram_size;
2307         dma_params.desc_align           = 16;
2308         dma_params.has_ext_regs         = true;
2309         dma_params.desc_hw_addr         = dma_params.desc_mem_phys;
2310
2311         priv->dma = cpdma_ctlr_create(&dma_params);
2312         if (!priv->dma) {
2313                 dev_err(priv->dev, "error initializing dma\n");
2314                 ret = -ENOMEM;
2315                 goto clean_runtime_disable_ret;
2316         }
2317
2318         priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0),
2319                                        cpsw_tx_handler);
2320         priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0),
2321                                        cpsw_rx_handler);
2322
2323         if (WARN_ON(!priv->txch || !priv->rxch)) {
2324                 dev_err(priv->dev, "error initializing dma channels\n");
2325                 ret = -ENOMEM;
2326                 goto clean_dma_ret;
2327         }
2328
2329         ale_params.dev                  = &ndev->dev;
2330         ale_params.ale_ageout           = ale_ageout;
2331         ale_params.ale_entries          = data->ale_entries;
2332         ale_params.ale_ports            = data->slaves;
2333
2334         priv->ale = cpsw_ale_create(&ale_params);
2335         if (!priv->ale) {
2336                 dev_err(priv->dev, "error initializing ale engine\n");
2337                 ret = -ENODEV;
2338                 goto clean_dma_ret;
2339         }
2340
2341         ndev->irq = platform_get_irq(pdev, 0);
2342         if (ndev->irq < 0) {
2343                 dev_err(priv->dev, "error getting irq resource\n");
2344                 ret = -ENOENT;
2345                 goto clean_ale_ret;
2346         }
2347
2348         while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) {
2349                 if (k >= ARRAY_SIZE(priv->irqs_table)) {
2350                         ret = -EINVAL;
2351                         goto clean_ale_ret;
2352                 }
2353
2354                 ret = devm_request_irq(&pdev->dev, res->start, cpsw_interrupt,
2355                                        0, dev_name(&pdev->dev), priv);
2356                 if (ret < 0) {
2357                         dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2358                         goto clean_ale_ret;
2359                 }
2360
2361                 priv->irqs_table[k] = res->start;
2362                 k++;
2363         }
2364
2365         priv->num_irqs = k;
2366
2367         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2368
2369         ndev->netdev_ops = &cpsw_netdev_ops;
2370         ndev->ethtool_ops = &cpsw_ethtool_ops;
2371         netif_napi_add(ndev, &priv->napi, cpsw_poll, CPSW_POLL_WEIGHT);
2372
2373         /* register the network device */
2374         SET_NETDEV_DEV(ndev, &pdev->dev);
2375         ret = register_netdev(ndev);
2376         if (ret) {
2377                 dev_err(priv->dev, "error registering net device\n");
2378                 ret = -ENODEV;
2379                 goto clean_ale_ret;
2380         }
2381
2382         cpsw_notice(priv, probe, "initialized device (regs %pa, irq %d)\n",
2383                     &ss_res->start, ndev->irq);
2384
2385         if (priv->data.dual_emac) {
2386                 ret = cpsw_probe_dual_emac(pdev, priv);
2387                 if (ret) {
2388                         cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
2389                         goto clean_ale_ret;
2390                 }
2391         }
2392
2393         return 0;
2394
2395 clean_ale_ret:
2396         cpsw_ale_destroy(priv->ale);
2397 clean_dma_ret:
2398         cpdma_chan_destroy(priv->txch);
2399         cpdma_chan_destroy(priv->rxch);
2400         cpdma_ctlr_destroy(priv->dma);
2401 clean_runtime_disable_ret:
2402         pm_runtime_disable(&pdev->dev);
2403 clean_ndev_ret:
2404         free_netdev(priv->ndev);
2405         return ret;
2406 }
2407
2408 static int cpsw_remove_child_device(struct device *dev, void *c)
2409 {
2410         struct platform_device *pdev = to_platform_device(dev);
2411
2412         of_device_unregister(pdev);
2413
2414         return 0;
2415 }
2416
2417 static int cpsw_remove(struct platform_device *pdev)
2418 {
2419         struct net_device *ndev = platform_get_drvdata(pdev);
2420         struct cpsw_priv *priv = netdev_priv(ndev);
2421
2422         if (priv->data.dual_emac)
2423                 unregister_netdev(cpsw_get_slave_ndev(priv, 1));
2424         unregister_netdev(ndev);
2425
2426         cpsw_ale_destroy(priv->ale);
2427         cpdma_chan_destroy(priv->txch);
2428         cpdma_chan_destroy(priv->rxch);
2429         cpdma_ctlr_destroy(priv->dma);
2430         pm_runtime_disable(&pdev->dev);
2431         device_for_each_child(&pdev->dev, NULL, cpsw_remove_child_device);
2432         if (priv->data.dual_emac)
2433                 free_netdev(cpsw_get_slave_ndev(priv, 1));
2434         free_netdev(ndev);
2435         return 0;
2436 }
2437
2438 static int cpsw_suspend(struct device *dev)
2439 {
2440         struct platform_device  *pdev = to_platform_device(dev);
2441         struct net_device       *ndev = platform_get_drvdata(pdev);
2442         struct cpsw_priv        *priv = netdev_priv(ndev);
2443
2444         if (priv->data.dual_emac) {
2445                 int i;
2446
2447                 for (i = 0; i < priv->data.slaves; i++) {
2448                         if (netif_running(priv->slaves[i].ndev))
2449                                 cpsw_ndo_stop(priv->slaves[i].ndev);
2450                         soft_reset_slave(priv->slaves + i);
2451                 }
2452         } else {
2453                 if (netif_running(ndev))
2454                         cpsw_ndo_stop(ndev);
2455                 for_each_slave(priv, soft_reset_slave);
2456         }
2457
2458         pm_runtime_put_sync(&pdev->dev);
2459
2460         /* Select sleep pin state */
2461         pinctrl_pm_select_sleep_state(&pdev->dev);
2462
2463         return 0;
2464 }
2465
2466 static int cpsw_resume(struct device *dev)
2467 {
2468         struct platform_device  *pdev = to_platform_device(dev);
2469         struct net_device       *ndev = platform_get_drvdata(pdev);
2470         struct cpsw_priv        *priv = netdev_priv(ndev);
2471
2472         pm_runtime_get_sync(&pdev->dev);
2473
2474         /* Select default pin state */
2475         pinctrl_pm_select_default_state(&pdev->dev);
2476
2477         if (priv->data.dual_emac) {
2478                 int i;
2479
2480                 for (i = 0; i < priv->data.slaves; i++) {
2481                         if (netif_running(priv->slaves[i].ndev))
2482                                 cpsw_ndo_open(priv->slaves[i].ndev);
2483                 }
2484         } else {
2485                 if (netif_running(ndev))
2486                         cpsw_ndo_open(ndev);
2487         }
2488         return 0;
2489 }
2490
2491 static const struct dev_pm_ops cpsw_pm_ops = {
2492         .suspend        = cpsw_suspend,
2493         .resume         = cpsw_resume,
2494 };
2495
2496 static const struct of_device_id cpsw_of_mtable[] = {
2497         { .compatible = "ti,cpsw", },
2498         { /* sentinel */ },
2499 };
2500 MODULE_DEVICE_TABLE(of, cpsw_of_mtable);
2501
2502 static struct platform_driver cpsw_driver = {
2503         .driver = {
2504                 .name    = "cpsw",
2505                 .pm      = &cpsw_pm_ops,
2506                 .of_match_table = cpsw_of_mtable,
2507         },
2508         .probe = cpsw_probe,
2509         .remove = cpsw_remove,
2510 };
2511
2512 static int __init cpsw_init(void)
2513 {
2514         return platform_driver_register(&cpsw_driver);
2515 }
2516 late_initcall(cpsw_init);
2517
2518 static void __exit cpsw_exit(void)
2519 {
2520         platform_driver_unregister(&cpsw_driver);
2521 }
2522 module_exit(cpsw_exit);
2523
2524 MODULE_LICENSE("GPL");
2525 MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
2526 MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
2527 MODULE_DESCRIPTION("TI CPSW Ethernet driver");