drivers/net/ethernet/ti/cpmac.c

   1 /*
   2  * Copyright (C) 2006, 2007 Eugene Konev
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  17  */
  18
  19 #include <linux/module.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/moduleparam.h>
  22
  23 #include <linux/sched.h>
  24 #include <linux/kernel.h>
  25 #include <linux/slab.h>
  26 #include <linux/errno.h>
  27 #include <linux/types.h>
  28 #include <linux/delay.h>
  29
  30 #include <linux/netdevice.h>
  31 #include <linux/if_vlan.h>
  32 #include <linux/etherdevice.h>
  33 #include <linux/ethtool.h>
  34 #include <linux/skbuff.h>
  35 #include <linux/mii.h>
  36 #include <linux/phy.h>
  37 #include <linux/phy_fixed.h>
  38 #include <linux/platform_device.h>
  39 #include <linux/dma-mapping.h>
  40 #include <linux/clk.h>
  41 #include <linux/gpio.h>
  42 #include <linux/atomic.h>
  43
  44 MODULE_AUTHOR("Eugene Konev <ejka@imfi.kspu.ru>");
  45 MODULE_DESCRIPTION("TI AR7 ethernet driver (CPMAC)");
  46 MODULE_LICENSE("GPL");
  47 MODULE_ALIAS("platform:cpmac");
  48
  49 static int debug_level = 8;
  50 static int dumb_switch;
  51
  52 /* Next 2 are only used in cpmac_probe, so it's pointless to change them */
  53 module_param(debug_level, int, 0444);
  54 module_param(dumb_switch, int, 0444);
  55
  56 MODULE_PARM_DESC(debug_level, "Number of NETIF_MSG bits to enable");
  57 MODULE_PARM_DESC(dumb_switch, "Assume switch is not connected to MDIO bus");
  58
  59 #define CPMAC_VERSION "0.5.2"
  60 /* frame size + 802.1q tag + FCS size */
  61 #define CPMAC_SKB_SIZE          (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
  62 #define CPMAC_QUEUES    8
  63
  64 /* Ethernet registers */
  65 #define CPMAC_TX_CONTROL                0x0004
  66 #define CPMAC_TX_TEARDOWN               0x0008
  67 #define CPMAC_RX_CONTROL                0x0014
  68 #define CPMAC_RX_TEARDOWN               0x0018
  69 #define CPMAC_MBP                       0x0100
  70 #define MBP_RXPASSCRC                   0x40000000
  71 #define MBP_RXQOS                       0x20000000
  72 #define MBP_RXNOCHAIN                   0x10000000
  73 #define MBP_RXCMF                       0x01000000
  74 #define MBP_RXSHORT                     0x00800000
  75 #define MBP_RXCEF                       0x00400000
  76 #define MBP_RXPROMISC                   0x00200000
  77 #define MBP_PROMISCCHAN(channel)        (((channel) & 0x7) << 16)
  78 #define MBP_RXBCAST                     0x00002000
  79 #define MBP_BCASTCHAN(channel)          (((channel) & 0x7) << 8)
  80 #define MBP_RXMCAST                     0x00000020
  81 #define MBP_MCASTCHAN(channel)          ((channel) & 0x7)
  82 #define CPMAC_UNICAST_ENABLE            0x0104
  83 #define CPMAC_UNICAST_CLEAR             0x0108
  84 #define CPMAC_MAX_LENGTH                0x010c
  85 #define CPMAC_BUFFER_OFFSET             0x0110
  86 #define CPMAC_MAC_CONTROL               0x0160
  87 #define MAC_TXPTYPE                     0x00000200
  88 #define MAC_TXPACE                      0x00000040
  89 #define MAC_MII                         0x00000020
  90 #define MAC_TXFLOW                      0x00000010
  91 #define MAC_RXFLOW                      0x00000008
  92 #define MAC_MTEST                       0x00000004
  93 #define MAC_LOOPBACK                    0x00000002
  94 #define MAC_FDX                         0x00000001
  95 #define CPMAC_MAC_STATUS                0x0164
  96 #define MAC_STATUS_QOS                  0x00000004
  97 #define MAC_STATUS_RXFLOW               0x00000002
  98 #define MAC_STATUS_TXFLOW               0x00000001
  99 #define CPMAC_TX_INT_ENABLE             0x0178
 100 #define CPMAC_TX_INT_CLEAR              0x017c
 101 #define CPMAC_MAC_INT_VECTOR            0x0180
 102 #define MAC_INT_STATUS                  0x00080000
 103 #define MAC_INT_HOST                    0x00040000
 104 #define MAC_INT_RX                      0x00020000
 105 #define MAC_INT_TX                      0x00010000
 106 #define CPMAC_MAC_EOI_VECTOR            0x0184
 107 #define CPMAC_RX_INT_ENABLE             0x0198
 108 #define CPMAC_RX_INT_CLEAR              0x019c
 109 #define CPMAC_MAC_INT_ENABLE            0x01a8
 110 #define CPMAC_MAC_INT_CLEAR             0x01ac
 111 #define CPMAC_MAC_ADDR_LO(channel)      (0x01b0 + (channel) * 4)
 112 #define CPMAC_MAC_ADDR_MID              0x01d0
 113 #define CPMAC_MAC_ADDR_HI               0x01d4
 114 #define CPMAC_MAC_HASH_LO               0x01d8
 115 #define CPMAC_MAC_HASH_HI               0x01dc
 116 #define CPMAC_TX_PTR(channel)           (0x0600 + (channel) * 4)
 117 #define CPMAC_RX_PTR(channel)           (0x0620 + (channel) * 4)
 118 #define CPMAC_TX_ACK(channel)           (0x0640 + (channel) * 4)
 119 #define CPMAC_RX_ACK(channel)           (0x0660 + (channel) * 4)
 120 #define CPMAC_REG_END                   0x0680
 121
 122 /* Rx/Tx statistics
 123  * TODO: use some of them to fill stats in cpmac_stats()
 124  */
 125 #define CPMAC_STATS_RX_GOOD             0x0200
 126 #define CPMAC_STATS_RX_BCAST            0x0204
 127 #define CPMAC_STATS_RX_MCAST            0x0208
 128 #define CPMAC_STATS_RX_PAUSE            0x020c
 129 #define CPMAC_STATS_RX_CRC              0x0210
 130 #define CPMAC_STATS_RX_ALIGN            0x0214
 131 #define CPMAC_STATS_RX_OVER             0x0218
 132 #define CPMAC_STATS_RX_JABBER           0x021c
 133 #define CPMAC_STATS_RX_UNDER            0x0220
 134 #define CPMAC_STATS_RX_FRAG             0x0224
 135 #define CPMAC_STATS_RX_FILTER           0x0228
 136 #define CPMAC_STATS_RX_QOSFILTER        0x022c
 137 #define CPMAC_STATS_RX_OCTETS           0x0230
 138
 139 #define CPMAC_STATS_TX_GOOD             0x0234
 140 #define CPMAC_STATS_TX_BCAST            0x0238
 141 #define CPMAC_STATS_TX_MCAST            0x023c
 142 #define CPMAC_STATS_TX_PAUSE            0x0240
 143 #define CPMAC_STATS_TX_DEFER            0x0244
 144 #define CPMAC_STATS_TX_COLLISION        0x0248
 145 #define CPMAC_STATS_TX_SINGLECOLL       0x024c
 146 #define CPMAC_STATS_TX_MULTICOLL        0x0250
 147 #define CPMAC_STATS_TX_EXCESSCOLL       0x0254
 148 #define CPMAC_STATS_TX_LATECOLL         0x0258
 149 #define CPMAC_STATS_TX_UNDERRUN         0x025c
 150 #define CPMAC_STATS_TX_CARRIERSENSE     0x0260
 151 #define CPMAC_STATS_TX_OCTETS           0x0264
 152
 153 #define cpmac_read(base, reg)           (readl((void __iomem *)(base) + (reg)))
 154 #define cpmac_write(base, reg, val)     (writel(val, (void __iomem *)(base) + \
 155                                                 (reg)))
 156
 157 /* MDIO bus */
 158 #define CPMAC_MDIO_VERSION              0x0000
 159 #define CPMAC_MDIO_CONTROL              0x0004
 160 #define MDIOC_IDLE                      0x80000000
 161 #define MDIOC_ENABLE                    0x40000000
 162 #define MDIOC_PREAMBLE                  0x00100000
 163 #define MDIOC_FAULT                     0x00080000
 164 #define MDIOC_FAULTDETECT               0x00040000
 165 #define MDIOC_INTTEST                   0x00020000
 166 #define MDIOC_CLKDIV(div)               ((div) & 0xff)
 167 #define CPMAC_MDIO_ALIVE                0x0008
 168 #define CPMAC_MDIO_LINK                 0x000c
 169 #define CPMAC_MDIO_ACCESS(channel)      (0x0080 + (channel) * 8)
 170 #define MDIO_BUSY                       0x80000000
 171 #define MDIO_WRITE                      0x40000000
 172 #define MDIO_REG(reg)                   (((reg) & 0x1f) << 21)
 173 #define MDIO_PHY(phy)                   (((phy) & 0x1f) << 16)
 174 #define MDIO_DATA(data)                 ((data) & 0xffff)
 175 #define CPMAC_MDIO_PHYSEL(channel)      (0x0084 + (channel) * 8)
 176 #define PHYSEL_LINKSEL                  0x00000040
 177 #define PHYSEL_LINKINT                  0x00000020
 178
 179 struct cpmac_desc {
 180         u32 hw_next;
 181         u32 hw_data;
 182         u16 buflen;
 183         u16 bufflags;
 184         u16 datalen;
 185         u16 dataflags;
 186 #define CPMAC_SOP                       0x8000
 187 #define CPMAC_EOP                       0x4000
 188 #define CPMAC_OWN                       0x2000
 189 #define CPMAC_EOQ                       0x1000
 190         struct sk_buff *skb;
 191         struct cpmac_desc *next;
 192         struct cpmac_desc *prev;
 193         dma_addr_t mapping;
 194         dma_addr_t data_mapping;
 195 };
 196
 197 struct cpmac_priv {
 198         spinlock_t lock;
 199         spinlock_t rx_lock;
 200         struct cpmac_desc *rx_head;
 201         int ring_size;
 202         struct cpmac_desc *desc_ring;
 203         dma_addr_t dma_ring;
 204         void __iomem *regs;
 205         struct mii_bus *mii_bus;
 206         struct phy_device *phy;
 207         char phy_name[MII_BUS_ID_SIZE + 3];
 208         int oldlink, oldspeed, oldduplex;
 209         u32 msg_enable;
 210         struct net_device *dev;
 211         struct work_struct reset_work;
 212         struct platform_device *pdev;
 213         struct napi_struct napi;
 214         atomic_t reset_pending;
 215 };
 216
 217 static irqreturn_t cpmac_irq(int, void *);
 218 static void cpmac_hw_start(struct net_device *dev);
 219 static void cpmac_hw_stop(struct net_device *dev);
 220 static int cpmac_stop(struct net_device *dev);
 221 static int cpmac_open(struct net_device *dev);
 222
 223 static void cpmac_dump_regs(struct net_device *dev)
 224 {
 225         int i;
 226         struct cpmac_priv *priv = netdev_priv(dev);
 227
 228         for (i = 0; i < CPMAC_REG_END; i += 4) {
 229                 if (i % 16 == 0) {
 230                         if (i)
 231                                 pr_cont("\n");
 232                         netdev_dbg(dev, "reg[%p]:", priv->regs + i);
 233                 }
 234                 pr_debug(" %08x", cpmac_read(priv->regs, i));
 235         }
 236         pr_debug("\n");
 237 }
 238
 239 static void cpmac_dump_desc(struct net_device *dev, struct cpmac_desc *desc)
 240 {
 241         int i;
 242
 243         netdev_dbg(dev, "desc[%p]:", desc);
 244         for (i = 0; i < sizeof(*desc) / 4; i++)
 245                 pr_debug(" %08x", ((u32 *)desc)[i]);
 246         pr_debug("\n");
 247 }
 248
 249 static void cpmac_dump_all_desc(struct net_device *dev)
 250 {
 251         struct cpmac_priv *priv = netdev_priv(dev);
 252         struct cpmac_desc *dump = priv->rx_head;
 253
 254         do {
 255                 cpmac_dump_desc(dev, dump);
 256                 dump = dump->next;
 257         } while (dump != priv->rx_head);
 258 }
 259
 260 static void cpmac_dump_skb(struct net_device *dev, struct sk_buff *skb)
 261 {
 262         int i;
 263
 264         netdev_dbg(dev, "skb 0x%p, len=%d\n", skb, skb->len);
 265         for (i = 0; i < skb->len; i++) {
 266                 if (i % 16 == 0) {
 267                         if (i)
 268                                 pr_cont("\n");
 269                         netdev_dbg(dev, "data[%p]:", skb->data + i);
 270                 }
 271                 pr_debug(" %02x", ((u8 *)skb->data)[i]);
 272         }
 273         pr_debug("\n");
 274 }
 275
 276 static int cpmac_mdio_read(struct mii_bus *bus, int phy_id, int reg)
 277 {
 278         u32 val;
 279
 280         while (cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0)) & MDIO_BUSY)
 281                 cpu_relax();
 282         cpmac_write(bus->priv, CPMAC_MDIO_ACCESS(0), MDIO_BUSY | MDIO_REG(reg) |
 283                     MDIO_PHY(phy_id));
 284         while ((val = cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0))) & MDIO_BUSY)
 285                 cpu_relax();
 286         return MDIO_DATA(val);
 287 }
 288
 289 static int cpmac_mdio_write(struct mii_bus *bus, int phy_id,
 290                             int reg, u16 val)
 291 {
 292         while (cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0)) & MDIO_BUSY)
 293                 cpu_relax();
 294         cpmac_write(bus->priv, CPMAC_MDIO_ACCESS(0), MDIO_BUSY | MDIO_WRITE |
 295                     MDIO_REG(reg) | MDIO_PHY(phy_id) | MDIO_DATA(val));
 296         return 0;
 297 }
 298
 299 static int cpmac_mdio_reset(struct mii_bus *bus)
 300 {
 301         struct clk *cpmac_clk;
 302
 303         cpmac_clk = clk_get(&bus->dev, "cpmac");
 304         if (IS_ERR(cpmac_clk)) {
 305                 pr_err("unable to get cpmac clock\n");
 306                 return -1;
 307         }
 308         ar7_device_reset(AR7_RESET_BIT_MDIO);
 309         cpmac_write(bus->priv, CPMAC_MDIO_CONTROL, MDIOC_ENABLE |
 310                     MDIOC_CLKDIV(clk_get_rate(cpmac_clk) / 2200000 - 1));
 311         return 0;
 312 }
 313
 314 static int mii_irqs[PHY_MAX_ADDR] = { PHY_POLL, };
 315
 316 static struct mii_bus *cpmac_mii;
 317
 318 static void cpmac_set_multicast_list(struct net_device *dev)
 319 {
 320         struct netdev_hw_addr *ha;
 321         u8 tmp;
 322         u32 mbp, bit, hash[2] = { 0, };
 323         struct cpmac_priv *priv = netdev_priv(dev);
 324
 325         mbp = cpmac_read(priv->regs, CPMAC_MBP);
 326         if (dev->flags & IFF_PROMISC) {
 327                 cpmac_write(priv->regs, CPMAC_MBP, (mbp & ~MBP_PROMISCCHAN(0)) |
 328                             MBP_RXPROMISC);
 329         } else {
 330                 cpmac_write(priv->regs, CPMAC_MBP, mbp & ~MBP_RXPROMISC);
 331                 if (dev->flags & IFF_ALLMULTI) {
 332                         /* enable all multicast mode */
 333                         cpmac_write(priv->regs, CPMAC_MAC_HASH_LO, 0xffffffff);
 334                         cpmac_write(priv->regs, CPMAC_MAC_HASH_HI, 0xffffffff);
 335                 } else {
 336                         /* cpmac uses some strange mac address hashing
 337                          * (not crc32)
 338                          */
 339                         netdev_for_each_mc_addr(ha, dev) {
 340                                 bit = 0;
 341                                 tmp = ha->addr[0];
 342                                 bit  ^= (tmp >> 2) ^ (tmp << 4);
 343                                 tmp = ha->addr[1];
 344                                 bit  ^= (tmp >> 4) ^ (tmp << 2);
 345                                 tmp = ha->addr[2];
 346                                 bit  ^= (tmp >> 6) ^ tmp;
 347                                 tmp = ha->addr[3];
 348                                 bit  ^= (tmp >> 2) ^ (tmp << 4);
 349                                 tmp = ha->addr[4];
 350                                 bit  ^= (tmp >> 4) ^ (tmp << 2);
 351                                 tmp = ha->addr[5];
 352                                 bit  ^= (tmp >> 6) ^ tmp;
 353                                 bit &= 0x3f;
 354                                 hash[bit / 32] |= 1 << (bit % 32);
 355                         }
 356
 357                         cpmac_write(priv->regs, CPMAC_MAC_HASH_LO, hash[0]);
 358                         cpmac_write(priv->regs, CPMAC_MAC_HASH_HI, hash[1]);
 359                 }
 360         }
 361 }
 362
 363 static struct sk_buff *cpmac_rx_one(struct cpmac_priv *priv,
 364                                     struct cpmac_desc *desc)
 365 {
 366         struct sk_buff *skb, *result = NULL;
 367
 368         if (unlikely(netif_msg_hw(priv)))
 369                 cpmac_dump_desc(priv->dev, desc);
 370         cpmac_write(priv->regs, CPMAC_RX_ACK(0), (u32)desc->mapping);
 371         if (unlikely(!desc->datalen)) {
 372                 if (netif_msg_rx_err(priv) && net_ratelimit())
 373                         netdev_warn(priv->dev, "rx: spurious interrupt\n");
 374
 375                 return NULL;
 376         }
 377
 378         skb = netdev_alloc_skb_ip_align(priv->dev, CPMAC_SKB_SIZE);
 379         if (likely(skb)) {
 380                 skb_put(desc->skb, desc->datalen);
 381                 desc->skb->protocol = eth_type_trans(desc->skb, priv->dev);
 382                 skb_checksum_none_assert(desc->skb);
 383                 priv->dev->stats.rx_packets++;
 384                 priv->dev->stats.rx_bytes += desc->datalen;
 385                 result = desc->skb;
 386                 dma_unmap_single(&priv->dev->dev, desc->data_mapping,
 387                                  CPMAC_SKB_SIZE, DMA_FROM_DEVICE);
 388                 desc->skb = skb;
 389                 desc->data_mapping = dma_map_single(&priv->dev->dev, skb->data,
 390                                                     CPMAC_SKB_SIZE,
 391                                                     DMA_FROM_DEVICE);
 392                 desc->hw_data = (u32)desc->data_mapping;
 393                 if (unlikely(netif_msg_pktdata(priv))) {
 394                         netdev_dbg(priv->dev, "received packet:\n");
 395                         cpmac_dump_skb(priv->dev, result);
 396                 }
 397         } else {
 398                 if (netif_msg_rx_err(priv) && net_ratelimit())
 399                         netdev_warn(priv->dev,
 400                                     "low on skbs, dropping packet\n");
 401
 402                 priv->dev->stats.rx_dropped++;
 403         }
 404
 405         desc->buflen = CPMAC_SKB_SIZE;
 406         desc->dataflags = CPMAC_OWN;
 407
 408         return result;
 409 }
 410
 411 static int cpmac_poll(struct napi_struct *napi, int budget)
 412 {
 413         struct sk_buff *skb;
 414         struct cpmac_desc *desc, *restart;
 415         struct cpmac_priv *priv = container_of(napi, struct cpmac_priv, napi);
 416         int received = 0, processed = 0;
 417
 418         spin_lock(&priv->rx_lock);
 419         if (unlikely(!priv->rx_head)) {
 420                 if (netif_msg_rx_err(priv) && net_ratelimit())
 421                         netdev_warn(priv->dev, "rx: polling, but no queue\n");
 422
 423                 spin_unlock(&priv->rx_lock);
 424                 napi_complete(napi);
 425                 return 0;
 426         }
 427
 428         desc = priv->rx_head;
 429         restart = NULL;
 430         while (((desc->dataflags & CPMAC_OWN) == 0) && (received < budget)) {
 431                 processed++;
 432
 433                 if ((desc->dataflags & CPMAC_EOQ) != 0) {
 434                         /* The last update to eoq->hw_next didn't happen
 435                          * soon enough, and the receiver stopped here.
 436                          * Remember this descriptor so we can restart
 437                          * the receiver after freeing some space.
 438                          */
 439                         if (unlikely(restart)) {
 440                                 if (netif_msg_rx_err(priv))
 441                                         netdev_err(priv->dev, "poll found a"
 442                                                    " duplicate EOQ: %p and %p\n",
 443                                                    restart, desc);
 444                                 goto fatal_error;
 445                         }
 446
 447                         restart = desc->next;
 448                 }
 449
 450                 skb = cpmac_rx_one(priv, desc);
 451                 if (likely(skb)) {
 452                         netif_receive_skb(skb);
 453                         received++;
 454                 }
 455                 desc = desc->next;
 456         }
 457
 458         if (desc != priv->rx_head) {
 459                 /* We freed some buffers, but not the whole ring,
 460                  * add what we did free to the rx list
 461                  */
 462                 desc->prev->hw_next = (u32)0;
 463                 priv->rx_head->prev->hw_next = priv->rx_head->mapping;
 464         }
 465
 466         /* Optimization: If we did not actually process an EOQ (perhaps because
 467          * of quota limits), check to see if the tail of the queue has EOQ set.
 468          * We should immediately restart in that case so that the receiver can
 469          * restart and run in parallel with more packet processing.
 470          * This lets us handle slightly larger bursts before running
 471          * out of ring space (assuming dev->weight < ring_size)
 472          */
 473
 474         if (!restart &&
 475              (priv->rx_head->prev->dataflags & (CPMAC_OWN|CPMAC_EOQ))
 476                     == CPMAC_EOQ &&
 477              (priv->rx_head->dataflags & CPMAC_OWN) != 0) {
 478                 /* reset EOQ so the poll loop (above) doesn't try to
 479                  * restart this when it eventually gets to this descriptor.
 480                  */
 481                 priv->rx_head->prev->dataflags &= ~CPMAC_EOQ;
 482                 restart = priv->rx_head;
 483         }
 484
 485         if (restart) {
 486                 priv->dev->stats.rx_errors++;
 487                 priv->dev->stats.rx_fifo_errors++;
 488                 if (netif_msg_rx_err(priv) && net_ratelimit())
 489                         netdev_warn(priv->dev, "rx dma ring overrun\n");
 490
 491                 if (unlikely((restart->dataflags & CPMAC_OWN) == 0)) {
 492                         if (netif_msg_drv(priv))
 493                                 netdev_err(priv->dev, "cpmac_poll is trying "
 494                                         "to restart rx from a descriptor "
 495                                         "that's not free: %p\n", restart);
 496                         goto fatal_error;
 497                 }
 498
 499                 cpmac_write(priv->regs, CPMAC_RX_PTR(0), restart->mapping);
 500         }
 501
 502         priv->rx_head = desc;
 503         spin_unlock(&priv->rx_lock);
 504         if (unlikely(netif_msg_rx_status(priv)))
 505                 netdev_dbg(priv->dev, "poll processed %d packets\n", received);
 506
 507         if (processed == 0) {
 508                 /* we ran out of packets to read,
 509                  * revert to interrupt-driven mode
 510                  */
 511                 napi_complete(napi);
 512                 cpmac_write(priv->regs, CPMAC_RX_INT_ENABLE, 1);
 513                 return 0;
 514         }
 515
 516         return 1;
 517
 518 fatal_error:
 519         /* Something went horribly wrong.
 520          * Reset hardware to try to recover rather than wedging.
 521          */
 522         if (netif_msg_drv(priv)) {
 523                 netdev_err(priv->dev, "cpmac_poll is confused. "
 524                            "Resetting hardware\n");
 525                 cpmac_dump_all_desc(priv->dev);
 526                 netdev_dbg(priv->dev, "RX_PTR(0)=0x%08x RX_ACK(0)=0x%08x\n",
 527                            cpmac_read(priv->regs, CPMAC_RX_PTR(0)),
 528                            cpmac_read(priv->regs, CPMAC_RX_ACK(0)));
 529         }
 530
 531         spin_unlock(&priv->rx_lock);
 532         napi_complete(napi);
 533         netif_tx_stop_all_queues(priv->dev);
 534         napi_disable(&priv->napi);
 535
 536         atomic_inc(&priv->reset_pending);
 537         cpmac_hw_stop(priv->dev);
 538         if (!schedule_work(&priv->reset_work))
 539                 atomic_dec(&priv->reset_pending);
 540         return 0;
 541
 542 }
 543
 544 static int cpmac_start_xmit(struct sk_buff *skb, struct net_device *dev)
 545 {
 546         int queue, len;
 547         struct cpmac_desc *desc;
 548         struct cpmac_priv *priv = netdev_priv(dev);
 549
 550         if (unlikely(atomic_read(&priv->reset_pending)))
 551                 return NETDEV_TX_BUSY;
 552
 553         if (unlikely(skb_padto(skb, ETH_ZLEN)))
 554                 return NETDEV_TX_OK;
 555
 556         len = max(skb->len, ETH_ZLEN);
 557         queue = skb_get_queue_mapping(skb);
 558         netif_stop_subqueue(dev, queue);
 559
 560         desc = &priv->desc_ring[queue];
 561         if (unlikely(desc->dataflags & CPMAC_OWN)) {
 562                 if (netif_msg_tx_err(priv) && net_ratelimit())
 563                         netdev_warn(dev, "tx dma ring full\n");
 564
 565                 return NETDEV_TX_BUSY;
 566         }
 567
 568         spin_lock(&priv->lock);
 569         spin_unlock(&priv->lock);
 570         desc->dataflags = CPMAC_SOP | CPMAC_EOP | CPMAC_OWN;
 571         desc->skb = skb;
 572         desc->data_mapping = dma_map_single(&dev->dev, skb->data, len,
 573                                             DMA_TO_DEVICE);
 574         desc->hw_data = (u32)desc->data_mapping;
 575         desc->datalen = len;
 576         desc->buflen = len;
 577         if (unlikely(netif_msg_tx_queued(priv)))
 578                 netdev_dbg(dev, "sending 0x%p, len=%d\n", skb, skb->len);
 579         if (unlikely(netif_msg_hw(priv)))
 580                 cpmac_dump_desc(dev, desc);
 581         if (unlikely(netif_msg_pktdata(priv)))
 582                 cpmac_dump_skb(dev, skb);
 583         cpmac_write(priv->regs, CPMAC_TX_PTR(queue), (u32)desc->mapping);
 584
 585         return NETDEV_TX_OK;
 586 }
 587
 588 static void cpmac_end_xmit(struct net_device *dev, int queue)
 589 {
 590         struct cpmac_desc *desc;
 591         struct cpmac_priv *priv = netdev_priv(dev);
 592
 593         desc = &priv->desc_ring[queue];
 594         cpmac_write(priv->regs, CPMAC_TX_ACK(queue), (u32)desc->mapping);
 595         if (likely(desc->skb)) {
 596                 spin_lock(&priv->lock);
 597                 dev->stats.tx_packets++;
 598                 dev->stats.tx_bytes += desc->skb->len;
 599                 spin_unlock(&priv->lock);
 600                 dma_unmap_single(&dev->dev, desc->data_mapping, desc->skb->len,
 601                                  DMA_TO_DEVICE);
 602
 603                 if (unlikely(netif_msg_tx_done(priv)))
 604                         netdev_dbg(dev, "sent 0x%p, len=%d\n",
 605                                    desc->skb, desc->skb->len);
 606
 607                 dev_kfree_skb_irq(desc->skb);
 608                 desc->skb = NULL;
 609                 if (__netif_subqueue_stopped(dev, queue))
 610                         netif_wake_subqueue(dev, queue);
 611         } else {
 612                 if (netif_msg_tx_err(priv) && net_ratelimit())
 613                         netdev_warn(dev, "end_xmit: spurious interrupt\n");
 614                 if (__netif_subqueue_stopped(dev, queue))
 615                         netif_wake_subqueue(dev, queue);
 616         }
 617 }
 618
 619 static void cpmac_hw_stop(struct net_device *dev)
 620 {
 621         int i;
 622         struct cpmac_priv *priv = netdev_priv(dev);
 623         struct plat_cpmac_data *pdata = dev_get_platdata(&priv->pdev->dev);
 624
 625         ar7_device_reset(pdata->reset_bit);
 626         cpmac_write(priv->regs, CPMAC_RX_CONTROL,
 627                     cpmac_read(priv->regs, CPMAC_RX_CONTROL) & ~1);
 628         cpmac_write(priv->regs, CPMAC_TX_CONTROL,
 629                     cpmac_read(priv->regs, CPMAC_TX_CONTROL) & ~1);
 630         for (i = 0; i < 8; i++) {
 631                 cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
 632                 cpmac_write(priv->regs, CPMAC_RX_PTR(i), 0);
 633         }
 634         cpmac_write(priv->regs, CPMAC_UNICAST_CLEAR, 0xff);
 635         cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 0xff);
 636         cpmac_write(priv->regs, CPMAC_TX_INT_CLEAR, 0xff);
 637         cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff);
 638         cpmac_write(priv->regs, CPMAC_MAC_CONTROL,
 639                     cpmac_read(priv->regs, CPMAC_MAC_CONTROL) & ~MAC_MII);
 640 }
 641
 642 static void cpmac_hw_start(struct net_device *dev)
 643 {
 644         int i;
 645         struct cpmac_priv *priv = netdev_priv(dev);
 646         struct plat_cpmac_data *pdata = dev_get_platdata(&priv->pdev->dev);
 647
 648         ar7_device_reset(pdata->reset_bit);
 649         for (i = 0; i < 8; i++) {
 650                 cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
 651                 cpmac_write(priv->regs, CPMAC_RX_PTR(i), 0);
 652         }
 653         cpmac_write(priv->regs, CPMAC_RX_PTR(0), priv->rx_head->mapping);
 654
 655         cpmac_write(priv->regs, CPMAC_MBP, MBP_RXSHORT | MBP_RXBCAST |
 656                     MBP_RXMCAST);
 657         cpmac_write(priv->regs, CPMAC_BUFFER_OFFSET, 0);
 658         for (i = 0; i < 8; i++)
 659                 cpmac_write(priv->regs, CPMAC_MAC_ADDR_LO(i), dev->dev_addr[5]);
 660         cpmac_write(priv->regs, CPMAC_MAC_ADDR_MID, dev->dev_addr[4]);
 661         cpmac_write(priv->regs, CPMAC_MAC_ADDR_HI, dev->dev_addr[0] |
 662                     (dev->dev_addr[1] << 8) | (dev->dev_addr[2] << 16) |
 663                     (dev->dev_addr[3] << 24));
 664         cpmac_write(priv->regs, CPMAC_MAX_LENGTH, CPMAC_SKB_SIZE);
 665         cpmac_write(priv->regs, CPMAC_UNICAST_CLEAR, 0xff);
 666         cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 0xff);
 667         cpmac_write(priv->regs, CPMAC_TX_INT_CLEAR, 0xff);
 668         cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff);
 669         cpmac_write(priv->regs, CPMAC_UNICAST_ENABLE, 1);
 670         cpmac_write(priv->regs, CPMAC_RX_INT_ENABLE, 1);
 671         cpmac_write(priv->regs, CPMAC_TX_INT_ENABLE, 0xff);
 672         cpmac_write(priv->regs, CPMAC_MAC_INT_ENABLE, 3);
 673
 674         cpmac_write(priv->regs, CPMAC_RX_CONTROL,
 675                     cpmac_read(priv->regs, CPMAC_RX_CONTROL) | 1);
 676         cpmac_write(priv->regs, CPMAC_TX_CONTROL,
 677                     cpmac_read(priv->regs, CPMAC_TX_CONTROL) | 1);
 678         cpmac_write(priv->regs, CPMAC_MAC_CONTROL,
 679                     cpmac_read(priv->regs, CPMAC_MAC_CONTROL) | MAC_MII |
 680                     MAC_FDX);
 681 }
 682
 683 static void cpmac_clear_rx(struct net_device *dev)
 684 {
 685         struct cpmac_priv *priv = netdev_priv(dev);
 686         struct cpmac_desc *desc;
 687         int i;
 688
 689         if (unlikely(!priv->rx_head))
 690                 return;
 691         desc = priv->rx_head;
 692         for (i = 0; i < priv->ring_size; i++) {
 693                 if ((desc->dataflags & CPMAC_OWN) == 0) {
 694                         if (netif_msg_rx_err(priv) && net_ratelimit())
 695                                 netdev_warn(dev, "packet dropped\n");
 696                         if (unlikely(netif_msg_hw(priv)))
 697                                 cpmac_dump_desc(dev, desc);
 698                         desc->dataflags = CPMAC_OWN;
 699                         dev->stats.rx_dropped++;
 700                 }
 701                 desc->hw_next = desc->next->mapping;
 702                 desc = desc->next;
 703         }
 704         priv->rx_head->prev->hw_next = 0;
 705 }
 706
 707 static void cpmac_clear_tx(struct net_device *dev)
 708 {
 709         struct cpmac_priv *priv = netdev_priv(dev);
 710         int i;
 711
 712         if (unlikely(!priv->desc_ring))
 713                 return;
 714         for (i = 0; i < CPMAC_QUEUES; i++) {
 715                 priv->desc_ring[i].dataflags = 0;
 716                 if (priv->desc_ring[i].skb) {
 717                         dev_kfree_skb_any(priv->desc_ring[i].skb);
 718                         priv->desc_ring[i].skb = NULL;
 719                 }
 720         }
 721 }
 722
 723 static void cpmac_hw_error(struct work_struct *work)
 724 {
 725         struct cpmac_priv *priv =
 726                 container_of(work, struct cpmac_priv, reset_work);
 727
 728         spin_lock(&priv->rx_lock);
 729         cpmac_clear_rx(priv->dev);
 730         spin_unlock(&priv->rx_lock);
 731         cpmac_clear_tx(priv->dev);
 732         cpmac_hw_start(priv->dev);
 733         barrier();
 734         atomic_dec(&priv->reset_pending);
 735
 736         netif_tx_wake_all_queues(priv->dev);
 737         cpmac_write(priv->regs, CPMAC_MAC_INT_ENABLE, 3);
 738 }
 739
 740 static void cpmac_check_status(struct net_device *dev)
 741 {
 742         struct cpmac_priv *priv = netdev_priv(dev);
 743
 744         u32 macstatus = cpmac_read(priv->regs, CPMAC_MAC_STATUS);
 745         int rx_channel = (macstatus >> 8) & 7;
 746         int rx_code = (macstatus >> 12) & 15;
 747         int tx_channel = (macstatus >> 16) & 7;
 748         int tx_code = (macstatus >> 20) & 15;
 749
 750         if (rx_code || tx_code) {
 751                 if (netif_msg_drv(priv) && net_ratelimit()) {
 752                         /* Can't find any documentation on what these
 753                          * error codes actually are. So just log them and hope..
 754                          */
 755                         if (rx_code)
 756                                 netdev_warn(dev, "host error %d on rx "
 757                                         "channel %d (macstatus %08x), resetting\n",
 758                                         rx_code, rx_channel, macstatus);
 759                         if (tx_code)
 760                                 netdev_warn(dev, "host error %d on tx "
 761                                         "channel %d (macstatus %08x), resetting\n",
 762                                         tx_code, tx_channel, macstatus);
 763                 }
 764
 765                 netif_tx_stop_all_queues(dev);
 766                 cpmac_hw_stop(dev);
 767                 if (schedule_work(&priv->reset_work))
 768                         atomic_inc(&priv->reset_pending);
 769                 if (unlikely(netif_msg_hw(priv)))
 770                         cpmac_dump_regs(dev);
 771         }
 772         cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff);
 773 }
 774
 775 static irqreturn_t cpmac_irq(int irq, void *dev_id)
 776 {
 777         struct net_device *dev = dev_id;
 778         struct cpmac_priv *priv;
 779         int queue;
 780         u32 status;
 781
 782         priv = netdev_priv(dev);
 783
 784         status = cpmac_read(priv->regs, CPMAC_MAC_INT_VECTOR);
 785
 786         if (unlikely(netif_msg_intr(priv)))
 787                 netdev_dbg(dev, "interrupt status: 0x%08x\n", status);
 788
 789         if (status & MAC_INT_TX)
 790                 cpmac_end_xmit(dev, (status & 7));
 791
 792         if (status & MAC_INT_RX) {
 793                 queue = (status >> 8) & 7;
 794                 if (napi_schedule_prep(&priv->napi)) {
 795                         cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 1 << queue);
 796                         __napi_schedule(&priv->napi);
 797                 }
 798         }
 799
 800         cpmac_write(priv->regs, CPMAC_MAC_EOI_VECTOR, 0);
 801
 802         if (unlikely(status & (MAC_INT_HOST | MAC_INT_STATUS)))
 803                 cpmac_check_status(dev);
 804
 805         return IRQ_HANDLED;
 806 }
 807
 808 static void cpmac_tx_timeout(struct net_device *dev)
 809 {
 810         struct cpmac_priv *priv = netdev_priv(dev);
 811
 812         spin_lock(&priv->lock);
 813         dev->stats.tx_errors++;
 814         spin_unlock(&priv->lock);
 815         if (netif_msg_tx_err(priv) && net_ratelimit())
 816                 netdev_warn(dev, "transmit timeout\n");
 817
 818         atomic_inc(&priv->reset_pending);
 819         barrier();
 820         cpmac_clear_tx(dev);
 821         barrier();
 822         atomic_dec(&priv->reset_pending);
 823
 824         netif_tx_wake_all_queues(priv->dev);
 825 }
 826
 827 static int cpmac_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
 828 {
 829         struct cpmac_priv *priv = netdev_priv(dev);
 830
 831         if (!(netif_running(dev)))
 832                 return -EINVAL;
 833         if (!priv->phy)
 834                 return -EINVAL;
 835
 836         return phy_mii_ioctl(priv->phy, ifr, cmd);
 837 }
 838
 839 static int cpmac_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 840 {
 841         struct cpmac_priv *priv = netdev_priv(dev);
 842
 843         if (priv->phy)
 844                 return phy_ethtool_gset(priv->phy, cmd);
 845
 846         return -EINVAL;
 847 }
 848
 849 static int cpmac_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 850 {
 851         struct cpmac_priv *priv = netdev_priv(dev);
 852
 853         if (!capable(CAP_NET_ADMIN))
 854                 return -EPERM;
 855
 856         if (priv->phy)
 857                 return phy_ethtool_sset(priv->phy, cmd);
 858
 859         return -EINVAL;
 860 }
 861
 862 static void cpmac_get_ringparam(struct net_device *dev,
 863                                                 struct ethtool_ringparam *ring)
 864 {
 865         struct cpmac_priv *priv = netdev_priv(dev);
 866
 867         ring->rx_max_pending = 1024;
 868         ring->rx_mini_max_pending = 1;
 869         ring->rx_jumbo_max_pending = 1;
 870         ring->tx_max_pending = 1;
 871
 872         ring->rx_pending = priv->ring_size;
 873         ring->rx_mini_pending = 1;
 874         ring->rx_jumbo_pending = 1;
 875         ring->tx_pending = 1;
 876 }
 877
 878 static int cpmac_set_ringparam(struct net_device *dev,
 879                                                 struct ethtool_ringparam *ring)
 880 {
 881         struct cpmac_priv *priv = netdev_priv(dev);
 882
 883         if (netif_running(dev))
 884                 return -EBUSY;
 885         priv->ring_size = ring->rx_pending;
 886         return 0;
 887 }
 888
 889 static void cpmac_get_drvinfo(struct net_device *dev,
 890                               struct ethtool_drvinfo *info)
 891 {
 892         strlcpy(info->driver, "cpmac", sizeof(info->driver));
 893         strlcpy(info->version, CPMAC_VERSION, sizeof(info->version));
 894         snprintf(info->bus_info, sizeof(info->bus_info), "%s", "cpmac");
 895         info->regdump_len = 0;
 896 }
 897
 898 static const struct ethtool_ops cpmac_ethtool_ops = {
 899         .get_settings = cpmac_get_settings,
 900         .set_settings = cpmac_set_settings,
 901         .get_drvinfo = cpmac_get_drvinfo,
 902         .get_link = ethtool_op_get_link,
 903         .get_ringparam = cpmac_get_ringparam,
 904         .set_ringparam = cpmac_set_ringparam,
 905 };
 906
 907 static void cpmac_adjust_link(struct net_device *dev)
 908 {
 909         struct cpmac_priv *priv = netdev_priv(dev);
 910         int new_state = 0;
 911
 912         spin_lock(&priv->lock);
 913         if (priv->phy->link) {
 914                 netif_tx_start_all_queues(dev);
 915                 if (priv->phy->duplex != priv->oldduplex) {
 916                         new_state = 1;
 917                         priv->oldduplex = priv->phy->duplex;
 918                 }
 919
 920                 if (priv->phy->speed != priv->oldspeed) {
 921                         new_state = 1;
 922                         priv->oldspeed = priv->phy->speed;
 923                 }
 924
 925                 if (!priv->oldlink) {
 926                         new_state = 1;
 927                         priv->oldlink = 1;
 928                 }
 929         } else if (priv->oldlink) {
 930                 new_state = 1;
 931                 priv->oldlink = 0;
 932                 priv->oldspeed = 0;
 933                 priv->oldduplex = -1;
 934         }
 935
 936         if (new_state && netif_msg_link(priv) && net_ratelimit())
 937                 phy_print_status(priv->phy);
 938
 939         spin_unlock(&priv->lock);
 940 }
 941
 942 static int cpmac_open(struct net_device *dev)
 943 {
 944         int i, size, res;
 945         struct cpmac_priv *priv = netdev_priv(dev);
 946         struct resource *mem;
 947         struct cpmac_desc *desc;
 948         struct sk_buff *skb;
 949
 950         mem = platform_get_resource_byname(priv->pdev, IORESOURCE_MEM, "regs");
 951         if (!request_mem_region(mem->start, resource_size(mem), dev->name)) {
 952                 if (netif_msg_drv(priv))
 953                         netdev_err(dev, "failed to request registers\n");
 954
 955                 res = -ENXIO;
 956                 goto fail_reserve;
 957         }
 958
 959         priv->regs = ioremap(mem->start, resource_size(mem));
 960         if (!priv->regs) {
 961                 if (netif_msg_drv(priv))
 962                         netdev_err(dev, "failed to remap registers\n");
 963
 964                 res = -ENXIO;
 965                 goto fail_remap;
 966         }
 967
 968         size = priv->ring_size + CPMAC_QUEUES;
 969         priv->desc_ring = dma_alloc_coherent(&dev->dev,
 970                                              sizeof(struct cpmac_desc) * size,
 971                                              &priv->dma_ring,
 972                                              GFP_KERNEL);
 973         if (!priv->desc_ring) {
 974                 res = -ENOMEM;
 975                 goto fail_alloc;
 976         }
 977
 978         for (i = 0; i < size; i++)
 979                 priv->desc_ring[i].mapping = priv->dma_ring + sizeof(*desc) * i;
 980
 981         priv->rx_head = &priv->desc_ring[CPMAC_QUEUES];
 982         for (i = 0, desc = priv->rx_head; i < priv->ring_size; i++, desc++) {
 983                 skb = netdev_alloc_skb_ip_align(dev, CPMAC_SKB_SIZE);
 984                 if (unlikely(!skb)) {
 985                         res = -ENOMEM;
 986                         goto fail_desc;
 987                 }
 988                 desc->skb = skb;
 989                 desc->data_mapping = dma_map_single(&dev->dev, skb->data,
 990                                                     CPMAC_SKB_SIZE,
 991                                                     DMA_FROM_DEVICE);
 992                 desc->hw_data = (u32)desc->data_mapping;
 993                 desc->buflen = CPMAC_SKB_SIZE;
 994                 desc->dataflags = CPMAC_OWN;
 995                 desc->next = &priv->rx_head[(i + 1) % priv->ring_size];
 996                 desc->next->prev = desc;
 997                 desc->hw_next = (u32)desc->next->mapping;
 998         }
 999
1000         priv->rx_head->prev->hw_next = (u32)0;
1001
1002         res = request_irq(dev->irq, cpmac_irq, IRQF_SHARED, dev->name, dev);
1003         if (res) {
1004                 if (netif_msg_drv(priv))
1005                         netdev_err(dev, "failed to obtain irq\n");
1006
1007                 goto fail_irq;
1008         }
1009
1010         atomic_set(&priv->reset_pending, 0);
1011         INIT_WORK(&priv->reset_work, cpmac_hw_error);
1012         cpmac_hw_start(dev);
1013
1014         napi_enable(&priv->napi);
1015         priv->phy->state = PHY_CHANGELINK;
1016         phy_start(priv->phy);
1017
1018         return 0;
1019
1020 fail_irq:
1021 fail_desc:
1022         for (i = 0; i < priv->ring_size; i++) {
1023                 if (priv->rx_head[i].skb) {
1024                         dma_unmap_single(&dev->dev,
1025                                          priv->rx_head[i].data_mapping,
1026                                          CPMAC_SKB_SIZE,
1027                                          DMA_FROM_DEVICE);
1028                         kfree_skb(priv->rx_head[i].skb);
1029                 }
1030         }
1031 fail_alloc:
1032         kfree(priv->desc_ring);
1033         iounmap(priv->regs);
1034
1035 fail_remap:
1036         release_mem_region(mem->start, resource_size(mem));
1037
1038 fail_reserve:
1039         return res;
1040 }
1041
1042 static int cpmac_stop(struct net_device *dev)
1043 {
1044         int i;
1045         struct cpmac_priv *priv = netdev_priv(dev);
1046         struct resource *mem;
1047
1048         netif_tx_stop_all_queues(dev);
1049
1050         cancel_work_sync(&priv->reset_work);
1051         napi_disable(&priv->napi);
1052         phy_stop(priv->phy);
1053
1054         cpmac_hw_stop(dev);
1055
1056         for (i = 0; i < 8; i++)
1057                 cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
1058         cpmac_write(priv->regs, CPMAC_RX_PTR(0), 0);
1059         cpmac_write(priv->regs, CPMAC_MBP, 0);
1060
1061         free_irq(dev->irq, dev);
1062         iounmap(priv->regs);
1063         mem = platform_get_resource_byname(priv->pdev, IORESOURCE_MEM, "regs");
1064         release_mem_region(mem->start, resource_size(mem));
1065         priv->rx_head = &priv->desc_ring[CPMAC_QUEUES];
1066         for (i = 0; i < priv->ring_size; i++) {
1067                 if (priv->rx_head[i].skb) {
1068                         dma_unmap_single(&dev->dev,
1069                                          priv->rx_head[i].data_mapping,
1070                                          CPMAC_SKB_SIZE,
1071                                          DMA_FROM_DEVICE);
1072                         kfree_skb(priv->rx_head[i].skb);
1073                 }
1074         }
1075
1076         dma_free_coherent(&dev->dev, sizeof(struct cpmac_desc) *
1077                           (CPMAC_QUEUES + priv->ring_size),
1078                           priv->desc_ring, priv->dma_ring);
1079         return 0;
1080 }
1081
1082 static const struct net_device_ops cpmac_netdev_ops = {
1083         .ndo_open               = cpmac_open,
1084         .ndo_stop               = cpmac_stop,
1085         .ndo_start_xmit         = cpmac_start_xmit,
1086         .ndo_tx_timeout         = cpmac_tx_timeout,
1087         .ndo_set_rx_mode        = cpmac_set_multicast_list,
1088         .ndo_do_ioctl           = cpmac_ioctl,
1089         .ndo_change_mtu         = eth_change_mtu,
1090         .ndo_validate_addr      = eth_validate_addr,
1091         .ndo_set_mac_address    = eth_mac_addr,
1092 };
1093
1094 static int external_switch;
1095
1096 static int cpmac_probe(struct platform_device *pdev)
1097 {
1098         int rc, phy_id;
1099         char mdio_bus_id[MII_BUS_ID_SIZE];
1100         struct resource *mem;
1101         struct cpmac_priv *priv;
1102         struct net_device *dev;
1103         struct plat_cpmac_data *pdata;
1104
1105         pdata = dev_get_platdata(&pdev->dev);
1106
1107         if (external_switch || dumb_switch) {
1108                 strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); /* fixed phys bus */
1109                 phy_id = pdev->id;
1110         } else {
1111                 for (phy_id = 0; phy_id < PHY_MAX_ADDR; phy_id++) {
1112                         if (!(pdata->phy_mask & (1 << phy_id)))
1113                                 continue;
1114                         if (!cpmac_mii->phy_map[phy_id])
1115                                 continue;
1116                         strncpy(mdio_bus_id, cpmac_mii->id, MII_BUS_ID_SIZE);
1117                         break;
1118                 }
1119         }
1120
1121         if (phy_id == PHY_MAX_ADDR) {
1122                 dev_err(&pdev->dev, "no PHY present, falling back "
1123                         "to switch on MDIO bus 0\n");
1124                 strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); /* fixed phys bus */
1125                 phy_id = pdev->id;
1126         }
1127
1128         dev = alloc_etherdev_mq(sizeof(*priv), CPMAC_QUEUES);
1129         if (!dev)
1130                 return -ENOMEM;
1131
1132         platform_set_drvdata(pdev, dev);
1133         priv = netdev_priv(dev);
1134
1135         priv->pdev = pdev;
1136         mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
1137         if (!mem) {
1138                 rc = -ENODEV;
1139                 goto fail;
1140         }
1141
1142         dev->irq = platform_get_irq_byname(pdev, "irq");
1143
1144         dev->netdev_ops = &cpmac_netdev_ops;
1145         dev->ethtool_ops = &cpmac_ethtool_ops;
1146
1147         netif_napi_add(dev, &priv->napi, cpmac_poll, 64);
1148
1149         spin_lock_init(&priv->lock);
1150         spin_lock_init(&priv->rx_lock);
1151         priv->dev = dev;
1152         priv->ring_size = 64;
1153         priv->msg_enable = netif_msg_init(debug_level, 0xff);
1154         memcpy(dev->dev_addr, pdata->dev_addr, sizeof(pdata->dev_addr));
1155
1156         snprintf(priv->phy_name, MII_BUS_ID_SIZE, PHY_ID_FMT,
1157                                                 mdio_bus_id, phy_id);
1158
1159         priv->phy = phy_connect(dev, priv->phy_name, cpmac_adjust_link,
1160                                 PHY_INTERFACE_MODE_MII);
1161
1162         if (IS_ERR(priv->phy)) {
1163                 if (netif_msg_drv(priv))
1164                         dev_err(&pdev->dev, "Could not attach to PHY\n");
1165
1166                 rc = PTR_ERR(priv->phy);
1167                 goto fail;
1168         }
1169
1170         rc = register_netdev(dev);
1171         if (rc) {
1172                 dev_err(&pdev->dev, "Could not register net device\n");
1173                 goto fail;
1174         }
1175
1176         if (netif_msg_probe(priv)) {
1177                 dev_info(&pdev->dev, "regs: %p, irq: %d, phy: %s, "
1178                          "mac: %pM\n", (void *)mem->start, dev->irq,
1179                          priv->phy_name, dev->dev_addr);
1180         }
1181         return 0;
1182
1183 fail:
1184         free_netdev(dev);
1185         return rc;
1186 }
1187
1188 static int cpmac_remove(struct platform_device *pdev)
1189 {
1190         struct net_device *dev = platform_get_drvdata(pdev);
1191
1192         unregister_netdev(dev);
1193         free_netdev(dev);
1194         return 0;
1195 }
1196
1197 static struct platform_driver cpmac_driver = {
1198         .driver = {
1199                 .name   = "cpmac",
1200                 .owner  = THIS_MODULE,
1201         },
1202         .probe  = cpmac_probe,
1203         .remove = cpmac_remove,
1204 };
1205
1206 int cpmac_init(void)
1207 {
1208         u32 mask;
1209         int i, res;
1210
1211         cpmac_mii = mdiobus_alloc();
1212         if (cpmac_mii == NULL)
1213                 return -ENOMEM;
1214
1215         cpmac_mii->name = "cpmac-mii";
1216         cpmac_mii->read = cpmac_mdio_read;
1217         cpmac_mii->write = cpmac_mdio_write;
1218         cpmac_mii->reset = cpmac_mdio_reset;
1219         cpmac_mii->irq = mii_irqs;
1220
1221         cpmac_mii->priv = ioremap(AR7_REGS_MDIO, 256);
1222
1223         if (!cpmac_mii->priv) {
1224                 pr_err("Can't ioremap mdio registers\n");
1225                 res = -ENXIO;
1226                 goto fail_alloc;
1227         }
1228
1229 #warning FIXME: unhardcode gpio&reset bits
1230         ar7_gpio_disable(26);
1231         ar7_gpio_disable(27);
1232         ar7_device_reset(AR7_RESET_BIT_CPMAC_LO);
1233         ar7_device_reset(AR7_RESET_BIT_CPMAC_HI);
1234         ar7_device_reset(AR7_RESET_BIT_EPHY);
1235
1236         cpmac_mii->reset(cpmac_mii);
1237
1238         for (i = 0; i < 300; i++) {
1239                 mask = cpmac_read(cpmac_mii->priv, CPMAC_MDIO_ALIVE);
1240                 if (mask)
1241                         break;
1242                 else
1243                         msleep(10);
1244         }
1245
1246         mask &= 0x7fffffff;
1247         if (mask & (mask - 1)) {
1248                 external_switch = 1;
1249                 mask = 0;
1250         }
1251
1252         cpmac_mii->phy_mask = ~(mask | 0x80000000);
1253         snprintf(cpmac_mii->id, MII_BUS_ID_SIZE, "cpmac-1");
1254
1255         res = mdiobus_register(cpmac_mii);
1256         if (res)
1257                 goto fail_mii;
1258
1259         res = platform_driver_register(&cpmac_driver);
1260         if (res)
1261                 goto fail_cpmac;
1262
1263         return 0;
1264
1265 fail_cpmac:
1266         mdiobus_unregister(cpmac_mii);
1267
1268 fail_mii:
1269         iounmap(cpmac_mii->priv);
1270
1271 fail_alloc:
1272         mdiobus_free(cpmac_mii);
1273
1274         return res;
1275 }
1276
1277 void cpmac_exit(void)
1278 {
1279         platform_driver_unregister(&cpmac_driver);
1280         mdiobus_unregister(cpmac_mii);
1281         iounmap(cpmac_mii->priv);
1282         mdiobus_free(cpmac_mii);
1283 }
1284
1285 module_init(cpmac_init);
1286 module_exit(cpmac_exit);