drivers/net/ethernet/stmicro/stmmac/stmmac_main.c

   1 /*******************************************************************************
   2   This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
   3   ST Ethernet IPs are built around a Synopsys IP Core.
   4
   5         Copyright(C) 2007-2011 STMicroelectronics Ltd
   6
   7   This program is free software; you can redistribute it and/or modify it
   8   under the terms and conditions of the GNU General Public License,
   9   version 2, as published by the Free Software Foundation.
  10
  11   This program is distributed in the hope it will be useful, but WITHOUT
  12   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14   more details.
  15
  16   You should have received a copy of the GNU General Public License along with
  17   this program; if not, write to the Free Software Foundation, Inc.,
  18   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  19
  20   The full GNU General Public License is included in this distribution in
  21   the file called "COPYING".
  22
  23   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  24
  25   Documentation available at:
  26         http://www.stlinux.com
  27   Support available at:
  28         https://bugzilla.stlinux.com/
  29 *******************************************************************************/
  30
  31 #include <linux/kernel.h>
  32 #include <linux/interrupt.h>
  33 #include <linux/ip.h>
  34 #include <linux/tcp.h>
  35 #include <linux/skbuff.h>
  36 #include <linux/ethtool.h>
  37 #include <linux/if_ether.h>
  38 #include <linux/crc32.h>
  39 #include <linux/mii.h>
  40 #include <linux/if.h>
  41 #include <linux/if_vlan.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/slab.h>
  44 #include <linux/prefetch.h>
  45 #ifdef CONFIG_STMMAC_DEBUG_FS
  46 #include <linux/debugfs.h>
  47 #include <linux/seq_file.h>
  48 #endif
  49 #include "stmmac.h"
  50
  51 #undef STMMAC_DEBUG
  52 /*#define STMMAC_DEBUG*/
  53 #ifdef STMMAC_DEBUG
  54 #define DBG(nlevel, klevel, fmt, args...) \
  55                 ((void)(netif_msg_##nlevel(priv) && \
  56                 printk(KERN_##klevel fmt, ## args)))
  57 #else
  58 #define DBG(nlevel, klevel, fmt, args...) do { } while (0)
  59 #endif
  60
  61 #undef STMMAC_RX_DEBUG
  62 /*#define STMMAC_RX_DEBUG*/
  63 #ifdef STMMAC_RX_DEBUG
  64 #define RX_DBG(fmt, args...)  printk(fmt, ## args)
  65 #else
  66 #define RX_DBG(fmt, args...)  do { } while (0)
  67 #endif
  68
  69 #undef STMMAC_XMIT_DEBUG
  70 /*#define STMMAC_XMIT_DEBUG*/
  71 #ifdef STMMAC_TX_DEBUG
  72 #define TX_DBG(fmt, args...)  printk(fmt, ## args)
  73 #else
  74 #define TX_DBG(fmt, args...)  do { } while (0)
  75 #endif
  76
  77 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
  78 #define JUMBO_LEN       9000
  79
  80 /* Module parameters */
  81 #define TX_TIMEO 5000 /* default 5 seconds */
  82 static int watchdog = TX_TIMEO;
  83 module_param(watchdog, int, S_IRUGO | S_IWUSR);
  84 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds");
  85
  86 static int debug = -1;          /* -1: default, 0: no output, 16:  all */
  87 module_param(debug, int, S_IRUGO | S_IWUSR);
  88 MODULE_PARM_DESC(debug, "Message Level (0: no output, 16: all)");
  89
  90 int phyaddr = -1;
  91 module_param(phyaddr, int, S_IRUGO);
  92 MODULE_PARM_DESC(phyaddr, "Physical device address");
  93
  94 #define DMA_TX_SIZE 256
  95 static int dma_txsize = DMA_TX_SIZE;
  96 module_param(dma_txsize, int, S_IRUGO | S_IWUSR);
  97 MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list");
  98
  99 #define DMA_RX_SIZE 256
 100 static int dma_rxsize = DMA_RX_SIZE;
 101 module_param(dma_rxsize, int, S_IRUGO | S_IWUSR);
 102 MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list");
 103
 104 static int flow_ctrl = FLOW_OFF;
 105 module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
 106 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
 107
 108 static int pause = PAUSE_TIME;
 109 module_param(pause, int, S_IRUGO | S_IWUSR);
 110 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
 111
 112 #define TC_DEFAULT 64
 113 static int tc = TC_DEFAULT;
 114 module_param(tc, int, S_IRUGO | S_IWUSR);
 115 MODULE_PARM_DESC(tc, "DMA threshold control value");
 116
 117 /* Pay attention to tune this parameter; take care of both
 118  * hardware capability and network stabitily/performance impact.
 119  * Many tests showed that ~4ms latency seems to be good enough. */
 120 #ifdef CONFIG_STMMAC_TIMER
 121 #define DEFAULT_PERIODIC_RATE   256
 122 static int tmrate = DEFAULT_PERIODIC_RATE;
 123 module_param(tmrate, int, S_IRUGO | S_IWUSR);
 124 MODULE_PARM_DESC(tmrate, "External timer freq. (default: 256Hz)");
 125 #endif
 126
 127 #define DMA_BUFFER_SIZE BUF_SIZE_2KiB
 128 static int buf_sz = DMA_BUFFER_SIZE;
 129 module_param(buf_sz, int, S_IRUGO | S_IWUSR);
 130 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
 131
 132 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
 133                                       NETIF_MSG_LINK | NETIF_MSG_IFUP |
 134                                       NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
 135
 136 #define STMMAC_DEFAULT_LPI_TIMER        1000
 137 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
 138 module_param(eee_timer, int, S_IRUGO | S_IWUSR);
 139 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
 140 #define STMMAC_LPI_TIMER(x) (jiffies + msecs_to_jiffies(x))
 141
 142 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
 143
 144 #ifdef CONFIG_STMMAC_DEBUG_FS
 145 static int stmmac_init_fs(struct net_device *dev);
 146 static void stmmac_exit_fs(void);
 147 #endif
 148
 149 /**
 150  * stmmac_verify_args - verify the driver parameters.
 151  * Description: it verifies if some wrong parameter is passed to the driver.
 152  * Note that wrong parameters are replaced with the default values.
 153  */
 154 static void stmmac_verify_args(void)
 155 {
 156         if (unlikely(watchdog < 0))
 157                 watchdog = TX_TIMEO;
 158         if (unlikely(dma_rxsize < 0))
 159                 dma_rxsize = DMA_RX_SIZE;
 160         if (unlikely(dma_txsize < 0))
 161                 dma_txsize = DMA_TX_SIZE;
 162         if (unlikely((buf_sz < DMA_BUFFER_SIZE) || (buf_sz > BUF_SIZE_16KiB)))
 163                 buf_sz = DMA_BUFFER_SIZE;
 164         if (unlikely(flow_ctrl > 1))
 165                 flow_ctrl = FLOW_AUTO;
 166         else if (likely(flow_ctrl < 0))
 167                 flow_ctrl = FLOW_OFF;
 168         if (unlikely((pause < 0) || (pause > 0xffff)))
 169                 pause = PAUSE_TIME;
 170         if (eee_timer < 0)
 171                 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
 172 }
 173
 174 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
 175 {
 176 #ifdef CONFIG_HAVE_CLK
 177         u32 clk_rate;
 178
 179         if (IS_ERR(priv->stmmac_clk))
 180                 return;
 181
 182         clk_rate = clk_get_rate(priv->stmmac_clk);
 183
 184         /* Platform provided default clk_csr would be assumed valid
 185          * for all other cases except for the below mentioned ones. */
 186         if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
 187                 if (clk_rate < CSR_F_35M)
 188                         priv->clk_csr = STMMAC_CSR_20_35M;
 189                 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
 190                         priv->clk_csr = STMMAC_CSR_35_60M;
 191                 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
 192                         priv->clk_csr = STMMAC_CSR_60_100M;
 193                 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
 194                         priv->clk_csr = STMMAC_CSR_100_150M;
 195                 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
 196                         priv->clk_csr = STMMAC_CSR_150_250M;
 197                 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
 198                         priv->clk_csr = STMMAC_CSR_250_300M;
 199         } /* For values higher than the IEEE 802.3 specified frequency
 200            * we can not estimate the proper divider as it is not known
 201            * the frequency of clk_csr_i. So we do not change the default
 202            * divider. */
 203 #endif
 204 }
 205
 206 #if defined(STMMAC_XMIT_DEBUG) || defined(STMMAC_RX_DEBUG)
 207 static void print_pkt(unsigned char *buf, int len)
 208 {
 209         int j;
 210         pr_info("len = %d byte, buf addr: 0x%p", len, buf);
 211         for (j = 0; j < len; j++) {
 212                 if ((j % 16) == 0)
 213                         pr_info("\n %03x:", j);
 214                 pr_info(" %02x", buf[j]);
 215         }
 216         pr_info("\n");
 217 }
 218 #endif
 219
 220 /* minimum number of free TX descriptors required to wake up TX process */
 221 #define STMMAC_TX_THRESH(x)     (x->dma_tx_size/4)
 222
 223 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
 224 {
 225         return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1;
 226 }
 227
 228 /* On some ST platforms, some HW system configuraton registers have to be
 229  * set according to the link speed negotiated.
 230  */
 231 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
 232 {
 233         struct phy_device *phydev = priv->phydev;
 234
 235         if (likely(priv->plat->fix_mac_speed))
 236                 priv->plat->fix_mac_speed(priv->plat->bsp_priv,
 237                                           phydev->speed);
 238 }
 239
 240 static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
 241 {
 242         /* Check and enter in LPI mode */
 243         if ((priv->dirty_tx == priv->cur_tx) &&
 244             (priv->tx_path_in_lpi_mode == false))
 245                 priv->hw->mac->set_eee_mode(priv->ioaddr);
 246 }
 247
 248 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
 249 {
 250         /* Exit and disable EEE in case of we are are in LPI state. */
 251         priv->hw->mac->reset_eee_mode(priv->ioaddr);
 252         del_timer_sync(&priv->eee_ctrl_timer);
 253         priv->tx_path_in_lpi_mode = false;
 254 }
 255
 256 /**
 257  * stmmac_eee_ctrl_timer
 258  * @arg : data hook
 259  * Description:
 260  *  If there is no data transfer and if we are not in LPI state,
 261  *  then MAC Transmitter can be moved to LPI state.
 262  */
 263 static void stmmac_eee_ctrl_timer(unsigned long arg)
 264 {
 265         struct stmmac_priv *priv = (struct stmmac_priv *)arg;
 266
 267         stmmac_enable_eee_mode(priv);
 268         mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_TIMER(eee_timer));
 269 }
 270
 271 /**
 272  * stmmac_eee_init
 273  * @priv: private device pointer
 274  * Description:
 275  *  If the EEE support has been enabled while configuring the driver,
 276  *  if the GMAC actually supports the EEE (from the HW cap reg) and the
 277  *  phy can also manage EEE, so enable the LPI state and start the timer
 278  *  to verify if the tx path can enter in LPI state.
 279  */
 280 bool stmmac_eee_init(struct stmmac_priv *priv)
 281 {
 282         bool ret = false;
 283
 284         /* MAC core supports the EEE feature. */
 285         if (priv->dma_cap.eee) {
 286                 /* Check if the PHY supports EEE */
 287                 if (phy_init_eee(priv->phydev, 1))
 288                         goto out;
 289
 290                 priv->eee_active = 1;
 291                 init_timer(&priv->eee_ctrl_timer);
 292                 priv->eee_ctrl_timer.function = stmmac_eee_ctrl_timer;
 293                 priv->eee_ctrl_timer.data = (unsigned long)priv;
 294                 priv->eee_ctrl_timer.expires = STMMAC_LPI_TIMER(eee_timer);
 295                 add_timer(&priv->eee_ctrl_timer);
 296
 297                 priv->hw->mac->set_eee_timer(priv->ioaddr,
 298                                              STMMAC_DEFAULT_LIT_LS_TIMER,
 299                                              priv->tx_lpi_timer);
 300
 301                 pr_info("stmmac: Energy-Efficient Ethernet initialized\n");
 302
 303                 ret = true;
 304         }
 305 out:
 306         return ret;
 307 }
 308
 309 static void stmmac_eee_adjust(struct stmmac_priv *priv)
 310 {
 311         /* When the EEE has been already initialised we have to
 312          * modify the PLS bit in the LPI ctrl & status reg according
 313          * to the PHY link status. For this reason.
 314          */
 315         if (priv->eee_enabled)
 316                 priv->hw->mac->set_eee_pls(priv->ioaddr, priv->phydev->link);
 317 }
 318
 319 /**
 320  * stmmac_adjust_link
 321  * @dev: net device structure
 322  * Description: it adjusts the link parameters.
 323  */
 324 static void stmmac_adjust_link(struct net_device *dev)
 325 {
 326         struct stmmac_priv *priv = netdev_priv(dev);
 327         struct phy_device *phydev = priv->phydev;
 328         unsigned long flags;
 329         int new_state = 0;
 330         unsigned int fc = priv->flow_ctrl, pause_time = priv->pause;
 331
 332         if (phydev == NULL)
 333                 return;
 334
 335         DBG(probe, DEBUG, "stmmac_adjust_link: called.  address %d link %d\n",
 336             phydev->addr, phydev->link);
 337
 338         spin_lock_irqsave(&priv->lock, flags);
 339
 340         if (phydev->link) {
 341                 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
 342
 343                 /* Now we make sure that we can be in full duplex mode.
 344                  * If not, we operate in half-duplex mode. */
 345                 if (phydev->duplex != priv->oldduplex) {
 346                         new_state = 1;
 347                         if (!(phydev->duplex))
 348                                 ctrl &= ~priv->hw->link.duplex;
 349                         else
 350                                 ctrl |= priv->hw->link.duplex;
 351                         priv->oldduplex = phydev->duplex;
 352                 }
 353                 /* Flow Control operation */
 354                 if (phydev->pause)
 355                         priv->hw->mac->flow_ctrl(priv->ioaddr, phydev->duplex,
 356                                                  fc, pause_time);
 357
 358                 if (phydev->speed != priv->speed) {
 359                         new_state = 1;
 360                         switch (phydev->speed) {
 361                         case 1000:
 362                                 if (likely(priv->plat->has_gmac))
 363                                         ctrl &= ~priv->hw->link.port;
 364                                         stmmac_hw_fix_mac_speed(priv);
 365                                 break;
 366                         case 100:
 367                         case 10:
 368                                 if (priv->plat->has_gmac) {
 369                                         ctrl |= priv->hw->link.port;
 370                                         if (phydev->speed == SPEED_100) {
 371                                                 ctrl |= priv->hw->link.speed;
 372                                         } else {
 373                                                 ctrl &= ~(priv->hw->link.speed);
 374                                         }
 375                                 } else {
 376                                         ctrl &= ~priv->hw->link.port;
 377                                 }
 378                                 stmmac_hw_fix_mac_speed(priv);
 379                                 break;
 380                         default:
 381                                 if (netif_msg_link(priv))
 382                                         pr_warning("%s: Speed (%d) is not 10"
 383                                        " or 100!\n", dev->name, phydev->speed);
 384                                 break;
 385                         }
 386
 387                         priv->speed = phydev->speed;
 388                 }
 389
 390                 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
 391
 392                 if (!priv->oldlink) {
 393                         new_state = 1;
 394                         priv->oldlink = 1;
 395                 }
 396         } else if (priv->oldlink) {
 397                 new_state = 1;
 398                 priv->oldlink = 0;
 399                 priv->speed = 0;
 400                 priv->oldduplex = -1;
 401         }
 402
 403         if (new_state && netif_msg_link(priv))
 404                 phy_print_status(phydev);
 405
 406         stmmac_eee_adjust(priv);
 407
 408         spin_unlock_irqrestore(&priv->lock, flags);
 409
 410         DBG(probe, DEBUG, "stmmac_adjust_link: exiting\n");
 411 }
 412
 413 /**
 414  * stmmac_init_phy - PHY initialization
 415  * @dev: net device structure
 416  * Description: it initializes the driver's PHY state, and attaches the PHY
 417  * to the mac driver.
 418  *  Return value:
 419  *  0 on success
 420  */
 421 static int stmmac_init_phy(struct net_device *dev)
 422 {
 423         struct stmmac_priv *priv = netdev_priv(dev);
 424         struct phy_device *phydev;
 425         char phy_id_fmt[MII_BUS_ID_SIZE + 3];
 426         char bus_id[MII_BUS_ID_SIZE];
 427         int interface = priv->plat->interface;
 428         priv->oldlink = 0;
 429         priv->speed = 0;
 430         priv->oldduplex = -1;
 431
 432         if (priv->plat->phy_bus_name)
 433                 snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x",
 434                                 priv->plat->phy_bus_name, priv->plat->bus_id);
 435         else
 436                 snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x",
 437                                 priv->plat->bus_id);
 438
 439         snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
 440                  priv->plat->phy_addr);
 441         pr_debug("stmmac_init_phy:  trying to attach to %s\n", phy_id_fmt);
 442
 443         phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link, 0,
 444                              interface);
 445
 446         if (IS_ERR(phydev)) {
 447                 pr_err("%s: Could not attach to PHY\n", dev->name);
 448                 return PTR_ERR(phydev);
 449         }
 450
 451         /* Stop Advertising 1000BASE Capability if interface is not GMII */
 452         if ((interface == PHY_INTERFACE_MODE_MII) ||
 453             (interface == PHY_INTERFACE_MODE_RMII))
 454                 phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
 455                                          SUPPORTED_1000baseT_Full);
 456
 457         /*
 458          * Broken HW is sometimes missing the pull-up resistor on the
 459          * MDIO line, which results in reads to non-existent devices returning
 460          * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
 461          * device as well.
 462          * Note: phydev->phy_id is the result of reading the UID PHY registers.
 463          */
 464         if (phydev->phy_id == 0) {
 465                 phy_disconnect(phydev);
 466                 return -ENODEV;
 467         }
 468         pr_debug("stmmac_init_phy:  %s: attached to PHY (UID 0x%x)"
 469                  " Link = %d\n", dev->name, phydev->phy_id, phydev->link);
 470
 471         priv->phydev = phydev;
 472
 473         return 0;
 474 }
 475
 476 /**
 477  * display_ring
 478  * @p: pointer to the ring.
 479  * @size: size of the ring.
 480  * Description: display all the descriptors within the ring.
 481  */
 482 static void display_ring(struct dma_desc *p, int size)
 483 {
 484         struct tmp_s {
 485                 u64 a;
 486                 unsigned int b;
 487                 unsigned int c;
 488         };
 489         int i;
 490         for (i = 0; i < size; i++) {
 491                 struct tmp_s *x = (struct tmp_s *)(p + i);
 492                 pr_info("\t%d [0x%x]: DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x",
 493                        i, (unsigned int)virt_to_phys(&p[i]),
 494                        (unsigned int)(x->a), (unsigned int)((x->a) >> 32),
 495                        x->b, x->c);
 496                 pr_info("\n");
 497         }
 498 }
 499
 500 static int stmmac_set_bfsize(int mtu, int bufsize)
 501 {
 502         int ret = bufsize;
 503
 504         if (mtu >= BUF_SIZE_4KiB)
 505                 ret = BUF_SIZE_8KiB;
 506         else if (mtu >= BUF_SIZE_2KiB)
 507                 ret = BUF_SIZE_4KiB;
 508         else if (mtu >= DMA_BUFFER_SIZE)
 509                 ret = BUF_SIZE_2KiB;
 510         else
 511                 ret = DMA_BUFFER_SIZE;
 512
 513         return ret;
 514 }
 515
 516 /**
 517  * init_dma_desc_rings - init the RX/TX descriptor rings
 518  * @dev: net device structure
 519  * Description:  this function initializes the DMA RX/TX descriptors
 520  * and allocates the socket buffers. It suppors the chained and ring
 521  * modes.
 522  */
 523 static void init_dma_desc_rings(struct net_device *dev)
 524 {
 525         int i;
 526         struct stmmac_priv *priv = netdev_priv(dev);
 527         struct sk_buff *skb;
 528         unsigned int txsize = priv->dma_tx_size;
 529         unsigned int rxsize = priv->dma_rx_size;
 530         unsigned int bfsize;
 531         int dis_ic = 0;
 532         int des3_as_data_buf = 0;
 533
 534         /* Set the max buffer size according to the DESC mode
 535          * and the MTU. Note that RING mode allows 16KiB bsize. */
 536         bfsize = priv->hw->ring->set_16kib_bfsize(dev->mtu);
 537
 538         if (bfsize == BUF_SIZE_16KiB)
 539                 des3_as_data_buf = 1;
 540         else
 541                 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
 542
 543 #ifdef CONFIG_STMMAC_TIMER
 544         /* Disable interrupts on completion for the reception if timer is on */
 545         if (likely(priv->tm->enable))
 546                 dis_ic = 1;
 547 #endif
 548
 549         DBG(probe, INFO, "stmmac: txsize %d, rxsize %d, bfsize %d\n",
 550             txsize, rxsize, bfsize);
 551
 552         priv->rx_skbuff_dma = kmalloc(rxsize * sizeof(dma_addr_t), GFP_KERNEL);
 553         priv->rx_skbuff =
 554             kmalloc(sizeof(struct sk_buff *) * rxsize, GFP_KERNEL);
 555         priv->dma_rx =
 556             (struct dma_desc *)dma_alloc_coherent(priv->device,
 557                                                   rxsize *
 558                                                   sizeof(struct dma_desc),
 559                                                   &priv->dma_rx_phy,
 560                                                   GFP_KERNEL);
 561         priv->tx_skbuff = kmalloc(sizeof(struct sk_buff *) * txsize,
 562                                        GFP_KERNEL);
 563         priv->dma_tx =
 564             (struct dma_desc *)dma_alloc_coherent(priv->device,
 565                                                   txsize *
 566                                                   sizeof(struct dma_desc),
 567                                                   &priv->dma_tx_phy,
 568                                                   GFP_KERNEL);
 569
 570         if ((priv->dma_rx == NULL) || (priv->dma_tx == NULL)) {
 571                 pr_err("%s:ERROR allocating the DMA Tx/Rx desc\n", __func__);
 572                 return;
 573         }
 574
 575         DBG(probe, INFO, "stmmac (%s) DMA desc: virt addr (Rx %p, "
 576             "Tx %p)\n\tDMA phy addr (Rx 0x%08x, Tx 0x%08x)\n",
 577             dev->name, priv->dma_rx, priv->dma_tx,
 578             (unsigned int)priv->dma_rx_phy, (unsigned int)priv->dma_tx_phy);
 579
 580         /* RX INITIALIZATION */
 581         DBG(probe, INFO, "stmmac: SKB addresses:\n"
 582                          "skb\t\tskb data\tdma data\n");
 583
 584         for (i = 0; i < rxsize; i++) {
 585                 struct dma_desc *p = priv->dma_rx + i;
 586
 587                 skb = __netdev_alloc_skb(dev, bfsize + NET_IP_ALIGN,
 588                                          GFP_KERNEL);
 589                 if (unlikely(skb == NULL)) {
 590                         pr_err("%s: Rx init fails; skb is NULL\n", __func__);
 591                         break;
 592                 }
 593                 skb_reserve(skb, NET_IP_ALIGN);
 594                 priv->rx_skbuff[i] = skb;
 595                 priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
 596                                                 bfsize, DMA_FROM_DEVICE);
 597
 598                 p->des2 = priv->rx_skbuff_dma[i];
 599
 600                 priv->hw->ring->init_desc3(des3_as_data_buf, p);
 601
 602                 DBG(probe, INFO, "[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i],
 603                         priv->rx_skbuff[i]->data, priv->rx_skbuff_dma[i]);
 604         }
 605         priv->cur_rx = 0;
 606         priv->dirty_rx = (unsigned int)(i - rxsize);
 607         priv->dma_buf_sz = bfsize;
 608         buf_sz = bfsize;
 609
 610         /* TX INITIALIZATION */
 611         for (i = 0; i < txsize; i++) {
 612                 priv->tx_skbuff[i] = NULL;
 613                 priv->dma_tx[i].des2 = 0;
 614         }
 615
 616         /* In case of Chained mode this sets the des3 to the next
 617          * element in the chain */
 618         priv->hw->ring->init_dma_chain(priv->dma_rx, priv->dma_rx_phy, rxsize);
 619         priv->hw->ring->init_dma_chain(priv->dma_tx, priv->dma_tx_phy, txsize);
 620
 621         priv->dirty_tx = 0;
 622         priv->cur_tx = 0;
 623
 624         /* Clear the Rx/Tx descriptors */
 625         priv->hw->desc->init_rx_desc(priv->dma_rx, rxsize, dis_ic);
 626         priv->hw->desc->init_tx_desc(priv->dma_tx, txsize);
 627
 628         if (netif_msg_hw(priv)) {
 629                 pr_info("RX descriptor ring:\n");
 630                 display_ring(priv->dma_rx, rxsize);
 631                 pr_info("TX descriptor ring:\n");
 632                 display_ring(priv->dma_tx, txsize);
 633         }
 634 }
 635
 636 static void dma_free_rx_skbufs(struct stmmac_priv *priv)
 637 {
 638         int i;
 639
 640         for (i = 0; i < priv->dma_rx_size; i++) {
 641                 if (priv->rx_skbuff[i]) {
 642                         dma_unmap_single(priv->device, priv->rx_skbuff_dma[i],
 643                                          priv->dma_buf_sz, DMA_FROM_DEVICE);
 644                         dev_kfree_skb_any(priv->rx_skbuff[i]);
 645                 }
 646                 priv->rx_skbuff[i] = NULL;
 647         }
 648 }
 649
 650 static void dma_free_tx_skbufs(struct stmmac_priv *priv)
 651 {
 652         int i;
 653
 654         for (i = 0; i < priv->dma_tx_size; i++) {
 655                 if (priv->tx_skbuff[i] != NULL) {
 656                         struct dma_desc *p = priv->dma_tx + i;
 657                         if (p->des2)
 658                                 dma_unmap_single(priv->device, p->des2,
 659                                                  priv->hw->desc->get_tx_len(p),
 660                                                  DMA_TO_DEVICE);
 661                         dev_kfree_skb_any(priv->tx_skbuff[i]);
 662                         priv->tx_skbuff[i] = NULL;
 663                 }
 664         }
 665 }
 666
 667 static void free_dma_desc_resources(struct stmmac_priv *priv)
 668 {
 669         /* Release the DMA TX/RX socket buffers */
 670         dma_free_rx_skbufs(priv);
 671         dma_free_tx_skbufs(priv);
 672
 673         /* Free the region of consistent memory previously allocated for
 674          * the DMA */
 675         dma_free_coherent(priv->device,
 676                           priv->dma_tx_size * sizeof(struct dma_desc),
 677                           priv->dma_tx, priv->dma_tx_phy);
 678         dma_free_coherent(priv->device,
 679                           priv->dma_rx_size * sizeof(struct dma_desc),
 680                           priv->dma_rx, priv->dma_rx_phy);
 681         kfree(priv->rx_skbuff_dma);
 682         kfree(priv->rx_skbuff);
 683         kfree(priv->tx_skbuff);
 684 }
 685
 686 /**
 687  *  stmmac_dma_operation_mode - HW DMA operation mode
 688  *  @priv : pointer to the private device structure.
 689  *  Description: it sets the DMA operation mode: tx/rx DMA thresholds
 690  *  or Store-And-Forward capability.
 691  */
 692 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
 693 {
 694         if (likely(priv->plat->force_sf_dma_mode ||
 695                 ((priv->plat->tx_coe) && (!priv->no_csum_insertion)))) {
 696                 /*
 697                  * In case of GMAC, SF mode can be enabled
 698                  * to perform the TX COE in HW. This depends on:
 699                  * 1) TX COE if actually supported
 700                  * 2) There is no bugged Jumbo frame support
 701                  *    that needs to not insert csum in the TDES.
 702                  */
 703                 priv->hw->dma->dma_mode(priv->ioaddr,
 704                                         SF_DMA_MODE, SF_DMA_MODE);
 705                 tc = SF_DMA_MODE;
 706         } else
 707                 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
 708 }
 709
 710 /**
 711  * stmmac_tx:
 712  * @priv: private driver structure
 713  * Description: it reclaims resources after transmission completes.
 714  */
 715 static void stmmac_tx(struct stmmac_priv *priv)
 716 {
 717         unsigned int txsize = priv->dma_tx_size;
 718
 719         spin_lock(&priv->tx_lock);
 720
 721         while (priv->dirty_tx != priv->cur_tx) {
 722                 int last;
 723                 unsigned int entry = priv->dirty_tx % txsize;
 724                 struct sk_buff *skb = priv->tx_skbuff[entry];
 725                 struct dma_desc *p = priv->dma_tx + entry;
 726
 727                 /* Check if the descriptor is owned by the DMA. */
 728                 if (priv->hw->desc->get_tx_owner(p))
 729                         break;
 730
 731                 /* Verify tx error by looking at the last segment */
 732                 last = priv->hw->desc->get_tx_ls(p);
 733                 if (likely(last)) {
 734                         int tx_error =
 735                                 priv->hw->desc->tx_status(&priv->dev->stats,
 736                                                           &priv->xstats, p,
 737                                                           priv->ioaddr);
 738                         if (likely(tx_error == 0)) {
 739                                 priv->dev->stats.tx_packets++;
 740                                 priv->xstats.tx_pkt_n++;
 741                         } else
 742                                 priv->dev->stats.tx_errors++;
 743                 }
 744                 TX_DBG("%s: curr %d, dirty %d\n", __func__,
 745                         priv->cur_tx, priv->dirty_tx);
 746
 747                 if (likely(p->des2))
 748                         dma_unmap_single(priv->device, p->des2,
 749                                          priv->hw->desc->get_tx_len(p),
 750                                          DMA_TO_DEVICE);
 751                 priv->hw->ring->clean_desc3(p);
 752
 753                 if (likely(skb != NULL)) {
 754                         /*
 755                          * If there's room in the queue (limit it to size)
 756                          * we add this skb back into the pool,
 757                          * if it's the right size.
 758                          */
 759                         if ((skb_queue_len(&priv->rx_recycle) <
 760                                 priv->dma_rx_size) &&
 761                                 skb_recycle_check(skb, priv->dma_buf_sz))
 762                                 __skb_queue_head(&priv->rx_recycle, skb);
 763                         else
 764                                 dev_kfree_skb(skb);
 765
 766                         priv->tx_skbuff[entry] = NULL;
 767                 }
 768
 769                 priv->hw->desc->release_tx_desc(p);
 770
 771                 priv->dirty_tx++;
 772         }
 773         if (unlikely(netif_queue_stopped(priv->dev) &&
 774                      stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) {
 775                 netif_tx_lock(priv->dev);
 776                 if (netif_queue_stopped(priv->dev) &&
 777                      stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) {
 778                         TX_DBG("%s: restart transmit\n", __func__);
 779                         netif_wake_queue(priv->dev);
 780                 }
 781                 netif_tx_unlock(priv->dev);
 782         }
 783
 784         if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
 785                 stmmac_enable_eee_mode(priv);
 786                 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_TIMER(eee_timer));
 787         }
 788         spin_unlock(&priv->tx_lock);
 789 }
 790
 791 static inline void stmmac_enable_irq(struct stmmac_priv *priv)
 792 {
 793 #ifdef CONFIG_STMMAC_TIMER
 794         if (likely(priv->tm->enable))
 795                 priv->tm->timer_start(tmrate);
 796         else
 797 #endif
 798                 priv->hw->dma->enable_dma_irq(priv->ioaddr);
 799 }
 800
 801 static inline void stmmac_disable_irq(struct stmmac_priv *priv)
 802 {
 803 #ifdef CONFIG_STMMAC_TIMER
 804         if (likely(priv->tm->enable))
 805                 priv->tm->timer_stop();
 806         else
 807 #endif
 808                 priv->hw->dma->disable_dma_irq(priv->ioaddr);
 809 }
 810
 811 static int stmmac_has_work(struct stmmac_priv *priv)
 812 {
 813         unsigned int has_work = 0;
 814         int rxret, tx_work = 0;
 815
 816         rxret = priv->hw->desc->get_rx_owner(priv->dma_rx +
 817                 (priv->cur_rx % priv->dma_rx_size));
 818
 819         if (priv->dirty_tx != priv->cur_tx)
 820                 tx_work = 1;
 821
 822         if (likely(!rxret || tx_work))
 823                 has_work = 1;
 824
 825         return has_work;
 826 }
 827
 828 static inline void _stmmac_schedule(struct stmmac_priv *priv)
 829 {
 830         if (likely(stmmac_has_work(priv))) {
 831                 stmmac_disable_irq(priv);
 832                 napi_schedule(&priv->napi);
 833         }
 834 }
 835
 836 #ifdef CONFIG_STMMAC_TIMER
 837 void stmmac_schedule(struct net_device *dev)
 838 {
 839         struct stmmac_priv *priv = netdev_priv(dev);
 840
 841         priv->xstats.sched_timer_n++;
 842
 843         _stmmac_schedule(priv);
 844 }
 845
 846 static void stmmac_no_timer_started(unsigned int x)
 847 {;
 848 };
 849
 850 static void stmmac_no_timer_stopped(void)
 851 {;
 852 };
 853 #endif
 854
 855 /**
 856  * stmmac_tx_err:
 857  * @priv: pointer to the private device structure
 858  * Description: it cleans the descriptors and restarts the transmission
 859  * in case of errors.
 860  */
 861 static void stmmac_tx_err(struct stmmac_priv *priv)
 862 {
 863         netif_stop_queue(priv->dev);
 864
 865         priv->hw->dma->stop_tx(priv->ioaddr);
 866         dma_free_tx_skbufs(priv);
 867         priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size);
 868         priv->dirty_tx = 0;
 869         priv->cur_tx = 0;
 870         priv->hw->dma->start_tx(priv->ioaddr);
 871
 872         priv->dev->stats.tx_errors++;
 873         netif_wake_queue(priv->dev);
 874 }
 875
 876
 877 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
 878 {
 879         int status;
 880
 881         status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats);
 882         if (likely(status == handle_tx_rx))
 883                 _stmmac_schedule(priv);
 884
 885         else if (unlikely(status == tx_hard_error_bump_tc)) {
 886                 /* Try to bump up the dma threshold on this failure */
 887                 if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) {
 888                         tc += 64;
 889                         priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
 890                         priv->xstats.threshold = tc;
 891                 }
 892         } else if (unlikely(status == tx_hard_error))
 893                 stmmac_tx_err(priv);
 894 }
 895
 896 static void stmmac_mmc_setup(struct stmmac_priv *priv)
 897 {
 898         unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
 899                             MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
 900
 901         /* Mask MMC irq, counters are managed in SW and registers
 902          * are cleared on each READ eventually. */
 903         dwmac_mmc_intr_all_mask(priv->ioaddr);
 904
 905         if (priv->dma_cap.rmon) {
 906                 dwmac_mmc_ctrl(priv->ioaddr, mode);
 907                 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
 908         } else
 909                 pr_info(" No MAC Management Counters available\n");
 910 }
 911
 912 static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv)
 913 {
 914         u32 hwid = priv->hw->synopsys_uid;
 915
 916         /* Only check valid Synopsys Id because old MAC chips
 917          * have no HW registers where get the ID */
 918         if (likely(hwid)) {
 919                 u32 uid = ((hwid & 0x0000ff00) >> 8);
 920                 u32 synid = (hwid & 0x000000ff);
 921
 922                 pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n",
 923                         uid, synid);
 924
 925                 return synid;
 926         }
 927         return 0;
 928 }
 929
 930 /**
 931  * stmmac_selec_desc_mode
 932  * @priv : private structure
 933  * Description: select the Enhanced/Alternate or Normal descriptors
 934  */
 935 static void stmmac_selec_desc_mode(struct stmmac_priv *priv)
 936 {
 937         if (priv->plat->enh_desc) {
 938                 pr_info(" Enhanced/Alternate descriptors\n");
 939                 priv->hw->desc = &enh_desc_ops;
 940         } else {
 941                 pr_info(" Normal descriptors\n");
 942                 priv->hw->desc = &ndesc_ops;
 943         }
 944 }
 945
 946 /**
 947  * stmmac_get_hw_features
 948  * @priv : private device pointer
 949  * Description:
 950  *  new GMAC chip generations have a new register to indicate the
 951  *  presence of the optional feature/functions.
 952  *  This can be also used to override the value passed through the
 953  *  platform and necessary for old MAC10/100 and GMAC chips.
 954  */
 955 static int stmmac_get_hw_features(struct stmmac_priv *priv)
 956 {
 957         u32 hw_cap = 0;
 958
 959         if (priv->hw->dma->get_hw_feature) {
 960                 hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr);
 961
 962                 priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL);
 963                 priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1;
 964                 priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2;
 965                 priv->dma_cap.hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4;
 966                 priv->dma_cap.multi_addr =
 967                         (hw_cap & DMA_HW_FEAT_ADDMACADRSEL) >> 5;
 968                 priv->dma_cap.pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6;
 969                 priv->dma_cap.sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8;
 970                 priv->dma_cap.pmt_remote_wake_up =
 971                         (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9;
 972                 priv->dma_cap.pmt_magic_frame =
 973                         (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10;
 974                 /* MMC */
 975                 priv->dma_cap.rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11;
 976                 /* IEEE 1588-2002*/
 977                 priv->dma_cap.time_stamp =
 978                         (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12;
 979                 /* IEEE 1588-2008*/
 980                 priv->dma_cap.atime_stamp =
 981                         (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13;
 982                 /* 802.3az - Energy-Efficient Ethernet (EEE) */
 983                 priv->dma_cap.eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14;
 984                 priv->dma_cap.av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15;
 985                 /* TX and RX csum */
 986                 priv->dma_cap.tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16;
 987                 priv->dma_cap.rx_coe_type1 =
 988                         (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17;
 989                 priv->dma_cap.rx_coe_type2 =
 990                         (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18;
 991                 priv->dma_cap.rxfifo_over_2048 =
 992                         (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19;
 993                 /* TX and RX number of channels */
 994                 priv->dma_cap.number_rx_channel =
 995                         (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20;
 996                 priv->dma_cap.number_tx_channel =
 997                         (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22;
 998                 /* Alternate (enhanced) DESC mode*/
 999                 priv->dma_cap.enh_desc =
1000                         (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24;
1001
1002         }
1003
1004         return hw_cap;
1005 }
1006
1007 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
1008 {
1009         /* verify if the MAC address is valid, in case of failures it
1010          * generates a random MAC address */
1011         if (!is_valid_ether_addr(priv->dev->dev_addr)) {
1012                 priv->hw->mac->get_umac_addr((void __iomem *)
1013                                              priv->dev->base_addr,
1014                                              priv->dev->dev_addr, 0);
1015                 if  (!is_valid_ether_addr(priv->dev->dev_addr))
1016                         eth_hw_addr_random(priv->dev);
1017         }
1018         pr_warning("%s: device MAC address %pM\n", priv->dev->name,
1019                                                    priv->dev->dev_addr);
1020 }
1021
1022 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
1023 {
1024         int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, burst_len = 0;
1025         int mixed_burst = 0;
1026
1027         /* Some DMA parameters can be passed from the platform;
1028          * in case of these are not passed we keep a default
1029          * (good for all the chips) and init the DMA! */
1030         if (priv->plat->dma_cfg) {
1031                 pbl = priv->plat->dma_cfg->pbl;
1032                 fixed_burst = priv->plat->dma_cfg->fixed_burst;
1033                 mixed_burst = priv->plat->dma_cfg->mixed_burst;
1034                 burst_len = priv->plat->dma_cfg->burst_len;
1035         }
1036
1037         return priv->hw->dma->init(priv->ioaddr, pbl, fixed_burst, mixed_burst,
1038                                    burst_len, priv->dma_tx_phy,
1039                                    priv->dma_rx_phy);
1040 }
1041
1042 /**
1043  *  stmmac_open - open entry point of the driver
1044  *  @dev : pointer to the device structure.
1045  *  Description:
1046  *  This function is the open entry point of the driver.
1047  *  Return value:
1048  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1049  *  file on failure.
1050  */
1051 static int stmmac_open(struct net_device *dev)
1052 {
1053         struct stmmac_priv *priv = netdev_priv(dev);
1054         int ret;
1055
1056 #ifdef CONFIG_STMMAC_TIMER
1057         priv->tm = kzalloc(sizeof(struct stmmac_timer *), GFP_KERNEL);
1058         if (unlikely(priv->tm == NULL))
1059                 return -ENOMEM;
1060
1061         priv->tm->freq = tmrate;
1062
1063         /* Test if the external timer can be actually used.
1064          * In case of failure continue without timer. */
1065         if (unlikely((stmmac_open_ext_timer(dev, priv->tm)) < 0)) {
1066                 pr_warning("stmmaceth: cannot attach the external timer.\n");
1067                 priv->tm->freq = 0;
1068                 priv->tm->timer_start = stmmac_no_timer_started;
1069                 priv->tm->timer_stop = stmmac_no_timer_stopped;
1070         } else
1071                 priv->tm->enable = 1;
1072 #endif
1073         stmmac_clk_enable(priv);
1074
1075         stmmac_check_ether_addr(priv);
1076
1077         ret = stmmac_init_phy(dev);
1078         if (unlikely(ret)) {
1079                 pr_err("%s: Cannot attach to PHY (error: %d)\n", __func__, ret);
1080                 goto open_error;
1081         }
1082
1083         /* Create and initialize the TX/RX descriptors chains. */
1084         priv->dma_tx_size = STMMAC_ALIGN(dma_txsize);
1085         priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize);
1086         priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
1087         init_dma_desc_rings(dev);
1088
1089         /* DMA initialization and SW reset */
1090         ret = stmmac_init_dma_engine(priv);
1091         if (ret < 0) {
1092                 pr_err("%s: DMA initialization failed\n", __func__);
1093                 goto open_error;
1094         }
1095
1096         /* Copy the MAC addr into the HW  */
1097         priv->hw->mac->set_umac_addr(priv->ioaddr, dev->dev_addr, 0);
1098
1099         /* If required, perform hw setup of the bus. */
1100         if (priv->plat->bus_setup)
1101                 priv->plat->bus_setup(priv->ioaddr);
1102
1103         /* Initialize the MAC Core */
1104         priv->hw->mac->core_init(priv->ioaddr);
1105
1106         /* Request the IRQ lines */
1107         ret = request_irq(dev->irq, stmmac_interrupt,
1108                          IRQF_SHARED, dev->name, dev);
1109         if (unlikely(ret < 0)) {
1110                 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
1111                        __func__, dev->irq, ret);
1112                 goto open_error;
1113         }
1114
1115         /* Request the Wake IRQ in case of another line is used for WoL */
1116         if (priv->wol_irq != dev->irq) {
1117                 ret = request_irq(priv->wol_irq, stmmac_interrupt,
1118                                   IRQF_SHARED, dev->name, dev);
1119                 if (unlikely(ret < 0)) {
1120                         pr_err("%s: ERROR: allocating the ext WoL IRQ %d "
1121                                "(error: %d)\n", __func__, priv->wol_irq, ret);
1122                         goto open_error_wolirq;
1123                 }
1124         }
1125
1126         /* Request the IRQ lines */
1127         if (priv->lpi_irq != -ENXIO) {
1128                 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
1129                                   dev->name, dev);
1130                 if (unlikely(ret < 0)) {
1131                         pr_err("%s: ERROR: allocating the LPI IRQ %d (%d)\n",
1132                                __func__, priv->lpi_irq, ret);
1133                         goto open_error_lpiirq;
1134                 }
1135         }
1136
1137         /* Enable the MAC Rx/Tx */
1138         stmmac_set_mac(priv->ioaddr, true);
1139
1140         /* Set the HW DMA mode and the COE */
1141         stmmac_dma_operation_mode(priv);
1142
1143         /* Extra statistics */
1144         memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
1145         priv->xstats.threshold = tc;
1146
1147         stmmac_mmc_setup(priv);
1148
1149 #ifdef CONFIG_STMMAC_DEBUG_FS
1150         ret = stmmac_init_fs(dev);
1151         if (ret < 0)
1152                 pr_warning("%s: failed debugFS registration\n", __func__);
1153 #endif
1154         /* Start the ball rolling... */
1155         DBG(probe, DEBUG, "%s: DMA RX/TX processes started...\n", dev->name);
1156         priv->hw->dma->start_tx(priv->ioaddr);
1157         priv->hw->dma->start_rx(priv->ioaddr);
1158
1159 #ifdef CONFIG_STMMAC_TIMER
1160         priv->tm->timer_start(tmrate);
1161 #endif
1162
1163         /* Dump DMA/MAC registers */
1164         if (netif_msg_hw(priv)) {
1165                 priv->hw->mac->dump_regs(priv->ioaddr);
1166                 priv->hw->dma->dump_regs(priv->ioaddr);
1167         }
1168
1169         if (priv->phydev)
1170                 phy_start(priv->phydev);
1171
1172         priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS_TIMER;
1173         priv->eee_enabled = stmmac_eee_init(priv);
1174
1175         napi_enable(&priv->napi);
1176         skb_queue_head_init(&priv->rx_recycle);
1177         netif_start_queue(dev);
1178
1179         return 0;
1180
1181 open_error_lpiirq:
1182         if (priv->wol_irq != dev->irq)
1183                 free_irq(priv->wol_irq, dev);
1184
1185 open_error_wolirq:
1186         free_irq(dev->irq, dev);
1187
1188 open_error:
1189 #ifdef CONFIG_STMMAC_TIMER
1190         kfree(priv->tm);
1191 #endif
1192         if (priv->phydev)
1193                 phy_disconnect(priv->phydev);
1194
1195         stmmac_clk_disable(priv);
1196
1197         return ret;
1198 }
1199
1200 /**
1201  *  stmmac_release - close entry point of the driver
1202  *  @dev : device pointer.
1203  *  Description:
1204  *  This is the stop entry point of the driver.
1205  */
1206 static int stmmac_release(struct net_device *dev)
1207 {
1208         struct stmmac_priv *priv = netdev_priv(dev);
1209
1210         if (priv->eee_enabled)
1211                 del_timer_sync(&priv->eee_ctrl_timer);
1212
1213         /* Stop and disconnect the PHY */
1214         if (priv->phydev) {
1215                 phy_stop(priv->phydev);
1216                 phy_disconnect(priv->phydev);
1217                 priv->phydev = NULL;
1218         }
1219
1220         netif_stop_queue(dev);
1221
1222 #ifdef CONFIG_STMMAC_TIMER
1223         /* Stop and release the timer */
1224         stmmac_close_ext_timer();
1225         if (priv->tm != NULL)
1226                 kfree(priv->tm);
1227 #endif
1228         napi_disable(&priv->napi);
1229         skb_queue_purge(&priv->rx_recycle);
1230
1231         /* Free the IRQ lines */
1232         free_irq(dev->irq, dev);
1233         if (priv->wol_irq != dev->irq)
1234                 free_irq(priv->wol_irq, dev);
1235         if (priv->lpi_irq != -ENXIO)
1236                 free_irq(priv->lpi_irq, dev);
1237
1238         /* Stop TX/RX DMA and clear the descriptors */
1239         priv->hw->dma->stop_tx(priv->ioaddr);
1240         priv->hw->dma->stop_rx(priv->ioaddr);
1241
1242         /* Release and free the Rx/Tx resources */
1243         free_dma_desc_resources(priv);
1244
1245         /* Disable the MAC Rx/Tx */
1246         stmmac_set_mac(priv->ioaddr, false);
1247
1248         netif_carrier_off(dev);
1249
1250 #ifdef CONFIG_STMMAC_DEBUG_FS
1251         stmmac_exit_fs();
1252 #endif
1253         stmmac_clk_disable(priv);
1254
1255         return 0;
1256 }
1257
1258 /**
1259  *  stmmac_xmit:
1260  *  @skb : the socket buffer
1261  *  @dev : device pointer
1262  *  Description : Tx entry point of the driver.
1263  */
1264 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
1265 {
1266         struct stmmac_priv *priv = netdev_priv(dev);
1267         unsigned int txsize = priv->dma_tx_size;
1268         unsigned int entry;
1269         int i, csum_insertion = 0;
1270         int nfrags = skb_shinfo(skb)->nr_frags;
1271         struct dma_desc *desc, *first;
1272         unsigned int nopaged_len = skb_headlen(skb);
1273
1274         if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) {
1275                 if (!netif_queue_stopped(dev)) {
1276                         netif_stop_queue(dev);
1277                         /* This is a hard error, log it. */
1278                         pr_err("%s: BUG! Tx Ring full when queue awake\n",
1279                                 __func__);
1280                 }
1281                 return NETDEV_TX_BUSY;
1282         }
1283
1284         spin_lock(&priv->tx_lock);
1285
1286         if (priv->tx_path_in_lpi_mode)
1287                 stmmac_disable_eee_mode(priv);
1288
1289         entry = priv->cur_tx % txsize;
1290
1291 #ifdef STMMAC_XMIT_DEBUG
1292         if ((skb->len > ETH_FRAME_LEN) || nfrags)
1293                 pr_info("stmmac xmit:\n"
1294                        "\tskb addr %p - len: %d - nopaged_len: %d\n"
1295                        "\tn_frags: %d - ip_summed: %d - %s gso\n",
1296                        skb, skb->len, nopaged_len, nfrags, skb->ip_summed,
1297                        !skb_is_gso(skb) ? "isn't" : "is");
1298 #endif
1299
1300         csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
1301
1302         desc = priv->dma_tx + entry;
1303         first = desc;
1304
1305 #ifdef STMMAC_XMIT_DEBUG
1306         if ((nfrags > 0) || (skb->len > ETH_FRAME_LEN))
1307                 pr_debug("stmmac xmit: skb len: %d, nopaged_len: %d,\n"
1308                        "\t\tn_frags: %d, ip_summed: %d\n",
1309                        skb->len, nopaged_len, nfrags, skb->ip_summed);
1310 #endif
1311         priv->tx_skbuff[entry] = skb;
1312
1313         if (priv->hw->ring->is_jumbo_frm(skb->len, priv->plat->enh_desc)) {
1314                 entry = priv->hw->ring->jumbo_frm(priv, skb, csum_insertion);
1315                 desc = priv->dma_tx + entry;
1316         } else {
1317                 desc->des2 = dma_map_single(priv->device, skb->data,
1318                                         nopaged_len, DMA_TO_DEVICE);
1319                 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len,
1320                                                 csum_insertion);
1321         }
1322
1323         for (i = 0; i < nfrags; i++) {
1324                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1325                 int len = skb_frag_size(frag);
1326
1327                 entry = (++priv->cur_tx) % txsize;
1328                 desc = priv->dma_tx + entry;
1329
1330                 TX_DBG("\t[entry %d] segment len: %d\n", entry, len);
1331                 desc->des2 = skb_frag_dma_map(priv->device, frag, 0, len,
1332                                               DMA_TO_DEVICE);
1333                 priv->tx_skbuff[entry] = NULL;
1334                 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion);
1335                 wmb();
1336                 priv->hw->desc->set_tx_owner(desc);
1337                 wmb();
1338         }
1339
1340         /* Interrupt on completition only for the latest segment */
1341         priv->hw->desc->close_tx_desc(desc);
1342
1343 #ifdef CONFIG_STMMAC_TIMER
1344         /* Clean IC while using timer */
1345         if (likely(priv->tm->enable))
1346                 priv->hw->desc->clear_tx_ic(desc);
1347 #endif
1348
1349         wmb();
1350
1351         /* To avoid raise condition */
1352         priv->hw->desc->set_tx_owner(first);
1353         wmb();
1354
1355         priv->cur_tx++;
1356
1357 #ifdef STMMAC_XMIT_DEBUG
1358         if (netif_msg_pktdata(priv)) {
1359                 pr_info("stmmac xmit: current=%d, dirty=%d, entry=%d, "
1360                        "first=%p, nfrags=%d\n",
1361                        (priv->cur_tx % txsize), (priv->dirty_tx % txsize),
1362                        entry, first, nfrags);
1363                 display_ring(priv->dma_tx, txsize);
1364                 pr_info(">>> frame to be transmitted: ");
1365                 print_pkt(skb->data, skb->len);
1366         }
1367 #endif
1368         if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
1369                 TX_DBG("%s: stop transmitted packets\n", __func__);
1370                 netif_stop_queue(dev);
1371         }
1372
1373         dev->stats.tx_bytes += skb->len;
1374
1375         skb_tx_timestamp(skb);
1376
1377         priv->hw->dma->enable_dma_transmission(priv->ioaddr);
1378
1379         spin_unlock(&priv->tx_lock);
1380
1381         return NETDEV_TX_OK;
1382 }
1383
1384 static inline void stmmac_rx_refill(struct stmmac_priv *priv)
1385 {
1386         unsigned int rxsize = priv->dma_rx_size;
1387         int bfsize = priv->dma_buf_sz;
1388         struct dma_desc *p = priv->dma_rx;
1389
1390         for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) {
1391                 unsigned int entry = priv->dirty_rx % rxsize;
1392                 if (likely(priv->rx_skbuff[entry] == NULL)) {
1393                         struct sk_buff *skb;
1394
1395                         skb = __skb_dequeue(&priv->rx_recycle);
1396                         if (skb == NULL)
1397                                 skb = netdev_alloc_skb_ip_align(priv->dev,
1398                                                                 bfsize);
1399
1400                         if (unlikely(skb == NULL))
1401                                 break;
1402
1403                         priv->rx_skbuff[entry] = skb;
1404                         priv->rx_skbuff_dma[entry] =
1405                             dma_map_single(priv->device, skb->data, bfsize,
1406                                            DMA_FROM_DEVICE);
1407
1408                         (p + entry)->des2 = priv->rx_skbuff_dma[entry];
1409
1410                         if (unlikely(priv->plat->has_gmac))
1411                                 priv->hw->ring->refill_desc3(bfsize, p + entry);
1412
1413                         RX_DBG(KERN_INFO "\trefill entry #%d\n", entry);
1414                 }
1415                 wmb();
1416                 priv->hw->desc->set_rx_owner(p + entry);
1417                 wmb();
1418         }
1419 }
1420
1421 static int stmmac_rx(struct stmmac_priv *priv, int limit)
1422 {
1423         unsigned int rxsize = priv->dma_rx_size;
1424         unsigned int entry = priv->cur_rx % rxsize;
1425         unsigned int next_entry;
1426         unsigned int count = 0;
1427         struct dma_desc *p = priv->dma_rx + entry;
1428         struct dma_desc *p_next;
1429
1430 #ifdef STMMAC_RX_DEBUG
1431         if (netif_msg_hw(priv)) {
1432                 pr_debug(">>> stmmac_rx: descriptor ring:\n");
1433                 display_ring(priv->dma_rx, rxsize);
1434         }
1435 #endif
1436         while (!priv->hw->desc->get_rx_owner(p)) {
1437                 int status;
1438
1439                 if (count >= limit)
1440                         break;
1441
1442                 count++;
1443
1444                 next_entry = (++priv->cur_rx) % rxsize;
1445                 p_next = priv->dma_rx + next_entry;
1446                 prefetch(p_next);
1447
1448                 /* read the status of the incoming frame */
1449                 status = (priv->hw->desc->rx_status(&priv->dev->stats,
1450                                                     &priv->xstats, p));
1451                 if (unlikely(status == discard_frame))
1452                         priv->dev->stats.rx_errors++;
1453                 else {
1454                         struct sk_buff *skb;
1455                         int frame_len;
1456
1457                         frame_len = priv->hw->desc->get_rx_frame_len(p,
1458                                         priv->plat->rx_coe);
1459                         /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
1460                          * Type frames (LLC/LLC-SNAP) */
1461                         if (unlikely(status != llc_snap))
1462                                 frame_len -= ETH_FCS_LEN;
1463 #ifdef STMMAC_RX_DEBUG
1464                         if (frame_len > ETH_FRAME_LEN)
1465                                 pr_debug("\tRX frame size %d, COE status: %d\n",
1466                                         frame_len, status);
1467
1468                         if (netif_msg_hw(priv))
1469                                 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n",
1470                                         p, entry, p->des2);
1471 #endif
1472                         skb = priv->rx_skbuff[entry];
1473                         if (unlikely(!skb)) {
1474                                 pr_err("%s: Inconsistent Rx descriptor chain\n",
1475                                         priv->dev->name);
1476                                 priv->dev->stats.rx_dropped++;
1477                                 break;
1478                         }
1479                         prefetch(skb->data - NET_IP_ALIGN);
1480                         priv->rx_skbuff[entry] = NULL;
1481
1482                         skb_put(skb, frame_len);
1483                         dma_unmap_single(priv->device,
1484                                          priv->rx_skbuff_dma[entry],
1485                                          priv->dma_buf_sz, DMA_FROM_DEVICE);
1486 #ifdef STMMAC_RX_DEBUG
1487                         if (netif_msg_pktdata(priv)) {
1488                                 pr_info(" frame received (%dbytes)", frame_len);
1489                                 print_pkt(skb->data, frame_len);
1490                         }
1491 #endif
1492                         skb->protocol = eth_type_trans(skb, priv->dev);
1493
1494                         if (unlikely(!priv->plat->rx_coe)) {
1495                                 /* No RX COE for old mac10/100 devices */
1496                                 skb_checksum_none_assert(skb);
1497                                 netif_receive_skb(skb);
1498                         } else {
1499                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1500                                 napi_gro_receive(&priv->napi, skb);
1501                         }
1502
1503                         priv->dev->stats.rx_packets++;
1504                         priv->dev->stats.rx_bytes += frame_len;
1505                 }
1506                 entry = next_entry;
1507                 p = p_next;     /* use prefetched values */
1508         }
1509
1510         stmmac_rx_refill(priv);
1511
1512         priv->xstats.rx_pkt_n += count;
1513
1514         return count;
1515 }
1516
1517 /**
1518  *  stmmac_poll - stmmac poll method (NAPI)
1519  *  @napi : pointer to the napi structure.
1520  *  @budget : maximum number of packets that the current CPU can receive from
1521  *            all interfaces.
1522  *  Description :
1523  *   This function implements the the reception process.
1524  *   Also it runs the TX completion thread
1525  */
1526 static int stmmac_poll(struct napi_struct *napi, int budget)
1527 {
1528         struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi);
1529         int work_done = 0;
1530
1531         priv->xstats.poll_n++;
1532         stmmac_tx(priv);
1533         work_done = stmmac_rx(priv, budget);
1534
1535         if (work_done < budget) {
1536                 napi_complete(napi);
1537                 stmmac_enable_irq(priv);
1538         }
1539         return work_done;
1540 }
1541
1542 /**
1543  *  stmmac_tx_timeout
1544  *  @dev : Pointer to net device structure
1545  *  Description: this function is called when a packet transmission fails to
1546  *   complete within a reasonable tmrate. The driver will mark the error in the
1547  *   netdev structure and arrange for the device to be reset to a sane state
1548  *   in order to transmit a new packet.
1549  */
1550 static void stmmac_tx_timeout(struct net_device *dev)
1551 {
1552         struct stmmac_priv *priv = netdev_priv(dev);
1553
1554         /* Clear Tx resources and restart transmitting again */
1555         stmmac_tx_err(priv);
1556 }
1557
1558 /* Configuration changes (passed on by ifconfig) */
1559 static int stmmac_config(struct net_device *dev, struct ifmap *map)
1560 {
1561         if (dev->flags & IFF_UP)        /* can't act on a running interface */
1562                 return -EBUSY;
1563
1564         /* Don't allow changing the I/O address */
1565         if (map->base_addr != dev->base_addr) {
1566                 pr_warning("%s: can't change I/O address\n", dev->name);
1567                 return -EOPNOTSUPP;
1568         }
1569
1570         /* Don't allow changing the IRQ */
1571         if (map->irq != dev->irq) {
1572                 pr_warning("%s: can't change IRQ number %d\n",
1573                        dev->name, dev->irq);
1574                 return -EOPNOTSUPP;
1575         }
1576
1577         /* ignore other fields */
1578         return 0;
1579 }
1580
1581 /**
1582  *  stmmac_set_rx_mode - entry point for multicast addressing
1583  *  @dev : pointer to the device structure
1584  *  Description:
1585  *  This function is a driver entry point which gets called by the kernel
1586  *  whenever multicast addresses must be enabled/disabled.
1587  *  Return value:
1588  *  void.
1589  */
1590 static void stmmac_set_rx_mode(struct net_device *dev)
1591 {
1592         struct stmmac_priv *priv = netdev_priv(dev);
1593
1594         spin_lock(&priv->lock);
1595         priv->hw->mac->set_filter(dev, priv->synopsys_id);
1596         spin_unlock(&priv->lock);
1597 }
1598
1599 /**
1600  *  stmmac_change_mtu - entry point to change MTU size for the device.
1601  *  @dev : device pointer.
1602  *  @new_mtu : the new MTU size for the device.
1603  *  Description: the Maximum Transfer Unit (MTU) is used by the network layer
1604  *  to drive packet transmission. Ethernet has an MTU of 1500 octets
1605  *  (ETH_DATA_LEN). This value can be changed with ifconfig.
1606  *  Return value:
1607  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1608  *  file on failure.
1609  */
1610 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
1611 {
1612         struct stmmac_priv *priv = netdev_priv(dev);
1613         int max_mtu;
1614
1615         if (netif_running(dev)) {
1616                 pr_err("%s: must be stopped to change its MTU\n", dev->name);
1617                 return -EBUSY;
1618         }
1619
1620         if (priv->plat->enh_desc)
1621                 max_mtu = JUMBO_LEN;
1622         else
1623                 max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
1624
1625         if ((new_mtu < 46) || (new_mtu > max_mtu)) {
1626                 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu);
1627                 return -EINVAL;
1628         }
1629
1630         dev->mtu = new_mtu;
1631         netdev_update_features(dev);
1632
1633         return 0;
1634 }
1635
1636 static netdev_features_t stmmac_fix_features(struct net_device *dev,
1637         netdev_features_t features)
1638 {
1639         struct stmmac_priv *priv = netdev_priv(dev);
1640
1641         if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
1642                 features &= ~NETIF_F_RXCSUM;
1643         else if (priv->plat->rx_coe == STMMAC_RX_COE_TYPE1)
1644                 features &= ~NETIF_F_IPV6_CSUM;
1645         if (!priv->plat->tx_coe)
1646                 features &= ~NETIF_F_ALL_CSUM;
1647
1648         /* Some GMAC devices have a bugged Jumbo frame support that
1649          * needs to have the Tx COE disabled for oversized frames
1650          * (due to limited buffer sizes). In this case we disable
1651          * the TX csum insertionin the TDES and not use SF. */
1652         if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
1653                 features &= ~NETIF_F_ALL_CSUM;
1654
1655         return features;
1656 }
1657
1658 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
1659 {
1660         struct net_device *dev = (struct net_device *)dev_id;
1661         struct stmmac_priv *priv = netdev_priv(dev);
1662
1663         if (unlikely(!dev)) {
1664                 pr_err("%s: invalid dev pointer\n", __func__);
1665                 return IRQ_NONE;
1666         }
1667
1668         /* To handle GMAC own interrupts */
1669         if (priv->plat->has_gmac) {
1670                 int status = priv->hw->mac->host_irq_status((void __iomem *)
1671                                                             dev->base_addr);
1672                 if (unlikely(status)) {
1673                         if (status & core_mmc_tx_irq)
1674                                 priv->xstats.mmc_tx_irq_n++;
1675                         if (status & core_mmc_rx_irq)
1676                                 priv->xstats.mmc_rx_irq_n++;
1677                         if (status & core_mmc_rx_csum_offload_irq)
1678                                 priv->xstats.mmc_rx_csum_offload_irq_n++;
1679                         if (status & core_irq_receive_pmt_irq)
1680                                 priv->xstats.irq_receive_pmt_irq_n++;
1681
1682                         /* For LPI we need to save the tx status */
1683                         if (status & core_irq_tx_path_in_lpi_mode) {
1684                                 priv->xstats.irq_tx_path_in_lpi_mode_n++;
1685                                 priv->tx_path_in_lpi_mode = true;
1686                         }
1687                         if (status & core_irq_tx_path_exit_lpi_mode) {
1688                                 priv->xstats.irq_tx_path_exit_lpi_mode_n++;
1689                                 priv->tx_path_in_lpi_mode = false;
1690                         }
1691                         if (status & core_irq_rx_path_in_lpi_mode)
1692                                 priv->xstats.irq_rx_path_in_lpi_mode_n++;
1693                         if (status & core_irq_rx_path_exit_lpi_mode)
1694                                 priv->xstats.irq_rx_path_exit_lpi_mode_n++;
1695                 }
1696         }
1697
1698         /* To handle DMA interrupts */
1699         stmmac_dma_interrupt(priv);
1700
1701         return IRQ_HANDLED;
1702 }
1703
1704 #ifdef CONFIG_NET_POLL_CONTROLLER
1705 /* Polling receive - used by NETCONSOLE and other diagnostic tools
1706  * to allow network I/O with interrupts disabled. */
1707 static void stmmac_poll_controller(struct net_device *dev)
1708 {
1709         disable_irq(dev->irq);
1710         stmmac_interrupt(dev->irq, dev);
1711         enable_irq(dev->irq);
1712 }
1713 #endif
1714
1715 /**
1716  *  stmmac_ioctl - Entry point for the Ioctl
1717  *  @dev: Device pointer.
1718  *  @rq: An IOCTL specefic structure, that can contain a pointer to
1719  *  a proprietary structure used to pass information to the driver.
1720  *  @cmd: IOCTL command
1721  *  Description:
1722  *  Currently there are no special functionality supported in IOCTL, just the
1723  *  phy_mii_ioctl(...) can be invoked.
1724  */
1725 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1726 {
1727         struct stmmac_priv *priv = netdev_priv(dev);
1728         int ret;
1729
1730         if (!netif_running(dev))
1731                 return -EINVAL;
1732
1733         if (!priv->phydev)
1734                 return -EINVAL;
1735
1736         ret = phy_mii_ioctl(priv->phydev, rq, cmd);
1737
1738         return ret;
1739 }
1740
1741 #ifdef CONFIG_STMMAC_DEBUG_FS
1742 static struct dentry *stmmac_fs_dir;
1743 static struct dentry *stmmac_rings_status;
1744 static struct dentry *stmmac_dma_cap;
1745
1746 static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v)
1747 {
1748         struct tmp_s {
1749                 u64 a;
1750                 unsigned int b;
1751                 unsigned int c;
1752         };
1753         int i;
1754         struct net_device *dev = seq->private;
1755         struct stmmac_priv *priv = netdev_priv(dev);
1756
1757         seq_printf(seq, "=======================\n");
1758         seq_printf(seq, " RX descriptor ring\n");
1759         seq_printf(seq, "=======================\n");
1760
1761         for (i = 0; i < priv->dma_rx_size; i++) {
1762                 struct tmp_s *x = (struct tmp_s *)(priv->dma_rx + i);
1763                 seq_printf(seq, "[%d] DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x",
1764                            i, (unsigned int)(x->a),
1765                            (unsigned int)((x->a) >> 32), x->b, x->c);
1766                 seq_printf(seq, "\n");
1767         }
1768
1769         seq_printf(seq, "\n");
1770         seq_printf(seq, "=======================\n");
1771         seq_printf(seq, "  TX descriptor ring\n");
1772         seq_printf(seq, "=======================\n");
1773
1774         for (i = 0; i < priv->dma_tx_size; i++) {
1775                 struct tmp_s *x = (struct tmp_s *)(priv->dma_tx + i);
1776                 seq_printf(seq, "[%d] DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x",
1777                            i, (unsigned int)(x->a),
1778                            (unsigned int)((x->a) >> 32), x->b, x->c);
1779                 seq_printf(seq, "\n");
1780         }
1781
1782         return 0;
1783 }
1784
1785 static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file)
1786 {
1787         return single_open(file, stmmac_sysfs_ring_read, inode->i_private);
1788 }
1789
1790 static const struct file_operations stmmac_rings_status_fops = {
1791         .owner = THIS_MODULE,
1792         .open = stmmac_sysfs_ring_open,
1793         .read = seq_read,
1794         .llseek = seq_lseek,
1795         .release = single_release,
1796 };
1797
1798 static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v)
1799 {
1800         struct net_device *dev = seq->private;
1801         struct stmmac_priv *priv = netdev_priv(dev);
1802
1803         if (!priv->hw_cap_support) {
1804                 seq_printf(seq, "DMA HW features not supported\n");
1805                 return 0;
1806         }
1807
1808         seq_printf(seq, "==============================\n");
1809         seq_printf(seq, "\tDMA HW features\n");
1810         seq_printf(seq, "==============================\n");
1811
1812         seq_printf(seq, "\t10/100 Mbps %s\n",
1813                    (priv->dma_cap.mbps_10_100) ? "Y" : "N");
1814         seq_printf(seq, "\t1000 Mbps %s\n",
1815                    (priv->dma_cap.mbps_1000) ? "Y" : "N");
1816         seq_printf(seq, "\tHalf duple %s\n",
1817                    (priv->dma_cap.half_duplex) ? "Y" : "N");
1818         seq_printf(seq, "\tHash Filter: %s\n",
1819                    (priv->dma_cap.hash_filter) ? "Y" : "N");
1820         seq_printf(seq, "\tMultiple MAC address registers: %s\n",
1821                    (priv->dma_cap.multi_addr) ? "Y" : "N");
1822         seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n",
1823                    (priv->dma_cap.pcs) ? "Y" : "N");
1824         seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
1825                    (priv->dma_cap.sma_mdio) ? "Y" : "N");
1826         seq_printf(seq, "\tPMT Remote wake up: %s\n",
1827                    (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
1828         seq_printf(seq, "\tPMT Magic Frame: %s\n",
1829                    (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
1830         seq_printf(seq, "\tRMON module: %s\n",
1831                    (priv->dma_cap.rmon) ? "Y" : "N");
1832         seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
1833                    (priv->dma_cap.time_stamp) ? "Y" : "N");
1834         seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n",
1835                    (priv->dma_cap.atime_stamp) ? "Y" : "N");
1836         seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n",
1837                    (priv->dma_cap.eee) ? "Y" : "N");
1838         seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
1839         seq_printf(seq, "\tChecksum Offload in TX: %s\n",
1840                    (priv->dma_cap.tx_coe) ? "Y" : "N");
1841         seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
1842                    (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
1843         seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
1844                    (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
1845         seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
1846                    (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
1847         seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
1848                    priv->dma_cap.number_rx_channel);
1849         seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
1850                    priv->dma_cap.number_tx_channel);
1851         seq_printf(seq, "\tEnhanced descriptors: %s\n",
1852                    (priv->dma_cap.enh_desc) ? "Y" : "N");
1853
1854         return 0;
1855 }
1856
1857 static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file)
1858 {
1859         return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private);
1860 }
1861
1862 static const struct file_operations stmmac_dma_cap_fops = {
1863         .owner = THIS_MODULE,
1864         .open = stmmac_sysfs_dma_cap_open,
1865         .read = seq_read,
1866         .llseek = seq_lseek,
1867         .release = single_release,
1868 };
1869
1870 static int stmmac_init_fs(struct net_device *dev)
1871 {
1872         /* Create debugfs entries */
1873         stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
1874
1875         if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
1876                 pr_err("ERROR %s, debugfs create directory failed\n",
1877                        STMMAC_RESOURCE_NAME);
1878
1879                 return -ENOMEM;
1880         }
1881
1882         /* Entry to report DMA RX/TX rings */
1883         stmmac_rings_status = debugfs_create_file("descriptors_status",
1884                                            S_IRUGO, stmmac_fs_dir, dev,
1885                                            &stmmac_rings_status_fops);
1886
1887         if (!stmmac_rings_status || IS_ERR(stmmac_rings_status)) {
1888                 pr_info("ERROR creating stmmac ring debugfs file\n");
1889                 debugfs_remove(stmmac_fs_dir);
1890
1891                 return -ENOMEM;
1892         }
1893
1894         /* Entry to report the DMA HW features */
1895         stmmac_dma_cap = debugfs_create_file("dma_cap", S_IRUGO, stmmac_fs_dir,
1896                                              dev, &stmmac_dma_cap_fops);
1897
1898         if (!stmmac_dma_cap || IS_ERR(stmmac_dma_cap)) {
1899                 pr_info("ERROR creating stmmac MMC debugfs file\n");
1900                 debugfs_remove(stmmac_rings_status);
1901                 debugfs_remove(stmmac_fs_dir);
1902
1903                 return -ENOMEM;
1904         }
1905
1906         return 0;
1907 }
1908
1909 static void stmmac_exit_fs(void)
1910 {
1911         debugfs_remove(stmmac_rings_status);
1912         debugfs_remove(stmmac_dma_cap);
1913         debugfs_remove(stmmac_fs_dir);
1914 }
1915 #endif /* CONFIG_STMMAC_DEBUG_FS */
1916
1917 static const struct net_device_ops stmmac_netdev_ops = {
1918         .ndo_open = stmmac_open,
1919         .ndo_start_xmit = stmmac_xmit,
1920         .ndo_stop = stmmac_release,
1921         .ndo_change_mtu = stmmac_change_mtu,
1922         .ndo_fix_features = stmmac_fix_features,
1923         .ndo_set_rx_mode = stmmac_set_rx_mode,
1924         .ndo_tx_timeout = stmmac_tx_timeout,
1925         .ndo_do_ioctl = stmmac_ioctl,
1926         .ndo_set_config = stmmac_config,
1927 #ifdef CONFIG_NET_POLL_CONTROLLER
1928         .ndo_poll_controller = stmmac_poll_controller,
1929 #endif
1930         .ndo_set_mac_address = eth_mac_addr,
1931 };
1932
1933 /**
1934  *  stmmac_hw_init - Init the MAC device
1935  *  @priv : pointer to the private device structure.
1936  *  Description: this function detects which MAC device
1937  *  (GMAC/MAC10-100) has to attached, checks the HW capability
1938  *  (if supported) and sets the driver's features (for example
1939  *  to use the ring or chaine mode or support the normal/enh
1940  *  descriptor structure).
1941  */
1942 static int stmmac_hw_init(struct stmmac_priv *priv)
1943 {
1944         int ret = 0;
1945         struct mac_device_info *mac;
1946
1947         /* Identify the MAC HW device */
1948         if (priv->plat->has_gmac) {
1949                 priv->dev->priv_flags |= IFF_UNICAST_FLT;
1950                 mac = dwmac1000_setup(priv->ioaddr);
1951         } else {
1952                 mac = dwmac100_setup(priv->ioaddr);
1953         }
1954         if (!mac)
1955                 return -ENOMEM;
1956
1957         priv->hw = mac;
1958
1959         /* To use the chained or ring mode */
1960         priv->hw->ring = &ring_mode_ops;
1961
1962         /* Get and dump the chip ID */
1963         priv->synopsys_id = stmmac_get_synopsys_id(priv);
1964
1965         /* Get the HW capability (new GMAC newer than 3.50a) */
1966         priv->hw_cap_support = stmmac_get_hw_features(priv);
1967         if (priv->hw_cap_support) {
1968                 pr_info(" DMA HW capability register supported");
1969
1970                 /* We can override some gmac/dma configuration fields: e.g.
1971                  * enh_desc, tx_coe (e.g. that are passed through the
1972                  * platform) with the values from the HW capability
1973                  * register (if supported).
1974                  */
1975                 priv->plat->enh_desc = priv->dma_cap.enh_desc;
1976                 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
1977
1978                 priv->plat->tx_coe = priv->dma_cap.tx_coe;
1979
1980                 if (priv->dma_cap.rx_coe_type2)
1981                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
1982                 else if (priv->dma_cap.rx_coe_type1)
1983                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
1984
1985         } else
1986                 pr_info(" No HW DMA feature register supported");
1987
1988         /* Select the enhnaced/normal descriptor structures */
1989         stmmac_selec_desc_mode(priv);
1990
1991         /* Enable the IPC (Checksum Offload) and check if the feature has been
1992          * enabled during the core configuration. */
1993         ret = priv->hw->mac->rx_ipc(priv->ioaddr);
1994         if (!ret) {
1995                 pr_warning(" RX IPC Checksum Offload not configured.\n");
1996                 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
1997         }
1998
1999         if (priv->plat->rx_coe)
2000                 pr_info(" RX Checksum Offload Engine supported (type %d)\n",
2001                         priv->plat->rx_coe);
2002         if (priv->plat->tx_coe)
2003                 pr_info(" TX Checksum insertion supported\n");
2004
2005         if (priv->plat->pmt) {
2006                 pr_info(" Wake-Up On Lan supported\n");
2007                 device_set_wakeup_capable(priv->device, 1);
2008         }
2009
2010         return ret;
2011 }
2012
2013 /**
2014  * stmmac_dvr_probe
2015  * @device: device pointer
2016  * @plat_dat: platform data pointer
2017  * @addr: iobase memory address
2018  * Description: this is the main probe function used to
2019  * call the alloc_etherdev, allocate the priv structure.
2020  */
2021 struct stmmac_priv *stmmac_dvr_probe(struct device *device,
2022                                      struct plat_stmmacenet_data *plat_dat,
2023                                      void __iomem *addr)
2024 {
2025         int ret = 0;
2026         struct net_device *ndev = NULL;
2027         struct stmmac_priv *priv;
2028
2029         ndev = alloc_etherdev(sizeof(struct stmmac_priv));
2030         if (!ndev)
2031                 return NULL;
2032
2033         SET_NETDEV_DEV(ndev, device);
2034
2035         priv = netdev_priv(ndev);
2036         priv->device = device;
2037         priv->dev = ndev;
2038
2039         ether_setup(ndev);
2040
2041         stmmac_set_ethtool_ops(ndev);
2042         priv->pause = pause;
2043         priv->plat = plat_dat;
2044         priv->ioaddr = addr;
2045         priv->dev->base_addr = (unsigned long)addr;
2046
2047         /* Verify driver arguments */
2048         stmmac_verify_args();
2049
2050         /* Override with kernel parameters if supplied XXX CRS XXX
2051          * this needs to have multiple instances */
2052         if ((phyaddr >= 0) && (phyaddr <= 31))
2053                 priv->plat->phy_addr = phyaddr;
2054
2055         /* Init MAC and get the capabilities */
2056         stmmac_hw_init(priv);
2057
2058         ndev->netdev_ops = &stmmac_netdev_ops;
2059
2060         ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2061                             NETIF_F_RXCSUM;
2062         ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
2063         ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
2064 #ifdef STMMAC_VLAN_TAG_USED
2065         /* Both mac100 and gmac support receive VLAN tag detection */
2066         ndev->features |= NETIF_F_HW_VLAN_RX;
2067 #endif
2068         priv->msg_enable = netif_msg_init(debug, default_msg_level);
2069
2070         if (flow_ctrl)
2071                 priv->flow_ctrl = FLOW_AUTO;    /* RX/TX pause on */
2072
2073         netif_napi_add(ndev, &priv->napi, stmmac_poll, 64);
2074
2075         spin_lock_init(&priv->lock);
2076         spin_lock_init(&priv->tx_lock);
2077
2078         ret = register_netdev(ndev);
2079         if (ret) {
2080                 pr_err("%s: ERROR %i registering the device\n", __func__, ret);
2081                 goto error;
2082         }
2083
2084         if (stmmac_clk_get(priv))
2085                 pr_warning("%s: warning: cannot get CSR clock\n", __func__);
2086
2087         /* If a specific clk_csr value is passed from the platform
2088          * this means that the CSR Clock Range selection cannot be
2089          * changed at run-time and it is fixed. Viceversa the driver'll try to
2090          * set the MDC clock dynamically according to the csr actual
2091          * clock input.
2092          */
2093         if (!priv->plat->clk_csr)
2094                 stmmac_clk_csr_set(priv);
2095         else
2096                 priv->clk_csr = priv->plat->clk_csr;
2097
2098         /* MDIO bus Registration */
2099         ret = stmmac_mdio_register(ndev);
2100         if (ret < 0) {
2101                 pr_debug("%s: MDIO bus (id: %d) registration failed",
2102                          __func__, priv->plat->bus_id);
2103                 goto error;
2104         }
2105
2106         return priv;
2107
2108 error:
2109         netif_napi_del(&priv->napi);
2110
2111         unregister_netdev(ndev);
2112         free_netdev(ndev);
2113
2114         return NULL;
2115 }
2116
2117 /**
2118  * stmmac_dvr_remove
2119  * @ndev: net device pointer
2120  * Description: this function resets the TX/RX processes, disables the MAC RX/TX
2121  * changes the link status, releases the DMA descriptor rings.
2122  */
2123 int stmmac_dvr_remove(struct net_device *ndev)
2124 {
2125         struct stmmac_priv *priv = netdev_priv(ndev);
2126
2127         pr_info("%s:\n\tremoving driver", __func__);
2128
2129         priv->hw->dma->stop_rx(priv->ioaddr);
2130         priv->hw->dma->stop_tx(priv->ioaddr);
2131
2132         stmmac_set_mac(priv->ioaddr, false);
2133         stmmac_mdio_unregister(ndev);
2134         netif_carrier_off(ndev);
2135         unregister_netdev(ndev);
2136         free_netdev(ndev);
2137
2138         return 0;
2139 }
2140
2141 #ifdef CONFIG_PM
2142 int stmmac_suspend(struct net_device *ndev)
2143 {
2144         struct stmmac_priv *priv = netdev_priv(ndev);
2145         int dis_ic = 0;
2146         unsigned long flags;
2147
2148         if (!ndev || !netif_running(ndev))
2149                 return 0;
2150
2151         if (priv->phydev)
2152                 phy_stop(priv->phydev);
2153
2154         spin_lock_irqsave(&priv->lock, flags);
2155
2156         netif_device_detach(ndev);
2157         netif_stop_queue(ndev);
2158
2159 #ifdef CONFIG_STMMAC_TIMER
2160         priv->tm->timer_stop();
2161         if (likely(priv->tm->enable))
2162                 dis_ic = 1;
2163 #endif
2164         napi_disable(&priv->napi);
2165
2166         /* Stop TX/RX DMA */
2167         priv->hw->dma->stop_tx(priv->ioaddr);
2168         priv->hw->dma->stop_rx(priv->ioaddr);
2169         /* Clear the Rx/Tx descriptors */
2170         priv->hw->desc->init_rx_desc(priv->dma_rx, priv->dma_rx_size,
2171                                      dis_ic);
2172         priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size);
2173
2174         /* Enable Power down mode by programming the PMT regs */
2175         if (device_may_wakeup(priv->device))
2176                 priv->hw->mac->pmt(priv->ioaddr, priv->wolopts);
2177         else {
2178                 stmmac_set_mac(priv->ioaddr, false);
2179                 /* Disable clock in case of PWM is off */
2180                 stmmac_clk_disable(priv);
2181         }
2182         spin_unlock_irqrestore(&priv->lock, flags);
2183         return 0;
2184 }
2185
2186 int stmmac_resume(struct net_device *ndev)
2187 {
2188         struct stmmac_priv *priv = netdev_priv(ndev);
2189         unsigned long flags;
2190
2191         if (!netif_running(ndev))
2192                 return 0;
2193
2194         spin_lock_irqsave(&priv->lock, flags);
2195
2196         /* Power Down bit, into the PM register, is cleared
2197          * automatically as soon as a magic packet or a Wake-up frame
2198          * is received. Anyway, it's better to manually clear
2199          * this bit because it can generate problems while resuming
2200          * from another devices (e.g. serial console). */
2201         if (device_may_wakeup(priv->device))
2202                 priv->hw->mac->pmt(priv->ioaddr, 0);
2203         else
2204                 /* enable the clk prevously disabled */
2205                 stmmac_clk_enable(priv);
2206
2207         netif_device_attach(ndev);
2208
2209         /* Enable the MAC and DMA */
2210         stmmac_set_mac(priv->ioaddr, true);
2211         priv->hw->dma->start_tx(priv->ioaddr);
2212         priv->hw->dma->start_rx(priv->ioaddr);
2213
2214 #ifdef CONFIG_STMMAC_TIMER
2215         if (likely(priv->tm->enable))
2216                 priv->tm->timer_start(tmrate);
2217 #endif
2218         napi_enable(&priv->napi);
2219
2220         netif_start_queue(ndev);
2221
2222         spin_unlock_irqrestore(&priv->lock, flags);
2223
2224         if (priv->phydev)
2225                 phy_start(priv->phydev);
2226
2227         return 0;
2228 }
2229
2230 int stmmac_freeze(struct net_device *ndev)
2231 {
2232         if (!ndev || !netif_running(ndev))
2233                 return 0;
2234
2235         return stmmac_release(ndev);
2236 }
2237
2238 int stmmac_restore(struct net_device *ndev)
2239 {
2240         if (!ndev || !netif_running(ndev))
2241                 return 0;
2242
2243         return stmmac_open(ndev);
2244 }
2245 #endif /* CONFIG_PM */
2246
2247 /* Driver can be configured w/ and w/ both PCI and Platf drivers
2248  * depending on the configuration selected.
2249  */
2250 static int __init stmmac_init(void)
2251 {
2252         int err_plt = 0;
2253         int err_pci = 0;
2254
2255         err_plt = stmmac_register_platform();
2256         err_pci = stmmac_register_pci();
2257
2258         if ((err_pci) && (err_plt)) {
2259                 pr_err("stmmac: driver registration failed\n");
2260                 return -EINVAL;
2261         }
2262
2263         return 0;
2264 }
2265
2266 static void __exit stmmac_exit(void)
2267 {
2268         stmmac_unregister_platform();
2269         stmmac_unregister_pci();
2270 }
2271
2272 module_init(stmmac_init);
2273 module_exit(stmmac_exit);
2274
2275 #ifndef MODULE
2276 static int __init stmmac_cmdline_opt(char *str)
2277 {
2278         char *opt;
2279
2280         if (!str || !*str)
2281                 return -EINVAL;
2282         while ((opt = strsep(&str, ",")) != NULL) {
2283                 if (!strncmp(opt, "debug:", 6)) {
2284                         if (kstrtoint(opt + 6, 0, &debug))
2285                                 goto err;
2286                 } else if (!strncmp(opt, "phyaddr:", 8)) {
2287                         if (kstrtoint(opt + 8, 0, &phyaddr))
2288                                 goto err;
2289                 } else if (!strncmp(opt, "dma_txsize:", 11)) {
2290                         if (kstrtoint(opt + 11, 0, &dma_txsize))
2291                                 goto err;
2292                 } else if (!strncmp(opt, "dma_rxsize:", 11)) {
2293                         if (kstrtoint(opt + 11, 0, &dma_rxsize))
2294                                 goto err;
2295                 } else if (!strncmp(opt, "buf_sz:", 7)) {
2296                         if (kstrtoint(opt + 7, 0, &buf_sz))
2297                                 goto err;
2298                 } else if (!strncmp(opt, "tc:", 3)) {
2299                         if (kstrtoint(opt + 3, 0, &tc))
2300                                 goto err;
2301                 } else if (!strncmp(opt, "watchdog:", 9)) {
2302                         if (kstrtoint(opt + 9, 0, &watchdog))
2303                                 goto err;
2304                 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
2305                         if (kstrtoint(opt + 10, 0, &flow_ctrl))
2306                                 goto err;
2307                 } else if (!strncmp(opt, "pause:", 6)) {
2308                         if (kstrtoint(opt + 6, 0, &pause))
2309                                 goto err;
2310                 } else if (!strncmp(opt, "eee_timer:", 6)) {
2311                         if (kstrtoint(opt + 10, 0, &eee_timer))
2312                                 goto err;
2313 #ifdef CONFIG_STMMAC_TIMER
2314                 } else if (!strncmp(opt, "tmrate:", 7)) {
2315                         if (kstrtoint(opt + 7, 0, &tmrate))
2316                                 goto err;
2317 #endif
2318                 }
2319         }
2320         return 0;
2321
2322 err:
2323         pr_err("%s: ERROR broken module parameter conversion", __func__);
2324         return -EINVAL;
2325 }
2326
2327 __setup("stmmaceth=", stmmac_cmdline_opt);
2328 #endif
2329
2330 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
2331 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
2332 MODULE_LICENSE("GPL");