1 /***************************************************************************
3 * Copyright (C) 2007,2008 SMSC
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 ***************************************************************************
22 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
24 #include <linux/interrupt.h>
25 #include <linux/kernel.h>
26 #include <linux/netdevice.h>
27 #include <linux/phy.h>
28 #include <linux/pci.h>
29 #include <linux/if_vlan.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/crc32.h>
32 #include <linux/slab.h>
33 #include <linux/module.h>
34 #include <asm/unaligned.h>
37 #define DRV_NAME "smsc9420"
38 #define DRV_MDIONAME "smsc9420-mdio"
39 #define DRV_DESCRIPTION "SMSC LAN9420 driver"
40 #define DRV_VERSION "1.01"
42 MODULE_LICENSE("GPL");
43 MODULE_VERSION(DRV_VERSION);
45 struct smsc9420_dma_desc {
52 struct smsc9420_ring_info {
57 struct smsc9420_pdata {
60 struct net_device *dev;
62 struct smsc9420_dma_desc *rx_ring;
63 struct smsc9420_dma_desc *tx_ring;
64 struct smsc9420_ring_info *tx_buffers;
65 struct smsc9420_ring_info *rx_buffers;
66 dma_addr_t rx_dma_addr;
67 dma_addr_t tx_dma_addr;
68 int tx_ring_head, tx_ring_tail;
69 int rx_ring_head, rx_ring_tail;
74 struct napi_struct napi;
76 bool software_irq_signal;
80 struct phy_device *phy_dev;
81 struct mii_bus *mii_bus;
82 int phy_irq[PHY_MAX_ADDR];
87 static DEFINE_PCI_DEVICE_TABLE(smsc9420_id_table) = {
88 { PCI_VENDOR_ID_9420, PCI_DEVICE_ID_9420, PCI_ANY_ID, PCI_ANY_ID, },
92 MODULE_DEVICE_TABLE(pci, smsc9420_id_table);
94 #define SMSC_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
96 static uint smsc_debug;
97 static uint debug = -1;
98 module_param(debug, uint, 0);
99 MODULE_PARM_DESC(debug, "debug level");
101 static inline u32 smsc9420_reg_read(struct smsc9420_pdata *pd, u32 offset)
103 return ioread32(pd->ioaddr + offset);
107 smsc9420_reg_write(struct smsc9420_pdata *pd, u32 offset, u32 value)
109 iowrite32(value, pd->ioaddr + offset);
112 static inline void smsc9420_pci_flush_write(struct smsc9420_pdata *pd)
114 /* to ensure PCI write completion, we must perform a PCI read */
115 smsc9420_reg_read(pd, ID_REV);
118 static int smsc9420_mii_read(struct mii_bus *bus, int phyaddr, int regidx)
120 struct smsc9420_pdata *pd = (struct smsc9420_pdata *)bus->priv;
125 spin_lock_irqsave(&pd->phy_lock, flags);
127 /* confirm MII not busy */
128 if ((smsc9420_reg_read(pd, MII_ACCESS) & MII_ACCESS_MII_BUSY_)) {
129 netif_warn(pd, drv, pd->dev, "MII is busy???\n");
133 /* set the address, index & direction (read from PHY) */
134 addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) |
135 MII_ACCESS_MII_READ_;
136 smsc9420_reg_write(pd, MII_ACCESS, addr);
138 /* wait for read to complete with 50us timeout */
139 for (i = 0; i < 5; i++) {
140 if (!(smsc9420_reg_read(pd, MII_ACCESS) &
141 MII_ACCESS_MII_BUSY_)) {
142 reg = (u16)smsc9420_reg_read(pd, MII_DATA);
148 netif_warn(pd, drv, pd->dev, "MII busy timeout!\n");
151 spin_unlock_irqrestore(&pd->phy_lock, flags);
155 static int smsc9420_mii_write(struct mii_bus *bus, int phyaddr, int regidx,
158 struct smsc9420_pdata *pd = (struct smsc9420_pdata *)bus->priv;
163 spin_lock_irqsave(&pd->phy_lock, flags);
165 /* confirm MII not busy */
166 if ((smsc9420_reg_read(pd, MII_ACCESS) & MII_ACCESS_MII_BUSY_)) {
167 netif_warn(pd, drv, pd->dev, "MII is busy???\n");
171 /* put the data to write in the MAC */
172 smsc9420_reg_write(pd, MII_DATA, (u32)val);
174 /* set the address, index & direction (write to PHY) */
175 addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) |
176 MII_ACCESS_MII_WRITE_;
177 smsc9420_reg_write(pd, MII_ACCESS, addr);
179 /* wait for write to complete with 50us timeout */
180 for (i = 0; i < 5; i++) {
181 if (!(smsc9420_reg_read(pd, MII_ACCESS) &
182 MII_ACCESS_MII_BUSY_)) {
189 netif_warn(pd, drv, pd->dev, "MII busy timeout!\n");
192 spin_unlock_irqrestore(&pd->phy_lock, flags);
196 /* Returns hash bit number for given MAC address
198 * 01 00 5E 00 00 01 -> returns bit number 31 */
199 static u32 smsc9420_hash(u8 addr[ETH_ALEN])
201 return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f;
204 static int smsc9420_eeprom_reload(struct smsc9420_pdata *pd)
206 int timeout = 100000;
210 if (smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_) {
211 netif_dbg(pd, drv, pd->dev, "%s: Eeprom busy\n", __func__);
215 smsc9420_reg_write(pd, E2P_CMD,
216 (E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_RELOAD_));
220 if (!(smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_))
224 netif_warn(pd, drv, pd->dev, "%s: Eeprom timed out\n", __func__);
228 /* Standard ioctls for mii-tool */
229 static int smsc9420_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
231 struct smsc9420_pdata *pd = netdev_priv(dev);
233 if (!netif_running(dev) || !pd->phy_dev)
236 return phy_mii_ioctl(pd->phy_dev, ifr, cmd);
239 static int smsc9420_ethtool_get_settings(struct net_device *dev,
240 struct ethtool_cmd *cmd)
242 struct smsc9420_pdata *pd = netdev_priv(dev);
249 return phy_ethtool_gset(pd->phy_dev, cmd);
252 static int smsc9420_ethtool_set_settings(struct net_device *dev,
253 struct ethtool_cmd *cmd)
255 struct smsc9420_pdata *pd = netdev_priv(dev);
260 return phy_ethtool_sset(pd->phy_dev, cmd);
263 static void smsc9420_ethtool_get_drvinfo(struct net_device *netdev,
264 struct ethtool_drvinfo *drvinfo)
266 struct smsc9420_pdata *pd = netdev_priv(netdev);
268 strlcpy(drvinfo->driver, DRV_NAME, sizeof(drvinfo->driver));
269 strlcpy(drvinfo->bus_info, pci_name(pd->pdev),
270 sizeof(drvinfo->bus_info));
271 strlcpy(drvinfo->version, DRV_VERSION, sizeof(drvinfo->version));
274 static u32 smsc9420_ethtool_get_msglevel(struct net_device *netdev)
276 struct smsc9420_pdata *pd = netdev_priv(netdev);
277 return pd->msg_enable;
280 static void smsc9420_ethtool_set_msglevel(struct net_device *netdev, u32 data)
282 struct smsc9420_pdata *pd = netdev_priv(netdev);
283 pd->msg_enable = data;
286 static int smsc9420_ethtool_nway_reset(struct net_device *netdev)
288 struct smsc9420_pdata *pd = netdev_priv(netdev);
293 return phy_start_aneg(pd->phy_dev);
296 static int smsc9420_ethtool_getregslen(struct net_device *dev)
298 /* all smsc9420 registers plus all phy registers */
299 return 0x100 + (32 * sizeof(u32));
303 smsc9420_ethtool_getregs(struct net_device *dev, struct ethtool_regs *regs,
306 struct smsc9420_pdata *pd = netdev_priv(dev);
307 struct phy_device *phy_dev = pd->phy_dev;
308 unsigned int i, j = 0;
311 regs->version = smsc9420_reg_read(pd, ID_REV);
312 for (i = 0; i < 0x100; i += (sizeof(u32)))
313 data[j++] = smsc9420_reg_read(pd, i);
315 // cannot read phy registers if the net device is down
319 for (i = 0; i <= 31; i++)
320 data[j++] = smsc9420_mii_read(phy_dev->bus, phy_dev->addr, i);
323 static void smsc9420_eeprom_enable_access(struct smsc9420_pdata *pd)
325 unsigned int temp = smsc9420_reg_read(pd, GPIO_CFG);
326 temp &= ~GPIO_CFG_EEPR_EN_;
327 smsc9420_reg_write(pd, GPIO_CFG, temp);
331 static int smsc9420_eeprom_send_cmd(struct smsc9420_pdata *pd, u32 op)
336 netif_dbg(pd, hw, pd->dev, "op 0x%08x\n", op);
337 if (smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_) {
338 netif_warn(pd, hw, pd->dev, "Busy at start\n");
342 e2cmd = op | E2P_CMD_EPC_BUSY_;
343 smsc9420_reg_write(pd, E2P_CMD, e2cmd);
347 e2cmd = smsc9420_reg_read(pd, E2P_CMD);
348 } while ((e2cmd & E2P_CMD_EPC_BUSY_) && (--timeout));
351 netif_info(pd, hw, pd->dev, "TIMED OUT\n");
355 if (e2cmd & E2P_CMD_EPC_TIMEOUT_) {
356 netif_info(pd, hw, pd->dev,
357 "Error occurred during eeprom operation\n");
364 static int smsc9420_eeprom_read_location(struct smsc9420_pdata *pd,
365 u8 address, u8 *data)
367 u32 op = E2P_CMD_EPC_CMD_READ_ | address;
370 netif_dbg(pd, hw, pd->dev, "address 0x%x\n", address);
371 ret = smsc9420_eeprom_send_cmd(pd, op);
374 data[address] = smsc9420_reg_read(pd, E2P_DATA);
379 static int smsc9420_eeprom_write_location(struct smsc9420_pdata *pd,
382 u32 op = E2P_CMD_EPC_CMD_ERASE_ | address;
385 netif_dbg(pd, hw, pd->dev, "address 0x%x, data 0x%x\n", address, data);
386 ret = smsc9420_eeprom_send_cmd(pd, op);
389 op = E2P_CMD_EPC_CMD_WRITE_ | address;
390 smsc9420_reg_write(pd, E2P_DATA, (u32)data);
391 ret = smsc9420_eeprom_send_cmd(pd, op);
397 static int smsc9420_ethtool_get_eeprom_len(struct net_device *dev)
399 return SMSC9420_EEPROM_SIZE;
402 static int smsc9420_ethtool_get_eeprom(struct net_device *dev,
403 struct ethtool_eeprom *eeprom, u8 *data)
405 struct smsc9420_pdata *pd = netdev_priv(dev);
406 u8 eeprom_data[SMSC9420_EEPROM_SIZE];
409 smsc9420_eeprom_enable_access(pd);
411 len = min(eeprom->len, SMSC9420_EEPROM_SIZE);
412 for (i = 0; i < len; i++) {
413 int ret = smsc9420_eeprom_read_location(pd, i, eeprom_data);
420 memcpy(data, &eeprom_data[eeprom->offset], len);
421 eeprom->magic = SMSC9420_EEPROM_MAGIC;
426 static int smsc9420_ethtool_set_eeprom(struct net_device *dev,
427 struct ethtool_eeprom *eeprom, u8 *data)
429 struct smsc9420_pdata *pd = netdev_priv(dev);
432 if (eeprom->magic != SMSC9420_EEPROM_MAGIC)
435 smsc9420_eeprom_enable_access(pd);
436 smsc9420_eeprom_send_cmd(pd, E2P_CMD_EPC_CMD_EWEN_);
437 ret = smsc9420_eeprom_write_location(pd, eeprom->offset, *data);
438 smsc9420_eeprom_send_cmd(pd, E2P_CMD_EPC_CMD_EWDS_);
440 /* Single byte write, according to man page */
446 static const struct ethtool_ops smsc9420_ethtool_ops = {
447 .get_settings = smsc9420_ethtool_get_settings,
448 .set_settings = smsc9420_ethtool_set_settings,
449 .get_drvinfo = smsc9420_ethtool_get_drvinfo,
450 .get_msglevel = smsc9420_ethtool_get_msglevel,
451 .set_msglevel = smsc9420_ethtool_set_msglevel,
452 .nway_reset = smsc9420_ethtool_nway_reset,
453 .get_link = ethtool_op_get_link,
454 .get_eeprom_len = smsc9420_ethtool_get_eeprom_len,
455 .get_eeprom = smsc9420_ethtool_get_eeprom,
456 .set_eeprom = smsc9420_ethtool_set_eeprom,
457 .get_regs_len = smsc9420_ethtool_getregslen,
458 .get_regs = smsc9420_ethtool_getregs,
459 .get_ts_info = ethtool_op_get_ts_info,
462 /* Sets the device MAC address to dev_addr */
463 static void smsc9420_set_mac_address(struct net_device *dev)
465 struct smsc9420_pdata *pd = netdev_priv(dev);
466 u8 *dev_addr = dev->dev_addr;
467 u32 mac_high16 = (dev_addr[5] << 8) | dev_addr[4];
468 u32 mac_low32 = (dev_addr[3] << 24) | (dev_addr[2] << 16) |
469 (dev_addr[1] << 8) | dev_addr[0];
471 smsc9420_reg_write(pd, ADDRH, mac_high16);
472 smsc9420_reg_write(pd, ADDRL, mac_low32);
475 static void smsc9420_check_mac_address(struct net_device *dev)
477 struct smsc9420_pdata *pd = netdev_priv(dev);
479 /* Check if mac address has been specified when bringing interface up */
480 if (is_valid_ether_addr(dev->dev_addr)) {
481 smsc9420_set_mac_address(dev);
482 netif_dbg(pd, probe, pd->dev,
483 "MAC Address is specified by configuration\n");
485 /* Try reading mac address from device. if EEPROM is present
486 * it will already have been set */
487 u32 mac_high16 = smsc9420_reg_read(pd, ADDRH);
488 u32 mac_low32 = smsc9420_reg_read(pd, ADDRL);
489 dev->dev_addr[0] = (u8)(mac_low32);
490 dev->dev_addr[1] = (u8)(mac_low32 >> 8);
491 dev->dev_addr[2] = (u8)(mac_low32 >> 16);
492 dev->dev_addr[3] = (u8)(mac_low32 >> 24);
493 dev->dev_addr[4] = (u8)(mac_high16);
494 dev->dev_addr[5] = (u8)(mac_high16 >> 8);
496 if (is_valid_ether_addr(dev->dev_addr)) {
497 /* eeprom values are valid so use them */
498 netif_dbg(pd, probe, pd->dev,
499 "Mac Address is read from EEPROM\n");
501 /* eeprom values are invalid, generate random MAC */
502 eth_hw_addr_random(dev);
503 smsc9420_set_mac_address(dev);
504 netif_dbg(pd, probe, pd->dev,
505 "MAC Address is set to random\n");
510 static void smsc9420_stop_tx(struct smsc9420_pdata *pd)
512 u32 dmac_control, mac_cr, dma_intr_ena;
515 /* disable TX DMAC */
516 dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL);
517 dmac_control &= (~DMAC_CONTROL_ST_);
518 smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control);
520 /* Wait max 10ms for transmit process to stop */
522 if (smsc9420_reg_read(pd, DMAC_STATUS) & DMAC_STS_TS_)
528 netif_warn(pd, ifdown, pd->dev, "TX DMAC failed to stop\n");
530 /* ACK Tx DMAC stop bit */
531 smsc9420_reg_write(pd, DMAC_STATUS, DMAC_STS_TXPS_);
533 /* mask TX DMAC interrupts */
534 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
535 dma_intr_ena &= ~(DMAC_INTR_ENA_TX_);
536 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
537 smsc9420_pci_flush_write(pd);
540 mac_cr = smsc9420_reg_read(pd, MAC_CR) & (~MAC_CR_TXEN_);
541 smsc9420_reg_write(pd, MAC_CR, mac_cr);
542 smsc9420_pci_flush_write(pd);
545 static void smsc9420_free_tx_ring(struct smsc9420_pdata *pd)
549 BUG_ON(!pd->tx_ring);
554 for (i = 0; i < TX_RING_SIZE; i++) {
555 struct sk_buff *skb = pd->tx_buffers[i].skb;
558 BUG_ON(!pd->tx_buffers[i].mapping);
559 pci_unmap_single(pd->pdev, pd->tx_buffers[i].mapping,
560 skb->len, PCI_DMA_TODEVICE);
561 dev_kfree_skb_any(skb);
564 pd->tx_ring[i].status = 0;
565 pd->tx_ring[i].length = 0;
566 pd->tx_ring[i].buffer1 = 0;
567 pd->tx_ring[i].buffer2 = 0;
571 kfree(pd->tx_buffers);
572 pd->tx_buffers = NULL;
574 pd->tx_ring_head = 0;
575 pd->tx_ring_tail = 0;
578 static void smsc9420_free_rx_ring(struct smsc9420_pdata *pd)
582 BUG_ON(!pd->rx_ring);
587 for (i = 0; i < RX_RING_SIZE; i++) {
588 if (pd->rx_buffers[i].skb)
589 dev_kfree_skb_any(pd->rx_buffers[i].skb);
591 if (pd->rx_buffers[i].mapping)
592 pci_unmap_single(pd->pdev, pd->rx_buffers[i].mapping,
593 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
595 pd->rx_ring[i].status = 0;
596 pd->rx_ring[i].length = 0;
597 pd->rx_ring[i].buffer1 = 0;
598 pd->rx_ring[i].buffer2 = 0;
602 kfree(pd->rx_buffers);
603 pd->rx_buffers = NULL;
605 pd->rx_ring_head = 0;
606 pd->rx_ring_tail = 0;
609 static void smsc9420_stop_rx(struct smsc9420_pdata *pd)
612 u32 mac_cr, dmac_control, dma_intr_ena;
614 /* mask RX DMAC interrupts */
615 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
616 dma_intr_ena &= (~DMAC_INTR_ENA_RX_);
617 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
618 smsc9420_pci_flush_write(pd);
620 /* stop RX MAC prior to stoping DMA */
621 mac_cr = smsc9420_reg_read(pd, MAC_CR) & (~MAC_CR_RXEN_);
622 smsc9420_reg_write(pd, MAC_CR, mac_cr);
623 smsc9420_pci_flush_write(pd);
626 dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL);
627 dmac_control &= (~DMAC_CONTROL_SR_);
628 smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control);
629 smsc9420_pci_flush_write(pd);
631 /* wait up to 10ms for receive to stop */
633 if (smsc9420_reg_read(pd, DMAC_STATUS) & DMAC_STS_RS_)
639 netif_warn(pd, ifdown, pd->dev,
640 "RX DMAC did not stop! timeout\n");
642 /* ACK the Rx DMAC stop bit */
643 smsc9420_reg_write(pd, DMAC_STATUS, DMAC_STS_RXPS_);
646 static irqreturn_t smsc9420_isr(int irq, void *dev_id)
648 struct smsc9420_pdata *pd = dev_id;
649 u32 int_cfg, int_sts, int_ctl;
650 irqreturn_t ret = IRQ_NONE;
656 int_cfg = smsc9420_reg_read(pd, INT_CFG);
658 /* check if it's our interrupt */
659 if ((int_cfg & (INT_CFG_IRQ_EN_ | INT_CFG_IRQ_INT_)) !=
660 (INT_CFG_IRQ_EN_ | INT_CFG_IRQ_INT_))
663 int_sts = smsc9420_reg_read(pd, INT_STAT);
665 if (likely(INT_STAT_DMAC_INT_ & int_sts)) {
666 u32 status = smsc9420_reg_read(pd, DMAC_STATUS);
667 u32 ints_to_clear = 0;
669 if (status & DMAC_STS_TX_) {
670 ints_to_clear |= (DMAC_STS_TX_ | DMAC_STS_NIS_);
671 netif_wake_queue(pd->dev);
674 if (status & DMAC_STS_RX_) {
675 /* mask RX DMAC interrupts */
676 u32 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
677 dma_intr_ena &= (~DMAC_INTR_ENA_RX_);
678 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
679 smsc9420_pci_flush_write(pd);
681 ints_to_clear |= (DMAC_STS_RX_ | DMAC_STS_NIS_);
682 napi_schedule(&pd->napi);
686 smsc9420_reg_write(pd, DMAC_STATUS, ints_to_clear);
691 if (unlikely(INT_STAT_SW_INT_ & int_sts)) {
692 /* mask software interrupt */
693 spin_lock_irqsave(&pd->int_lock, flags);
694 int_ctl = smsc9420_reg_read(pd, INT_CTL);
695 int_ctl &= (~INT_CTL_SW_INT_EN_);
696 smsc9420_reg_write(pd, INT_CTL, int_ctl);
697 spin_unlock_irqrestore(&pd->int_lock, flags);
699 smsc9420_reg_write(pd, INT_STAT, INT_STAT_SW_INT_);
700 pd->software_irq_signal = true;
706 /* to ensure PCI write completion, we must perform a PCI read */
707 smsc9420_pci_flush_write(pd);
712 #ifdef CONFIG_NET_POLL_CONTROLLER
713 static void smsc9420_poll_controller(struct net_device *dev)
715 struct smsc9420_pdata *pd = netdev_priv(dev);
716 const int irq = pd->pdev->irq;
719 smsc9420_isr(0, dev);
722 #endif /* CONFIG_NET_POLL_CONTROLLER */
724 static void smsc9420_dmac_soft_reset(struct smsc9420_pdata *pd)
726 smsc9420_reg_write(pd, BUS_MODE, BUS_MODE_SWR_);
727 smsc9420_reg_read(pd, BUS_MODE);
729 if (smsc9420_reg_read(pd, BUS_MODE) & BUS_MODE_SWR_)
730 netif_warn(pd, drv, pd->dev, "Software reset not cleared\n");
733 static int smsc9420_stop(struct net_device *dev)
735 struct smsc9420_pdata *pd = netdev_priv(dev);
740 BUG_ON(!pd->phy_dev);
742 /* disable master interrupt */
743 spin_lock_irqsave(&pd->int_lock, flags);
744 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
745 smsc9420_reg_write(pd, INT_CFG, int_cfg);
746 spin_unlock_irqrestore(&pd->int_lock, flags);
748 netif_tx_disable(dev);
749 napi_disable(&pd->napi);
751 smsc9420_stop_tx(pd);
752 smsc9420_free_tx_ring(pd);
754 smsc9420_stop_rx(pd);
755 smsc9420_free_rx_ring(pd);
757 free_irq(pd->pdev->irq, pd);
759 smsc9420_dmac_soft_reset(pd);
761 phy_stop(pd->phy_dev);
763 phy_disconnect(pd->phy_dev);
765 mdiobus_unregister(pd->mii_bus);
766 mdiobus_free(pd->mii_bus);
771 static void smsc9420_rx_count_stats(struct net_device *dev, u32 desc_status)
773 if (unlikely(desc_status & RDES0_ERROR_SUMMARY_)) {
774 dev->stats.rx_errors++;
775 if (desc_status & RDES0_DESCRIPTOR_ERROR_)
776 dev->stats.rx_over_errors++;
777 else if (desc_status & (RDES0_FRAME_TOO_LONG_ |
778 RDES0_RUNT_FRAME_ | RDES0_COLLISION_SEEN_))
779 dev->stats.rx_frame_errors++;
780 else if (desc_status & RDES0_CRC_ERROR_)
781 dev->stats.rx_crc_errors++;
784 if (unlikely(desc_status & RDES0_LENGTH_ERROR_))
785 dev->stats.rx_length_errors++;
787 if (unlikely(!((desc_status & RDES0_LAST_DESCRIPTOR_) &&
788 (desc_status & RDES0_FIRST_DESCRIPTOR_))))
789 dev->stats.rx_length_errors++;
791 if (desc_status & RDES0_MULTICAST_FRAME_)
792 dev->stats.multicast++;
795 static void smsc9420_rx_handoff(struct smsc9420_pdata *pd, const int index,
798 struct net_device *dev = pd->dev;
800 u16 packet_length = (status & RDES0_FRAME_LENGTH_MASK_)
801 >> RDES0_FRAME_LENGTH_SHFT_;
803 /* remove crc from packet lendth */
809 dev->stats.rx_packets++;
810 dev->stats.rx_bytes += packet_length;
812 pci_unmap_single(pd->pdev, pd->rx_buffers[index].mapping,
813 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
814 pd->rx_buffers[index].mapping = 0;
816 skb = pd->rx_buffers[index].skb;
817 pd->rx_buffers[index].skb = NULL;
820 u16 hw_csum = get_unaligned_le16(skb_tail_pointer(skb) +
821 NET_IP_ALIGN + packet_length + 4);
822 put_unaligned_le16(hw_csum, &skb->csum);
823 skb->ip_summed = CHECKSUM_COMPLETE;
826 skb_reserve(skb, NET_IP_ALIGN);
827 skb_put(skb, packet_length);
829 skb->protocol = eth_type_trans(skb, dev);
831 netif_receive_skb(skb);
834 static int smsc9420_alloc_rx_buffer(struct smsc9420_pdata *pd, int index)
836 struct sk_buff *skb = netdev_alloc_skb(pd->dev, PKT_BUF_SZ);
839 BUG_ON(pd->rx_buffers[index].skb);
840 BUG_ON(pd->rx_buffers[index].mapping);
845 mapping = pci_map_single(pd->pdev, skb_tail_pointer(skb),
846 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
847 if (pci_dma_mapping_error(pd->pdev, mapping)) {
848 dev_kfree_skb_any(skb);
849 netif_warn(pd, rx_err, pd->dev, "pci_map_single failed!\n");
853 pd->rx_buffers[index].skb = skb;
854 pd->rx_buffers[index].mapping = mapping;
855 pd->rx_ring[index].buffer1 = mapping + NET_IP_ALIGN;
856 pd->rx_ring[index].status = RDES0_OWN_;
862 static void smsc9420_alloc_new_rx_buffers(struct smsc9420_pdata *pd)
864 while (pd->rx_ring_tail != pd->rx_ring_head) {
865 if (smsc9420_alloc_rx_buffer(pd, pd->rx_ring_tail))
868 pd->rx_ring_tail = (pd->rx_ring_tail + 1) % RX_RING_SIZE;
872 static int smsc9420_rx_poll(struct napi_struct *napi, int budget)
874 struct smsc9420_pdata *pd =
875 container_of(napi, struct smsc9420_pdata, napi);
876 struct net_device *dev = pd->dev;
877 u32 drop_frame_cnt, dma_intr_ena, status;
880 for (work_done = 0; work_done < budget; work_done++) {
882 status = pd->rx_ring[pd->rx_ring_head].status;
884 /* stop if DMAC owns this dma descriptor */
885 if (status & RDES0_OWN_)
888 smsc9420_rx_count_stats(dev, status);
889 smsc9420_rx_handoff(pd, pd->rx_ring_head, status);
890 pd->rx_ring_head = (pd->rx_ring_head + 1) % RX_RING_SIZE;
891 smsc9420_alloc_new_rx_buffers(pd);
894 drop_frame_cnt = smsc9420_reg_read(pd, MISS_FRAME_CNTR);
895 dev->stats.rx_dropped +=
896 (drop_frame_cnt & 0xFFFF) + ((drop_frame_cnt >> 17) & 0x3FF);
899 smsc9420_reg_write(pd, RX_POLL_DEMAND, 1);
900 smsc9420_pci_flush_write(pd);
902 if (work_done < budget) {
903 napi_complete(&pd->napi);
905 /* re-enable RX DMA interrupts */
906 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
907 dma_intr_ena |= (DMAC_INTR_ENA_RX_ | DMAC_INTR_ENA_NIS_);
908 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
909 smsc9420_pci_flush_write(pd);
915 smsc9420_tx_update_stats(struct net_device *dev, u32 status, u32 length)
917 if (unlikely(status & TDES0_ERROR_SUMMARY_)) {
918 dev->stats.tx_errors++;
919 if (status & (TDES0_EXCESSIVE_DEFERRAL_ |
920 TDES0_EXCESSIVE_COLLISIONS_))
921 dev->stats.tx_aborted_errors++;
923 if (status & (TDES0_LOSS_OF_CARRIER_ | TDES0_NO_CARRIER_))
924 dev->stats.tx_carrier_errors++;
926 dev->stats.tx_packets++;
927 dev->stats.tx_bytes += (length & 0x7FF);
930 if (unlikely(status & TDES0_EXCESSIVE_COLLISIONS_)) {
931 dev->stats.collisions += 16;
933 dev->stats.collisions +=
934 (status & TDES0_COLLISION_COUNT_MASK_) >>
935 TDES0_COLLISION_COUNT_SHFT_;
938 if (unlikely(status & TDES0_HEARTBEAT_FAIL_))
939 dev->stats.tx_heartbeat_errors++;
942 /* Check for completed dma transfers, update stats and free skbs */
943 static void smsc9420_complete_tx(struct net_device *dev)
945 struct smsc9420_pdata *pd = netdev_priv(dev);
947 while (pd->tx_ring_tail != pd->tx_ring_head) {
948 int index = pd->tx_ring_tail;
952 status = pd->tx_ring[index].status;
953 length = pd->tx_ring[index].length;
955 /* Check if DMA still owns this descriptor */
956 if (unlikely(TDES0_OWN_ & status))
959 smsc9420_tx_update_stats(dev, status, length);
961 BUG_ON(!pd->tx_buffers[index].skb);
962 BUG_ON(!pd->tx_buffers[index].mapping);
964 pci_unmap_single(pd->pdev, pd->tx_buffers[index].mapping,
965 pd->tx_buffers[index].skb->len, PCI_DMA_TODEVICE);
966 pd->tx_buffers[index].mapping = 0;
968 dev_kfree_skb_any(pd->tx_buffers[index].skb);
969 pd->tx_buffers[index].skb = NULL;
971 pd->tx_ring[index].buffer1 = 0;
974 pd->tx_ring_tail = (pd->tx_ring_tail + 1) % TX_RING_SIZE;
978 static netdev_tx_t smsc9420_hard_start_xmit(struct sk_buff *skb,
979 struct net_device *dev)
981 struct smsc9420_pdata *pd = netdev_priv(dev);
983 int index = pd->tx_ring_head;
985 bool about_to_take_last_desc =
986 (((pd->tx_ring_head + 2) % TX_RING_SIZE) == pd->tx_ring_tail);
988 smsc9420_complete_tx(dev);
991 BUG_ON(pd->tx_ring[index].status & TDES0_OWN_);
992 BUG_ON(pd->tx_buffers[index].skb);
993 BUG_ON(pd->tx_buffers[index].mapping);
995 mapping = pci_map_single(pd->pdev, skb->data,
996 skb->len, PCI_DMA_TODEVICE);
997 if (pci_dma_mapping_error(pd->pdev, mapping)) {
998 netif_warn(pd, tx_err, pd->dev,
999 "pci_map_single failed, dropping packet\n");
1000 return NETDEV_TX_BUSY;
1003 pd->tx_buffers[index].skb = skb;
1004 pd->tx_buffers[index].mapping = mapping;
1006 tmp_desc1 = (TDES1_LS_ | ((u32)skb->len & 0x7FF));
1007 if (unlikely(about_to_take_last_desc)) {
1008 tmp_desc1 |= TDES1_IC_;
1009 netif_stop_queue(pd->dev);
1012 /* check if we are at the last descriptor and need to set EOR */
1013 if (unlikely(index == (TX_RING_SIZE - 1)))
1014 tmp_desc1 |= TDES1_TER_;
1016 pd->tx_ring[index].buffer1 = mapping;
1017 pd->tx_ring[index].length = tmp_desc1;
1020 /* increment head */
1021 pd->tx_ring_head = (pd->tx_ring_head + 1) % TX_RING_SIZE;
1023 /* assign ownership to DMAC */
1024 pd->tx_ring[index].status = TDES0_OWN_;
1027 skb_tx_timestamp(skb);
1030 smsc9420_reg_write(pd, TX_POLL_DEMAND, 1);
1031 smsc9420_pci_flush_write(pd);
1033 return NETDEV_TX_OK;
1036 static struct net_device_stats *smsc9420_get_stats(struct net_device *dev)
1038 struct smsc9420_pdata *pd = netdev_priv(dev);
1039 u32 counter = smsc9420_reg_read(pd, MISS_FRAME_CNTR);
1040 dev->stats.rx_dropped +=
1041 (counter & 0x0000FFFF) + ((counter >> 17) & 0x000003FF);
1045 static void smsc9420_set_multicast_list(struct net_device *dev)
1047 struct smsc9420_pdata *pd = netdev_priv(dev);
1048 u32 mac_cr = smsc9420_reg_read(pd, MAC_CR);
1050 if (dev->flags & IFF_PROMISC) {
1051 netif_dbg(pd, hw, pd->dev, "Promiscuous Mode Enabled\n");
1052 mac_cr |= MAC_CR_PRMS_;
1053 mac_cr &= (~MAC_CR_MCPAS_);
1054 mac_cr &= (~MAC_CR_HPFILT_);
1055 } else if (dev->flags & IFF_ALLMULTI) {
1056 netif_dbg(pd, hw, pd->dev, "Receive all Multicast Enabled\n");
1057 mac_cr &= (~MAC_CR_PRMS_);
1058 mac_cr |= MAC_CR_MCPAS_;
1059 mac_cr &= (~MAC_CR_HPFILT_);
1060 } else if (!netdev_mc_empty(dev)) {
1061 struct netdev_hw_addr *ha;
1062 u32 hash_lo = 0, hash_hi = 0;
1064 netif_dbg(pd, hw, pd->dev, "Multicast filter enabled\n");
1065 netdev_for_each_mc_addr(ha, dev) {
1066 u32 bit_num = smsc9420_hash(ha->addr);
1067 u32 mask = 1 << (bit_num & 0x1F);
1075 smsc9420_reg_write(pd, HASHH, hash_hi);
1076 smsc9420_reg_write(pd, HASHL, hash_lo);
1078 mac_cr &= (~MAC_CR_PRMS_);
1079 mac_cr &= (~MAC_CR_MCPAS_);
1080 mac_cr |= MAC_CR_HPFILT_;
1082 netif_dbg(pd, hw, pd->dev, "Receive own packets only\n");
1083 smsc9420_reg_write(pd, HASHH, 0);
1084 smsc9420_reg_write(pd, HASHL, 0);
1086 mac_cr &= (~MAC_CR_PRMS_);
1087 mac_cr &= (~MAC_CR_MCPAS_);
1088 mac_cr &= (~MAC_CR_HPFILT_);
1091 smsc9420_reg_write(pd, MAC_CR, mac_cr);
1092 smsc9420_pci_flush_write(pd);
1095 static void smsc9420_phy_update_flowcontrol(struct smsc9420_pdata *pd)
1097 struct phy_device *phy_dev = pd->phy_dev;
1100 if (phy_dev->duplex == DUPLEX_FULL) {
1101 u16 lcladv = phy_read(phy_dev, MII_ADVERTISE);
1102 u16 rmtadv = phy_read(phy_dev, MII_LPA);
1103 u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1105 if (cap & FLOW_CTRL_RX)
1110 netif_info(pd, link, pd->dev, "rx pause %s, tx pause %s\n",
1111 cap & FLOW_CTRL_RX ? "enabled" : "disabled",
1112 cap & FLOW_CTRL_TX ? "enabled" : "disabled");
1114 netif_info(pd, link, pd->dev, "half duplex\n");
1118 smsc9420_reg_write(pd, FLOW, flow);
1121 /* Update link mode if anything has changed. Called periodically when the
1122 * PHY is in polling mode, even if nothing has changed. */
1123 static void smsc9420_phy_adjust_link(struct net_device *dev)
1125 struct smsc9420_pdata *pd = netdev_priv(dev);
1126 struct phy_device *phy_dev = pd->phy_dev;
1129 if (phy_dev->duplex != pd->last_duplex) {
1130 u32 mac_cr = smsc9420_reg_read(pd, MAC_CR);
1131 if (phy_dev->duplex) {
1132 netif_dbg(pd, link, pd->dev, "full duplex mode\n");
1133 mac_cr |= MAC_CR_FDPX_;
1135 netif_dbg(pd, link, pd->dev, "half duplex mode\n");
1136 mac_cr &= ~MAC_CR_FDPX_;
1138 smsc9420_reg_write(pd, MAC_CR, mac_cr);
1140 smsc9420_phy_update_flowcontrol(pd);
1141 pd->last_duplex = phy_dev->duplex;
1144 carrier = netif_carrier_ok(dev);
1145 if (carrier != pd->last_carrier) {
1147 netif_dbg(pd, link, pd->dev, "carrier OK\n");
1149 netif_dbg(pd, link, pd->dev, "no carrier\n");
1150 pd->last_carrier = carrier;
1154 static int smsc9420_mii_probe(struct net_device *dev)
1156 struct smsc9420_pdata *pd = netdev_priv(dev);
1157 struct phy_device *phydev = NULL;
1159 BUG_ON(pd->phy_dev);
1161 /* Device only supports internal PHY at address 1 */
1162 if (!pd->mii_bus->phy_map[1]) {
1163 netdev_err(dev, "no PHY found at address 1\n");
1167 phydev = pd->mii_bus->phy_map[1];
1168 netif_info(pd, probe, pd->dev, "PHY addr %d, phy_id 0x%08X\n",
1169 phydev->addr, phydev->phy_id);
1171 phydev = phy_connect(dev, dev_name(&phydev->dev),
1172 smsc9420_phy_adjust_link, PHY_INTERFACE_MODE_MII);
1174 if (IS_ERR(phydev)) {
1175 netdev_err(dev, "Could not attach to PHY\n");
1176 return PTR_ERR(phydev);
1179 netdev_info(dev, "attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1180 phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
1182 /* mask with MAC supported features */
1183 phydev->supported &= (PHY_BASIC_FEATURES | SUPPORTED_Pause |
1184 SUPPORTED_Asym_Pause);
1185 phydev->advertising = phydev->supported;
1187 pd->phy_dev = phydev;
1188 pd->last_duplex = -1;
1189 pd->last_carrier = -1;
1194 static int smsc9420_mii_init(struct net_device *dev)
1196 struct smsc9420_pdata *pd = netdev_priv(dev);
1197 int err = -ENXIO, i;
1199 pd->mii_bus = mdiobus_alloc();
1204 pd->mii_bus->name = DRV_MDIONAME;
1205 snprintf(pd->mii_bus->id, MII_BUS_ID_SIZE, "%x",
1206 (pd->pdev->bus->number << 8) | pd->pdev->devfn);
1207 pd->mii_bus->priv = pd;
1208 pd->mii_bus->read = smsc9420_mii_read;
1209 pd->mii_bus->write = smsc9420_mii_write;
1210 pd->mii_bus->irq = pd->phy_irq;
1211 for (i = 0; i < PHY_MAX_ADDR; ++i)
1212 pd->mii_bus->irq[i] = PHY_POLL;
1214 /* Mask all PHYs except ID 1 (internal) */
1215 pd->mii_bus->phy_mask = ~(1 << 1);
1217 if (mdiobus_register(pd->mii_bus)) {
1218 netif_warn(pd, probe, pd->dev, "Error registering mii bus\n");
1219 goto err_out_free_bus_2;
1222 if (smsc9420_mii_probe(dev) < 0) {
1223 netif_warn(pd, probe, pd->dev, "Error probing mii bus\n");
1224 goto err_out_unregister_bus_3;
1229 err_out_unregister_bus_3:
1230 mdiobus_unregister(pd->mii_bus);
1232 mdiobus_free(pd->mii_bus);
1237 static int smsc9420_alloc_tx_ring(struct smsc9420_pdata *pd)
1241 BUG_ON(!pd->tx_ring);
1243 pd->tx_buffers = kmalloc_array(TX_RING_SIZE,
1244 sizeof(struct smsc9420_ring_info),
1246 if (!pd->tx_buffers)
1249 /* Initialize the TX Ring */
1250 for (i = 0; i < TX_RING_SIZE; i++) {
1251 pd->tx_buffers[i].skb = NULL;
1252 pd->tx_buffers[i].mapping = 0;
1253 pd->tx_ring[i].status = 0;
1254 pd->tx_ring[i].length = 0;
1255 pd->tx_ring[i].buffer1 = 0;
1256 pd->tx_ring[i].buffer2 = 0;
1258 pd->tx_ring[TX_RING_SIZE - 1].length = TDES1_TER_;
1261 pd->tx_ring_head = 0;
1262 pd->tx_ring_tail = 0;
1264 smsc9420_reg_write(pd, TX_BASE_ADDR, pd->tx_dma_addr);
1265 smsc9420_pci_flush_write(pd);
1270 static int smsc9420_alloc_rx_ring(struct smsc9420_pdata *pd)
1274 BUG_ON(!pd->rx_ring);
1276 pd->rx_buffers = kmalloc_array(RX_RING_SIZE,
1277 sizeof(struct smsc9420_ring_info),
1279 if (pd->rx_buffers == NULL)
1282 /* initialize the rx ring */
1283 for (i = 0; i < RX_RING_SIZE; i++) {
1284 pd->rx_ring[i].status = 0;
1285 pd->rx_ring[i].length = PKT_BUF_SZ;
1286 pd->rx_ring[i].buffer2 = 0;
1287 pd->rx_buffers[i].skb = NULL;
1288 pd->rx_buffers[i].mapping = 0;
1290 pd->rx_ring[RX_RING_SIZE - 1].length = (PKT_BUF_SZ | RDES1_RER_);
1292 /* now allocate the entire ring of skbs */
1293 for (i = 0; i < RX_RING_SIZE; i++) {
1294 if (smsc9420_alloc_rx_buffer(pd, i)) {
1295 netif_warn(pd, ifup, pd->dev,
1296 "failed to allocate rx skb %d\n", i);
1297 goto out_free_rx_skbs;
1301 pd->rx_ring_head = 0;
1302 pd->rx_ring_tail = 0;
1304 smsc9420_reg_write(pd, VLAN1, ETH_P_8021Q);
1305 netif_dbg(pd, ifup, pd->dev, "VLAN1 = 0x%08x\n",
1306 smsc9420_reg_read(pd, VLAN1));
1310 u32 coe = smsc9420_reg_read(pd, COE_CR) | RX_COE_EN;
1311 smsc9420_reg_write(pd, COE_CR, coe);
1312 netif_dbg(pd, ifup, pd->dev, "COE_CR = 0x%08x\n", coe);
1315 smsc9420_reg_write(pd, RX_BASE_ADDR, pd->rx_dma_addr);
1316 smsc9420_pci_flush_write(pd);
1321 smsc9420_free_rx_ring(pd);
1326 static int smsc9420_open(struct net_device *dev)
1328 struct smsc9420_pdata *pd = netdev_priv(dev);
1329 u32 bus_mode, mac_cr, dmac_control, int_cfg, dma_intr_ena, int_ctl;
1330 const int irq = pd->pdev->irq;
1331 unsigned long flags;
1332 int result = 0, timeout;
1334 if (!is_valid_ether_addr(dev->dev_addr)) {
1335 netif_warn(pd, ifup, pd->dev,
1336 "dev_addr is not a valid MAC address\n");
1337 result = -EADDRNOTAVAIL;
1341 netif_carrier_off(dev);
1343 /* disable, mask and acknowledge all interrupts */
1344 spin_lock_irqsave(&pd->int_lock, flags);
1345 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
1346 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1347 smsc9420_reg_write(pd, INT_CTL, 0);
1348 spin_unlock_irqrestore(&pd->int_lock, flags);
1349 smsc9420_reg_write(pd, DMAC_INTR_ENA, 0);
1350 smsc9420_reg_write(pd, INT_STAT, 0xFFFFFFFF);
1351 smsc9420_pci_flush_write(pd);
1353 result = request_irq(irq, smsc9420_isr, IRQF_SHARED, DRV_NAME, pd);
1355 netif_warn(pd, ifup, pd->dev, "Unable to use IRQ = %d\n", irq);
1360 smsc9420_dmac_soft_reset(pd);
1362 /* make sure MAC_CR is sane */
1363 smsc9420_reg_write(pd, MAC_CR, 0);
1365 smsc9420_set_mac_address(dev);
1367 /* Configure GPIO pins to drive LEDs */
1368 smsc9420_reg_write(pd, GPIO_CFG,
1369 (GPIO_CFG_LED_3_ | GPIO_CFG_LED_2_ | GPIO_CFG_LED_1_));
1371 bus_mode = BUS_MODE_DMA_BURST_LENGTH_16;
1374 bus_mode |= BUS_MODE_DBO_;
1377 smsc9420_reg_write(pd, BUS_MODE, bus_mode);
1379 smsc9420_pci_flush_write(pd);
1381 /* set bus master bridge arbitration priority for Rx and TX DMA */
1382 smsc9420_reg_write(pd, BUS_CFG, BUS_CFG_RXTXWEIGHT_4_1);
1384 smsc9420_reg_write(pd, DMAC_CONTROL,
1385 (DMAC_CONTROL_SF_ | DMAC_CONTROL_OSF_));
1387 smsc9420_pci_flush_write(pd);
1389 /* test the IRQ connection to the ISR */
1390 netif_dbg(pd, ifup, pd->dev, "Testing ISR using IRQ %d\n", irq);
1391 pd->software_irq_signal = false;
1393 spin_lock_irqsave(&pd->int_lock, flags);
1394 /* configure interrupt deassertion timer and enable interrupts */
1395 int_cfg = smsc9420_reg_read(pd, INT_CFG) | INT_CFG_IRQ_EN_;
1396 int_cfg &= ~(INT_CFG_INT_DEAS_MASK);
1397 int_cfg |= (INT_DEAS_TIME & INT_CFG_INT_DEAS_MASK);
1398 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1400 /* unmask software interrupt */
1401 int_ctl = smsc9420_reg_read(pd, INT_CTL) | INT_CTL_SW_INT_EN_;
1402 smsc9420_reg_write(pd, INT_CTL, int_ctl);
1403 spin_unlock_irqrestore(&pd->int_lock, flags);
1404 smsc9420_pci_flush_write(pd);
1408 if (pd->software_irq_signal)
1413 /* disable interrupts */
1414 spin_lock_irqsave(&pd->int_lock, flags);
1415 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
1416 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1417 spin_unlock_irqrestore(&pd->int_lock, flags);
1419 if (!pd->software_irq_signal) {
1420 netif_warn(pd, ifup, pd->dev, "ISR failed signaling test\n");
1422 goto out_free_irq_1;
1425 netif_dbg(pd, ifup, pd->dev, "ISR passed test using IRQ %d\n", irq);
1427 result = smsc9420_alloc_tx_ring(pd);
1429 netif_warn(pd, ifup, pd->dev,
1430 "Failed to Initialize tx dma ring\n");
1432 goto out_free_irq_1;
1435 result = smsc9420_alloc_rx_ring(pd);
1437 netif_warn(pd, ifup, pd->dev,
1438 "Failed to Initialize rx dma ring\n");
1440 goto out_free_tx_ring_2;
1443 result = smsc9420_mii_init(dev);
1445 netif_warn(pd, ifup, pd->dev, "Failed to initialize Phy\n");
1447 goto out_free_rx_ring_3;
1450 /* Bring the PHY up */
1451 phy_start(pd->phy_dev);
1453 napi_enable(&pd->napi);
1455 /* start tx and rx */
1456 mac_cr = smsc9420_reg_read(pd, MAC_CR) | MAC_CR_TXEN_ | MAC_CR_RXEN_;
1457 smsc9420_reg_write(pd, MAC_CR, mac_cr);
1459 dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL);
1460 dmac_control |= DMAC_CONTROL_ST_ | DMAC_CONTROL_SR_;
1461 smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control);
1462 smsc9420_pci_flush_write(pd);
1464 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
1466 (DMAC_INTR_ENA_TX_ | DMAC_INTR_ENA_RX_ | DMAC_INTR_ENA_NIS_);
1467 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
1468 smsc9420_pci_flush_write(pd);
1470 netif_wake_queue(dev);
1472 smsc9420_reg_write(pd, RX_POLL_DEMAND, 1);
1474 /* enable interrupts */
1475 spin_lock_irqsave(&pd->int_lock, flags);
1476 int_cfg = smsc9420_reg_read(pd, INT_CFG) | INT_CFG_IRQ_EN_;
1477 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1478 spin_unlock_irqrestore(&pd->int_lock, flags);
1483 smsc9420_free_rx_ring(pd);
1485 smsc9420_free_tx_ring(pd);
1494 static int smsc9420_suspend(struct pci_dev *pdev, pm_message_t state)
1496 struct net_device *dev = pci_get_drvdata(pdev);
1497 struct smsc9420_pdata *pd = netdev_priv(dev);
1501 /* disable interrupts */
1502 spin_lock_irqsave(&pd->int_lock, flags);
1503 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
1504 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1505 spin_unlock_irqrestore(&pd->int_lock, flags);
1507 if (netif_running(dev)) {
1508 netif_tx_disable(dev);
1509 smsc9420_stop_tx(pd);
1510 smsc9420_free_tx_ring(pd);
1512 napi_disable(&pd->napi);
1513 smsc9420_stop_rx(pd);
1514 smsc9420_free_rx_ring(pd);
1516 free_irq(pd->pdev->irq, pd);
1518 netif_device_detach(dev);
1521 pci_save_state(pdev);
1522 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
1523 pci_disable_device(pdev);
1524 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1529 static int smsc9420_resume(struct pci_dev *pdev)
1531 struct net_device *dev = pci_get_drvdata(pdev);
1532 struct smsc9420_pdata *pd = netdev_priv(dev);
1535 pci_set_power_state(pdev, PCI_D0);
1536 pci_restore_state(pdev);
1538 err = pci_enable_device(pdev);
1542 pci_set_master(pdev);
1544 err = pci_enable_wake(pdev, 0, 0);
1546 netif_warn(pd, ifup, pd->dev, "pci_enable_wake failed: %d\n",
1549 if (netif_running(dev)) {
1550 /* FIXME: gross. It looks like ancient PM relic.*/
1551 err = smsc9420_open(dev);
1552 netif_device_attach(dev);
1557 #endif /* CONFIG_PM */
1559 static const struct net_device_ops smsc9420_netdev_ops = {
1560 .ndo_open = smsc9420_open,
1561 .ndo_stop = smsc9420_stop,
1562 .ndo_start_xmit = smsc9420_hard_start_xmit,
1563 .ndo_get_stats = smsc9420_get_stats,
1564 .ndo_set_rx_mode = smsc9420_set_multicast_list,
1565 .ndo_do_ioctl = smsc9420_do_ioctl,
1566 .ndo_validate_addr = eth_validate_addr,
1567 .ndo_set_mac_address = eth_mac_addr,
1568 #ifdef CONFIG_NET_POLL_CONTROLLER
1569 .ndo_poll_controller = smsc9420_poll_controller,
1570 #endif /* CONFIG_NET_POLL_CONTROLLER */
1574 smsc9420_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1576 struct net_device *dev;
1577 struct smsc9420_pdata *pd;
1578 void __iomem *virt_addr;
1582 pr_info("%s version %s\n", DRV_DESCRIPTION, DRV_VERSION);
1584 /* First do the PCI initialisation */
1585 result = pci_enable_device(pdev);
1586 if (unlikely(result)) {
1587 pr_err("Cannot enable smsc9420\n");
1591 pci_set_master(pdev);
1593 dev = alloc_etherdev(sizeof(*pd));
1595 goto out_disable_pci_device_1;
1597 SET_NETDEV_DEV(dev, &pdev->dev);
1599 if (!(pci_resource_flags(pdev, SMSC_BAR) & IORESOURCE_MEM)) {
1600 netdev_err(dev, "Cannot find PCI device base address\n");
1601 goto out_free_netdev_2;
1604 if ((pci_request_regions(pdev, DRV_NAME))) {
1605 netdev_err(dev, "Cannot obtain PCI resources, aborting\n");
1606 goto out_free_netdev_2;
1609 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
1610 netdev_err(dev, "No usable DMA configuration, aborting\n");
1611 goto out_free_regions_3;
1614 virt_addr = ioremap(pci_resource_start(pdev, SMSC_BAR),
1615 pci_resource_len(pdev, SMSC_BAR));
1617 netdev_err(dev, "Cannot map device registers, aborting\n");
1618 goto out_free_regions_3;
1621 /* registers are double mapped with 0 offset for LE and 0x200 for BE */
1622 virt_addr += LAN9420_CPSR_ENDIAN_OFFSET;
1624 pd = netdev_priv(dev);
1626 /* pci descriptors are created in the PCI consistent area */
1627 pd->rx_ring = pci_alloc_consistent(pdev,
1628 sizeof(struct smsc9420_dma_desc) * RX_RING_SIZE +
1629 sizeof(struct smsc9420_dma_desc) * TX_RING_SIZE,
1635 /* descriptors are aligned due to the nature of pci_alloc_consistent */
1636 pd->tx_ring = (pd->rx_ring + RX_RING_SIZE);
1637 pd->tx_dma_addr = pd->rx_dma_addr +
1638 sizeof(struct smsc9420_dma_desc) * RX_RING_SIZE;
1642 pd->ioaddr = virt_addr;
1643 pd->msg_enable = smsc_debug;
1646 netif_dbg(pd, probe, pd->dev, "lan_base=0x%08lx\n", (ulong)virt_addr);
1648 id_rev = smsc9420_reg_read(pd, ID_REV);
1649 switch (id_rev & 0xFFFF0000) {
1651 netif_info(pd, probe, pd->dev,
1652 "LAN9420 identified, ID_REV=0x%08X\n", id_rev);
1655 netif_warn(pd, probe, pd->dev, "LAN9420 NOT identified\n");
1656 netif_warn(pd, probe, pd->dev, "ID_REV=0x%08X\n", id_rev);
1657 goto out_free_dmadesc_5;
1660 smsc9420_dmac_soft_reset(pd);
1661 smsc9420_eeprom_reload(pd);
1662 smsc9420_check_mac_address(dev);
1664 dev->netdev_ops = &smsc9420_netdev_ops;
1665 dev->ethtool_ops = &smsc9420_ethtool_ops;
1667 netif_napi_add(dev, &pd->napi, smsc9420_rx_poll, NAPI_WEIGHT);
1669 result = register_netdev(dev);
1671 netif_warn(pd, probe, pd->dev, "error %i registering device\n",
1673 goto out_free_dmadesc_5;
1676 pci_set_drvdata(pdev, dev);
1678 spin_lock_init(&pd->int_lock);
1679 spin_lock_init(&pd->phy_lock);
1681 dev_info(&dev->dev, "MAC Address: %pM\n", dev->dev_addr);
1686 pci_free_consistent(pdev, sizeof(struct smsc9420_dma_desc) *
1687 (RX_RING_SIZE + TX_RING_SIZE), pd->rx_ring, pd->rx_dma_addr);
1689 iounmap(virt_addr - LAN9420_CPSR_ENDIAN_OFFSET);
1691 pci_release_regions(pdev);
1694 out_disable_pci_device_1:
1695 pci_disable_device(pdev);
1700 static void smsc9420_remove(struct pci_dev *pdev)
1702 struct net_device *dev;
1703 struct smsc9420_pdata *pd;
1705 dev = pci_get_drvdata(pdev);
1709 pd = netdev_priv(dev);
1710 unregister_netdev(dev);
1712 /* tx_buffers and rx_buffers are freed in stop */
1713 BUG_ON(pd->tx_buffers);
1714 BUG_ON(pd->rx_buffers);
1716 BUG_ON(!pd->tx_ring);
1717 BUG_ON(!pd->rx_ring);
1719 pci_free_consistent(pdev, sizeof(struct smsc9420_dma_desc) *
1720 (RX_RING_SIZE + TX_RING_SIZE), pd->rx_ring, pd->rx_dma_addr);
1722 iounmap(pd->ioaddr - LAN9420_CPSR_ENDIAN_OFFSET);
1723 pci_release_regions(pdev);
1725 pci_disable_device(pdev);
1728 static struct pci_driver smsc9420_driver = {
1730 .id_table = smsc9420_id_table,
1731 .probe = smsc9420_probe,
1732 .remove = smsc9420_remove,
1734 .suspend = smsc9420_suspend,
1735 .resume = smsc9420_resume,
1736 #endif /* CONFIG_PM */
1739 static int __init smsc9420_init_module(void)
1741 smsc_debug = netif_msg_init(debug, SMSC_MSG_DEFAULT);
1743 return pci_register_driver(&smsc9420_driver);
1746 static void __exit smsc9420_exit_module(void)
1748 pci_unregister_driver(&smsc9420_driver);
1751 module_init(smsc9420_init_module);
1752 module_exit(smsc9420_exit_module);