1 /****************************************************************************
2 * Driver for Solarflare network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2005-2013 Solarflare Communications Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
11 #include <linux/pci.h>
12 #include <linux/tcp.h>
15 #include <linux/ipv6.h>
16 #include <linux/slab.h>
18 #include <linux/if_ether.h>
19 #include <linux/highmem.h>
20 #include <linux/cache.h>
21 #include "net_driver.h"
25 #include "workarounds.h"
26 #include "ef10_regs.h"
30 #define EFX_PIOBUF_SIZE_MAX ER_DZ_TX_PIOBUF_SIZE
31 #define EFX_PIOBUF_SIZE_DEF ALIGN(256, L1_CACHE_BYTES)
32 unsigned int efx_piobuf_size __read_mostly = EFX_PIOBUF_SIZE_DEF;
34 #endif /* EFX_USE_PIO */
36 static inline unsigned int
37 efx_tx_queue_get_insert_index(const struct efx_tx_queue *tx_queue)
39 return tx_queue->insert_count & tx_queue->ptr_mask;
42 static inline struct efx_tx_buffer *
43 __efx_tx_queue_get_insert_buffer(const struct efx_tx_queue *tx_queue)
45 return &tx_queue->buffer[efx_tx_queue_get_insert_index(tx_queue)];
48 static inline struct efx_tx_buffer *
49 efx_tx_queue_get_insert_buffer(const struct efx_tx_queue *tx_queue)
51 struct efx_tx_buffer *buffer =
52 __efx_tx_queue_get_insert_buffer(tx_queue);
54 EFX_BUG_ON_PARANOID(buffer->len);
55 EFX_BUG_ON_PARANOID(buffer->flags);
56 EFX_BUG_ON_PARANOID(buffer->unmap_len);
61 static void efx_dequeue_buffer(struct efx_tx_queue *tx_queue,
62 struct efx_tx_buffer *buffer,
63 unsigned int *pkts_compl,
64 unsigned int *bytes_compl)
66 if (buffer->unmap_len) {
67 struct device *dma_dev = &tx_queue->efx->pci_dev->dev;
68 dma_addr_t unmap_addr = buffer->dma_addr - buffer->dma_offset;
69 if (buffer->flags & EFX_TX_BUF_MAP_SINGLE)
70 dma_unmap_single(dma_dev, unmap_addr, buffer->unmap_len,
73 dma_unmap_page(dma_dev, unmap_addr, buffer->unmap_len,
75 buffer->unmap_len = 0;
78 if (buffer->flags & EFX_TX_BUF_SKB) {
80 (*bytes_compl) += buffer->skb->len;
81 dev_kfree_skb_any((struct sk_buff *) buffer->skb);
82 netif_vdbg(tx_queue->efx, tx_done, tx_queue->efx->net_dev,
83 "TX queue %d transmission id %x complete\n",
84 tx_queue->queue, tx_queue->read_count);
85 } else if (buffer->flags & EFX_TX_BUF_HEAP) {
86 kfree(buffer->heap_buf);
93 static int efx_enqueue_skb_tso(struct efx_tx_queue *tx_queue,
96 static inline unsigned
97 efx_max_tx_len(struct efx_nic *efx, dma_addr_t dma_addr)
99 /* Depending on the NIC revision, we can use descriptor
100 * lengths up to 8K or 8K-1. However, since PCI Express
101 * devices must split read requests at 4K boundaries, there is
102 * little benefit from using descriptors that cross those
103 * boundaries and we keep things simple by not doing so.
105 unsigned len = (~dma_addr & (EFX_PAGE_SIZE - 1)) + 1;
107 /* Work around hardware bug for unaligned buffers. */
108 if (EFX_WORKAROUND_5391(efx) && (dma_addr & 0xf))
109 len = min_t(unsigned, len, 512 - (dma_addr & 0xf));
114 unsigned int efx_tx_max_skb_descs(struct efx_nic *efx)
116 /* Header and payload descriptor for each output segment, plus
117 * one for every input fragment boundary within a segment
119 unsigned int max_descs = EFX_TSO_MAX_SEGS * 2 + MAX_SKB_FRAGS;
121 /* Possibly one more per segment for the alignment workaround,
122 * or for option descriptors
124 if (EFX_WORKAROUND_5391(efx) || efx_nic_rev(efx) >= EFX_REV_HUNT_A0)
125 max_descs += EFX_TSO_MAX_SEGS;
127 /* Possibly more for PCIe page boundaries within input fragments */
128 if (PAGE_SIZE > EFX_PAGE_SIZE)
129 max_descs += max_t(unsigned int, MAX_SKB_FRAGS,
130 DIV_ROUND_UP(GSO_MAX_SIZE, EFX_PAGE_SIZE));
135 /* Get partner of a TX queue, seen as part of the same net core queue */
136 static struct efx_tx_queue *efx_tx_queue_partner(struct efx_tx_queue *tx_queue)
138 if (tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD)
139 return tx_queue - EFX_TXQ_TYPE_OFFLOAD;
141 return tx_queue + EFX_TXQ_TYPE_OFFLOAD;
144 static void efx_tx_maybe_stop_queue(struct efx_tx_queue *txq1)
146 /* We need to consider both queues that the net core sees as one */
147 struct efx_tx_queue *txq2 = efx_tx_queue_partner(txq1);
148 struct efx_nic *efx = txq1->efx;
149 unsigned int fill_level;
151 fill_level = max(txq1->insert_count - txq1->old_read_count,
152 txq2->insert_count - txq2->old_read_count);
153 if (likely(fill_level < efx->txq_stop_thresh))
156 /* We used the stale old_read_count above, which gives us a
157 * pessimistic estimate of the fill level (which may even
158 * validly be >= efx->txq_entries). Now try again using
159 * read_count (more likely to be a cache miss).
161 * If we read read_count and then conditionally stop the
162 * queue, it is possible for the completion path to race with
163 * us and complete all outstanding descriptors in the middle,
164 * after which there will be no more completions to wake it.
165 * Therefore we stop the queue first, then read read_count
166 * (with a memory barrier to ensure the ordering), then
167 * restart the queue if the fill level turns out to be low
170 netif_tx_stop_queue(txq1->core_txq);
172 txq1->old_read_count = ACCESS_ONCE(txq1->read_count);
173 txq2->old_read_count = ACCESS_ONCE(txq2->read_count);
175 fill_level = max(txq1->insert_count - txq1->old_read_count,
176 txq2->insert_count - txq2->old_read_count);
177 EFX_BUG_ON_PARANOID(fill_level >= efx->txq_entries);
178 if (likely(fill_level < efx->txq_stop_thresh)) {
180 if (likely(!efx->loopback_selftest))
181 netif_tx_start_queue(txq1->core_txq);
187 struct efx_short_copy_buffer {
189 u8 buf[L1_CACHE_BYTES];
192 /* Copy to PIO, respecting that writes to PIO buffers must be dword aligned.
193 * Advances piobuf pointer. Leaves additional data in the copy buffer.
195 static void efx_memcpy_toio_aligned(struct efx_nic *efx, u8 __iomem **piobuf,
197 struct efx_short_copy_buffer *copy_buf)
199 int block_len = len & ~(sizeof(copy_buf->buf) - 1);
201 memcpy_toio(*piobuf, data, block_len);
202 *piobuf += block_len;
207 BUG_ON(copy_buf->used);
208 BUG_ON(len > sizeof(copy_buf->buf));
209 memcpy(copy_buf->buf, data, len);
210 copy_buf->used = len;
214 /* Copy to PIO, respecting dword alignment, popping data from copy buffer first.
215 * Advances piobuf pointer. Leaves additional data in the copy buffer.
217 static void efx_memcpy_toio_aligned_cb(struct efx_nic *efx, u8 __iomem **piobuf,
219 struct efx_short_copy_buffer *copy_buf)
221 if (copy_buf->used) {
222 /* if the copy buffer is partially full, fill it up and write */
224 min_t(int, sizeof(copy_buf->buf) - copy_buf->used, len);
226 memcpy(copy_buf->buf + copy_buf->used, data, copy_to_buf);
227 copy_buf->used += copy_to_buf;
229 /* if we didn't fill it up then we're done for now */
230 if (copy_buf->used < sizeof(copy_buf->buf))
233 memcpy_toio(*piobuf, copy_buf->buf, sizeof(copy_buf->buf));
234 *piobuf += sizeof(copy_buf->buf);
240 efx_memcpy_toio_aligned(efx, piobuf, data, len, copy_buf);
243 static void efx_flush_copy_buffer(struct efx_nic *efx, u8 __iomem *piobuf,
244 struct efx_short_copy_buffer *copy_buf)
246 /* if there's anything in it, write the whole buffer, including junk */
248 memcpy_toio(piobuf, copy_buf->buf, sizeof(copy_buf->buf));
251 /* Traverse skb structure and copy fragments in to PIO buffer.
252 * Advances piobuf pointer.
254 static void efx_skb_copy_bits_to_pio(struct efx_nic *efx, struct sk_buff *skb,
256 struct efx_short_copy_buffer *copy_buf)
260 efx_memcpy_toio_aligned(efx, piobuf, skb->data, skb_headlen(skb),
263 for (i = 0; i < skb_shinfo(skb)->nr_frags; ++i) {
264 skb_frag_t *f = &skb_shinfo(skb)->frags[i];
267 vaddr = kmap_atomic(skb_frag_page(f));
269 efx_memcpy_toio_aligned_cb(efx, piobuf, vaddr + f->page_offset,
270 skb_frag_size(f), copy_buf);
271 kunmap_atomic(vaddr);
274 EFX_BUG_ON_PARANOID(skb_shinfo(skb)->frag_list);
277 static struct efx_tx_buffer *
278 efx_enqueue_skb_pio(struct efx_tx_queue *tx_queue, struct sk_buff *skb)
280 struct efx_tx_buffer *buffer =
281 efx_tx_queue_get_insert_buffer(tx_queue);
282 u8 __iomem *piobuf = tx_queue->piobuf;
284 /* Copy to PIO buffer. Ensure the writes are padded to the end
285 * of a cache line, as this is required for write-combining to be
286 * effective on at least x86.
289 if (skb_shinfo(skb)->nr_frags) {
290 /* The size of the copy buffer will ensure all writes
291 * are the size of a cache line.
293 struct efx_short_copy_buffer copy_buf;
297 efx_skb_copy_bits_to_pio(tx_queue->efx, skb,
299 efx_flush_copy_buffer(tx_queue->efx, piobuf, ©_buf);
301 /* Pad the write to the size of a cache line.
302 * We can do this because we know the skb_shared_info sruct is
303 * after the source, and the destination buffer is big enough.
305 BUILD_BUG_ON(L1_CACHE_BYTES >
306 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)));
307 memcpy_toio(tx_queue->piobuf, skb->data,
308 ALIGN(skb->len, L1_CACHE_BYTES));
311 EFX_POPULATE_QWORD_5(buffer->option,
312 ESF_DZ_TX_DESC_IS_OPT, 1,
313 ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_PIO,
314 ESF_DZ_TX_PIO_CONT, 0,
315 ESF_DZ_TX_PIO_BYTE_CNT, skb->len,
316 ESF_DZ_TX_PIO_BUF_ADDR,
317 tx_queue->piobuf_offset);
318 ++tx_queue->pio_packets;
319 ++tx_queue->insert_count;
322 #endif /* EFX_USE_PIO */
325 * Add a socket buffer to a TX queue
327 * This maps all fragments of a socket buffer for DMA and adds them to
328 * the TX queue. The queue's insert pointer will be incremented by
329 * the number of fragments in the socket buffer.
331 * If any DMA mapping fails, any mapped fragments will be unmapped,
332 * the queue's insert pointer will be restored to its original value.
334 * This function is split out from efx_hard_start_xmit to allow the
335 * loopback test to direct packets via specific TX queues.
337 * Returns NETDEV_TX_OK.
338 * You must hold netif_tx_lock() to call this function.
340 netdev_tx_t efx_enqueue_skb(struct efx_tx_queue *tx_queue, struct sk_buff *skb)
342 struct efx_nic *efx = tx_queue->efx;
343 struct device *dma_dev = &efx->pci_dev->dev;
344 struct efx_tx_buffer *buffer;
345 skb_frag_t *fragment;
346 unsigned int len, unmap_len = 0;
347 dma_addr_t dma_addr, unmap_addr = 0;
348 unsigned int dma_len;
349 unsigned short dma_flags;
352 EFX_BUG_ON_PARANOID(tx_queue->write_count != tx_queue->insert_count);
354 if (skb_shinfo(skb)->gso_size)
355 return efx_enqueue_skb_tso(tx_queue, skb);
357 /* Get size of the initial fragment */
358 len = skb_headlen(skb);
360 /* Pad if necessary */
361 if (EFX_WORKAROUND_15592(efx) && skb->len <= 32) {
362 EFX_BUG_ON_PARANOID(skb->data_len);
364 if (skb_pad(skb, len - skb->len))
368 /* Consider using PIO for short packets */
370 if (skb->len <= efx_piobuf_size && tx_queue->piobuf &&
371 efx_nic_tx_is_empty(tx_queue) &&
372 efx_nic_tx_is_empty(efx_tx_queue_partner(tx_queue))) {
373 buffer = efx_enqueue_skb_pio(tx_queue, skb);
374 dma_flags = EFX_TX_BUF_OPTION;
379 /* Map for DMA. Use dma_map_single rather than dma_map_page
380 * since this is more efficient on machines with sparse
383 dma_flags = EFX_TX_BUF_MAP_SINGLE;
384 dma_addr = dma_map_single(dma_dev, skb->data, len, PCI_DMA_TODEVICE);
386 /* Process all fragments */
388 if (unlikely(dma_mapping_error(dma_dev, dma_addr)))
391 /* Store fields for marking in the per-fragment final
394 unmap_addr = dma_addr;
396 /* Add to TX queue, splitting across DMA boundaries */
398 buffer = efx_tx_queue_get_insert_buffer(tx_queue);
400 dma_len = efx_max_tx_len(efx, dma_addr);
401 if (likely(dma_len >= len))
404 /* Fill out per descriptor fields */
405 buffer->len = dma_len;
406 buffer->dma_addr = dma_addr;
407 buffer->flags = EFX_TX_BUF_CONT;
410 ++tx_queue->insert_count;
413 /* Transfer ownership of the unmapping to the final buffer */
414 buffer->flags = EFX_TX_BUF_CONT | dma_flags;
415 buffer->unmap_len = unmap_len;
416 buffer->dma_offset = buffer->dma_addr - unmap_addr;
419 /* Get address and size of next fragment */
420 if (i >= skb_shinfo(skb)->nr_frags)
422 fragment = &skb_shinfo(skb)->frags[i];
423 len = skb_frag_size(fragment);
427 dma_addr = skb_frag_dma_map(dma_dev, fragment, 0, len,
431 /* Transfer ownership of the skb to the final buffer */
434 buffer->flags = EFX_TX_BUF_SKB | dma_flags;
436 netdev_tx_sent_queue(tx_queue->core_txq, skb->len);
438 /* Pass off to hardware */
439 efx_nic_push_buffers(tx_queue);
441 efx_tx_maybe_stop_queue(tx_queue);
446 netif_err(efx, tx_err, efx->net_dev,
447 " TX queue %d could not map skb with %d bytes %d "
448 "fragments for DMA\n", tx_queue->queue, skb->len,
449 skb_shinfo(skb)->nr_frags + 1);
451 /* Mark the packet as transmitted, and free the SKB ourselves */
452 dev_kfree_skb_any(skb);
454 /* Work backwards until we hit the original insert pointer value */
455 while (tx_queue->insert_count != tx_queue->write_count) {
456 unsigned int pkts_compl = 0, bytes_compl = 0;
457 --tx_queue->insert_count;
458 buffer = __efx_tx_queue_get_insert_buffer(tx_queue);
459 efx_dequeue_buffer(tx_queue, buffer, &pkts_compl, &bytes_compl);
462 /* Free the fragment we were mid-way through pushing */
464 if (dma_flags & EFX_TX_BUF_MAP_SINGLE)
465 dma_unmap_single(dma_dev, unmap_addr, unmap_len,
468 dma_unmap_page(dma_dev, unmap_addr, unmap_len,
475 /* Remove packets from the TX queue
477 * This removes packets from the TX queue, up to and including the
480 static void efx_dequeue_buffers(struct efx_tx_queue *tx_queue,
482 unsigned int *pkts_compl,
483 unsigned int *bytes_compl)
485 struct efx_nic *efx = tx_queue->efx;
486 unsigned int stop_index, read_ptr;
488 stop_index = (index + 1) & tx_queue->ptr_mask;
489 read_ptr = tx_queue->read_count & tx_queue->ptr_mask;
491 while (read_ptr != stop_index) {
492 struct efx_tx_buffer *buffer = &tx_queue->buffer[read_ptr];
494 if (!(buffer->flags & EFX_TX_BUF_OPTION) &&
495 unlikely(buffer->len == 0)) {
496 netif_err(efx, tx_err, efx->net_dev,
497 "TX queue %d spurious TX completion id %x\n",
498 tx_queue->queue, read_ptr);
499 efx_schedule_reset(efx, RESET_TYPE_TX_SKIP);
503 efx_dequeue_buffer(tx_queue, buffer, pkts_compl, bytes_compl);
505 ++tx_queue->read_count;
506 read_ptr = tx_queue->read_count & tx_queue->ptr_mask;
510 /* Initiate a packet transmission. We use one channel per CPU
511 * (sharing when we have more CPUs than channels). On Falcon, the TX
512 * completion events will be directed back to the CPU that transmitted
513 * the packet, which should be cache-efficient.
515 * Context: non-blocking.
516 * Note that returning anything other than NETDEV_TX_OK will cause the
517 * OS to free the skb.
519 netdev_tx_t efx_hard_start_xmit(struct sk_buff *skb,
520 struct net_device *net_dev)
522 struct efx_nic *efx = netdev_priv(net_dev);
523 struct efx_tx_queue *tx_queue;
524 unsigned index, type;
526 EFX_WARN_ON_PARANOID(!netif_device_present(net_dev));
528 /* PTP "event" packet */
529 if (unlikely(efx_xmit_with_hwtstamp(skb)) &&
530 unlikely(efx_ptp_is_ptp_tx(efx, skb))) {
531 return efx_ptp_tx(efx, skb);
534 index = skb_get_queue_mapping(skb);
535 type = skb->ip_summed == CHECKSUM_PARTIAL ? EFX_TXQ_TYPE_OFFLOAD : 0;
536 if (index >= efx->n_tx_channels) {
537 index -= efx->n_tx_channels;
538 type |= EFX_TXQ_TYPE_HIGHPRI;
540 tx_queue = efx_get_tx_queue(efx, index, type);
542 return efx_enqueue_skb(tx_queue, skb);
545 void efx_init_tx_queue_core_txq(struct efx_tx_queue *tx_queue)
547 struct efx_nic *efx = tx_queue->efx;
549 /* Must be inverse of queue lookup in efx_hard_start_xmit() */
551 netdev_get_tx_queue(efx->net_dev,
552 tx_queue->queue / EFX_TXQ_TYPES +
553 ((tx_queue->queue & EFX_TXQ_TYPE_HIGHPRI) ?
554 efx->n_tx_channels : 0));
557 int efx_setup_tc(struct net_device *net_dev, u8 num_tc)
559 struct efx_nic *efx = netdev_priv(net_dev);
560 struct efx_channel *channel;
561 struct efx_tx_queue *tx_queue;
565 if (efx_nic_rev(efx) < EFX_REV_FALCON_B0 || num_tc > EFX_MAX_TX_TC)
568 if (num_tc == net_dev->num_tc)
571 for (tc = 0; tc < num_tc; tc++) {
572 net_dev->tc_to_txq[tc].offset = tc * efx->n_tx_channels;
573 net_dev->tc_to_txq[tc].count = efx->n_tx_channels;
576 if (num_tc > net_dev->num_tc) {
577 /* Initialise high-priority queues as necessary */
578 efx_for_each_channel(channel, efx) {
579 efx_for_each_possible_channel_tx_queue(tx_queue,
581 if (!(tx_queue->queue & EFX_TXQ_TYPE_HIGHPRI))
583 if (!tx_queue->buffer) {
584 rc = efx_probe_tx_queue(tx_queue);
588 if (!tx_queue->initialised)
589 efx_init_tx_queue(tx_queue);
590 efx_init_tx_queue_core_txq(tx_queue);
594 /* Reduce number of classes before number of queues */
595 net_dev->num_tc = num_tc;
598 rc = netif_set_real_num_tx_queues(net_dev,
599 max_t(int, num_tc, 1) *
604 /* Do not destroy high-priority queues when they become
605 * unused. We would have to flush them first, and it is
606 * fairly difficult to flush a subset of TX queues. Leave
607 * it to efx_fini_channels().
610 net_dev->num_tc = num_tc;
614 void efx_xmit_done(struct efx_tx_queue *tx_queue, unsigned int index)
617 struct efx_nic *efx = tx_queue->efx;
618 struct efx_tx_queue *txq2;
619 unsigned int pkts_compl = 0, bytes_compl = 0;
621 EFX_BUG_ON_PARANOID(index > tx_queue->ptr_mask);
623 efx_dequeue_buffers(tx_queue, index, &pkts_compl, &bytes_compl);
624 netdev_tx_completed_queue(tx_queue->core_txq, pkts_compl, bytes_compl);
627 ++tx_queue->merge_events;
629 /* See if we need to restart the netif queue. This memory
630 * barrier ensures that we write read_count (inside
631 * efx_dequeue_buffers()) before reading the queue status.
634 if (unlikely(netif_tx_queue_stopped(tx_queue->core_txq)) &&
635 likely(efx->port_enabled) &&
636 likely(netif_device_present(efx->net_dev))) {
637 txq2 = efx_tx_queue_partner(tx_queue);
638 fill_level = max(tx_queue->insert_count - tx_queue->read_count,
639 txq2->insert_count - txq2->read_count);
640 if (fill_level <= efx->txq_wake_thresh)
641 netif_tx_wake_queue(tx_queue->core_txq);
644 /* Check whether the hardware queue is now empty */
645 if ((int)(tx_queue->read_count - tx_queue->old_write_count) >= 0) {
646 tx_queue->old_write_count = ACCESS_ONCE(tx_queue->write_count);
647 if (tx_queue->read_count == tx_queue->old_write_count) {
649 tx_queue->empty_read_count =
650 tx_queue->read_count | EFX_EMPTY_COUNT_VALID;
655 /* Size of page-based TSO header buffers. Larger blocks must be
656 * allocated from the heap.
658 #define TSOH_STD_SIZE 128
659 #define TSOH_PER_PAGE (PAGE_SIZE / TSOH_STD_SIZE)
661 /* At most half the descriptors in the queue at any time will refer to
662 * a TSO header buffer, since they must always be followed by a
663 * payload descriptor referring to an skb.
665 static unsigned int efx_tsoh_page_count(struct efx_tx_queue *tx_queue)
667 return DIV_ROUND_UP(tx_queue->ptr_mask + 1, 2 * TSOH_PER_PAGE);
670 int efx_probe_tx_queue(struct efx_tx_queue *tx_queue)
672 struct efx_nic *efx = tx_queue->efx;
673 unsigned int entries;
676 /* Create the smallest power-of-two aligned ring */
677 entries = max(roundup_pow_of_two(efx->txq_entries), EFX_MIN_DMAQ_SIZE);
678 EFX_BUG_ON_PARANOID(entries > EFX_MAX_DMAQ_SIZE);
679 tx_queue->ptr_mask = entries - 1;
681 netif_dbg(efx, probe, efx->net_dev,
682 "creating TX queue %d size %#x mask %#x\n",
683 tx_queue->queue, efx->txq_entries, tx_queue->ptr_mask);
685 /* Allocate software ring */
686 tx_queue->buffer = kcalloc(entries, sizeof(*tx_queue->buffer),
688 if (!tx_queue->buffer)
691 if (tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD) {
692 tx_queue->tsoh_page =
693 kcalloc(efx_tsoh_page_count(tx_queue),
694 sizeof(tx_queue->tsoh_page[0]), GFP_KERNEL);
695 if (!tx_queue->tsoh_page) {
701 /* Allocate hardware ring */
702 rc = efx_nic_probe_tx(tx_queue);
709 kfree(tx_queue->tsoh_page);
710 tx_queue->tsoh_page = NULL;
712 kfree(tx_queue->buffer);
713 tx_queue->buffer = NULL;
717 void efx_init_tx_queue(struct efx_tx_queue *tx_queue)
719 netif_dbg(tx_queue->efx, drv, tx_queue->efx->net_dev,
720 "initialising TX queue %d\n", tx_queue->queue);
722 tx_queue->insert_count = 0;
723 tx_queue->write_count = 0;
724 tx_queue->old_write_count = 0;
725 tx_queue->read_count = 0;
726 tx_queue->old_read_count = 0;
727 tx_queue->empty_read_count = 0 | EFX_EMPTY_COUNT_VALID;
729 /* Set up TX descriptor ring */
730 efx_nic_init_tx(tx_queue);
732 tx_queue->initialised = true;
735 void efx_fini_tx_queue(struct efx_tx_queue *tx_queue)
737 struct efx_tx_buffer *buffer;
739 netif_dbg(tx_queue->efx, drv, tx_queue->efx->net_dev,
740 "shutting down TX queue %d\n", tx_queue->queue);
742 if (!tx_queue->buffer)
745 /* Free any buffers left in the ring */
746 while (tx_queue->read_count != tx_queue->write_count) {
747 unsigned int pkts_compl = 0, bytes_compl = 0;
748 buffer = &tx_queue->buffer[tx_queue->read_count & tx_queue->ptr_mask];
749 efx_dequeue_buffer(tx_queue, buffer, &pkts_compl, &bytes_compl);
751 ++tx_queue->read_count;
753 netdev_tx_reset_queue(tx_queue->core_txq);
756 void efx_remove_tx_queue(struct efx_tx_queue *tx_queue)
760 if (!tx_queue->buffer)
763 netif_dbg(tx_queue->efx, drv, tx_queue->efx->net_dev,
764 "destroying TX queue %d\n", tx_queue->queue);
765 efx_nic_remove_tx(tx_queue);
767 if (tx_queue->tsoh_page) {
768 for (i = 0; i < efx_tsoh_page_count(tx_queue); i++)
769 efx_nic_free_buffer(tx_queue->efx,
770 &tx_queue->tsoh_page[i]);
771 kfree(tx_queue->tsoh_page);
772 tx_queue->tsoh_page = NULL;
775 kfree(tx_queue->buffer);
776 tx_queue->buffer = NULL;
780 /* Efx TCP segmentation acceleration.
782 * Why? Because by doing it here in the driver we can go significantly
783 * faster than the GSO.
785 * Requires TX checksum offload support.
788 /* Number of bytes inserted at the start of a TSO header buffer,
789 * similar to NET_IP_ALIGN.
791 #ifdef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
792 #define TSOH_OFFSET 0
794 #define TSOH_OFFSET NET_IP_ALIGN
797 #define PTR_DIFF(p1, p2) ((u8 *)(p1) - (u8 *)(p2))
800 * struct tso_state - TSO state for an SKB
801 * @out_len: Remaining length in current segment
802 * @seqnum: Current sequence number
803 * @ipv4_id: Current IPv4 ID, host endian
804 * @packet_space: Remaining space in current packet
805 * @dma_addr: DMA address of current position
806 * @in_len: Remaining length in current SKB fragment
807 * @unmap_len: Length of SKB fragment
808 * @unmap_addr: DMA address of SKB fragment
809 * @dma_flags: TX buffer flags for DMA mapping - %EFX_TX_BUF_MAP_SINGLE or 0
810 * @protocol: Network protocol (after any VLAN header)
811 * @ip_off: Offset of IP header
812 * @tcp_off: Offset of TCP header
813 * @header_len: Number of bytes of header
814 * @ip_base_len: IPv4 tot_len or IPv6 payload_len, before TCP payload
815 * @header_dma_addr: Header DMA address, when using option descriptors
816 * @header_unmap_len: Header DMA mapped length, or 0 if not using option
819 * The state used during segmentation. It is put into this data structure
820 * just to make it easy to pass into inline functions.
823 /* Output position */
827 unsigned packet_space;
833 dma_addr_t unmap_addr;
834 unsigned short dma_flags;
838 unsigned int tcp_off;
840 unsigned int ip_base_len;
841 dma_addr_t header_dma_addr;
842 unsigned int header_unmap_len;
847 * Verify that our various assumptions about sk_buffs and the conditions
848 * under which TSO will be attempted hold true. Return the protocol number.
850 static __be16 efx_tso_check_protocol(struct sk_buff *skb)
852 __be16 protocol = skb->protocol;
854 EFX_BUG_ON_PARANOID(((struct ethhdr *)skb->data)->h_proto !=
856 if (protocol == htons(ETH_P_8021Q)) {
857 struct vlan_ethhdr *veh = (struct vlan_ethhdr *)skb->data;
858 protocol = veh->h_vlan_encapsulated_proto;
861 if (protocol == htons(ETH_P_IP)) {
862 EFX_BUG_ON_PARANOID(ip_hdr(skb)->protocol != IPPROTO_TCP);
864 EFX_BUG_ON_PARANOID(protocol != htons(ETH_P_IPV6));
865 EFX_BUG_ON_PARANOID(ipv6_hdr(skb)->nexthdr != NEXTHDR_TCP);
867 EFX_BUG_ON_PARANOID((PTR_DIFF(tcp_hdr(skb), skb->data)
868 + (tcp_hdr(skb)->doff << 2u)) >
874 static u8 *efx_tsoh_get_buffer(struct efx_tx_queue *tx_queue,
875 struct efx_tx_buffer *buffer, unsigned int len)
879 EFX_BUG_ON_PARANOID(buffer->len);
880 EFX_BUG_ON_PARANOID(buffer->flags);
881 EFX_BUG_ON_PARANOID(buffer->unmap_len);
883 if (likely(len <= TSOH_STD_SIZE - TSOH_OFFSET)) {
885 (tx_queue->insert_count & tx_queue->ptr_mask) / 2;
886 struct efx_buffer *page_buf =
887 &tx_queue->tsoh_page[index / TSOH_PER_PAGE];
889 TSOH_STD_SIZE * (index % TSOH_PER_PAGE) + TSOH_OFFSET;
891 if (unlikely(!page_buf->addr) &&
892 efx_nic_alloc_buffer(tx_queue->efx, page_buf, PAGE_SIZE,
896 result = (u8 *)page_buf->addr + offset;
897 buffer->dma_addr = page_buf->dma_addr + offset;
898 buffer->flags = EFX_TX_BUF_CONT;
900 tx_queue->tso_long_headers++;
902 buffer->heap_buf = kmalloc(TSOH_OFFSET + len, GFP_ATOMIC);
903 if (unlikely(!buffer->heap_buf))
905 result = (u8 *)buffer->heap_buf + TSOH_OFFSET;
906 buffer->flags = EFX_TX_BUF_CONT | EFX_TX_BUF_HEAP;
915 * efx_tx_queue_insert - push descriptors onto the TX queue
916 * @tx_queue: Efx TX queue
917 * @dma_addr: DMA address of fragment
918 * @len: Length of fragment
919 * @final_buffer: The final buffer inserted into the queue
921 * Push descriptors onto the TX queue.
923 static void efx_tx_queue_insert(struct efx_tx_queue *tx_queue,
924 dma_addr_t dma_addr, unsigned len,
925 struct efx_tx_buffer **final_buffer)
927 struct efx_tx_buffer *buffer;
928 struct efx_nic *efx = tx_queue->efx;
931 EFX_BUG_ON_PARANOID(len <= 0);
934 buffer = efx_tx_queue_get_insert_buffer(tx_queue);
935 ++tx_queue->insert_count;
937 EFX_BUG_ON_PARANOID(tx_queue->insert_count -
938 tx_queue->read_count >=
941 buffer->dma_addr = dma_addr;
943 dma_len = efx_max_tx_len(efx, dma_addr);
945 /* If there is enough space to send then do so */
949 buffer->len = dma_len;
950 buffer->flags = EFX_TX_BUF_CONT;
955 EFX_BUG_ON_PARANOID(!len);
957 *final_buffer = buffer;
962 * Put a TSO header into the TX queue.
964 * This is special-cased because we know that it is small enough to fit in
965 * a single fragment, and we know it doesn't cross a page boundary. It
966 * also allows us to not worry about end-of-packet etc.
968 static int efx_tso_put_header(struct efx_tx_queue *tx_queue,
969 struct efx_tx_buffer *buffer, u8 *header)
971 if (unlikely(buffer->flags & EFX_TX_BUF_HEAP)) {
972 buffer->dma_addr = dma_map_single(&tx_queue->efx->pci_dev->dev,
975 if (unlikely(dma_mapping_error(&tx_queue->efx->pci_dev->dev,
976 buffer->dma_addr))) {
977 kfree(buffer->heap_buf);
982 buffer->unmap_len = buffer->len;
983 buffer->dma_offset = 0;
984 buffer->flags |= EFX_TX_BUF_MAP_SINGLE;
987 ++tx_queue->insert_count;
992 /* Remove buffers put into a tx_queue. None of the buffers must have
995 static void efx_enqueue_unwind(struct efx_tx_queue *tx_queue)
997 struct efx_tx_buffer *buffer;
999 /* Work backwards until we hit the original insert pointer value */
1000 while (tx_queue->insert_count != tx_queue->write_count) {
1001 --tx_queue->insert_count;
1002 buffer = __efx_tx_queue_get_insert_buffer(tx_queue);
1003 efx_dequeue_buffer(tx_queue, buffer, NULL, NULL);
1008 /* Parse the SKB header and initialise state. */
1009 static int tso_start(struct tso_state *st, struct efx_nic *efx,
1010 const struct sk_buff *skb)
1012 bool use_options = efx_nic_rev(efx) >= EFX_REV_HUNT_A0;
1013 struct device *dma_dev = &efx->pci_dev->dev;
1014 unsigned int header_len, in_len;
1015 dma_addr_t dma_addr;
1017 st->ip_off = skb_network_header(skb) - skb->data;
1018 st->tcp_off = skb_transport_header(skb) - skb->data;
1019 header_len = st->tcp_off + (tcp_hdr(skb)->doff << 2u);
1020 in_len = skb_headlen(skb) - header_len;
1021 st->header_len = header_len;
1022 st->in_len = in_len;
1023 if (st->protocol == htons(ETH_P_IP)) {
1024 st->ip_base_len = st->header_len - st->ip_off;
1025 st->ipv4_id = ntohs(ip_hdr(skb)->id);
1027 st->ip_base_len = st->header_len - st->tcp_off;
1030 st->seqnum = ntohl(tcp_hdr(skb)->seq);
1032 EFX_BUG_ON_PARANOID(tcp_hdr(skb)->urg);
1033 EFX_BUG_ON_PARANOID(tcp_hdr(skb)->syn);
1034 EFX_BUG_ON_PARANOID(tcp_hdr(skb)->rst);
1036 st->out_len = skb->len - header_len;
1039 st->header_unmap_len = 0;
1041 if (likely(in_len == 0)) {
1047 dma_addr = dma_map_single(dma_dev, skb->data + header_len,
1048 in_len, DMA_TO_DEVICE);
1049 st->dma_flags = EFX_TX_BUF_MAP_SINGLE;
1050 st->dma_addr = dma_addr;
1051 st->unmap_addr = dma_addr;
1052 st->unmap_len = in_len;
1054 dma_addr = dma_map_single(dma_dev, skb->data,
1055 skb_headlen(skb), DMA_TO_DEVICE);
1056 st->header_dma_addr = dma_addr;
1057 st->header_unmap_len = skb_headlen(skb);
1059 st->dma_addr = dma_addr + header_len;
1063 return unlikely(dma_mapping_error(dma_dev, dma_addr)) ? -ENOMEM : 0;
1066 static int tso_get_fragment(struct tso_state *st, struct efx_nic *efx,
1069 st->unmap_addr = skb_frag_dma_map(&efx->pci_dev->dev, frag, 0,
1070 skb_frag_size(frag), DMA_TO_DEVICE);
1071 if (likely(!dma_mapping_error(&efx->pci_dev->dev, st->unmap_addr))) {
1073 st->unmap_len = skb_frag_size(frag);
1074 st->in_len = skb_frag_size(frag);
1075 st->dma_addr = st->unmap_addr;
1083 * tso_fill_packet_with_fragment - form descriptors for the current fragment
1084 * @tx_queue: Efx TX queue
1085 * @skb: Socket buffer
1088 * Form descriptors for the current fragment, until we reach the end
1089 * of fragment or end-of-packet.
1091 static void tso_fill_packet_with_fragment(struct efx_tx_queue *tx_queue,
1092 const struct sk_buff *skb,
1093 struct tso_state *st)
1095 struct efx_tx_buffer *buffer;
1098 if (st->in_len == 0)
1100 if (st->packet_space == 0)
1103 EFX_BUG_ON_PARANOID(st->in_len <= 0);
1104 EFX_BUG_ON_PARANOID(st->packet_space <= 0);
1106 n = min(st->in_len, st->packet_space);
1108 st->packet_space -= n;
1112 efx_tx_queue_insert(tx_queue, st->dma_addr, n, &buffer);
1114 if (st->out_len == 0) {
1115 /* Transfer ownership of the skb */
1117 buffer->flags = EFX_TX_BUF_SKB;
1118 } else if (st->packet_space != 0) {
1119 buffer->flags = EFX_TX_BUF_CONT;
1122 if (st->in_len == 0) {
1123 /* Transfer ownership of the DMA mapping */
1124 buffer->unmap_len = st->unmap_len;
1125 buffer->dma_offset = buffer->unmap_len - buffer->len;
1126 buffer->flags |= st->dma_flags;
1135 * tso_start_new_packet - generate a new header and prepare for the new packet
1136 * @tx_queue: Efx TX queue
1137 * @skb: Socket buffer
1140 * Generate a new header and prepare for the new packet. Return 0 on
1141 * success, or -%ENOMEM if failed to alloc header.
1143 static int tso_start_new_packet(struct efx_tx_queue *tx_queue,
1144 const struct sk_buff *skb,
1145 struct tso_state *st)
1147 struct efx_tx_buffer *buffer =
1148 efx_tx_queue_get_insert_buffer(tx_queue);
1149 bool is_last = st->out_len <= skb_shinfo(skb)->gso_size;
1153 st->packet_space = skb_shinfo(skb)->gso_size;
1154 tcp_flags_clear = 0x09; /* mask out FIN and PSH */
1156 st->packet_space = st->out_len;
1157 tcp_flags_clear = 0x00;
1160 if (!st->header_unmap_len) {
1161 /* Allocate and insert a DMA-mapped header buffer. */
1162 struct tcphdr *tsoh_th;
1167 header = efx_tsoh_get_buffer(tx_queue, buffer, st->header_len);
1171 tsoh_th = (struct tcphdr *)(header + st->tcp_off);
1173 /* Copy and update the headers. */
1174 memcpy(header, skb->data, st->header_len);
1176 tsoh_th->seq = htonl(st->seqnum);
1177 ((u8 *)tsoh_th)[13] &= ~tcp_flags_clear;
1179 ip_length = st->ip_base_len + st->packet_space;
1181 if (st->protocol == htons(ETH_P_IP)) {
1182 struct iphdr *tsoh_iph =
1183 (struct iphdr *)(header + st->ip_off);
1185 tsoh_iph->tot_len = htons(ip_length);
1186 tsoh_iph->id = htons(st->ipv4_id);
1188 struct ipv6hdr *tsoh_iph =
1189 (struct ipv6hdr *)(header + st->ip_off);
1191 tsoh_iph->payload_len = htons(ip_length);
1194 rc = efx_tso_put_header(tx_queue, buffer, header);
1198 /* Send the original headers with a TSO option descriptor
1201 u8 tcp_flags = ((u8 *)tcp_hdr(skb))[13] & ~tcp_flags_clear;
1203 buffer->flags = EFX_TX_BUF_OPTION;
1205 buffer->unmap_len = 0;
1206 EFX_POPULATE_QWORD_5(buffer->option,
1207 ESF_DZ_TX_DESC_IS_OPT, 1,
1208 ESF_DZ_TX_OPTION_TYPE,
1209 ESE_DZ_TX_OPTION_DESC_TSO,
1210 ESF_DZ_TX_TSO_TCP_FLAGS, tcp_flags,
1211 ESF_DZ_TX_TSO_IP_ID, st->ipv4_id,
1212 ESF_DZ_TX_TSO_TCP_SEQNO, st->seqnum);
1213 ++tx_queue->insert_count;
1215 /* We mapped the headers in tso_start(). Unmap them
1216 * when the last segment is completed.
1218 buffer = efx_tx_queue_get_insert_buffer(tx_queue);
1219 buffer->dma_addr = st->header_dma_addr;
1220 buffer->len = st->header_len;
1222 buffer->flags = EFX_TX_BUF_CONT | EFX_TX_BUF_MAP_SINGLE;
1223 buffer->unmap_len = st->header_unmap_len;
1224 buffer->dma_offset = 0;
1225 /* Ensure we only unmap them once in case of a
1226 * later DMA mapping error and rollback
1228 st->header_unmap_len = 0;
1230 buffer->flags = EFX_TX_BUF_CONT;
1231 buffer->unmap_len = 0;
1233 ++tx_queue->insert_count;
1236 st->seqnum += skb_shinfo(skb)->gso_size;
1238 /* Linux leaves suitable gaps in the IP ID space for us to fill. */
1241 ++tx_queue->tso_packets;
1248 * efx_enqueue_skb_tso - segment and transmit a TSO socket buffer
1249 * @tx_queue: Efx TX queue
1250 * @skb: Socket buffer
1252 * Context: You must hold netif_tx_lock() to call this function.
1254 * Add socket buffer @skb to @tx_queue, doing TSO or return != 0 if
1255 * @skb was not enqueued. In all cases @skb is consumed. Return
1258 static int efx_enqueue_skb_tso(struct efx_tx_queue *tx_queue,
1259 struct sk_buff *skb)
1261 struct efx_nic *efx = tx_queue->efx;
1263 struct tso_state state;
1265 /* Find the packet protocol and sanity-check it */
1266 state.protocol = efx_tso_check_protocol(skb);
1268 EFX_BUG_ON_PARANOID(tx_queue->write_count != tx_queue->insert_count);
1270 rc = tso_start(&state, efx, skb);
1274 if (likely(state.in_len == 0)) {
1275 /* Grab the first payload fragment. */
1276 EFX_BUG_ON_PARANOID(skb_shinfo(skb)->nr_frags < 1);
1278 rc = tso_get_fragment(&state, efx,
1279 skb_shinfo(skb)->frags + frag_i);
1283 /* Payload starts in the header area. */
1287 if (tso_start_new_packet(tx_queue, skb, &state) < 0)
1291 tso_fill_packet_with_fragment(tx_queue, skb, &state);
1293 /* Move onto the next fragment? */
1294 if (state.in_len == 0) {
1295 if (++frag_i >= skb_shinfo(skb)->nr_frags)
1296 /* End of payload reached. */
1298 rc = tso_get_fragment(&state, efx,
1299 skb_shinfo(skb)->frags + frag_i);
1304 /* Start at new packet? */
1305 if (state.packet_space == 0 &&
1306 tso_start_new_packet(tx_queue, skb, &state) < 0)
1310 netdev_tx_sent_queue(tx_queue->core_txq, skb->len);
1312 /* Pass off to hardware */
1313 efx_nic_push_buffers(tx_queue);
1315 efx_tx_maybe_stop_queue(tx_queue);
1317 tx_queue->tso_bursts++;
1318 return NETDEV_TX_OK;
1321 netif_err(efx, tx_err, efx->net_dev,
1322 "Out of memory for TSO headers, or DMA mapping error\n");
1323 dev_kfree_skb_any(skb);
1325 /* Free the DMA mapping we were in the process of writing out */
1326 if (state.unmap_len) {
1327 if (state.dma_flags & EFX_TX_BUF_MAP_SINGLE)
1328 dma_unmap_single(&efx->pci_dev->dev, state.unmap_addr,
1329 state.unmap_len, DMA_TO_DEVICE);
1331 dma_unmap_page(&efx->pci_dev->dev, state.unmap_addr,
1332 state.unmap_len, DMA_TO_DEVICE);
1335 /* Free the header DMA mapping, if using option descriptors */
1336 if (state.header_unmap_len)
1337 dma_unmap_single(&efx->pci_dev->dev, state.header_dma_addr,
1338 state.header_unmap_len, DMA_TO_DEVICE);
1340 efx_enqueue_unwind(tx_queue);
1341 return NETDEV_TX_OK;