1 /*******************************************************************************
2 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
3 ST Ethernet IPs are built around a Synopsys IP Core.
5 Copyright(C) 2007-2011 STMicroelectronics Ltd
7 This program is free software; you can redistribute it and/or modify it
8 under the terms and conditions of the GNU General Public License,
9 version 2, as published by the Free Software Foundation.
11 This program is distributed in the hope it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc.,
18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
20 The full GNU General Public License is included in this distribution in
21 the file called "COPYING".
23 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
25 Documentation available at:
26 http://www.stlinux.com
28 https://bugzilla.stlinux.com/
29 *******************************************************************************/
31 #include <linux/clk.h>
32 #include <linux/kernel.h>
33 #include <linux/interrupt.h>
35 #include <linux/tcp.h>
36 #include <linux/skbuff.h>
37 #include <linux/ethtool.h>
38 #include <linux/if_ether.h>
39 #include <linux/crc32.h>
40 #include <linux/mii.h>
42 #include <linux/if_vlan.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/slab.h>
45 #include <linux/prefetch.h>
46 #ifdef CONFIG_GMAC_DEBUG_FS
47 #include <linux/debugfs.h>
48 #include <linux/seq_file.h>
49 #endif /* CONFIG_GMAC_DEBUG_FS */
50 #include <linux/net_tstamp.h>
51 #include "stmmac_ptp.h"
55 /*#define STMMAC_DEBUG*/
57 #define DBG(nlevel, klevel, fmt, args...) \
58 ((void)(netif_msg_##nlevel(priv) && \
59 printk(KERN_##klevel fmt, ## args)))
61 #define DBG(nlevel, klevel, fmt, args...) do { } while (0)
64 #undef STMMAC_RX_DEBUG
65 /*#define STMMAC_RX_DEBUG*/
66 #ifdef STMMAC_RX_DEBUG
67 #define RX_DBG(fmt, args...) printk(fmt, ## args)
69 #define RX_DBG(fmt, args...) do { } while (0)
72 #undef STMMAC_XMIT_DEBUG
73 /*#define STMMAC_XMIT_DEBUG*/
74 #ifdef STMMAC_XMIT_DEBUG
75 #define TX_DBG(fmt, args...) printk(fmt, ## args)
77 #define TX_DBG(fmt, args...) do { } while (0)
80 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
81 #define JUMBO_LEN 9000
83 /* Module parameters */
85 static int watchdog = TX_TIMEO;
86 module_param(watchdog, int, S_IRUGO | S_IWUSR);
87 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");
89 static int debug = -1;
90 module_param(debug, int, S_IRUGO | S_IWUSR);
91 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
94 module_param(phyaddr, int, S_IRUGO);
95 MODULE_PARM_DESC(phyaddr, "Physical device address");
97 #define DMA_TX_SIZE 256
98 static int dma_txsize = DMA_TX_SIZE;
99 module_param(dma_txsize, int, S_IRUGO | S_IWUSR);
100 MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list");
102 #define DMA_RX_SIZE 256
103 static int dma_rxsize = DMA_RX_SIZE;
104 module_param(dma_rxsize, int, S_IRUGO | S_IWUSR);
105 MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list");
107 static int flow_ctrl = FLOW_OFF;
108 module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
109 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
111 static int pause = PAUSE_TIME;
112 module_param(pause, int, S_IRUGO | S_IWUSR);
113 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
115 #define TC_DEFAULT 64
116 static int tc = TC_DEFAULT;
117 module_param(tc, int, S_IRUGO | S_IWUSR);
118 MODULE_PARM_DESC(tc, "DMA threshold control value");
120 #define DMA_BUFFER_SIZE BUF_SIZE_2KiB
121 static int buf_sz = DMA_BUFFER_SIZE;
122 module_param(buf_sz, int, S_IRUGO | S_IWUSR);
123 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
125 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
126 NETIF_MSG_LINK | NETIF_MSG_IFUP |
127 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
129 #define STMMAC_DEFAULT_LPI_TIMER 1000
130 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
131 module_param(eee_timer, int, S_IRUGO | S_IWUSR);
132 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
133 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x))
135 /* By default the driver will use the ring mode to manage tx and rx descriptors
136 * but passing this value so user can force to use the chain instead of the ring
138 static unsigned int chain_mode;
139 module_param(chain_mode, int, S_IRUGO);
140 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
142 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
144 #ifdef CONFIG_GMAC_DEBUG_FS
145 static int stmmac_init_fs(struct net_device *dev);
146 static void stmmac_exit_fs(void);
149 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
152 * stmmac_verify_args - verify the driver parameters.
153 * Description: it verifies if some wrong parameter is passed to the driver.
154 * Note that wrong parameters are replaced with the default values.
156 static void stmmac_verify_args(void)
158 if (unlikely(watchdog < 0))
160 if (unlikely(dma_rxsize < 0))
161 dma_rxsize = DMA_RX_SIZE;
162 if (unlikely(dma_txsize < 0))
163 dma_txsize = DMA_TX_SIZE;
164 if (unlikely((buf_sz < DMA_BUFFER_SIZE) || (buf_sz > BUF_SIZE_16KiB)))
165 buf_sz = DMA_BUFFER_SIZE;
166 if (unlikely(flow_ctrl > 1))
167 flow_ctrl = FLOW_AUTO;
168 else if (likely(flow_ctrl < 0))
169 flow_ctrl = FLOW_OFF;
170 if (unlikely((pause < 0) || (pause > 0xffff)))
173 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
177 * stmmac_clk_csr_set - dynamically set the MDC clock
178 * @priv: driver private structure
179 * Description: this is to dynamically set the MDC clock according to the csr
182 * If a specific clk_csr value is passed from the platform
183 * this means that the CSR Clock Range selection cannot be
184 * changed at run-time and it is fixed (as reported in the driver
185 * documentation). Viceversa the driver will try to set the MDC
186 * clock dynamically according to the actual clock input.
188 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
192 clk_rate = clk_get_rate(priv->stmmac_clk);
194 /* Platform provided default clk_csr would be assumed valid
195 * for all other cases except for the below mentioned ones.
196 * For values higher than the IEEE 802.3 specified frequency
197 * we can not estimate the proper divider as it is not known
198 * the frequency of clk_csr_i. So we do not change the default
201 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
202 if (clk_rate < CSR_F_35M)
203 priv->clk_csr = STMMAC_CSR_20_35M;
204 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
205 priv->clk_csr = STMMAC_CSR_35_60M;
206 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
207 priv->clk_csr = STMMAC_CSR_60_100M;
208 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
209 priv->clk_csr = STMMAC_CSR_100_150M;
210 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
211 priv->clk_csr = STMMAC_CSR_150_250M;
212 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
213 priv->clk_csr = STMMAC_CSR_250_300M;
217 #if defined(STMMAC_XMIT_DEBUG) || defined(STMMAC_RX_DEBUG)
218 static void print_pkt(unsigned char *buf, int len)
221 pr_info("len = %d byte, buf addr: 0x%p", len, buf);
222 for (j = 0; j < len; j++) {
224 pr_info("\n %03x:", j);
225 pr_info(" %02x", buf[j]);
231 /* minimum number of free TX descriptors required to wake up TX process */
232 #define STMMAC_TX_THRESH(x) (x->dma_tx_size/4)
234 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
236 return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1;
240 * stmmac_hw_fix_mac_speed: callback for speed selection
241 * @priv: driver private structure
242 * Description: on some platforms (e.g. ST), some HW system configuraton
243 * registers have to be set according to the link speed negotiated.
245 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
247 struct phy_device *phydev = priv->phydev;
249 if (likely(priv->plat->fix_mac_speed))
250 priv->plat->fix_mac_speed(priv->plat->bsp_priv, phydev->speed);
252 if (priv->rk_pdata->gmac_speed_switch) {
253 priv->rk_pdata->gmac_speed_switch(phydev->speed);
258 * stmmac_enable_eee_mode: Check and enter in LPI mode
259 * @priv: driver private structure
260 * Description: this function is to verify and enter in LPI mode for EEE.
262 static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
264 /* Check and enter in LPI mode */
265 if ((priv->dirty_tx == priv->cur_tx) &&
266 (priv->tx_path_in_lpi_mode == false))
267 priv->hw->mac->set_eee_mode(priv->ioaddr);
271 * stmmac_disable_eee_mode: disable/exit from EEE
272 * @priv: driver private structure
273 * Description: this function is to exit and disable EEE in case of
274 * LPI state is true. This is called by the xmit.
276 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
278 priv->hw->mac->reset_eee_mode(priv->ioaddr);
279 del_timer_sync(&priv->eee_ctrl_timer);
280 priv->tx_path_in_lpi_mode = false;
284 * stmmac_eee_ctrl_timer: EEE TX SW timer.
287 * if there is no data transfer and if we are not in LPI state,
288 * then MAC Transmitter can be moved to LPI state.
290 static void stmmac_eee_ctrl_timer(unsigned long arg)
292 struct stmmac_priv *priv = (struct stmmac_priv *)arg;
294 stmmac_enable_eee_mode(priv);
295 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
299 * stmmac_eee_init: init EEE
300 * @priv: driver private structure
302 * If the EEE support has been enabled while configuring the driver,
303 * if the GMAC actually supports the EEE (from the HW cap reg) and the
304 * phy can also manage EEE, so enable the LPI state and start the timer
305 * to verify if the tx path can enter in LPI state.
307 bool stmmac_eee_init(struct stmmac_priv *priv)
311 /* Using PCS we cannot dial with the phy registers at this stage
312 * so we do not support extra feature like EEE.
314 if ((priv->pcs == STMMAC_PCS_RGMII) || (priv->pcs == STMMAC_PCS_TBI) ||
315 (priv->pcs == STMMAC_PCS_RTBI))
318 /* MAC core supports the EEE feature. */
319 if (priv->dma_cap.eee) {
320 /* Check if the PHY supports EEE */
321 if (phy_init_eee(priv->phydev, 1))
324 if (!priv->eee_active) {
325 priv->eee_active = 1;
326 init_timer(&priv->eee_ctrl_timer);
327 priv->eee_ctrl_timer.function = stmmac_eee_ctrl_timer;
328 priv->eee_ctrl_timer.data = (unsigned long)priv;
329 priv->eee_ctrl_timer.expires = STMMAC_LPI_T(eee_timer);
330 add_timer(&priv->eee_ctrl_timer);
332 priv->hw->mac->set_eee_timer(priv->ioaddr,
333 STMMAC_DEFAULT_LIT_LS,
336 /* Set HW EEE according to the speed */
337 priv->hw->mac->set_eee_pls(priv->ioaddr,
340 pr_info("stmmac: Energy-Efficient Ethernet initialized\n");
348 /* stmmac_get_tx_hwtstamp: get HW TX timestamps
349 * @priv: driver private structure
350 * @entry : descriptor index to be used.
351 * @skb : the socket buffer
353 * This function will read timestamp from the descriptor & pass it to stack.
354 * and also perform some sanity checks.
356 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
357 unsigned int entry, struct sk_buff *skb)
359 struct skb_shared_hwtstamps shhwtstamp;
363 if (!priv->hwts_tx_en)
366 /* exit if skb doesn't support hw tstamp */
367 if (likely(!(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
371 desc = (priv->dma_etx + entry);
373 desc = (priv->dma_tx + entry);
375 /* check tx tstamp status */
376 if (!priv->hw->desc->get_tx_timestamp_status((struct dma_desc *)desc))
379 /* get the valid tstamp */
380 ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);
382 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
383 shhwtstamp.hwtstamp = ns_to_ktime(ns);
384 /* pass tstamp to stack */
385 skb_tstamp_tx(skb, &shhwtstamp);
390 /* stmmac_get_rx_hwtstamp: get HW RX timestamps
391 * @priv: driver private structure
392 * @entry : descriptor index to be used.
393 * @skb : the socket buffer
395 * This function will read received packet's timestamp from the descriptor
396 * and pass it to stack. It also perform some sanity checks.
398 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv,
399 unsigned int entry, struct sk_buff *skb)
401 struct skb_shared_hwtstamps *shhwtstamp = NULL;
405 if (!priv->hwts_rx_en)
409 desc = (priv->dma_erx + entry);
411 desc = (priv->dma_rx + entry);
413 /* exit if rx tstamp is not valid */
414 if (!priv->hw->desc->get_rx_timestamp_status(desc, priv->adv_ts))
417 /* get valid tstamp */
418 ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);
419 shhwtstamp = skb_hwtstamps(skb);
420 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
421 shhwtstamp->hwtstamp = ns_to_ktime(ns);
425 * stmmac_hwtstamp_ioctl - control hardware timestamping.
426 * @dev: device pointer.
427 * @ifr: An IOCTL specefic structure, that can contain a pointer to
428 * a proprietary structure used to pass information to the driver.
430 * This function configures the MAC to enable/disable both outgoing(TX)
431 * and incoming(RX) packets time stamping based on user input.
433 * 0 on success and an appropriate -ve integer on failure.
435 static int stmmac_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr)
437 struct stmmac_priv *priv = netdev_priv(dev);
438 struct hwtstamp_config config;
443 u32 ptp_over_ipv4_udp = 0;
444 u32 ptp_over_ipv6_udp = 0;
445 u32 ptp_over_ethernet = 0;
446 u32 snap_type_sel = 0;
447 u32 ts_master_en = 0;
451 if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
452 netdev_alert(priv->dev, "No support for HW time stamping\n");
453 priv->hwts_tx_en = 0;
454 priv->hwts_rx_en = 0;
459 if (copy_from_user(&config, ifr->ifr_data,
460 sizeof(struct hwtstamp_config)))
463 pr_debug("%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
464 __func__, config.flags, config.tx_type, config.rx_filter);
466 /* reserved for future extensions */
470 switch (config.tx_type) {
471 case HWTSTAMP_TX_OFF:
472 priv->hwts_tx_en = 0;
475 priv->hwts_tx_en = 1;
482 switch (config.rx_filter) {
483 case HWTSTAMP_FILTER_NONE:
484 /* time stamp no incoming packet at all */
485 config.rx_filter = HWTSTAMP_FILTER_NONE;
488 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
489 /* PTP v1, UDP, any kind of event packet */
490 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
491 /* take time stamp for all event messages */
492 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
494 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
495 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
498 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
499 /* PTP v1, UDP, Sync packet */
500 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
501 /* take time stamp for SYNC messages only */
502 ts_event_en = PTP_TCR_TSEVNTENA;
504 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
505 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
508 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
509 /* PTP v1, UDP, Delay_req packet */
510 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
511 /* take time stamp for Delay_Req messages only */
512 ts_master_en = PTP_TCR_TSMSTRENA;
513 ts_event_en = PTP_TCR_TSEVNTENA;
515 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
516 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
519 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
520 /* PTP v2, UDP, any kind of event packet */
521 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
522 ptp_v2 = PTP_TCR_TSVER2ENA;
523 /* take time stamp for all event messages */
524 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
526 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
527 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
530 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
531 /* PTP v2, UDP, Sync packet */
532 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
533 ptp_v2 = PTP_TCR_TSVER2ENA;
534 /* take time stamp for SYNC messages only */
535 ts_event_en = PTP_TCR_TSEVNTENA;
537 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
538 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
541 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
542 /* PTP v2, UDP, Delay_req packet */
543 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
544 ptp_v2 = PTP_TCR_TSVER2ENA;
545 /* take time stamp for Delay_Req messages only */
546 ts_master_en = PTP_TCR_TSMSTRENA;
547 ts_event_en = PTP_TCR_TSEVNTENA;
549 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
550 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
553 case HWTSTAMP_FILTER_PTP_V2_EVENT:
554 /* PTP v2/802.AS1 any layer, any kind of event packet */
555 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
556 ptp_v2 = PTP_TCR_TSVER2ENA;
557 /* take time stamp for all event messages */
558 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
560 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
561 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
562 ptp_over_ethernet = PTP_TCR_TSIPENA;
565 case HWTSTAMP_FILTER_PTP_V2_SYNC:
566 /* PTP v2/802.AS1, any layer, Sync packet */
567 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
568 ptp_v2 = PTP_TCR_TSVER2ENA;
569 /* take time stamp for SYNC messages only */
570 ts_event_en = PTP_TCR_TSEVNTENA;
572 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
573 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
574 ptp_over_ethernet = PTP_TCR_TSIPENA;
577 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
578 /* PTP v2/802.AS1, any layer, Delay_req packet */
579 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
580 ptp_v2 = PTP_TCR_TSVER2ENA;
581 /* take time stamp for Delay_Req messages only */
582 ts_master_en = PTP_TCR_TSMSTRENA;
583 ts_event_en = PTP_TCR_TSEVNTENA;
585 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
586 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
587 ptp_over_ethernet = PTP_TCR_TSIPENA;
590 case HWTSTAMP_FILTER_ALL:
591 /* time stamp any incoming packet */
592 config.rx_filter = HWTSTAMP_FILTER_ALL;
593 tstamp_all = PTP_TCR_TSENALL;
600 switch (config.rx_filter) {
601 case HWTSTAMP_FILTER_NONE:
602 config.rx_filter = HWTSTAMP_FILTER_NONE;
605 /* PTP v1, UDP, any kind of event packet */
606 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
610 priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
612 if (!priv->hwts_tx_en && !priv->hwts_rx_en)
613 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, 0);
615 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR |
616 tstamp_all | ptp_v2 | ptp_over_ethernet |
617 ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en |
618 ts_master_en | snap_type_sel);
620 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, value);
622 /* program Sub Second Increment reg */
623 priv->hw->ptp->config_sub_second_increment(priv->ioaddr);
625 /* calculate default added value:
627 * addend = (2^32)/freq_div_ratio;
628 * where, freq_div_ratio = STMMAC_SYSCLOCK/50MHz
629 * hence, addend = ((2^32) * 50MHz)/STMMAC_SYSCLOCK;
630 * NOTE: STMMAC_SYSCLOCK should be >= 50MHz to
631 * achive 20ns accuracy.
633 * 2^x * y == (y << x), hence
634 * 2^32 * 50000000 ==> (50000000 << 32)
636 temp = (u64) (50000000ULL << 32);
637 priv->default_addend = div_u64(temp, STMMAC_SYSCLOCK);
638 priv->hw->ptp->config_addend(priv->ioaddr,
639 priv->default_addend);
641 /* initialize system time */
642 getnstimeofday(&now);
643 priv->hw->ptp->init_systime(priv->ioaddr, now.tv_sec,
647 return copy_to_user(ifr->ifr_data, &config,
648 sizeof(struct hwtstamp_config)) ? -EFAULT : 0;
652 * stmmac_init_ptp: init PTP
653 * @priv: driver private structure
654 * Description: this is to verify if the HW supports the PTPv1 or v2.
655 * This is done by looking at the HW cap. register.
656 * Also it registers the ptp driver.
658 static int stmmac_init_ptp(struct stmmac_priv *priv)
660 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
663 if (netif_msg_hw(priv)) {
664 if (priv->dma_cap.time_stamp) {
665 pr_debug("IEEE 1588-2002 Time Stamp supported\n");
668 if (priv->dma_cap.atime_stamp && priv->extend_desc) {
670 ("IEEE 1588-2008 Advanced Time Stamp supported\n");
675 priv->hw->ptp = &stmmac_ptp;
676 priv->hwts_tx_en = 0;
677 priv->hwts_rx_en = 0;
679 return stmmac_ptp_register(priv);
682 static void stmmac_release_ptp(struct stmmac_priv *priv)
684 stmmac_ptp_unregister(priv);
689 * @dev: net device structure
690 * Description: it adjusts the link parameters.
692 static void stmmac_adjust_link(struct net_device *dev)
694 struct stmmac_priv *priv = netdev_priv(dev);
695 struct phy_device *phydev = priv->phydev;
698 unsigned int fc = priv->flow_ctrl, pause_time = priv->pause;
703 DBG(probe, DEBUG, "stmmac_adjust_link: called. address %d link %d\n",
704 phydev->addr, phydev->link);
706 spin_lock_irqsave(&priv->lock, flags);
709 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
711 /* Now we make sure that we can be in full duplex mode.
712 * If not, we operate in half-duplex mode. */
713 if (phydev->duplex != priv->oldduplex) {
715 if (!(phydev->duplex))
716 ctrl &= ~priv->hw->link.duplex;
718 ctrl |= priv->hw->link.duplex;
719 priv->oldduplex = phydev->duplex;
721 /* Flow Control operation */
723 priv->hw->mac->flow_ctrl(priv->ioaddr, phydev->duplex,
726 if (phydev->speed != priv->speed) {
728 switch (phydev->speed) {
730 if (likely(priv->plat->has_gmac))
731 ctrl &= ~priv->hw->link.port;
732 stmmac_hw_fix_mac_speed(priv);
736 if (priv->plat->has_gmac) {
737 ctrl |= priv->hw->link.port;
738 if (phydev->speed == SPEED_100) {
739 ctrl |= priv->hw->link.speed;
741 ctrl &= ~(priv->hw->link.speed);
744 ctrl &= ~priv->hw->link.port;
746 stmmac_hw_fix_mac_speed(priv);
749 if (netif_msg_link(priv))
750 pr_warn("%s: Speed (%d) not 10/100\n",
751 dev->name, phydev->speed);
755 priv->speed = phydev->speed;
758 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
760 if (!priv->oldlink) {
764 } else if (priv->oldlink) {
768 priv->oldduplex = -1;
771 if (new_state && netif_msg_link(priv))
772 phy_print_status(phydev);
774 /* At this stage, it could be needed to setup the EEE or adjust some
775 * MAC related HW registers.
777 priv->eee_enabled = stmmac_eee_init(priv);
779 spin_unlock_irqrestore(&priv->lock, flags);
781 DBG(probe, DEBUG, "stmmac_adjust_link: exiting\n");
785 * stmmac_check_pcs_mode: verify if RGMII/SGMII is supported
786 * @priv: driver private structure
787 * Description: this is to verify if the HW supports the PCS.
788 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
789 * configured for the TBI, RTBI, or SGMII PHY interface.
791 static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
793 int interface = priv->plat->interface;
795 if (priv->dma_cap.pcs) {
796 if ((interface & PHY_INTERFACE_MODE_RGMII) ||
797 (interface & PHY_INTERFACE_MODE_RGMII_ID) ||
798 (interface & PHY_INTERFACE_MODE_RGMII_RXID) ||
799 (interface & PHY_INTERFACE_MODE_RGMII_TXID)) {
800 pr_debug("STMMAC: PCS RGMII support enable\n");
801 priv->pcs = STMMAC_PCS_RGMII;
802 } else if (interface & PHY_INTERFACE_MODE_SGMII) {
803 pr_debug("STMMAC: PCS SGMII support enable\n");
804 priv->pcs = STMMAC_PCS_SGMII;
810 * stmmac_init_phy - PHY initialization
811 * @dev: net device structure
812 * Description: it initializes the driver's PHY state, and attaches the PHY
817 static int stmmac_init_phy(struct net_device *dev)
819 struct stmmac_priv *priv = netdev_priv(dev);
820 struct phy_device *phydev;
821 char phy_id_fmt[MII_BUS_ID_SIZE + 3];
822 char bus_id[MII_BUS_ID_SIZE];
823 int interface = priv->plat->interface;
826 priv->oldduplex = -1;
828 if (priv->plat->phy_bus_name)
829 snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x",
830 priv->plat->phy_bus_name, priv->plat->bus_id);
832 snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x",
835 snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
836 priv->plat->phy_addr);
837 pr_debug("stmmac_init_phy: trying to attach to %s\n", phy_id_fmt);
839 phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link, interface);
841 if (IS_ERR(phydev)) {
842 pr_err("%s: Could not attach to PHY\n", dev->name);
843 return PTR_ERR(phydev);
846 /* Stop Advertising 1000BASE Capability if interface is not GMII */
847 if ((interface == PHY_INTERFACE_MODE_MII) ||
848 (interface == PHY_INTERFACE_MODE_RMII))
849 phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
850 SUPPORTED_1000baseT_Full);
853 * Broken HW is sometimes missing the pull-up resistor on the
854 * MDIO line, which results in reads to non-existent devices returning
855 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
857 * Note: phydev->phy_id is the result of reading the UID PHY registers.
859 if (phydev->phy_id == 0) {
860 phy_disconnect(phydev);
863 pr_debug("stmmac_init_phy: %s: attached to PHY (UID 0x%x)"
864 " Link = %d\n", dev->name, phydev->phy_id, phydev->link);
866 priv->phydev = phydev;
872 * stmmac_display_ring: display ring
873 * @head: pointer to the head of the ring passed.
874 * @size: size of the ring.
875 * @extend_desc: to verify if extended descriptors are used.
876 * Description: display the control/status and buffer descriptors.
878 static void stmmac_display_ring(void *head, int size, int extend_desc)
881 struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
882 struct dma_desc *p = (struct dma_desc *)head;
884 for (i = 0; i < size; i++) {
888 pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
889 i, (unsigned int)virt_to_phys(ep),
890 (unsigned int)x, (unsigned int)(x >> 32),
891 ep->basic.des2, ep->basic.des3);
895 pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x",
896 i, (unsigned int)virt_to_phys(p),
897 (unsigned int)x, (unsigned int)(x >> 32),
905 static void stmmac_display_rings(struct stmmac_priv *priv)
907 unsigned int txsize = priv->dma_tx_size;
908 unsigned int rxsize = priv->dma_rx_size;
910 if (priv->extend_desc) {
911 pr_info("Extended RX descriptor ring:\n");
912 stmmac_display_ring((void *)priv->dma_erx, rxsize, 1);
913 pr_info("Extended TX descriptor ring:\n");
914 stmmac_display_ring((void *)priv->dma_etx, txsize, 1);
916 pr_info("RX descriptor ring:\n");
917 stmmac_display_ring((void *)priv->dma_rx, rxsize, 0);
918 pr_info("TX descriptor ring:\n");
919 stmmac_display_ring((void *)priv->dma_tx, txsize, 0);
923 static int stmmac_set_bfsize(int mtu, int bufsize)
927 if (mtu >= BUF_SIZE_4KiB)
929 else if (mtu >= BUF_SIZE_2KiB)
931 else if (mtu >= DMA_BUFFER_SIZE)
934 ret = DMA_BUFFER_SIZE;
940 * stmmac_clear_descriptors: clear descriptors
941 * @priv: driver private structure
942 * Description: this function is called to clear the tx and rx descriptors
943 * in case of both basic and extended descriptors are used.
945 static void stmmac_clear_descriptors(struct stmmac_priv *priv)
948 unsigned int txsize = priv->dma_tx_size;
949 unsigned int rxsize = priv->dma_rx_size;
951 /* Clear the Rx/Tx descriptors */
952 for (i = 0; i < rxsize; i++)
953 if (priv->extend_desc)
954 priv->hw->desc->init_rx_desc(&priv->dma_erx[i].basic,
955 priv->use_riwt, priv->mode,
958 priv->hw->desc->init_rx_desc(&priv->dma_rx[i],
959 priv->use_riwt, priv->mode,
961 for (i = 0; i < txsize; i++)
962 if (priv->extend_desc)
963 priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
967 priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
972 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
977 skb = __netdev_alloc_skb(priv->dev, priv->dma_buf_sz + NET_IP_ALIGN,
979 if (unlikely(skb == NULL)) {
980 pr_err("%s: Rx init fails; skb is NULL\n", __func__);
983 skb_reserve(skb, NET_IP_ALIGN);
984 priv->rx_skbuff[i] = skb;
985 priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
989 p->des2 = priv->rx_skbuff_dma[i];
991 if ((priv->mode == STMMAC_RING_MODE) &&
992 (priv->dma_buf_sz == BUF_SIZE_16KiB))
993 priv->hw->ring->init_desc3(p);
999 * init_dma_desc_rings - init the RX/TX descriptor rings
1000 * @dev: net device structure
1001 * Description: this function initializes the DMA RX/TX descriptors
1002 * and allocates the socket buffers. It suppors the chained and ring
1005 static void init_dma_desc_rings(struct net_device *dev)
1008 struct stmmac_priv *priv = netdev_priv(dev);
1009 unsigned int txsize = priv->dma_tx_size;
1010 unsigned int rxsize = priv->dma_rx_size;
1011 unsigned int bfsize = 0;
1013 /* Set the max buffer size according to the DESC mode
1014 * and the MTU. Note that RING mode allows 16KiB bsize.
1016 if (priv->mode == STMMAC_RING_MODE)
1017 bfsize = priv->hw->ring->set_16kib_bfsize(dev->mtu);
1019 if (bfsize < BUF_SIZE_16KiB)
1020 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
1022 DBG(probe, INFO, "stmmac: txsize %d, rxsize %d, bfsize %d\n",
1023 txsize, rxsize, bfsize);
1025 if (priv->extend_desc) {
1026 priv->dma_erx = dma_alloc_coherent(priv->device, rxsize *
1031 priv->dma_etx = dma_alloc_coherent(priv->device, txsize *
1036 if ((!priv->dma_erx) || (!priv->dma_etx))
1039 priv->dma_rx = dma_alloc_coherent(priv->device, rxsize *
1040 sizeof(struct dma_desc),
1043 priv->dma_tx = dma_alloc_coherent(priv->device, txsize *
1044 sizeof(struct dma_desc),
1047 if ((!priv->dma_rx) || (!priv->dma_tx))
1051 priv->rx_skbuff_dma = kmalloc_array(rxsize, sizeof(dma_addr_t),
1053 priv->rx_skbuff = kmalloc_array(rxsize, sizeof(struct sk_buff *),
1055 priv->tx_skbuff_dma = kmalloc_array(txsize, sizeof(dma_addr_t),
1057 priv->tx_skbuff = kmalloc_array(txsize, sizeof(struct sk_buff *),
1059 if (netif_msg_drv(priv))
1060 pr_debug("(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n", __func__,
1061 (u32) priv->dma_rx_phy, (u32) priv->dma_tx_phy);
1063 /* RX INITIALIZATION */
1064 DBG(probe, INFO, "stmmac: SKB addresses:\nskb\t\tskb data\tdma data\n");
1065 for (i = 0; i < rxsize; i++) {
1067 if (priv->extend_desc)
1068 p = &((priv->dma_erx + i)->basic);
1070 p = priv->dma_rx + i;
1072 if (stmmac_init_rx_buffers(priv, p, i))
1075 DBG(probe, INFO, "[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i],
1076 priv->rx_skbuff[i]->data, priv->rx_skbuff_dma[i]);
1079 priv->dirty_rx = (unsigned int)(i - rxsize);
1080 priv->dma_buf_sz = bfsize;
1083 /* Setup the chained descriptor addresses */
1084 if (priv->mode == STMMAC_CHAIN_MODE) {
1085 if (priv->extend_desc) {
1086 priv->hw->chain->init(priv->dma_erx, priv->dma_rx_phy,
1088 priv->hw->chain->init(priv->dma_etx, priv->dma_tx_phy,
1091 priv->hw->chain->init(priv->dma_rx, priv->dma_rx_phy,
1093 priv->hw->chain->init(priv->dma_tx, priv->dma_tx_phy,
1098 /* TX INITIALIZATION */
1099 for (i = 0; i < txsize; i++) {
1101 if (priv->extend_desc)
1102 p = &((priv->dma_etx + i)->basic);
1104 p = priv->dma_tx + i;
1106 priv->tx_skbuff_dma[i] = 0;
1107 priv->tx_skbuff[i] = NULL;
1113 stmmac_clear_descriptors(priv);
1115 if (netif_msg_hw(priv))
1116 stmmac_display_rings(priv);
1119 static void dma_free_rx_skbufs(struct stmmac_priv *priv)
1123 for (i = 0; i < priv->dma_rx_size; i++) {
1124 if (priv->rx_skbuff[i]) {
1125 dma_unmap_single(priv->device, priv->rx_skbuff_dma[i],
1126 priv->dma_buf_sz, DMA_FROM_DEVICE);
1127 dev_kfree_skb_any(priv->rx_skbuff[i]);
1129 priv->rx_skbuff[i] = NULL;
1133 static void dma_free_tx_skbufs(struct stmmac_priv *priv)
1137 for (i = 0; i < priv->dma_tx_size; i++) {
1138 if (priv->tx_skbuff[i] != NULL) {
1140 if (priv->extend_desc)
1141 p = &((priv->dma_etx + i)->basic);
1143 p = priv->dma_tx + i;
1145 if (priv->tx_skbuff_dma[i])
1146 dma_unmap_single(priv->device,
1147 priv->tx_skbuff_dma[i],
1148 priv->hw->desc->get_tx_len(p),
1150 dev_kfree_skb_any(priv->tx_skbuff[i]);
1151 priv->tx_skbuff[i] = NULL;
1152 priv->tx_skbuff_dma[i] = 0;
1157 static void free_dma_desc_resources(struct stmmac_priv *priv)
1159 /* Release the DMA TX/RX socket buffers */
1160 dma_free_rx_skbufs(priv);
1161 dma_free_tx_skbufs(priv);
1163 /* Free DMA regions of consistent memory previously allocated */
1164 if (!priv->extend_desc) {
1165 dma_free_coherent(priv->device,
1166 priv->dma_tx_size * sizeof(struct dma_desc),
1167 priv->dma_tx, priv->dma_tx_phy);
1168 dma_free_coherent(priv->device,
1169 priv->dma_rx_size * sizeof(struct dma_desc),
1170 priv->dma_rx, priv->dma_rx_phy);
1172 dma_free_coherent(priv->device, priv->dma_tx_size *
1173 sizeof(struct dma_extended_desc),
1174 priv->dma_etx, priv->dma_tx_phy);
1175 dma_free_coherent(priv->device, priv->dma_rx_size *
1176 sizeof(struct dma_extended_desc),
1177 priv->dma_erx, priv->dma_rx_phy);
1179 kfree(priv->rx_skbuff_dma);
1180 kfree(priv->rx_skbuff);
1181 kfree(priv->tx_skbuff_dma);
1182 kfree(priv->tx_skbuff);
1186 * stmmac_dma_operation_mode - HW DMA operation mode
1187 * @priv: driver private structure
1188 * Description: it sets the DMA operation mode: tx/rx DMA thresholds
1189 * or Store-And-Forward capability.
1191 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
1193 if (likely(priv->plat->force_sf_dma_mode ||
1194 ((priv->plat->tx_coe) && (!priv->no_csum_insertion)))) {
1196 * In case of GMAC, SF mode can be enabled
1197 * to perform the TX COE in HW. This depends on:
1198 * 1) TX COE if actually supported
1199 * 2) There is no bugged Jumbo frame support
1200 * that needs to not insert csum in the TDES.
1202 priv->hw->dma->dma_mode(priv->ioaddr, SF_DMA_MODE, SF_DMA_MODE);
1205 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
1210 * @priv: driver private structure
1211 * Description: it reclaims resources after transmission completes.
1213 static void stmmac_tx_clean(struct stmmac_priv *priv)
1215 unsigned int txsize = priv->dma_tx_size;
1217 spin_lock(&priv->tx_lock);
1219 priv->xstats.tx_clean++;
1221 while (priv->dirty_tx != priv->cur_tx) {
1223 unsigned int entry = priv->dirty_tx % txsize;
1224 struct sk_buff *skb = priv->tx_skbuff[entry];
1227 if (priv->extend_desc)
1228 p = (struct dma_desc *)(priv->dma_etx + entry);
1230 p = priv->dma_tx + entry;
1232 /* Check if the descriptor is owned by the DMA. */
1233 if (priv->hw->desc->get_tx_owner(p))
1236 /* Verify tx error by looking at the last segment. */
1237 last = priv->hw->desc->get_tx_ls(p);
1240 priv->hw->desc->tx_status(&priv->dev->stats,
1243 if (likely(tx_error == 0)) {
1244 priv->dev->stats.tx_packets++;
1245 priv->xstats.tx_pkt_n++;
1247 priv->dev->stats.tx_errors++;
1249 stmmac_get_tx_hwtstamp(priv, entry, skb);
1251 TX_DBG("%s: curr %d, dirty %d\n", __func__,
1252 priv->cur_tx, priv->dirty_tx);
1254 if (likely(priv->tx_skbuff_dma[entry])) {
1255 dma_unmap_single(priv->device,
1256 priv->tx_skbuff_dma[entry],
1257 priv->hw->desc->get_tx_len(p),
1259 priv->tx_skbuff_dma[entry] = 0;
1261 priv->hw->ring->clean_desc3(priv, p);
1263 if (likely(skb != NULL)) {
1265 priv->tx_skbuff[entry] = NULL;
1268 priv->hw->desc->release_tx_desc(p, priv->mode);
1272 if (unlikely(netif_queue_stopped(priv->dev) &&
1273 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) {
1274 netif_tx_lock(priv->dev);
1275 if (netif_queue_stopped(priv->dev) &&
1276 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) {
1277 TX_DBG("%s: restart transmit\n", __func__);
1278 netif_wake_queue(priv->dev);
1280 netif_tx_unlock(priv->dev);
1283 if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
1284 stmmac_enable_eee_mode(priv);
1285 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
1287 spin_unlock(&priv->tx_lock);
1290 static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv)
1292 priv->hw->dma->enable_dma_irq(priv->ioaddr);
1295 static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv)
1297 priv->hw->dma->disable_dma_irq(priv->ioaddr);
1301 * stmmac_tx_err: irq tx error mng function
1302 * @priv: driver private structure
1303 * Description: it cleans the descriptors and restarts the transmission
1304 * in case of errors.
1306 static void stmmac_tx_err(struct stmmac_priv *priv)
1309 int txsize = priv->dma_tx_size;
1310 netif_stop_queue(priv->dev);
1312 priv->hw->dma->stop_tx(priv->ioaddr);
1313 dma_free_tx_skbufs(priv);
1314 for (i = 0; i < txsize; i++)
1315 if (priv->extend_desc)
1316 priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
1320 priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
1325 priv->hw->dma->start_tx(priv->ioaddr);
1327 priv->dev->stats.tx_errors++;
1328 netif_wake_queue(priv->dev);
1332 * stmmac_dma_interrupt: DMA ISR
1333 * @priv: driver private structure
1334 * Description: this is the DMA ISR. It is called by the main ISR.
1335 * It calls the dwmac dma routine to understand which type of interrupt
1336 * happened. In case of there is a Normal interrupt and either TX or RX
1337 * interrupt happened so the NAPI is scheduled.
1339 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
1343 status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats);
1344 if (likely((status & handle_rx)) || (status & handle_tx)) {
1345 if (likely(napi_schedule_prep(&priv->napi))) {
1346 stmmac_disable_dma_irq(priv);
1347 __napi_schedule(&priv->napi);
1350 if (unlikely(status & tx_hard_error_bump_tc)) {
1351 /* Try to bump up the dma threshold on this failure */
1352 if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) {
1354 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
1355 priv->xstats.threshold = tc;
1357 } else if (unlikely(status == tx_hard_error))
1358 stmmac_tx_err(priv);
1362 * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
1363 * @priv: driver private structure
1364 * Description: this masks the MMC irq, in fact, the counters are managed in SW.
1366 static void stmmac_mmc_setup(struct stmmac_priv *priv)
1368 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
1369 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
1371 dwmac_mmc_intr_all_mask(priv->ioaddr);
1373 if (priv->dma_cap.rmon) {
1374 dwmac_mmc_ctrl(priv->ioaddr, mode);
1375 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
1377 pr_info(" No MAC Management Counters available\n");
1380 static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv)
1382 u32 hwid = priv->hw->synopsys_uid;
1384 /* Check Synopsys Id (not available on old chips) */
1386 u32 uid = ((hwid & 0x0000ff00) >> 8);
1387 u32 synid = (hwid & 0x000000ff);
1389 pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n",
1398 * stmmac_selec_desc_mode: to select among: normal/alternate/extend descriptors
1399 * @priv: driver private structure
1400 * Description: select the Enhanced/Alternate or Normal descriptors.
1401 * In case of Enhanced/Alternate, it looks at the extended descriptors are
1402 * supported by the HW cap. register.
1404 static void stmmac_selec_desc_mode(struct stmmac_priv *priv)
1406 if (priv->plat->enh_desc) {
1407 pr_info(" Enhanced/Alternate descriptors\n");
1409 /* GMAC older than 3.50 has no extended descriptors */
1410 if (priv->synopsys_id >= DWMAC_CORE_3_50) {
1411 pr_info("\tEnabled extended descriptors\n");
1412 priv->extend_desc = 1;
1414 pr_warn("Extended descriptors not supported\n");
1416 priv->hw->desc = &enh_desc_ops;
1418 pr_info(" Normal descriptors\n");
1419 priv->hw->desc = &ndesc_ops;
1424 * stmmac_get_hw_features: get MAC capabilities from the HW cap. register.
1425 * @priv: driver private structure
1427 * new GMAC chip generations have a new register to indicate the
1428 * presence of the optional feature/functions.
1429 * This can be also used to override the value passed through the
1430 * platform and necessary for old MAC10/100 and GMAC chips.
1432 static int stmmac_get_hw_features(struct stmmac_priv *priv)
1436 if (priv->hw->dma->get_hw_feature) {
1437 hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr);
1439 priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL);
1440 priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1;
1441 priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2;
1442 priv->dma_cap.hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4;
1443 priv->dma_cap.multi_addr = (hw_cap & DMA_HW_FEAT_ADDMAC) >> 5;
1444 priv->dma_cap.pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6;
1445 priv->dma_cap.sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8;
1446 priv->dma_cap.pmt_remote_wake_up =
1447 (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9;
1448 priv->dma_cap.pmt_magic_frame =
1449 (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10;
1451 priv->dma_cap.rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11;
1452 /* IEEE 1588-2002 */
1453 priv->dma_cap.time_stamp =
1454 (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12;
1455 /* IEEE 1588-2008 */
1456 priv->dma_cap.atime_stamp =
1457 (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13;
1458 /* 802.3az - Energy-Efficient Ethernet (EEE) */
1459 priv->dma_cap.eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14;
1460 priv->dma_cap.av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15;
1461 /* TX and RX csum */
1462 priv->dma_cap.tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16;
1463 priv->dma_cap.rx_coe_type1 =
1464 (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17;
1465 priv->dma_cap.rx_coe_type2 =
1466 (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18;
1467 priv->dma_cap.rxfifo_over_2048 =
1468 (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19;
1469 /* TX and RX number of channels */
1470 priv->dma_cap.number_rx_channel =
1471 (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20;
1472 priv->dma_cap.number_tx_channel =
1473 (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22;
1474 /* Alternate (enhanced) DESC mode */
1475 priv->dma_cap.enh_desc = (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24;
1482 * stmmac_check_ether_addr: check if the MAC addr is valid
1483 * @priv: driver private structure
1485 * it is to verify if the MAC address is valid, in case of failures it
1486 * generates a random MAC address
1488 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
1490 if (!is_valid_ether_addr(priv->dev->dev_addr)) {
1491 priv->hw->mac->get_umac_addr((void __iomem *)
1492 priv->dev->base_addr,
1493 priv->dev->dev_addr, 0);
1494 if (!is_valid_ether_addr(priv->dev->dev_addr))
1495 eth_hw_addr_random(priv->dev);
1497 pr_warn("%s: device MAC address %pM\n", priv->dev->name,
1498 priv->dev->dev_addr);
1502 * stmmac_init_dma_engine: DMA init.
1503 * @priv: driver private structure
1505 * It inits the DMA invoking the specific MAC/GMAC callback.
1506 * Some DMA parameters can be passed from the platform;
1507 * in case of these are not passed a default is kept for the MAC or GMAC.
1509 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
1511 int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, burst_len = 0;
1512 int mixed_burst = 0;
1515 if (priv->plat->dma_cfg) {
1516 pbl = priv->plat->dma_cfg->pbl;
1517 fixed_burst = priv->plat->dma_cfg->fixed_burst;
1518 mixed_burst = priv->plat->dma_cfg->mixed_burst;
1519 burst_len = priv->plat->dma_cfg->burst_len;
1522 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
1525 return priv->hw->dma->init(priv->ioaddr, pbl, fixed_burst, mixed_burst,
1526 burst_len, priv->dma_tx_phy,
1527 priv->dma_rx_phy, atds);
1531 * stmmac_tx_timer: mitigation sw timer for tx.
1532 * @data: data pointer
1534 * This is the timer handler to directly invoke the stmmac_tx_clean.
1536 static void stmmac_tx_timer(unsigned long data)
1538 struct stmmac_priv *priv = (struct stmmac_priv *)data;
1540 stmmac_tx_clean(priv);
1544 * stmmac_init_tx_coalesce: init tx mitigation options.
1545 * @priv: driver private structure
1547 * This inits the transmit coalesce parameters: i.e. timer rate,
1548 * timer handler and default threshold used for enabling the
1549 * interrupt on completion bit.
1551 static void stmmac_init_tx_coalesce(struct stmmac_priv *priv)
1553 priv->tx_coal_frames = STMMAC_TX_FRAMES;
1554 priv->tx_coal_timer = STMMAC_COAL_TX_TIMER;
1555 init_timer(&priv->txtimer);
1556 priv->txtimer.expires = STMMAC_COAL_TIMER(priv->tx_coal_timer);
1557 priv->txtimer.data = (unsigned long)priv;
1558 priv->txtimer.function = stmmac_tx_timer;
1559 add_timer(&priv->txtimer);
1563 * stmmac_open - open entry point of the driver
1564 * @dev : pointer to the device structure.
1566 * This function is the open entry point of the driver.
1568 * 0 on success and an appropriate (-)ve integer as defined in errno.h
1571 static int stmmac_open(struct net_device *dev)
1573 struct stmmac_priv *priv = netdev_priv(dev);
1576 clk_prepare_enable(priv->stmmac_clk);
1578 if (priv->rk_pdata->gmac_io_init) {
1579 priv->rk_pdata->gmac_io_init(priv->device);
1582 stmmac_check_ether_addr(priv);
1584 if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
1585 priv->pcs != STMMAC_PCS_RTBI) {
1586 ret = stmmac_init_phy(dev);
1588 pr_err("%s: Cannot attach to PHY (error: %d)\n",
1594 /* Create and initialize the TX/RX descriptors chains. */
1595 priv->dma_tx_size = STMMAC_ALIGN(dma_txsize);
1596 priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize);
1597 priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
1598 init_dma_desc_rings(dev);
1600 /* DMA initialization and SW reset */
1601 ret = stmmac_init_dma_engine(priv);
1603 pr_err("%s: DMA initialization failed\n", __func__);
1607 /* Copy the MAC addr into the HW */
1608 priv->hw->mac->set_umac_addr(priv->ioaddr, dev->dev_addr, 0);
1610 /* If required, perform hw setup of the bus. */
1611 if (priv->plat->bus_setup)
1612 priv->plat->bus_setup(priv->ioaddr);
1614 /* Initialize the MAC Core */
1615 priv->hw->mac->core_init(priv->ioaddr);
1617 /* Request the IRQ lines */
1618 ret = request_irq(dev->irq, stmmac_interrupt,
1619 IRQF_SHARED, dev->name, dev);
1620 if (unlikely(ret < 0)) {
1621 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
1622 __func__, dev->irq, ret);
1626 /* Request the Wake IRQ in case of another line is used for WoL */
1627 if (priv->wol_irq != dev->irq) {
1628 ret = request_irq(priv->wol_irq, stmmac_interrupt,
1629 IRQF_SHARED, dev->name, dev);
1630 if (unlikely(ret < 0)) {
1631 pr_err("%s: ERROR: allocating the WoL IRQ %d (%d)\n",
1632 __func__, priv->wol_irq, ret);
1633 goto open_error_wolirq;
1637 /* Request the IRQ lines */
1638 if (priv->lpi_irq != -ENXIO) {
1639 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
1641 if (unlikely(ret < 0)) {
1642 pr_err("%s: ERROR: allocating the LPI IRQ %d (%d)\n",
1643 __func__, priv->lpi_irq, ret);
1644 goto open_error_lpiirq;
1648 /* Enable the MAC Rx/Tx */
1649 stmmac_set_mac(priv->ioaddr, true);
1651 /* Set the HW DMA mode and the COE */
1652 stmmac_dma_operation_mode(priv);
1654 /* Extra statistics */
1655 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
1656 priv->xstats.threshold = tc;
1658 stmmac_mmc_setup(priv);
1660 ret = stmmac_init_ptp(priv);
1662 pr_warn("%s: failed PTP initialisation\n", __func__);
1664 #ifdef CONFIG_GMAC_DEBUG_FS
1665 ret = stmmac_init_fs(dev);
1667 pr_warn("%s: failed debugFS registration\n", __func__);
1669 /* Start the ball rolling... */
1670 DBG(probe, DEBUG, "%s: DMA RX/TX processes started...\n", dev->name);
1671 priv->hw->dma->start_tx(priv->ioaddr);
1672 priv->hw->dma->start_rx(priv->ioaddr);
1674 /* Dump DMA/MAC registers */
1675 if (netif_msg_hw(priv)) {
1676 priv->hw->mac->dump_regs(priv->ioaddr);
1677 priv->hw->dma->dump_regs(priv->ioaddr);
1681 phy_start(priv->phydev);
1683 priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS;
1685 priv->eee_enabled = stmmac_eee_init(priv);
1687 stmmac_init_tx_coalesce(priv);
1689 if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) {
1690 priv->rx_riwt = MAX_DMA_RIWT;
1691 priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT);
1694 if (priv->pcs && priv->hw->mac->ctrl_ane)
1695 priv->hw->mac->ctrl_ane(priv->ioaddr, 0);
1697 napi_enable(&priv->napi);
1698 netif_start_queue(dev);
1703 if (priv->wol_irq != dev->irq)
1704 free_irq(priv->wol_irq, dev);
1707 free_irq(dev->irq, dev);
1711 phy_disconnect(priv->phydev);
1713 clk_disable_unprepare(priv->stmmac_clk);
1719 * stmmac_release - close entry point of the driver
1720 * @dev : device pointer.
1722 * This is the stop entry point of the driver.
1724 static int stmmac_release(struct net_device *dev)
1726 struct stmmac_priv *priv = netdev_priv(dev);
1728 if (priv->eee_enabled)
1729 del_timer_sync(&priv->eee_ctrl_timer);
1731 /* Stop and disconnect the PHY */
1733 phy_stop(priv->phydev);
1734 phy_disconnect(priv->phydev);
1735 priv->phydev = NULL;
1738 netif_stop_queue(dev);
1740 napi_disable(&priv->napi);
1742 del_timer_sync(&priv->txtimer);
1744 /* Free the IRQ lines */
1745 free_irq(dev->irq, dev);
1746 if (priv->wol_irq != dev->irq)
1747 free_irq(priv->wol_irq, dev);
1748 if (priv->lpi_irq != -ENXIO)
1749 free_irq(priv->lpi_irq, dev);
1751 /* Stop TX/RX DMA and clear the descriptors */
1752 priv->hw->dma->stop_tx(priv->ioaddr);
1753 priv->hw->dma->stop_rx(priv->ioaddr);
1755 /* Release and free the Rx/Tx resources */
1756 free_dma_desc_resources(priv);
1758 /* Disable the MAC Rx/Tx */
1759 stmmac_set_mac(priv->ioaddr, false);
1761 netif_carrier_off(dev);
1763 #ifdef CONFIG_GMAC_DEBUG_FS
1766 clk_disable_unprepare(priv->stmmac_clk);
1768 stmmac_release_ptp(priv);
1770 if (priv->rk_pdata->gmac_io_deinit) {
1771 priv->rk_pdata->gmac_io_deinit(priv->device);
1778 * stmmac_xmit: Tx entry point of the driver
1779 * @skb : the socket buffer
1780 * @dev : device pointer
1781 * Description : this is the tx entry point of the driver.
1782 * It programs the chain or the ring and supports oversized frames
1785 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
1787 struct stmmac_priv *priv = netdev_priv(dev);
1788 unsigned int txsize = priv->dma_tx_size;
1790 int i, csum_insertion = 0, is_jumbo = 0;
1791 int nfrags = skb_shinfo(skb)->nr_frags;
1792 struct dma_desc *desc, *first;
1793 unsigned int nopaged_len = skb_headlen(skb);
1795 if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) {
1796 if (!netif_queue_stopped(dev)) {
1797 netif_stop_queue(dev);
1798 /* This is a hard error, log it. */
1799 pr_err("%s: Tx Ring full when queue awake\n", __func__);
1801 return NETDEV_TX_BUSY;
1804 spin_lock(&priv->tx_lock);
1806 if (priv->tx_path_in_lpi_mode)
1807 stmmac_disable_eee_mode(priv);
1809 entry = priv->cur_tx % txsize;
1811 #ifdef STMMAC_XMIT_DEBUG
1812 if ((skb->len > ETH_FRAME_LEN) || nfrags)
1813 pr_debug("%s: [entry %d]: skb addr %p len: %d nopagedlen: %d\n"
1814 "\tn_frags: %d - ip_summed: %d - %s gso\n"
1815 "\ttx_count_frames %d\n", __func__, entry,
1816 skb, skb->len, nopaged_len, nfrags, skb->ip_summed,
1817 !skb_is_gso(skb) ? "isn't" : "is",
1818 priv->tx_count_frames);
1821 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
1823 if (priv->extend_desc)
1824 desc = (struct dma_desc *)(priv->dma_etx + entry);
1826 desc = priv->dma_tx + entry;
1830 #ifdef STMMAC_XMIT_DEBUG
1831 if ((nfrags > 0) || (skb->len > ETH_FRAME_LEN))
1832 pr_debug("\tskb len: %d, nopaged_len: %d,\n"
1833 "\t\tn_frags: %d, ip_summed: %d\n",
1834 skb->len, nopaged_len, nfrags, skb->ip_summed);
1836 priv->tx_skbuff[entry] = skb;
1838 /* To program the descriptors according to the size of the frame */
1839 if (priv->mode == STMMAC_RING_MODE) {
1840 is_jumbo = priv->hw->ring->is_jumbo_frm(skb->len,
1841 priv->plat->enh_desc);
1842 if (unlikely(is_jumbo))
1843 entry = priv->hw->ring->jumbo_frm(priv, skb,
1846 is_jumbo = priv->hw->chain->is_jumbo_frm(skb->len,
1847 priv->plat->enh_desc);
1848 if (unlikely(is_jumbo))
1849 entry = priv->hw->chain->jumbo_frm(priv, skb,
1852 if (likely(!is_jumbo)) {
1853 desc->des2 = dma_map_single(priv->device, skb->data,
1854 nopaged_len, DMA_TO_DEVICE);
1855 priv->tx_skbuff_dma[entry] = desc->des2;
1856 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len,
1857 csum_insertion, priv->mode);
1861 for (i = 0; i < nfrags; i++) {
1862 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1863 int len = skb_frag_size(frag);
1865 entry = (++priv->cur_tx) % txsize;
1866 if (priv->extend_desc)
1867 desc = (struct dma_desc *)(priv->dma_etx + entry);
1869 desc = priv->dma_tx + entry;
1871 TX_DBG("\t[entry %d] segment len: %d\n", entry, len);
1872 desc->des2 = skb_frag_dma_map(priv->device, frag, 0, len,
1874 priv->tx_skbuff_dma[entry] = desc->des2;
1875 priv->tx_skbuff[entry] = NULL;
1876 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion,
1879 priv->hw->desc->set_tx_owner(desc);
1883 /* Finalize the latest segment. */
1884 priv->hw->desc->close_tx_desc(desc);
1887 /* According to the coalesce parameter the IC bit for the latest
1888 * segment could be reset and the timer re-started to invoke the
1889 * stmmac_tx function. This approach takes care about the fragments.
1891 priv->tx_count_frames += nfrags + 1;
1892 if (priv->tx_coal_frames > priv->tx_count_frames) {
1893 priv->hw->desc->clear_tx_ic(desc);
1894 priv->xstats.tx_reset_ic_bit++;
1895 TX_DBG("\t[entry %d]: tx_count_frames %d\n", entry,
1896 priv->tx_count_frames);
1897 mod_timer(&priv->txtimer,
1898 STMMAC_COAL_TIMER(priv->tx_coal_timer));
1900 priv->tx_count_frames = 0;
1902 /* To avoid raise condition */
1903 priv->hw->desc->set_tx_owner(first);
1908 #ifdef STMMAC_XMIT_DEBUG
1909 if (netif_msg_pktdata(priv)) {
1910 pr_info("%s: curr %d dirty=%d entry=%d, first=%p, nfrags=%d",
1911 __func__, (priv->cur_tx % txsize),
1912 (priv->dirty_tx % txsize), entry, first, nfrags);
1913 if (priv->extend_desc)
1914 stmmac_display_ring((void *)priv->dma_etx, txsize, 1);
1916 stmmac_display_ring((void *)priv->dma_tx, txsize, 0);
1918 pr_info(">>> frame to be transmitted: ");
1919 print_pkt(skb->data, skb->len);
1922 if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
1923 TX_DBG("%s: stop transmitted packets\n", __func__);
1924 netif_stop_queue(dev);
1927 dev->stats.tx_bytes += skb->len;
1929 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
1930 priv->hwts_tx_en)) {
1931 /* declare that device is doing timestamping */
1932 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1933 priv->hw->desc->enable_tx_timestamp(first);
1936 if (!priv->hwts_tx_en)
1937 skb_tx_timestamp(skb);
1939 priv->hw->dma->enable_dma_transmission(priv->ioaddr);
1941 spin_unlock(&priv->tx_lock);
1943 return NETDEV_TX_OK;
1947 * stmmac_rx_refill: refill used skb preallocated buffers
1948 * @priv: driver private structure
1949 * Description : this is to reallocate the skb for the reception process
1950 * that is based on zero-copy.
1952 static inline void stmmac_rx_refill(struct stmmac_priv *priv)
1954 unsigned int rxsize = priv->dma_rx_size;
1955 int bfsize = priv->dma_buf_sz;
1957 for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) {
1958 unsigned int entry = priv->dirty_rx % rxsize;
1961 if (priv->extend_desc)
1962 p = (struct dma_desc *)(priv->dma_erx + entry);
1964 p = priv->dma_rx + entry;
1966 if (likely(priv->rx_skbuff[entry] == NULL)) {
1967 struct sk_buff *skb;
1969 skb = netdev_alloc_skb_ip_align(priv->dev, bfsize);
1971 if (unlikely(skb == NULL))
1974 priv->rx_skbuff[entry] = skb;
1975 priv->rx_skbuff_dma[entry] =
1976 dma_map_single(priv->device, skb->data, bfsize,
1979 p->des2 = priv->rx_skbuff_dma[entry];
1981 priv->hw->ring->refill_desc3(priv, p);
1983 RX_DBG(KERN_INFO "\trefill entry #%d\n", entry);
1986 priv->hw->desc->set_rx_owner(p);
1992 * stmmac_rx_refill: refill used skb preallocated buffers
1993 * @priv: driver private structure
1994 * @limit: napi bugget.
1995 * Description : this the function called by the napi poll method.
1996 * It gets all the frames inside the ring.
1998 static int stmmac_rx(struct stmmac_priv *priv, int limit)
2000 unsigned int rxsize = priv->dma_rx_size;
2001 unsigned int entry = priv->cur_rx % rxsize;
2002 unsigned int next_entry;
2003 unsigned int count = 0;
2004 int coe = priv->plat->rx_coe;
2006 #ifdef STMMAC_RX_DEBUG
2007 if (netif_msg_hw(priv)) {
2008 pr_debug(">>> stmmac_rx: descriptor ring:\n");
2009 if (priv->extend_desc)
2010 stmmac_display_ring((void *)priv->dma_erx, rxsize, 1);
2012 stmmac_display_ring((void *)priv->dma_rx, rxsize, 0);
2015 while (count < limit) {
2019 if (priv->extend_desc)
2020 p = (struct dma_desc *)(priv->dma_erx + entry);
2022 p = priv->dma_rx + entry;
2024 if (priv->hw->desc->get_rx_owner(p))
2029 next_entry = (++priv->cur_rx) % rxsize;
2030 if (priv->extend_desc)
2031 prefetch(priv->dma_erx + next_entry);
2033 prefetch(priv->dma_rx + next_entry);
2035 /* read the status of the incoming frame */
2036 status = priv->hw->desc->rx_status(&priv->dev->stats,
2038 if ((priv->extend_desc) && (priv->hw->desc->rx_extended_status))
2039 priv->hw->desc->rx_extended_status(&priv->dev->stats,
2043 if (unlikely(status == discard_frame)) {
2044 priv->dev->stats.rx_errors++;
2045 if (priv->hwts_rx_en && !priv->extend_desc) {
2046 /* DESC2 & DESC3 will be overwitten by device
2047 * with timestamp value, hence reinitialize
2048 * them in stmmac_rx_refill() function so that
2049 * device can reuse it.
2051 priv->rx_skbuff[entry] = NULL;
2052 dma_unmap_single(priv->device,
2053 priv->rx_skbuff_dma[entry],
2058 struct sk_buff *skb;
2061 frame_len = priv->hw->desc->get_rx_frame_len(p, coe);
2063 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
2064 * Type frames (LLC/LLC-SNAP)
2066 if (unlikely(status != llc_snap))
2067 frame_len -= ETH_FCS_LEN;
2068 #ifdef STMMAC_RX_DEBUG
2069 if (frame_len > ETH_FRAME_LEN)
2070 pr_debug("\tRX frame size %d, COE status: %d\n",
2073 if (netif_msg_hw(priv))
2074 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n",
2077 skb = priv->rx_skbuff[entry];
2078 if (unlikely(!skb)) {
2079 pr_err("%s: Inconsistent Rx descriptor chain\n",
2081 priv->dev->stats.rx_dropped++;
2084 prefetch(skb->data - NET_IP_ALIGN);
2085 priv->rx_skbuff[entry] = NULL;
2087 stmmac_get_rx_hwtstamp(priv, entry, skb);
2089 skb_put(skb, frame_len);
2090 dma_unmap_single(priv->device,
2091 priv->rx_skbuff_dma[entry],
2092 priv->dma_buf_sz, DMA_FROM_DEVICE);
2093 #ifdef STMMAC_RX_DEBUG
2094 if (netif_msg_pktdata(priv)) {
2095 pr_info(" frame received (%dbytes)", frame_len);
2096 print_pkt(skb->data, frame_len);
2099 skb->protocol = eth_type_trans(skb, priv->dev);
2102 skb_checksum_none_assert(skb);
2104 skb->ip_summed = CHECKSUM_UNNECESSARY;
2106 napi_gro_receive(&priv->napi, skb);
2108 priv->dev->stats.rx_packets++;
2109 priv->dev->stats.rx_bytes += frame_len;
2114 stmmac_rx_refill(priv);
2116 priv->xstats.rx_pkt_n += count;
2122 * stmmac_poll - stmmac poll method (NAPI)
2123 * @napi : pointer to the napi structure.
2124 * @budget : maximum number of packets that the current CPU can receive from
2127 * To look at the incoming frames and clear the tx resources.
2129 static int stmmac_poll(struct napi_struct *napi, int budget)
2131 struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi);
2134 priv->xstats.napi_poll++;
2135 stmmac_tx_clean(priv);
2137 work_done = stmmac_rx(priv, budget);
2138 if (work_done < budget) {
2139 napi_complete(napi);
2140 stmmac_enable_dma_irq(priv);
2147 * @dev : Pointer to net device structure
2148 * Description: this function is called when a packet transmission fails to
2149 * complete within a reasonable time. The driver will mark the error in the
2150 * netdev structure and arrange for the device to be reset to a sane state
2151 * in order to transmit a new packet.
2153 static void stmmac_tx_timeout(struct net_device *dev)
2155 struct stmmac_priv *priv = netdev_priv(dev);
2157 /* Clear Tx resources and restart transmitting again */
2158 stmmac_tx_err(priv);
2161 /* Configuration changes (passed on by ifconfig) */
2162 static int stmmac_config(struct net_device *dev, struct ifmap *map)
2164 if (dev->flags & IFF_UP) /* can't act on a running interface */
2167 /* Don't allow changing the I/O address */
2168 if (map->base_addr != dev->base_addr) {
2169 pr_warn("%s: can't change I/O address\n", dev->name);
2173 /* Don't allow changing the IRQ */
2174 if (map->irq != dev->irq) {
2175 pr_warn("%s: not change IRQ number %d\n", dev->name, dev->irq);
2183 * stmmac_set_rx_mode - entry point for multicast addressing
2184 * @dev : pointer to the device structure
2186 * This function is a driver entry point which gets called by the kernel
2187 * whenever multicast addresses must be enabled/disabled.
2191 static void stmmac_set_rx_mode(struct net_device *dev)
2193 struct stmmac_priv *priv = netdev_priv(dev);
2195 spin_lock(&priv->lock);
2196 priv->hw->mac->set_filter(dev, priv->synopsys_id);
2197 spin_unlock(&priv->lock);
2201 * stmmac_change_mtu - entry point to change MTU size for the device.
2202 * @dev : device pointer.
2203 * @new_mtu : the new MTU size for the device.
2204 * Description: the Maximum Transfer Unit (MTU) is used by the network layer
2205 * to drive packet transmission. Ethernet has an MTU of 1500 octets
2206 * (ETH_DATA_LEN). This value can be changed with ifconfig.
2208 * 0 on success and an appropriate (-)ve integer as defined in errno.h
2211 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
2213 struct stmmac_priv *priv = netdev_priv(dev);
2216 if (netif_running(dev)) {
2217 pr_err("%s: must be stopped to change its MTU\n", dev->name);
2221 if (priv->plat->enh_desc)
2222 max_mtu = JUMBO_LEN;
2224 max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
2226 if ((new_mtu < 46) || (new_mtu > max_mtu)) {
2227 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu);
2232 netdev_update_features(dev);
2237 static netdev_features_t stmmac_fix_features(struct net_device *dev,
2238 netdev_features_t features)
2240 struct stmmac_priv *priv = netdev_priv(dev);
2242 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
2243 features &= ~NETIF_F_RXCSUM;
2244 else if (priv->plat->rx_coe == STMMAC_RX_COE_TYPE1)
2245 features &= ~NETIF_F_IPV6_CSUM;
2246 if (!priv->plat->tx_coe)
2247 features &= ~NETIF_F_ALL_CSUM;
2249 /* Some GMAC devices have a bugged Jumbo frame support that
2250 * needs to have the Tx COE disabled for oversized frames
2251 * (due to limited buffer sizes). In this case we disable
2252 * the TX csum insertionin the TDES and not use SF.
2254 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
2255 features &= ~NETIF_F_ALL_CSUM;
2261 * stmmac_interrupt - main ISR
2262 * @irq: interrupt number.
2263 * @dev_id: to pass the net device pointer.
2264 * Description: this is the main driver interrupt service routine.
2265 * It calls the DMA ISR and also the core ISR to manage PMT, MMC, LPI
2268 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
2270 struct net_device *dev = (struct net_device *)dev_id;
2271 struct stmmac_priv *priv = netdev_priv(dev);
2273 if (unlikely(!dev)) {
2274 pr_err("%s: invalid dev pointer\n", __func__);
2278 /* To handle GMAC own interrupts */
2279 if (priv->plat->has_gmac) {
2280 int status = priv->hw->mac->host_irq_status((void __iomem *)
2283 if (unlikely(status)) {
2284 /* For LPI we need to save the tx status */
2285 if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
2286 priv->tx_path_in_lpi_mode = true;
2287 if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
2288 priv->tx_path_in_lpi_mode = false;
2292 /* To handle DMA interrupts */
2293 stmmac_dma_interrupt(priv);
2298 #ifdef CONFIG_NET_POLL_CONTROLLER
2299 /* Polling receive - used by NETCONSOLE and other diagnostic tools
2300 * to allow network I/O with interrupts disabled.
2302 static void stmmac_poll_controller(struct net_device *dev)
2304 disable_irq(dev->irq);
2305 stmmac_interrupt(dev->irq, dev);
2306 enable_irq(dev->irq);
2311 * stmmac_ioctl - Entry point for the Ioctl
2312 * @dev: Device pointer.
2313 * @rq: An IOCTL specefic structure, that can contain a pointer to
2314 * a proprietary structure used to pass information to the driver.
2315 * @cmd: IOCTL command
2317 * Currently it supports the phy_mii_ioctl(...) and HW time stamping.
2319 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2321 struct stmmac_priv *priv = netdev_priv(dev);
2322 int ret = -EOPNOTSUPP;
2324 if (!netif_running(dev))
2333 ret = phy_mii_ioctl(priv->phydev, rq, cmd);
2336 ret = stmmac_hwtstamp_ioctl(dev, rq);
2345 #ifdef CONFIG_GMAC_DEBUG_FS
2346 static struct dentry *stmmac_fs_dir;
2347 static struct dentry *stmmac_rings_status;
2348 static struct dentry *stmmac_dma_cap;
2350 static void sysfs_display_ring(void *head, int size, int extend_desc,
2351 struct seq_file *seq)
2354 struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
2355 struct dma_desc *p = (struct dma_desc *)head;
2357 for (i = 0; i < size; i++) {
2361 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2362 i, (unsigned int)virt_to_phys(ep),
2363 (unsigned int)x, (unsigned int)(x >> 32),
2364 ep->basic.des2, ep->basic.des3);
2368 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2369 i, (unsigned int)virt_to_phys(ep),
2370 (unsigned int)x, (unsigned int)(x >> 32),
2374 seq_printf(seq, "\n");
2378 static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v)
2380 struct net_device *dev = seq->private;
2381 struct stmmac_priv *priv = netdev_priv(dev);
2382 unsigned int txsize = priv->dma_tx_size;
2383 unsigned int rxsize = priv->dma_rx_size;
2385 if (priv->extend_desc) {
2386 seq_printf(seq, "Extended RX descriptor ring:\n");
2387 sysfs_display_ring((void *)priv->dma_erx, rxsize, 1, seq);
2388 seq_printf(seq, "Extended TX descriptor ring:\n");
2389 sysfs_display_ring((void *)priv->dma_etx, txsize, 1, seq);
2391 seq_printf(seq, "RX descriptor ring:\n");
2392 sysfs_display_ring((void *)priv->dma_rx, rxsize, 0, seq);
2393 seq_printf(seq, "TX descriptor ring:\n");
2394 sysfs_display_ring((void *)priv->dma_tx, txsize, 0, seq);
2400 static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file)
2402 return single_open(file, stmmac_sysfs_ring_read, inode->i_private);
2405 static const struct file_operations stmmac_rings_status_fops = {
2406 .owner = THIS_MODULE,
2407 .open = stmmac_sysfs_ring_open,
2409 .llseek = seq_lseek,
2410 .release = single_release,
2413 static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v)
2415 struct net_device *dev = seq->private;
2416 struct stmmac_priv *priv = netdev_priv(dev);
2418 if (!priv->hw_cap_support) {
2419 seq_printf(seq, "DMA HW features not supported\n");
2423 seq_printf(seq, "==============================\n");
2424 seq_printf(seq, "\tDMA HW features\n");
2425 seq_printf(seq, "==============================\n");
2427 seq_printf(seq, "\t10/100 Mbps %s\n",
2428 (priv->dma_cap.mbps_10_100) ? "Y" : "N");
2429 seq_printf(seq, "\t1000 Mbps %s\n",
2430 (priv->dma_cap.mbps_1000) ? "Y" : "N");
2431 seq_printf(seq, "\tHalf duple %s\n",
2432 (priv->dma_cap.half_duplex) ? "Y" : "N");
2433 seq_printf(seq, "\tHash Filter: %s\n",
2434 (priv->dma_cap.hash_filter) ? "Y" : "N");
2435 seq_printf(seq, "\tMultiple MAC address registers: %s\n",
2436 (priv->dma_cap.multi_addr) ? "Y" : "N");
2437 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n",
2438 (priv->dma_cap.pcs) ? "Y" : "N");
2439 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
2440 (priv->dma_cap.sma_mdio) ? "Y" : "N");
2441 seq_printf(seq, "\tPMT Remote wake up: %s\n",
2442 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
2443 seq_printf(seq, "\tPMT Magic Frame: %s\n",
2444 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
2445 seq_printf(seq, "\tRMON module: %s\n",
2446 (priv->dma_cap.rmon) ? "Y" : "N");
2447 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
2448 (priv->dma_cap.time_stamp) ? "Y" : "N");
2449 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n",
2450 (priv->dma_cap.atime_stamp) ? "Y" : "N");
2451 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n",
2452 (priv->dma_cap.eee) ? "Y" : "N");
2453 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
2454 seq_printf(seq, "\tChecksum Offload in TX: %s\n",
2455 (priv->dma_cap.tx_coe) ? "Y" : "N");
2456 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
2457 (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
2458 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
2459 (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
2460 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
2461 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
2462 seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
2463 priv->dma_cap.number_rx_channel);
2464 seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
2465 priv->dma_cap.number_tx_channel);
2466 seq_printf(seq, "\tEnhanced descriptors: %s\n",
2467 (priv->dma_cap.enh_desc) ? "Y" : "N");
2472 static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file)
2474 return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private);
2477 static const struct file_operations stmmac_dma_cap_fops = {
2478 .owner = THIS_MODULE,
2479 .open = stmmac_sysfs_dma_cap_open,
2481 .llseek = seq_lseek,
2482 .release = single_release,
2485 static int stmmac_init_fs(struct net_device *dev)
2487 /* Create debugfs entries */
2488 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
2490 if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
2491 pr_err("ERROR %s, debugfs create directory failed\n",
2492 STMMAC_RESOURCE_NAME);
2497 /* Entry to report DMA RX/TX rings */
2498 stmmac_rings_status = debugfs_create_file("descriptors_status",
2499 S_IRUGO, stmmac_fs_dir, dev,
2500 &stmmac_rings_status_fops);
2502 if (!stmmac_rings_status || IS_ERR(stmmac_rings_status)) {
2503 pr_info("ERROR creating stmmac ring debugfs file\n");
2504 debugfs_remove(stmmac_fs_dir);
2509 /* Entry to report the DMA HW features */
2510 stmmac_dma_cap = debugfs_create_file("dma_cap", S_IRUGO, stmmac_fs_dir,
2511 dev, &stmmac_dma_cap_fops);
2513 if (!stmmac_dma_cap || IS_ERR(stmmac_dma_cap)) {
2514 pr_info("ERROR creating stmmac MMC debugfs file\n");
2515 debugfs_remove(stmmac_rings_status);
2516 debugfs_remove(stmmac_fs_dir);
2524 static void stmmac_exit_fs(void)
2526 debugfs_remove(stmmac_rings_status);
2527 debugfs_remove(stmmac_dma_cap);
2528 debugfs_remove(stmmac_fs_dir);
2530 #endif /* CONFIG_GMAC_DEBUG_FS */
2532 static const struct net_device_ops stmmac_netdev_ops = {
2533 .ndo_open = stmmac_open,
2534 .ndo_start_xmit = stmmac_xmit,
2535 .ndo_stop = stmmac_release,
2536 .ndo_change_mtu = stmmac_change_mtu,
2537 .ndo_fix_features = stmmac_fix_features,
2538 .ndo_set_rx_mode = stmmac_set_rx_mode,
2539 .ndo_tx_timeout = stmmac_tx_timeout,
2540 .ndo_do_ioctl = stmmac_ioctl,
2541 .ndo_set_config = stmmac_config,
2542 #ifdef CONFIG_NET_POLL_CONTROLLER
2543 .ndo_poll_controller = stmmac_poll_controller,
2545 .ndo_set_mac_address = eth_mac_addr,
2549 * stmmac_hw_init - Init the MAC device
2550 * @priv: driver private structure
2551 * Description: this function detects which MAC device
2552 * (GMAC/MAC10-100) has to attached, checks the HW capability
2553 * (if supported) and sets the driver's features (for example
2554 * to use the ring or chaine mode or support the normal/enh
2555 * descriptor structure).
2557 static int stmmac_hw_init(struct stmmac_priv *priv)
2560 struct mac_device_info *mac;
2562 /* Identify the MAC HW device */
2563 if (priv->plat->has_gmac) {
2564 priv->dev->priv_flags |= IFF_UNICAST_FLT;
2565 mac = dwmac1000_setup(priv->ioaddr);
2567 mac = dwmac100_setup(priv->ioaddr);
2574 /* Get and dump the chip ID */
2575 priv->synopsys_id = stmmac_get_synopsys_id(priv);
2577 /* To use alternate (extended) or normal descriptor structures */
2578 stmmac_selec_desc_mode(priv);
2580 /* To use the chained or ring mode */
2582 priv->hw->chain = &chain_mode_ops;
2583 pr_info(" Chain mode enabled\n");
2584 priv->mode = STMMAC_CHAIN_MODE;
2586 priv->hw->ring = &ring_mode_ops;
2587 pr_info(" Ring mode enabled\n");
2588 priv->mode = STMMAC_RING_MODE;
2591 /* Get the HW capability (new GMAC newer than 3.50a) */
2592 priv->hw_cap_support = stmmac_get_hw_features(priv);
2593 if (priv->hw_cap_support) {
2594 pr_info(" DMA HW capability register supported");
2596 /* We can override some gmac/dma configuration fields: e.g.
2597 * enh_desc, tx_coe (e.g. that are passed through the
2598 * platform) with the values from the HW capability
2599 * register (if supported).
2601 priv->plat->enh_desc = priv->dma_cap.enh_desc;
2602 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
2604 priv->plat->tx_coe = priv->dma_cap.tx_coe;
2606 if (priv->dma_cap.rx_coe_type2)
2607 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
2608 else if (priv->dma_cap.rx_coe_type1)
2609 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
2612 pr_info(" No HW DMA feature register supported");
2614 ret = priv->hw->mac->rx_ipc(priv->ioaddr);
2616 pr_warn(" RX IPC Checksum Offload not configured.\n");
2617 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
2620 if (priv->plat->rx_coe)
2621 pr_info(" RX Checksum Offload Engine supported (type %d)\n",
2622 priv->plat->rx_coe);
2623 if (priv->plat->tx_coe)
2624 pr_info(" TX Checksum insertion supported\n");
2626 if (priv->plat->pmt) {
2627 pr_info(" Wake-Up On Lan supported\n");
2628 device_set_wakeup_capable(priv->device, 1);
2636 * @device: device pointer
2637 * @plat_dat: platform data pointer
2638 * @addr: iobase memory address
2639 * Description: this is the main probe function used to
2640 * call the alloc_etherdev, allocate the priv structure.
2642 struct stmmac_priv *stmmac_dvr_probe(struct device *device,
2643 struct plat_stmmacenet_data *plat_dat,
2647 struct net_device *ndev = NULL;
2648 struct stmmac_priv *priv;
2650 ndev = alloc_etherdev(sizeof(struct stmmac_priv));
2654 SET_NETDEV_DEV(ndev, device);
2656 priv = netdev_priv(ndev);
2657 priv->device = device;
2662 stmmac_set_ethtool_ops(ndev);
2663 priv->pause = pause;
2664 priv->plat = plat_dat;
2665 priv->ioaddr = addr;
2666 priv->dev->base_addr = (unsigned long)addr;
2668 /* Verify driver arguments */
2669 stmmac_verify_args();
2671 /* Override with kernel parameters if supplied XXX CRS XXX
2672 * this needs to have multiple instances
2674 if ((phyaddr >= 0) && (phyaddr <= 31))
2675 priv->plat->phy_addr = phyaddr;
2677 /* Init MAC and get the capabilities */
2678 ret = stmmac_hw_init(priv);
2680 goto error_free_netdev;
2682 ndev->netdev_ops = &stmmac_netdev_ops;
2684 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2686 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
2687 ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
2688 #ifdef STMMAC_VLAN_TAG_USED
2689 /* Both mac100 and gmac support receive VLAN tag detection */
2690 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
2692 priv->msg_enable = netif_msg_init(debug, default_msg_level);
2695 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */
2697 /* Rx Watchdog is available in the COREs newer than the 3.40.
2698 * In some case, for example on bugged HW this feature
2699 * has to be disable and this can be done by passing the
2700 * riwt_off field from the platform.
2702 if ((priv->synopsys_id >= DWMAC_CORE_3_50) && (!priv->plat->riwt_off)) {
2704 pr_info(" Enable RX Mitigation via HW Watchdog Timer\n");
2707 netif_napi_add(ndev, &priv->napi, stmmac_poll, 64);
2709 spin_lock_init(&priv->lock);
2710 spin_lock_init(&priv->tx_lock);
2712 ret = register_netdev(ndev);
2714 pr_err("%s: ERROR %i registering the device\n", __func__, ret);
2715 goto error_netdev_register;
2718 priv->stmmac_clk = clk_get(priv->device, STMMAC_RESOURCE_NAME);
2719 if (IS_ERR(priv->stmmac_clk)) {
2720 pr_warn("%s: warning: cannot get CSR clock\n", __func__);
2724 /* If a specific clk_csr value is passed from the platform
2725 * this means that the CSR Clock Range selection cannot be
2726 * changed at run-time and it is fixed. Viceversa the driver'll try to
2727 * set the MDC clock dynamically according to the csr actual
2730 if (!priv->plat->clk_csr)
2731 stmmac_clk_csr_set(priv);
2733 priv->clk_csr = priv->plat->clk_csr;
2735 stmmac_check_pcs_mode(priv);
2737 if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
2738 priv->pcs != STMMAC_PCS_RTBI) {
2739 /* MDIO bus Registration */
2740 ret = stmmac_mdio_register(ndev);
2742 pr_debug("%s: MDIO bus (id: %d) registration failed",
2743 __func__, priv->plat->bus_id);
2744 goto error_mdio_register;
2750 error_mdio_register:
2751 clk_put(priv->stmmac_clk);
2753 unregister_netdev(ndev);
2754 error_netdev_register:
2755 netif_napi_del(&priv->napi);
2764 * @ndev: net device pointer
2765 * Description: this function resets the TX/RX processes, disables the MAC RX/TX
2766 * changes the link status, releases the DMA descriptor rings.
2768 int stmmac_dvr_remove(struct net_device *ndev)
2770 struct stmmac_priv *priv = netdev_priv(ndev);
2772 pr_info("%s:\n\tremoving driver", __func__);
2774 priv->hw->dma->stop_rx(priv->ioaddr);
2775 priv->hw->dma->stop_tx(priv->ioaddr);
2777 stmmac_set_mac(priv->ioaddr, false);
2778 if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
2779 priv->pcs != STMMAC_PCS_RTBI)
2780 stmmac_mdio_unregister(ndev);
2781 netif_carrier_off(ndev);
2782 unregister_netdev(ndev);
2789 int stmmac_suspend(struct net_device *ndev)
2791 struct stmmac_priv *priv = netdev_priv(ndev);
2792 unsigned long flags;
2794 if (!ndev || !netif_running(ndev))
2798 phy_stop(priv->phydev);
2800 spin_lock_irqsave(&priv->lock, flags);
2802 netif_device_detach(ndev);
2803 netif_stop_queue(ndev);
2805 napi_disable(&priv->napi);
2807 /* Stop TX/RX DMA */
2808 priv->hw->dma->stop_tx(priv->ioaddr);
2809 priv->hw->dma->stop_rx(priv->ioaddr);
2811 stmmac_clear_descriptors(priv);
2813 /* Enable Power down mode by programming the PMT regs */
2814 if (device_may_wakeup(priv->device))
2815 priv->hw->mac->pmt(priv->ioaddr, priv->wolopts);
2817 stmmac_set_mac(priv->ioaddr, false);
2818 /* Disable clock in case of PWM is off */
2819 clk_disable_unprepare(priv->stmmac_clk);
2821 spin_unlock_irqrestore(&priv->lock, flags);
2825 int stmmac_resume(struct net_device *ndev)
2827 struct stmmac_priv *priv = netdev_priv(ndev);
2828 unsigned long flags;
2830 if (!netif_running(ndev))
2833 spin_lock_irqsave(&priv->lock, flags);
2835 /* Power Down bit, into the PM register, is cleared
2836 * automatically as soon as a magic packet or a Wake-up frame
2837 * is received. Anyway, it's better to manually clear
2838 * this bit because it can generate problems while resuming
2839 * from another devices (e.g. serial console).
2841 if (device_may_wakeup(priv->device))
2842 priv->hw->mac->pmt(priv->ioaddr, 0);
2844 /* enable the clk prevously disabled */
2845 clk_prepare_enable(priv->stmmac_clk);
2847 netif_device_attach(ndev);
2849 /* Enable the MAC and DMA */
2850 stmmac_set_mac(priv->ioaddr, true);
2851 priv->hw->dma->start_tx(priv->ioaddr);
2852 priv->hw->dma->start_rx(priv->ioaddr);
2854 napi_enable(&priv->napi);
2856 netif_start_queue(ndev);
2858 spin_unlock_irqrestore(&priv->lock, flags);
2861 phy_start(priv->phydev);
2866 int stmmac_freeze(struct net_device *ndev)
2868 if (!ndev || !netif_running(ndev))
2871 return stmmac_release(ndev);
2874 int stmmac_restore(struct net_device *ndev)
2876 if (!ndev || !netif_running(ndev))
2879 return stmmac_open(ndev);
2881 #endif /* CONFIG_PM */
2883 /* Driver can be configured w/ and w/ both PCI and Platf drivers
2884 * depending on the configuration selected.
2886 static int __init stmmac_init(void)
2890 ret = stmmac_register_platform();
2893 ret = stmmac_register_pci();
2898 stmmac_unregister_platform();
2900 pr_err("stmmac: driver registration failed\n");
2904 static void __exit stmmac_exit(void)
2906 stmmac_unregister_platform();
2907 stmmac_unregister_pci();
2910 module_init(stmmac_init);
2911 module_exit(stmmac_exit);
2914 static int __init stmmac_cmdline_opt(char *str)
2920 while ((opt = strsep(&str, ",")) != NULL) {
2921 if (!strncmp(opt, "debug:", 6)) {
2922 if (kstrtoint(opt + 6, 0, &debug))
2924 } else if (!strncmp(opt, "phyaddr:", 8)) {
2925 if (kstrtoint(opt + 8, 0, &phyaddr))
2927 } else if (!strncmp(opt, "dma_txsize:", 11)) {
2928 if (kstrtoint(opt + 11, 0, &dma_txsize))
2930 } else if (!strncmp(opt, "dma_rxsize:", 11)) {
2931 if (kstrtoint(opt + 11, 0, &dma_rxsize))
2933 } else if (!strncmp(opt, "buf_sz:", 7)) {
2934 if (kstrtoint(opt + 7, 0, &buf_sz))
2936 } else if (!strncmp(opt, "tc:", 3)) {
2937 if (kstrtoint(opt + 3, 0, &tc))
2939 } else if (!strncmp(opt, "watchdog:", 9)) {
2940 if (kstrtoint(opt + 9, 0, &watchdog))
2942 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
2943 if (kstrtoint(opt + 10, 0, &flow_ctrl))
2945 } else if (!strncmp(opt, "pause:", 6)) {
2946 if (kstrtoint(opt + 6, 0, &pause))
2948 } else if (!strncmp(opt, "eee_timer:", 10)) {
2949 if (kstrtoint(opt + 10, 0, &eee_timer))
2951 } else if (!strncmp(opt, "chain_mode:", 11)) {
2952 if (kstrtoint(opt + 11, 0, &chain_mode))
2959 pr_err("%s: ERROR broken module parameter conversion", __func__);
2963 __setup("stmmaceth=", stmmac_cmdline_opt);
2966 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
2967 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
2968 MODULE_LICENSE("GPL");