drivers/net/ethernet/rockchip/gmac/stmmac_main.c

   1 /*******************************************************************************
   2   This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
   3   ST Ethernet IPs are built around a Synopsys IP Core.
   4
   5         Copyright(C) 2007-2011 STMicroelectronics Ltd
   6
   7   This program is free software; you can redistribute it and/or modify it
   8   under the terms and conditions of the GNU General Public License,
   9   version 2, as published by the Free Software Foundation.
  10
  11   This program is distributed in the hope it will be useful, but WITHOUT
  12   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14   more details.
  15
  16   You should have received a copy of the GNU General Public License along with
  17   this program; if not, write to the Free Software Foundation, Inc.,
  18   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  19
  20   The full GNU General Public License is included in this distribution in
  21   the file called "COPYING".
  22
  23   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  24
  25   Documentation available at:
  26         http://www.stlinux.com
  27   Support available at:
  28         https://bugzilla.stlinux.com/
  29 *******************************************************************************/
  30
  31 #include <linux/clk.h>
  32 #include <linux/kernel.h>
  33 #include <linux/interrupt.h>
  34 #include <linux/ip.h>
  35 #include <linux/tcp.h>
  36 #include <linux/skbuff.h>
  37 #include <linux/ethtool.h>
  38 #include <linux/if_ether.h>
  39 #include <linux/crc32.h>
  40 #include <linux/mii.h>
  41 #include <linux/if.h>
  42 #include <linux/if_vlan.h>
  43 #include <linux/dma-mapping.h>
  44 #include <linux/slab.h>
  45 #include <linux/prefetch.h>
  46 #ifdef CONFIG_GMAC_DEBUG_FS
  47 #include <linux/debugfs.h>
  48 #include <linux/seq_file.h>
  49 #endif /* CONFIG_GMAC_DEBUG_FS */
  50 #include <linux/net_tstamp.h>
  51 #include "stmmac_ptp.h"
  52 #include "stmmac.h"
  53
  54 #undef STMMAC_DEBUG
  55 /*#define STMMAC_DEBUG*/
  56 #ifdef STMMAC_DEBUG
  57 #define DBG(nlevel, klevel, fmt, args...) \
  58                 ((void)(netif_msg_##nlevel(priv) && \
  59                 printk(KERN_##klevel fmt, ## args)))
  60 #else
  61 #define DBG(nlevel, klevel, fmt, args...) do { } while (0)
  62 #endif
  63
  64 #undef STMMAC_RX_DEBUG
  65 /*#define STMMAC_RX_DEBUG*/
  66 #ifdef STMMAC_RX_DEBUG
  67 #define RX_DBG(fmt, args...)  printk(fmt, ## args)
  68 #else
  69 #define RX_DBG(fmt, args...)  do { } while (0)
  70 #endif
  71
  72 #undef STMMAC_XMIT_DEBUG
  73 /*#define STMMAC_XMIT_DEBUG*/
  74 #ifdef STMMAC_XMIT_DEBUG
  75 #define TX_DBG(fmt, args...)  printk(fmt, ## args)
  76 #else
  77 #define TX_DBG(fmt, args...)  do { } while (0)
  78 #endif
  79
  80 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
  81 #define JUMBO_LEN       9000
  82
  83 /* Module parameters */
  84 #define TX_TIMEO        5000
  85 static int watchdog = TX_TIMEO;
  86 module_param(watchdog, int, S_IRUGO | S_IWUSR);
  87 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");
  88
  89 static int debug = -1;
  90 module_param(debug, int, S_IRUGO | S_IWUSR);
  91 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
  92
  93 int phyaddr = -1;
  94 module_param(phyaddr, int, S_IRUGO);
  95 MODULE_PARM_DESC(phyaddr, "Physical device address");
  96
  97 #define DMA_TX_SIZE 256
  98 static int dma_txsize = DMA_TX_SIZE;
  99 module_param(dma_txsize, int, S_IRUGO | S_IWUSR);
 100 MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list");
 101
 102 #define DMA_RX_SIZE 256
 103 static int dma_rxsize = DMA_RX_SIZE;
 104 module_param(dma_rxsize, int, S_IRUGO | S_IWUSR);
 105 MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list");
 106
 107 static int flow_ctrl = FLOW_OFF;
 108 module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
 109 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
 110
 111 static int pause = PAUSE_TIME;
 112 module_param(pause, int, S_IRUGO | S_IWUSR);
 113 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
 114
 115 #define TC_DEFAULT 64
 116 static int tc = TC_DEFAULT;
 117 module_param(tc, int, S_IRUGO | S_IWUSR);
 118 MODULE_PARM_DESC(tc, "DMA threshold control value");
 119
 120 #define DMA_BUFFER_SIZE BUF_SIZE_2KiB
 121 static int buf_sz = DMA_BUFFER_SIZE;
 122 module_param(buf_sz, int, S_IRUGO | S_IWUSR);
 123 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
 124
 125 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
 126                                       NETIF_MSG_LINK | NETIF_MSG_IFUP |
 127                                       NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
 128
 129 #define STMMAC_DEFAULT_LPI_TIMER        1000
 130 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
 131 module_param(eee_timer, int, S_IRUGO | S_IWUSR);
 132 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
 133 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x))
 134
 135 /* By default the driver will use the ring mode to manage tx and rx descriptors
 136  * but passing this value so user can force to use the chain instead of the ring
 137  */
 138 static unsigned int chain_mode;
 139 module_param(chain_mode, int, S_IRUGO);
 140 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
 141
 142 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
 143
 144 #ifdef CONFIG_GMAC_DEBUG_FS
 145 static int stmmac_init_fs(struct net_device *dev);
 146 static void stmmac_exit_fs(void);
 147 #endif
 148
 149 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
 150
 151 /**
 152  * stmmac_verify_args - verify the driver parameters.
 153  * Description: it verifies if some wrong parameter is passed to the driver.
 154  * Note that wrong parameters are replaced with the default values.
 155  */
 156 static void stmmac_verify_args(void)
 157 {
 158         if (unlikely(watchdog < 0))
 159                 watchdog = TX_TIMEO;
 160         if (unlikely(dma_rxsize < 0))
 161                 dma_rxsize = DMA_RX_SIZE;
 162         if (unlikely(dma_txsize < 0))
 163                 dma_txsize = DMA_TX_SIZE;
 164         if (unlikely((buf_sz < DMA_BUFFER_SIZE) || (buf_sz > BUF_SIZE_16KiB)))
 165                 buf_sz = DMA_BUFFER_SIZE;
 166         if (unlikely(flow_ctrl > 1))
 167                 flow_ctrl = FLOW_AUTO;
 168         else if (likely(flow_ctrl < 0))
 169                 flow_ctrl = FLOW_OFF;
 170         if (unlikely((pause < 0) || (pause > 0xffff)))
 171                 pause = PAUSE_TIME;
 172         if (eee_timer < 0)
 173                 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
 174 }
 175
 176 /**
 177  * stmmac_clk_csr_set - dynamically set the MDC clock
 178  * @priv: driver private structure
 179  * Description: this is to dynamically set the MDC clock according to the csr
 180  * clock input.
 181  * Note:
 182  *      If a specific clk_csr value is passed from the platform
 183  *      this means that the CSR Clock Range selection cannot be
 184  *      changed at run-time and it is fixed (as reported in the driver
 185  *      documentation). Viceversa the driver will try to set the MDC
 186  *      clock dynamically according to the actual clock input.
 187  */
 188 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
 189 {
 190         u32 clk_rate;
 191
 192         clk_rate = clk_get_rate(priv->stmmac_clk);
 193
 194         /* Platform provided default clk_csr would be assumed valid
 195          * for all other cases except for the below mentioned ones.
 196          * For values higher than the IEEE 802.3 specified frequency
 197          * we can not estimate the proper divider as it is not known
 198          * the frequency of clk_csr_i. So we do not change the default
 199          * divider.
 200          */
 201         if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
 202                 if (clk_rate < CSR_F_35M)
 203                         priv->clk_csr = STMMAC_CSR_20_35M;
 204                 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
 205                         priv->clk_csr = STMMAC_CSR_35_60M;
 206                 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
 207                         priv->clk_csr = STMMAC_CSR_60_100M;
 208                 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
 209                         priv->clk_csr = STMMAC_CSR_100_150M;
 210                 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
 211                         priv->clk_csr = STMMAC_CSR_150_250M;
 212                 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
 213                         priv->clk_csr = STMMAC_CSR_250_300M;
 214         }
 215 }
 216
 217 #if defined(STMMAC_XMIT_DEBUG) || defined(STMMAC_RX_DEBUG)
 218 static void print_pkt(unsigned char *buf, int len)
 219 {
 220         int j;
 221         pr_info("len = %d byte, buf addr: 0x%p", len, buf);
 222         for (j = 0; j < len; j++) {
 223                 if ((j % 16) == 0)
 224                         pr_info("\n %03x:", j);
 225                 pr_info(" %02x", buf[j]);
 226         }
 227         pr_info("\n");
 228 }
 229 #endif
 230
 231 /* minimum number of free TX descriptors required to wake up TX process */
 232 #define STMMAC_TX_THRESH(x)     (x->dma_tx_size/4)
 233
 234 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
 235 {
 236         return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1;
 237 }
 238
 239 /**
 240  * stmmac_hw_fix_mac_speed: callback for speed selection
 241  * @priv: driver private structure
 242  * Description: on some platforms (e.g. ST), some HW system configuraton
 243  * registers have to be set according to the link speed negotiated.
 244  */
 245 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
 246 {
 247         struct phy_device *phydev = priv->phydev;
 248
 249         if (likely(priv->plat->fix_mac_speed))
 250                 priv->plat->fix_mac_speed(priv->plat->bsp_priv, phydev->speed);
 251
 252         if (priv->rk_pdata->gmac_speed_switch) {
 253                 priv->rk_pdata->gmac_speed_switch(phydev->speed);
 254         }
 255 }
 256
 257 /**
 258  * stmmac_enable_eee_mode: Check and enter in LPI mode
 259  * @priv: driver private structure
 260  * Description: this function is to verify and enter in LPI mode for EEE.
 261  */
 262 static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
 263 {
 264         /* Check and enter in LPI mode */
 265         if ((priv->dirty_tx == priv->cur_tx) &&
 266             (priv->tx_path_in_lpi_mode == false))
 267                 priv->hw->mac->set_eee_mode(priv->ioaddr);
 268 }
 269
 270 /**
 271  * stmmac_disable_eee_mode: disable/exit from EEE
 272  * @priv: driver private structure
 273  * Description: this function is to exit and disable EEE in case of
 274  * LPI state is true. This is called by the xmit.
 275  */
 276 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
 277 {
 278         priv->hw->mac->reset_eee_mode(priv->ioaddr);
 279         del_timer_sync(&priv->eee_ctrl_timer);
 280         priv->tx_path_in_lpi_mode = false;
 281 }
 282
 283 /**
 284  * stmmac_eee_ctrl_timer: EEE TX SW timer.
 285  * @arg : data hook
 286  * Description:
 287  *  if there is no data transfer and if we are not in LPI state,
 288  *  then MAC Transmitter can be moved to LPI state.
 289  */
 290 static void stmmac_eee_ctrl_timer(unsigned long arg)
 291 {
 292         struct stmmac_priv *priv = (struct stmmac_priv *)arg;
 293
 294         stmmac_enable_eee_mode(priv);
 295         mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
 296 }
 297
 298 /**
 299  * stmmac_eee_init: init EEE
 300  * @priv: driver private structure
 301  * Description:
 302  *  If the EEE support has been enabled while configuring the driver,
 303  *  if the GMAC actually supports the EEE (from the HW cap reg) and the
 304  *  phy can also manage EEE, so enable the LPI state and start the timer
 305  *  to verify if the tx path can enter in LPI state.
 306  */
 307 bool stmmac_eee_init(struct stmmac_priv *priv)
 308 {
 309         bool ret = false;
 310
 311         /* Using PCS we cannot dial with the phy registers at this stage
 312          * so we do not support extra feature like EEE.
 313          */
 314         if ((priv->pcs == STMMAC_PCS_RGMII) || (priv->pcs == STMMAC_PCS_TBI) ||
 315             (priv->pcs == STMMAC_PCS_RTBI))
 316                 goto out;
 317
 318         /* MAC core supports the EEE feature. */
 319         if (priv->dma_cap.eee) {
 320                 /* Check if the PHY supports EEE */
 321                 if (phy_init_eee(priv->phydev, 1))
 322                         goto out;
 323
 324                 if (!priv->eee_active) {
 325                         priv->eee_active = 1;
 326                         init_timer(&priv->eee_ctrl_timer);
 327                         priv->eee_ctrl_timer.function = stmmac_eee_ctrl_timer;
 328                         priv->eee_ctrl_timer.data = (unsigned long)priv;
 329                         priv->eee_ctrl_timer.expires = STMMAC_LPI_T(eee_timer);
 330                         add_timer(&priv->eee_ctrl_timer);
 331
 332                         priv->hw->mac->set_eee_timer(priv->ioaddr,
 333                                                      STMMAC_DEFAULT_LIT_LS,
 334                                                      priv->tx_lpi_timer);
 335                 } else
 336                         /* Set HW EEE according to the speed */
 337                         priv->hw->mac->set_eee_pls(priv->ioaddr,
 338                                                    priv->phydev->link);
 339
 340                 pr_info("stmmac: Energy-Efficient Ethernet initialized\n");
 341
 342                 ret = true;
 343         }
 344 out:
 345         return ret;
 346 }
 347
 348 /* stmmac_get_tx_hwtstamp: get HW TX timestamps
 349  * @priv: driver private structure
 350  * @entry : descriptor index to be used.
 351  * @skb : the socket buffer
 352  * Description :
 353  * This function will read timestamp from the descriptor & pass it to stack.
 354  * and also perform some sanity checks.
 355  */
 356 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
 357                                    unsigned int entry, struct sk_buff *skb)
 358 {
 359         struct skb_shared_hwtstamps shhwtstamp;
 360         u64 ns;
 361         void *desc = NULL;
 362
 363         if (!priv->hwts_tx_en)
 364                 return;
 365
 366         /* exit if skb doesn't support hw tstamp */
 367         if (likely(!(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
 368                 return;
 369
 370         if (priv->adv_ts)
 371                 desc = (priv->dma_etx + entry);
 372         else
 373                 desc = (priv->dma_tx + entry);
 374
 375         /* check tx tstamp status */
 376         if (!priv->hw->desc->get_tx_timestamp_status((struct dma_desc *)desc))
 377                 return;
 378
 379         /* get the valid tstamp */
 380         ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);
 381
 382         memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
 383         shhwtstamp.hwtstamp = ns_to_ktime(ns);
 384         /* pass tstamp to stack */
 385         skb_tstamp_tx(skb, &shhwtstamp);
 386
 387         return;
 388 }
 389
 390 /* stmmac_get_rx_hwtstamp: get HW RX timestamps
 391  * @priv: driver private structure
 392  * @entry : descriptor index to be used.
 393  * @skb : the socket buffer
 394  * Description :
 395  * This function will read received packet's timestamp from the descriptor
 396  * and pass it to stack. It also perform some sanity checks.
 397  */
 398 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv,
 399                                    unsigned int entry, struct sk_buff *skb)
 400 {
 401         struct skb_shared_hwtstamps *shhwtstamp = NULL;
 402         u64 ns;
 403         void *desc = NULL;
 404
 405         if (!priv->hwts_rx_en)
 406                 return;
 407
 408         if (priv->adv_ts)
 409                 desc = (priv->dma_erx + entry);
 410         else
 411                 desc = (priv->dma_rx + entry);
 412
 413         /* exit if rx tstamp is not valid */
 414         if (!priv->hw->desc->get_rx_timestamp_status(desc, priv->adv_ts))
 415                 return;
 416
 417         /* get valid tstamp */
 418         ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);
 419         shhwtstamp = skb_hwtstamps(skb);
 420         memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
 421         shhwtstamp->hwtstamp = ns_to_ktime(ns);
 422 }
 423
 424 /**
 425  *  stmmac_hwtstamp_ioctl - control hardware timestamping.
 426  *  @dev: device pointer.
 427  *  @ifr: An IOCTL specefic structure, that can contain a pointer to
 428  *  a proprietary structure used to pass information to the driver.
 429  *  Description:
 430  *  This function configures the MAC to enable/disable both outgoing(TX)
 431  *  and incoming(RX) packets time stamping based on user input.
 432  *  Return Value:
 433  *  0 on success and an appropriate -ve integer on failure.
 434  */
 435 static int stmmac_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr)
 436 {
 437         struct stmmac_priv *priv = netdev_priv(dev);
 438         struct hwtstamp_config config;
 439         struct timespec now;
 440         u64 temp = 0;
 441         u32 ptp_v2 = 0;
 442         u32 tstamp_all = 0;
 443         u32 ptp_over_ipv4_udp = 0;
 444         u32 ptp_over_ipv6_udp = 0;
 445         u32 ptp_over_ethernet = 0;
 446         u32 snap_type_sel = 0;
 447         u32 ts_master_en = 0;
 448         u32 ts_event_en = 0;
 449         u32 value = 0;
 450
 451         if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
 452                 netdev_alert(priv->dev, "No support for HW time stamping\n");
 453                 priv->hwts_tx_en = 0;
 454                 priv->hwts_rx_en = 0;
 455
 456                 return -EOPNOTSUPP;
 457         }
 458
 459         if (copy_from_user(&config, ifr->ifr_data,
 460                            sizeof(struct hwtstamp_config)))
 461                 return -EFAULT;
 462
 463         pr_debug("%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
 464                  __func__, config.flags, config.tx_type, config.rx_filter);
 465
 466         /* reserved for future extensions */
 467         if (config.flags)
 468                 return -EINVAL;
 469
 470         switch (config.tx_type) {
 471         case HWTSTAMP_TX_OFF:
 472                 priv->hwts_tx_en = 0;
 473                 break;
 474         case HWTSTAMP_TX_ON:
 475                 priv->hwts_tx_en = 1;
 476                 break;
 477         default:
 478                 return -ERANGE;
 479         }
 480
 481         if (priv->adv_ts) {
 482                 switch (config.rx_filter) {
 483                 case HWTSTAMP_FILTER_NONE:
 484                         /* time stamp no incoming packet at all */
 485                         config.rx_filter = HWTSTAMP_FILTER_NONE;
 486                         break;
 487
 488                 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
 489                         /* PTP v1, UDP, any kind of event packet */
 490                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
 491                         /* take time stamp for all event messages */
 492                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 493
 494                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 495                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 496                         break;
 497
 498                 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
 499                         /* PTP v1, UDP, Sync packet */
 500                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
 501                         /* take time stamp for SYNC messages only */
 502                         ts_event_en = PTP_TCR_TSEVNTENA;
 503
 504                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 505                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 506                         break;
 507
 508                 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
 509                         /* PTP v1, UDP, Delay_req packet */
 510                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
 511                         /* take time stamp for Delay_Req messages only */
 512                         ts_master_en = PTP_TCR_TSMSTRENA;
 513                         ts_event_en = PTP_TCR_TSEVNTENA;
 514
 515                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 516                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 517                         break;
 518
 519                 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
 520                         /* PTP v2, UDP, any kind of event packet */
 521                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
 522                         ptp_v2 = PTP_TCR_TSVER2ENA;
 523                         /* take time stamp for all event messages */
 524                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 525
 526                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 527                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 528                         break;
 529
 530                 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
 531                         /* PTP v2, UDP, Sync packet */
 532                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
 533                         ptp_v2 = PTP_TCR_TSVER2ENA;
 534                         /* take time stamp for SYNC messages only */
 535                         ts_event_en = PTP_TCR_TSEVNTENA;
 536
 537                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 538                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 539                         break;
 540
 541                 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
 542                         /* PTP v2, UDP, Delay_req packet */
 543                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
 544                         ptp_v2 = PTP_TCR_TSVER2ENA;
 545                         /* take time stamp for Delay_Req messages only */
 546                         ts_master_en = PTP_TCR_TSMSTRENA;
 547                         ts_event_en = PTP_TCR_TSEVNTENA;
 548
 549                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 550                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 551                         break;
 552
 553                 case HWTSTAMP_FILTER_PTP_V2_EVENT:
 554                         /* PTP v2/802.AS1 any layer, any kind of event packet */
 555                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
 556                         ptp_v2 = PTP_TCR_TSVER2ENA;
 557                         /* take time stamp for all event messages */
 558                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 559
 560                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 561                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 562                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 563                         break;
 564
 565                 case HWTSTAMP_FILTER_PTP_V2_SYNC:
 566                         /* PTP v2/802.AS1, any layer, Sync packet */
 567                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
 568                         ptp_v2 = PTP_TCR_TSVER2ENA;
 569                         /* take time stamp for SYNC messages only */
 570                         ts_event_en = PTP_TCR_TSEVNTENA;
 571
 572                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 573                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 574                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 575                         break;
 576
 577                 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
 578                         /* PTP v2/802.AS1, any layer, Delay_req packet */
 579                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
 580                         ptp_v2 = PTP_TCR_TSVER2ENA;
 581                         /* take time stamp for Delay_Req messages only */
 582                         ts_master_en = PTP_TCR_TSMSTRENA;
 583                         ts_event_en = PTP_TCR_TSEVNTENA;
 584
 585                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 586                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 587                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 588                         break;
 589
 590                 case HWTSTAMP_FILTER_ALL:
 591                         /* time stamp any incoming packet */
 592                         config.rx_filter = HWTSTAMP_FILTER_ALL;
 593                         tstamp_all = PTP_TCR_TSENALL;
 594                         break;
 595
 596                 default:
 597                         return -ERANGE;
 598                 }
 599         } else {
 600                 switch (config.rx_filter) {
 601                 case HWTSTAMP_FILTER_NONE:
 602                         config.rx_filter = HWTSTAMP_FILTER_NONE;
 603                         break;
 604                 default:
 605                         /* PTP v1, UDP, any kind of event packet */
 606                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
 607                         break;
 608                 }
 609         }
 610         priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
 611
 612         if (!priv->hwts_tx_en && !priv->hwts_rx_en)
 613                 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, 0);
 614         else {
 615                 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR |
 616                          tstamp_all | ptp_v2 | ptp_over_ethernet |
 617                          ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en |
 618                          ts_master_en | snap_type_sel);
 619
 620                 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, value);
 621
 622                 /* program Sub Second Increment reg */
 623                 priv->hw->ptp->config_sub_second_increment(priv->ioaddr);
 624
 625                 /* calculate default added value:
 626                  * formula is :
 627                  * addend = (2^32)/freq_div_ratio;
 628                  * where, freq_div_ratio = STMMAC_SYSCLOCK/50MHz
 629                  * hence, addend = ((2^32) * 50MHz)/STMMAC_SYSCLOCK;
 630                  * NOTE: STMMAC_SYSCLOCK should be >= 50MHz to
 631                  *       achive 20ns accuracy.
 632                  *
 633                  * 2^x * y == (y << x), hence
 634                  * 2^32 * 50000000 ==> (50000000 << 32)
 635                  */
 636                 temp = (u64) (50000000ULL << 32);
 637                 priv->default_addend = div_u64(temp, STMMAC_SYSCLOCK);
 638                 priv->hw->ptp->config_addend(priv->ioaddr,
 639                                              priv->default_addend);
 640
 641                 /* initialize system time */
 642                 getnstimeofday(&now);
 643                 priv->hw->ptp->init_systime(priv->ioaddr, now.tv_sec,
 644                                             now.tv_nsec);
 645         }
 646
 647         return copy_to_user(ifr->ifr_data, &config,
 648                             sizeof(struct hwtstamp_config)) ? -EFAULT : 0;
 649 }
 650
 651 /**
 652  * stmmac_init_ptp: init PTP
 653  * @priv: driver private structure
 654  * Description: this is to verify if the HW supports the PTPv1 or v2.
 655  * This is done by looking at the HW cap. register.
 656  * Also it registers the ptp driver.
 657  */
 658 static int stmmac_init_ptp(struct stmmac_priv *priv)
 659 {
 660         if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
 661                 return -EOPNOTSUPP;
 662
 663         if (netif_msg_hw(priv)) {
 664                 if (priv->dma_cap.time_stamp) {
 665                         pr_debug("IEEE 1588-2002 Time Stamp supported\n");
 666                         priv->adv_ts = 0;
 667                 }
 668                 if (priv->dma_cap.atime_stamp && priv->extend_desc) {
 669                         pr_debug
 670                             ("IEEE 1588-2008 Advanced Time Stamp supported\n");
 671                         priv->adv_ts = 1;
 672                 }
 673         }
 674
 675         priv->hw->ptp = &stmmac_ptp;
 676         priv->hwts_tx_en = 0;
 677         priv->hwts_rx_en = 0;
 678
 679         return stmmac_ptp_register(priv);
 680 }
 681
 682 static void stmmac_release_ptp(struct stmmac_priv *priv)
 683 {
 684         stmmac_ptp_unregister(priv);
 685 }
 686
 687 /**
 688  * stmmac_adjust_link
 689  * @dev: net device structure
 690  * Description: it adjusts the link parameters.
 691  */
 692 static void stmmac_adjust_link(struct net_device *dev)
 693 {
 694         struct stmmac_priv *priv = netdev_priv(dev);
 695         struct phy_device *phydev = priv->phydev;
 696         unsigned long flags;
 697         int new_state = 0;
 698         unsigned int fc = priv->flow_ctrl, pause_time = priv->pause;
 699
 700         if (phydev == NULL)
 701                 return;
 702
 703         DBG(probe, DEBUG, "stmmac_adjust_link: called.  address %d link %d\n",
 704             phydev->addr, phydev->link);
 705
 706         spin_lock_irqsave(&priv->lock, flags);
 707
 708         if (phydev->link) {
 709                 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
 710
 711                 /* Now we make sure that we can be in full duplex mode.
 712                  * If not, we operate in half-duplex mode. */
 713                 if (phydev->duplex != priv->oldduplex) {
 714                         new_state = 1;
 715                         if (!(phydev->duplex))
 716                                 ctrl &= ~priv->hw->link.duplex;
 717                         else
 718                                 ctrl |= priv->hw->link.duplex;
 719                         priv->oldduplex = phydev->duplex;
 720                 }
 721                 /* Flow Control operation */
 722                 if (phydev->pause)
 723                         priv->hw->mac->flow_ctrl(priv->ioaddr, phydev->duplex,
 724                                                  fc, pause_time);
 725
 726                 if (phydev->speed != priv->speed) {
 727                         new_state = 1;
 728                         switch (phydev->speed) {
 729                         case 1000:
 730                                 if (likely(priv->plat->has_gmac))
 731                                         ctrl &= ~priv->hw->link.port;
 732                                 stmmac_hw_fix_mac_speed(priv);
 733                                 break;
 734                         case 100:
 735                         case 10:
 736                                 if (priv->plat->has_gmac) {
 737                                         ctrl |= priv->hw->link.port;
 738                                         if (phydev->speed == SPEED_100) {
 739                                                 ctrl |= priv->hw->link.speed;
 740                                         } else {
 741                                                 ctrl &= ~(priv->hw->link.speed);
 742                                         }
 743                                 } else {
 744                                         ctrl &= ~priv->hw->link.port;
 745                                 }
 746                                 stmmac_hw_fix_mac_speed(priv);
 747                                 break;
 748                         default:
 749                                 if (netif_msg_link(priv))
 750                                         pr_warn("%s: Speed (%d) not 10/100\n",
 751                                                 dev->name, phydev->speed);
 752                                 break;
 753                         }
 754
 755                         priv->speed = phydev->speed;
 756                 }
 757
 758                 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
 759
 760                 if (!priv->oldlink) {
 761                         new_state = 1;
 762                         priv->oldlink = 1;
 763                 }
 764         } else if (priv->oldlink) {
 765                 new_state = 1;
 766                 priv->oldlink = 0;
 767                 priv->speed = 0;
 768                 priv->oldduplex = -1;
 769         }
 770
 771         if (new_state && netif_msg_link(priv))
 772                 phy_print_status(phydev);
 773
 774         /* At this stage, it could be needed to setup the EEE or adjust some
 775          * MAC related HW registers.
 776          */
 777         priv->eee_enabled = stmmac_eee_init(priv);
 778
 779         spin_unlock_irqrestore(&priv->lock, flags);
 780
 781         DBG(probe, DEBUG, "stmmac_adjust_link: exiting\n");
 782 }
 783
 784 /**
 785  * stmmac_check_pcs_mode: verify if RGMII/SGMII is supported
 786  * @priv: driver private structure
 787  * Description: this is to verify if the HW supports the PCS.
 788  * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
 789  * configured for the TBI, RTBI, or SGMII PHY interface.
 790  */
 791 static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
 792 {
 793         int interface = priv->plat->interface;
 794
 795         if (priv->dma_cap.pcs) {
 796                 if ((interface & PHY_INTERFACE_MODE_RGMII) ||
 797                     (interface & PHY_INTERFACE_MODE_RGMII_ID) ||
 798                     (interface & PHY_INTERFACE_MODE_RGMII_RXID) ||
 799                     (interface & PHY_INTERFACE_MODE_RGMII_TXID)) {
 800                         pr_debug("STMMAC: PCS RGMII support enable\n");
 801                         priv->pcs = STMMAC_PCS_RGMII;
 802                 } else if (interface & PHY_INTERFACE_MODE_SGMII) {
 803                         pr_debug("STMMAC: PCS SGMII support enable\n");
 804                         priv->pcs = STMMAC_PCS_SGMII;
 805                 }
 806         }
 807 }
 808
 809 /**
 810  * stmmac_init_phy - PHY initialization
 811  * @dev: net device structure
 812  * Description: it initializes the driver's PHY state, and attaches the PHY
 813  * to the mac driver.
 814  *  Return value:
 815  *  0 on success
 816  */
 817 static int stmmac_init_phy(struct net_device *dev)
 818 {
 819         struct stmmac_priv *priv = netdev_priv(dev);
 820         struct phy_device *phydev;
 821         char phy_id_fmt[MII_BUS_ID_SIZE + 3];
 822         char bus_id[MII_BUS_ID_SIZE];
 823         int interface = priv->plat->interface;
 824         priv->oldlink = 0;
 825         priv->speed = 0;
 826         priv->oldduplex = -1;
 827
 828         if (priv->plat->phy_bus_name)
 829                 snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x",
 830                          priv->plat->phy_bus_name, priv->plat->bus_id);
 831         else
 832                 snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x",
 833                          priv->plat->bus_id);
 834
 835         snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
 836                  priv->plat->phy_addr);
 837         pr_debug("stmmac_init_phy:  trying to attach to %s\n", phy_id_fmt);
 838
 839         phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link, interface);
 840
 841         if (IS_ERR(phydev)) {
 842                 pr_err("%s: Could not attach to PHY\n", dev->name);
 843                 return PTR_ERR(phydev);
 844         }
 845
 846         /* Stop Advertising 1000BASE Capability if interface is not GMII */
 847         if ((interface == PHY_INTERFACE_MODE_MII) ||
 848             (interface == PHY_INTERFACE_MODE_RMII))
 849                 phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
 850                                          SUPPORTED_1000baseT_Full);
 851
 852         /*
 853          * Broken HW is sometimes missing the pull-up resistor on the
 854          * MDIO line, which results in reads to non-existent devices returning
 855          * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
 856          * device as well.
 857          * Note: phydev->phy_id is the result of reading the UID PHY registers.
 858          */
 859         if (phydev->phy_id == 0) {
 860                 phy_disconnect(phydev);
 861                 return -ENODEV;
 862         }
 863         pr_debug("stmmac_init_phy:  %s: attached to PHY (UID 0x%x)"
 864                  " Link = %d\n", dev->name, phydev->phy_id, phydev->link);
 865
 866         priv->phydev = phydev;
 867
 868         return 0;
 869 }
 870
 871 /**
 872  * stmmac_display_ring: display ring
 873  * @head: pointer to the head of the ring passed.
 874  * @size: size of the ring.
 875  * @extend_desc: to verify if extended descriptors are used.
 876  * Description: display the control/status and buffer descriptors.
 877  */
 878 static void stmmac_display_ring(void *head, int size, int extend_desc)
 879 {
 880         int i;
 881         struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
 882         struct dma_desc *p = (struct dma_desc *)head;
 883
 884         for (i = 0; i < size; i++) {
 885                 u64 x;
 886                 if (extend_desc) {
 887                         x = *(u64 *) ep;
 888                         pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
 889                                 i, (unsigned int)virt_to_phys(ep),
 890                                 (unsigned int)x, (unsigned int)(x >> 32),
 891                                 ep->basic.des2, ep->basic.des3);
 892                         ep++;
 893                 } else {
 894                         x = *(u64 *) p;
 895                         pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x",
 896                                 i, (unsigned int)virt_to_phys(p),
 897                                 (unsigned int)x, (unsigned int)(x >> 32),
 898                                 p->des2, p->des3);
 899                         p++;
 900                 }
 901                 pr_info("\n");
 902         }
 903 }
 904
 905 static void stmmac_display_rings(struct stmmac_priv *priv)
 906 {
 907         unsigned int txsize = priv->dma_tx_size;
 908         unsigned int rxsize = priv->dma_rx_size;
 909
 910         if (priv->extend_desc) {
 911                 pr_info("Extended RX descriptor ring:\n");
 912                 stmmac_display_ring((void *)priv->dma_erx, rxsize, 1);
 913                 pr_info("Extended TX descriptor ring:\n");
 914                 stmmac_display_ring((void *)priv->dma_etx, txsize, 1);
 915         } else {
 916                 pr_info("RX descriptor ring:\n");
 917                 stmmac_display_ring((void *)priv->dma_rx, rxsize, 0);
 918                 pr_info("TX descriptor ring:\n");
 919                 stmmac_display_ring((void *)priv->dma_tx, txsize, 0);
 920         }
 921 }
 922
 923 static int stmmac_set_bfsize(int mtu, int bufsize)
 924 {
 925         int ret = bufsize;
 926
 927         if (mtu >= BUF_SIZE_4KiB)
 928                 ret = BUF_SIZE_8KiB;
 929         else if (mtu >= BUF_SIZE_2KiB)
 930                 ret = BUF_SIZE_4KiB;
 931         else if (mtu >= DMA_BUFFER_SIZE)
 932                 ret = BUF_SIZE_2KiB;
 933         else
 934                 ret = DMA_BUFFER_SIZE;
 935
 936         return ret;
 937 }
 938
 939 /**
 940  * stmmac_clear_descriptors: clear descriptors
 941  * @priv: driver private structure
 942  * Description: this function is called to clear the tx and rx descriptors
 943  * in case of both basic and extended descriptors are used.
 944  */
 945 static void stmmac_clear_descriptors(struct stmmac_priv *priv)
 946 {
 947         int i;
 948         unsigned int txsize = priv->dma_tx_size;
 949         unsigned int rxsize = priv->dma_rx_size;
 950
 951         /* Clear the Rx/Tx descriptors */
 952         for (i = 0; i < rxsize; i++)
 953                 if (priv->extend_desc)
 954                         priv->hw->desc->init_rx_desc(&priv->dma_erx[i].basic,
 955                                                      priv->use_riwt, priv->mode,
 956                                                      (i == rxsize - 1));
 957                 else
 958                         priv->hw->desc->init_rx_desc(&priv->dma_rx[i],
 959                                                      priv->use_riwt, priv->mode,
 960                                                      (i == rxsize - 1));
 961         for (i = 0; i < txsize; i++)
 962                 if (priv->extend_desc)
 963                         priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
 964                                                      priv->mode,
 965                                                      (i == txsize - 1));
 966                 else
 967                         priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
 968                                                      priv->mode,
 969                                                      (i == txsize - 1));
 970 }
 971
 972 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
 973                                   int i)
 974 {
 975         struct sk_buff *skb;
 976
 977         skb = __netdev_alloc_skb(priv->dev, priv->dma_buf_sz + NET_IP_ALIGN,
 978                                  GFP_KERNEL);
 979         if (unlikely(skb == NULL)) {
 980                 pr_err("%s: Rx init fails; skb is NULL\n", __func__);
 981                 return 1;
 982         }
 983         skb_reserve(skb, NET_IP_ALIGN);
 984         priv->rx_skbuff[i] = skb;
 985         priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
 986                                                 priv->dma_buf_sz,
 987                                                 DMA_FROM_DEVICE);
 988
 989         p->des2 = priv->rx_skbuff_dma[i];
 990
 991         if ((priv->mode == STMMAC_RING_MODE) &&
 992             (priv->dma_buf_sz == BUF_SIZE_16KiB))
 993                 priv->hw->ring->init_desc3(p);
 994
 995         return 0;
 996 }
 997
 998 /**
 999  * init_dma_desc_rings - init the RX/TX descriptor rings
1000  * @dev: net device structure
1001  * Description:  this function initializes the DMA RX/TX descriptors
1002  * and allocates the socket buffers. It suppors the chained and ring
1003  * modes.
1004  */
1005 static void init_dma_desc_rings(struct net_device *dev)
1006 {
1007         int i;
1008         struct stmmac_priv *priv = netdev_priv(dev);
1009         unsigned int txsize = priv->dma_tx_size;
1010         unsigned int rxsize = priv->dma_rx_size;
1011         unsigned int bfsize = 0;
1012
1013         /* Set the max buffer size according to the DESC mode
1014          * and the MTU. Note that RING mode allows 16KiB bsize.
1015          */
1016         if (priv->mode == STMMAC_RING_MODE)
1017                 bfsize = priv->hw->ring->set_16kib_bfsize(dev->mtu);
1018
1019         if (bfsize < BUF_SIZE_16KiB)
1020                 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
1021
1022         DBG(probe, INFO, "stmmac: txsize %d, rxsize %d, bfsize %d\n",
1023             txsize, rxsize, bfsize);
1024
1025         if (priv->extend_desc) {
1026                 priv->dma_erx = dma_alloc_coherent(priv->device, rxsize *
1027                                                    sizeof(struct
1028                                                           dma_extended_desc),
1029                                                    &priv->dma_rx_phy,
1030                                                    GFP_KERNEL);
1031                 priv->dma_etx = dma_alloc_coherent(priv->device, txsize *
1032                                                    sizeof(struct
1033                                                           dma_extended_desc),
1034                                                    &priv->dma_tx_phy,
1035                                                    GFP_KERNEL);
1036                 if ((!priv->dma_erx) || (!priv->dma_etx))
1037                         return;
1038         } else {
1039                 priv->dma_rx = dma_alloc_coherent(priv->device, rxsize *
1040                                                   sizeof(struct dma_desc),
1041                                                   &priv->dma_rx_phy,
1042                                                   GFP_KERNEL);
1043                 priv->dma_tx = dma_alloc_coherent(priv->device, txsize *
1044                                                   sizeof(struct dma_desc),
1045                                                   &priv->dma_tx_phy,
1046                                                   GFP_KERNEL);
1047                 if ((!priv->dma_rx) || (!priv->dma_tx))
1048                         return;
1049         }
1050
1051         priv->rx_skbuff_dma = kmalloc_array(rxsize, sizeof(dma_addr_t),
1052                                             GFP_KERNEL);
1053         priv->rx_skbuff = kmalloc_array(rxsize, sizeof(struct sk_buff *),
1054                                         GFP_KERNEL);
1055         priv->tx_skbuff_dma = kmalloc_array(txsize, sizeof(dma_addr_t),
1056                                             GFP_KERNEL);
1057         priv->tx_skbuff = kmalloc_array(txsize, sizeof(struct sk_buff *),
1058                                         GFP_KERNEL);
1059         if (netif_msg_drv(priv))
1060                 pr_debug("(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n", __func__,
1061                          (u32) priv->dma_rx_phy, (u32) priv->dma_tx_phy);
1062
1063         /* RX INITIALIZATION */
1064         DBG(probe, INFO, "stmmac: SKB addresses:\nskb\t\tskb data\tdma data\n");
1065         for (i = 0; i < rxsize; i++) {
1066                 struct dma_desc *p;
1067                 if (priv->extend_desc)
1068                         p = &((priv->dma_erx + i)->basic);
1069                 else
1070                         p = priv->dma_rx + i;
1071
1072                 if (stmmac_init_rx_buffers(priv, p, i))
1073                         break;
1074
1075                 DBG(probe, INFO, "[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i],
1076                     priv->rx_skbuff[i]->data, priv->rx_skbuff_dma[i]);
1077         }
1078         priv->cur_rx = 0;
1079         priv->dirty_rx = (unsigned int)(i - rxsize);
1080         priv->dma_buf_sz = bfsize;
1081         buf_sz = bfsize;
1082
1083         /* Setup the chained descriptor addresses */
1084         if (priv->mode == STMMAC_CHAIN_MODE) {
1085                 if (priv->extend_desc) {
1086                         priv->hw->chain->init(priv->dma_erx, priv->dma_rx_phy,
1087                                               rxsize, 1);
1088                         priv->hw->chain->init(priv->dma_etx, priv->dma_tx_phy,
1089                                               txsize, 1);
1090                 } else {
1091                         priv->hw->chain->init(priv->dma_rx, priv->dma_rx_phy,
1092                                               rxsize, 0);
1093                         priv->hw->chain->init(priv->dma_tx, priv->dma_tx_phy,
1094                                               txsize, 0);
1095                 }
1096         }
1097
1098         /* TX INITIALIZATION */
1099         for (i = 0; i < txsize; i++) {
1100                 struct dma_desc *p;
1101                 if (priv->extend_desc)
1102                         p = &((priv->dma_etx + i)->basic);
1103                 else
1104                         p = priv->dma_tx + i;
1105                 p->des2 = 0;
1106                 priv->tx_skbuff_dma[i] = 0;
1107                 priv->tx_skbuff[i] = NULL;
1108         }
1109
1110         priv->dirty_tx = 0;
1111         priv->cur_tx = 0;
1112
1113         stmmac_clear_descriptors(priv);
1114
1115         if (netif_msg_hw(priv))
1116                 stmmac_display_rings(priv);
1117 }
1118
1119 static void dma_free_rx_skbufs(struct stmmac_priv *priv)
1120 {
1121         int i;
1122
1123         for (i = 0; i < priv->dma_rx_size; i++) {
1124                 if (priv->rx_skbuff[i]) {
1125                         dma_unmap_single(priv->device, priv->rx_skbuff_dma[i],
1126                                          priv->dma_buf_sz, DMA_FROM_DEVICE);
1127                         dev_kfree_skb_any(priv->rx_skbuff[i]);
1128                 }
1129                 priv->rx_skbuff[i] = NULL;
1130         }
1131 }
1132
1133 static void dma_free_tx_skbufs(struct stmmac_priv *priv)
1134 {
1135         int i;
1136
1137         for (i = 0; i < priv->dma_tx_size; i++) {
1138                 if (priv->tx_skbuff[i] != NULL) {
1139                         struct dma_desc *p;
1140                         if (priv->extend_desc)
1141                                 p = &((priv->dma_etx + i)->basic);
1142                         else
1143                                 p = priv->dma_tx + i;
1144
1145                         if (priv->tx_skbuff_dma[i])
1146                                 dma_unmap_single(priv->device,
1147                                                  priv->tx_skbuff_dma[i],
1148                                                  priv->hw->desc->get_tx_len(p),
1149                                                  DMA_TO_DEVICE);
1150                         dev_kfree_skb_any(priv->tx_skbuff[i]);
1151                         priv->tx_skbuff[i] = NULL;
1152                         priv->tx_skbuff_dma[i] = 0;
1153                 }
1154         }
1155 }
1156
1157 static void free_dma_desc_resources(struct stmmac_priv *priv)
1158 {
1159         /* Release the DMA TX/RX socket buffers */
1160         dma_free_rx_skbufs(priv);
1161         dma_free_tx_skbufs(priv);
1162
1163         /* Free DMA regions of consistent memory previously allocated */
1164         if (!priv->extend_desc) {
1165                 dma_free_coherent(priv->device,
1166                                   priv->dma_tx_size * sizeof(struct dma_desc),
1167                                   priv->dma_tx, priv->dma_tx_phy);
1168                 dma_free_coherent(priv->device,
1169                                   priv->dma_rx_size * sizeof(struct dma_desc),
1170                                   priv->dma_rx, priv->dma_rx_phy);
1171         } else {
1172                 dma_free_coherent(priv->device, priv->dma_tx_size *
1173                                   sizeof(struct dma_extended_desc),
1174                                   priv->dma_etx, priv->dma_tx_phy);
1175                 dma_free_coherent(priv->device, priv->dma_rx_size *
1176                                   sizeof(struct dma_extended_desc),
1177                                   priv->dma_erx, priv->dma_rx_phy);
1178         }
1179         kfree(priv->rx_skbuff_dma);
1180         kfree(priv->rx_skbuff);
1181         kfree(priv->tx_skbuff_dma);
1182         kfree(priv->tx_skbuff);
1183 }
1184
1185 /**
1186  *  stmmac_dma_operation_mode - HW DMA operation mode
1187  *  @priv: driver private structure
1188  *  Description: it sets the DMA operation mode: tx/rx DMA thresholds
1189  *  or Store-And-Forward capability.
1190  */
1191 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
1192 {
1193         if (likely(priv->plat->force_sf_dma_mode ||
1194                    ((priv->plat->tx_coe) && (!priv->no_csum_insertion)))) {
1195                 /*
1196                  * In case of GMAC, SF mode can be enabled
1197                  * to perform the TX COE in HW. This depends on:
1198                  * 1) TX COE if actually supported
1199                  * 2) There is no bugged Jumbo frame support
1200                  *    that needs to not insert csum in the TDES.
1201                  */
1202                 priv->hw->dma->dma_mode(priv->ioaddr, SF_DMA_MODE, SF_DMA_MODE);
1203                 tc = SF_DMA_MODE;
1204         } else
1205                 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
1206 }
1207
1208 /**
1209  * stmmac_tx_clean:
1210  * @priv: driver private structure
1211  * Description: it reclaims resources after transmission completes.
1212  */
1213 static void stmmac_tx_clean(struct stmmac_priv *priv)
1214 {
1215         unsigned int txsize = priv->dma_tx_size;
1216
1217         spin_lock(&priv->tx_lock);
1218
1219         priv->xstats.tx_clean++;
1220
1221         while (priv->dirty_tx != priv->cur_tx) {
1222                 int last;
1223                 unsigned int entry = priv->dirty_tx % txsize;
1224                 struct sk_buff *skb = priv->tx_skbuff[entry];
1225                 struct dma_desc *p;
1226
1227                 if (priv->extend_desc)
1228                         p = (struct dma_desc *)(priv->dma_etx + entry);
1229                 else
1230                         p = priv->dma_tx + entry;
1231
1232                 /* Check if the descriptor is owned by the DMA. */
1233                 if (priv->hw->desc->get_tx_owner(p))
1234                         break;
1235
1236                 /* Verify tx error by looking at the last segment. */
1237                 last = priv->hw->desc->get_tx_ls(p);
1238                 if (likely(last)) {
1239                         int tx_error =
1240                             priv->hw->desc->tx_status(&priv->dev->stats,
1241                                                       &priv->xstats, p,
1242                                                       priv->ioaddr);
1243                         if (likely(tx_error == 0)) {
1244                                 priv->dev->stats.tx_packets++;
1245                                 priv->xstats.tx_pkt_n++;
1246                         } else
1247                                 priv->dev->stats.tx_errors++;
1248
1249                         stmmac_get_tx_hwtstamp(priv, entry, skb);
1250                 }
1251                 TX_DBG("%s: curr %d, dirty %d\n", __func__,
1252                        priv->cur_tx, priv->dirty_tx);
1253
1254                 if (likely(priv->tx_skbuff_dma[entry])) {
1255                         dma_unmap_single(priv->device,
1256                                          priv->tx_skbuff_dma[entry],
1257                                          priv->hw->desc->get_tx_len(p),
1258                                          DMA_TO_DEVICE);
1259                         priv->tx_skbuff_dma[entry] = 0;
1260                 }
1261                 priv->hw->ring->clean_desc3(priv, p);
1262
1263                 if (likely(skb != NULL)) {
1264                         dev_kfree_skb(skb);
1265                         priv->tx_skbuff[entry] = NULL;
1266                 }
1267
1268                 priv->hw->desc->release_tx_desc(p, priv->mode);
1269
1270                 priv->dirty_tx++;
1271         }
1272         if (unlikely(netif_queue_stopped(priv->dev) &&
1273                      stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) {
1274                 netif_tx_lock(priv->dev);
1275                 if (netif_queue_stopped(priv->dev) &&
1276                     stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) {
1277                         TX_DBG("%s: restart transmit\n", __func__);
1278                         netif_wake_queue(priv->dev);
1279                 }
1280                 netif_tx_unlock(priv->dev);
1281         }
1282
1283         if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
1284                 stmmac_enable_eee_mode(priv);
1285                 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
1286         }
1287         spin_unlock(&priv->tx_lock);
1288 }
1289
1290 static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv)
1291 {
1292         priv->hw->dma->enable_dma_irq(priv->ioaddr);
1293 }
1294
1295 static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv)
1296 {
1297         priv->hw->dma->disable_dma_irq(priv->ioaddr);
1298 }
1299
1300 /**
1301  * stmmac_tx_err: irq tx error mng function
1302  * @priv: driver private structure
1303  * Description: it cleans the descriptors and restarts the transmission
1304  * in case of errors.
1305  */
1306 static void stmmac_tx_err(struct stmmac_priv *priv)
1307 {
1308         int i;
1309         int txsize = priv->dma_tx_size;
1310         netif_stop_queue(priv->dev);
1311
1312         priv->hw->dma->stop_tx(priv->ioaddr);
1313         dma_free_tx_skbufs(priv);
1314         for (i = 0; i < txsize; i++)
1315                 if (priv->extend_desc)
1316                         priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
1317                                                      priv->mode,
1318                                                      (i == txsize - 1));
1319                 else
1320                         priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
1321                                                      priv->mode,
1322                                                      (i == txsize - 1));
1323         priv->dirty_tx = 0;
1324         priv->cur_tx = 0;
1325         priv->hw->dma->start_tx(priv->ioaddr);
1326
1327         priv->dev->stats.tx_errors++;
1328         netif_wake_queue(priv->dev);
1329 }
1330
1331 /**
1332  * stmmac_dma_interrupt: DMA ISR
1333  * @priv: driver private structure
1334  * Description: this is the DMA ISR. It is called by the main ISR.
1335  * It calls the dwmac dma routine to understand which type of interrupt
1336  * happened. In case of there is a Normal interrupt and either TX or RX
1337  * interrupt happened so the NAPI is scheduled.
1338  */
1339 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
1340 {
1341         int status;
1342
1343         status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats);
1344         if (likely((status & handle_rx)) || (status & handle_tx)) {
1345                 if (likely(napi_schedule_prep(&priv->napi))) {
1346                         stmmac_disable_dma_irq(priv);
1347                         __napi_schedule(&priv->napi);
1348                 }
1349         }
1350         if (unlikely(status & tx_hard_error_bump_tc)) {
1351                 /* Try to bump up the dma threshold on this failure */
1352                 if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) {
1353                         tc += 64;
1354                         priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
1355                         priv->xstats.threshold = tc;
1356                 }
1357         } else if (unlikely(status == tx_hard_error))
1358                 stmmac_tx_err(priv);
1359 }
1360
1361 /**
1362  * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
1363  * @priv: driver private structure
1364  * Description: this masks the MMC irq, in fact, the counters are managed in SW.
1365  */
1366 static void stmmac_mmc_setup(struct stmmac_priv *priv)
1367 {
1368         unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
1369             MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
1370
1371         dwmac_mmc_intr_all_mask(priv->ioaddr);
1372
1373         if (priv->dma_cap.rmon) {
1374                 dwmac_mmc_ctrl(priv->ioaddr, mode);
1375                 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
1376         } else
1377                 pr_info(" No MAC Management Counters available\n");
1378 }
1379
1380 static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv)
1381 {
1382         u32 hwid = priv->hw->synopsys_uid;
1383
1384         /* Check Synopsys Id (not available on old chips) */
1385         if (likely(hwid)) {
1386                 u32 uid = ((hwid & 0x0000ff00) >> 8);
1387                 u32 synid = (hwid & 0x000000ff);
1388
1389                 pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n",
1390                         uid, synid);
1391
1392                 return synid;
1393         }
1394         return 0;
1395 }
1396
1397 /**
1398  * stmmac_selec_desc_mode: to select among: normal/alternate/extend descriptors
1399  * @priv: driver private structure
1400  * Description: select the Enhanced/Alternate or Normal descriptors.
1401  * In case of Enhanced/Alternate, it looks at the extended descriptors are
1402  * supported by the HW cap. register.
1403  */
1404 static void stmmac_selec_desc_mode(struct stmmac_priv *priv)
1405 {
1406         if (priv->plat->enh_desc) {
1407                 pr_info(" Enhanced/Alternate descriptors\n");
1408
1409                 /* GMAC older than 3.50 has no extended descriptors */
1410                 if (priv->synopsys_id >= DWMAC_CORE_3_50) {
1411                         pr_info("\tEnabled extended descriptors\n");
1412                         priv->extend_desc = 1;
1413                 } else
1414                         pr_warn("Extended descriptors not supported\n");
1415
1416                 priv->hw->desc = &enh_desc_ops;
1417         } else {
1418                 pr_info(" Normal descriptors\n");
1419                 priv->hw->desc = &ndesc_ops;
1420         }
1421 }
1422
1423 /**
1424  * stmmac_get_hw_features: get MAC capabilities from the HW cap. register.
1425  * @priv: driver private structure
1426  * Description:
1427  *  new GMAC chip generations have a new register to indicate the
1428  *  presence of the optional feature/functions.
1429  *  This can be also used to override the value passed through the
1430  *  platform and necessary for old MAC10/100 and GMAC chips.
1431  */
1432 static int stmmac_get_hw_features(struct stmmac_priv *priv)
1433 {
1434         u32 hw_cap = 0;
1435
1436         if (priv->hw->dma->get_hw_feature) {
1437                 hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr);
1438
1439                 priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL);
1440                 priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1;
1441                 priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2;
1442                 priv->dma_cap.hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4;
1443                 priv->dma_cap.multi_addr = (hw_cap & DMA_HW_FEAT_ADDMAC) >> 5;
1444                 priv->dma_cap.pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6;
1445                 priv->dma_cap.sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8;
1446                 priv->dma_cap.pmt_remote_wake_up =
1447                     (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9;
1448                 priv->dma_cap.pmt_magic_frame =
1449                     (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10;
1450                 /* MMC */
1451                 priv->dma_cap.rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11;
1452                 /* IEEE 1588-2002 */
1453                 priv->dma_cap.time_stamp =
1454                     (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12;
1455                 /* IEEE 1588-2008 */
1456                 priv->dma_cap.atime_stamp =
1457                     (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13;
1458                 /* 802.3az - Energy-Efficient Ethernet (EEE) */
1459                 priv->dma_cap.eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14;
1460                 priv->dma_cap.av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15;
1461                 /* TX and RX csum */
1462                 priv->dma_cap.tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16;
1463                 priv->dma_cap.rx_coe_type1 =
1464                     (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17;
1465                 priv->dma_cap.rx_coe_type2 =
1466                     (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18;
1467                 priv->dma_cap.rxfifo_over_2048 =
1468                     (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19;
1469                 /* TX and RX number of channels */
1470                 priv->dma_cap.number_rx_channel =
1471                     (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20;
1472                 priv->dma_cap.number_tx_channel =
1473                     (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22;
1474                 /* Alternate (enhanced) DESC mode */
1475                 priv->dma_cap.enh_desc = (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24;
1476         }
1477
1478         return hw_cap;
1479 }
1480
1481 /**
1482  * stmmac_check_ether_addr: check if the MAC addr is valid
1483  * @priv: driver private structure
1484  * Description:
1485  * it is to verify if the MAC address is valid, in case of failures it
1486  * generates a random MAC address
1487  */
1488 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
1489 {
1490         if (!is_valid_ether_addr(priv->dev->dev_addr)) {
1491                 priv->hw->mac->get_umac_addr((void __iomem *)
1492                                              priv->dev->base_addr,
1493                                              priv->dev->dev_addr, 0);
1494                 if (!is_valid_ether_addr(priv->dev->dev_addr))
1495                         eth_hw_addr_random(priv->dev);
1496         }
1497         pr_warn("%s: device MAC address %pM\n", priv->dev->name,
1498                 priv->dev->dev_addr);
1499 }
1500
1501 /**
1502  * stmmac_init_dma_engine: DMA init.
1503  * @priv: driver private structure
1504  * Description:
1505  * It inits the DMA invoking the specific MAC/GMAC callback.
1506  * Some DMA parameters can be passed from the platform;
1507  * in case of these are not passed a default is kept for the MAC or GMAC.
1508  */
1509 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
1510 {
1511         int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, burst_len = 0;
1512         int mixed_burst = 0;
1513         int atds = 0;
1514
1515         if (priv->plat->dma_cfg) {
1516                 pbl = priv->plat->dma_cfg->pbl;
1517                 fixed_burst = priv->plat->dma_cfg->fixed_burst;
1518                 mixed_burst = priv->plat->dma_cfg->mixed_burst;
1519                 burst_len = priv->plat->dma_cfg->burst_len;
1520         }
1521
1522         if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
1523                 atds = 1;
1524
1525         return priv->hw->dma->init(priv->ioaddr, pbl, fixed_burst, mixed_burst,
1526                                    burst_len, priv->dma_tx_phy,
1527                                    priv->dma_rx_phy, atds);
1528 }
1529
1530 /**
1531  * stmmac_tx_timer: mitigation sw timer for tx.
1532  * @data: data pointer
1533  * Description:
1534  * This is the timer handler to directly invoke the stmmac_tx_clean.
1535  */
1536 static void stmmac_tx_timer(unsigned long data)
1537 {
1538         struct stmmac_priv *priv = (struct stmmac_priv *)data;
1539
1540         stmmac_tx_clean(priv);
1541 }
1542
1543 /**
1544  * stmmac_init_tx_coalesce: init tx mitigation options.
1545  * @priv: driver private structure
1546  * Description:
1547  * This inits the transmit coalesce parameters: i.e. timer rate,
1548  * timer handler and default threshold used for enabling the
1549  * interrupt on completion bit.
1550  */
1551 static void stmmac_init_tx_coalesce(struct stmmac_priv *priv)
1552 {
1553         priv->tx_coal_frames = STMMAC_TX_FRAMES;
1554         priv->tx_coal_timer = STMMAC_COAL_TX_TIMER;
1555         init_timer(&priv->txtimer);
1556         priv->txtimer.expires = STMMAC_COAL_TIMER(priv->tx_coal_timer);
1557         priv->txtimer.data = (unsigned long)priv;
1558         priv->txtimer.function = stmmac_tx_timer;
1559         add_timer(&priv->txtimer);
1560 }
1561
1562 /**
1563  *  stmmac_open - open entry point of the driver
1564  *  @dev : pointer to the device structure.
1565  *  Description:
1566  *  This function is the open entry point of the driver.
1567  *  Return value:
1568  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1569  *  file on failure.
1570  */
1571 static int stmmac_open(struct net_device *dev)
1572 {
1573         struct stmmac_priv *priv = netdev_priv(dev);
1574         int ret;
1575
1576         clk_prepare_enable(priv->stmmac_clk);
1577
1578         if (priv->rk_pdata->gmac_io_init) {
1579                 priv->rk_pdata->gmac_io_init(priv->device);
1580         }
1581
1582         stmmac_check_ether_addr(priv);
1583
1584         if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
1585             priv->pcs != STMMAC_PCS_RTBI) {
1586                 ret = stmmac_init_phy(dev);
1587                 if (ret) {
1588                         pr_err("%s: Cannot attach to PHY (error: %d)\n",
1589                                __func__, ret);
1590                         goto open_error;
1591                 }
1592         }
1593
1594         /* Create and initialize the TX/RX descriptors chains. */
1595         priv->dma_tx_size = STMMAC_ALIGN(dma_txsize);
1596         priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize);
1597         priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
1598         init_dma_desc_rings(dev);
1599
1600         /* DMA initialization and SW reset */
1601         ret = stmmac_init_dma_engine(priv);
1602         if (ret < 0) {
1603                 pr_err("%s: DMA initialization failed\n", __func__);
1604                 goto open_error;
1605         }
1606
1607         /* Copy the MAC addr into the HW  */
1608         priv->hw->mac->set_umac_addr(priv->ioaddr, dev->dev_addr, 0);
1609
1610         /* If required, perform hw setup of the bus. */
1611         if (priv->plat->bus_setup)
1612                 priv->plat->bus_setup(priv->ioaddr);
1613
1614         /* Initialize the MAC Core */
1615         priv->hw->mac->core_init(priv->ioaddr);
1616
1617         /* Request the IRQ lines */
1618         ret = request_irq(dev->irq, stmmac_interrupt,
1619                           IRQF_SHARED, dev->name, dev);
1620         if (unlikely(ret < 0)) {
1621                 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
1622                        __func__, dev->irq, ret);
1623                 goto open_error;
1624         }
1625
1626         /* Request the Wake IRQ in case of another line is used for WoL */
1627         if (priv->wol_irq != dev->irq) {
1628                 ret = request_irq(priv->wol_irq, stmmac_interrupt,
1629                                   IRQF_SHARED, dev->name, dev);
1630                 if (unlikely(ret < 0)) {
1631                         pr_err("%s: ERROR: allocating the WoL IRQ %d (%d)\n",
1632                                __func__, priv->wol_irq, ret);
1633                         goto open_error_wolirq;
1634                 }
1635         }
1636
1637         /* Request the IRQ lines */
1638         if (priv->lpi_irq != -ENXIO) {
1639                 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
1640                                   dev->name, dev);
1641                 if (unlikely(ret < 0)) {
1642                         pr_err("%s: ERROR: allocating the LPI IRQ %d (%d)\n",
1643                                __func__, priv->lpi_irq, ret);
1644                         goto open_error_lpiirq;
1645                 }
1646         }
1647
1648         /* Enable the MAC Rx/Tx */
1649         stmmac_set_mac(priv->ioaddr, true);
1650
1651         /* Set the HW DMA mode and the COE */
1652         stmmac_dma_operation_mode(priv);
1653
1654         /* Extra statistics */
1655         memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
1656         priv->xstats.threshold = tc;
1657
1658         stmmac_mmc_setup(priv);
1659
1660         ret = stmmac_init_ptp(priv);
1661         if (ret)
1662                 pr_warn("%s: failed PTP initialisation\n", __func__);
1663
1664 #ifdef CONFIG_GMAC_DEBUG_FS
1665         ret = stmmac_init_fs(dev);
1666         if (ret < 0)
1667                 pr_warn("%s: failed debugFS registration\n", __func__);
1668 #endif
1669         /* Start the ball rolling... */
1670         DBG(probe, DEBUG, "%s: DMA RX/TX processes started...\n", dev->name);
1671         priv->hw->dma->start_tx(priv->ioaddr);
1672         priv->hw->dma->start_rx(priv->ioaddr);
1673
1674         /* Dump DMA/MAC registers */
1675         if (netif_msg_hw(priv)) {
1676                 priv->hw->mac->dump_regs(priv->ioaddr);
1677                 priv->hw->dma->dump_regs(priv->ioaddr);
1678         }
1679
1680         if (priv->phydev)
1681                 phy_start(priv->phydev);
1682
1683         priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS;
1684
1685         priv->eee_enabled = stmmac_eee_init(priv);
1686
1687         stmmac_init_tx_coalesce(priv);
1688
1689         if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) {
1690                 priv->rx_riwt = MAX_DMA_RIWT;
1691                 priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT);
1692         }
1693
1694         if (priv->pcs && priv->hw->mac->ctrl_ane)
1695                 priv->hw->mac->ctrl_ane(priv->ioaddr, 0);
1696
1697         napi_enable(&priv->napi);
1698         netif_start_queue(dev);
1699
1700         return 0;
1701
1702 open_error_lpiirq:
1703         if (priv->wol_irq != dev->irq)
1704                 free_irq(priv->wol_irq, dev);
1705
1706 open_error_wolirq:
1707         free_irq(dev->irq, dev);
1708
1709 open_error:
1710         if (priv->phydev)
1711                 phy_disconnect(priv->phydev);
1712
1713         clk_disable_unprepare(priv->stmmac_clk);
1714
1715         return ret;
1716 }
1717
1718 /**
1719  *  stmmac_release - close entry point of the driver
1720  *  @dev : device pointer.
1721  *  Description:
1722  *  This is the stop entry point of the driver.
1723  */
1724 static int stmmac_release(struct net_device *dev)
1725 {
1726         struct stmmac_priv *priv = netdev_priv(dev);
1727
1728         if (priv->eee_enabled)
1729                 del_timer_sync(&priv->eee_ctrl_timer);
1730
1731         /* Stop and disconnect the PHY */
1732         if (priv->phydev) {
1733                 phy_stop(priv->phydev);
1734                 phy_disconnect(priv->phydev);
1735                 priv->phydev = NULL;
1736         }
1737
1738         netif_stop_queue(dev);
1739
1740         napi_disable(&priv->napi);
1741
1742         del_timer_sync(&priv->txtimer);
1743
1744         /* Free the IRQ lines */
1745         free_irq(dev->irq, dev);
1746         if (priv->wol_irq != dev->irq)
1747                 free_irq(priv->wol_irq, dev);
1748         if (priv->lpi_irq != -ENXIO)
1749                 free_irq(priv->lpi_irq, dev);
1750
1751         /* Stop TX/RX DMA and clear the descriptors */
1752         priv->hw->dma->stop_tx(priv->ioaddr);
1753         priv->hw->dma->stop_rx(priv->ioaddr);
1754
1755         /* Release and free the Rx/Tx resources */
1756         free_dma_desc_resources(priv);
1757
1758         /* Disable the MAC Rx/Tx */
1759         stmmac_set_mac(priv->ioaddr, false);
1760
1761         netif_carrier_off(dev);
1762
1763 #ifdef CONFIG_GMAC_DEBUG_FS
1764         stmmac_exit_fs();
1765 #endif
1766         clk_disable_unprepare(priv->stmmac_clk);
1767
1768         stmmac_release_ptp(priv);
1769
1770         if (priv->rk_pdata->gmac_io_deinit) {
1771                 priv->rk_pdata->gmac_io_deinit(priv->device);
1772         }
1773
1774         return 0;
1775 }
1776
1777 /**
1778  *  stmmac_xmit: Tx entry point of the driver
1779  *  @skb : the socket buffer
1780  *  @dev : device pointer
1781  *  Description : this is the tx entry point of the driver.
1782  *  It programs the chain or the ring and supports oversized frames
1783  *  and SG feature.
1784  */
1785 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
1786 {
1787         struct stmmac_priv *priv = netdev_priv(dev);
1788         unsigned int txsize = priv->dma_tx_size;
1789         unsigned int entry;
1790         int i, csum_insertion = 0, is_jumbo = 0;
1791         int nfrags = skb_shinfo(skb)->nr_frags;
1792         struct dma_desc *desc, *first;
1793         unsigned int nopaged_len = skb_headlen(skb);
1794
1795         if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) {
1796                 if (!netif_queue_stopped(dev)) {
1797                         netif_stop_queue(dev);
1798                         /* This is a hard error, log it. */
1799                         pr_err("%s: Tx Ring full when queue awake\n", __func__);
1800                 }
1801                 return NETDEV_TX_BUSY;
1802         }
1803
1804         spin_lock(&priv->tx_lock);
1805
1806         if (priv->tx_path_in_lpi_mode)
1807                 stmmac_disable_eee_mode(priv);
1808
1809         entry = priv->cur_tx % txsize;
1810
1811 #ifdef STMMAC_XMIT_DEBUG
1812         if ((skb->len > ETH_FRAME_LEN) || nfrags)
1813                 pr_debug("%s: [entry %d]: skb addr %p len: %d nopagedlen: %d\n"
1814                          "\tn_frags: %d - ip_summed: %d - %s gso\n"
1815                          "\ttx_count_frames %d\n", __func__, entry,
1816                          skb, skb->len, nopaged_len, nfrags, skb->ip_summed,
1817                          !skb_is_gso(skb) ? "isn't" : "is",
1818                          priv->tx_count_frames);
1819 #endif
1820
1821         csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
1822
1823         if (priv->extend_desc)
1824                 desc = (struct dma_desc *)(priv->dma_etx + entry);
1825         else
1826                 desc = priv->dma_tx + entry;
1827
1828         first = desc;
1829
1830 #ifdef STMMAC_XMIT_DEBUG
1831         if ((nfrags > 0) || (skb->len > ETH_FRAME_LEN))
1832                 pr_debug("\tskb len: %d, nopaged_len: %d,\n"
1833                          "\t\tn_frags: %d, ip_summed: %d\n",
1834                          skb->len, nopaged_len, nfrags, skb->ip_summed);
1835 #endif
1836         priv->tx_skbuff[entry] = skb;
1837
1838         /* To program the descriptors according to the size of the frame */
1839         if (priv->mode == STMMAC_RING_MODE) {
1840                 is_jumbo = priv->hw->ring->is_jumbo_frm(skb->len,
1841                                                         priv->plat->enh_desc);
1842                 if (unlikely(is_jumbo))
1843                         entry = priv->hw->ring->jumbo_frm(priv, skb,
1844                                                           csum_insertion);
1845         } else {
1846                 is_jumbo = priv->hw->chain->is_jumbo_frm(skb->len,
1847                                                          priv->plat->enh_desc);
1848                 if (unlikely(is_jumbo))
1849                         entry = priv->hw->chain->jumbo_frm(priv, skb,
1850                                                            csum_insertion);
1851         }
1852         if (likely(!is_jumbo)) {
1853                 desc->des2 = dma_map_single(priv->device, skb->data,
1854                                             nopaged_len, DMA_TO_DEVICE);
1855                 priv->tx_skbuff_dma[entry] = desc->des2;
1856                 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len,
1857                                                 csum_insertion, priv->mode);
1858         } else
1859                 desc = first;
1860
1861         for (i = 0; i < nfrags; i++) {
1862                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1863                 int len = skb_frag_size(frag);
1864
1865                 entry = (++priv->cur_tx) % txsize;
1866                 if (priv->extend_desc)
1867                         desc = (struct dma_desc *)(priv->dma_etx + entry);
1868                 else
1869                         desc = priv->dma_tx + entry;
1870
1871                 TX_DBG("\t[entry %d] segment len: %d\n", entry, len);
1872                 desc->des2 = skb_frag_dma_map(priv->device, frag, 0, len,
1873                                               DMA_TO_DEVICE);
1874                 priv->tx_skbuff_dma[entry] = desc->des2;
1875                 priv->tx_skbuff[entry] = NULL;
1876                 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion,
1877                                                 priv->mode);
1878                 wmb();
1879                 priv->hw->desc->set_tx_owner(desc);
1880                 wmb();
1881         }
1882
1883         /* Finalize the latest segment. */
1884         priv->hw->desc->close_tx_desc(desc);
1885
1886         wmb();
1887         /* According to the coalesce parameter the IC bit for the latest
1888          * segment could be reset and the timer re-started to invoke the
1889          * stmmac_tx function. This approach takes care about the fragments.
1890          */
1891         priv->tx_count_frames += nfrags + 1;
1892         if (priv->tx_coal_frames > priv->tx_count_frames) {
1893                 priv->hw->desc->clear_tx_ic(desc);
1894                 priv->xstats.tx_reset_ic_bit++;
1895                 TX_DBG("\t[entry %d]: tx_count_frames %d\n", entry,
1896                        priv->tx_count_frames);
1897                 mod_timer(&priv->txtimer,
1898                           STMMAC_COAL_TIMER(priv->tx_coal_timer));
1899         } else
1900                 priv->tx_count_frames = 0;
1901
1902         /* To avoid raise condition */
1903         priv->hw->desc->set_tx_owner(first);
1904         wmb();
1905
1906         priv->cur_tx++;
1907
1908 #ifdef STMMAC_XMIT_DEBUG
1909         if (netif_msg_pktdata(priv)) {
1910                 pr_info("%s: curr %d dirty=%d entry=%d, first=%p, nfrags=%d",
1911                         __func__, (priv->cur_tx % txsize),
1912                         (priv->dirty_tx % txsize), entry, first, nfrags);
1913                 if (priv->extend_desc)
1914                         stmmac_display_ring((void *)priv->dma_etx, txsize, 1);
1915                 else
1916                         stmmac_display_ring((void *)priv->dma_tx, txsize, 0);
1917
1918                 pr_info(">>> frame to be transmitted: ");
1919                 print_pkt(skb->data, skb->len);
1920         }
1921 #endif
1922         if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
1923                 TX_DBG("%s: stop transmitted packets\n", __func__);
1924                 netif_stop_queue(dev);
1925         }
1926
1927         dev->stats.tx_bytes += skb->len;
1928
1929         if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
1930                      priv->hwts_tx_en)) {
1931                 /* declare that device is doing timestamping */
1932                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1933                 priv->hw->desc->enable_tx_timestamp(first);
1934         }
1935
1936         if (!priv->hwts_tx_en)
1937                 skb_tx_timestamp(skb);
1938
1939         priv->hw->dma->enable_dma_transmission(priv->ioaddr);
1940
1941         spin_unlock(&priv->tx_lock);
1942
1943         return NETDEV_TX_OK;
1944 }
1945
1946 /**
1947  * stmmac_rx_refill: refill used skb preallocated buffers
1948  * @priv: driver private structure
1949  * Description : this is to reallocate the skb for the reception process
1950  * that is based on zero-copy.
1951  */
1952 static inline void stmmac_rx_refill(struct stmmac_priv *priv)
1953 {
1954         unsigned int rxsize = priv->dma_rx_size;
1955         int bfsize = priv->dma_buf_sz;
1956
1957         for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) {
1958                 unsigned int entry = priv->dirty_rx % rxsize;
1959                 struct dma_desc *p;
1960
1961                 if (priv->extend_desc)
1962                         p = (struct dma_desc *)(priv->dma_erx + entry);
1963                 else
1964                         p = priv->dma_rx + entry;
1965
1966                 if (likely(priv->rx_skbuff[entry] == NULL)) {
1967                         struct sk_buff *skb;
1968
1969                         skb = netdev_alloc_skb_ip_align(priv->dev, bfsize);
1970
1971                         if (unlikely(skb == NULL))
1972                                 break;
1973
1974                         priv->rx_skbuff[entry] = skb;
1975                         priv->rx_skbuff_dma[entry] =
1976                             dma_map_single(priv->device, skb->data, bfsize,
1977                                            DMA_FROM_DEVICE);
1978
1979                         p->des2 = priv->rx_skbuff_dma[entry];
1980
1981                         priv->hw->ring->refill_desc3(priv, p);
1982
1983                         RX_DBG(KERN_INFO "\trefill entry #%d\n", entry);
1984                 }
1985                 wmb();
1986                 priv->hw->desc->set_rx_owner(p);
1987                 wmb();
1988         }
1989 }
1990
1991 /**
1992  * stmmac_rx_refill: refill used skb preallocated buffers
1993  * @priv: driver private structure
1994  * @limit: napi bugget.
1995  * Description :  this the function called by the napi poll method.
1996  * It gets all the frames inside the ring.
1997  */
1998 static int stmmac_rx(struct stmmac_priv *priv, int limit)
1999 {
2000         unsigned int rxsize = priv->dma_rx_size;
2001         unsigned int entry = priv->cur_rx % rxsize;
2002         unsigned int next_entry;
2003         unsigned int count = 0;
2004         int coe = priv->plat->rx_coe;
2005
2006 #ifdef STMMAC_RX_DEBUG
2007         if (netif_msg_hw(priv)) {
2008                 pr_debug(">>> stmmac_rx: descriptor ring:\n");
2009                 if (priv->extend_desc)
2010                         stmmac_display_ring((void *)priv->dma_erx, rxsize, 1);
2011                 else
2012                         stmmac_display_ring((void *)priv->dma_rx, rxsize, 0);
2013         }
2014 #endif
2015         while (count < limit) {
2016                 int status;
2017                 struct dma_desc *p;
2018
2019                 if (priv->extend_desc)
2020                         p = (struct dma_desc *)(priv->dma_erx + entry);
2021                 else
2022                         p = priv->dma_rx + entry;
2023
2024                 if (priv->hw->desc->get_rx_owner(p))
2025                         break;
2026
2027                 count++;
2028
2029                 next_entry = (++priv->cur_rx) % rxsize;
2030                 if (priv->extend_desc)
2031                         prefetch(priv->dma_erx + next_entry);
2032                 else
2033                         prefetch(priv->dma_rx + next_entry);
2034
2035                 /* read the status of the incoming frame */
2036                 status = priv->hw->desc->rx_status(&priv->dev->stats,
2037                                                    &priv->xstats, p);
2038                 if ((priv->extend_desc) && (priv->hw->desc->rx_extended_status))
2039                         priv->hw->desc->rx_extended_status(&priv->dev->stats,
2040                                                            &priv->xstats,
2041                                                            priv->dma_erx +
2042                                                            entry);
2043                 if (unlikely(status == discard_frame)) {
2044                         priv->dev->stats.rx_errors++;
2045                         if (priv->hwts_rx_en && !priv->extend_desc) {
2046                                 /* DESC2 & DESC3 will be overwitten by device
2047                                  * with timestamp value, hence reinitialize
2048                                  * them in stmmac_rx_refill() function so that
2049                                  * device can reuse it.
2050                                  */
2051                                 priv->rx_skbuff[entry] = NULL;
2052                                 dma_unmap_single(priv->device,
2053                                                  priv->rx_skbuff_dma[entry],
2054                                                  priv->dma_buf_sz,
2055                                                  DMA_FROM_DEVICE);
2056                         }
2057                 } else {
2058                         struct sk_buff *skb;
2059                         int frame_len;
2060
2061                         frame_len = priv->hw->desc->get_rx_frame_len(p, coe);
2062
2063                         /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
2064                          * Type frames (LLC/LLC-SNAP)
2065                          */
2066                         if (unlikely(status != llc_snap))
2067                                 frame_len -= ETH_FCS_LEN;
2068 #ifdef STMMAC_RX_DEBUG
2069                         if (frame_len > ETH_FRAME_LEN)
2070                                 pr_debug("\tRX frame size %d, COE status: %d\n",
2071                                          frame_len, status);
2072
2073                         if (netif_msg_hw(priv))
2074                                 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n",
2075                                          p, entry, p->des2);
2076 #endif
2077                         skb = priv->rx_skbuff[entry];
2078                         if (unlikely(!skb)) {
2079                                 pr_err("%s: Inconsistent Rx descriptor chain\n",
2080                                        priv->dev->name);
2081                                 priv->dev->stats.rx_dropped++;
2082                                 break;
2083                         }
2084                         prefetch(skb->data - NET_IP_ALIGN);
2085                         priv->rx_skbuff[entry] = NULL;
2086
2087                         stmmac_get_rx_hwtstamp(priv, entry, skb);
2088
2089                         skb_put(skb, frame_len);
2090                         dma_unmap_single(priv->device,
2091                                          priv->rx_skbuff_dma[entry],
2092                                          priv->dma_buf_sz, DMA_FROM_DEVICE);
2093 #ifdef STMMAC_RX_DEBUG
2094                         if (netif_msg_pktdata(priv)) {
2095                                 pr_info(" frame received (%dbytes)", frame_len);
2096                                 print_pkt(skb->data, frame_len);
2097                         }
2098 #endif
2099                         skb->protocol = eth_type_trans(skb, priv->dev);
2100
2101                         if (unlikely(!coe))
2102                                 skb_checksum_none_assert(skb);
2103                         else
2104                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2105
2106                         napi_gro_receive(&priv->napi, skb);
2107
2108                         priv->dev->stats.rx_packets++;
2109                         priv->dev->stats.rx_bytes += frame_len;
2110                 }
2111                 entry = next_entry;
2112         }
2113
2114         stmmac_rx_refill(priv);
2115
2116         priv->xstats.rx_pkt_n += count;
2117
2118         return count;
2119 }
2120
2121 /**
2122  *  stmmac_poll - stmmac poll method (NAPI)
2123  *  @napi : pointer to the napi structure.
2124  *  @budget : maximum number of packets that the current CPU can receive from
2125  *            all interfaces.
2126  *  Description :
2127  *  To look at the incoming frames and clear the tx resources.
2128  */
2129 static int stmmac_poll(struct napi_struct *napi, int budget)
2130 {
2131         struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi);
2132         int work_done = 0;
2133
2134         priv->xstats.napi_poll++;
2135         stmmac_tx_clean(priv);
2136
2137         work_done = stmmac_rx(priv, budget);
2138         if (work_done < budget) {
2139                 napi_complete(napi);
2140                 stmmac_enable_dma_irq(priv);
2141         }
2142         return work_done;
2143 }
2144
2145 /**
2146  *  stmmac_tx_timeout
2147  *  @dev : Pointer to net device structure
2148  *  Description: this function is called when a packet transmission fails to
2149  *   complete within a reasonable time. The driver will mark the error in the
2150  *   netdev structure and arrange for the device to be reset to a sane state
2151  *   in order to transmit a new packet.
2152  */
2153 static void stmmac_tx_timeout(struct net_device *dev)
2154 {
2155         struct stmmac_priv *priv = netdev_priv(dev);
2156
2157         /* Clear Tx resources and restart transmitting again */
2158         stmmac_tx_err(priv);
2159 }
2160
2161 /* Configuration changes (passed on by ifconfig) */
2162 static int stmmac_config(struct net_device *dev, struct ifmap *map)
2163 {
2164         if (dev->flags & IFF_UP)        /* can't act on a running interface */
2165                 return -EBUSY;
2166
2167         /* Don't allow changing the I/O address */
2168         if (map->base_addr != dev->base_addr) {
2169                 pr_warn("%s: can't change I/O address\n", dev->name);
2170                 return -EOPNOTSUPP;
2171         }
2172
2173         /* Don't allow changing the IRQ */
2174         if (map->irq != dev->irq) {
2175                 pr_warn("%s: not change IRQ number %d\n", dev->name, dev->irq);
2176                 return -EOPNOTSUPP;
2177         }
2178
2179         return 0;
2180 }
2181
2182 /**
2183  *  stmmac_set_rx_mode - entry point for multicast addressing
2184  *  @dev : pointer to the device structure
2185  *  Description:
2186  *  This function is a driver entry point which gets called by the kernel
2187  *  whenever multicast addresses must be enabled/disabled.
2188  *  Return value:
2189  *  void.
2190  */
2191 static void stmmac_set_rx_mode(struct net_device *dev)
2192 {
2193         struct stmmac_priv *priv = netdev_priv(dev);
2194
2195         spin_lock(&priv->lock);
2196         priv->hw->mac->set_filter(dev, priv->synopsys_id);
2197         spin_unlock(&priv->lock);
2198 }
2199
2200 /**
2201  *  stmmac_change_mtu - entry point to change MTU size for the device.
2202  *  @dev : device pointer.
2203  *  @new_mtu : the new MTU size for the device.
2204  *  Description: the Maximum Transfer Unit (MTU) is used by the network layer
2205  *  to drive packet transmission. Ethernet has an MTU of 1500 octets
2206  *  (ETH_DATA_LEN). This value can be changed with ifconfig.
2207  *  Return value:
2208  *  0 on success and an appropriate (-)ve integer as defined in errno.h
2209  *  file on failure.
2210  */
2211 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
2212 {
2213         struct stmmac_priv *priv = netdev_priv(dev);
2214         int max_mtu;
2215
2216         if (netif_running(dev)) {
2217                 pr_err("%s: must be stopped to change its MTU\n", dev->name);
2218                 return -EBUSY;
2219         }
2220
2221         if (priv->plat->enh_desc)
2222                 max_mtu = JUMBO_LEN;
2223         else
2224                 max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
2225
2226         if ((new_mtu < 46) || (new_mtu > max_mtu)) {
2227                 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu);
2228                 return -EINVAL;
2229         }
2230
2231         dev->mtu = new_mtu;
2232         netdev_update_features(dev);
2233
2234         return 0;
2235 }
2236
2237 static netdev_features_t stmmac_fix_features(struct net_device *dev,
2238                                              netdev_features_t features)
2239 {
2240         struct stmmac_priv *priv = netdev_priv(dev);
2241
2242         if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
2243                 features &= ~NETIF_F_RXCSUM;
2244         else if (priv->plat->rx_coe == STMMAC_RX_COE_TYPE1)
2245                 features &= ~NETIF_F_IPV6_CSUM;
2246         if (!priv->plat->tx_coe)
2247                 features &= ~NETIF_F_ALL_CSUM;
2248
2249         /* Some GMAC devices have a bugged Jumbo frame support that
2250          * needs to have the Tx COE disabled for oversized frames
2251          * (due to limited buffer sizes). In this case we disable
2252          * the TX csum insertionin the TDES and not use SF.
2253          */
2254         if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
2255                 features &= ~NETIF_F_ALL_CSUM;
2256
2257         return features;
2258 }
2259
2260 /**
2261  *  stmmac_interrupt - main ISR
2262  *  @irq: interrupt number.
2263  *  @dev_id: to pass the net device pointer.
2264  *  Description: this is the main driver interrupt service routine.
2265  *  It calls the DMA ISR and also the core ISR to manage PMT, MMC, LPI
2266  *  interrupts.
2267  */
2268 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
2269 {
2270         struct net_device *dev = (struct net_device *)dev_id;
2271         struct stmmac_priv *priv = netdev_priv(dev);
2272
2273         if (unlikely(!dev)) {
2274                 pr_err("%s: invalid dev pointer\n", __func__);
2275                 return IRQ_NONE;
2276         }
2277
2278         /* To handle GMAC own interrupts */
2279         if (priv->plat->has_gmac) {
2280                 int status = priv->hw->mac->host_irq_status((void __iomem *)
2281                                                             dev->base_addr,
2282                                                             &priv->xstats);
2283                 if (unlikely(status)) {
2284                         /* For LPI we need to save the tx status */
2285                         if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
2286                                 priv->tx_path_in_lpi_mode = true;
2287                         if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
2288                                 priv->tx_path_in_lpi_mode = false;
2289                 }
2290         }
2291
2292         /* To handle DMA interrupts */
2293         stmmac_dma_interrupt(priv);
2294
2295         return IRQ_HANDLED;
2296 }
2297
2298 #ifdef CONFIG_NET_POLL_CONTROLLER
2299 /* Polling receive - used by NETCONSOLE and other diagnostic tools
2300  * to allow network I/O with interrupts disabled.
2301  */
2302 static void stmmac_poll_controller(struct net_device *dev)
2303 {
2304         disable_irq(dev->irq);
2305         stmmac_interrupt(dev->irq, dev);
2306         enable_irq(dev->irq);
2307 }
2308 #endif
2309
2310 /**
2311  *  stmmac_ioctl - Entry point for the Ioctl
2312  *  @dev: Device pointer.
2313  *  @rq: An IOCTL specefic structure, that can contain a pointer to
2314  *  a proprietary structure used to pass information to the driver.
2315  *  @cmd: IOCTL command
2316  *  Description:
2317  *  Currently it supports the phy_mii_ioctl(...) and HW time stamping.
2318  */
2319 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2320 {
2321         struct stmmac_priv *priv = netdev_priv(dev);
2322         int ret = -EOPNOTSUPP;
2323
2324         if (!netif_running(dev))
2325                 return -EINVAL;
2326
2327         switch (cmd) {
2328         case SIOCGMIIPHY:
2329         case SIOCGMIIREG:
2330         case SIOCSMIIREG:
2331                 if (!priv->phydev)
2332                         return -EINVAL;
2333                 ret = phy_mii_ioctl(priv->phydev, rq, cmd);
2334                 break;
2335         case SIOCSHWTSTAMP:
2336                 ret = stmmac_hwtstamp_ioctl(dev, rq);
2337                 break;
2338         default:
2339                 break;
2340         }
2341
2342         return ret;
2343 }
2344
2345 #ifdef CONFIG_GMAC_DEBUG_FS
2346 static struct dentry *stmmac_fs_dir;
2347 static struct dentry *stmmac_rings_status;
2348 static struct dentry *stmmac_dma_cap;
2349
2350 static void sysfs_display_ring(void *head, int size, int extend_desc,
2351                                struct seq_file *seq)
2352 {
2353         int i;
2354         struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
2355         struct dma_desc *p = (struct dma_desc *)head;
2356
2357         for (i = 0; i < size; i++) {
2358                 u64 x;
2359                 if (extend_desc) {
2360                         x = *(u64 *) ep;
2361                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2362                                    i, (unsigned int)virt_to_phys(ep),
2363                                    (unsigned int)x, (unsigned int)(x >> 32),
2364                                    ep->basic.des2, ep->basic.des3);
2365                         ep++;
2366                 } else {
2367                         x = *(u64 *) p;
2368                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2369                                    i, (unsigned int)virt_to_phys(ep),
2370                                    (unsigned int)x, (unsigned int)(x >> 32),
2371                                    p->des2, p->des3);
2372                         p++;
2373                 }
2374                 seq_printf(seq, "\n");
2375         }
2376 }
2377
2378 static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v)
2379 {
2380         struct net_device *dev = seq->private;
2381         struct stmmac_priv *priv = netdev_priv(dev);
2382         unsigned int txsize = priv->dma_tx_size;
2383         unsigned int rxsize = priv->dma_rx_size;
2384
2385         if (priv->extend_desc) {
2386                 seq_printf(seq, "Extended RX descriptor ring:\n");
2387                 sysfs_display_ring((void *)priv->dma_erx, rxsize, 1, seq);
2388                 seq_printf(seq, "Extended TX descriptor ring:\n");
2389                 sysfs_display_ring((void *)priv->dma_etx, txsize, 1, seq);
2390         } else {
2391                 seq_printf(seq, "RX descriptor ring:\n");
2392                 sysfs_display_ring((void *)priv->dma_rx, rxsize, 0, seq);
2393                 seq_printf(seq, "TX descriptor ring:\n");
2394                 sysfs_display_ring((void *)priv->dma_tx, txsize, 0, seq);
2395         }
2396
2397         return 0;
2398 }
2399
2400 static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file)
2401 {
2402         return single_open(file, stmmac_sysfs_ring_read, inode->i_private);
2403 }
2404
2405 static const struct file_operations stmmac_rings_status_fops = {
2406         .owner = THIS_MODULE,
2407         .open = stmmac_sysfs_ring_open,
2408         .read = seq_read,
2409         .llseek = seq_lseek,
2410         .release = single_release,
2411 };
2412
2413 static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v)
2414 {
2415         struct net_device *dev = seq->private;
2416         struct stmmac_priv *priv = netdev_priv(dev);
2417
2418         if (!priv->hw_cap_support) {
2419                 seq_printf(seq, "DMA HW features not supported\n");
2420                 return 0;
2421         }
2422
2423         seq_printf(seq, "==============================\n");
2424         seq_printf(seq, "\tDMA HW features\n");
2425         seq_printf(seq, "==============================\n");
2426
2427         seq_printf(seq, "\t10/100 Mbps %s\n",
2428                    (priv->dma_cap.mbps_10_100) ? "Y" : "N");
2429         seq_printf(seq, "\t1000 Mbps %s\n",
2430                    (priv->dma_cap.mbps_1000) ? "Y" : "N");
2431         seq_printf(seq, "\tHalf duple %s\n",
2432                    (priv->dma_cap.half_duplex) ? "Y" : "N");
2433         seq_printf(seq, "\tHash Filter: %s\n",
2434                    (priv->dma_cap.hash_filter) ? "Y" : "N");
2435         seq_printf(seq, "\tMultiple MAC address registers: %s\n",
2436                    (priv->dma_cap.multi_addr) ? "Y" : "N");
2437         seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n",
2438                    (priv->dma_cap.pcs) ? "Y" : "N");
2439         seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
2440                    (priv->dma_cap.sma_mdio) ? "Y" : "N");
2441         seq_printf(seq, "\tPMT Remote wake up: %s\n",
2442                    (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
2443         seq_printf(seq, "\tPMT Magic Frame: %s\n",
2444                    (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
2445         seq_printf(seq, "\tRMON module: %s\n",
2446                    (priv->dma_cap.rmon) ? "Y" : "N");
2447         seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
2448                    (priv->dma_cap.time_stamp) ? "Y" : "N");
2449         seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n",
2450                    (priv->dma_cap.atime_stamp) ? "Y" : "N");
2451         seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n",
2452                    (priv->dma_cap.eee) ? "Y" : "N");
2453         seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
2454         seq_printf(seq, "\tChecksum Offload in TX: %s\n",
2455                    (priv->dma_cap.tx_coe) ? "Y" : "N");
2456         seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
2457                    (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
2458         seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
2459                    (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
2460         seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
2461                    (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
2462         seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
2463                    priv->dma_cap.number_rx_channel);
2464         seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
2465                    priv->dma_cap.number_tx_channel);
2466         seq_printf(seq, "\tEnhanced descriptors: %s\n",
2467                    (priv->dma_cap.enh_desc) ? "Y" : "N");
2468
2469         return 0;
2470 }
2471
2472 static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file)
2473 {
2474         return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private);
2475 }
2476
2477 static const struct file_operations stmmac_dma_cap_fops = {
2478         .owner = THIS_MODULE,
2479         .open = stmmac_sysfs_dma_cap_open,
2480         .read = seq_read,
2481         .llseek = seq_lseek,
2482         .release = single_release,
2483 };
2484
2485 static int stmmac_init_fs(struct net_device *dev)
2486 {
2487         /* Create debugfs entries */
2488         stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
2489
2490         if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
2491                 pr_err("ERROR %s, debugfs create directory failed\n",
2492                        STMMAC_RESOURCE_NAME);
2493
2494                 return -ENOMEM;
2495         }
2496
2497         /* Entry to report DMA RX/TX rings */
2498         stmmac_rings_status = debugfs_create_file("descriptors_status",
2499                                                   S_IRUGO, stmmac_fs_dir, dev,
2500                                                   &stmmac_rings_status_fops);
2501
2502         if (!stmmac_rings_status || IS_ERR(stmmac_rings_status)) {
2503                 pr_info("ERROR creating stmmac ring debugfs file\n");
2504                 debugfs_remove(stmmac_fs_dir);
2505
2506                 return -ENOMEM;
2507         }
2508
2509         /* Entry to report the DMA HW features */
2510         stmmac_dma_cap = debugfs_create_file("dma_cap", S_IRUGO, stmmac_fs_dir,
2511                                              dev, &stmmac_dma_cap_fops);
2512
2513         if (!stmmac_dma_cap || IS_ERR(stmmac_dma_cap)) {
2514                 pr_info("ERROR creating stmmac MMC debugfs file\n");
2515                 debugfs_remove(stmmac_rings_status);
2516                 debugfs_remove(stmmac_fs_dir);
2517
2518                 return -ENOMEM;
2519         }
2520
2521         return 0;
2522 }
2523
2524 static void stmmac_exit_fs(void)
2525 {
2526         debugfs_remove(stmmac_rings_status);
2527         debugfs_remove(stmmac_dma_cap);
2528         debugfs_remove(stmmac_fs_dir);
2529 }
2530 #endif /* CONFIG_GMAC_DEBUG_FS */
2531
2532 static const struct net_device_ops stmmac_netdev_ops = {
2533         .ndo_open = stmmac_open,
2534         .ndo_start_xmit = stmmac_xmit,
2535         .ndo_stop = stmmac_release,
2536         .ndo_change_mtu = stmmac_change_mtu,
2537         .ndo_fix_features = stmmac_fix_features,
2538         .ndo_set_rx_mode = stmmac_set_rx_mode,
2539         .ndo_tx_timeout = stmmac_tx_timeout,
2540         .ndo_do_ioctl = stmmac_ioctl,
2541         .ndo_set_config = stmmac_config,
2542 #ifdef CONFIG_NET_POLL_CONTROLLER
2543         .ndo_poll_controller = stmmac_poll_controller,
2544 #endif
2545         .ndo_set_mac_address = eth_mac_addr,
2546 };
2547
2548 /**
2549  *  stmmac_hw_init - Init the MAC device
2550  *  @priv: driver private structure
2551  *  Description: this function detects which MAC device
2552  *  (GMAC/MAC10-100) has to attached, checks the HW capability
2553  *  (if supported) and sets the driver's features (for example
2554  *  to use the ring or chaine mode or support the normal/enh
2555  *  descriptor structure).
2556  */
2557 static int stmmac_hw_init(struct stmmac_priv *priv)
2558 {
2559         int ret;
2560         struct mac_device_info *mac;
2561
2562         /* Identify the MAC HW device */
2563         if (priv->plat->has_gmac) {
2564                 priv->dev->priv_flags |= IFF_UNICAST_FLT;
2565                 mac = dwmac1000_setup(priv->ioaddr);
2566         } else {
2567                 mac = dwmac100_setup(priv->ioaddr);
2568         }
2569         if (!mac)
2570                 return -ENOMEM;
2571
2572         priv->hw = mac;
2573
2574         /* Get and dump the chip ID */
2575         priv->synopsys_id = stmmac_get_synopsys_id(priv);
2576
2577         /* To use alternate (extended) or normal descriptor structures */
2578         stmmac_selec_desc_mode(priv);
2579
2580         /* To use the chained or ring mode */
2581         if (chain_mode) {
2582                 priv->hw->chain = &chain_mode_ops;
2583                 pr_info(" Chain mode enabled\n");
2584                 priv->mode = STMMAC_CHAIN_MODE;
2585         } else {
2586                 priv->hw->ring = &ring_mode_ops;
2587                 pr_info(" Ring mode enabled\n");
2588                 priv->mode = STMMAC_RING_MODE;
2589         }
2590
2591         /* Get the HW capability (new GMAC newer than 3.50a) */
2592         priv->hw_cap_support = stmmac_get_hw_features(priv);
2593         if (priv->hw_cap_support) {
2594                 pr_info(" DMA HW capability register supported");
2595
2596                 /* We can override some gmac/dma configuration fields: e.g.
2597                  * enh_desc, tx_coe (e.g. that are passed through the
2598                  * platform) with the values from the HW capability
2599                  * register (if supported).
2600                  */
2601                 priv->plat->enh_desc = priv->dma_cap.enh_desc;
2602                 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
2603
2604                 priv->plat->tx_coe = priv->dma_cap.tx_coe;
2605
2606                 if (priv->dma_cap.rx_coe_type2)
2607                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
2608                 else if (priv->dma_cap.rx_coe_type1)
2609                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
2610
2611         } else
2612                 pr_info(" No HW DMA feature register supported");
2613
2614         ret = priv->hw->mac->rx_ipc(priv->ioaddr);
2615         if (!ret) {
2616                 pr_warn(" RX IPC Checksum Offload not configured.\n");
2617                 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
2618         }
2619
2620         if (priv->plat->rx_coe)
2621                 pr_info(" RX Checksum Offload Engine supported (type %d)\n",
2622                         priv->plat->rx_coe);
2623         if (priv->plat->tx_coe)
2624                 pr_info(" TX Checksum insertion supported\n");
2625
2626         if (priv->plat->pmt) {
2627                 pr_info(" Wake-Up On Lan supported\n");
2628                 device_set_wakeup_capable(priv->device, 1);
2629         }
2630
2631         return 0;
2632 }
2633
2634 /**
2635  * stmmac_dvr_probe
2636  * @device: device pointer
2637  * @plat_dat: platform data pointer
2638  * @addr: iobase memory address
2639  * Description: this is the main probe function used to
2640  * call the alloc_etherdev, allocate the priv structure.
2641  */
2642 struct stmmac_priv *stmmac_dvr_probe(struct device *device,
2643                                      struct plat_stmmacenet_data *plat_dat,
2644                                      void __iomem *addr)
2645 {
2646         int ret = 0;
2647         struct net_device *ndev = NULL;
2648         struct stmmac_priv *priv;
2649
2650         ndev = alloc_etherdev(sizeof(struct stmmac_priv));
2651         if (!ndev)
2652                 return NULL;
2653
2654         SET_NETDEV_DEV(ndev, device);
2655
2656         priv = netdev_priv(ndev);
2657         priv->device = device;
2658         priv->dev = ndev;
2659
2660         ether_setup(ndev);
2661
2662         stmmac_set_ethtool_ops(ndev);
2663         priv->pause = pause;
2664         priv->plat = plat_dat;
2665         priv->ioaddr = addr;
2666         priv->dev->base_addr = (unsigned long)addr;
2667
2668         /* Verify driver arguments */
2669         stmmac_verify_args();
2670
2671         /* Override with kernel parameters if supplied XXX CRS XXX
2672          * this needs to have multiple instances
2673          */
2674         if ((phyaddr >= 0) && (phyaddr <= 31))
2675                 priv->plat->phy_addr = phyaddr;
2676
2677         /* Init MAC and get the capabilities */
2678         ret = stmmac_hw_init(priv);
2679         if (ret)
2680                 goto error_free_netdev;
2681
2682         ndev->netdev_ops = &stmmac_netdev_ops;
2683
2684         ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2685                             NETIF_F_RXCSUM;
2686         ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
2687         ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
2688 #ifdef STMMAC_VLAN_TAG_USED
2689         /* Both mac100 and gmac support receive VLAN tag detection */
2690         ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
2691 #endif
2692         priv->msg_enable = netif_msg_init(debug, default_msg_level);
2693
2694         if (flow_ctrl)
2695                 priv->flow_ctrl = FLOW_AUTO;    /* RX/TX pause on */
2696
2697         /* Rx Watchdog is available in the COREs newer than the 3.40.
2698          * In some case, for example on bugged HW this feature
2699          * has to be disable and this can be done by passing the
2700          * riwt_off field from the platform.
2701          */
2702         if ((priv->synopsys_id >= DWMAC_CORE_3_50) && (!priv->plat->riwt_off)) {
2703                 priv->use_riwt = 1;
2704                 pr_info(" Enable RX Mitigation via HW Watchdog Timer\n");
2705         }
2706
2707         netif_napi_add(ndev, &priv->napi, stmmac_poll, 64);
2708
2709         spin_lock_init(&priv->lock);
2710         spin_lock_init(&priv->tx_lock);
2711
2712         ret = register_netdev(ndev);
2713         if (ret) {
2714                 pr_err("%s: ERROR %i registering the device\n", __func__, ret);
2715                 goto error_netdev_register;
2716         }
2717
2718         priv->stmmac_clk = clk_get(priv->device, STMMAC_RESOURCE_NAME);
2719         if (IS_ERR(priv->stmmac_clk)) {
2720                 pr_warn("%s: warning: cannot get CSR clock\n", __func__);
2721                 goto error_clk_get;
2722         }
2723
2724         /* If a specific clk_csr value is passed from the platform
2725          * this means that the CSR Clock Range selection cannot be
2726          * changed at run-time and it is fixed. Viceversa the driver'll try to
2727          * set the MDC clock dynamically according to the csr actual
2728          * clock input.
2729          */
2730         if (!priv->plat->clk_csr)
2731                 stmmac_clk_csr_set(priv);
2732         else
2733                 priv->clk_csr = priv->plat->clk_csr;
2734
2735         stmmac_check_pcs_mode(priv);
2736
2737         if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
2738             priv->pcs != STMMAC_PCS_RTBI) {
2739                 /* MDIO bus Registration */
2740                 ret = stmmac_mdio_register(ndev);
2741                 if (ret < 0) {
2742                         pr_debug("%s: MDIO bus (id: %d) registration failed",
2743                                  __func__, priv->plat->bus_id);
2744                         goto error_mdio_register;
2745                 }
2746         }
2747
2748         return priv;
2749
2750 error_mdio_register:
2751         clk_put(priv->stmmac_clk);
2752 error_clk_get:
2753         unregister_netdev(ndev);
2754 error_netdev_register:
2755         netif_napi_del(&priv->napi);
2756 error_free_netdev:
2757         free_netdev(ndev);
2758
2759         return NULL;
2760 }
2761
2762 /**
2763  * stmmac_dvr_remove
2764  * @ndev: net device pointer
2765  * Description: this function resets the TX/RX processes, disables the MAC RX/TX
2766  * changes the link status, releases the DMA descriptor rings.
2767  */
2768 int stmmac_dvr_remove(struct net_device *ndev)
2769 {
2770         struct stmmac_priv *priv = netdev_priv(ndev);
2771
2772         pr_info("%s:\n\tremoving driver", __func__);
2773
2774         priv->hw->dma->stop_rx(priv->ioaddr);
2775         priv->hw->dma->stop_tx(priv->ioaddr);
2776
2777         stmmac_set_mac(priv->ioaddr, false);
2778         if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
2779             priv->pcs != STMMAC_PCS_RTBI)
2780                 stmmac_mdio_unregister(ndev);
2781         netif_carrier_off(ndev);
2782         unregister_netdev(ndev);
2783         free_netdev(ndev);
2784
2785         return 0;
2786 }
2787
2788 #ifdef CONFIG_PM
2789 int stmmac_suspend(struct net_device *ndev)
2790 {
2791         struct stmmac_priv *priv = netdev_priv(ndev);
2792         unsigned long flags;
2793
2794         if (!ndev || !netif_running(ndev))
2795                 return 0;
2796
2797         if (priv->phydev)
2798                 phy_stop(priv->phydev);
2799
2800         spin_lock_irqsave(&priv->lock, flags);
2801
2802         netif_device_detach(ndev);
2803         netif_stop_queue(ndev);
2804
2805         napi_disable(&priv->napi);
2806
2807         /* Stop TX/RX DMA */
2808         priv->hw->dma->stop_tx(priv->ioaddr);
2809         priv->hw->dma->stop_rx(priv->ioaddr);
2810
2811         stmmac_clear_descriptors(priv);
2812
2813         /* Enable Power down mode by programming the PMT regs */
2814         if (device_may_wakeup(priv->device))
2815                 priv->hw->mac->pmt(priv->ioaddr, priv->wolopts);
2816         else {
2817                 stmmac_set_mac(priv->ioaddr, false);
2818                 /* Disable clock in case of PWM is off */
2819                 clk_disable_unprepare(priv->stmmac_clk);
2820         }
2821         spin_unlock_irqrestore(&priv->lock, flags);
2822         return 0;
2823 }
2824
2825 int stmmac_resume(struct net_device *ndev)
2826 {
2827         struct stmmac_priv *priv = netdev_priv(ndev);
2828         unsigned long flags;
2829
2830         if (!netif_running(ndev))
2831                 return 0;
2832
2833         spin_lock_irqsave(&priv->lock, flags);
2834
2835         /* Power Down bit, into the PM register, is cleared
2836          * automatically as soon as a magic packet or a Wake-up frame
2837          * is received. Anyway, it's better to manually clear
2838          * this bit because it can generate problems while resuming
2839          * from another devices (e.g. serial console).
2840          */
2841         if (device_may_wakeup(priv->device))
2842                 priv->hw->mac->pmt(priv->ioaddr, 0);
2843         else
2844                 /* enable the clk prevously disabled */
2845                 clk_prepare_enable(priv->stmmac_clk);
2846
2847         netif_device_attach(ndev);
2848
2849         /* Enable the MAC and DMA */
2850         stmmac_set_mac(priv->ioaddr, true);
2851         priv->hw->dma->start_tx(priv->ioaddr);
2852         priv->hw->dma->start_rx(priv->ioaddr);
2853
2854         napi_enable(&priv->napi);
2855
2856         netif_start_queue(ndev);
2857
2858         spin_unlock_irqrestore(&priv->lock, flags);
2859
2860         if (priv->phydev)
2861                 phy_start(priv->phydev);
2862
2863         return 0;
2864 }
2865
2866 int stmmac_freeze(struct net_device *ndev)
2867 {
2868         if (!ndev || !netif_running(ndev))
2869                 return 0;
2870
2871         return stmmac_release(ndev);
2872 }
2873
2874 int stmmac_restore(struct net_device *ndev)
2875 {
2876         if (!ndev || !netif_running(ndev))
2877                 return 0;
2878
2879         return stmmac_open(ndev);
2880 }
2881 #endif /* CONFIG_PM */
2882
2883 /* Driver can be configured w/ and w/ both PCI and Platf drivers
2884  * depending on the configuration selected.
2885  */
2886 static int __init stmmac_init(void)
2887 {
2888         int ret;
2889
2890         ret = stmmac_register_platform();
2891         if (ret)
2892                 goto err;
2893         ret = stmmac_register_pci();
2894         if (ret)
2895                 goto err_pci;
2896         return 0;
2897 err_pci:
2898         stmmac_unregister_platform();
2899 err:
2900         pr_err("stmmac: driver registration failed\n");
2901         return ret;
2902 }
2903
2904 static void __exit stmmac_exit(void)
2905 {
2906         stmmac_unregister_platform();
2907         stmmac_unregister_pci();
2908 }
2909
2910 module_init(stmmac_init);
2911 module_exit(stmmac_exit);
2912
2913 #ifndef MODULE
2914 static int __init stmmac_cmdline_opt(char *str)
2915 {
2916         char *opt;
2917
2918         if (!str || !*str)
2919                 return -EINVAL;
2920         while ((opt = strsep(&str, ",")) != NULL) {
2921                 if (!strncmp(opt, "debug:", 6)) {
2922                         if (kstrtoint(opt + 6, 0, &debug))
2923                                 goto err;
2924                 } else if (!strncmp(opt, "phyaddr:", 8)) {
2925                         if (kstrtoint(opt + 8, 0, &phyaddr))
2926                                 goto err;
2927                 } else if (!strncmp(opt, "dma_txsize:", 11)) {
2928                         if (kstrtoint(opt + 11, 0, &dma_txsize))
2929                                 goto err;
2930                 } else if (!strncmp(opt, "dma_rxsize:", 11)) {
2931                         if (kstrtoint(opt + 11, 0, &dma_rxsize))
2932                                 goto err;
2933                 } else if (!strncmp(opt, "buf_sz:", 7)) {
2934                         if (kstrtoint(opt + 7, 0, &buf_sz))
2935                                 goto err;
2936                 } else if (!strncmp(opt, "tc:", 3)) {
2937                         if (kstrtoint(opt + 3, 0, &tc))
2938                                 goto err;
2939                 } else if (!strncmp(opt, "watchdog:", 9)) {
2940                         if (kstrtoint(opt + 9, 0, &watchdog))
2941                                 goto err;
2942                 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
2943                         if (kstrtoint(opt + 10, 0, &flow_ctrl))
2944                                 goto err;
2945                 } else if (!strncmp(opt, "pause:", 6)) {
2946                         if (kstrtoint(opt + 6, 0, &pause))
2947                                 goto err;
2948                 } else if (!strncmp(opt, "eee_timer:", 10)) {
2949                         if (kstrtoint(opt + 10, 0, &eee_timer))
2950                                 goto err;
2951                 } else if (!strncmp(opt, "chain_mode:", 11)) {
2952                         if (kstrtoint(opt + 11, 0, &chain_mode))
2953                                 goto err;
2954                 }
2955         }
2956         return 0;
2957
2958 err:
2959         pr_err("%s: ERROR broken module parameter conversion", __func__);
2960         return -EINVAL;
2961 }
2962
2963 __setup("stmmaceth=", stmmac_cmdline_opt);
2964 #endif /* MODULE */
2965
2966 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
2967 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
2968 MODULE_LICENSE("GPL");