1 /*******************************************************************************
2 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
3 ST Ethernet IPs are built around a Synopsys IP Core.
5 Copyright(C) 2007-2011 STMicroelectronics Ltd
7 This program is free software; you can redistribute it and/or modify it
8 under the terms and conditions of the GNU General Public License,
9 version 2, as published by the Free Software Foundation.
11 This program is distributed in the hope it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc.,
18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
20 The full GNU General Public License is included in this distribution in
21 the file called "COPYING".
23 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
25 Documentation available at:
26 http://www.stlinux.com
28 https://bugzilla.stlinux.com/
29 *******************************************************************************/
31 #include <linux/clk.h>
32 #include <linux/kernel.h>
33 #include <linux/interrupt.h>
35 #include <linux/tcp.h>
36 #include <linux/skbuff.h>
37 #include <linux/ethtool.h>
38 #include <linux/if_ether.h>
39 #include <linux/crc32.h>
40 #include <linux/mii.h>
42 #include <linux/if_vlan.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/slab.h>
45 #include <linux/prefetch.h>
46 #ifdef CONFIG_GMAC_DEBUG_FS
47 #include <linux/debugfs.h>
48 #include <linux/seq_file.h>
49 #endif /* CONFIG_GMAC_DEBUG_FS */
50 #include <linux/net_tstamp.h>
51 #include "stmmac_ptp.h"
55 /*#define STMMAC_DEBUG*/
57 #define DBG(nlevel, klevel, fmt, args...) \
58 ((void)(netif_msg_##nlevel(priv) && \
59 printk(KERN_##klevel fmt, ## args)))
61 #define DBG(nlevel, klevel, fmt, args...) do { } while (0)
64 #undef STMMAC_RX_DEBUG
65 /*#define STMMAC_RX_DEBUG*/
66 #ifdef STMMAC_RX_DEBUG
67 #define RX_DBG(fmt, args...) printk(fmt, ## args)
69 #define RX_DBG(fmt, args...) do { } while (0)
72 #undef STMMAC_XMIT_DEBUG
73 /*#define STMMAC_XMIT_DEBUG*/
74 #ifdef STMMAC_XMIT_DEBUG
75 #define TX_DBG(fmt, args...) printk(fmt, ## args)
77 #define TX_DBG(fmt, args...) do { } while (0)
80 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
81 #define JUMBO_LEN 9000
83 /* Module parameters */
85 static int watchdog = TX_TIMEO;
86 module_param(watchdog, int, S_IRUGO | S_IWUSR);
87 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");
89 static int debug = -1;
90 module_param(debug, int, S_IRUGO | S_IWUSR);
91 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
94 module_param(phyaddr, int, S_IRUGO);
95 MODULE_PARM_DESC(phyaddr, "Physical device address");
97 #define DMA_TX_SIZE 256
98 static int dma_txsize = DMA_TX_SIZE;
99 module_param(dma_txsize, int, S_IRUGO | S_IWUSR);
100 MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list");
102 #define DMA_RX_SIZE 256
103 static int dma_rxsize = DMA_RX_SIZE;
104 module_param(dma_rxsize, int, S_IRUGO | S_IWUSR);
105 MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list");
107 static int flow_ctrl = FLOW_OFF;
108 module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
109 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
111 static int pause = PAUSE_TIME;
112 module_param(pause, int, S_IRUGO | S_IWUSR);
113 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
115 #define TC_DEFAULT 64
116 static int tc = TC_DEFAULT;
117 module_param(tc, int, S_IRUGO | S_IWUSR);
118 MODULE_PARM_DESC(tc, "DMA threshold control value");
120 #define DMA_BUFFER_SIZE BUF_SIZE_2KiB
121 static int buf_sz = DMA_BUFFER_SIZE;
122 module_param(buf_sz, int, S_IRUGO | S_IWUSR);
123 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
125 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
126 NETIF_MSG_LINK | NETIF_MSG_IFUP |
127 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
129 #define STMMAC_DEFAULT_LPI_TIMER 1000
130 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
131 module_param(eee_timer, int, S_IRUGO | S_IWUSR);
132 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
133 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x))
135 /* By default the driver will use the ring mode to manage tx and rx descriptors
136 * but passing this value so user can force to use the chain instead of the ring
138 static unsigned int chain_mode;
139 module_param(chain_mode, int, S_IRUGO);
140 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
142 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
144 #ifdef CONFIG_GMAC_DEBUG_FS
145 static int stmmac_init_fs(struct net_device *dev);
146 static void stmmac_exit_fs(void);
149 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
152 * stmmac_verify_args - verify the driver parameters.
153 * Description: it verifies if some wrong parameter is passed to the driver.
154 * Note that wrong parameters are replaced with the default values.
156 static void stmmac_verify_args(void)
158 if (unlikely(watchdog < 0))
160 if (unlikely(dma_rxsize < 0))
161 dma_rxsize = DMA_RX_SIZE;
162 if (unlikely(dma_txsize < 0))
163 dma_txsize = DMA_TX_SIZE;
164 if (unlikely((buf_sz < DMA_BUFFER_SIZE) || (buf_sz > BUF_SIZE_16KiB)))
165 buf_sz = DMA_BUFFER_SIZE;
166 if (unlikely(flow_ctrl > 1))
167 flow_ctrl = FLOW_AUTO;
168 else if (likely(flow_ctrl < 0))
169 flow_ctrl = FLOW_OFF;
170 if (unlikely((pause < 0) || (pause > 0xffff)))
173 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
177 * stmmac_clk_csr_set - dynamically set the MDC clock
178 * @priv: driver private structure
179 * Description: this is to dynamically set the MDC clock according to the csr
182 * If a specific clk_csr value is passed from the platform
183 * this means that the CSR Clock Range selection cannot be
184 * changed at run-time and it is fixed (as reported in the driver
185 * documentation). Viceversa the driver will try to set the MDC
186 * clock dynamically according to the actual clock input.
188 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
192 clk_rate = clk_get_rate(priv->stmmac_clk);
194 /* Platform provided default clk_csr would be assumed valid
195 * for all other cases except for the below mentioned ones.
196 * For values higher than the IEEE 802.3 specified frequency
197 * we can not estimate the proper divider as it is not known
198 * the frequency of clk_csr_i. So we do not change the default
201 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
202 if (clk_rate < CSR_F_35M)
203 priv->clk_csr = STMMAC_CSR_20_35M;
204 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
205 priv->clk_csr = STMMAC_CSR_35_60M;
206 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
207 priv->clk_csr = STMMAC_CSR_60_100M;
208 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
209 priv->clk_csr = STMMAC_CSR_100_150M;
210 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
211 priv->clk_csr = STMMAC_CSR_150_250M;
212 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
213 priv->clk_csr = STMMAC_CSR_250_300M;
217 #if defined(STMMAC_XMIT_DEBUG) || defined(STMMAC_RX_DEBUG)
218 static void print_pkt(unsigned char *buf, int len)
221 pr_info("len = %d byte, buf addr: 0x%p", len, buf);
222 for (j = 0; j < len; j++) {
224 pr_info("\n %03x:", j);
225 pr_info(" %02x", buf[j]);
231 /* minimum number of free TX descriptors required to wake up TX process */
232 #define STMMAC_TX_THRESH(x) (x->dma_tx_size/4)
234 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
236 return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1;
240 * stmmac_hw_fix_mac_speed: callback for speed selection
241 * @priv: driver private structure
242 * Description: on some platforms (e.g. ST), some HW system configuraton
243 * registers have to be set according to the link speed negotiated.
245 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
247 struct phy_device *phydev = priv->phydev;
249 if (likely(priv->plat->fix_mac_speed))
250 priv->plat->fix_mac_speed(priv->plat->bsp_priv, phydev->speed);
254 * stmmac_enable_eee_mode: Check and enter in LPI mode
255 * @priv: driver private structure
256 * Description: this function is to verify and enter in LPI mode for EEE.
258 static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
260 /* Check and enter in LPI mode */
261 if ((priv->dirty_tx == priv->cur_tx) &&
262 (priv->tx_path_in_lpi_mode == false))
263 priv->hw->mac->set_eee_mode(priv->ioaddr);
267 * stmmac_disable_eee_mode: disable/exit from EEE
268 * @priv: driver private structure
269 * Description: this function is to exit and disable EEE in case of
270 * LPI state is true. This is called by the xmit.
272 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
274 priv->hw->mac->reset_eee_mode(priv->ioaddr);
275 del_timer_sync(&priv->eee_ctrl_timer);
276 priv->tx_path_in_lpi_mode = false;
280 * stmmac_eee_ctrl_timer: EEE TX SW timer.
283 * if there is no data transfer and if we are not in LPI state,
284 * then MAC Transmitter can be moved to LPI state.
286 static void stmmac_eee_ctrl_timer(unsigned long arg)
288 struct stmmac_priv *priv = (struct stmmac_priv *)arg;
290 stmmac_enable_eee_mode(priv);
291 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
295 * stmmac_eee_init: init EEE
296 * @priv: driver private structure
298 * If the EEE support has been enabled while configuring the driver,
299 * if the GMAC actually supports the EEE (from the HW cap reg) and the
300 * phy can also manage EEE, so enable the LPI state and start the timer
301 * to verify if the tx path can enter in LPI state.
303 bool stmmac_eee_init(struct stmmac_priv *priv)
307 /* Using PCS we cannot dial with the phy registers at this stage
308 * so we do not support extra feature like EEE.
310 if ((priv->pcs == STMMAC_PCS_RGMII) || (priv->pcs == STMMAC_PCS_TBI) ||
311 (priv->pcs == STMMAC_PCS_RTBI))
314 /* MAC core supports the EEE feature. */
315 if (priv->dma_cap.eee) {
316 /* Check if the PHY supports EEE */
317 if (phy_init_eee(priv->phydev, 1))
320 if (!priv->eee_active) {
321 priv->eee_active = 1;
322 init_timer(&priv->eee_ctrl_timer);
323 priv->eee_ctrl_timer.function = stmmac_eee_ctrl_timer;
324 priv->eee_ctrl_timer.data = (unsigned long)priv;
325 priv->eee_ctrl_timer.expires = STMMAC_LPI_T(eee_timer);
326 add_timer(&priv->eee_ctrl_timer);
328 priv->hw->mac->set_eee_timer(priv->ioaddr,
329 STMMAC_DEFAULT_LIT_LS,
332 /* Set HW EEE according to the speed */
333 priv->hw->mac->set_eee_pls(priv->ioaddr,
336 pr_info("stmmac: Energy-Efficient Ethernet initialized\n");
344 /* stmmac_get_tx_hwtstamp: get HW TX timestamps
345 * @priv: driver private structure
346 * @entry : descriptor index to be used.
347 * @skb : the socket buffer
349 * This function will read timestamp from the descriptor & pass it to stack.
350 * and also perform some sanity checks.
352 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
353 unsigned int entry, struct sk_buff *skb)
355 struct skb_shared_hwtstamps shhwtstamp;
359 if (!priv->hwts_tx_en)
362 /* exit if skb doesn't support hw tstamp */
363 if (likely(!(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
367 desc = (priv->dma_etx + entry);
369 desc = (priv->dma_tx + entry);
371 /* check tx tstamp status */
372 if (!priv->hw->desc->get_tx_timestamp_status((struct dma_desc *)desc))
375 /* get the valid tstamp */
376 ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);
378 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
379 shhwtstamp.hwtstamp = ns_to_ktime(ns);
380 /* pass tstamp to stack */
381 skb_tstamp_tx(skb, &shhwtstamp);
386 /* stmmac_get_rx_hwtstamp: get HW RX timestamps
387 * @priv: driver private structure
388 * @entry : descriptor index to be used.
389 * @skb : the socket buffer
391 * This function will read received packet's timestamp from the descriptor
392 * and pass it to stack. It also perform some sanity checks.
394 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv,
395 unsigned int entry, struct sk_buff *skb)
397 struct skb_shared_hwtstamps *shhwtstamp = NULL;
401 if (!priv->hwts_rx_en)
405 desc = (priv->dma_erx + entry);
407 desc = (priv->dma_rx + entry);
409 /* exit if rx tstamp is not valid */
410 if (!priv->hw->desc->get_rx_timestamp_status(desc, priv->adv_ts))
413 /* get valid tstamp */
414 ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);
415 shhwtstamp = skb_hwtstamps(skb);
416 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
417 shhwtstamp->hwtstamp = ns_to_ktime(ns);
421 * stmmac_hwtstamp_ioctl - control hardware timestamping.
422 * @dev: device pointer.
423 * @ifr: An IOCTL specefic structure, that can contain a pointer to
424 * a proprietary structure used to pass information to the driver.
426 * This function configures the MAC to enable/disable both outgoing(TX)
427 * and incoming(RX) packets time stamping based on user input.
429 * 0 on success and an appropriate -ve integer on failure.
431 static int stmmac_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr)
433 struct stmmac_priv *priv = netdev_priv(dev);
434 struct hwtstamp_config config;
439 u32 ptp_over_ipv4_udp = 0;
440 u32 ptp_over_ipv6_udp = 0;
441 u32 ptp_over_ethernet = 0;
442 u32 snap_type_sel = 0;
443 u32 ts_master_en = 0;
447 if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
448 netdev_alert(priv->dev, "No support for HW time stamping\n");
449 priv->hwts_tx_en = 0;
450 priv->hwts_rx_en = 0;
455 if (copy_from_user(&config, ifr->ifr_data,
456 sizeof(struct hwtstamp_config)))
459 pr_debug("%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
460 __func__, config.flags, config.tx_type, config.rx_filter);
462 /* reserved for future extensions */
466 switch (config.tx_type) {
467 case HWTSTAMP_TX_OFF:
468 priv->hwts_tx_en = 0;
471 priv->hwts_tx_en = 1;
478 switch (config.rx_filter) {
479 case HWTSTAMP_FILTER_NONE:
480 /* time stamp no incoming packet at all */
481 config.rx_filter = HWTSTAMP_FILTER_NONE;
484 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
485 /* PTP v1, UDP, any kind of event packet */
486 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
487 /* take time stamp for all event messages */
488 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
490 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
491 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
494 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
495 /* PTP v1, UDP, Sync packet */
496 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
497 /* take time stamp for SYNC messages only */
498 ts_event_en = PTP_TCR_TSEVNTENA;
500 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
501 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
504 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
505 /* PTP v1, UDP, Delay_req packet */
506 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
507 /* take time stamp for Delay_Req messages only */
508 ts_master_en = PTP_TCR_TSMSTRENA;
509 ts_event_en = PTP_TCR_TSEVNTENA;
511 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
512 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
515 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
516 /* PTP v2, UDP, any kind of event packet */
517 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
518 ptp_v2 = PTP_TCR_TSVER2ENA;
519 /* take time stamp for all event messages */
520 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
522 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
523 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
526 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
527 /* PTP v2, UDP, Sync packet */
528 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
529 ptp_v2 = PTP_TCR_TSVER2ENA;
530 /* take time stamp for SYNC messages only */
531 ts_event_en = PTP_TCR_TSEVNTENA;
533 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
534 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
537 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
538 /* PTP v2, UDP, Delay_req packet */
539 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
540 ptp_v2 = PTP_TCR_TSVER2ENA;
541 /* take time stamp for Delay_Req messages only */
542 ts_master_en = PTP_TCR_TSMSTRENA;
543 ts_event_en = PTP_TCR_TSEVNTENA;
545 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
546 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
549 case HWTSTAMP_FILTER_PTP_V2_EVENT:
550 /* PTP v2/802.AS1 any layer, any kind of event packet */
551 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
552 ptp_v2 = PTP_TCR_TSVER2ENA;
553 /* take time stamp for all event messages */
554 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
556 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
557 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
558 ptp_over_ethernet = PTP_TCR_TSIPENA;
561 case HWTSTAMP_FILTER_PTP_V2_SYNC:
562 /* PTP v2/802.AS1, any layer, Sync packet */
563 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
564 ptp_v2 = PTP_TCR_TSVER2ENA;
565 /* take time stamp for SYNC messages only */
566 ts_event_en = PTP_TCR_TSEVNTENA;
568 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
569 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
570 ptp_over_ethernet = PTP_TCR_TSIPENA;
573 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
574 /* PTP v2/802.AS1, any layer, Delay_req packet */
575 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
576 ptp_v2 = PTP_TCR_TSVER2ENA;
577 /* take time stamp for Delay_Req messages only */
578 ts_master_en = PTP_TCR_TSMSTRENA;
579 ts_event_en = PTP_TCR_TSEVNTENA;
581 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
582 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
583 ptp_over_ethernet = PTP_TCR_TSIPENA;
586 case HWTSTAMP_FILTER_ALL:
587 /* time stamp any incoming packet */
588 config.rx_filter = HWTSTAMP_FILTER_ALL;
589 tstamp_all = PTP_TCR_TSENALL;
596 switch (config.rx_filter) {
597 case HWTSTAMP_FILTER_NONE:
598 config.rx_filter = HWTSTAMP_FILTER_NONE;
601 /* PTP v1, UDP, any kind of event packet */
602 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
606 priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
608 if (!priv->hwts_tx_en && !priv->hwts_rx_en)
609 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, 0);
611 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR |
612 tstamp_all | ptp_v2 | ptp_over_ethernet |
613 ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en |
614 ts_master_en | snap_type_sel);
616 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, value);
618 /* program Sub Second Increment reg */
619 priv->hw->ptp->config_sub_second_increment(priv->ioaddr);
621 /* calculate default added value:
623 * addend = (2^32)/freq_div_ratio;
624 * where, freq_div_ratio = STMMAC_SYSCLOCK/50MHz
625 * hence, addend = ((2^32) * 50MHz)/STMMAC_SYSCLOCK;
626 * NOTE: STMMAC_SYSCLOCK should be >= 50MHz to
627 * achive 20ns accuracy.
629 * 2^x * y == (y << x), hence
630 * 2^32 * 50000000 ==> (50000000 << 32)
632 temp = (u64) (50000000ULL << 32);
633 priv->default_addend = div_u64(temp, STMMAC_SYSCLOCK);
634 priv->hw->ptp->config_addend(priv->ioaddr,
635 priv->default_addend);
637 /* initialize system time */
638 getnstimeofday(&now);
639 priv->hw->ptp->init_systime(priv->ioaddr, now.tv_sec,
643 return copy_to_user(ifr->ifr_data, &config,
644 sizeof(struct hwtstamp_config)) ? -EFAULT : 0;
648 * stmmac_init_ptp: init PTP
649 * @priv: driver private structure
650 * Description: this is to verify if the HW supports the PTPv1 or v2.
651 * This is done by looking at the HW cap. register.
652 * Also it registers the ptp driver.
654 static int stmmac_init_ptp(struct stmmac_priv *priv)
656 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
659 if (netif_msg_hw(priv)) {
660 if (priv->dma_cap.time_stamp) {
661 pr_debug("IEEE 1588-2002 Time Stamp supported\n");
664 if (priv->dma_cap.atime_stamp && priv->extend_desc) {
666 ("IEEE 1588-2008 Advanced Time Stamp supported\n");
671 priv->hw->ptp = &stmmac_ptp;
672 priv->hwts_tx_en = 0;
673 priv->hwts_rx_en = 0;
675 return stmmac_ptp_register(priv);
678 static void stmmac_release_ptp(struct stmmac_priv *priv)
680 stmmac_ptp_unregister(priv);
685 * @dev: net device structure
686 * Description: it adjusts the link parameters.
688 static void stmmac_adjust_link(struct net_device *dev)
690 struct stmmac_priv *priv = netdev_priv(dev);
691 struct phy_device *phydev = priv->phydev;
694 unsigned int fc = priv->flow_ctrl, pause_time = priv->pause;
699 DBG(probe, DEBUG, "stmmac_adjust_link: called. address %d link %d\n",
700 phydev->addr, phydev->link);
702 spin_lock_irqsave(&priv->lock, flags);
705 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
707 /* Now we make sure that we can be in full duplex mode.
708 * If not, we operate in half-duplex mode. */
709 if (phydev->duplex != priv->oldduplex) {
711 if (!(phydev->duplex))
712 ctrl &= ~priv->hw->link.duplex;
714 ctrl |= priv->hw->link.duplex;
715 priv->oldduplex = phydev->duplex;
717 /* Flow Control operation */
719 priv->hw->mac->flow_ctrl(priv->ioaddr, phydev->duplex,
722 if (phydev->speed != priv->speed) {
724 switch (phydev->speed) {
726 if (likely(priv->plat->has_gmac))
727 ctrl &= ~priv->hw->link.port;
728 stmmac_hw_fix_mac_speed(priv);
732 if (priv->plat->has_gmac) {
733 ctrl |= priv->hw->link.port;
734 if (phydev->speed == SPEED_100) {
735 ctrl |= priv->hw->link.speed;
737 ctrl &= ~(priv->hw->link.speed);
740 ctrl &= ~priv->hw->link.port;
742 stmmac_hw_fix_mac_speed(priv);
745 if (netif_msg_link(priv))
746 pr_warn("%s: Speed (%d) not 10/100\n",
747 dev->name, phydev->speed);
751 priv->speed = phydev->speed;
754 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
756 if (!priv->oldlink) {
760 } else if (priv->oldlink) {
764 priv->oldduplex = -1;
767 if (new_state && netif_msg_link(priv))
768 phy_print_status(phydev);
770 /* At this stage, it could be needed to setup the EEE or adjust some
771 * MAC related HW registers.
773 priv->eee_enabled = stmmac_eee_init(priv);
775 spin_unlock_irqrestore(&priv->lock, flags);
777 DBG(probe, DEBUG, "stmmac_adjust_link: exiting\n");
781 * stmmac_check_pcs_mode: verify if RGMII/SGMII is supported
782 * @priv: driver private structure
783 * Description: this is to verify if the HW supports the PCS.
784 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
785 * configured for the TBI, RTBI, or SGMII PHY interface.
787 static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
789 int interface = priv->plat->interface;
791 if (priv->dma_cap.pcs) {
792 if ((interface & PHY_INTERFACE_MODE_RGMII) ||
793 (interface & PHY_INTERFACE_MODE_RGMII_ID) ||
794 (interface & PHY_INTERFACE_MODE_RGMII_RXID) ||
795 (interface & PHY_INTERFACE_MODE_RGMII_TXID)) {
796 pr_debug("STMMAC: PCS RGMII support enable\n");
797 priv->pcs = STMMAC_PCS_RGMII;
798 } else if (interface & PHY_INTERFACE_MODE_SGMII) {
799 pr_debug("STMMAC: PCS SGMII support enable\n");
800 priv->pcs = STMMAC_PCS_SGMII;
806 * stmmac_init_phy - PHY initialization
807 * @dev: net device structure
808 * Description: it initializes the driver's PHY state, and attaches the PHY
813 static int stmmac_init_phy(struct net_device *dev)
815 struct stmmac_priv *priv = netdev_priv(dev);
816 struct phy_device *phydev;
817 char phy_id_fmt[MII_BUS_ID_SIZE + 3];
818 char bus_id[MII_BUS_ID_SIZE];
819 int interface = priv->plat->interface;
822 priv->oldduplex = -1;
824 if (priv->plat->phy_bus_name)
825 snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x",
826 priv->plat->phy_bus_name, priv->plat->bus_id);
828 snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x",
831 snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
832 priv->plat->phy_addr);
833 pr_debug("stmmac_init_phy: trying to attach to %s\n", phy_id_fmt);
835 phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link, interface);
837 if (IS_ERR(phydev)) {
838 pr_err("%s: Could not attach to PHY\n", dev->name);
839 return PTR_ERR(phydev);
842 /* Stop Advertising 1000BASE Capability if interface is not GMII */
843 if ((interface == PHY_INTERFACE_MODE_MII) ||
844 (interface == PHY_INTERFACE_MODE_RMII))
845 phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
846 SUPPORTED_1000baseT_Full);
849 * Broken HW is sometimes missing the pull-up resistor on the
850 * MDIO line, which results in reads to non-existent devices returning
851 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
853 * Note: phydev->phy_id is the result of reading the UID PHY registers.
855 if (phydev->phy_id == 0) {
856 phy_disconnect(phydev);
859 pr_debug("stmmac_init_phy: %s: attached to PHY (UID 0x%x)"
860 " Link = %d\n", dev->name, phydev->phy_id, phydev->link);
862 priv->phydev = phydev;
868 * stmmac_display_ring: display ring
869 * @head: pointer to the head of the ring passed.
870 * @size: size of the ring.
871 * @extend_desc: to verify if extended descriptors are used.
872 * Description: display the control/status and buffer descriptors.
874 static void stmmac_display_ring(void *head, int size, int extend_desc)
877 struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
878 struct dma_desc *p = (struct dma_desc *)head;
880 for (i = 0; i < size; i++) {
884 pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
885 i, (unsigned int)virt_to_phys(ep),
886 (unsigned int)x, (unsigned int)(x >> 32),
887 ep->basic.des2, ep->basic.des3);
891 pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x",
892 i, (unsigned int)virt_to_phys(p),
893 (unsigned int)x, (unsigned int)(x >> 32),
901 static void stmmac_display_rings(struct stmmac_priv *priv)
903 unsigned int txsize = priv->dma_tx_size;
904 unsigned int rxsize = priv->dma_rx_size;
906 if (priv->extend_desc) {
907 pr_info("Extended RX descriptor ring:\n");
908 stmmac_display_ring((void *)priv->dma_erx, rxsize, 1);
909 pr_info("Extended TX descriptor ring:\n");
910 stmmac_display_ring((void *)priv->dma_etx, txsize, 1);
912 pr_info("RX descriptor ring:\n");
913 stmmac_display_ring((void *)priv->dma_rx, rxsize, 0);
914 pr_info("TX descriptor ring:\n");
915 stmmac_display_ring((void *)priv->dma_tx, txsize, 0);
919 static int stmmac_set_bfsize(int mtu, int bufsize)
923 if (mtu >= BUF_SIZE_4KiB)
925 else if (mtu >= BUF_SIZE_2KiB)
927 else if (mtu >= DMA_BUFFER_SIZE)
930 ret = DMA_BUFFER_SIZE;
936 * stmmac_clear_descriptors: clear descriptors
937 * @priv: driver private structure
938 * Description: this function is called to clear the tx and rx descriptors
939 * in case of both basic and extended descriptors are used.
941 static void stmmac_clear_descriptors(struct stmmac_priv *priv)
944 unsigned int txsize = priv->dma_tx_size;
945 unsigned int rxsize = priv->dma_rx_size;
947 /* Clear the Rx/Tx descriptors */
948 for (i = 0; i < rxsize; i++)
949 if (priv->extend_desc)
950 priv->hw->desc->init_rx_desc(&priv->dma_erx[i].basic,
951 priv->use_riwt, priv->mode,
954 priv->hw->desc->init_rx_desc(&priv->dma_rx[i],
955 priv->use_riwt, priv->mode,
957 for (i = 0; i < txsize; i++)
958 if (priv->extend_desc)
959 priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
963 priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
968 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
973 skb = __netdev_alloc_skb(priv->dev, priv->dma_buf_sz + NET_IP_ALIGN,
975 if (unlikely(skb == NULL)) {
976 pr_err("%s: Rx init fails; skb is NULL\n", __func__);
979 skb_reserve(skb, NET_IP_ALIGN);
980 priv->rx_skbuff[i] = skb;
981 priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
985 p->des2 = priv->rx_skbuff_dma[i];
987 if ((priv->mode == STMMAC_RING_MODE) &&
988 (priv->dma_buf_sz == BUF_SIZE_16KiB))
989 priv->hw->ring->init_desc3(p);
995 * init_dma_desc_rings - init the RX/TX descriptor rings
996 * @dev: net device structure
997 * Description: this function initializes the DMA RX/TX descriptors
998 * and allocates the socket buffers. It suppors the chained and ring
1001 static void init_dma_desc_rings(struct net_device *dev)
1004 struct stmmac_priv *priv = netdev_priv(dev);
1005 unsigned int txsize = priv->dma_tx_size;
1006 unsigned int rxsize = priv->dma_rx_size;
1007 unsigned int bfsize = 0;
1009 /* Set the max buffer size according to the DESC mode
1010 * and the MTU. Note that RING mode allows 16KiB bsize.
1012 if (priv->mode == STMMAC_RING_MODE)
1013 bfsize = priv->hw->ring->set_16kib_bfsize(dev->mtu);
1015 if (bfsize < BUF_SIZE_16KiB)
1016 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
1018 DBG(probe, INFO, "stmmac: txsize %d, rxsize %d, bfsize %d\n",
1019 txsize, rxsize, bfsize);
1021 if (priv->extend_desc) {
1022 priv->dma_erx = dma_alloc_coherent(priv->device, rxsize *
1027 priv->dma_etx = dma_alloc_coherent(priv->device, txsize *
1032 if ((!priv->dma_erx) || (!priv->dma_etx))
1035 priv->dma_rx = dma_alloc_coherent(priv->device, rxsize *
1036 sizeof(struct dma_desc),
1039 priv->dma_tx = dma_alloc_coherent(priv->device, txsize *
1040 sizeof(struct dma_desc),
1043 if ((!priv->dma_rx) || (!priv->dma_tx))
1047 priv->rx_skbuff_dma = kmalloc_array(rxsize, sizeof(dma_addr_t),
1049 priv->rx_skbuff = kmalloc_array(rxsize, sizeof(struct sk_buff *),
1051 priv->tx_skbuff_dma = kmalloc_array(txsize, sizeof(dma_addr_t),
1053 priv->tx_skbuff = kmalloc_array(txsize, sizeof(struct sk_buff *),
1055 if (netif_msg_drv(priv))
1056 pr_debug("(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n", __func__,
1057 (u32) priv->dma_rx_phy, (u32) priv->dma_tx_phy);
1059 /* RX INITIALIZATION */
1060 DBG(probe, INFO, "stmmac: SKB addresses:\nskb\t\tskb data\tdma data\n");
1061 for (i = 0; i < rxsize; i++) {
1063 if (priv->extend_desc)
1064 p = &((priv->dma_erx + i)->basic);
1066 p = priv->dma_rx + i;
1068 if (stmmac_init_rx_buffers(priv, p, i))
1071 DBG(probe, INFO, "[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i],
1072 priv->rx_skbuff[i]->data, priv->rx_skbuff_dma[i]);
1075 priv->dirty_rx = (unsigned int)(i - rxsize);
1076 priv->dma_buf_sz = bfsize;
1079 /* Setup the chained descriptor addresses */
1080 if (priv->mode == STMMAC_CHAIN_MODE) {
1081 if (priv->extend_desc) {
1082 priv->hw->chain->init(priv->dma_erx, priv->dma_rx_phy,
1084 priv->hw->chain->init(priv->dma_etx, priv->dma_tx_phy,
1087 priv->hw->chain->init(priv->dma_rx, priv->dma_rx_phy,
1089 priv->hw->chain->init(priv->dma_tx, priv->dma_tx_phy,
1094 /* TX INITIALIZATION */
1095 for (i = 0; i < txsize; i++) {
1097 if (priv->extend_desc)
1098 p = &((priv->dma_etx + i)->basic);
1100 p = priv->dma_tx + i;
1102 priv->tx_skbuff_dma[i] = 0;
1103 priv->tx_skbuff[i] = NULL;
1109 stmmac_clear_descriptors(priv);
1111 if (netif_msg_hw(priv))
1112 stmmac_display_rings(priv);
1115 static void dma_free_rx_skbufs(struct stmmac_priv *priv)
1119 for (i = 0; i < priv->dma_rx_size; i++) {
1120 if (priv->rx_skbuff[i]) {
1121 dma_unmap_single(priv->device, priv->rx_skbuff_dma[i],
1122 priv->dma_buf_sz, DMA_FROM_DEVICE);
1123 dev_kfree_skb_any(priv->rx_skbuff[i]);
1125 priv->rx_skbuff[i] = NULL;
1129 static void dma_free_tx_skbufs(struct stmmac_priv *priv)
1133 for (i = 0; i < priv->dma_tx_size; i++) {
1134 if (priv->tx_skbuff[i] != NULL) {
1136 if (priv->extend_desc)
1137 p = &((priv->dma_etx + i)->basic);
1139 p = priv->dma_tx + i;
1141 if (priv->tx_skbuff_dma[i])
1142 dma_unmap_single(priv->device,
1143 priv->tx_skbuff_dma[i],
1144 priv->hw->desc->get_tx_len(p),
1146 dev_kfree_skb_any(priv->tx_skbuff[i]);
1147 priv->tx_skbuff[i] = NULL;
1148 priv->tx_skbuff_dma[i] = 0;
1153 static void free_dma_desc_resources(struct stmmac_priv *priv)
1155 /* Release the DMA TX/RX socket buffers */
1156 dma_free_rx_skbufs(priv);
1157 dma_free_tx_skbufs(priv);
1159 /* Free DMA regions of consistent memory previously allocated */
1160 if (!priv->extend_desc) {
1161 dma_free_coherent(priv->device,
1162 priv->dma_tx_size * sizeof(struct dma_desc),
1163 priv->dma_tx, priv->dma_tx_phy);
1164 dma_free_coherent(priv->device,
1165 priv->dma_rx_size * sizeof(struct dma_desc),
1166 priv->dma_rx, priv->dma_rx_phy);
1168 dma_free_coherent(priv->device, priv->dma_tx_size *
1169 sizeof(struct dma_extended_desc),
1170 priv->dma_etx, priv->dma_tx_phy);
1171 dma_free_coherent(priv->device, priv->dma_rx_size *
1172 sizeof(struct dma_extended_desc),
1173 priv->dma_erx, priv->dma_rx_phy);
1175 kfree(priv->rx_skbuff_dma);
1176 kfree(priv->rx_skbuff);
1177 kfree(priv->tx_skbuff_dma);
1178 kfree(priv->tx_skbuff);
1182 * stmmac_dma_operation_mode - HW DMA operation mode
1183 * @priv: driver private structure
1184 * Description: it sets the DMA operation mode: tx/rx DMA thresholds
1185 * or Store-And-Forward capability.
1187 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
1189 if (likely(priv->plat->force_sf_dma_mode ||
1190 ((priv->plat->tx_coe) && (!priv->no_csum_insertion)))) {
1192 * In case of GMAC, SF mode can be enabled
1193 * to perform the TX COE in HW. This depends on:
1194 * 1) TX COE if actually supported
1195 * 2) There is no bugged Jumbo frame support
1196 * that needs to not insert csum in the TDES.
1198 priv->hw->dma->dma_mode(priv->ioaddr, SF_DMA_MODE, SF_DMA_MODE);
1201 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
1206 * @priv: driver private structure
1207 * Description: it reclaims resources after transmission completes.
1209 static void stmmac_tx_clean(struct stmmac_priv *priv)
1211 unsigned int txsize = priv->dma_tx_size;
1213 spin_lock(&priv->tx_lock);
1215 priv->xstats.tx_clean++;
1217 while (priv->dirty_tx != priv->cur_tx) {
1219 unsigned int entry = priv->dirty_tx % txsize;
1220 struct sk_buff *skb = priv->tx_skbuff[entry];
1223 if (priv->extend_desc)
1224 p = (struct dma_desc *)(priv->dma_etx + entry);
1226 p = priv->dma_tx + entry;
1228 /* Check if the descriptor is owned by the DMA. */
1229 if (priv->hw->desc->get_tx_owner(p))
1232 /* Verify tx error by looking at the last segment. */
1233 last = priv->hw->desc->get_tx_ls(p);
1236 priv->hw->desc->tx_status(&priv->dev->stats,
1239 if (likely(tx_error == 0)) {
1240 priv->dev->stats.tx_packets++;
1241 priv->xstats.tx_pkt_n++;
1243 priv->dev->stats.tx_errors++;
1245 stmmac_get_tx_hwtstamp(priv, entry, skb);
1247 TX_DBG("%s: curr %d, dirty %d\n", __func__,
1248 priv->cur_tx, priv->dirty_tx);
1250 if (likely(priv->tx_skbuff_dma[entry])) {
1251 dma_unmap_single(priv->device,
1252 priv->tx_skbuff_dma[entry],
1253 priv->hw->desc->get_tx_len(p),
1255 priv->tx_skbuff_dma[entry] = 0;
1257 priv->hw->ring->clean_desc3(priv, p);
1259 if (likely(skb != NULL)) {
1261 priv->tx_skbuff[entry] = NULL;
1264 priv->hw->desc->release_tx_desc(p, priv->mode);
1268 if (unlikely(netif_queue_stopped(priv->dev) &&
1269 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) {
1270 netif_tx_lock(priv->dev);
1271 if (netif_queue_stopped(priv->dev) &&
1272 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) {
1273 TX_DBG("%s: restart transmit\n", __func__);
1274 netif_wake_queue(priv->dev);
1276 netif_tx_unlock(priv->dev);
1279 if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
1280 stmmac_enable_eee_mode(priv);
1281 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
1283 spin_unlock(&priv->tx_lock);
1286 static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv)
1288 priv->hw->dma->enable_dma_irq(priv->ioaddr);
1291 static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv)
1293 priv->hw->dma->disable_dma_irq(priv->ioaddr);
1297 * stmmac_tx_err: irq tx error mng function
1298 * @priv: driver private structure
1299 * Description: it cleans the descriptors and restarts the transmission
1300 * in case of errors.
1302 static void stmmac_tx_err(struct stmmac_priv *priv)
1305 int txsize = priv->dma_tx_size;
1306 netif_stop_queue(priv->dev);
1308 priv->hw->dma->stop_tx(priv->ioaddr);
1309 dma_free_tx_skbufs(priv);
1310 for (i = 0; i < txsize; i++)
1311 if (priv->extend_desc)
1312 priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
1316 priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
1321 priv->hw->dma->start_tx(priv->ioaddr);
1323 priv->dev->stats.tx_errors++;
1324 netif_wake_queue(priv->dev);
1328 * stmmac_dma_interrupt: DMA ISR
1329 * @priv: driver private structure
1330 * Description: this is the DMA ISR. It is called by the main ISR.
1331 * It calls the dwmac dma routine to understand which type of interrupt
1332 * happened. In case of there is a Normal interrupt and either TX or RX
1333 * interrupt happened so the NAPI is scheduled.
1335 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
1339 status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats);
1340 if (likely((status & handle_rx)) || (status & handle_tx)) {
1341 if (likely(napi_schedule_prep(&priv->napi))) {
1342 stmmac_disable_dma_irq(priv);
1343 __napi_schedule(&priv->napi);
1346 if (unlikely(status & tx_hard_error_bump_tc)) {
1347 /* Try to bump up the dma threshold on this failure */
1348 if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) {
1350 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
1351 priv->xstats.threshold = tc;
1353 } else if (unlikely(status == tx_hard_error))
1354 stmmac_tx_err(priv);
1358 * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
1359 * @priv: driver private structure
1360 * Description: this masks the MMC irq, in fact, the counters are managed in SW.
1362 static void stmmac_mmc_setup(struct stmmac_priv *priv)
1364 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
1365 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
1367 dwmac_mmc_intr_all_mask(priv->ioaddr);
1369 if (priv->dma_cap.rmon) {
1370 dwmac_mmc_ctrl(priv->ioaddr, mode);
1371 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
1373 pr_info(" No MAC Management Counters available\n");
1376 static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv)
1378 u32 hwid = priv->hw->synopsys_uid;
1380 /* Check Synopsys Id (not available on old chips) */
1382 u32 uid = ((hwid & 0x0000ff00) >> 8);
1383 u32 synid = (hwid & 0x000000ff);
1385 pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n",
1394 * stmmac_selec_desc_mode: to select among: normal/alternate/extend descriptors
1395 * @priv: driver private structure
1396 * Description: select the Enhanced/Alternate or Normal descriptors.
1397 * In case of Enhanced/Alternate, it looks at the extended descriptors are
1398 * supported by the HW cap. register.
1400 static void stmmac_selec_desc_mode(struct stmmac_priv *priv)
1402 if (priv->plat->enh_desc) {
1403 pr_info(" Enhanced/Alternate descriptors\n");
1405 /* GMAC older than 3.50 has no extended descriptors */
1406 if (priv->synopsys_id >= DWMAC_CORE_3_50) {
1407 pr_info("\tEnabled extended descriptors\n");
1408 priv->extend_desc = 1;
1410 pr_warn("Extended descriptors not supported\n");
1412 priv->hw->desc = &enh_desc_ops;
1414 pr_info(" Normal descriptors\n");
1415 priv->hw->desc = &ndesc_ops;
1420 * stmmac_get_hw_features: get MAC capabilities from the HW cap. register.
1421 * @priv: driver private structure
1423 * new GMAC chip generations have a new register to indicate the
1424 * presence of the optional feature/functions.
1425 * This can be also used to override the value passed through the
1426 * platform and necessary for old MAC10/100 and GMAC chips.
1428 static int stmmac_get_hw_features(struct stmmac_priv *priv)
1432 if (priv->hw->dma->get_hw_feature) {
1433 hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr);
1435 priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL);
1436 priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1;
1437 priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2;
1438 priv->dma_cap.hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4;
1439 priv->dma_cap.multi_addr = (hw_cap & DMA_HW_FEAT_ADDMAC) >> 5;
1440 priv->dma_cap.pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6;
1441 priv->dma_cap.sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8;
1442 priv->dma_cap.pmt_remote_wake_up =
1443 (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9;
1444 priv->dma_cap.pmt_magic_frame =
1445 (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10;
1447 priv->dma_cap.rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11;
1448 /* IEEE 1588-2002 */
1449 priv->dma_cap.time_stamp =
1450 (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12;
1451 /* IEEE 1588-2008 */
1452 priv->dma_cap.atime_stamp =
1453 (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13;
1454 /* 802.3az - Energy-Efficient Ethernet (EEE) */
1455 priv->dma_cap.eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14;
1456 priv->dma_cap.av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15;
1457 /* TX and RX csum */
1458 priv->dma_cap.tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16;
1459 priv->dma_cap.rx_coe_type1 =
1460 (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17;
1461 priv->dma_cap.rx_coe_type2 =
1462 (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18;
1463 priv->dma_cap.rxfifo_over_2048 =
1464 (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19;
1465 /* TX and RX number of channels */
1466 priv->dma_cap.number_rx_channel =
1467 (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20;
1468 priv->dma_cap.number_tx_channel =
1469 (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22;
1470 /* Alternate (enhanced) DESC mode */
1471 priv->dma_cap.enh_desc = (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24;
1478 * stmmac_check_ether_addr: check if the MAC addr is valid
1479 * @priv: driver private structure
1481 * it is to verify if the MAC address is valid, in case of failures it
1482 * generates a random MAC address
1484 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
1486 if (!is_valid_ether_addr(priv->dev->dev_addr)) {
1487 priv->hw->mac->get_umac_addr((void __iomem *)
1488 priv->dev->base_addr,
1489 priv->dev->dev_addr, 0);
1490 if (!is_valid_ether_addr(priv->dev->dev_addr))
1491 eth_hw_addr_random(priv->dev);
1493 pr_warn("%s: device MAC address %pM\n", priv->dev->name,
1494 priv->dev->dev_addr);
1498 * stmmac_init_dma_engine: DMA init.
1499 * @priv: driver private structure
1501 * It inits the DMA invoking the specific MAC/GMAC callback.
1502 * Some DMA parameters can be passed from the platform;
1503 * in case of these are not passed a default is kept for the MAC or GMAC.
1505 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
1507 int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, burst_len = 0;
1508 int mixed_burst = 0;
1511 if (priv->plat->dma_cfg) {
1512 pbl = priv->plat->dma_cfg->pbl;
1513 fixed_burst = priv->plat->dma_cfg->fixed_burst;
1514 mixed_burst = priv->plat->dma_cfg->mixed_burst;
1515 burst_len = priv->plat->dma_cfg->burst_len;
1518 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
1521 return priv->hw->dma->init(priv->ioaddr, pbl, fixed_burst, mixed_burst,
1522 burst_len, priv->dma_tx_phy,
1523 priv->dma_rx_phy, atds);
1527 * stmmac_tx_timer: mitigation sw timer for tx.
1528 * @data: data pointer
1530 * This is the timer handler to directly invoke the stmmac_tx_clean.
1532 static void stmmac_tx_timer(unsigned long data)
1534 struct stmmac_priv *priv = (struct stmmac_priv *)data;
1536 stmmac_tx_clean(priv);
1540 * stmmac_init_tx_coalesce: init tx mitigation options.
1541 * @priv: driver private structure
1543 * This inits the transmit coalesce parameters: i.e. timer rate,
1544 * timer handler and default threshold used for enabling the
1545 * interrupt on completion bit.
1547 static void stmmac_init_tx_coalesce(struct stmmac_priv *priv)
1549 priv->tx_coal_frames = STMMAC_TX_FRAMES;
1550 priv->tx_coal_timer = STMMAC_COAL_TX_TIMER;
1551 init_timer(&priv->txtimer);
1552 priv->txtimer.expires = STMMAC_COAL_TIMER(priv->tx_coal_timer);
1553 priv->txtimer.data = (unsigned long)priv;
1554 priv->txtimer.function = stmmac_tx_timer;
1555 add_timer(&priv->txtimer);
1559 * stmmac_open - open entry point of the driver
1560 * @dev : pointer to the device structure.
1562 * This function is the open entry point of the driver.
1564 * 0 on success and an appropriate (-)ve integer as defined in errno.h
1567 static int stmmac_open(struct net_device *dev)
1569 struct stmmac_priv *priv = netdev_priv(dev);
1572 clk_prepare_enable(priv->stmmac_clk);
1574 if ((priv->plat) && (priv->plat->bsp_priv)) {
1575 struct bsp_priv * bsp_priv = priv->plat->bsp_priv;
1576 if ((bsp_priv) && (bsp_priv->phy_power_on)) {
1577 bsp_priv->phy_power_on(priv->plat, 1);
1581 stmmac_check_ether_addr(priv);
1583 if (priv->pcs != STMMAC_PCS_SGMII && priv->pcs != STMMAC_PCS_TBI &&
1584 priv->pcs != STMMAC_PCS_RTBI) {
1585 ret = stmmac_init_phy(dev);
1587 pr_err("%s: Cannot attach to PHY (error: %d)\n",
1593 /* Create and initialize the TX/RX descriptors chains. */
1594 priv->dma_tx_size = STMMAC_ALIGN(dma_txsize);
1595 priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize);
1596 priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
1597 init_dma_desc_rings(dev);
1599 /* DMA initialization and SW reset */
1600 ret = stmmac_init_dma_engine(priv);
1602 pr_err("%s: DMA initialization failed\n", __func__);
1606 /* Copy the MAC addr into the HW */
1607 priv->hw->mac->set_umac_addr(priv->ioaddr, dev->dev_addr, 0);
1609 /* If required, perform hw setup of the bus. */
1610 if (priv->plat->bus_setup)
1611 priv->plat->bus_setup(priv->ioaddr);
1613 /* Initialize the MAC Core */
1614 priv->hw->mac->core_init(priv->ioaddr);
1616 /* Request the IRQ lines */
1617 ret = request_irq(dev->irq, stmmac_interrupt,
1618 IRQF_SHARED, dev->name, dev);
1619 if (unlikely(ret < 0)) {
1620 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
1621 __func__, dev->irq, ret);
1625 /* Request the Wake IRQ in case of another line is used for WoL */
1626 if (priv->wol_irq != dev->irq) {
1627 ret = request_irq(priv->wol_irq, stmmac_interrupt,
1628 IRQF_SHARED, dev->name, dev);
1629 if (unlikely(ret < 0)) {
1630 pr_err("%s: ERROR: allocating the WoL IRQ %d (%d)\n",
1631 __func__, priv->wol_irq, ret);
1632 goto open_error_wolirq;
1636 /* Request the IRQ lines */
1637 if (priv->lpi_irq != -ENXIO) {
1638 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
1640 if (unlikely(ret < 0)) {
1641 pr_err("%s: ERROR: allocating the LPI IRQ %d (%d)\n",
1642 __func__, priv->lpi_irq, ret);
1643 goto open_error_lpiirq;
1647 /* Enable the MAC Rx/Tx */
1648 stmmac_set_mac(priv->ioaddr, true);
1650 /* Set the HW DMA mode and the COE */
1651 stmmac_dma_operation_mode(priv);
1653 /* Extra statistics */
1654 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
1655 priv->xstats.threshold = tc;
1657 stmmac_mmc_setup(priv);
1659 ret = stmmac_init_ptp(priv);
1661 pr_warn("%s: failed PTP initialisation\n", __func__);
1663 #ifdef CONFIG_GMAC_DEBUG_FS
1664 ret = stmmac_init_fs(dev);
1666 pr_warn("%s: failed debugFS registration\n", __func__);
1668 /* Start the ball rolling... */
1669 DBG(probe, DEBUG, "%s: DMA RX/TX processes started...\n", dev->name);
1670 priv->hw->dma->start_tx(priv->ioaddr);
1671 priv->hw->dma->start_rx(priv->ioaddr);
1673 /* Dump DMA/MAC registers */
1674 if (netif_msg_hw(priv)) {
1675 priv->hw->mac->dump_regs(priv->ioaddr);
1676 priv->hw->dma->dump_regs(priv->ioaddr);
1680 phy_start(priv->phydev);
1682 priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS;
1684 priv->eee_enabled = stmmac_eee_init(priv);
1686 stmmac_init_tx_coalesce(priv);
1688 if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) {
1689 priv->rx_riwt = MAX_DMA_RIWT;
1690 priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT);
1693 if (priv->pcs && priv->hw->mac->ctrl_ane)
1694 priv->hw->mac->ctrl_ane(priv->ioaddr, 0);
1696 napi_enable(&priv->napi);
1697 netif_start_queue(dev);
1702 if (priv->wol_irq != dev->irq)
1703 free_irq(priv->wol_irq, dev);
1706 free_irq(dev->irq, dev);
1710 phy_disconnect(priv->phydev);
1712 clk_disable_unprepare(priv->stmmac_clk);
1718 * stmmac_release - close entry point of the driver
1719 * @dev : device pointer.
1721 * This is the stop entry point of the driver.
1723 static int stmmac_release(struct net_device *dev)
1725 struct stmmac_priv *priv = netdev_priv(dev);
1727 if (priv->eee_enabled)
1728 del_timer_sync(&priv->eee_ctrl_timer);
1730 /* Stop and disconnect the PHY */
1732 phy_stop(priv->phydev);
1733 phy_disconnect(priv->phydev);
1734 priv->phydev = NULL;
1737 netif_stop_queue(dev);
1739 napi_disable(&priv->napi);
1741 del_timer_sync(&priv->txtimer);
1743 /* Free the IRQ lines */
1744 free_irq(dev->irq, dev);
1745 if (priv->wol_irq != dev->irq)
1746 free_irq(priv->wol_irq, dev);
1747 if (priv->lpi_irq != -ENXIO)
1748 free_irq(priv->lpi_irq, dev);
1750 /* Stop TX/RX DMA and clear the descriptors */
1751 priv->hw->dma->stop_tx(priv->ioaddr);
1752 priv->hw->dma->stop_rx(priv->ioaddr);
1754 /* Release and free the Rx/Tx resources */
1755 free_dma_desc_resources(priv);
1757 /* Disable the MAC Rx/Tx */
1758 stmmac_set_mac(priv->ioaddr, false);
1760 netif_carrier_off(dev);
1762 #ifdef CONFIG_GMAC_DEBUG_FS
1765 clk_disable_unprepare(priv->stmmac_clk);
1767 stmmac_release_ptp(priv);
1769 if ((priv->plat) && (priv->plat->bsp_priv)) {
1770 struct bsp_priv * bsp_priv = priv->plat->bsp_priv;
1771 if ((bsp_priv) && (bsp_priv->phy_power_on)) {
1772 bsp_priv->phy_power_on(priv->plat, 0);
1780 * stmmac_xmit: Tx entry point of the driver
1781 * @skb : the socket buffer
1782 * @dev : device pointer
1783 * Description : this is the tx entry point of the driver.
1784 * It programs the chain or the ring and supports oversized frames
1787 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
1789 struct stmmac_priv *priv = netdev_priv(dev);
1790 unsigned int txsize = priv->dma_tx_size;
1792 int i, csum_insertion = 0, is_jumbo = 0;
1793 int nfrags = skb_shinfo(skb)->nr_frags;
1794 struct dma_desc *desc, *first;
1795 unsigned int nopaged_len = skb_headlen(skb);
1797 if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) {
1798 if (!netif_queue_stopped(dev)) {
1799 netif_stop_queue(dev);
1800 /* This is a hard error, log it. */
1801 pr_err("%s: Tx Ring full when queue awake\n", __func__);
1803 return NETDEV_TX_BUSY;
1806 spin_lock(&priv->tx_lock);
1808 if (priv->tx_path_in_lpi_mode)
1809 stmmac_disable_eee_mode(priv);
1811 entry = priv->cur_tx % txsize;
1813 #ifdef STMMAC_XMIT_DEBUG
1814 if ((skb->len > ETH_FRAME_LEN) || nfrags)
1815 pr_debug("%s: [entry %d]: skb addr %p len: %d nopagedlen: %d\n"
1816 "\tn_frags: %d - ip_summed: %d - %s gso\n"
1817 "\ttx_count_frames %d\n", __func__, entry,
1818 skb, skb->len, nopaged_len, nfrags, skb->ip_summed,
1819 !skb_is_gso(skb) ? "isn't" : "is",
1820 priv->tx_count_frames);
1823 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
1825 if (priv->extend_desc)
1826 desc = (struct dma_desc *)(priv->dma_etx + entry);
1828 desc = priv->dma_tx + entry;
1832 #ifdef STMMAC_XMIT_DEBUG
1833 if ((nfrags > 0) || (skb->len > ETH_FRAME_LEN))
1834 pr_debug("\tskb len: %d, nopaged_len: %d,\n"
1835 "\t\tn_frags: %d, ip_summed: %d\n",
1836 skb->len, nopaged_len, nfrags, skb->ip_summed);
1838 priv->tx_skbuff[entry] = skb;
1840 /* To program the descriptors according to the size of the frame */
1841 if (priv->mode == STMMAC_RING_MODE) {
1842 is_jumbo = priv->hw->ring->is_jumbo_frm(skb->len,
1843 priv->plat->enh_desc);
1844 if (unlikely(is_jumbo))
1845 entry = priv->hw->ring->jumbo_frm(priv, skb,
1848 is_jumbo = priv->hw->chain->is_jumbo_frm(skb->len,
1849 priv->plat->enh_desc);
1850 if (unlikely(is_jumbo))
1851 entry = priv->hw->chain->jumbo_frm(priv, skb,
1854 if (likely(!is_jumbo)) {
1855 desc->des2 = dma_map_single(priv->device, skb->data,
1856 nopaged_len, DMA_TO_DEVICE);
1857 priv->tx_skbuff_dma[entry] = desc->des2;
1858 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len,
1859 csum_insertion, priv->mode);
1863 for (i = 0; i < nfrags; i++) {
1864 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1865 int len = skb_frag_size(frag);
1867 entry = (++priv->cur_tx) % txsize;
1868 if (priv->extend_desc)
1869 desc = (struct dma_desc *)(priv->dma_etx + entry);
1871 desc = priv->dma_tx + entry;
1873 TX_DBG("\t[entry %d] segment len: %d\n", entry, len);
1874 desc->des2 = skb_frag_dma_map(priv->device, frag, 0, len,
1876 priv->tx_skbuff_dma[entry] = desc->des2;
1877 priv->tx_skbuff[entry] = NULL;
1878 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion,
1881 priv->hw->desc->set_tx_owner(desc);
1885 /* Finalize the latest segment. */
1886 priv->hw->desc->close_tx_desc(desc);
1889 /* According to the coalesce parameter the IC bit for the latest
1890 * segment could be reset and the timer re-started to invoke the
1891 * stmmac_tx function. This approach takes care about the fragments.
1893 priv->tx_count_frames += nfrags + 1;
1894 if (priv->tx_coal_frames > priv->tx_count_frames) {
1895 priv->hw->desc->clear_tx_ic(desc);
1896 priv->xstats.tx_reset_ic_bit++;
1897 TX_DBG("\t[entry %d]: tx_count_frames %d\n", entry,
1898 priv->tx_count_frames);
1899 mod_timer(&priv->txtimer,
1900 STMMAC_COAL_TIMER(priv->tx_coal_timer));
1902 priv->tx_count_frames = 0;
1904 /* To avoid raise condition */
1905 priv->hw->desc->set_tx_owner(first);
1910 #ifdef STMMAC_XMIT_DEBUG
1911 if (netif_msg_pktdata(priv)) {
1912 pr_info("%s: curr %d dirty=%d entry=%d, first=%p, nfrags=%d",
1913 __func__, (priv->cur_tx % txsize),
1914 (priv->dirty_tx % txsize), entry, first, nfrags);
1915 if (priv->extend_desc)
1916 stmmac_display_ring((void *)priv->dma_etx, txsize, 1);
1918 stmmac_display_ring((void *)priv->dma_tx, txsize, 0);
1920 pr_info(">>> frame to be transmitted: ");
1921 print_pkt(skb->data, skb->len);
1924 if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
1925 TX_DBG("%s: stop transmitted packets\n", __func__);
1926 netif_stop_queue(dev);
1929 dev->stats.tx_bytes += skb->len;
1931 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
1932 priv->hwts_tx_en)) {
1933 /* declare that device is doing timestamping */
1934 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1935 priv->hw->desc->enable_tx_timestamp(first);
1938 if (!priv->hwts_tx_en)
1939 skb_tx_timestamp(skb);
1941 priv->hw->dma->enable_dma_transmission(priv->ioaddr);
1943 spin_unlock(&priv->tx_lock);
1945 return NETDEV_TX_OK;
1949 * stmmac_rx_refill: refill used skb preallocated buffers
1950 * @priv: driver private structure
1951 * Description : this is to reallocate the skb for the reception process
1952 * that is based on zero-copy.
1954 static inline void stmmac_rx_refill(struct stmmac_priv *priv)
1956 unsigned int rxsize = priv->dma_rx_size;
1957 int bfsize = priv->dma_buf_sz;
1959 for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) {
1960 unsigned int entry = priv->dirty_rx % rxsize;
1963 if (priv->extend_desc)
1964 p = (struct dma_desc *)(priv->dma_erx + entry);
1966 p = priv->dma_rx + entry;
1968 if (likely(priv->rx_skbuff[entry] == NULL)) {
1969 struct sk_buff *skb;
1971 skb = netdev_alloc_skb_ip_align(priv->dev, bfsize);
1973 if (unlikely(skb == NULL))
1976 priv->rx_skbuff[entry] = skb;
1977 priv->rx_skbuff_dma[entry] =
1978 dma_map_single(priv->device, skb->data, bfsize,
1981 p->des2 = priv->rx_skbuff_dma[entry];
1983 priv->hw->ring->refill_desc3(priv, p);
1985 RX_DBG(KERN_INFO "\trefill entry #%d\n", entry);
1988 priv->hw->desc->set_rx_owner(p);
1994 * stmmac_rx_refill: refill used skb preallocated buffers
1995 * @priv: driver private structure
1996 * @limit: napi bugget.
1997 * Description : this the function called by the napi poll method.
1998 * It gets all the frames inside the ring.
2000 static int stmmac_rx(struct stmmac_priv *priv, int limit)
2002 unsigned int rxsize = priv->dma_rx_size;
2003 unsigned int entry = priv->cur_rx % rxsize;
2004 unsigned int next_entry;
2005 unsigned int count = 0;
2006 int coe = priv->plat->rx_coe;
2008 #ifdef STMMAC_RX_DEBUG
2009 if (netif_msg_hw(priv)) {
2010 pr_debug(">>> stmmac_rx: descriptor ring:\n");
2011 if (priv->extend_desc)
2012 stmmac_display_ring((void *)priv->dma_erx, rxsize, 1);
2014 stmmac_display_ring((void *)priv->dma_rx, rxsize, 0);
2017 while (count < limit) {
2021 if (priv->extend_desc)
2022 p = (struct dma_desc *)(priv->dma_erx + entry);
2024 p = priv->dma_rx + entry;
2026 if (priv->hw->desc->get_rx_owner(p))
2031 next_entry = (++priv->cur_rx) % rxsize;
2032 if (priv->extend_desc)
2033 prefetch(priv->dma_erx + next_entry);
2035 prefetch(priv->dma_rx + next_entry);
2037 /* read the status of the incoming frame */
2038 status = priv->hw->desc->rx_status(&priv->dev->stats,
2040 if ((priv->extend_desc) && (priv->hw->desc->rx_extended_status))
2041 priv->hw->desc->rx_extended_status(&priv->dev->stats,
2045 if (unlikely(status == discard_frame)) {
2046 priv->dev->stats.rx_errors++;
2047 if (priv->hwts_rx_en && !priv->extend_desc) {
2048 /* DESC2 & DESC3 will be overwitten by device
2049 * with timestamp value, hence reinitialize
2050 * them in stmmac_rx_refill() function so that
2051 * device can reuse it.
2053 priv->rx_skbuff[entry] = NULL;
2054 dma_unmap_single(priv->device,
2055 priv->rx_skbuff_dma[entry],
2060 struct sk_buff *skb;
2063 frame_len = priv->hw->desc->get_rx_frame_len(p, coe);
2065 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
2066 * Type frames (LLC/LLC-SNAP)
2068 if (unlikely(status != llc_snap))
2069 frame_len -= ETH_FCS_LEN;
2070 #ifdef STMMAC_RX_DEBUG
2071 if (frame_len > ETH_FRAME_LEN)
2072 pr_debug("\tRX frame size %d, COE status: %d\n",
2075 if (netif_msg_hw(priv))
2076 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n",
2079 skb = priv->rx_skbuff[entry];
2080 if (unlikely(!skb)) {
2081 pr_err("%s: Inconsistent Rx descriptor chain\n",
2083 priv->dev->stats.rx_dropped++;
2086 prefetch(skb->data - NET_IP_ALIGN);
2087 priv->rx_skbuff[entry] = NULL;
2089 stmmac_get_rx_hwtstamp(priv, entry, skb);
2091 skb_put(skb, frame_len);
2092 dma_unmap_single(priv->device,
2093 priv->rx_skbuff_dma[entry],
2094 priv->dma_buf_sz, DMA_FROM_DEVICE);
2095 #ifdef STMMAC_RX_DEBUG
2096 if (netif_msg_pktdata(priv)) {
2097 pr_info(" frame received (%dbytes)", frame_len);
2098 print_pkt(skb->data, frame_len);
2101 skb->protocol = eth_type_trans(skb, priv->dev);
2104 skb_checksum_none_assert(skb);
2106 skb->ip_summed = CHECKSUM_UNNECESSARY;
2108 napi_gro_receive(&priv->napi, skb);
2110 priv->dev->stats.rx_packets++;
2111 priv->dev->stats.rx_bytes += frame_len;
2116 stmmac_rx_refill(priv);
2118 priv->xstats.rx_pkt_n += count;
2124 * stmmac_poll - stmmac poll method (NAPI)
2125 * @napi : pointer to the napi structure.
2126 * @budget : maximum number of packets that the current CPU can receive from
2129 * To look at the incoming frames and clear the tx resources.
2131 static int stmmac_poll(struct napi_struct *napi, int budget)
2133 struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi);
2136 priv->xstats.napi_poll++;
2137 stmmac_tx_clean(priv);
2139 work_done = stmmac_rx(priv, budget);
2140 if (work_done < budget) {
2141 napi_complete(napi);
2142 stmmac_enable_dma_irq(priv);
2149 * @dev : Pointer to net device structure
2150 * Description: this function is called when a packet transmission fails to
2151 * complete within a reasonable time. The driver will mark the error in the
2152 * netdev structure and arrange for the device to be reset to a sane state
2153 * in order to transmit a new packet.
2155 static void stmmac_tx_timeout(struct net_device *dev)
2157 struct stmmac_priv *priv = netdev_priv(dev);
2159 /* Clear Tx resources and restart transmitting again */
2160 stmmac_tx_err(priv);
2163 /* Configuration changes (passed on by ifconfig) */
2164 static int stmmac_config(struct net_device *dev, struct ifmap *map)
2166 if (dev->flags & IFF_UP) /* can't act on a running interface */
2169 /* Don't allow changing the I/O address */
2170 if (map->base_addr != dev->base_addr) {
2171 pr_warn("%s: can't change I/O address\n", dev->name);
2175 /* Don't allow changing the IRQ */
2176 if (map->irq != dev->irq) {
2177 pr_warn("%s: not change IRQ number %d\n", dev->name, dev->irq);
2185 * stmmac_set_rx_mode - entry point for multicast addressing
2186 * @dev : pointer to the device structure
2188 * This function is a driver entry point which gets called by the kernel
2189 * whenever multicast addresses must be enabled/disabled.
2193 static void stmmac_set_rx_mode(struct net_device *dev)
2195 struct stmmac_priv *priv = netdev_priv(dev);
2197 spin_lock(&priv->lock);
2198 priv->hw->mac->set_filter(dev, priv->synopsys_id);
2199 spin_unlock(&priv->lock);
2203 * stmmac_change_mtu - entry point to change MTU size for the device.
2204 * @dev : device pointer.
2205 * @new_mtu : the new MTU size for the device.
2206 * Description: the Maximum Transfer Unit (MTU) is used by the network layer
2207 * to drive packet transmission. Ethernet has an MTU of 1500 octets
2208 * (ETH_DATA_LEN). This value can be changed with ifconfig.
2210 * 0 on success and an appropriate (-)ve integer as defined in errno.h
2213 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
2215 struct stmmac_priv *priv = netdev_priv(dev);
2218 if (netif_running(dev)) {
2219 pr_err("%s: must be stopped to change its MTU\n", dev->name);
2223 if (priv->plat->enh_desc)
2224 max_mtu = JUMBO_LEN;
2226 max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
2228 if ((new_mtu < 46) || (new_mtu > max_mtu)) {
2229 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu);
2234 netdev_update_features(dev);
2239 static netdev_features_t stmmac_fix_features(struct net_device *dev,
2240 netdev_features_t features)
2242 struct stmmac_priv *priv = netdev_priv(dev);
2244 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
2245 features &= ~NETIF_F_RXCSUM;
2246 else if (priv->plat->rx_coe == STMMAC_RX_COE_TYPE1)
2247 features &= ~NETIF_F_IPV6_CSUM;
2248 if (!priv->plat->tx_coe)
2249 features &= ~NETIF_F_ALL_CSUM;
2251 /* Some GMAC devices have a bugged Jumbo frame support that
2252 * needs to have the Tx COE disabled for oversized frames
2253 * (due to limited buffer sizes). In this case we disable
2254 * the TX csum insertionin the TDES and not use SF.
2256 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
2257 features &= ~NETIF_F_ALL_CSUM;
2263 * stmmac_interrupt - main ISR
2264 * @irq: interrupt number.
2265 * @dev_id: to pass the net device pointer.
2266 * Description: this is the main driver interrupt service routine.
2267 * It calls the DMA ISR and also the core ISR to manage PMT, MMC, LPI
2270 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
2272 struct net_device *dev = (struct net_device *)dev_id;
2273 struct stmmac_priv *priv = netdev_priv(dev);
2275 if (unlikely(!dev)) {
2276 pr_err("%s: invalid dev pointer\n", __func__);
2280 /* To handle GMAC own interrupts */
2281 if (priv->plat->has_gmac) {
2282 int status = priv->hw->mac->host_irq_status((void __iomem *)
2285 if (unlikely(status)) {
2286 /* For LPI we need to save the tx status */
2287 if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
2288 priv->tx_path_in_lpi_mode = true;
2289 if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
2290 priv->tx_path_in_lpi_mode = false;
2294 /* To handle DMA interrupts */
2295 stmmac_dma_interrupt(priv);
2300 #ifdef CONFIG_NET_POLL_CONTROLLER
2301 /* Polling receive - used by NETCONSOLE and other diagnostic tools
2302 * to allow network I/O with interrupts disabled.
2304 static void stmmac_poll_controller(struct net_device *dev)
2306 disable_irq(dev->irq);
2307 stmmac_interrupt(dev->irq, dev);
2308 enable_irq(dev->irq);
2313 * stmmac_ioctl - Entry point for the Ioctl
2314 * @dev: Device pointer.
2315 * @rq: An IOCTL specefic structure, that can contain a pointer to
2316 * a proprietary structure used to pass information to the driver.
2317 * @cmd: IOCTL command
2319 * Currently it supports the phy_mii_ioctl(...) and HW time stamping.
2321 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2323 struct stmmac_priv *priv = netdev_priv(dev);
2324 int ret = -EOPNOTSUPP;
2326 if (!netif_running(dev))
2335 ret = phy_mii_ioctl(priv->phydev, rq, cmd);
2338 ret = stmmac_hwtstamp_ioctl(dev, rq);
2347 #ifdef CONFIG_GMAC_DEBUG_FS
2348 static struct dentry *stmmac_fs_dir;
2349 static struct dentry *stmmac_rings_status;
2350 static struct dentry *stmmac_dma_cap;
2352 static void sysfs_display_ring(void *head, int size, int extend_desc,
2353 struct seq_file *seq)
2356 struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
2357 struct dma_desc *p = (struct dma_desc *)head;
2359 for (i = 0; i < size; i++) {
2363 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2364 i, (unsigned int)virt_to_phys(ep),
2365 (unsigned int)x, (unsigned int)(x >> 32),
2366 ep->basic.des2, ep->basic.des3);
2370 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2371 i, (unsigned int)virt_to_phys(ep),
2372 (unsigned int)x, (unsigned int)(x >> 32),
2376 seq_printf(seq, "\n");
2380 static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v)
2382 struct net_device *dev = seq->private;
2383 struct stmmac_priv *priv = netdev_priv(dev);
2384 unsigned int txsize = priv->dma_tx_size;
2385 unsigned int rxsize = priv->dma_rx_size;
2387 if (priv->extend_desc) {
2388 seq_printf(seq, "Extended RX descriptor ring:\n");
2389 sysfs_display_ring((void *)priv->dma_erx, rxsize, 1, seq);
2390 seq_printf(seq, "Extended TX descriptor ring:\n");
2391 sysfs_display_ring((void *)priv->dma_etx, txsize, 1, seq);
2393 seq_printf(seq, "RX descriptor ring:\n");
2394 sysfs_display_ring((void *)priv->dma_rx, rxsize, 0, seq);
2395 seq_printf(seq, "TX descriptor ring:\n");
2396 sysfs_display_ring((void *)priv->dma_tx, txsize, 0, seq);
2402 static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file)
2404 return single_open(file, stmmac_sysfs_ring_read, inode->i_private);
2407 static const struct file_operations stmmac_rings_status_fops = {
2408 .owner = THIS_MODULE,
2409 .open = stmmac_sysfs_ring_open,
2411 .llseek = seq_lseek,
2412 .release = single_release,
2415 static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v)
2417 struct net_device *dev = seq->private;
2418 struct stmmac_priv *priv = netdev_priv(dev);
2420 if (!priv->hw_cap_support) {
2421 seq_printf(seq, "DMA HW features not supported\n");
2425 seq_printf(seq, "==============================\n");
2426 seq_printf(seq, "\tDMA HW features\n");
2427 seq_printf(seq, "==============================\n");
2429 seq_printf(seq, "\t10/100 Mbps %s\n",
2430 (priv->dma_cap.mbps_10_100) ? "Y" : "N");
2431 seq_printf(seq, "\t1000 Mbps %s\n",
2432 (priv->dma_cap.mbps_1000) ? "Y" : "N");
2433 seq_printf(seq, "\tHalf duple %s\n",
2434 (priv->dma_cap.half_duplex) ? "Y" : "N");
2435 seq_printf(seq, "\tHash Filter: %s\n",
2436 (priv->dma_cap.hash_filter) ? "Y" : "N");
2437 seq_printf(seq, "\tMultiple MAC address registers: %s\n",
2438 (priv->dma_cap.multi_addr) ? "Y" : "N");
2439 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n",
2440 (priv->dma_cap.pcs) ? "Y" : "N");
2441 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
2442 (priv->dma_cap.sma_mdio) ? "Y" : "N");
2443 seq_printf(seq, "\tPMT Remote wake up: %s\n",
2444 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
2445 seq_printf(seq, "\tPMT Magic Frame: %s\n",
2446 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
2447 seq_printf(seq, "\tRMON module: %s\n",
2448 (priv->dma_cap.rmon) ? "Y" : "N");
2449 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
2450 (priv->dma_cap.time_stamp) ? "Y" : "N");
2451 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n",
2452 (priv->dma_cap.atime_stamp) ? "Y" : "N");
2453 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n",
2454 (priv->dma_cap.eee) ? "Y" : "N");
2455 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
2456 seq_printf(seq, "\tChecksum Offload in TX: %s\n",
2457 (priv->dma_cap.tx_coe) ? "Y" : "N");
2458 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
2459 (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
2460 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
2461 (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
2462 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
2463 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
2464 seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
2465 priv->dma_cap.number_rx_channel);
2466 seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
2467 priv->dma_cap.number_tx_channel);
2468 seq_printf(seq, "\tEnhanced descriptors: %s\n",
2469 (priv->dma_cap.enh_desc) ? "Y" : "N");
2474 static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file)
2476 return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private);
2479 static const struct file_operations stmmac_dma_cap_fops = {
2480 .owner = THIS_MODULE,
2481 .open = stmmac_sysfs_dma_cap_open,
2483 .llseek = seq_lseek,
2484 .release = single_release,
2487 static int stmmac_init_fs(struct net_device *dev)
2489 /* Create debugfs entries */
2490 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
2492 if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
2493 pr_err("ERROR %s, debugfs create directory failed\n",
2494 STMMAC_RESOURCE_NAME);
2499 /* Entry to report DMA RX/TX rings */
2500 stmmac_rings_status = debugfs_create_file("descriptors_status",
2501 S_IRUGO, stmmac_fs_dir, dev,
2502 &stmmac_rings_status_fops);
2504 if (!stmmac_rings_status || IS_ERR(stmmac_rings_status)) {
2505 pr_info("ERROR creating stmmac ring debugfs file\n");
2506 debugfs_remove(stmmac_fs_dir);
2511 /* Entry to report the DMA HW features */
2512 stmmac_dma_cap = debugfs_create_file("dma_cap", S_IRUGO, stmmac_fs_dir,
2513 dev, &stmmac_dma_cap_fops);
2515 if (!stmmac_dma_cap || IS_ERR(stmmac_dma_cap)) {
2516 pr_info("ERROR creating stmmac MMC debugfs file\n");
2517 debugfs_remove(stmmac_rings_status);
2518 debugfs_remove(stmmac_fs_dir);
2526 static void stmmac_exit_fs(void)
2528 debugfs_remove(stmmac_rings_status);
2529 debugfs_remove(stmmac_dma_cap);
2530 debugfs_remove(stmmac_fs_dir);
2532 #endif /* CONFIG_GMAC_DEBUG_FS */
2534 static const struct net_device_ops stmmac_netdev_ops = {
2535 .ndo_open = stmmac_open,
2536 .ndo_start_xmit = stmmac_xmit,
2537 .ndo_stop = stmmac_release,
2538 .ndo_change_mtu = stmmac_change_mtu,
2539 .ndo_fix_features = stmmac_fix_features,
2540 .ndo_set_rx_mode = stmmac_set_rx_mode,
2541 .ndo_tx_timeout = stmmac_tx_timeout,
2542 .ndo_do_ioctl = stmmac_ioctl,
2543 .ndo_set_config = stmmac_config,
2544 #ifdef CONFIG_NET_POLL_CONTROLLER
2545 .ndo_poll_controller = stmmac_poll_controller,
2547 .ndo_set_mac_address = eth_mac_addr,
2551 * stmmac_hw_init - Init the MAC device
2552 * @priv: driver private structure
2553 * Description: this function detects which MAC device
2554 * (GMAC/MAC10-100) has to attached, checks the HW capability
2555 * (if supported) and sets the driver's features (for example
2556 * to use the ring or chaine mode or support the normal/enh
2557 * descriptor structure).
2559 static int stmmac_hw_init(struct stmmac_priv *priv)
2562 struct mac_device_info *mac;
2564 /* Identify the MAC HW device */
2565 if (priv->plat->has_gmac) {
2566 priv->dev->priv_flags |= IFF_UNICAST_FLT;
2567 mac = dwmac1000_setup(priv->ioaddr);
2569 mac = dwmac100_setup(priv->ioaddr);
2576 /* Get and dump the chip ID */
2577 priv->synopsys_id = stmmac_get_synopsys_id(priv);
2579 /* To use alternate (extended) or normal descriptor structures */
2580 stmmac_selec_desc_mode(priv);
2582 /* To use the chained or ring mode */
2584 priv->hw->chain = &chain_mode_ops;
2585 pr_info(" Chain mode enabled\n");
2586 priv->mode = STMMAC_CHAIN_MODE;
2588 priv->hw->ring = &ring_mode_ops;
2589 pr_info(" Ring mode enabled\n");
2590 priv->mode = STMMAC_RING_MODE;
2593 /* Get the HW capability (new GMAC newer than 3.50a) */
2594 priv->hw_cap_support = stmmac_get_hw_features(priv);
2595 if (priv->hw_cap_support) {
2596 pr_info(" DMA HW capability register supported");
2598 /* We can override some gmac/dma configuration fields: e.g.
2599 * enh_desc, tx_coe (e.g. that are passed through the
2600 * platform) with the values from the HW capability
2601 * register (if supported).
2603 priv->plat->enh_desc = priv->dma_cap.enh_desc;
2604 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
2606 priv->plat->tx_coe = priv->dma_cap.tx_coe;
2608 if (priv->dma_cap.rx_coe_type2)
2609 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
2610 else if (priv->dma_cap.rx_coe_type1)
2611 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
2614 pr_info(" No HW DMA feature register supported");
2616 ret = priv->hw->mac->rx_ipc(priv->ioaddr);
2618 pr_warn(" RX IPC Checksum Offload not configured.\n");
2619 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
2622 if (priv->plat->rx_coe)
2623 pr_info(" RX Checksum Offload Engine supported (type %d)\n",
2624 priv->plat->rx_coe);
2625 if (priv->plat->tx_coe)
2626 pr_info(" TX Checksum insertion supported\n");
2628 if (priv->plat->pmt) {
2629 pr_info(" Wake-Up On Lan supported\n");
2630 device_set_wakeup_capable(priv->device, 1);
2638 * @device: device pointer
2639 * @plat_dat: platform data pointer
2640 * @addr: iobase memory address
2641 * Description: this is the main probe function used to
2642 * call the alloc_etherdev, allocate the priv structure.
2644 struct stmmac_priv *stmmac_dvr_probe(struct device *device,
2645 struct plat_stmmacenet_data *plat_dat,
2649 struct net_device *ndev = NULL;
2650 struct stmmac_priv *priv;
2652 ndev = alloc_etherdev(sizeof(struct stmmac_priv));
2656 SET_NETDEV_DEV(ndev, device);
2658 priv = netdev_priv(ndev);
2659 priv->device = device;
2664 stmmac_set_ethtool_ops(ndev);
2665 priv->pause = pause;
2666 priv->plat = plat_dat;
2667 priv->ioaddr = addr;
2668 priv->dev->base_addr = (unsigned long)addr;
2670 /* Verify driver arguments */
2671 stmmac_verify_args();
2673 /* Override with kernel parameters if supplied XXX CRS XXX
2674 * this needs to have multiple instances
2676 if ((phyaddr >= 0) && (phyaddr <= 31))
2677 priv->plat->phy_addr = phyaddr;
2679 /* Init MAC and get the capabilities */
2680 ret = stmmac_hw_init(priv);
2682 goto error_free_netdev;
2684 ndev->netdev_ops = &stmmac_netdev_ops;
2686 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2688 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
2689 ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
2690 #ifdef STMMAC_VLAN_TAG_USED
2691 /* Both mac100 and gmac support receive VLAN tag detection */
2692 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
2694 priv->msg_enable = netif_msg_init(debug, default_msg_level);
2697 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */
2699 /* Rx Watchdog is available in the COREs newer than the 3.40.
2700 * In some case, for example on bugged HW this feature
2701 * has to be disable and this can be done by passing the
2702 * riwt_off field from the platform.
2704 if ((priv->synopsys_id >= DWMAC_CORE_3_50) && (!priv->plat->riwt_off)) {
2706 pr_info(" Enable RX Mitigation via HW Watchdog Timer\n");
2709 netif_napi_add(ndev, &priv->napi, stmmac_poll, 64);
2711 spin_lock_init(&priv->lock);
2712 spin_lock_init(&priv->tx_lock);
2714 ret = register_netdev(ndev);
2716 pr_err("%s: ERROR %i registering the device\n", __func__, ret);
2717 goto error_netdev_register;
2720 priv->stmmac_clk = clk_get(priv->device, "clk_mac"/*STMMAC_RESOURCE_NAME*/);
2721 if (IS_ERR(priv->stmmac_clk)) {
2722 pr_warn("%s: warning: cannot get CSR clock\n", __func__);
2726 /* If a specific clk_csr value is passed from the platform
2727 * this means that the CSR Clock Range selection cannot be
2728 * changed at run-time and it is fixed. Viceversa the driver'll try to
2729 * set the MDC clock dynamically according to the csr actual
2732 if (!priv->plat->clk_csr)
2733 stmmac_clk_csr_set(priv);
2735 priv->clk_csr = priv->plat->clk_csr;
2737 stmmac_check_pcs_mode(priv);
2739 if (priv->pcs != STMMAC_PCS_SGMII && priv->pcs != STMMAC_PCS_TBI &&
2740 priv->pcs != STMMAC_PCS_RTBI) {
2741 /* MDIO bus Registration */
2742 ret = stmmac_mdio_register(ndev);
2744 pr_debug("%s: MDIO bus (id: %d) registration failed",
2745 __func__, priv->plat->bus_id);
2746 goto error_mdio_register;
2752 error_mdio_register:
2753 clk_put(priv->stmmac_clk);
2755 unregister_netdev(ndev);
2756 error_netdev_register:
2757 netif_napi_del(&priv->napi);
2766 * @ndev: net device pointer
2767 * Description: this function resets the TX/RX processes, disables the MAC RX/TX
2768 * changes the link status, releases the DMA descriptor rings.
2770 int stmmac_dvr_remove(struct net_device *ndev)
2772 struct stmmac_priv *priv = netdev_priv(ndev);
2774 pr_info("%s:\n\tremoving driver", __func__);
2776 priv->hw->dma->stop_rx(priv->ioaddr);
2777 priv->hw->dma->stop_tx(priv->ioaddr);
2779 stmmac_set_mac(priv->ioaddr, false);
2780 if (priv->pcs != STMMAC_PCS_SGMII && priv->pcs != STMMAC_PCS_TBI &&
2781 priv->pcs != STMMAC_PCS_RTBI)
2782 stmmac_mdio_unregister(ndev);
2783 netif_carrier_off(ndev);
2784 unregister_netdev(ndev);
2791 int stmmac_suspend(struct net_device *ndev)
2793 struct stmmac_priv *priv = netdev_priv(ndev);
2794 unsigned long flags;
2796 if (!ndev || !netif_running(ndev))
2800 phy_stop(priv->phydev);
2802 spin_lock_irqsave(&priv->lock, flags);
2804 netif_device_detach(ndev);
2805 netif_stop_queue(ndev);
2807 napi_disable(&priv->napi);
2809 /* Stop TX/RX DMA */
2810 priv->hw->dma->stop_tx(priv->ioaddr);
2811 priv->hw->dma->stop_rx(priv->ioaddr);
2813 stmmac_clear_descriptors(priv);
2815 /* Enable Power down mode by programming the PMT regs */
2816 if (device_may_wakeup(priv->device))
2817 priv->hw->mac->pmt(priv->ioaddr, priv->wolopts);
2819 stmmac_set_mac(priv->ioaddr, false);
2820 /* Disable clock in case of PWM is off */
2821 clk_disable_unprepare(priv->stmmac_clk);
2823 spin_unlock_irqrestore(&priv->lock, flags);
2827 int stmmac_resume(struct net_device *ndev)
2829 struct stmmac_priv *priv = netdev_priv(ndev);
2830 unsigned long flags;
2832 if (!netif_running(ndev))
2835 spin_lock_irqsave(&priv->lock, flags);
2837 /* Power Down bit, into the PM register, is cleared
2838 * automatically as soon as a magic packet or a Wake-up frame
2839 * is received. Anyway, it's better to manually clear
2840 * this bit because it can generate problems while resuming
2841 * from another devices (e.g. serial console).
2843 if (device_may_wakeup(priv->device))
2844 priv->hw->mac->pmt(priv->ioaddr, 0);
2846 /* enable the clk prevously disabled */
2847 clk_prepare_enable(priv->stmmac_clk);
2849 netif_device_attach(ndev);
2851 /* Enable the MAC and DMA */
2852 stmmac_set_mac(priv->ioaddr, true);
2853 priv->hw->dma->start_tx(priv->ioaddr);
2854 priv->hw->dma->start_rx(priv->ioaddr);
2856 napi_enable(&priv->napi);
2858 netif_start_queue(ndev);
2860 spin_unlock_irqrestore(&priv->lock, flags);
2863 phy_start(priv->phydev);
2868 int stmmac_freeze(struct net_device *ndev)
2870 if (!ndev || !netif_running(ndev))
2873 return stmmac_release(ndev);
2876 int stmmac_restore(struct net_device *ndev)
2878 if (!ndev || !netif_running(ndev))
2881 return stmmac_open(ndev);
2883 #endif /* CONFIG_PM */
2885 /* Driver can be configured w/ and w/ both PCI and Platf drivers
2886 * depending on the configuration selected.
2888 static int __init stmmac_init(void)
2892 ret = stmmac_register_platform();
2895 ret = stmmac_register_pci();
2900 stmmac_unregister_platform();
2902 pr_err("stmmac: driver registration failed\n");
2906 static void __exit stmmac_exit(void)
2908 stmmac_unregister_platform();
2909 stmmac_unregister_pci();
2912 module_init(stmmac_init);
2913 module_exit(stmmac_exit);
2916 static int __init stmmac_cmdline_opt(char *str)
2922 while ((opt = strsep(&str, ",")) != NULL) {
2923 if (!strncmp(opt, "debug:", 6)) {
2924 if (kstrtoint(opt + 6, 0, &debug))
2926 } else if (!strncmp(opt, "phyaddr:", 8)) {
2927 if (kstrtoint(opt + 8, 0, &phyaddr))
2929 } else if (!strncmp(opt, "dma_txsize:", 11)) {
2930 if (kstrtoint(opt + 11, 0, &dma_txsize))
2932 } else if (!strncmp(opt, "dma_rxsize:", 11)) {
2933 if (kstrtoint(opt + 11, 0, &dma_rxsize))
2935 } else if (!strncmp(opt, "buf_sz:", 7)) {
2936 if (kstrtoint(opt + 7, 0, &buf_sz))
2938 } else if (!strncmp(opt, "tc:", 3)) {
2939 if (kstrtoint(opt + 3, 0, &tc))
2941 } else if (!strncmp(opt, "watchdog:", 9)) {
2942 if (kstrtoint(opt + 9, 0, &watchdog))
2944 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
2945 if (kstrtoint(opt + 10, 0, &flow_ctrl))
2947 } else if (!strncmp(opt, "pause:", 6)) {
2948 if (kstrtoint(opt + 6, 0, &pause))
2950 } else if (!strncmp(opt, "eee_timer:", 10)) {
2951 if (kstrtoint(opt + 10, 0, &eee_timer))
2953 } else if (!strncmp(opt, "chain_mode:", 11)) {
2954 if (kstrtoint(opt + 11, 0, &chain_mode))
2961 pr_err("%s: ERROR broken module parameter conversion", __func__);
2965 __setup("stmmaceth=", stmmac_cmdline_opt);
2968 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
2969 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
2970 MODULE_LICENSE("GPL");