2 * SuperH Ethernet device driver
4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
5 * Copyright (C) 2008-2012 Renesas Solutions Corp.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 * The full GNU General Public License is included in this distribution in
20 * the file called "COPYING".
26 #define CARDNAME "sh-eth"
27 #define TX_TIMEOUT (5*HZ)
28 #define TX_RING_SIZE 64 /* Tx ring size */
29 #define RX_RING_SIZE 64 /* Rx ring size */
30 #define TX_RING_MIN 64
31 #define RX_RING_MIN 64
32 #define TX_RING_MAX 1024
33 #define RX_RING_MAX 1024
35 #define PKT_BUF_SZ 1538
36 #define SH_ETH_TSU_TIMEOUT_MS 500
37 #define SH_ETH_TSU_CAM_ENTRIES 32
40 /* E-DMAC registers */
109 /* TSU Absolute address */
156 /* This value must be written at last. */
157 SH_ETH_MAX_REGISTER_OFFSET,
162 SH_ETH_REG_FAST_RCAR,
164 SH_ETH_REG_FAST_SH3_SH2
167 /* Driver's parameters */
168 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
169 #define SH4_SKB_RX_ALIGN 32
171 #define SH2_SH3_SKB_RX_ALIGN 2
177 /* EDSR : sh7734, sh7757, sh7763, and r8a7740 only */
179 EDSR_ENT = 0x01, EDSR_ENR = 0x02,
181 #define EDSR_ENALL (EDSR_ENT|EDSR_ENR)
183 /* GECMR : sh7734, sh7763 and r8a7740 only */
185 GECMR_10 = 0x0, GECMR_100 = 0x04, GECMR_1000 = 0x01,
190 EDMR_EL = 0x40, /* Litte endian */
191 EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
192 EDMR_SRST_GETHER = 0x03,
193 EDMR_SRST_ETHER = 0x01,
198 EDTRR_TRNS_GETHER = 0x03,
199 EDTRR_TRNS_ETHER = 0x01,
209 TPAUSER_TPAUSE = 0x0000ffff,
210 TPAUSER_UNLIMITED = 0,
215 BCFR_RPAUSE = 0x0000ffff,
221 PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01,
225 enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, };
229 EESR_TWB1 = 0x80000000,
230 EESR_TWB = 0x40000000, /* same as TWB0 */
231 EESR_TC1 = 0x20000000,
232 EESR_TUC = 0x10000000,
233 EESR_ROC = 0x08000000,
234 EESR_TABT = 0x04000000,
235 EESR_RABT = 0x02000000,
236 EESR_RFRMER = 0x01000000, /* same as RFCOF */
237 EESR_ADE = 0x00800000,
238 EESR_ECI = 0x00400000,
239 EESR_FTC = 0x00200000, /* same as TC or TC0 */
240 EESR_TDE = 0x00100000,
241 EESR_TFE = 0x00080000, /* same as TFUF */
242 EESR_FRC = 0x00040000, /* same as FR */
243 EESR_RDE = 0x00020000,
244 EESR_RFE = 0x00010000,
245 EESR_CND = 0x00000800,
246 EESR_DLC = 0x00000400,
247 EESR_CD = 0x00000200,
248 EESR_RTO = 0x00000100,
249 EESR_RMAF = 0x00000080,
250 EESR_CEEF = 0x00000040,
251 EESR_CELF = 0x00000020,
252 EESR_RRF = 0x00000010,
253 EESR_RTLF = 0x00000008,
254 EESR_RTSF = 0x00000004,
255 EESR_PRE = 0x00000002,
256 EESR_CERF = 0x00000001,
259 #define EESR_RX_CHECK (EESR_FRC | /* Frame recv */ \
260 EESR_RMAF | /* Multicast address recv */ \
261 EESR_RRF | /* Bit frame recv */ \
262 EESR_RTLF | /* Long frame recv */ \
263 EESR_RTSF | /* Short frame recv */ \
264 EESR_PRE | /* PHY-LSI recv error */ \
265 EESR_CERF) /* Recv frame CRC error */
267 #define DEFAULT_TX_CHECK (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | \
269 #define DEFAULT_EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | \
270 EESR_RDE | EESR_RFRMER | EESR_ADE | \
271 EESR_TFE | EESR_TDE | EESR_ECI)
275 DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000,
276 DMAC_M_RABT = 0x02000000,
277 DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000,
278 DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000,
279 DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000,
280 DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000,
281 DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800,
282 DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200,
283 DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080,
284 DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008,
285 DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002,
286 DMAC_M_RINT1 = 0x00000001,
289 /* Receive descriptor bit */
291 RD_RACT = 0x80000000, RD_RDEL = 0x40000000,
292 RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000,
293 RD_RFE = 0x08000000, RD_RFS10 = 0x00000200,
294 RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080,
295 RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020,
296 RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008,
297 RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002,
298 RD_RFS1 = 0x00000001,
300 #define RDF1ST RD_RFP1
301 #define RDFEND RD_RFP0
302 #define RD_RFP (RD_RFP1|RD_RFP0)
306 FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000,
307 FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004,
308 FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001,
310 #define DEFAULT_FIFO_F_D_RFF (FCFTR_RFF2 | FCFTR_RFF1 | FCFTR_RFF0)
311 #define DEFAULT_FIFO_F_D_RFD (FCFTR_RFD2 | FCFTR_RFD1 | FCFTR_RFD0)
313 /* Transmit descriptor bit */
315 TD_TACT = 0x80000000, TD_TDLE = 0x40000000,
316 TD_TFP1 = 0x20000000, TD_TFP0 = 0x10000000,
317 TD_TFE = 0x08000000, TD_TWBI = 0x04000000,
319 #define TDF1ST TD_TFP1
320 #define TDFEND TD_TFP0
321 #define TD_TFP (TD_TFP1|TD_TFP0)
324 #define DEFAULT_RMCR_VALUE 0x00000000
327 enum FELIC_MODE_BIT {
328 ECMR_TRCCM = 0x04000000, ECMR_RCSC = 0x00800000,
329 ECMR_DPAD = 0x00200000, ECMR_RZPF = 0x00100000,
330 ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000,
331 ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000,
332 ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020,
333 ECMR_RTM = 0x00000010, ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004,
334 ECMR_DM = 0x00000002, ECMR_PRM = 0x00000001,
338 enum ECSR_STATUS_BIT {
339 ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10,
341 ECSR_MPD = 0x02, ECSR_ICD = 0x01,
344 #define DEFAULT_ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | ECSR_LCHNG | \
345 ECSR_ICD | ECSIPR_MPDIP)
348 enum ECSIPR_STATUS_MASK_BIT {
349 ECSIPR_BRCRXIP = 0x20, ECSIPR_PSRTOIP = 0x10,
350 ECSIPR_LCHNGIP = 0x04,
351 ECSIPR_MPDIP = 0x02, ECSIPR_ICDIP = 0x01,
354 #define DEFAULT_ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | \
355 ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP)
369 DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200,
370 DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010,
371 DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002,
372 DESC_I_RINT1 = 0x0001,
377 RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000,
378 RPADIR_PADR = 0x0003f,
382 #define DEFAULT_FDR_INIT 0x00000707
385 enum ARSTR_BIT { ARSTR_ARSTR = 0x00000001, };
389 TSU_FWEN0_0 = 0x00000001,
393 enum TSU_ADSBSY_BIT {
394 TSU_ADSBSY_0 = 0x00000001,
399 TSU_TEN_0 = 0x80000000,
404 TSU_FWSL0_FW50 = 0x1000, TSU_FWSL0_FW40 = 0x0800,
405 TSU_FWSL0_FW30 = 0x0400, TSU_FWSL0_FW20 = 0x0200,
406 TSU_FWSL0_FW10 = 0x0100, TSU_FWSL0_RMSA0 = 0x0010,
411 TSU_FWSLC_POSTENU = 0x2000, TSU_FWSLC_POSTENL = 0x1000,
412 TSU_FWSLC_CAMSEL03 = 0x0080, TSU_FWSLC_CAMSEL02 = 0x0040,
413 TSU_FWSLC_CAMSEL01 = 0x0020, TSU_FWSLC_CAMSEL00 = 0x0010,
414 TSU_FWSLC_CAMSEL13 = 0x0008, TSU_FWSLC_CAMSEL12 = 0x0004,
415 TSU_FWSLC_CAMSEL11 = 0x0002, TSU_FWSLC_CAMSEL10 = 0x0001,
419 #define TSU_VTAG_ENABLE 0x80000000
420 #define TSU_VTAG_VID_MASK 0x00000fff
423 * The sh ether Tx buffer descriptors.
424 * This structure should be 20 bytes.
426 struct sh_eth_txdesc {
427 u32 status; /* TD0 */
428 #if defined(__LITTLE_ENDIAN)
430 u16 buffer_length; /* TD1 */
432 u16 buffer_length; /* TD1 */
436 u32 pad1; /* padding data */
437 } __attribute__((aligned(2), packed));
440 * The sh ether Rx buffer descriptors.
441 * This structure should be 20 bytes.
443 struct sh_eth_rxdesc {
444 u32 status; /* RD0 */
445 #if defined(__LITTLE_ENDIAN)
446 u16 frame_length; /* RD1 */
447 u16 buffer_length; /* RD1 */
449 u16 buffer_length; /* RD1 */
450 u16 frame_length; /* RD1 */
453 u32 pad0; /* padding data */
454 } __attribute__((aligned(2), packed));
456 /* This structure is used by each CPU dependency handling. */
457 struct sh_eth_cpu_data {
458 /* optional functions */
459 void (*chip_reset)(struct net_device *ndev);
460 void (*set_duplex)(struct net_device *ndev);
461 void (*set_rate)(struct net_device *ndev);
463 /* mandatory initialize value */
465 unsigned long eesipr_value;
467 /* optional initialize value */
468 unsigned long ecsr_value;
469 unsigned long ecsipr_value;
470 unsigned long fdr_value;
471 unsigned long fcftr_value;
472 unsigned long rpadir_value;
473 unsigned long rmcr_value;
475 /* interrupt checking mask */
476 unsigned long tx_check;
477 unsigned long eesr_err_check;
479 /* hardware features */
480 unsigned long irq_flags; /* IRQ configuration flags */
481 unsigned no_psr:1; /* EtherC DO NOT have PSR */
482 unsigned apr:1; /* EtherC have APR */
483 unsigned mpr:1; /* EtherC have MPR */
484 unsigned tpauser:1; /* EtherC have TPAUSER */
485 unsigned bculr:1; /* EtherC have BCULR */
486 unsigned tsu:1; /* EtherC have TSU */
487 unsigned hw_swap:1; /* E-DMAC have DE bit in EDMR */
488 unsigned rpadir:1; /* E-DMAC have RPADIR */
489 unsigned no_trimd:1; /* E-DMAC DO NOT have TRIMD */
490 unsigned no_ade:1; /* E-DMAC DO NOT have ADE bit in EESR */
491 unsigned hw_crc:1; /* E-DMAC have CSMR */
492 unsigned select_mii:1; /* EtherC have RMII_MII (MII select register) */
493 unsigned shift_rd0:1; /* shift Rx descriptor word 0 right by 16 */
494 unsigned rmiimode:1; /* EtherC has RMIIMODE register */
497 struct sh_eth_private {
498 struct platform_device *pdev;
499 struct sh_eth_cpu_data *cd;
500 const u16 *reg_offset;
502 void __iomem *tsu_addr;
505 dma_addr_t rx_desc_dma;
506 dma_addr_t tx_desc_dma;
507 struct sh_eth_rxdesc *rx_ring;
508 struct sh_eth_txdesc *tx_ring;
509 struct sk_buff **rx_skbuff;
510 struct sk_buff **tx_skbuff;
512 u32 cur_rx, dirty_rx; /* Producer/consumer ring indices */
513 u32 cur_tx, dirty_tx;
514 u32 rx_buf_sz; /* Based on MTU+slack. */
516 struct napi_struct napi;
517 /* MII transceiver section. */
518 u32 phy_id; /* PHY ID */
519 struct mii_bus *mii_bus; /* MDIO bus control */
520 struct phy_device *phydev; /* PHY device control */
522 phy_interface_t phy_interface;
526 int port; /* for TSU */
527 int vlan_num_ids; /* for VLAN tag filter */
529 unsigned no_ether_link:1;
530 unsigned ether_link_active_low:1;
533 static inline void sh_eth_soft_swap(char *src, int len)
535 #ifdef __LITTLE_ENDIAN__
538 maxp = p + ((len + sizeof(u32) - 1) / sizeof(u32));
540 for (; p < maxp; p++)
545 static inline void sh_eth_write(struct net_device *ndev, unsigned long data,
548 struct sh_eth_private *mdp = netdev_priv(ndev);
550 iowrite32(data, mdp->addr + mdp->reg_offset[enum_index]);
553 static inline unsigned long sh_eth_read(struct net_device *ndev,
556 struct sh_eth_private *mdp = netdev_priv(ndev);
558 return ioread32(mdp->addr + mdp->reg_offset[enum_index]);
561 static inline void *sh_eth_tsu_get_offset(struct sh_eth_private *mdp,
564 return mdp->tsu_addr + mdp->reg_offset[enum_index];
567 static inline void sh_eth_tsu_write(struct sh_eth_private *mdp,
568 unsigned long data, int enum_index)
570 iowrite32(data, mdp->tsu_addr + mdp->reg_offset[enum_index]);
573 static inline unsigned long sh_eth_tsu_read(struct sh_eth_private *mdp,
576 return ioread32(mdp->tsu_addr + mdp->reg_offset[enum_index]);
579 #endif /* #ifndef __SH_ETH_H__ */