2 * SuperH Ethernet device driver
4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
5 * Copyright (C) 2008-2012 Renesas Solutions Corp.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 * The full GNU General Public License is included in this distribution in
20 * the file called "COPYING".
26 #define CARDNAME "sh-eth"
27 #define TX_TIMEOUT (5*HZ)
28 #define TX_RING_SIZE 64 /* Tx ring size */
29 #define RX_RING_SIZE 64 /* Rx ring size */
31 #define PKT_BUF_SZ 1538
32 #define SH_ETH_TSU_TIMEOUT_MS 500
33 #define SH_ETH_TSU_CAM_ENTRIES 32
36 /* E-DMAC registers */
104 /* TSU Absolute address */
151 /* This value must be written at last. */
152 SH_ETH_MAX_REGISTER_OFFSET,
155 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
209 [TSU_CTRST] = 0x0004,
210 [TSU_FWEN0] = 0x0010,
211 [TSU_FWEN1] = 0x0014,
213 [TSU_BSYSL0] = 0x0020,
214 [TSU_BSYSL1] = 0x0024,
215 [TSU_PRISL0] = 0x0028,
216 [TSU_PRISL1] = 0x002c,
217 [TSU_FWSL0] = 0x0030,
218 [TSU_FWSL1] = 0x0034,
219 [TSU_FWSLC] = 0x0038,
220 [TSU_QTAG0] = 0x0040,
221 [TSU_QTAG1] = 0x0044,
223 [TSU_FWINMK] = 0x0054,
224 [TSU_ADQT0] = 0x0048,
225 [TSU_ADQT1] = 0x004c,
226 [TSU_VTAG0] = 0x0058,
227 [TSU_VTAG1] = 0x005c,
228 [TSU_ADSBSY] = 0x0060,
230 [TSU_POST1] = 0x0070,
231 [TSU_POST2] = 0x0074,
232 [TSU_POST3] = 0x0078,
233 [TSU_POST4] = 0x007c,
234 [TSU_ADRH0] = 0x0100,
235 [TSU_ADRL0] = 0x0104,
236 [TSU_ADRH31] = 0x01f8,
237 [TSU_ADRL31] = 0x01fc,
253 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
305 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
331 [TSU_CTRST] = 0x0004,
332 [TSU_FWEN0] = 0x0010,
333 [TSU_FWEN1] = 0x0014,
335 [TSU_BSYSL0] = 0x0020,
336 [TSU_BSYSL1] = 0x0024,
337 [TSU_PRISL0] = 0x0028,
338 [TSU_PRISL1] = 0x002c,
339 [TSU_FWSL0] = 0x0030,
340 [TSU_FWSL1] = 0x0034,
341 [TSU_FWSLC] = 0x0038,
342 [TSU_QTAGM0] = 0x0040,
343 [TSU_QTAGM1] = 0x0044,
344 [TSU_ADQT0] = 0x0048,
345 [TSU_ADQT1] = 0x004c,
347 [TSU_FWINMK] = 0x0054,
348 [TSU_ADSBSY] = 0x0060,
350 [TSU_POST1] = 0x0070,
351 [TSU_POST2] = 0x0074,
352 [TSU_POST3] = 0x0078,
353 [TSU_POST4] = 0x007c,
368 [TSU_ADRH0] = 0x0100,
369 [TSU_ADRL0] = 0x0104,
370 [TSU_ADRL31] = 0x01fc,
374 /* Driver's parameters */
375 #if defined(CONFIG_CPU_SH4)
376 #define SH4_SKB_RX_ALIGN 32
378 #define SH2_SH3_SKB_RX_ALIGN 2
384 #if defined(CONFIG_CPU_SUBTYPE_SH7734) || defined(CONFIG_CPU_SUBTYPE_SH7763)
387 EDSR_ENT = 0x01, EDSR_ENR = 0x02,
389 #define EDSR_ENALL (EDSR_ENT|EDSR_ENR)
393 GECMR_10 = 0x0, GECMR_100 = 0x04, GECMR_1000 = 0x01,
399 EDMR_EL = 0x40, /* Litte endian */
400 EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
401 EDMR_SRST_GETHER = 0x03,
402 EDMR_SRST_ETHER = 0x01,
407 EDTRR_TRNS_GETHER = 0x03,
408 EDTRR_TRNS_ETHER = 0x01,
418 TPAUSER_TPAUSE = 0x0000ffff,
419 TPAUSER_UNLIMITED = 0,
424 BCFR_RPAUSE = 0x0000ffff,
430 PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01,
434 enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, };
438 EESR_TWB1 = 0x80000000,
439 EESR_TWB = 0x40000000, /* same as TWB0 */
440 EESR_TC1 = 0x20000000,
441 EESR_TUC = 0x10000000,
442 EESR_ROC = 0x08000000,
443 EESR_TABT = 0x04000000,
444 EESR_RABT = 0x02000000,
445 EESR_RFRMER = 0x01000000, /* same as RFCOF */
446 EESR_ADE = 0x00800000,
447 EESR_ECI = 0x00400000,
448 EESR_FTC = 0x00200000, /* same as TC or TC0 */
449 EESR_TDE = 0x00100000,
450 EESR_TFE = 0x00080000, /* same as TFUF */
451 EESR_FRC = 0x00040000, /* same as FR */
452 EESR_RDE = 0x00020000,
453 EESR_RFE = 0x00010000,
454 EESR_CND = 0x00000800,
455 EESR_DLC = 0x00000400,
456 EESR_CD = 0x00000200,
457 EESR_RTO = 0x00000100,
458 EESR_RMAF = 0x00000080,
459 EESR_CEEF = 0x00000040,
460 EESR_CELF = 0x00000020,
461 EESR_RRF = 0x00000010,
462 EESR_RTLF = 0x00000008,
463 EESR_RTSF = 0x00000004,
464 EESR_PRE = 0x00000002,
465 EESR_CERF = 0x00000001,
468 #define DEFAULT_TX_CHECK (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | \
470 #define DEFAULT_EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | \
471 EESR_RDE | EESR_RFRMER | EESR_ADE | \
472 EESR_TFE | EESR_TDE | EESR_ECI)
473 #define DEFAULT_TX_ERROR_CHECK (EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | \
478 DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000,
479 DMAC_M_RABT = 0x02000000,
480 DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000,
481 DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000,
482 DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000,
483 DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000,
484 DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800,
485 DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200,
486 DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080,
487 DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008,
488 DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002,
489 DMAC_M_RINT1 = 0x00000001,
492 /* Receive descriptor bit */
494 RD_RACT = 0x80000000, RD_RDEL = 0x40000000,
495 RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000,
496 RD_RFE = 0x08000000, RD_RFS10 = 0x00000200,
497 RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080,
498 RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020,
499 RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008,
500 RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002,
501 RD_RFS1 = 0x00000001,
503 #define RDF1ST RD_RFP1
504 #define RDFEND RD_RFP0
505 #define RD_RFP (RD_RFP1|RD_RFP0)
509 FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000,
510 FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004,
511 FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001,
513 #define DEFAULT_FIFO_F_D_RFF (FCFTR_RFF2 | FCFTR_RFF1 | FCFTR_RFF0)
514 #define DEFAULT_FIFO_F_D_RFD (FCFTR_RFD2 | FCFTR_RFD1 | FCFTR_RFD0)
516 /* Transfer descriptor bit */
518 TD_TACT = 0x80000000,
519 TD_TDLE = 0x40000000, TD_TFP1 = 0x20000000,
520 TD_TFP0 = 0x10000000,
522 #define TDF1ST TD_TFP1
523 #define TDFEND TD_TFP0
524 #define TD_TFP (TD_TFP1|TD_TFP0)
527 #define DEFAULT_RMCR_VALUE 0x00000000
530 enum FELIC_MODE_BIT {
531 ECMR_TRCCM = 0x04000000, ECMR_RCSC = 0x00800000,
532 ECMR_DPAD = 0x00200000, ECMR_RZPF = 0x00100000,
533 ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000,
534 ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000,
535 ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020,
536 ECMR_RTM = 0x00000010, ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004,
537 ECMR_DM = 0x00000002, ECMR_PRM = 0x00000001,
541 enum ECSR_STATUS_BIT {
542 ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10,
544 ECSR_MPD = 0x02, ECSR_ICD = 0x01,
547 #define DEFAULT_ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | ECSR_LCHNG | \
548 ECSR_ICD | ECSIPR_MPDIP)
551 enum ECSIPR_STATUS_MASK_BIT {
552 ECSIPR_BRCRXIP = 0x20, ECSIPR_PSRTOIP = 0x10,
553 ECSIPR_LCHNGIP = 0x04,
554 ECSIPR_MPDIP = 0x02, ECSIPR_ICDIP = 0x01,
557 #define DEFAULT_ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | \
558 ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP)
572 DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200,
573 DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010,
574 DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002,
575 DESC_I_RINT1 = 0x0001,
580 RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000,
581 RPADIR_PADR = 0x0003f,
585 #define DEFAULT_FDR_INIT 0x00000707
588 PHY_CTRL = 0, PHY_STAT = 1, PHY_IDT1 = 2, PHY_IDT2 = 3,
589 PHY_ANA = 4, PHY_ANL = 5, PHY_ANE = 6,
595 PHY_C_RESET = 0x8000, PHY_C_LOOPBK = 0x4000, PHY_C_SPEEDSL = 0x2000,
596 PHY_C_ANEGEN = 0x1000, PHY_C_PWRDN = 0x0800, PHY_C_ISO = 0x0400,
597 PHY_C_RANEG = 0x0200, PHY_C_DUPLEX = 0x0100, PHY_C_COLT = 0x0080,
599 #define DM9161_PHY_C_ANEGEN 0 /* auto nego special */
603 PHY_S_100T4 = 0x8000, PHY_S_100X_F = 0x4000, PHY_S_100X_H = 0x2000,
604 PHY_S_10T_F = 0x1000, PHY_S_10T_H = 0x0800, PHY_S_ANEGC = 0x0020,
605 PHY_S_RFAULT = 0x0010, PHY_S_ANEGA = 0x0008, PHY_S_LINK = 0x0004,
606 PHY_S_JAB = 0x0002, PHY_S_EXTD = 0x0001,
611 PHY_A_NP = 0x8000, PHY_A_ACK = 0x4000, PHY_A_RF = 0x2000,
612 PHY_A_FCS = 0x0400, PHY_A_T4 = 0x0200, PHY_A_FDX = 0x0100,
613 PHY_A_HDX = 0x0080, PHY_A_10FDX = 0x0040, PHY_A_10HDX = 0x0020,
618 PHY_L_NP = 0x8000, PHY_L_ACK = 0x4000, PHY_L_RF = 0x2000,
619 PHY_L_FCS = 0x0400, PHY_L_T4 = 0x0200, PHY_L_FDX = 0x0100,
620 PHY_L_HDX = 0x0080, PHY_L_10FDX = 0x0040, PHY_L_10HDX = 0x0020,
626 PHY_E_PDF = 0x0010, PHY_E_LPNPA = 0x0008, PHY_E_NPA = 0x0004,
627 PHY_E_PRX = 0x0002, PHY_E_LPANEGA = 0x0001,
632 PHY_16_BP4B45 = 0x8000, PHY_16_BPSCR = 0x4000, PHY_16_BPALIGN = 0x2000,
633 PHY_16_BP_ADPOK = 0x1000, PHY_16_Repeatmode = 0x0800,
634 PHY_16_TXselect = 0x0400,
635 PHY_16_Rsvd = 0x0200, PHY_16_RMIIEnable = 0x0100,
636 PHY_16_Force100LNK = 0x0080,
637 PHY_16_APDLED_CTL = 0x0040, PHY_16_COLLED_CTL = 0x0020,
638 PHY_16_RPDCTR_EN = 0x0010,
639 PHY_16_ResetStMch = 0x0008, PHY_16_PreamSupr = 0x0004,
640 PHY_16_Sleepmode = 0x0002,
641 PHY_16_RemoteLoopOut = 0x0001,
646 #define POST0_RX (POST_RX)
647 #define POST0_FW (POST_FW)
648 #define POST1_RX (POST_RX >> 2)
649 #define POST1_FW (POST_FW >> 2)
650 #define POST_ALL (POST0_RX | POST0_FW | POST1_RX | POST1_FW)
653 enum ARSTR_BIT { ARSTR_ARSTR = 0x00000001, };
657 TSU_FWEN0_0 = 0x00000001,
661 enum TSU_ADSBSY_BIT {
662 TSU_ADSBSY_0 = 0x00000001,
667 TSU_TEN_0 = 0x80000000,
672 TSU_FWSL0_FW50 = 0x1000, TSU_FWSL0_FW40 = 0x0800,
673 TSU_FWSL0_FW30 = 0x0400, TSU_FWSL0_FW20 = 0x0200,
674 TSU_FWSL0_FW10 = 0x0100, TSU_FWSL0_RMSA0 = 0x0010,
679 TSU_FWSLC_POSTENU = 0x2000, TSU_FWSLC_POSTENL = 0x1000,
680 TSU_FWSLC_CAMSEL03 = 0x0080, TSU_FWSLC_CAMSEL02 = 0x0040,
681 TSU_FWSLC_CAMSEL01 = 0x0020, TSU_FWSLC_CAMSEL00 = 0x0010,
682 TSU_FWSLC_CAMSEL13 = 0x0008, TSU_FWSLC_CAMSEL12 = 0x0004,
683 TSU_FWSLC_CAMSEL11 = 0x0002, TSU_FWSLC_CAMSEL10 = 0x0001,
687 #define TSU_VTAG_ENABLE 0x80000000
688 #define TSU_VTAG_VID_MASK 0x00000fff
691 * The sh ether Tx buffer descriptors.
692 * This structure should be 20 bytes.
694 struct sh_eth_txdesc {
695 u32 status; /* TD0 */
696 #if defined(__LITTLE_ENDIAN)
698 u16 buffer_length; /* TD1 */
700 u16 buffer_length; /* TD1 */
704 u32 pad1; /* padding data */
705 } __attribute__((aligned(2), packed));
708 * The sh ether Rx buffer descriptors.
709 * This structure should be 20 bytes.
711 struct sh_eth_rxdesc {
712 u32 status; /* RD0 */
713 #if defined(__LITTLE_ENDIAN)
714 u16 frame_length; /* RD1 */
715 u16 buffer_length; /* RD1 */
717 u16 buffer_length; /* RD1 */
718 u16 frame_length; /* RD1 */
721 u32 pad0; /* padding data */
722 } __attribute__((aligned(2), packed));
724 /* This structure is used by each CPU dependency handling. */
725 struct sh_eth_cpu_data {
726 /* optional functions */
727 void (*chip_reset)(struct net_device *ndev);
728 void (*set_duplex)(struct net_device *ndev);
729 void (*set_rate)(struct net_device *ndev);
731 /* mandatory initialize value */
732 unsigned long eesipr_value;
734 /* optional initialize value */
735 unsigned long ecsr_value;
736 unsigned long ecsipr_value;
737 unsigned long fdr_value;
738 unsigned long fcftr_value;
739 unsigned long rpadir_value;
740 unsigned long rmcr_value;
742 /* interrupt checking mask */
743 unsigned long tx_check;
744 unsigned long eesr_err_check;
745 unsigned long tx_error_check;
747 /* hardware features */
748 unsigned no_psr:1; /* EtherC DO NOT have PSR */
749 unsigned apr:1; /* EtherC have APR */
750 unsigned mpr:1; /* EtherC have MPR */
751 unsigned tpauser:1; /* EtherC have TPAUSER */
752 unsigned bculr:1; /* EtherC have BCULR */
753 unsigned tsu:1; /* EtherC have TSU */
754 unsigned hw_swap:1; /* E-DMAC have DE bit in EDMR */
755 unsigned rpadir:1; /* E-DMAC have RPADIR */
756 unsigned no_trimd:1; /* E-DMAC DO NOT have TRIMD */
757 unsigned no_ade:1; /* E-DMAC DO NOT have ADE bit in EESR */
758 unsigned hw_crc:1; /* E-DMAC have CSMR */
761 struct sh_eth_private {
762 struct platform_device *pdev;
763 struct sh_eth_cpu_data *cd;
764 const u16 *reg_offset;
766 void __iomem *tsu_addr;
767 dma_addr_t rx_desc_dma;
768 dma_addr_t tx_desc_dma;
769 struct sh_eth_rxdesc *rx_ring;
770 struct sh_eth_txdesc *tx_ring;
771 struct sk_buff **rx_skbuff;
772 struct sk_buff **tx_skbuff;
773 struct timer_list timer;
775 u32 cur_rx, dirty_rx; /* Producer/consumer ring indices */
776 u32 cur_tx, dirty_tx;
777 u32 rx_buf_sz; /* Based on MTU+slack. */
779 /* MII transceiver section. */
780 u32 phy_id; /* PHY ID */
781 struct mii_bus *mii_bus; /* MDIO bus control */
782 struct phy_device *phydev; /* PHY device control */
784 phy_interface_t phy_interface;
788 u32 rx_int_var, tx_int_var; /* interrupt control variables */
789 char post_rx; /* POST receive */
790 char post_fw; /* POST forward */
791 struct net_device_stats tsu_stats; /* TSU forward status */
792 int port; /* for TSU */
793 int vlan_num_ids; /* for VLAN tag filter */
795 unsigned no_ether_link:1;
796 unsigned ether_link_active_low:1;
799 static inline void sh_eth_soft_swap(char *src, int len)
801 #ifdef __LITTLE_ENDIAN__
804 maxp = p + ((len + sizeof(u32) - 1) / sizeof(u32));
806 for (; p < maxp; p++)
811 static inline void sh_eth_write(struct net_device *ndev, unsigned long data,
814 struct sh_eth_private *mdp = netdev_priv(ndev);
816 iowrite32(data, mdp->addr + mdp->reg_offset[enum_index]);
819 static inline unsigned long sh_eth_read(struct net_device *ndev,
822 struct sh_eth_private *mdp = netdev_priv(ndev);
824 return ioread32(mdp->addr + mdp->reg_offset[enum_index]);
827 static inline void *sh_eth_tsu_get_offset(struct sh_eth_private *mdp,
830 return mdp->tsu_addr + mdp->reg_offset[enum_index];
833 static inline void sh_eth_tsu_write(struct sh_eth_private *mdp,
834 unsigned long data, int enum_index)
836 iowrite32(data, mdp->tsu_addr + mdp->reg_offset[enum_index]);
839 static inline unsigned long sh_eth_tsu_read(struct sh_eth_private *mdp,
842 return ioread32(mdp->tsu_addr + mdp->reg_offset[enum_index]);
845 #endif /* #ifndef __SH_ETH_H__ */