drivers/net/ethernet/realtek/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/init.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/firmware.h>
  29 #include <linux/pci-aspm.h>
  30 #include <linux/prefetch.h>
  31
  32 #include <asm/system.h>
  33 #include <asm/io.h>
  34 #include <asm/irq.h>
  35
  36 #define RTL8169_VERSION "2.3LK-NAPI"
  37 #define MODULENAME "r8169"
  38 #define PFX MODULENAME ": "
  39
  40 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  41 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  42 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  43 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  44 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  45 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  46 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  47 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  48
  49 #ifdef RTL8169_DEBUG
  50 #define assert(expr) \
  51         if (!(expr)) {                                  \
  52                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  53                 #expr,__FILE__,__func__,__LINE__);              \
  54         }
  55 #define dprintk(fmt, args...) \
  56         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  57 #else
  58 #define assert(expr) do {} while (0)
  59 #define dprintk(fmt, args...)   do {} while (0)
  60 #endif /* RTL8169_DEBUG */
  61
  62 #define R8169_MSG_DEFAULT \
  63         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  64
  65 #define TX_BUFFS_AVAIL(tp) \
  66         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
  67
  68 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  69    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  70 static const int multicast_filter_limit = 32;
  71
  72 #define MAX_READ_REQUEST_SHIFT  12
  73 #define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  74 #define SafeMtu         0x1c20  /* ... actually life sucks beyond ~7k */
  75 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  76
  77 #define R8169_REGS_SIZE         256
  78 #define R8169_NAPI_WEIGHT       64
  79 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  80 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
  81 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
  82 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  83 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  84
  85 #define RTL8169_TX_TIMEOUT      (6*HZ)
  86 #define RTL8169_PHY_TIMEOUT     (10*HZ)
  87
  88 #define RTL_EEPROM_SIG          cpu_to_le32(0x8129)
  89 #define RTL_EEPROM_SIG_MASK     cpu_to_le32(0xffff)
  90 #define RTL_EEPROM_SIG_ADDR     0x0000
  91
  92 /* write/read MMIO register */
  93 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
  94 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
  95 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
  96 #define RTL_R8(reg)             readb (ioaddr + (reg))
  97 #define RTL_R16(reg)            readw (ioaddr + (reg))
  98 #define RTL_R32(reg)            readl (ioaddr + (reg))
  99
 100 enum mac_version {
 101         RTL_GIGA_MAC_VER_01 = 0,
 102         RTL_GIGA_MAC_VER_02,
 103         RTL_GIGA_MAC_VER_03,
 104         RTL_GIGA_MAC_VER_04,
 105         RTL_GIGA_MAC_VER_05,
 106         RTL_GIGA_MAC_VER_06,
 107         RTL_GIGA_MAC_VER_07,
 108         RTL_GIGA_MAC_VER_08,
 109         RTL_GIGA_MAC_VER_09,
 110         RTL_GIGA_MAC_VER_10,
 111         RTL_GIGA_MAC_VER_11,
 112         RTL_GIGA_MAC_VER_12,
 113         RTL_GIGA_MAC_VER_13,
 114         RTL_GIGA_MAC_VER_14,
 115         RTL_GIGA_MAC_VER_15,
 116         RTL_GIGA_MAC_VER_16,
 117         RTL_GIGA_MAC_VER_17,
 118         RTL_GIGA_MAC_VER_18,
 119         RTL_GIGA_MAC_VER_19,
 120         RTL_GIGA_MAC_VER_20,
 121         RTL_GIGA_MAC_VER_21,
 122         RTL_GIGA_MAC_VER_22,
 123         RTL_GIGA_MAC_VER_23,
 124         RTL_GIGA_MAC_VER_24,
 125         RTL_GIGA_MAC_VER_25,
 126         RTL_GIGA_MAC_VER_26,
 127         RTL_GIGA_MAC_VER_27,
 128         RTL_GIGA_MAC_VER_28,
 129         RTL_GIGA_MAC_VER_29,
 130         RTL_GIGA_MAC_VER_30,
 131         RTL_GIGA_MAC_VER_31,
 132         RTL_GIGA_MAC_VER_32,
 133         RTL_GIGA_MAC_VER_33,
 134         RTL_GIGA_MAC_VER_34,
 135         RTL_GIGA_MAC_VER_35,
 136         RTL_GIGA_MAC_VER_36,
 137         RTL_GIGA_MAC_NONE   = 0xff,
 138 };
 139
 140 enum rtl_tx_desc_version {
 141         RTL_TD_0        = 0,
 142         RTL_TD_1        = 1,
 143 };
 144
 145 #define JUMBO_1K        ETH_DATA_LEN
 146 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
 147 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
 148 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
 149 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
 150
 151 #define _R(NAME,TD,FW,SZ,B) {   \
 152         .name = NAME,           \
 153         .txd_version = TD,      \
 154         .fw_name = FW,          \
 155         .jumbo_max = SZ,        \
 156         .jumbo_tx_csum = B      \
 157 }
 158
 159 static const struct {
 160         const char *name;
 161         enum rtl_tx_desc_version txd_version;
 162         const char *fw_name;
 163         u16 jumbo_max;
 164         bool jumbo_tx_csum;
 165 } rtl_chip_infos[] = {
 166         /* PCI devices. */
 167         [RTL_GIGA_MAC_VER_01] =
 168                 _R("RTL8169",           RTL_TD_0, NULL, JUMBO_7K, true),
 169         [RTL_GIGA_MAC_VER_02] =
 170                 _R("RTL8169s",          RTL_TD_0, NULL, JUMBO_7K, true),
 171         [RTL_GIGA_MAC_VER_03] =
 172                 _R("RTL8110s",          RTL_TD_0, NULL, JUMBO_7K, true),
 173         [RTL_GIGA_MAC_VER_04] =
 174                 _R("RTL8169sb/8110sb",  RTL_TD_0, NULL, JUMBO_7K, true),
 175         [RTL_GIGA_MAC_VER_05] =
 176                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 177         [RTL_GIGA_MAC_VER_06] =
 178                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 179         /* PCI-E devices. */
 180         [RTL_GIGA_MAC_VER_07] =
 181                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 182         [RTL_GIGA_MAC_VER_08] =
 183                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 184         [RTL_GIGA_MAC_VER_09] =
 185                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 186         [RTL_GIGA_MAC_VER_10] =
 187                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 188         [RTL_GIGA_MAC_VER_11] =
 189                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 190         [RTL_GIGA_MAC_VER_12] =
 191                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 192         [RTL_GIGA_MAC_VER_13] =
 193                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 194         [RTL_GIGA_MAC_VER_14] =
 195                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 196         [RTL_GIGA_MAC_VER_15] =
 197                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 198         [RTL_GIGA_MAC_VER_16] =
 199                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 200         [RTL_GIGA_MAC_VER_17] =
 201                 _R("RTL8168b/8111b",    RTL_TD_1, NULL, JUMBO_4K, false),
 202         [RTL_GIGA_MAC_VER_18] =
 203                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 204         [RTL_GIGA_MAC_VER_19] =
 205                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 206         [RTL_GIGA_MAC_VER_20] =
 207                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 208         [RTL_GIGA_MAC_VER_21] =
 209                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 210         [RTL_GIGA_MAC_VER_22] =
 211                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 212         [RTL_GIGA_MAC_VER_23] =
 213                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 214         [RTL_GIGA_MAC_VER_24] =
 215                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 216         [RTL_GIGA_MAC_VER_25] =
 217                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_1,
 218                                                         JUMBO_9K, false),
 219         [RTL_GIGA_MAC_VER_26] =
 220                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_2,
 221                                                         JUMBO_9K, false),
 222         [RTL_GIGA_MAC_VER_27] =
 223                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 224         [RTL_GIGA_MAC_VER_28] =
 225                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 226         [RTL_GIGA_MAC_VER_29] =
 227                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 228                                                         JUMBO_1K, true),
 229         [RTL_GIGA_MAC_VER_30] =
 230                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 231                                                         JUMBO_1K, true),
 232         [RTL_GIGA_MAC_VER_31] =
 233                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 234         [RTL_GIGA_MAC_VER_32] =
 235                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_1,
 236                                                         JUMBO_9K, false),
 237         [RTL_GIGA_MAC_VER_33] =
 238                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_2,
 239                                                         JUMBO_9K, false),
 240         [RTL_GIGA_MAC_VER_34] =
 241                 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
 242                                                         JUMBO_9K, false),
 243         [RTL_GIGA_MAC_VER_35] =
 244                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_1,
 245                                                         JUMBO_9K, false),
 246         [RTL_GIGA_MAC_VER_36] =
 247                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_2,
 248                                                         JUMBO_9K, false),
 249 };
 250 #undef _R
 251
 252 enum cfg_version {
 253         RTL_CFG_0 = 0x00,
 254         RTL_CFG_1,
 255         RTL_CFG_2
 256 };
 257
 258 static void rtl_hw_start_8169(struct net_device *);
 259 static void rtl_hw_start_8168(struct net_device *);
 260 static void rtl_hw_start_8101(struct net_device *);
 261
 262 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
 263         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 264         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 265         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 266         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 267         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 268         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 269         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4302), 0, 0, RTL_CFG_0 },
 270         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 271         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 272         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 273                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 274         { 0x0001,                               0x8168,
 275                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 276         {0,},
 277 };
 278
 279 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 280
 281 static int rx_buf_sz = 16383;
 282 static int use_dac;
 283 static struct {
 284         u32 msg_enable;
 285 } debug = { -1 };
 286
 287 enum rtl_registers {
 288         MAC0            = 0,    /* Ethernet hardware address. */
 289         MAC4            = 4,
 290         MAR0            = 8,    /* Multicast filter. */
 291         CounterAddrLow          = 0x10,
 292         CounterAddrHigh         = 0x14,
 293         TxDescStartAddrLow      = 0x20,
 294         TxDescStartAddrHigh     = 0x24,
 295         TxHDescStartAddrLow     = 0x28,
 296         TxHDescStartAddrHigh    = 0x2c,
 297         FLASH           = 0x30,
 298         ERSR            = 0x36,
 299         ChipCmd         = 0x37,
 300         TxPoll          = 0x38,
 301         IntrMask        = 0x3c,
 302         IntrStatus      = 0x3e,
 303
 304         TxConfig        = 0x40,
 305 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 306 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 307
 308         RxConfig        = 0x44,
 309 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 310 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 311 #define RXCFG_FIFO_SHIFT                13
 312                                         /* No threshold before first PCI xfer */
 313 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 314 #define RXCFG_DMA_SHIFT                 8
 315                                         /* Unlimited maximum PCI burst. */
 316 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 317
 318         RxMissed        = 0x4c,
 319         Cfg9346         = 0x50,
 320         Config0         = 0x51,
 321         Config1         = 0x52,
 322         Config2         = 0x53,
 323         Config3         = 0x54,
 324         Config4         = 0x55,
 325         Config5         = 0x56,
 326         MultiIntr       = 0x5c,
 327         PHYAR           = 0x60,
 328         PHYstatus       = 0x6c,
 329         RxMaxSize       = 0xda,
 330         CPlusCmd        = 0xe0,
 331         IntrMitigate    = 0xe2,
 332         RxDescAddrLow   = 0xe4,
 333         RxDescAddrHigh  = 0xe8,
 334         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 335
 336 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 337
 338         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 339
 340 #define TxPacketMax     (8064 >> 7)
 341 #define EarlySize       0x27
 342
 343         FuncEvent       = 0xf0,
 344         FuncEventMask   = 0xf4,
 345         FuncPresetState = 0xf8,
 346         FuncForceEvent  = 0xfc,
 347 };
 348
 349 enum rtl8110_registers {
 350         TBICSR                  = 0x64,
 351         TBI_ANAR                = 0x68,
 352         TBI_LPAR                = 0x6a,
 353 };
 354
 355 enum rtl8168_8101_registers {
 356         CSIDR                   = 0x64,
 357         CSIAR                   = 0x68,
 358 #define CSIAR_FLAG                      0x80000000
 359 #define CSIAR_WRITE_CMD                 0x80000000
 360 #define CSIAR_BYTE_ENABLE               0x0f
 361 #define CSIAR_BYTE_ENABLE_SHIFT         12
 362 #define CSIAR_ADDR_MASK                 0x0fff
 363         PMCH                    = 0x6f,
 364         EPHYAR                  = 0x80,
 365 #define EPHYAR_FLAG                     0x80000000
 366 #define EPHYAR_WRITE_CMD                0x80000000
 367 #define EPHYAR_REG_MASK                 0x1f
 368 #define EPHYAR_REG_SHIFT                16
 369 #define EPHYAR_DATA_MASK                0xffff
 370         DLLPR                   = 0xd0,
 371 #define PFM_EN                          (1 << 6)
 372         DBG_REG                 = 0xd1,
 373 #define FIX_NAK_1                       (1 << 4)
 374 #define FIX_NAK_2                       (1 << 3)
 375         TWSI                    = 0xd2,
 376         MCU                     = 0xd3,
 377 #define NOW_IS_OOB                      (1 << 7)
 378 #define EN_NDP                          (1 << 3)
 379 #define EN_OOB_RESET                    (1 << 2)
 380         EFUSEAR                 = 0xdc,
 381 #define EFUSEAR_FLAG                    0x80000000
 382 #define EFUSEAR_WRITE_CMD               0x80000000
 383 #define EFUSEAR_READ_CMD                0x00000000
 384 #define EFUSEAR_REG_MASK                0x03ff
 385 #define EFUSEAR_REG_SHIFT               8
 386 #define EFUSEAR_DATA_MASK               0xff
 387 };
 388
 389 enum rtl8168_registers {
 390         LED_FREQ                = 0x1a,
 391         EEE_LED                 = 0x1b,
 392         ERIDR                   = 0x70,
 393         ERIAR                   = 0x74,
 394 #define ERIAR_FLAG                      0x80000000
 395 #define ERIAR_WRITE_CMD                 0x80000000
 396 #define ERIAR_READ_CMD                  0x00000000
 397 #define ERIAR_ADDR_BYTE_ALIGN           4
 398 #define ERIAR_TYPE_SHIFT                16
 399 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 400 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 401 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 402 #define ERIAR_MASK_SHIFT                12
 403 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 404 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 405 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 406         EPHY_RXER_NUM           = 0x7c,
 407         OCPDR                   = 0xb0, /* OCP GPHY access */
 408 #define OCPDR_WRITE_CMD                 0x80000000
 409 #define OCPDR_READ_CMD                  0x00000000
 410 #define OCPDR_REG_MASK                  0x7f
 411 #define OCPDR_GPHY_REG_SHIFT            16
 412 #define OCPDR_DATA_MASK                 0xffff
 413         OCPAR                   = 0xb4,
 414 #define OCPAR_FLAG                      0x80000000
 415 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 416 #define OCPAR_GPHY_READ_CMD             0x0000f060
 417         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 418         MISC                    = 0xf0, /* 8168e only. */
 419 #define TXPLA_RST                       (1 << 29)
 420 #define PWM_EN                          (1 << 22)
 421 };
 422
 423 enum rtl_register_content {
 424         /* InterruptStatusBits */
 425         SYSErr          = 0x8000,
 426         PCSTimeout      = 0x4000,
 427         SWInt           = 0x0100,
 428         TxDescUnavail   = 0x0080,
 429         RxFIFOOver      = 0x0040,
 430         LinkChg         = 0x0020,
 431         RxOverflow      = 0x0010,
 432         TxErr           = 0x0008,
 433         TxOK            = 0x0004,
 434         RxErr           = 0x0002,
 435         RxOK            = 0x0001,
 436
 437         /* RxStatusDesc */
 438         RxBOVF  = (1 << 24),
 439         RxFOVF  = (1 << 23),
 440         RxRWT   = (1 << 22),
 441         RxRES   = (1 << 21),
 442         RxRUNT  = (1 << 20),
 443         RxCRC   = (1 << 19),
 444
 445         /* ChipCmdBits */
 446         StopReq         = 0x80,
 447         CmdReset        = 0x10,
 448         CmdRxEnb        = 0x08,
 449         CmdTxEnb        = 0x04,
 450         RxBufEmpty      = 0x01,
 451
 452         /* TXPoll register p.5 */
 453         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 454         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 455         FSWInt          = 0x01,         /* Forced software interrupt */
 456
 457         /* Cfg9346Bits */
 458         Cfg9346_Lock    = 0x00,
 459         Cfg9346_Unlock  = 0xc0,
 460
 461         /* rx_mode_bits */
 462         AcceptErr       = 0x20,
 463         AcceptRunt      = 0x10,
 464         AcceptBroadcast = 0x08,
 465         AcceptMulticast = 0x04,
 466         AcceptMyPhys    = 0x02,
 467         AcceptAllPhys   = 0x01,
 468 #define RX_CONFIG_ACCEPT_MASK           0x3f
 469
 470         /* TxConfigBits */
 471         TxInterFrameGapShift = 24,
 472         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 473
 474         /* Config1 register p.24 */
 475         LEDS1           = (1 << 7),
 476         LEDS0           = (1 << 6),
 477         Speed_down      = (1 << 4),
 478         MEMMAP          = (1 << 3),
 479         IOMAP           = (1 << 2),
 480         VPD             = (1 << 1),
 481         PMEnable        = (1 << 0),     /* Power Management Enable */
 482
 483         /* Config2 register p. 25 */
 484         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 485         PCI_Clock_66MHz = 0x01,
 486         PCI_Clock_33MHz = 0x00,
 487
 488         /* Config3 register p.25 */
 489         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 490         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 491         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 492         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 493
 494         /* Config4 register */
 495         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 496
 497         /* Config5 register p.27 */
 498         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 499         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 500         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 501         Spi_en          = (1 << 3),
 502         LanWake         = (1 << 1),     /* LanWake enable/disable */
 503         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 504
 505         /* TBICSR p.28 */
 506         TBIReset        = 0x80000000,
 507         TBILoopback     = 0x40000000,
 508         TBINwEnable     = 0x20000000,
 509         TBINwRestart    = 0x10000000,
 510         TBILinkOk       = 0x02000000,
 511         TBINwComplete   = 0x01000000,
 512
 513         /* CPlusCmd p.31 */
 514         EnableBist      = (1 << 15),    // 8168 8101
 515         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 516         Normal_mode     = (1 << 13),    // unused
 517         Force_half_dup  = (1 << 12),    // 8168 8101
 518         Force_rxflow_en = (1 << 11),    // 8168 8101
 519         Force_txflow_en = (1 << 10),    // 8168 8101
 520         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 521         ASF             = (1 << 8),     // 8168 8101
 522         PktCntrDisable  = (1 << 7),     // 8168 8101
 523         Mac_dbgo_sel    = 0x001c,       // 8168
 524         RxVlan          = (1 << 6),
 525         RxChkSum        = (1 << 5),
 526         PCIDAC          = (1 << 4),
 527         PCIMulRW        = (1 << 3),
 528         INTT_0          = 0x0000,       // 8168
 529         INTT_1          = 0x0001,       // 8168
 530         INTT_2          = 0x0002,       // 8168
 531         INTT_3          = 0x0003,       // 8168
 532
 533         /* rtl8169_PHYstatus */
 534         TBI_Enable      = 0x80,
 535         TxFlowCtrl      = 0x40,
 536         RxFlowCtrl      = 0x20,
 537         _1000bpsF       = 0x10,
 538         _100bps         = 0x08,
 539         _10bps          = 0x04,
 540         LinkStatus      = 0x02,
 541         FullDup         = 0x01,
 542
 543         /* _TBICSRBit */
 544         TBILinkOK       = 0x02000000,
 545
 546         /* DumpCounterCommand */
 547         CounterDump     = 0x8,
 548 };
 549
 550 enum rtl_desc_bit {
 551         /* First doubleword. */
 552         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 553         RingEnd         = (1 << 30), /* End of descriptor ring */
 554         FirstFrag       = (1 << 29), /* First segment of a packet */
 555         LastFrag        = (1 << 28), /* Final segment of a packet */
 556 };
 557
 558 /* Generic case. */
 559 enum rtl_tx_desc_bit {
 560         /* First doubleword. */
 561         TD_LSO          = (1 << 27),            /* Large Send Offload */
 562 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 563
 564         /* Second doubleword. */
 565         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 566 };
 567
 568 /* 8169, 8168b and 810x except 8102e. */
 569 enum rtl_tx_desc_bit_0 {
 570         /* First doubleword. */
 571 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 572         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 573         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 574         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 575 };
 576
 577 /* 8102e, 8168c and beyond. */
 578 enum rtl_tx_desc_bit_1 {
 579         /* Second doubleword. */
 580 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 581         TD1_IP_CS       = (1 << 29),            /* Calculate IP checksum */
 582         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 583         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 584 };
 585
 586 static const struct rtl_tx_desc_info {
 587         struct {
 588                 u32 udp;
 589                 u32 tcp;
 590         } checksum;
 591         u16 mss_shift;
 592         u16 opts_offset;
 593 } tx_desc_info [] = {
 594         [RTL_TD_0] = {
 595                 .checksum = {
 596                         .udp    = TD0_IP_CS | TD0_UDP_CS,
 597                         .tcp    = TD0_IP_CS | TD0_TCP_CS
 598                 },
 599                 .mss_shift      = TD0_MSS_SHIFT,
 600                 .opts_offset    = 0
 601         },
 602         [RTL_TD_1] = {
 603                 .checksum = {
 604                         .udp    = TD1_IP_CS | TD1_UDP_CS,
 605                         .tcp    = TD1_IP_CS | TD1_TCP_CS
 606                 },
 607                 .mss_shift      = TD1_MSS_SHIFT,
 608                 .opts_offset    = 1
 609         }
 610 };
 611
 612 enum rtl_rx_desc_bit {
 613         /* Rx private */
 614         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 615         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
 616
 617 #define RxProtoUDP      (PID1)
 618 #define RxProtoTCP      (PID0)
 619 #define RxProtoIP       (PID1 | PID0)
 620 #define RxProtoMask     RxProtoIP
 621
 622         IPFail          = (1 << 16), /* IP checksum failed */
 623         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 624         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 625         RxVlanTag       = (1 << 16), /* VLAN tag available */
 626 };
 627
 628 #define RsvdMask        0x3fffc000
 629
 630 struct TxDesc {
 631         __le32 opts1;
 632         __le32 opts2;
 633         __le64 addr;
 634 };
 635
 636 struct RxDesc {
 637         __le32 opts1;
 638         __le32 opts2;
 639         __le64 addr;
 640 };
 641
 642 struct ring_info {
 643         struct sk_buff  *skb;
 644         u32             len;
 645         u8              __pad[sizeof(void *) - sizeof(u32)];
 646 };
 647
 648 enum features {
 649         RTL_FEATURE_WOL         = (1 << 0),
 650         RTL_FEATURE_MSI         = (1 << 1),
 651         RTL_FEATURE_GMII        = (1 << 2),
 652 };
 653
 654 struct rtl8169_counters {
 655         __le64  tx_packets;
 656         __le64  rx_packets;
 657         __le64  tx_errors;
 658         __le32  rx_errors;
 659         __le16  rx_missed;
 660         __le16  align_errors;
 661         __le32  tx_one_collision;
 662         __le32  tx_multi_collision;
 663         __le64  rx_unicast;
 664         __le64  rx_broadcast;
 665         __le32  rx_multicast;
 666         __le16  tx_aborted;
 667         __le16  tx_underun;
 668 };
 669
 670 enum rtl_flag {
 671         RTL_FLAG_TASK_ENABLED,
 672         RTL_FLAG_TASK_SLOW_PENDING,
 673         RTL_FLAG_TASK_RESET_PENDING,
 674         RTL_FLAG_TASK_PHY_PENDING,
 675         RTL_FLAG_MAX
 676 };
 677
 678 struct rtl8169_stats {
 679         u64                     packets;
 680         u64                     bytes;
 681         struct u64_stats_sync   syncp;
 682 };
 683
 684 struct rtl8169_private {
 685         void __iomem *mmio_addr;        /* memory map physical address */
 686         struct pci_dev *pci_dev;
 687         struct net_device *dev;
 688         struct napi_struct napi;
 689         u32 msg_enable;
 690         u16 txd_version;
 691         u16 mac_version;
 692         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 693         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 694         u32 dirty_rx;
 695         u32 dirty_tx;
 696         struct rtl8169_stats rx_stats;
 697         struct rtl8169_stats tx_stats;
 698         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 699         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 700         dma_addr_t TxPhyAddr;
 701         dma_addr_t RxPhyAddr;
 702         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 703         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 704         struct timer_list timer;
 705         u16 cp_cmd;
 706
 707         u16 event_slow;
 708
 709         struct mdio_ops {
 710                 void (*write)(void __iomem *, int, int);
 711                 int (*read)(void __iomem *, int);
 712         } mdio_ops;
 713
 714         struct pll_power_ops {
 715                 void (*down)(struct rtl8169_private *);
 716                 void (*up)(struct rtl8169_private *);
 717         } pll_power_ops;
 718
 719         struct jumbo_ops {
 720                 void (*enable)(struct rtl8169_private *);
 721                 void (*disable)(struct rtl8169_private *);
 722         } jumbo_ops;
 723
 724         int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
 725         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
 726         void (*phy_reset_enable)(struct rtl8169_private *tp);
 727         void (*hw_start)(struct net_device *);
 728         unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
 729         unsigned int (*link_ok)(void __iomem *);
 730         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
 731
 732         struct {
 733                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 734                 struct mutex mutex;
 735                 struct work_struct work;
 736         } wk;
 737
 738         unsigned features;
 739
 740         struct mii_if_info mii;
 741         struct rtl8169_counters counters;
 742         u32 saved_wolopts;
 743         u32 opts1_mask;
 744
 745         struct rtl_fw {
 746                 const struct firmware *fw;
 747
 748 #define RTL_VER_SIZE            32
 749
 750                 char version[RTL_VER_SIZE];
 751
 752                 struct rtl_fw_phy_action {
 753                         __le32 *code;
 754                         size_t size;
 755                 } phy_action;
 756         } *rtl_fw;
 757 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN)
 758 };
 759
 760 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 761 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 762 module_param(use_dac, int, 0);
 763 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 764 module_param_named(debug, debug.msg_enable, int, 0);
 765 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 766 MODULE_LICENSE("GPL");
 767 MODULE_VERSION(RTL8169_VERSION);
 768 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 769 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 770 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 771 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 772 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 773 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 774 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 775 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 776
 777 static int rtl8169_open(struct net_device *dev);
 778 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
 779                                       struct net_device *dev);
 780 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
 781 static int rtl8169_init_ring(struct net_device *dev);
 782 static void rtl_hw_start(struct net_device *dev);
 783 static int rtl8169_close(struct net_device *dev);
 784 static void rtl_set_rx_mode(struct net_device *dev);
 785 static void rtl8169_tx_timeout(struct net_device *dev);
 786 static struct rtnl_link_stats64 *rtl8169_get_stats64(struct net_device *dev,
 787                                                     struct rtnl_link_stats64
 788                                                     *stats);
 789 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
 790 static void rtl8169_rx_clear(struct rtl8169_private *tp);
 791 static int rtl8169_poll(struct napi_struct *napi, int budget);
 792
 793 static void rtl_lock_work(struct rtl8169_private *tp)
 794 {
 795         mutex_lock(&tp->wk.mutex);
 796 }
 797
 798 static void rtl_unlock_work(struct rtl8169_private *tp)
 799 {
 800         mutex_unlock(&tp->wk.mutex);
 801 }
 802
 803 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
 804 {
 805         int cap = pci_pcie_cap(pdev);
 806
 807         if (cap) {
 808                 u16 ctl;
 809
 810                 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
 811                 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
 812                 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
 813         }
 814 }
 815
 816 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
 817 {
 818         void __iomem *ioaddr = tp->mmio_addr;
 819         int i;
 820
 821         RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 822         for (i = 0; i < 20; i++) {
 823                 udelay(100);
 824                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
 825                         break;
 826         }
 827         return RTL_R32(OCPDR);
 828 }
 829
 830 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
 831 {
 832         void __iomem *ioaddr = tp->mmio_addr;
 833         int i;
 834
 835         RTL_W32(OCPDR, data);
 836         RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 837         for (i = 0; i < 20; i++) {
 838                 udelay(100);
 839                 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
 840                         break;
 841         }
 842 }
 843
 844 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
 845 {
 846         void __iomem *ioaddr = tp->mmio_addr;
 847         int i;
 848
 849         RTL_W8(ERIDR, cmd);
 850         RTL_W32(ERIAR, 0x800010e8);
 851         msleep(2);
 852         for (i = 0; i < 5; i++) {
 853                 udelay(100);
 854                 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
 855                         break;
 856         }
 857
 858         ocp_write(tp, 0x1, 0x30, 0x00000001);
 859 }
 860
 861 #define OOB_CMD_RESET           0x00
 862 #define OOB_CMD_DRIVER_START    0x05
 863 #define OOB_CMD_DRIVER_STOP     0x06
 864
 865 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
 866 {
 867         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
 868 }
 869
 870 static void rtl8168_driver_start(struct rtl8169_private *tp)
 871 {
 872         u16 reg;
 873         int i;
 874
 875         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
 876
 877         reg = rtl8168_get_ocp_reg(tp);
 878
 879         for (i = 0; i < 10; i++) {
 880                 msleep(10);
 881                 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
 882                         break;
 883         }
 884 }
 885
 886 static void rtl8168_driver_stop(struct rtl8169_private *tp)
 887 {
 888         u16 reg;
 889         int i;
 890
 891         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
 892
 893         reg = rtl8168_get_ocp_reg(tp);
 894
 895         for (i = 0; i < 10; i++) {
 896                 msleep(10);
 897                 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
 898                         break;
 899         }
 900 }
 901
 902 static int r8168dp_check_dash(struct rtl8169_private *tp)
 903 {
 904         u16 reg = rtl8168_get_ocp_reg(tp);
 905
 906         return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
 907 }
 908
 909 static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 910 {
 911         int i;
 912
 913         RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
 914
 915         for (i = 20; i > 0; i--) {
 916                 /*
 917                  * Check if the RTL8169 has completed writing to the specified
 918                  * MII register.
 919                  */
 920                 if (!(RTL_R32(PHYAR) & 0x80000000))
 921                         break;
 922                 udelay(25);
 923         }
 924         /*
 925          * According to hardware specs a 20us delay is required after write
 926          * complete indication, but before sending next command.
 927          */
 928         udelay(20);
 929 }
 930
 931 static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
 932 {
 933         int i, value = -1;
 934
 935         RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
 936
 937         for (i = 20; i > 0; i--) {
 938                 /*
 939                  * Check if the RTL8169 has completed retrieving data from
 940                  * the specified MII register.
 941                  */
 942                 if (RTL_R32(PHYAR) & 0x80000000) {
 943                         value = RTL_R32(PHYAR) & 0xffff;
 944                         break;
 945                 }
 946                 udelay(25);
 947         }
 948         /*
 949          * According to hardware specs a 20us delay is required after read
 950          * complete indication, but before sending next command.
 951          */
 952         udelay(20);
 953
 954         return value;
 955 }
 956
 957 static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
 958 {
 959         int i;
 960
 961         RTL_W32(OCPDR, data |
 962                 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
 963         RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
 964         RTL_W32(EPHY_RXER_NUM, 0);
 965
 966         for (i = 0; i < 100; i++) {
 967                 mdelay(1);
 968                 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
 969                         break;
 970         }
 971 }
 972
 973 static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 974 {
 975         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
 976                 (value & OCPDR_DATA_MASK));
 977 }
 978
 979 static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
 980 {
 981         int i;
 982
 983         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
 984
 985         mdelay(1);
 986         RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
 987         RTL_W32(EPHY_RXER_NUM, 0);
 988
 989         for (i = 0; i < 100; i++) {
 990                 mdelay(1);
 991                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
 992                         break;
 993         }
 994
 995         return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
 996 }
 997
 998 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
 999
1000 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
1001 {
1002         RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1003 }
1004
1005 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
1006 {
1007         RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1008 }
1009
1010 static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1011 {
1012         r8168dp_2_mdio_start(ioaddr);
1013
1014         r8169_mdio_write(ioaddr, reg_addr, value);
1015
1016         r8168dp_2_mdio_stop(ioaddr);
1017 }
1018
1019 static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
1020 {
1021         int value;
1022
1023         r8168dp_2_mdio_start(ioaddr);
1024
1025         value = r8169_mdio_read(ioaddr, reg_addr);
1026
1027         r8168dp_2_mdio_stop(ioaddr);
1028
1029         return value;
1030 }
1031
1032 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1033 {
1034         tp->mdio_ops.write(tp->mmio_addr, location, val);
1035 }
1036
1037 static int rtl_readphy(struct rtl8169_private *tp, int location)
1038 {
1039         return tp->mdio_ops.read(tp->mmio_addr, location);
1040 }
1041
1042 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1043 {
1044         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1045 }
1046
1047 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1048 {
1049         int val;
1050
1051         val = rtl_readphy(tp, reg_addr);
1052         rtl_writephy(tp, reg_addr, (val | p) & ~m);
1053 }
1054
1055 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1056                            int val)
1057 {
1058         struct rtl8169_private *tp = netdev_priv(dev);
1059
1060         rtl_writephy(tp, location, val);
1061 }
1062
1063 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1064 {
1065         struct rtl8169_private *tp = netdev_priv(dev);
1066
1067         return rtl_readphy(tp, location);
1068 }
1069
1070 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
1071 {
1072         unsigned int i;
1073
1074         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1075                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1076
1077         for (i = 0; i < 100; i++) {
1078                 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
1079                         break;
1080                 udelay(10);
1081         }
1082 }
1083
1084 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
1085 {
1086         u16 value = 0xffff;
1087         unsigned int i;
1088
1089         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1090
1091         for (i = 0; i < 100; i++) {
1092                 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
1093                         value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
1094                         break;
1095                 }
1096                 udelay(10);
1097         }
1098
1099         return value;
1100 }
1101
1102 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
1103 {
1104         unsigned int i;
1105
1106         RTL_W32(CSIDR, value);
1107         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
1108                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1109
1110         for (i = 0; i < 100; i++) {
1111                 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
1112                         break;
1113                 udelay(10);
1114         }
1115 }
1116
1117 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
1118 {
1119         u32 value = ~0x00;
1120         unsigned int i;
1121
1122         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
1123                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1124
1125         for (i = 0; i < 100; i++) {
1126                 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
1127                         value = RTL_R32(CSIDR);
1128                         break;
1129                 }
1130                 udelay(10);
1131         }
1132
1133         return value;
1134 }
1135
1136 static
1137 void rtl_eri_write(void __iomem *ioaddr, int addr, u32 mask, u32 val, int type)
1138 {
1139         unsigned int i;
1140
1141         BUG_ON((addr & 3) || (mask == 0));
1142         RTL_W32(ERIDR, val);
1143         RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1144
1145         for (i = 0; i < 100; i++) {
1146                 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
1147                         break;
1148                 udelay(100);
1149         }
1150 }
1151
1152 static u32 rtl_eri_read(void __iomem *ioaddr, int addr, int type)
1153 {
1154         u32 value = ~0x00;
1155         unsigned int i;
1156
1157         RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1158
1159         for (i = 0; i < 100; i++) {
1160                 if (RTL_R32(ERIAR) & ERIAR_FLAG) {
1161                         value = RTL_R32(ERIDR);
1162                         break;
1163                 }
1164                 udelay(100);
1165         }
1166
1167         return value;
1168 }
1169
1170 static void
1171 rtl_w1w0_eri(void __iomem *ioaddr, int addr, u32 mask, u32 p, u32 m, int type)
1172 {
1173         u32 val;
1174
1175         val = rtl_eri_read(ioaddr, addr, type);
1176         rtl_eri_write(ioaddr, addr, mask, (val & ~m) | p, type);
1177 }
1178
1179 struct exgmac_reg {
1180         u16 addr;
1181         u16 mask;
1182         u32 val;
1183 };
1184
1185 static void rtl_write_exgmac_batch(void __iomem *ioaddr,
1186                                    const struct exgmac_reg *r, int len)
1187 {
1188         while (len-- > 0) {
1189                 rtl_eri_write(ioaddr, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1190                 r++;
1191         }
1192 }
1193
1194 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1195 {
1196         u8 value = 0xff;
1197         unsigned int i;
1198
1199         RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1200
1201         for (i = 0; i < 300; i++) {
1202                 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1203                         value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1204                         break;
1205                 }
1206                 udelay(100);
1207         }
1208
1209         return value;
1210 }
1211
1212 static u16 rtl_get_events(struct rtl8169_private *tp)
1213 {
1214         void __iomem *ioaddr = tp->mmio_addr;
1215
1216         return RTL_R16(IntrStatus);
1217 }
1218
1219 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1220 {
1221         void __iomem *ioaddr = tp->mmio_addr;
1222
1223         RTL_W16(IntrStatus, bits);
1224         mmiowb();
1225 }
1226
1227 static void rtl_irq_disable(struct rtl8169_private *tp)
1228 {
1229         void __iomem *ioaddr = tp->mmio_addr;
1230
1231         RTL_W16(IntrMask, 0);
1232         mmiowb();
1233 }
1234
1235 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1236 {
1237         void __iomem *ioaddr = tp->mmio_addr;
1238
1239         RTL_W16(IntrMask, bits);
1240 }
1241
1242 #define RTL_EVENT_NAPI_RX       (RxOK | RxErr)
1243 #define RTL_EVENT_NAPI_TX       (TxOK | TxErr)
1244 #define RTL_EVENT_NAPI          (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1245
1246 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1247 {
1248         rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1249 }
1250
1251 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1252 {
1253         void __iomem *ioaddr = tp->mmio_addr;
1254
1255         rtl_irq_disable(tp);
1256         rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1257         RTL_R8(ChipCmd);
1258 }
1259
1260 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1261 {
1262         void __iomem *ioaddr = tp->mmio_addr;
1263
1264         return RTL_R32(TBICSR) & TBIReset;
1265 }
1266
1267 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1268 {
1269         return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1270 }
1271
1272 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1273 {
1274         return RTL_R32(TBICSR) & TBILinkOk;
1275 }
1276
1277 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1278 {
1279         return RTL_R8(PHYstatus) & LinkStatus;
1280 }
1281
1282 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1283 {
1284         void __iomem *ioaddr = tp->mmio_addr;
1285
1286         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1287 }
1288
1289 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1290 {
1291         unsigned int val;
1292
1293         val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1294         rtl_writephy(tp, MII_BMCR, val & 0xffff);
1295 }
1296
1297 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1298 {
1299         void __iomem *ioaddr = tp->mmio_addr;
1300         struct net_device *dev = tp->dev;
1301
1302         if (!netif_running(dev))
1303                 return;
1304
1305         if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
1306                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1307                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1308                                       0x00000011, ERIAR_EXGMAC);
1309                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1310                                       0x00000005, ERIAR_EXGMAC);
1311                 } else if (RTL_R8(PHYstatus) & _100bps) {
1312                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1313                                       0x0000001f, ERIAR_EXGMAC);
1314                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1315                                       0x00000005, ERIAR_EXGMAC);
1316                 } else {
1317                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1318                                       0x0000001f, ERIAR_EXGMAC);
1319                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1320                                       0x0000003f, ERIAR_EXGMAC);
1321                 }
1322                 /* Reset packet filter */
1323                 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1324                              ERIAR_EXGMAC);
1325                 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1326                              ERIAR_EXGMAC);
1327         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1328                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1329                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1330                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1331                                       0x00000011, ERIAR_EXGMAC);
1332                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1333                                       0x00000005, ERIAR_EXGMAC);
1334                 } else {
1335                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1336                                       0x0000001f, ERIAR_EXGMAC);
1337                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1338                                       0x0000003f, ERIAR_EXGMAC);
1339                 }
1340         }
1341 }
1342
1343 static void __rtl8169_check_link_status(struct net_device *dev,
1344                                         struct rtl8169_private *tp,
1345                                         void __iomem *ioaddr, bool pm)
1346 {
1347         if (tp->link_ok(ioaddr)) {
1348                 rtl_link_chg_patch(tp);
1349                 /* This is to cancel a scheduled suspend if there's one. */
1350                 if (pm)
1351                         pm_request_resume(&tp->pci_dev->dev);
1352                 netif_carrier_on(dev);
1353                 if (net_ratelimit())
1354                         netif_info(tp, ifup, dev, "link up\n");
1355         } else {
1356                 netif_carrier_off(dev);
1357                 netif_info(tp, ifdown, dev, "link down\n");
1358                 if (pm)
1359                         pm_schedule_suspend(&tp->pci_dev->dev, 5000);
1360         }
1361 }
1362
1363 static void rtl8169_check_link_status(struct net_device *dev,
1364                                       struct rtl8169_private *tp,
1365                                       void __iomem *ioaddr)
1366 {
1367         __rtl8169_check_link_status(dev, tp, ioaddr, false);
1368 }
1369
1370 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1371
1372 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1373 {
1374         void __iomem *ioaddr = tp->mmio_addr;
1375         u8 options;
1376         u32 wolopts = 0;
1377
1378         options = RTL_R8(Config1);
1379         if (!(options & PMEnable))
1380                 return 0;
1381
1382         options = RTL_R8(Config3);
1383         if (options & LinkUp)
1384                 wolopts |= WAKE_PHY;
1385         if (options & MagicPacket)
1386                 wolopts |= WAKE_MAGIC;
1387
1388         options = RTL_R8(Config5);
1389         if (options & UWF)
1390                 wolopts |= WAKE_UCAST;
1391         if (options & BWF)
1392                 wolopts |= WAKE_BCAST;
1393         if (options & MWF)
1394                 wolopts |= WAKE_MCAST;
1395
1396         return wolopts;
1397 }
1398
1399 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1400 {
1401         struct rtl8169_private *tp = netdev_priv(dev);
1402
1403         rtl_lock_work(tp);
1404
1405         wol->supported = WAKE_ANY;
1406         wol->wolopts = __rtl8169_get_wol(tp);
1407
1408         rtl_unlock_work(tp);
1409 }
1410
1411 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1412 {
1413         void __iomem *ioaddr = tp->mmio_addr;
1414         unsigned int i;
1415         static const struct {
1416                 u32 opt;
1417                 u16 reg;
1418                 u8  mask;
1419         } cfg[] = {
1420                 { WAKE_ANY,   Config1, PMEnable },
1421                 { WAKE_PHY,   Config3, LinkUp },
1422                 { WAKE_MAGIC, Config3, MagicPacket },
1423                 { WAKE_UCAST, Config5, UWF },
1424                 { WAKE_BCAST, Config5, BWF },
1425                 { WAKE_MCAST, Config5, MWF },
1426                 { WAKE_ANY,   Config5, LanWake }
1427         };
1428
1429         RTL_W8(Cfg9346, Cfg9346_Unlock);
1430
1431         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1432                 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1433                 if (wolopts & cfg[i].opt)
1434                         options |= cfg[i].mask;
1435                 RTL_W8(cfg[i].reg, options);
1436         }
1437
1438         RTL_W8(Cfg9346, Cfg9346_Lock);
1439 }
1440
1441 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1442 {
1443         struct rtl8169_private *tp = netdev_priv(dev);
1444
1445         rtl_lock_work(tp);
1446
1447         if (wol->wolopts)
1448                 tp->features |= RTL_FEATURE_WOL;
1449         else
1450                 tp->features &= ~RTL_FEATURE_WOL;
1451         __rtl8169_set_wol(tp, wol->wolopts);
1452
1453         rtl_unlock_work(tp);
1454
1455         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1456
1457         return 0;
1458 }
1459
1460 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1461 {
1462         return rtl_chip_infos[tp->mac_version].fw_name;
1463 }
1464
1465 static void rtl8169_get_drvinfo(struct net_device *dev,
1466                                 struct ethtool_drvinfo *info)
1467 {
1468         struct rtl8169_private *tp = netdev_priv(dev);
1469         struct rtl_fw *rtl_fw = tp->rtl_fw;
1470
1471         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1472         strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1473         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1474         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1475         if (!IS_ERR_OR_NULL(rtl_fw))
1476                 strlcpy(info->fw_version, rtl_fw->version,
1477                         sizeof(info->fw_version));
1478 }
1479
1480 static int rtl8169_get_regs_len(struct net_device *dev)
1481 {
1482         return R8169_REGS_SIZE;
1483 }
1484
1485 static int rtl8169_set_speed_tbi(struct net_device *dev,
1486                                  u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1487 {
1488         struct rtl8169_private *tp = netdev_priv(dev);
1489         void __iomem *ioaddr = tp->mmio_addr;
1490         int ret = 0;
1491         u32 reg;
1492
1493         reg = RTL_R32(TBICSR);
1494         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1495             (duplex == DUPLEX_FULL)) {
1496                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1497         } else if (autoneg == AUTONEG_ENABLE)
1498                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1499         else {
1500                 netif_warn(tp, link, dev,
1501                            "incorrect speed setting refused in TBI mode\n");
1502                 ret = -EOPNOTSUPP;
1503         }
1504
1505         return ret;
1506 }
1507
1508 static int rtl8169_set_speed_xmii(struct net_device *dev,
1509                                   u8 autoneg, u16 speed, u8 duplex, u32 adv)
1510 {
1511         struct rtl8169_private *tp = netdev_priv(dev);
1512         int giga_ctrl, bmcr;
1513         int rc = -EINVAL;
1514
1515         rtl_writephy(tp, 0x1f, 0x0000);
1516
1517         if (autoneg == AUTONEG_ENABLE) {
1518                 int auto_nego;
1519
1520                 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1521                 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1522                                 ADVERTISE_100HALF | ADVERTISE_100FULL);
1523
1524                 if (adv & ADVERTISED_10baseT_Half)
1525                         auto_nego |= ADVERTISE_10HALF;
1526                 if (adv & ADVERTISED_10baseT_Full)
1527                         auto_nego |= ADVERTISE_10FULL;
1528                 if (adv & ADVERTISED_100baseT_Half)
1529                         auto_nego |= ADVERTISE_100HALF;
1530                 if (adv & ADVERTISED_100baseT_Full)
1531                         auto_nego |= ADVERTISE_100FULL;
1532
1533                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1534
1535                 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1536                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1537
1538                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1539                 if (tp->mii.supports_gmii) {
1540                         if (adv & ADVERTISED_1000baseT_Half)
1541                                 giga_ctrl |= ADVERTISE_1000HALF;
1542                         if (adv & ADVERTISED_1000baseT_Full)
1543                                 giga_ctrl |= ADVERTISE_1000FULL;
1544                 } else if (adv & (ADVERTISED_1000baseT_Half |
1545                                   ADVERTISED_1000baseT_Full)) {
1546                         netif_info(tp, link, dev,
1547                                    "PHY does not support 1000Mbps\n");
1548                         goto out;
1549                 }
1550
1551                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1552
1553                 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1554                 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1555         } else {
1556                 giga_ctrl = 0;
1557
1558                 if (speed == SPEED_10)
1559                         bmcr = 0;
1560                 else if (speed == SPEED_100)
1561                         bmcr = BMCR_SPEED100;
1562                 else
1563                         goto out;
1564
1565                 if (duplex == DUPLEX_FULL)
1566                         bmcr |= BMCR_FULLDPLX;
1567         }
1568
1569         rtl_writephy(tp, MII_BMCR, bmcr);
1570
1571         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1572             tp->mac_version == RTL_GIGA_MAC_VER_03) {
1573                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1574                         rtl_writephy(tp, 0x17, 0x2138);
1575                         rtl_writephy(tp, 0x0e, 0x0260);
1576                 } else {
1577                         rtl_writephy(tp, 0x17, 0x2108);
1578                         rtl_writephy(tp, 0x0e, 0x0000);
1579                 }
1580         }
1581
1582         rc = 0;
1583 out:
1584         return rc;
1585 }
1586
1587 static int rtl8169_set_speed(struct net_device *dev,
1588                              u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1589 {
1590         struct rtl8169_private *tp = netdev_priv(dev);
1591         int ret;
1592
1593         ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1594         if (ret < 0)
1595                 goto out;
1596
1597         if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1598             (advertising & ADVERTISED_1000baseT_Full)) {
1599                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1600         }
1601 out:
1602         return ret;
1603 }
1604
1605 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1606 {
1607         struct rtl8169_private *tp = netdev_priv(dev);
1608         int ret;
1609
1610         del_timer_sync(&tp->timer);
1611
1612         rtl_lock_work(tp);
1613         ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1614                                 cmd->duplex, cmd->advertising);
1615         rtl_unlock_work(tp);
1616
1617         return ret;
1618 }
1619
1620 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1621         netdev_features_t features)
1622 {
1623         struct rtl8169_private *tp = netdev_priv(dev);
1624
1625         if (dev->mtu > TD_MSS_MAX)
1626                 features &= ~NETIF_F_ALL_TSO;
1627
1628         if (dev->mtu > JUMBO_1K &&
1629             !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1630                 features &= ~NETIF_F_IP_CSUM;
1631
1632         return features;
1633 }
1634
1635 static void __rtl8169_set_features(struct net_device *dev,
1636                                    netdev_features_t features)
1637 {
1638         struct rtl8169_private *tp = netdev_priv(dev);
1639         netdev_features_t changed = features ^ dev->features;
1640         void __iomem *ioaddr = tp->mmio_addr;
1641
1642         if (!(changed & (NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)))
1643                 return;
1644
1645         if (changed & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)) {
1646                 if (features & NETIF_F_RXCSUM)
1647                         tp->cp_cmd |= RxChkSum;
1648                 else
1649                         tp->cp_cmd &= ~RxChkSum;
1650
1651                 if (dev->features & NETIF_F_HW_VLAN_RX)
1652                         tp->cp_cmd |= RxVlan;
1653                 else
1654                         tp->cp_cmd &= ~RxVlan;
1655
1656                 RTL_W16(CPlusCmd, tp->cp_cmd);
1657                 RTL_R16(CPlusCmd);
1658         }
1659         if (changed & NETIF_F_RXALL) {
1660                 int tmp = (RTL_R32(RxConfig) & ~(AcceptErr | AcceptRunt));
1661                 if (features & NETIF_F_RXALL)
1662                         tmp |= (AcceptErr | AcceptRunt);
1663                 RTL_W32(RxConfig, tmp);
1664         }
1665 }
1666
1667 static int rtl8169_set_features(struct net_device *dev,
1668                                 netdev_features_t features)
1669 {
1670         struct rtl8169_private *tp = netdev_priv(dev);
1671
1672         rtl_lock_work(tp);
1673         __rtl8169_set_features(dev, features);
1674         rtl_unlock_work(tp);
1675
1676         return 0;
1677 }
1678
1679
1680 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1681                                       struct sk_buff *skb)
1682 {
1683         return (vlan_tx_tag_present(skb)) ?
1684                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1685 }
1686
1687 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1688 {
1689         u32 opts2 = le32_to_cpu(desc->opts2);
1690
1691         if (opts2 & RxVlanTag)
1692                 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
1693
1694         desc->opts2 = 0;
1695 }
1696
1697 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1698 {
1699         struct rtl8169_private *tp = netdev_priv(dev);
1700         void __iomem *ioaddr = tp->mmio_addr;
1701         u32 status;
1702
1703         cmd->supported =
1704                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1705         cmd->port = PORT_FIBRE;
1706         cmd->transceiver = XCVR_INTERNAL;
1707
1708         status = RTL_R32(TBICSR);
1709         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
1710         cmd->autoneg = !!(status & TBINwEnable);
1711
1712         ethtool_cmd_speed_set(cmd, SPEED_1000);
1713         cmd->duplex = DUPLEX_FULL; /* Always set */
1714
1715         return 0;
1716 }
1717
1718 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1719 {
1720         struct rtl8169_private *tp = netdev_priv(dev);
1721
1722         return mii_ethtool_gset(&tp->mii, cmd);
1723 }
1724
1725 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1726 {
1727         struct rtl8169_private *tp = netdev_priv(dev);
1728         int rc;
1729
1730         rtl_lock_work(tp);
1731         rc = tp->get_settings(dev, cmd);
1732         rtl_unlock_work(tp);
1733
1734         return rc;
1735 }
1736
1737 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1738                              void *p)
1739 {
1740         struct rtl8169_private *tp = netdev_priv(dev);
1741
1742         if (regs->len > R8169_REGS_SIZE)
1743                 regs->len = R8169_REGS_SIZE;
1744
1745         rtl_lock_work(tp);
1746         memcpy_fromio(p, tp->mmio_addr, regs->len);
1747         rtl_unlock_work(tp);
1748 }
1749
1750 static u32 rtl8169_get_msglevel(struct net_device *dev)
1751 {
1752         struct rtl8169_private *tp = netdev_priv(dev);
1753
1754         return tp->msg_enable;
1755 }
1756
1757 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1758 {
1759         struct rtl8169_private *tp = netdev_priv(dev);
1760
1761         tp->msg_enable = value;
1762 }
1763
1764 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1765         "tx_packets",
1766         "rx_packets",
1767         "tx_errors",
1768         "rx_errors",
1769         "rx_missed",
1770         "align_errors",
1771         "tx_single_collisions",
1772         "tx_multi_collisions",
1773         "unicast",
1774         "broadcast",
1775         "multicast",
1776         "tx_aborted",
1777         "tx_underrun",
1778 };
1779
1780 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1781 {
1782         switch (sset) {
1783         case ETH_SS_STATS:
1784                 return ARRAY_SIZE(rtl8169_gstrings);
1785         default:
1786                 return -EOPNOTSUPP;
1787         }
1788 }
1789
1790 static void rtl8169_update_counters(struct net_device *dev)
1791 {
1792         struct rtl8169_private *tp = netdev_priv(dev);
1793         void __iomem *ioaddr = tp->mmio_addr;
1794         struct device *d = &tp->pci_dev->dev;
1795         struct rtl8169_counters *counters;
1796         dma_addr_t paddr;
1797         u32 cmd;
1798         int wait = 1000;
1799
1800         /*
1801          * Some chips are unable to dump tally counters when the receiver
1802          * is disabled.
1803          */
1804         if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1805                 return;
1806
1807         counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1808         if (!counters)
1809                 return;
1810
1811         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1812         cmd = (u64)paddr & DMA_BIT_MASK(32);
1813         RTL_W32(CounterAddrLow, cmd);
1814         RTL_W32(CounterAddrLow, cmd | CounterDump);
1815
1816         while (wait--) {
1817                 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1818                         memcpy(&tp->counters, counters, sizeof(*counters));
1819                         break;
1820                 }
1821                 udelay(10);
1822         }
1823
1824         RTL_W32(CounterAddrLow, 0);
1825         RTL_W32(CounterAddrHigh, 0);
1826
1827         dma_free_coherent(d, sizeof(*counters), counters, paddr);
1828 }
1829
1830 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1831                                       struct ethtool_stats *stats, u64 *data)
1832 {
1833         struct rtl8169_private *tp = netdev_priv(dev);
1834
1835         ASSERT_RTNL();
1836
1837         rtl8169_update_counters(dev);
1838
1839         data[0] = le64_to_cpu(tp->counters.tx_packets);
1840         data[1] = le64_to_cpu(tp->counters.rx_packets);
1841         data[2] = le64_to_cpu(tp->counters.tx_errors);
1842         data[3] = le32_to_cpu(tp->counters.rx_errors);
1843         data[4] = le16_to_cpu(tp->counters.rx_missed);
1844         data[5] = le16_to_cpu(tp->counters.align_errors);
1845         data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1846         data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1847         data[8] = le64_to_cpu(tp->counters.rx_unicast);
1848         data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1849         data[10] = le32_to_cpu(tp->counters.rx_multicast);
1850         data[11] = le16_to_cpu(tp->counters.tx_aborted);
1851         data[12] = le16_to_cpu(tp->counters.tx_underun);
1852 }
1853
1854 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1855 {
1856         switch(stringset) {
1857         case ETH_SS_STATS:
1858                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1859                 break;
1860         }
1861 }
1862
1863 static const struct ethtool_ops rtl8169_ethtool_ops = {
1864         .get_drvinfo            = rtl8169_get_drvinfo,
1865         .get_regs_len           = rtl8169_get_regs_len,
1866         .get_link               = ethtool_op_get_link,
1867         .get_settings           = rtl8169_get_settings,
1868         .set_settings           = rtl8169_set_settings,
1869         .get_msglevel           = rtl8169_get_msglevel,
1870         .set_msglevel           = rtl8169_set_msglevel,
1871         .get_regs               = rtl8169_get_regs,
1872         .get_wol                = rtl8169_get_wol,
1873         .set_wol                = rtl8169_set_wol,
1874         .get_strings            = rtl8169_get_strings,
1875         .get_sset_count         = rtl8169_get_sset_count,
1876         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1877 };
1878
1879 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1880                                     struct net_device *dev, u8 default_version)
1881 {
1882         void __iomem *ioaddr = tp->mmio_addr;
1883         /*
1884          * The driver currently handles the 8168Bf and the 8168Be identically
1885          * but they can be identified more specifically through the test below
1886          * if needed:
1887          *
1888          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1889          *
1890          * Same thing for the 8101Eb and the 8101Ec:
1891          *
1892          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1893          */
1894         static const struct rtl_mac_info {
1895                 u32 mask;
1896                 u32 val;
1897                 int mac_version;
1898         } mac_info[] = {
1899                 /* 8168F family. */
1900                 { 0x7cf00000, 0x48100000,       RTL_GIGA_MAC_VER_36 },
1901                 { 0x7cf00000, 0x48000000,       RTL_GIGA_MAC_VER_35 },
1902
1903                 /* 8168E family. */
1904                 { 0x7c800000, 0x2c800000,       RTL_GIGA_MAC_VER_34 },
1905                 { 0x7cf00000, 0x2c200000,       RTL_GIGA_MAC_VER_33 },
1906                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
1907                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
1908
1909                 /* 8168D family. */
1910                 { 0x7cf00000, 0x28300000,       RTL_GIGA_MAC_VER_26 },
1911                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
1912                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
1913
1914                 /* 8168DP family. */
1915                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
1916                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
1917                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
1918
1919                 /* 8168C family. */
1920                 { 0x7cf00000, 0x3cb00000,       RTL_GIGA_MAC_VER_24 },
1921                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
1922                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
1923                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
1924                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
1925                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
1926                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
1927                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
1928                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
1929
1930                 /* 8168B family. */
1931                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
1932                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
1933                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
1934                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
1935
1936                 /* 8101 family. */
1937                 { 0x7cf00000, 0x40b00000,       RTL_GIGA_MAC_VER_30 },
1938                 { 0x7cf00000, 0x40a00000,       RTL_GIGA_MAC_VER_30 },
1939                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
1940                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
1941                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
1942                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
1943                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
1944                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
1945                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
1946                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
1947                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
1948                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
1949                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
1950                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
1951                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
1952                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
1953                 /* FIXME: where did these entries come from ? -- FR */
1954                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
1955                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
1956
1957                 /* 8110 family. */
1958                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
1959                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
1960                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
1961                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
1962                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
1963                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
1964
1965                 /* Catch-all */
1966                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
1967         };
1968         const struct rtl_mac_info *p = mac_info;
1969         u32 reg;
1970
1971         reg = RTL_R32(TxConfig);
1972         while ((reg & p->mask) != p->val)
1973                 p++;
1974         tp->mac_version = p->mac_version;
1975
1976         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
1977                 netif_notice(tp, probe, dev,
1978                              "unknown MAC, using family default\n");
1979                 tp->mac_version = default_version;
1980         }
1981 }
1982
1983 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1984 {
1985         dprintk("mac_version = 0x%02x\n", tp->mac_version);
1986 }
1987
1988 struct phy_reg {
1989         u16 reg;
1990         u16 val;
1991 };
1992
1993 static void rtl_writephy_batch(struct rtl8169_private *tp,
1994                                const struct phy_reg *regs, int len)
1995 {
1996         while (len-- > 0) {
1997                 rtl_writephy(tp, regs->reg, regs->val);
1998                 regs++;
1999         }
2000 }
2001
2002 #define PHY_READ                0x00000000
2003 #define PHY_DATA_OR             0x10000000
2004 #define PHY_DATA_AND            0x20000000
2005 #define PHY_BJMPN               0x30000000
2006 #define PHY_READ_EFUSE          0x40000000
2007 #define PHY_READ_MAC_BYTE       0x50000000
2008 #define PHY_WRITE_MAC_BYTE      0x60000000
2009 #define PHY_CLEAR_READCOUNT     0x70000000
2010 #define PHY_WRITE               0x80000000
2011 #define PHY_READCOUNT_EQ_SKIP   0x90000000
2012 #define PHY_COMP_EQ_SKIPN       0xa0000000
2013 #define PHY_COMP_NEQ_SKIPN      0xb0000000
2014 #define PHY_WRITE_PREVIOUS      0xc0000000
2015 #define PHY_SKIPN               0xd0000000
2016 #define PHY_DELAY_MS            0xe0000000
2017 #define PHY_WRITE_ERI_WORD      0xf0000000
2018
2019 struct fw_info {
2020         u32     magic;
2021         char    version[RTL_VER_SIZE];
2022         __le32  fw_start;
2023         __le32  fw_len;
2024         u8      chksum;
2025 } __packed;
2026
2027 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2028
2029 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2030 {
2031         const struct firmware *fw = rtl_fw->fw;
2032         struct fw_info *fw_info = (struct fw_info *)fw->data;
2033         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2034         char *version = rtl_fw->version;
2035         bool rc = false;
2036
2037         if (fw->size < FW_OPCODE_SIZE)
2038                 goto out;
2039
2040         if (!fw_info->magic) {
2041                 size_t i, size, start;
2042                 u8 checksum = 0;
2043
2044                 if (fw->size < sizeof(*fw_info))
2045                         goto out;
2046
2047                 for (i = 0; i < fw->size; i++)
2048                         checksum += fw->data[i];
2049                 if (checksum != 0)
2050                         goto out;
2051
2052                 start = le32_to_cpu(fw_info->fw_start);
2053                 if (start > fw->size)
2054                         goto out;
2055
2056                 size = le32_to_cpu(fw_info->fw_len);
2057                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2058                         goto out;
2059
2060                 memcpy(version, fw_info->version, RTL_VER_SIZE);
2061
2062                 pa->code = (__le32 *)(fw->data + start);
2063                 pa->size = size;
2064         } else {
2065                 if (fw->size % FW_OPCODE_SIZE)
2066                         goto out;
2067
2068                 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2069
2070                 pa->code = (__le32 *)fw->data;
2071                 pa->size = fw->size / FW_OPCODE_SIZE;
2072         }
2073         version[RTL_VER_SIZE - 1] = 0;
2074
2075         rc = true;
2076 out:
2077         return rc;
2078 }
2079
2080 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2081                            struct rtl_fw_phy_action *pa)
2082 {
2083         bool rc = false;
2084         size_t index;
2085
2086         for (index = 0; index < pa->size; index++) {
2087                 u32 action = le32_to_cpu(pa->code[index]);
2088                 u32 regno = (action & 0x0fff0000) >> 16;
2089
2090                 switch(action & 0xf0000000) {
2091                 case PHY_READ:
2092                 case PHY_DATA_OR:
2093                 case PHY_DATA_AND:
2094                 case PHY_READ_EFUSE:
2095                 case PHY_CLEAR_READCOUNT:
2096                 case PHY_WRITE:
2097                 case PHY_WRITE_PREVIOUS:
2098                 case PHY_DELAY_MS:
2099                         break;
2100
2101                 case PHY_BJMPN:
2102                         if (regno > index) {
2103                                 netif_err(tp, ifup, tp->dev,
2104                                           "Out of range of firmware\n");
2105                                 goto out;
2106                         }
2107                         break;
2108                 case PHY_READCOUNT_EQ_SKIP:
2109                         if (index + 2 >= pa->size) {
2110                                 netif_err(tp, ifup, tp->dev,
2111                                           "Out of range of firmware\n");
2112                                 goto out;
2113                         }
2114                         break;
2115                 case PHY_COMP_EQ_SKIPN:
2116                 case PHY_COMP_NEQ_SKIPN:
2117                 case PHY_SKIPN:
2118                         if (index + 1 + regno >= pa->size) {
2119                                 netif_err(tp, ifup, tp->dev,
2120                                           "Out of range of firmware\n");
2121                                 goto out;
2122                         }
2123                         break;
2124
2125                 case PHY_READ_MAC_BYTE:
2126                 case PHY_WRITE_MAC_BYTE:
2127                 case PHY_WRITE_ERI_WORD:
2128                 default:
2129                         netif_err(tp, ifup, tp->dev,
2130                                   "Invalid action 0x%08x\n", action);
2131                         goto out;
2132                 }
2133         }
2134         rc = true;
2135 out:
2136         return rc;
2137 }
2138
2139 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2140 {
2141         struct net_device *dev = tp->dev;
2142         int rc = -EINVAL;
2143
2144         if (!rtl_fw_format_ok(tp, rtl_fw)) {
2145                 netif_err(tp, ifup, dev, "invalid firwmare\n");
2146                 goto out;
2147         }
2148
2149         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2150                 rc = 0;
2151 out:
2152         return rc;
2153 }
2154
2155 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2156 {
2157         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2158         u32 predata, count;
2159         size_t index;
2160
2161         predata = count = 0;
2162
2163         for (index = 0; index < pa->size; ) {
2164                 u32 action = le32_to_cpu(pa->code[index]);
2165                 u32 data = action & 0x0000ffff;
2166                 u32 regno = (action & 0x0fff0000) >> 16;
2167
2168                 if (!action)
2169                         break;
2170
2171                 switch(action & 0xf0000000) {
2172                 case PHY_READ:
2173                         predata = rtl_readphy(tp, regno);
2174                         count++;
2175                         index++;
2176                         break;
2177                 case PHY_DATA_OR:
2178                         predata |= data;
2179                         index++;
2180                         break;
2181                 case PHY_DATA_AND:
2182                         predata &= data;
2183                         index++;
2184                         break;
2185                 case PHY_BJMPN:
2186                         index -= regno;
2187                         break;
2188                 case PHY_READ_EFUSE:
2189                         predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
2190                         index++;
2191                         break;
2192                 case PHY_CLEAR_READCOUNT:
2193                         count = 0;
2194                         index++;
2195                         break;
2196                 case PHY_WRITE:
2197                         rtl_writephy(tp, regno, data);
2198                         index++;
2199                         break;
2200                 case PHY_READCOUNT_EQ_SKIP:
2201                         index += (count == data) ? 2 : 1;
2202                         break;
2203                 case PHY_COMP_EQ_SKIPN:
2204                         if (predata == data)
2205                                 index += regno;
2206                         index++;
2207                         break;
2208                 case PHY_COMP_NEQ_SKIPN:
2209                         if (predata != data)
2210                                 index += regno;
2211                         index++;
2212                         break;
2213                 case PHY_WRITE_PREVIOUS:
2214                         rtl_writephy(tp, regno, predata);
2215                         index++;
2216                         break;
2217                 case PHY_SKIPN:
2218                         index += regno + 1;
2219                         break;
2220                 case PHY_DELAY_MS:
2221                         mdelay(data);
2222                         index++;
2223                         break;
2224
2225                 case PHY_READ_MAC_BYTE:
2226                 case PHY_WRITE_MAC_BYTE:
2227                 case PHY_WRITE_ERI_WORD:
2228                 default:
2229                         BUG();
2230                 }
2231         }
2232 }
2233
2234 static void rtl_release_firmware(struct rtl8169_private *tp)
2235 {
2236         if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2237                 release_firmware(tp->rtl_fw->fw);
2238                 kfree(tp->rtl_fw);
2239         }
2240         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2241 }
2242
2243 static void rtl_apply_firmware(struct rtl8169_private *tp)
2244 {
2245         struct rtl_fw *rtl_fw = tp->rtl_fw;
2246
2247         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2248         if (!IS_ERR_OR_NULL(rtl_fw))
2249                 rtl_phy_write_fw(tp, rtl_fw);
2250 }
2251
2252 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2253 {
2254         if (rtl_readphy(tp, reg) != val)
2255                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2256         else
2257                 rtl_apply_firmware(tp);
2258 }
2259
2260 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2261 {
2262         static const struct phy_reg phy_reg_init[] = {
2263                 { 0x1f, 0x0001 },
2264                 { 0x06, 0x006e },
2265                 { 0x08, 0x0708 },
2266                 { 0x15, 0x4000 },
2267                 { 0x18, 0x65c7 },
2268
2269                 { 0x1f, 0x0001 },
2270                 { 0x03, 0x00a1 },
2271                 { 0x02, 0x0008 },
2272                 { 0x01, 0x0120 },
2273                 { 0x00, 0x1000 },
2274                 { 0x04, 0x0800 },
2275                 { 0x04, 0x0000 },
2276
2277                 { 0x03, 0xff41 },
2278                 { 0x02, 0xdf60 },
2279                 { 0x01, 0x0140 },
2280                 { 0x00, 0x0077 },
2281                 { 0x04, 0x7800 },
2282                 { 0x04, 0x7000 },
2283
2284                 { 0x03, 0x802f },
2285                 { 0x02, 0x4f02 },
2286                 { 0x01, 0x0409 },
2287                 { 0x00, 0xf0f9 },
2288                 { 0x04, 0x9800 },
2289                 { 0x04, 0x9000 },
2290
2291                 { 0x03, 0xdf01 },
2292                 { 0x02, 0xdf20 },
2293                 { 0x01, 0xff95 },
2294                 { 0x00, 0xba00 },
2295                 { 0x04, 0xa800 },
2296                 { 0x04, 0xa000 },
2297
2298                 { 0x03, 0xff41 },
2299                 { 0x02, 0xdf20 },
2300                 { 0x01, 0x0140 },
2301                 { 0x00, 0x00bb },
2302                 { 0x04, 0xb800 },
2303                 { 0x04, 0xb000 },
2304
2305                 { 0x03, 0xdf41 },
2306                 { 0x02, 0xdc60 },
2307                 { 0x01, 0x6340 },
2308                 { 0x00, 0x007d },
2309                 { 0x04, 0xd800 },
2310                 { 0x04, 0xd000 },
2311
2312                 { 0x03, 0xdf01 },
2313                 { 0x02, 0xdf20 },
2314                 { 0x01, 0x100a },
2315                 { 0x00, 0xa0ff },
2316                 { 0x04, 0xf800 },
2317                 { 0x04, 0xf000 },
2318
2319                 { 0x1f, 0x0000 },
2320                 { 0x0b, 0x0000 },
2321                 { 0x00, 0x9200 }
2322         };
2323
2324         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2325 }
2326
2327 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2328 {
2329         static const struct phy_reg phy_reg_init[] = {
2330                 { 0x1f, 0x0002 },
2331                 { 0x01, 0x90d0 },
2332                 { 0x1f, 0x0000 }
2333         };
2334
2335         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2336 }
2337
2338 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2339 {
2340         struct pci_dev *pdev = tp->pci_dev;
2341
2342         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2343             (pdev->subsystem_device != 0xe000))
2344                 return;
2345
2346         rtl_writephy(tp, 0x1f, 0x0001);
2347         rtl_writephy(tp, 0x10, 0xf01b);
2348         rtl_writephy(tp, 0x1f, 0x0000);
2349 }
2350
2351 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2352 {
2353         static const struct phy_reg phy_reg_init[] = {
2354                 { 0x1f, 0x0001 },
2355                 { 0x04, 0x0000 },
2356                 { 0x03, 0x00a1 },
2357                 { 0x02, 0x0008 },
2358                 { 0x01, 0x0120 },
2359                 { 0x00, 0x1000 },
2360                 { 0x04, 0x0800 },
2361                 { 0x04, 0x9000 },
2362                 { 0x03, 0x802f },
2363                 { 0x02, 0x4f02 },
2364                 { 0x01, 0x0409 },
2365                 { 0x00, 0xf099 },
2366                 { 0x04, 0x9800 },
2367                 { 0x04, 0xa000 },
2368                 { 0x03, 0xdf01 },
2369                 { 0x02, 0xdf20 },
2370                 { 0x01, 0xff95 },
2371                 { 0x00, 0xba00 },
2372                 { 0x04, 0xa800 },
2373                 { 0x04, 0xf000 },
2374                 { 0x03, 0xdf01 },
2375                 { 0x02, 0xdf20 },
2376                 { 0x01, 0x101a },
2377                 { 0x00, 0xa0ff },
2378                 { 0x04, 0xf800 },
2379                 { 0x04, 0x0000 },
2380                 { 0x1f, 0x0000 },
2381
2382                 { 0x1f, 0x0001 },
2383                 { 0x10, 0xf41b },
2384                 { 0x14, 0xfb54 },
2385                 { 0x18, 0xf5c7 },
2386                 { 0x1f, 0x0000 },
2387
2388                 { 0x1f, 0x0001 },
2389                 { 0x17, 0x0cc0 },
2390                 { 0x1f, 0x0000 }
2391         };
2392
2393         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2394
2395         rtl8169scd_hw_phy_config_quirk(tp);
2396 }
2397
2398 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2399 {
2400         static const struct phy_reg phy_reg_init[] = {
2401                 { 0x1f, 0x0001 },
2402                 { 0x04, 0x0000 },
2403                 { 0x03, 0x00a1 },
2404                 { 0x02, 0x0008 },
2405                 { 0x01, 0x0120 },
2406                 { 0x00, 0x1000 },
2407                 { 0x04, 0x0800 },
2408                 { 0x04, 0x9000 },
2409                 { 0x03, 0x802f },
2410                 { 0x02, 0x4f02 },
2411                 { 0x01, 0x0409 },
2412                 { 0x00, 0xf099 },
2413                 { 0x04, 0x9800 },
2414                 { 0x04, 0xa000 },
2415                 { 0x03, 0xdf01 },
2416                 { 0x02, 0xdf20 },
2417                 { 0x01, 0xff95 },
2418                 { 0x00, 0xba00 },
2419                 { 0x04, 0xa800 },
2420                 { 0x04, 0xf000 },
2421                 { 0x03, 0xdf01 },
2422                 { 0x02, 0xdf20 },
2423                 { 0x01, 0x101a },
2424                 { 0x00, 0xa0ff },
2425                 { 0x04, 0xf800 },
2426                 { 0x04, 0x0000 },
2427                 { 0x1f, 0x0000 },
2428
2429                 { 0x1f, 0x0001 },
2430                 { 0x0b, 0x8480 },
2431                 { 0x1f, 0x0000 },
2432
2433                 { 0x1f, 0x0001 },
2434                 { 0x18, 0x67c7 },
2435                 { 0x04, 0x2000 },
2436                 { 0x03, 0x002f },
2437                 { 0x02, 0x4360 },
2438                 { 0x01, 0x0109 },
2439                 { 0x00, 0x3022 },
2440                 { 0x04, 0x2800 },
2441                 { 0x1f, 0x0000 },
2442
2443                 { 0x1f, 0x0001 },
2444                 { 0x17, 0x0cc0 },
2445                 { 0x1f, 0x0000 }
2446         };
2447
2448         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2449 }
2450
2451 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2452 {
2453         static const struct phy_reg phy_reg_init[] = {
2454                 { 0x10, 0xf41b },
2455                 { 0x1f, 0x0000 }
2456         };
2457
2458         rtl_writephy(tp, 0x1f, 0x0001);
2459         rtl_patchphy(tp, 0x16, 1 << 0);
2460
2461         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2462 }
2463
2464 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2465 {
2466         static const struct phy_reg phy_reg_init[] = {
2467                 { 0x1f, 0x0001 },
2468                 { 0x10, 0xf41b },
2469                 { 0x1f, 0x0000 }
2470         };
2471
2472         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2473 }
2474
2475 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2476 {
2477         static const struct phy_reg phy_reg_init[] = {
2478                 { 0x1f, 0x0000 },
2479                 { 0x1d, 0x0f00 },
2480                 { 0x1f, 0x0002 },
2481                 { 0x0c, 0x1ec8 },
2482                 { 0x1f, 0x0000 }
2483         };
2484
2485         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2486 }
2487
2488 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2489 {
2490         static const struct phy_reg phy_reg_init[] = {
2491                 { 0x1f, 0x0001 },
2492                 { 0x1d, 0x3d98 },
2493                 { 0x1f, 0x0000 }
2494         };
2495
2496         rtl_writephy(tp, 0x1f, 0x0000);
2497         rtl_patchphy(tp, 0x14, 1 << 5);
2498         rtl_patchphy(tp, 0x0d, 1 << 5);
2499
2500         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2501 }
2502
2503 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2504 {
2505         static const struct phy_reg phy_reg_init[] = {
2506                 { 0x1f, 0x0001 },
2507                 { 0x12, 0x2300 },
2508                 { 0x1f, 0x0002 },
2509                 { 0x00, 0x88d4 },
2510                 { 0x01, 0x82b1 },
2511                 { 0x03, 0x7002 },
2512                 { 0x08, 0x9e30 },
2513                 { 0x09, 0x01f0 },
2514                 { 0x0a, 0x5500 },
2515                 { 0x0c, 0x00c8 },
2516                 { 0x1f, 0x0003 },
2517                 { 0x12, 0xc096 },
2518                 { 0x16, 0x000a },
2519                 { 0x1f, 0x0000 },
2520                 { 0x1f, 0x0000 },
2521                 { 0x09, 0x2000 },
2522                 { 0x09, 0x0000 }
2523         };
2524
2525         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2526
2527         rtl_patchphy(tp, 0x14, 1 << 5);
2528         rtl_patchphy(tp, 0x0d, 1 << 5);
2529         rtl_writephy(tp, 0x1f, 0x0000);
2530 }
2531
2532 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2533 {
2534         static const struct phy_reg phy_reg_init[] = {
2535                 { 0x1f, 0x0001 },
2536                 { 0x12, 0x2300 },
2537                 { 0x03, 0x802f },
2538                 { 0x02, 0x4f02 },
2539                 { 0x01, 0x0409 },
2540                 { 0x00, 0xf099 },
2541                 { 0x04, 0x9800 },
2542                 { 0x04, 0x9000 },
2543                 { 0x1d, 0x3d98 },
2544                 { 0x1f, 0x0002 },
2545                 { 0x0c, 0x7eb8 },
2546                 { 0x06, 0x0761 },
2547                 { 0x1f, 0x0003 },
2548                 { 0x16, 0x0f0a },
2549                 { 0x1f, 0x0000 }
2550         };
2551
2552         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2553
2554         rtl_patchphy(tp, 0x16, 1 << 0);
2555         rtl_patchphy(tp, 0x14, 1 << 5);
2556         rtl_patchphy(tp, 0x0d, 1 << 5);
2557         rtl_writephy(tp, 0x1f, 0x0000);
2558 }
2559
2560 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2561 {
2562         static const struct phy_reg phy_reg_init[] = {
2563                 { 0x1f, 0x0001 },
2564                 { 0x12, 0x2300 },
2565                 { 0x1d, 0x3d98 },
2566                 { 0x1f, 0x0002 },
2567                 { 0x0c, 0x7eb8 },
2568                 { 0x06, 0x5461 },
2569                 { 0x1f, 0x0003 },
2570                 { 0x16, 0x0f0a },
2571                 { 0x1f, 0x0000 }
2572         };
2573
2574         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2575
2576         rtl_patchphy(tp, 0x16, 1 << 0);
2577         rtl_patchphy(tp, 0x14, 1 << 5);
2578         rtl_patchphy(tp, 0x0d, 1 << 5);
2579         rtl_writephy(tp, 0x1f, 0x0000);
2580 }
2581
2582 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2583 {
2584         rtl8168c_3_hw_phy_config(tp);
2585 }
2586
2587 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2588 {
2589         static const struct phy_reg phy_reg_init_0[] = {
2590                 /* Channel Estimation */
2591                 { 0x1f, 0x0001 },
2592                 { 0x06, 0x4064 },
2593                 { 0x07, 0x2863 },
2594                 { 0x08, 0x059c },
2595                 { 0x09, 0x26b4 },
2596                 { 0x0a, 0x6a19 },
2597                 { 0x0b, 0xdcc8 },
2598                 { 0x10, 0xf06d },
2599                 { 0x14, 0x7f68 },
2600                 { 0x18, 0x7fd9 },
2601                 { 0x1c, 0xf0ff },
2602                 { 0x1d, 0x3d9c },
2603                 { 0x1f, 0x0003 },
2604                 { 0x12, 0xf49f },
2605                 { 0x13, 0x070b },
2606                 { 0x1a, 0x05ad },
2607                 { 0x14, 0x94c0 },
2608
2609                 /*
2610                  * Tx Error Issue
2611                  * Enhance line driver power
2612                  */
2613                 { 0x1f, 0x0002 },
2614                 { 0x06, 0x5561 },
2615                 { 0x1f, 0x0005 },
2616                 { 0x05, 0x8332 },
2617                 { 0x06, 0x5561 },
2618
2619                 /*
2620                  * Can not link to 1Gbps with bad cable
2621                  * Decrease SNR threshold form 21.07dB to 19.04dB
2622                  */
2623                 { 0x1f, 0x0001 },
2624                 { 0x17, 0x0cc0 },
2625
2626                 { 0x1f, 0x0000 },
2627                 { 0x0d, 0xf880 }
2628         };
2629         void __iomem *ioaddr = tp->mmio_addr;
2630
2631         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2632
2633         /*
2634          * Rx Error Issue
2635          * Fine Tune Switching regulator parameter
2636          */
2637         rtl_writephy(tp, 0x1f, 0x0002);
2638         rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2639         rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2640
2641         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2642                 static const struct phy_reg phy_reg_init[] = {
2643                         { 0x1f, 0x0002 },
2644                         { 0x05, 0x669a },
2645                         { 0x1f, 0x0005 },
2646                         { 0x05, 0x8330 },
2647                         { 0x06, 0x669a },
2648                         { 0x1f, 0x0002 }
2649                 };
2650                 int val;
2651
2652                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2653
2654                 val = rtl_readphy(tp, 0x0d);
2655
2656                 if ((val & 0x00ff) != 0x006c) {
2657                         static const u32 set[] = {
2658                                 0x0065, 0x0066, 0x0067, 0x0068,
2659                                 0x0069, 0x006a, 0x006b, 0x006c
2660                         };
2661                         int i;
2662
2663                         rtl_writephy(tp, 0x1f, 0x0002);
2664
2665                         val &= 0xff00;
2666                         for (i = 0; i < ARRAY_SIZE(set); i++)
2667                                 rtl_writephy(tp, 0x0d, val | set[i]);
2668                 }
2669         } else {
2670                 static const struct phy_reg phy_reg_init[] = {
2671                         { 0x1f, 0x0002 },
2672                         { 0x05, 0x6662 },
2673                         { 0x1f, 0x0005 },
2674                         { 0x05, 0x8330 },
2675                         { 0x06, 0x6662 }
2676                 };
2677
2678                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2679         }
2680
2681         /* RSET couple improve */
2682         rtl_writephy(tp, 0x1f, 0x0002);
2683         rtl_patchphy(tp, 0x0d, 0x0300);
2684         rtl_patchphy(tp, 0x0f, 0x0010);
2685
2686         /* Fine tune PLL performance */
2687         rtl_writephy(tp, 0x1f, 0x0002);
2688         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2689         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2690
2691         rtl_writephy(tp, 0x1f, 0x0005);
2692         rtl_writephy(tp, 0x05, 0x001b);
2693
2694         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2695
2696         rtl_writephy(tp, 0x1f, 0x0000);
2697 }
2698
2699 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2700 {
2701         static const struct phy_reg phy_reg_init_0[] = {
2702                 /* Channel Estimation */
2703                 { 0x1f, 0x0001 },
2704                 { 0x06, 0x4064 },
2705                 { 0x07, 0x2863 },
2706                 { 0x08, 0x059c },
2707                 { 0x09, 0x26b4 },
2708                 { 0x0a, 0x6a19 },
2709                 { 0x0b, 0xdcc8 },
2710                 { 0x10, 0xf06d },
2711                 { 0x14, 0x7f68 },
2712                 { 0x18, 0x7fd9 },
2713                 { 0x1c, 0xf0ff },
2714                 { 0x1d, 0x3d9c },
2715                 { 0x1f, 0x0003 },
2716                 { 0x12, 0xf49f },
2717                 { 0x13, 0x070b },
2718                 { 0x1a, 0x05ad },
2719                 { 0x14, 0x94c0 },
2720
2721                 /*
2722                  * Tx Error Issue
2723                  * Enhance line driver power
2724                  */
2725                 { 0x1f, 0x0002 },
2726                 { 0x06, 0x5561 },
2727                 { 0x1f, 0x0005 },
2728                 { 0x05, 0x8332 },
2729                 { 0x06, 0x5561 },
2730
2731                 /*
2732                  * Can not link to 1Gbps with bad cable
2733                  * Decrease SNR threshold form 21.07dB to 19.04dB
2734                  */
2735                 { 0x1f, 0x0001 },
2736                 { 0x17, 0x0cc0 },
2737
2738                 { 0x1f, 0x0000 },
2739                 { 0x0d, 0xf880 }
2740         };
2741         void __iomem *ioaddr = tp->mmio_addr;
2742
2743         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2744
2745         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2746                 static const struct phy_reg phy_reg_init[] = {
2747                         { 0x1f, 0x0002 },
2748                         { 0x05, 0x669a },
2749                         { 0x1f, 0x0005 },
2750                         { 0x05, 0x8330 },
2751                         { 0x06, 0x669a },
2752
2753                         { 0x1f, 0x0002 }
2754                 };
2755                 int val;
2756
2757                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2758
2759                 val = rtl_readphy(tp, 0x0d);
2760                 if ((val & 0x00ff) != 0x006c) {
2761                         static const u32 set[] = {
2762                                 0x0065, 0x0066, 0x0067, 0x0068,
2763                                 0x0069, 0x006a, 0x006b, 0x006c
2764                         };
2765                         int i;
2766
2767                         rtl_writephy(tp, 0x1f, 0x0002);
2768
2769                         val &= 0xff00;
2770                         for (i = 0; i < ARRAY_SIZE(set); i++)
2771                                 rtl_writephy(tp, 0x0d, val | set[i]);
2772                 }
2773         } else {
2774                 static const struct phy_reg phy_reg_init[] = {
2775                         { 0x1f, 0x0002 },
2776                         { 0x05, 0x2642 },
2777                         { 0x1f, 0x0005 },
2778                         { 0x05, 0x8330 },
2779                         { 0x06, 0x2642 }
2780                 };
2781
2782                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2783         }
2784
2785         /* Fine tune PLL performance */
2786         rtl_writephy(tp, 0x1f, 0x0002);
2787         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2788         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2789
2790         /* Switching regulator Slew rate */
2791         rtl_writephy(tp, 0x1f, 0x0002);
2792         rtl_patchphy(tp, 0x0f, 0x0017);
2793
2794         rtl_writephy(tp, 0x1f, 0x0005);
2795         rtl_writephy(tp, 0x05, 0x001b);
2796
2797         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2798
2799         rtl_writephy(tp, 0x1f, 0x0000);
2800 }
2801
2802 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2803 {
2804         static const struct phy_reg phy_reg_init[] = {
2805                 { 0x1f, 0x0002 },
2806                 { 0x10, 0x0008 },
2807                 { 0x0d, 0x006c },
2808
2809                 { 0x1f, 0x0000 },
2810                 { 0x0d, 0xf880 },
2811
2812                 { 0x1f, 0x0001 },
2813                 { 0x17, 0x0cc0 },
2814
2815                 { 0x1f, 0x0001 },
2816                 { 0x0b, 0xa4d8 },
2817                 { 0x09, 0x281c },
2818                 { 0x07, 0x2883 },
2819                 { 0x0a, 0x6b35 },
2820                 { 0x1d, 0x3da4 },
2821                 { 0x1c, 0xeffd },
2822                 { 0x14, 0x7f52 },
2823                 { 0x18, 0x7fc6 },
2824                 { 0x08, 0x0601 },
2825                 { 0x06, 0x4063 },
2826                 { 0x10, 0xf074 },
2827                 { 0x1f, 0x0003 },
2828                 { 0x13, 0x0789 },
2829                 { 0x12, 0xf4bd },
2830                 { 0x1a, 0x04fd },
2831                 { 0x14, 0x84b0 },
2832                 { 0x1f, 0x0000 },
2833                 { 0x00, 0x9200 },
2834
2835                 { 0x1f, 0x0005 },
2836                 { 0x01, 0x0340 },
2837                 { 0x1f, 0x0001 },
2838                 { 0x04, 0x4000 },
2839                 { 0x03, 0x1d21 },
2840                 { 0x02, 0x0c32 },
2841                 { 0x01, 0x0200 },
2842                 { 0x00, 0x5554 },
2843                 { 0x04, 0x4800 },
2844                 { 0x04, 0x4000 },
2845                 { 0x04, 0xf000 },
2846                 { 0x03, 0xdf01 },
2847                 { 0x02, 0xdf20 },
2848                 { 0x01, 0x101a },
2849                 { 0x00, 0xa0ff },
2850                 { 0x04, 0xf800 },
2851                 { 0x04, 0xf000 },
2852                 { 0x1f, 0x0000 },
2853
2854                 { 0x1f, 0x0007 },
2855                 { 0x1e, 0x0023 },
2856                 { 0x16, 0x0000 },
2857                 { 0x1f, 0x0000 }
2858         };
2859
2860         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2861 }
2862
2863 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2864 {
2865         static const struct phy_reg phy_reg_init[] = {
2866                 { 0x1f, 0x0001 },
2867                 { 0x17, 0x0cc0 },
2868
2869                 { 0x1f, 0x0007 },
2870                 { 0x1e, 0x002d },
2871                 { 0x18, 0x0040 },
2872                 { 0x1f, 0x0000 }
2873         };
2874
2875         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2876         rtl_patchphy(tp, 0x0d, 1 << 5);
2877 }
2878
2879 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
2880 {
2881         static const struct phy_reg phy_reg_init[] = {
2882                 /* Enable Delay cap */
2883                 { 0x1f, 0x0005 },
2884                 { 0x05, 0x8b80 },
2885                 { 0x06, 0xc896 },
2886                 { 0x1f, 0x0000 },
2887
2888                 /* Channel estimation fine tune */
2889                 { 0x1f, 0x0001 },
2890                 { 0x0b, 0x6c20 },
2891                 { 0x07, 0x2872 },
2892                 { 0x1c, 0xefff },
2893                 { 0x1f, 0x0003 },
2894                 { 0x14, 0x6420 },
2895                 { 0x1f, 0x0000 },
2896
2897                 /* Update PFM & 10M TX idle timer */
2898                 { 0x1f, 0x0007 },
2899                 { 0x1e, 0x002f },
2900                 { 0x15, 0x1919 },
2901                 { 0x1f, 0x0000 },
2902
2903                 { 0x1f, 0x0007 },
2904                 { 0x1e, 0x00ac },
2905                 { 0x18, 0x0006 },
2906                 { 0x1f, 0x0000 }
2907         };
2908
2909         rtl_apply_firmware(tp);
2910
2911         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2912
2913         /* DCO enable for 10M IDLE Power */
2914         rtl_writephy(tp, 0x1f, 0x0007);
2915         rtl_writephy(tp, 0x1e, 0x0023);
2916         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2917         rtl_writephy(tp, 0x1f, 0x0000);
2918
2919         /* For impedance matching */
2920         rtl_writephy(tp, 0x1f, 0x0002);
2921         rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
2922         rtl_writephy(tp, 0x1f, 0x0000);
2923
2924         /* PHY auto speed down */
2925         rtl_writephy(tp, 0x1f, 0x0007);
2926         rtl_writephy(tp, 0x1e, 0x002d);
2927         rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2928         rtl_writephy(tp, 0x1f, 0x0000);
2929         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2930
2931         rtl_writephy(tp, 0x1f, 0x0005);
2932         rtl_writephy(tp, 0x05, 0x8b86);
2933         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2934         rtl_writephy(tp, 0x1f, 0x0000);
2935
2936         rtl_writephy(tp, 0x1f, 0x0005);
2937         rtl_writephy(tp, 0x05, 0x8b85);
2938         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2939         rtl_writephy(tp, 0x1f, 0x0007);
2940         rtl_writephy(tp, 0x1e, 0x0020);
2941         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2942         rtl_writephy(tp, 0x1f, 0x0006);
2943         rtl_writephy(tp, 0x00, 0x5a00);
2944         rtl_writephy(tp, 0x1f, 0x0000);
2945         rtl_writephy(tp, 0x0d, 0x0007);
2946         rtl_writephy(tp, 0x0e, 0x003c);
2947         rtl_writephy(tp, 0x0d, 0x4007);
2948         rtl_writephy(tp, 0x0e, 0x0000);
2949         rtl_writephy(tp, 0x0d, 0x0000);
2950 }
2951
2952 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
2953 {
2954         static const struct phy_reg phy_reg_init[] = {
2955                 /* Enable Delay cap */
2956                 { 0x1f, 0x0004 },
2957                 { 0x1f, 0x0007 },
2958                 { 0x1e, 0x00ac },
2959                 { 0x18, 0x0006 },
2960                 { 0x1f, 0x0002 },
2961                 { 0x1f, 0x0000 },
2962                 { 0x1f, 0x0000 },
2963
2964                 /* Channel estimation fine tune */
2965                 { 0x1f, 0x0003 },
2966                 { 0x09, 0xa20f },
2967                 { 0x1f, 0x0000 },
2968                 { 0x1f, 0x0000 },
2969
2970                 /* Green Setting */
2971                 { 0x1f, 0x0005 },
2972                 { 0x05, 0x8b5b },
2973                 { 0x06, 0x9222 },
2974                 { 0x05, 0x8b6d },
2975                 { 0x06, 0x8000 },
2976                 { 0x05, 0x8b76 },
2977                 { 0x06, 0x8000 },
2978                 { 0x1f, 0x0000 }
2979         };
2980
2981         rtl_apply_firmware(tp);
2982
2983         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2984
2985         /* For 4-corner performance improve */
2986         rtl_writephy(tp, 0x1f, 0x0005);
2987         rtl_writephy(tp, 0x05, 0x8b80);
2988         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2989         rtl_writephy(tp, 0x1f, 0x0000);
2990
2991         /* PHY auto speed down */
2992         rtl_writephy(tp, 0x1f, 0x0004);
2993         rtl_writephy(tp, 0x1f, 0x0007);
2994         rtl_writephy(tp, 0x1e, 0x002d);
2995         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
2996         rtl_writephy(tp, 0x1f, 0x0002);
2997         rtl_writephy(tp, 0x1f, 0x0000);
2998         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2999
3000         /* improve 10M EEE waveform */
3001         rtl_writephy(tp, 0x1f, 0x0005);
3002         rtl_writephy(tp, 0x05, 0x8b86);
3003         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3004         rtl_writephy(tp, 0x1f, 0x0000);
3005
3006         /* Improve 2-pair detection performance */
3007         rtl_writephy(tp, 0x1f, 0x0005);
3008         rtl_writephy(tp, 0x05, 0x8b85);
3009         rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3010         rtl_writephy(tp, 0x1f, 0x0000);
3011
3012         /* EEE setting */
3013         rtl_w1w0_eri(tp->mmio_addr, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003,
3014                      ERIAR_EXGMAC);
3015         rtl_writephy(tp, 0x1f, 0x0005);
3016         rtl_writephy(tp, 0x05, 0x8b85);
3017         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3018         rtl_writephy(tp, 0x1f, 0x0004);
3019         rtl_writephy(tp, 0x1f, 0x0007);
3020         rtl_writephy(tp, 0x1e, 0x0020);
3021         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
3022         rtl_writephy(tp, 0x1f, 0x0002);
3023         rtl_writephy(tp, 0x1f, 0x0000);
3024         rtl_writephy(tp, 0x0d, 0x0007);
3025         rtl_writephy(tp, 0x0e, 0x003c);
3026         rtl_writephy(tp, 0x0d, 0x4007);
3027         rtl_writephy(tp, 0x0e, 0x0000);
3028         rtl_writephy(tp, 0x0d, 0x0000);
3029
3030         /* Green feature */
3031         rtl_writephy(tp, 0x1f, 0x0003);
3032         rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3033         rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3034         rtl_writephy(tp, 0x1f, 0x0000);
3035 }
3036
3037 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3038 {
3039         static const struct phy_reg phy_reg_init[] = {
3040                 /* Channel estimation fine tune */
3041                 { 0x1f, 0x0003 },
3042                 { 0x09, 0xa20f },
3043                 { 0x1f, 0x0000 },
3044
3045                 /* Modify green table for giga & fnet */
3046                 { 0x1f, 0x0005 },
3047                 { 0x05, 0x8b55 },
3048                 { 0x06, 0x0000 },
3049                 { 0x05, 0x8b5e },
3050                 { 0x06, 0x0000 },
3051                 { 0x05, 0x8b67 },
3052                 { 0x06, 0x0000 },
3053                 { 0x05, 0x8b70 },
3054                 { 0x06, 0x0000 },
3055                 { 0x1f, 0x0000 },
3056                 { 0x1f, 0x0007 },
3057                 { 0x1e, 0x0078 },
3058                 { 0x17, 0x0000 },
3059                 { 0x19, 0x00fb },
3060                 { 0x1f, 0x0000 },
3061
3062                 /* Modify green table for 10M */
3063                 { 0x1f, 0x0005 },
3064                 { 0x05, 0x8b79 },
3065                 { 0x06, 0xaa00 },
3066                 { 0x1f, 0x0000 },
3067
3068                 /* Disable hiimpedance detection (RTCT) */
3069                 { 0x1f, 0x0003 },
3070                 { 0x01, 0x328a },
3071                 { 0x1f, 0x0000 }
3072         };
3073
3074         rtl_apply_firmware(tp);
3075
3076         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3077
3078         /* For 4-corner performance improve */
3079         rtl_writephy(tp, 0x1f, 0x0005);
3080         rtl_writephy(tp, 0x05, 0x8b80);
3081         rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3082         rtl_writephy(tp, 0x1f, 0x0000);
3083
3084         /* PHY auto speed down */
3085         rtl_writephy(tp, 0x1f, 0x0007);
3086         rtl_writephy(tp, 0x1e, 0x002d);
3087         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3088         rtl_writephy(tp, 0x1f, 0x0000);
3089         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3090
3091         /* Improve 10M EEE waveform */
3092         rtl_writephy(tp, 0x1f, 0x0005);
3093         rtl_writephy(tp, 0x05, 0x8b86);
3094         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3095         rtl_writephy(tp, 0x1f, 0x0000);
3096
3097         /* Improve 2-pair detection performance */
3098         rtl_writephy(tp, 0x1f, 0x0005);
3099         rtl_writephy(tp, 0x05, 0x8b85);
3100         rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3101         rtl_writephy(tp, 0x1f, 0x0000);
3102 }
3103
3104 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3105 {
3106         rtl_apply_firmware(tp);
3107
3108         /* For 4-corner performance improve */
3109         rtl_writephy(tp, 0x1f, 0x0005);
3110         rtl_writephy(tp, 0x05, 0x8b80);
3111         rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3112         rtl_writephy(tp, 0x1f, 0x0000);
3113
3114         /* PHY auto speed down */
3115         rtl_writephy(tp, 0x1f, 0x0007);
3116         rtl_writephy(tp, 0x1e, 0x002d);
3117         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3118         rtl_writephy(tp, 0x1f, 0x0000);
3119         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3120
3121         /* Improve 10M EEE waveform */
3122         rtl_writephy(tp, 0x1f, 0x0005);
3123         rtl_writephy(tp, 0x05, 0x8b86);
3124         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3125         rtl_writephy(tp, 0x1f, 0x0000);
3126 }
3127
3128 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3129 {
3130         static const struct phy_reg phy_reg_init[] = {
3131                 { 0x1f, 0x0003 },
3132                 { 0x08, 0x441d },
3133                 { 0x01, 0x9100 },
3134                 { 0x1f, 0x0000 }
3135         };
3136
3137         rtl_writephy(tp, 0x1f, 0x0000);
3138         rtl_patchphy(tp, 0x11, 1 << 12);
3139         rtl_patchphy(tp, 0x19, 1 << 13);
3140         rtl_patchphy(tp, 0x10, 1 << 15);
3141
3142         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3143 }
3144
3145 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3146 {
3147         static const struct phy_reg phy_reg_init[] = {
3148                 { 0x1f, 0x0005 },
3149                 { 0x1a, 0x0000 },
3150                 { 0x1f, 0x0000 },
3151
3152                 { 0x1f, 0x0004 },
3153                 { 0x1c, 0x0000 },
3154                 { 0x1f, 0x0000 },
3155
3156                 { 0x1f, 0x0001 },
3157                 { 0x15, 0x7701 },
3158                 { 0x1f, 0x0000 }
3159         };
3160
3161         /* Disable ALDPS before ram code */
3162         rtl_writephy(tp, 0x1f, 0x0000);
3163         rtl_writephy(tp, 0x18, 0x0310);
3164         msleep(100);
3165
3166         rtl_apply_firmware(tp);
3167
3168         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3169 }
3170
3171 static void rtl_hw_phy_config(struct net_device *dev)
3172 {
3173         struct rtl8169_private *tp = netdev_priv(dev);
3174
3175         rtl8169_print_mac_version(tp);
3176
3177         switch (tp->mac_version) {
3178         case RTL_GIGA_MAC_VER_01:
3179                 break;
3180         case RTL_GIGA_MAC_VER_02:
3181         case RTL_GIGA_MAC_VER_03:
3182                 rtl8169s_hw_phy_config(tp);
3183                 break;
3184         case RTL_GIGA_MAC_VER_04:
3185                 rtl8169sb_hw_phy_config(tp);
3186                 break;
3187         case RTL_GIGA_MAC_VER_05:
3188                 rtl8169scd_hw_phy_config(tp);
3189                 break;
3190         case RTL_GIGA_MAC_VER_06:
3191                 rtl8169sce_hw_phy_config(tp);
3192                 break;
3193         case RTL_GIGA_MAC_VER_07:
3194         case RTL_GIGA_MAC_VER_08:
3195         case RTL_GIGA_MAC_VER_09:
3196                 rtl8102e_hw_phy_config(tp);
3197                 break;
3198         case RTL_GIGA_MAC_VER_11:
3199                 rtl8168bb_hw_phy_config(tp);
3200                 break;
3201         case RTL_GIGA_MAC_VER_12:
3202                 rtl8168bef_hw_phy_config(tp);
3203                 break;
3204         case RTL_GIGA_MAC_VER_17:
3205                 rtl8168bef_hw_phy_config(tp);
3206                 break;
3207         case RTL_GIGA_MAC_VER_18:
3208                 rtl8168cp_1_hw_phy_config(tp);
3209                 break;
3210         case RTL_GIGA_MAC_VER_19:
3211                 rtl8168c_1_hw_phy_config(tp);
3212                 break;
3213         case RTL_GIGA_MAC_VER_20:
3214                 rtl8168c_2_hw_phy_config(tp);
3215                 break;
3216         case RTL_GIGA_MAC_VER_21:
3217                 rtl8168c_3_hw_phy_config(tp);
3218                 break;
3219         case RTL_GIGA_MAC_VER_22:
3220                 rtl8168c_4_hw_phy_config(tp);
3221                 break;
3222         case RTL_GIGA_MAC_VER_23:
3223         case RTL_GIGA_MAC_VER_24:
3224                 rtl8168cp_2_hw_phy_config(tp);
3225                 break;
3226         case RTL_GIGA_MAC_VER_25:
3227                 rtl8168d_1_hw_phy_config(tp);
3228                 break;
3229         case RTL_GIGA_MAC_VER_26:
3230                 rtl8168d_2_hw_phy_config(tp);
3231                 break;
3232         case RTL_GIGA_MAC_VER_27:
3233                 rtl8168d_3_hw_phy_config(tp);
3234                 break;
3235         case RTL_GIGA_MAC_VER_28:
3236                 rtl8168d_4_hw_phy_config(tp);
3237                 break;
3238         case RTL_GIGA_MAC_VER_29:
3239         case RTL_GIGA_MAC_VER_30:
3240                 rtl8105e_hw_phy_config(tp);
3241                 break;
3242         case RTL_GIGA_MAC_VER_31:
3243                 /* None. */
3244                 break;
3245         case RTL_GIGA_MAC_VER_32:
3246         case RTL_GIGA_MAC_VER_33:
3247                 rtl8168e_1_hw_phy_config(tp);
3248                 break;
3249         case RTL_GIGA_MAC_VER_34:
3250                 rtl8168e_2_hw_phy_config(tp);
3251                 break;
3252         case RTL_GIGA_MAC_VER_35:
3253                 rtl8168f_1_hw_phy_config(tp);
3254                 break;
3255         case RTL_GIGA_MAC_VER_36:
3256                 rtl8168f_2_hw_phy_config(tp);
3257                 break;
3258
3259         default:
3260                 break;
3261         }
3262 }
3263
3264 static void rtl_phy_work(struct rtl8169_private *tp)
3265 {
3266         struct timer_list *timer = &tp->timer;
3267         void __iomem *ioaddr = tp->mmio_addr;
3268         unsigned long timeout = RTL8169_PHY_TIMEOUT;
3269
3270         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
3271
3272         if (tp->phy_reset_pending(tp)) {
3273                 /*
3274                  * A busy loop could burn quite a few cycles on nowadays CPU.
3275                  * Let's delay the execution of the timer for a few ticks.
3276                  */
3277                 timeout = HZ/10;
3278                 goto out_mod_timer;
3279         }
3280
3281         if (tp->link_ok(ioaddr))
3282                 return;
3283
3284         netif_warn(tp, link, tp->dev, "PHY reset until link up\n");
3285
3286         tp->phy_reset_enable(tp);
3287
3288 out_mod_timer:
3289         mod_timer(timer, jiffies + timeout);
3290 }
3291
3292 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3293 {
3294         if (!test_and_set_bit(flag, tp->wk.flags))
3295                 schedule_work(&tp->wk.work);
3296 }
3297
3298 static void rtl8169_phy_timer(unsigned long __opaque)
3299 {
3300         struct net_device *dev = (struct net_device *)__opaque;
3301         struct rtl8169_private *tp = netdev_priv(dev);
3302
3303         rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
3304 }
3305
3306 #ifdef CONFIG_NET_POLL_CONTROLLER
3307 static void rtl8169_netpoll(struct net_device *dev)
3308 {
3309         struct rtl8169_private *tp = netdev_priv(dev);
3310
3311         rtl8169_interrupt(tp->pci_dev->irq, dev);
3312 }
3313 #endif
3314
3315 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3316                                   void __iomem *ioaddr)
3317 {
3318         iounmap(ioaddr);
3319         pci_release_regions(pdev);
3320         pci_clear_mwi(pdev);
3321         pci_disable_device(pdev);
3322         free_netdev(dev);
3323 }
3324
3325 static void rtl8169_phy_reset(struct net_device *dev,
3326                               struct rtl8169_private *tp)
3327 {
3328         unsigned int i;
3329
3330         tp->phy_reset_enable(tp);
3331         for (i = 0; i < 100; i++) {
3332                 if (!tp->phy_reset_pending(tp))
3333                         return;
3334                 msleep(1);
3335         }
3336         netif_err(tp, link, dev, "PHY reset failed\n");
3337 }
3338
3339 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
3340 {
3341         void __iomem *ioaddr = tp->mmio_addr;
3342
3343         return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
3344             (RTL_R8(PHYstatus) & TBI_Enable);
3345 }
3346
3347 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3348 {
3349         void __iomem *ioaddr = tp->mmio_addr;
3350
3351         rtl_hw_phy_config(dev);
3352
3353         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3354                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3355                 RTL_W8(0x82, 0x01);
3356         }
3357
3358         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3359
3360         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3361                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
3362
3363         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
3364                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3365                 RTL_W8(0x82, 0x01);
3366                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
3367                 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
3368         }
3369
3370         rtl8169_phy_reset(dev, tp);
3371
3372         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
3373                           ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3374                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3375                           (tp->mii.supports_gmii ?
3376                            ADVERTISED_1000baseT_Half |
3377                            ADVERTISED_1000baseT_Full : 0));
3378
3379         if (rtl_tbi_enabled(tp))
3380                 netif_info(tp, link, dev, "TBI auto-negotiating\n");
3381 }
3382
3383 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3384 {
3385         void __iomem *ioaddr = tp->mmio_addr;
3386         u32 high;
3387         u32 low;
3388
3389         low  = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
3390         high = addr[4] | (addr[5] << 8);
3391
3392         rtl_lock_work(tp);
3393
3394         RTL_W8(Cfg9346, Cfg9346_Unlock);
3395
3396         RTL_W32(MAC4, high);
3397         RTL_R32(MAC4);
3398
3399         RTL_W32(MAC0, low);
3400         RTL_R32(MAC0);
3401
3402         if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
3403                 const struct exgmac_reg e[] = {
3404                         { .addr = 0xe0, ERIAR_MASK_1111, .val = low },
3405                         { .addr = 0xe4, ERIAR_MASK_1111, .val = high },
3406                         { .addr = 0xf0, ERIAR_MASK_1111, .val = low << 16 },
3407                         { .addr = 0xf4, ERIAR_MASK_1111, .val = high << 16 |
3408                                                                 low  >> 16 },
3409                 };
3410
3411                 rtl_write_exgmac_batch(ioaddr, e, ARRAY_SIZE(e));
3412         }
3413
3414         RTL_W8(Cfg9346, Cfg9346_Lock);
3415
3416         rtl_unlock_work(tp);
3417 }
3418
3419 static int rtl_set_mac_address(struct net_device *dev, void *p)
3420 {
3421         struct rtl8169_private *tp = netdev_priv(dev);
3422         struct sockaddr *addr = p;
3423
3424         if (!is_valid_ether_addr(addr->sa_data))
3425                 return -EADDRNOTAVAIL;
3426
3427         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3428
3429         rtl_rar_set(tp, dev->dev_addr);
3430
3431         return 0;
3432 }
3433
3434 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3435 {
3436         struct rtl8169_private *tp = netdev_priv(dev);
3437         struct mii_ioctl_data *data = if_mii(ifr);
3438
3439         return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3440 }
3441
3442 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3443                           struct mii_ioctl_data *data, int cmd)
3444 {
3445         switch (cmd) {
3446         case SIOCGMIIPHY:
3447                 data->phy_id = 32; /* Internal PHY */
3448                 return 0;
3449
3450         case SIOCGMIIREG:
3451                 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
3452                 return 0;
3453
3454         case SIOCSMIIREG:
3455                 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
3456                 return 0;
3457         }
3458         return -EOPNOTSUPP;
3459 }
3460
3461 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3462 {
3463         return -EOPNOTSUPP;
3464 }
3465
3466 static const struct rtl_cfg_info {
3467         void (*hw_start)(struct net_device *);
3468         unsigned int region;
3469         unsigned int align;
3470         u16 event_slow;
3471         unsigned features;
3472         u8 default_ver;
3473 } rtl_cfg_infos [] = {
3474         [RTL_CFG_0] = {
3475                 .hw_start       = rtl_hw_start_8169,
3476                 .region         = 1,
3477                 .align          = 0,
3478                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
3479                 .features       = RTL_FEATURE_GMII,
3480                 .default_ver    = RTL_GIGA_MAC_VER_01,
3481         },
3482         [RTL_CFG_1] = {
3483                 .hw_start       = rtl_hw_start_8168,
3484                 .region         = 2,
3485                 .align          = 8,
3486                 .event_slow     = SYSErr | LinkChg | RxOverflow,
3487                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
3488                 .default_ver    = RTL_GIGA_MAC_VER_11,
3489         },
3490         [RTL_CFG_2] = {
3491                 .hw_start       = rtl_hw_start_8101,
3492                 .region         = 2,
3493                 .align          = 8,
3494                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
3495                                   PCSTimeout,
3496                 .features       = RTL_FEATURE_MSI,
3497                 .default_ver    = RTL_GIGA_MAC_VER_13,
3498         }
3499 };
3500
3501 /* Cfg9346_Unlock assumed. */
3502 static unsigned rtl_try_msi(struct rtl8169_private *tp,
3503                             const struct rtl_cfg_info *cfg)
3504 {
3505         void __iomem *ioaddr = tp->mmio_addr;
3506         unsigned msi = 0;
3507         u8 cfg2;
3508
3509         cfg2 = RTL_R8(Config2) & ~MSIEnable;
3510         if (cfg->features & RTL_FEATURE_MSI) {
3511                 if (pci_enable_msi(tp->pci_dev)) {
3512                         netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
3513                 } else {
3514                         cfg2 |= MSIEnable;
3515                         msi = RTL_FEATURE_MSI;
3516                 }
3517         }
3518         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3519                 RTL_W8(Config2, cfg2);
3520         return msi;
3521 }
3522
3523 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3524 {
3525         if (tp->features & RTL_FEATURE_MSI) {
3526                 pci_disable_msi(pdev);
3527                 tp->features &= ~RTL_FEATURE_MSI;
3528         }
3529 }
3530
3531 static const struct net_device_ops rtl8169_netdev_ops = {
3532         .ndo_open               = rtl8169_open,
3533         .ndo_stop               = rtl8169_close,
3534         .ndo_get_stats64        = rtl8169_get_stats64,
3535         .ndo_start_xmit         = rtl8169_start_xmit,
3536         .ndo_tx_timeout         = rtl8169_tx_timeout,
3537         .ndo_validate_addr      = eth_validate_addr,
3538         .ndo_change_mtu         = rtl8169_change_mtu,
3539         .ndo_fix_features       = rtl8169_fix_features,
3540         .ndo_set_features       = rtl8169_set_features,
3541         .ndo_set_mac_address    = rtl_set_mac_address,
3542         .ndo_do_ioctl           = rtl8169_ioctl,
3543         .ndo_set_rx_mode        = rtl_set_rx_mode,
3544 #ifdef CONFIG_NET_POLL_CONTROLLER
3545         .ndo_poll_controller    = rtl8169_netpoll,
3546 #endif
3547
3548 };
3549
3550 static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
3551 {
3552         struct mdio_ops *ops = &tp->mdio_ops;
3553
3554         switch (tp->mac_version) {
3555         case RTL_GIGA_MAC_VER_27:
3556                 ops->write      = r8168dp_1_mdio_write;
3557                 ops->read       = r8168dp_1_mdio_read;
3558                 break;
3559         case RTL_GIGA_MAC_VER_28:
3560         case RTL_GIGA_MAC_VER_31:
3561                 ops->write      = r8168dp_2_mdio_write;
3562                 ops->read       = r8168dp_2_mdio_read;
3563                 break;
3564         default:
3565                 ops->write      = r8169_mdio_write;
3566                 ops->read       = r8169_mdio_read;
3567                 break;
3568         }
3569 }
3570
3571 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3572 {
3573         void __iomem *ioaddr = tp->mmio_addr;
3574
3575         switch (tp->mac_version) {
3576         case RTL_GIGA_MAC_VER_29:
3577         case RTL_GIGA_MAC_VER_30:
3578         case RTL_GIGA_MAC_VER_32:
3579         case RTL_GIGA_MAC_VER_33:
3580         case RTL_GIGA_MAC_VER_34:
3581                 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3582                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3583                 break;
3584         default:
3585                 break;
3586         }
3587 }
3588
3589 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
3590 {
3591         if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
3592                 return false;
3593
3594         rtl_writephy(tp, 0x1f, 0x0000);
3595         rtl_writephy(tp, MII_BMCR, 0x0000);
3596
3597         rtl_wol_suspend_quirk(tp);
3598
3599         return true;
3600 }
3601
3602 static void r810x_phy_power_down(struct rtl8169_private *tp)
3603 {
3604         rtl_writephy(tp, 0x1f, 0x0000);
3605         rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3606 }
3607
3608 static void r810x_phy_power_up(struct rtl8169_private *tp)
3609 {
3610         rtl_writephy(tp, 0x1f, 0x0000);
3611         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3612 }
3613
3614 static void r810x_pll_power_down(struct rtl8169_private *tp)
3615 {
3616         if (rtl_wol_pll_power_down(tp))
3617                 return;
3618
3619         r810x_phy_power_down(tp);
3620 }
3621
3622 static void r810x_pll_power_up(struct rtl8169_private *tp)
3623 {
3624         r810x_phy_power_up(tp);
3625 }
3626
3627 static void r8168_phy_power_up(struct rtl8169_private *tp)
3628 {
3629         rtl_writephy(tp, 0x1f, 0x0000);
3630         switch (tp->mac_version) {
3631         case RTL_GIGA_MAC_VER_11:
3632         case RTL_GIGA_MAC_VER_12:
3633         case RTL_GIGA_MAC_VER_17:
3634         case RTL_GIGA_MAC_VER_18:
3635         case RTL_GIGA_MAC_VER_19:
3636         case RTL_GIGA_MAC_VER_20:
3637         case RTL_GIGA_MAC_VER_21:
3638         case RTL_GIGA_MAC_VER_22:
3639         case RTL_GIGA_MAC_VER_23:
3640         case RTL_GIGA_MAC_VER_24:
3641         case RTL_GIGA_MAC_VER_25:
3642         case RTL_GIGA_MAC_VER_26:
3643         case RTL_GIGA_MAC_VER_27:
3644         case RTL_GIGA_MAC_VER_28:
3645         case RTL_GIGA_MAC_VER_31:
3646                 rtl_writephy(tp, 0x0e, 0x0000);
3647                 break;
3648         default:
3649                 break;
3650         }
3651         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3652 }
3653
3654 static void r8168_phy_power_down(struct rtl8169_private *tp)
3655 {
3656         rtl_writephy(tp, 0x1f, 0x0000);
3657         switch (tp->mac_version) {
3658         case RTL_GIGA_MAC_VER_32:
3659         case RTL_GIGA_MAC_VER_33:
3660                 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3661                 break;
3662
3663         case RTL_GIGA_MAC_VER_11:
3664         case RTL_GIGA_MAC_VER_12:
3665         case RTL_GIGA_MAC_VER_17:
3666         case RTL_GIGA_MAC_VER_18:
3667         case RTL_GIGA_MAC_VER_19:
3668         case RTL_GIGA_MAC_VER_20:
3669         case RTL_GIGA_MAC_VER_21:
3670         case RTL_GIGA_MAC_VER_22:
3671         case RTL_GIGA_MAC_VER_23:
3672         case RTL_GIGA_MAC_VER_24:
3673         case RTL_GIGA_MAC_VER_25:
3674         case RTL_GIGA_MAC_VER_26:
3675         case RTL_GIGA_MAC_VER_27:
3676         case RTL_GIGA_MAC_VER_28:
3677         case RTL_GIGA_MAC_VER_31:
3678                 rtl_writephy(tp, 0x0e, 0x0200);
3679         default:
3680                 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3681                 break;
3682         }
3683 }
3684
3685 static void r8168_pll_power_down(struct rtl8169_private *tp)
3686 {
3687         void __iomem *ioaddr = tp->mmio_addr;
3688
3689         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3690              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3691              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3692             r8168dp_check_dash(tp)) {
3693                 return;
3694         }
3695
3696         if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3697              tp->mac_version == RTL_GIGA_MAC_VER_24) &&
3698             (RTL_R16(CPlusCmd) & ASF)) {
3699                 return;
3700         }
3701
3702         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3703             tp->mac_version == RTL_GIGA_MAC_VER_33)
3704                 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3705
3706         if (rtl_wol_pll_power_down(tp))
3707                 return;
3708
3709         r8168_phy_power_down(tp);
3710
3711         switch (tp->mac_version) {
3712         case RTL_GIGA_MAC_VER_25:
3713         case RTL_GIGA_MAC_VER_26:
3714         case RTL_GIGA_MAC_VER_27:
3715         case RTL_GIGA_MAC_VER_28:
3716         case RTL_GIGA_MAC_VER_31:
3717         case RTL_GIGA_MAC_VER_32:
3718         case RTL_GIGA_MAC_VER_33:
3719                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3720                 break;
3721         }
3722 }
3723
3724 static void r8168_pll_power_up(struct rtl8169_private *tp)
3725 {
3726         void __iomem *ioaddr = tp->mmio_addr;
3727
3728         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3729              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3730              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3731             r8168dp_check_dash(tp)) {
3732                 return;
3733         }
3734
3735         switch (tp->mac_version) {
3736         case RTL_GIGA_MAC_VER_25:
3737         case RTL_GIGA_MAC_VER_26:
3738         case RTL_GIGA_MAC_VER_27:
3739         case RTL_GIGA_MAC_VER_28:
3740         case RTL_GIGA_MAC_VER_31:
3741         case RTL_GIGA_MAC_VER_32:
3742         case RTL_GIGA_MAC_VER_33:
3743                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3744                 break;
3745         }
3746
3747         r8168_phy_power_up(tp);
3748 }
3749
3750 static void rtl_generic_op(struct rtl8169_private *tp,
3751                            void (*op)(struct rtl8169_private *))
3752 {
3753         if (op)
3754                 op(tp);
3755 }
3756
3757 static void rtl_pll_power_down(struct rtl8169_private *tp)
3758 {
3759         rtl_generic_op(tp, tp->pll_power_ops.down);
3760 }
3761
3762 static void rtl_pll_power_up(struct rtl8169_private *tp)
3763 {
3764         rtl_generic_op(tp, tp->pll_power_ops.up);
3765 }
3766
3767 static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3768 {
3769         struct pll_power_ops *ops = &tp->pll_power_ops;
3770
3771         switch (tp->mac_version) {
3772         case RTL_GIGA_MAC_VER_07:
3773         case RTL_GIGA_MAC_VER_08:
3774         case RTL_GIGA_MAC_VER_09:
3775         case RTL_GIGA_MAC_VER_10:
3776         case RTL_GIGA_MAC_VER_16:
3777         case RTL_GIGA_MAC_VER_29:
3778         case RTL_GIGA_MAC_VER_30:
3779                 ops->down       = r810x_pll_power_down;
3780                 ops->up         = r810x_pll_power_up;
3781                 break;
3782
3783         case RTL_GIGA_MAC_VER_11:
3784         case RTL_GIGA_MAC_VER_12:
3785         case RTL_GIGA_MAC_VER_17:
3786         case RTL_GIGA_MAC_VER_18:
3787         case RTL_GIGA_MAC_VER_19:
3788         case RTL_GIGA_MAC_VER_20:
3789         case RTL_GIGA_MAC_VER_21:
3790         case RTL_GIGA_MAC_VER_22:
3791         case RTL_GIGA_MAC_VER_23:
3792         case RTL_GIGA_MAC_VER_24:
3793         case RTL_GIGA_MAC_VER_25:
3794         case RTL_GIGA_MAC_VER_26:
3795         case RTL_GIGA_MAC_VER_27:
3796         case RTL_GIGA_MAC_VER_28:
3797         case RTL_GIGA_MAC_VER_31:
3798         case RTL_GIGA_MAC_VER_32:
3799         case RTL_GIGA_MAC_VER_33:
3800         case RTL_GIGA_MAC_VER_34:
3801         case RTL_GIGA_MAC_VER_35:
3802         case RTL_GIGA_MAC_VER_36:
3803                 ops->down       = r8168_pll_power_down;
3804                 ops->up         = r8168_pll_power_up;
3805                 break;
3806
3807         default:
3808                 ops->down       = NULL;
3809                 ops->up         = NULL;
3810                 break;
3811         }
3812 }
3813
3814 static void rtl_init_rxcfg(struct rtl8169_private *tp)
3815 {
3816         void __iomem *ioaddr = tp->mmio_addr;
3817
3818         switch (tp->mac_version) {
3819         case RTL_GIGA_MAC_VER_01:
3820         case RTL_GIGA_MAC_VER_02:
3821         case RTL_GIGA_MAC_VER_03:
3822         case RTL_GIGA_MAC_VER_04:
3823         case RTL_GIGA_MAC_VER_05:
3824         case RTL_GIGA_MAC_VER_06:
3825         case RTL_GIGA_MAC_VER_10:
3826         case RTL_GIGA_MAC_VER_11:
3827         case RTL_GIGA_MAC_VER_12:
3828         case RTL_GIGA_MAC_VER_13:
3829         case RTL_GIGA_MAC_VER_14:
3830         case RTL_GIGA_MAC_VER_15:
3831         case RTL_GIGA_MAC_VER_16:
3832         case RTL_GIGA_MAC_VER_17:
3833                 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
3834                 break;
3835         case RTL_GIGA_MAC_VER_18:
3836         case RTL_GIGA_MAC_VER_19:
3837         case RTL_GIGA_MAC_VER_20:
3838         case RTL_GIGA_MAC_VER_21:
3839         case RTL_GIGA_MAC_VER_22:
3840         case RTL_GIGA_MAC_VER_23:
3841         case RTL_GIGA_MAC_VER_24:
3842                 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
3843                 break;
3844         default:
3845                 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
3846                 break;
3847         }
3848 }
3849
3850 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3851 {
3852         tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
3853 }
3854
3855 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
3856 {
3857         void __iomem *ioaddr = tp->mmio_addr;
3858
3859         RTL_W8(Cfg9346, Cfg9346_Unlock);
3860         rtl_generic_op(tp, tp->jumbo_ops.enable);
3861         RTL_W8(Cfg9346, Cfg9346_Lock);
3862 }
3863
3864 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
3865 {
3866         void __iomem *ioaddr = tp->mmio_addr;
3867
3868         RTL_W8(Cfg9346, Cfg9346_Unlock);
3869         rtl_generic_op(tp, tp->jumbo_ops.disable);
3870         RTL_W8(Cfg9346, Cfg9346_Lock);
3871 }
3872
3873 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
3874 {
3875         void __iomem *ioaddr = tp->mmio_addr;
3876
3877         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3878         RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
3879         rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
3880 }
3881
3882 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
3883 {
3884         void __iomem *ioaddr = tp->mmio_addr;
3885
3886         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3887         RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
3888         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
3889 }
3890
3891 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
3892 {
3893         void __iomem *ioaddr = tp->mmio_addr;
3894
3895         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3896 }
3897
3898 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
3899 {
3900         void __iomem *ioaddr = tp->mmio_addr;
3901
3902         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3903 }
3904
3905 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
3906 {
3907         void __iomem *ioaddr = tp->mmio_addr;
3908
3909         RTL_W8(MaxTxPacketSize, 0x3f);
3910         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3911         RTL_W8(Config4, RTL_R8(Config4) | 0x01);
3912         rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
3913 }
3914
3915 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
3916 {
3917         void __iomem *ioaddr = tp->mmio_addr;
3918
3919         RTL_W8(MaxTxPacketSize, 0x0c);
3920         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3921         RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
3922         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
3923 }
3924
3925 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
3926 {
3927         rtl_tx_performance_tweak(tp->pci_dev,
3928                 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3929 }
3930
3931 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
3932 {
3933         rtl_tx_performance_tweak(tp->pci_dev,
3934                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3935 }
3936
3937 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
3938 {
3939         void __iomem *ioaddr = tp->mmio_addr;
3940
3941         r8168b_0_hw_jumbo_enable(tp);
3942
3943         RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
3944 }
3945
3946 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
3947 {
3948         void __iomem *ioaddr = tp->mmio_addr;
3949
3950         r8168b_0_hw_jumbo_disable(tp);
3951
3952         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3953 }
3954
3955 static void __devinit rtl_init_jumbo_ops(struct rtl8169_private *tp)
3956 {
3957         struct jumbo_ops *ops = &tp->jumbo_ops;
3958
3959         switch (tp->mac_version) {
3960         case RTL_GIGA_MAC_VER_11:
3961                 ops->disable    = r8168b_0_hw_jumbo_disable;
3962                 ops->enable     = r8168b_0_hw_jumbo_enable;
3963                 break;
3964         case RTL_GIGA_MAC_VER_12:
3965         case RTL_GIGA_MAC_VER_17:
3966                 ops->disable    = r8168b_1_hw_jumbo_disable;
3967                 ops->enable     = r8168b_1_hw_jumbo_enable;
3968                 break;
3969         case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
3970         case RTL_GIGA_MAC_VER_19:
3971         case RTL_GIGA_MAC_VER_20:
3972         case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
3973         case RTL_GIGA_MAC_VER_22:
3974         case RTL_GIGA_MAC_VER_23:
3975         case RTL_GIGA_MAC_VER_24:
3976         case RTL_GIGA_MAC_VER_25:
3977         case RTL_GIGA_MAC_VER_26:
3978                 ops->disable    = r8168c_hw_jumbo_disable;
3979                 ops->enable     = r8168c_hw_jumbo_enable;
3980                 break;
3981         case RTL_GIGA_MAC_VER_27:
3982         case RTL_GIGA_MAC_VER_28:
3983                 ops->disable    = r8168dp_hw_jumbo_disable;
3984                 ops->enable     = r8168dp_hw_jumbo_enable;
3985                 break;
3986         case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
3987         case RTL_GIGA_MAC_VER_32:
3988         case RTL_GIGA_MAC_VER_33:
3989         case RTL_GIGA_MAC_VER_34:
3990                 ops->disable    = r8168e_hw_jumbo_disable;
3991                 ops->enable     = r8168e_hw_jumbo_enable;
3992                 break;
3993
3994         /*
3995          * No action needed for jumbo frames with 8169.
3996          * No jumbo for 810x at all.
3997          */
3998         default:
3999                 ops->disable    = NULL;
4000                 ops->enable     = NULL;
4001                 break;
4002         }
4003 }
4004
4005 static void rtl_hw_reset(struct rtl8169_private *tp)
4006 {
4007         void __iomem *ioaddr = tp->mmio_addr;
4008         int i;
4009
4010         /* Soft reset the chip. */
4011         RTL_W8(ChipCmd, CmdReset);
4012
4013         /* Check that the chip has finished the reset. */
4014         for (i = 0; i < 100; i++) {
4015                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
4016                         break;
4017                 udelay(100);
4018         }
4019 }
4020
4021 static int __devinit
4022 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
4023 {
4024         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
4025         const unsigned int region = cfg->region;
4026         struct rtl8169_private *tp;
4027         struct mii_if_info *mii;
4028         struct net_device *dev;
4029         void __iomem *ioaddr;
4030         int chipset, i;
4031         int rc;
4032
4033         if (netif_msg_drv(&debug)) {
4034                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
4035                        MODULENAME, RTL8169_VERSION);
4036         }
4037
4038         dev = alloc_etherdev(sizeof (*tp));
4039         if (!dev) {
4040                 rc = -ENOMEM;
4041                 goto out;
4042         }
4043
4044         SET_NETDEV_DEV(dev, &pdev->dev);
4045         dev->netdev_ops = &rtl8169_netdev_ops;
4046         tp = netdev_priv(dev);
4047         tp->dev = dev;
4048         tp->pci_dev = pdev;
4049         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
4050
4051         mii = &tp->mii;
4052         mii->dev = dev;
4053         mii->mdio_read = rtl_mdio_read;
4054         mii->mdio_write = rtl_mdio_write;
4055         mii->phy_id_mask = 0x1f;
4056         mii->reg_num_mask = 0x1f;
4057         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
4058
4059         /* disable ASPM completely as that cause random device stop working
4060          * problems as well as full system hangs for some PCIe devices users */
4061         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
4062                                      PCIE_LINK_STATE_CLKPM);
4063
4064         /* enable device (incl. PCI PM wakeup and hotplug setup) */
4065         rc = pci_enable_device(pdev);
4066         if (rc < 0) {
4067                 netif_err(tp, probe, dev, "enable failure\n");
4068                 goto err_out_free_dev_1;
4069         }
4070
4071         if (pci_set_mwi(pdev) < 0)
4072                 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
4073
4074         /* make sure PCI base addr 1 is MMIO */
4075         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
4076                 netif_err(tp, probe, dev,
4077                           "region #%d not an MMIO resource, aborting\n",
4078                           region);
4079                 rc = -ENODEV;
4080                 goto err_out_mwi_2;
4081         }
4082
4083         /* check for weird/broken PCI region reporting */
4084         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
4085                 netif_err(tp, probe, dev,
4086                           "Invalid PCI region size(s), aborting\n");
4087                 rc = -ENODEV;
4088                 goto err_out_mwi_2;
4089         }
4090
4091         rc = pci_request_regions(pdev, MODULENAME);
4092         if (rc < 0) {
4093                 netif_err(tp, probe, dev, "could not request regions\n");
4094                 goto err_out_mwi_2;
4095         }
4096
4097         tp->cp_cmd = RxChkSum;
4098
4099         if ((sizeof(dma_addr_t) > 4) &&
4100             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
4101                 tp->cp_cmd |= PCIDAC;
4102                 dev->features |= NETIF_F_HIGHDMA;
4103         } else {
4104                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4105                 if (rc < 0) {
4106                         netif_err(tp, probe, dev, "DMA configuration failed\n");
4107                         goto err_out_free_res_3;
4108                 }
4109         }
4110
4111         /* ioremap MMIO region */
4112         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4113         if (!ioaddr) {
4114                 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
4115                 rc = -EIO;
4116                 goto err_out_free_res_3;
4117         }
4118         tp->mmio_addr = ioaddr;
4119
4120         if (!pci_is_pcie(pdev))
4121                 netif_info(tp, probe, dev, "not PCI Express\n");
4122
4123         /* Identify chip attached to board */
4124         rtl8169_get_mac_version(tp, dev, cfg->default_ver);
4125
4126         rtl_init_rxcfg(tp);
4127
4128         rtl_irq_disable(tp);
4129
4130         rtl_hw_reset(tp);
4131
4132         rtl_ack_events(tp, 0xffff);
4133
4134         pci_set_master(pdev);
4135
4136         /*
4137          * Pretend we are using VLANs; This bypasses a nasty bug where
4138          * Interrupts stop flowing on high load on 8110SCd controllers.
4139          */
4140         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4141                 tp->cp_cmd |= RxVlan;
4142
4143         rtl_init_mdio_ops(tp);
4144         rtl_init_pll_power_ops(tp);
4145         rtl_init_jumbo_ops(tp);
4146
4147         rtl8169_print_mac_version(tp);
4148
4149         chipset = tp->mac_version;
4150         tp->txd_version = rtl_chip_infos[chipset].txd_version;
4151
4152         RTL_W8(Cfg9346, Cfg9346_Unlock);
4153         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
4154         RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
4155         if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
4156                 tp->features |= RTL_FEATURE_WOL;
4157         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
4158                 tp->features |= RTL_FEATURE_WOL;
4159         tp->features |= rtl_try_msi(tp, cfg);
4160         RTL_W8(Cfg9346, Cfg9346_Lock);
4161
4162         if (rtl_tbi_enabled(tp)) {
4163                 tp->set_speed = rtl8169_set_speed_tbi;
4164                 tp->get_settings = rtl8169_gset_tbi;
4165                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
4166                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
4167                 tp->link_ok = rtl8169_tbi_link_ok;
4168                 tp->do_ioctl = rtl_tbi_ioctl;
4169         } else {
4170                 tp->set_speed = rtl8169_set_speed_xmii;
4171                 tp->get_settings = rtl8169_gset_xmii;
4172                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
4173                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
4174                 tp->link_ok = rtl8169_xmii_link_ok;
4175                 tp->do_ioctl = rtl_xmii_ioctl;
4176         }
4177
4178         mutex_init(&tp->wk.mutex);
4179
4180         /* Get MAC address */
4181         for (i = 0; i < ETH_ALEN; i++)
4182                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
4183         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
4184
4185         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
4186         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
4187         dev->irq = pdev->irq;
4188         dev->base_addr = (unsigned long) ioaddr;
4189
4190         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
4191
4192         /* don't enable SG, IP_CSUM and TSO by default - it might not work
4193          * properly for all devices */
4194         dev->features |= NETIF_F_RXCSUM |
4195                 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4196
4197         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
4198                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4199         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
4200                 NETIF_F_HIGHDMA;
4201
4202         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4203                 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
4204                 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
4205
4206         dev->hw_features |= NETIF_F_RXALL;
4207         dev->hw_features |= NETIF_F_RXFCS;
4208
4209         tp->hw_start = cfg->hw_start;
4210         tp->event_slow = cfg->event_slow;
4211
4212         tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
4213                 ~(RxBOVF | RxFOVF) : ~0;
4214
4215         init_timer(&tp->timer);
4216         tp->timer.data = (unsigned long) dev;
4217         tp->timer.function = rtl8169_phy_timer;
4218
4219         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
4220
4221         rc = register_netdev(dev);
4222         if (rc < 0)
4223                 goto err_out_msi_4;
4224
4225         pci_set_drvdata(pdev, dev);
4226
4227         netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
4228                    rtl_chip_infos[chipset].name, dev->base_addr, dev->dev_addr,
4229                    (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
4230         if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
4231                 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
4232                            "tx checksumming: %s]\n",
4233                            rtl_chip_infos[chipset].jumbo_max,
4234                            rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
4235         }
4236
4237         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4238             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4239             tp->mac_version == RTL_GIGA_MAC_VER_31) {
4240                 rtl8168_driver_start(tp);
4241         }
4242
4243         device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
4244
4245         if (pci_dev_run_wake(pdev))
4246                 pm_runtime_put_noidle(&pdev->dev);
4247
4248         netif_carrier_off(dev);
4249
4250 out:
4251         return rc;
4252
4253 err_out_msi_4:
4254         rtl_disable_msi(pdev, tp);
4255         iounmap(ioaddr);
4256 err_out_free_res_3:
4257         pci_release_regions(pdev);
4258 err_out_mwi_2:
4259         pci_clear_mwi(pdev);
4260         pci_disable_device(pdev);
4261 err_out_free_dev_1:
4262         free_netdev(dev);
4263         goto out;
4264 }
4265
4266 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
4267 {
4268         struct net_device *dev = pci_get_drvdata(pdev);
4269         struct rtl8169_private *tp = netdev_priv(dev);
4270
4271         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4272             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4273             tp->mac_version == RTL_GIGA_MAC_VER_31) {
4274                 rtl8168_driver_stop(tp);
4275         }
4276
4277         cancel_work_sync(&tp->wk.work);
4278
4279         unregister_netdev(dev);
4280
4281         rtl_release_firmware(tp);
4282
4283         if (pci_dev_run_wake(pdev))
4284                 pm_runtime_get_noresume(&pdev->dev);
4285
4286         /* restore original MAC address */
4287         rtl_rar_set(tp, dev->perm_addr);
4288
4289         rtl_disable_msi(pdev, tp);
4290         rtl8169_release_board(pdev, dev, tp->mmio_addr);
4291         pci_set_drvdata(pdev, NULL);
4292 }
4293
4294 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
4295 {
4296         struct rtl_fw *rtl_fw;
4297         const char *name;
4298         int rc = -ENOMEM;
4299
4300         name = rtl_lookup_firmware_name(tp);
4301         if (!name)
4302                 goto out_no_firmware;
4303
4304         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4305         if (!rtl_fw)
4306                 goto err_warn;
4307
4308         rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
4309         if (rc < 0)
4310                 goto err_free;
4311
4312         rc = rtl_check_firmware(tp, rtl_fw);
4313         if (rc < 0)
4314                 goto err_release_firmware;
4315
4316         tp->rtl_fw = rtl_fw;
4317 out:
4318         return;
4319
4320 err_release_firmware:
4321         release_firmware(rtl_fw->fw);
4322 err_free:
4323         kfree(rtl_fw);
4324 err_warn:
4325         netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4326                    name, rc);
4327 out_no_firmware:
4328         tp->rtl_fw = NULL;
4329         goto out;
4330 }
4331
4332 static void rtl_request_firmware(struct rtl8169_private *tp)
4333 {
4334         if (IS_ERR(tp->rtl_fw))
4335                 rtl_request_uncached_firmware(tp);
4336 }
4337
4338 static void rtl_task(struct work_struct *);
4339
4340 static int rtl8169_open(struct net_device *dev)
4341 {
4342         struct rtl8169_private *tp = netdev_priv(dev);
4343         void __iomem *ioaddr = tp->mmio_addr;
4344         struct pci_dev *pdev = tp->pci_dev;
4345         int retval = -ENOMEM;
4346
4347         pm_runtime_get_sync(&pdev->dev);
4348
4349         /*
4350          * Rx and Tx desscriptors needs 256 bytes alignment.
4351          * dma_alloc_coherent provides more.
4352          */
4353         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
4354                                              &tp->TxPhyAddr, GFP_KERNEL);
4355         if (!tp->TxDescArray)
4356                 goto err_pm_runtime_put;
4357
4358         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
4359                                              &tp->RxPhyAddr, GFP_KERNEL);
4360         if (!tp->RxDescArray)
4361                 goto err_free_tx_0;
4362
4363         retval = rtl8169_init_ring(dev);
4364         if (retval < 0)
4365                 goto err_free_rx_1;
4366
4367         INIT_WORK(&tp->wk.work, rtl_task);
4368
4369         smp_mb();
4370
4371         rtl_request_firmware(tp);
4372
4373         retval = request_irq(dev->irq, rtl8169_interrupt,
4374                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
4375                              dev->name, dev);
4376         if (retval < 0)
4377                 goto err_release_fw_2;
4378
4379         rtl_lock_work(tp);
4380
4381         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
4382
4383         napi_enable(&tp->napi);
4384
4385         rtl8169_init_phy(dev, tp);
4386
4387         __rtl8169_set_features(dev, dev->features);
4388
4389         rtl_pll_power_up(tp);
4390
4391         rtl_hw_start(dev);
4392
4393         netif_start_queue(dev);
4394
4395         rtl_unlock_work(tp);
4396
4397         tp->saved_wolopts = 0;
4398         pm_runtime_put_noidle(&pdev->dev);
4399
4400         rtl8169_check_link_status(dev, tp, ioaddr);
4401 out:
4402         return retval;
4403
4404 err_release_fw_2:
4405         rtl_release_firmware(tp);
4406         rtl8169_rx_clear(tp);
4407 err_free_rx_1:
4408         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4409                           tp->RxPhyAddr);
4410         tp->RxDescArray = NULL;
4411 err_free_tx_0:
4412         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4413                           tp->TxPhyAddr);
4414         tp->TxDescArray = NULL;
4415 err_pm_runtime_put:
4416         pm_runtime_put_noidle(&pdev->dev);
4417         goto out;
4418 }
4419
4420 static void rtl_rx_close(struct rtl8169_private *tp)
4421 {
4422         void __iomem *ioaddr = tp->mmio_addr;
4423
4424         RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4425 }
4426
4427 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4428 {
4429         void __iomem *ioaddr = tp->mmio_addr;
4430
4431         /* Disable interrupts */
4432         rtl8169_irq_mask_and_ack(tp);
4433
4434         rtl_rx_close(tp);
4435
4436         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4437             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4438             tp->mac_version == RTL_GIGA_MAC_VER_31) {
4439                 while (RTL_R8(TxPoll) & NPQ)
4440                         udelay(20);
4441         } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
4442                    tp->mac_version == RTL_GIGA_MAC_VER_35 ||
4443                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
4444                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4445                 while (!(RTL_R32(TxConfig) & TXCFG_EMPTY))
4446                         udelay(100);
4447         } else {
4448                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4449                 udelay(100);
4450         }
4451
4452         rtl_hw_reset(tp);
4453 }
4454
4455 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
4456 {
4457         void __iomem *ioaddr = tp->mmio_addr;
4458
4459         /* Set DMA burst size and Interframe Gap Time */
4460         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4461                 (InterFrameGap << TxInterFrameGapShift));
4462 }
4463
4464 static void rtl_hw_start(struct net_device *dev)
4465 {
4466         struct rtl8169_private *tp = netdev_priv(dev);
4467
4468         tp->hw_start(dev);
4469
4470         rtl_irq_enable_all(tp);
4471 }
4472
4473 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4474                                          void __iomem *ioaddr)
4475 {
4476         /*
4477          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4478          * register to be written before TxDescAddrLow to work.
4479          * Switching from MMIO to I/O access fixes the issue as well.
4480          */
4481         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4482         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4483         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4484         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4485 }
4486
4487 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4488 {
4489         u16 cmd;
4490
4491         cmd = RTL_R16(CPlusCmd);
4492         RTL_W16(CPlusCmd, cmd);
4493         return cmd;
4494 }
4495
4496 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
4497 {
4498         /* Low hurts. Let's disable the filtering. */
4499         RTL_W16(RxMaxSize, rx_buf_sz + 1);
4500 }
4501
4502 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4503 {
4504         static const struct rtl_cfg2_info {
4505                 u32 mac_version;
4506                 u32 clk;
4507                 u32 val;
4508         } cfg2_info [] = {
4509                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4510                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4511                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4512                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
4513         };
4514         const struct rtl_cfg2_info *p = cfg2_info;
4515         unsigned int i;
4516         u32 clk;
4517
4518         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
4519         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
4520                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4521                         RTL_W32(0x7c, p->val);
4522                         break;
4523                 }
4524         }
4525 }
4526
4527 static void rtl_hw_start_8169(struct net_device *dev)
4528 {
4529         struct rtl8169_private *tp = netdev_priv(dev);
4530         void __iomem *ioaddr = tp->mmio_addr;
4531         struct pci_dev *pdev = tp->pci_dev;
4532
4533         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4534                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4535                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4536         }
4537
4538         RTL_W8(Cfg9346, Cfg9346_Unlock);
4539         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4540             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4541             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4542             tp->mac_version == RTL_GIGA_MAC_VER_04)
4543                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4544
4545         rtl_init_rxcfg(tp);
4546
4547         RTL_W8(EarlyTxThres, NoEarlyTx);
4548
4549         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4550
4551         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4552             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4553             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4554             tp->mac_version == RTL_GIGA_MAC_VER_04)
4555                 rtl_set_rx_tx_config_registers(tp);
4556
4557         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
4558
4559         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4560             tp->mac_version == RTL_GIGA_MAC_VER_03) {
4561                 dprintk("Set MAC Reg C+CR Offset 0xE0. "
4562                         "Bit-3 and bit-14 MUST be 1\n");
4563                 tp->cp_cmd |= (1 << 14);
4564         }
4565
4566         RTL_W16(CPlusCmd, tp->cp_cmd);
4567
4568         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4569
4570         /*
4571          * Undocumented corner. Supposedly:
4572          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4573          */
4574         RTL_W16(IntrMitigate, 0x0000);
4575
4576         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4577
4578         if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4579             tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4580             tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4581             tp->mac_version != RTL_GIGA_MAC_VER_04) {
4582                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4583                 rtl_set_rx_tx_config_registers(tp);
4584         }
4585
4586         RTL_W8(Cfg9346, Cfg9346_Lock);
4587
4588         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4589         RTL_R8(IntrMask);
4590
4591         RTL_W32(RxMissed, 0);
4592
4593         rtl_set_rx_mode(dev);
4594
4595         /* no early-rx interrupts */
4596         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4597 }
4598
4599 static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
4600 {
4601         u32 csi;
4602
4603         csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
4604         rtl_csi_write(ioaddr, 0x070c, csi | bits);
4605 }
4606
4607 static void rtl_csi_access_enable_1(void __iomem *ioaddr)
4608 {
4609         rtl_csi_access_enable(ioaddr, 0x17000000);
4610 }
4611
4612 static void rtl_csi_access_enable_2(void __iomem *ioaddr)
4613 {
4614         rtl_csi_access_enable(ioaddr, 0x27000000);
4615 }
4616
4617 struct ephy_info {
4618         unsigned int offset;
4619         u16 mask;
4620         u16 bits;
4621 };
4622
4623 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
4624 {
4625         u16 w;
4626
4627         while (len-- > 0) {
4628                 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
4629                 rtl_ephy_write(ioaddr, e->offset, w);
4630                 e++;
4631         }
4632 }
4633
4634 static void rtl_disable_clock_request(struct pci_dev *pdev)
4635 {
4636         int cap = pci_pcie_cap(pdev);
4637
4638         if (cap) {
4639                 u16 ctl;
4640
4641                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4642                 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
4643                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4644         }
4645 }
4646
4647 static void rtl_enable_clock_request(struct pci_dev *pdev)
4648 {
4649         int cap = pci_pcie_cap(pdev);
4650
4651         if (cap) {
4652                 u16 ctl;
4653
4654                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4655                 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
4656                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4657         }
4658 }
4659
4660 #define R8168_CPCMD_QUIRK_MASK (\
4661         EnableBist | \
4662         Mac_dbgo_oe | \
4663         Force_half_dup | \
4664         Force_rxflow_en | \
4665         Force_txflow_en | \
4666         Cxpl_dbg_sel | \
4667         ASF | \
4668         PktCntrDisable | \
4669         Mac_dbgo_sel)
4670
4671 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
4672 {
4673         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4674
4675         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4676
4677         rtl_tx_performance_tweak(pdev,
4678                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4679 }
4680
4681 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
4682 {
4683         rtl_hw_start_8168bb(ioaddr, pdev);
4684
4685         RTL_W8(MaxTxPacketSize, TxPacketMax);
4686
4687         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4688 }
4689
4690 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
4691 {
4692         RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4693
4694         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4695
4696         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4697
4698         rtl_disable_clock_request(pdev);
4699
4700         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4701 }
4702
4703 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
4704 {
4705         static const struct ephy_info e_info_8168cp[] = {
4706                 { 0x01, 0,      0x0001 },
4707                 { 0x02, 0x0800, 0x1000 },
4708                 { 0x03, 0,      0x0042 },
4709                 { 0x06, 0x0080, 0x0000 },
4710                 { 0x07, 0,      0x2000 }
4711         };
4712
4713         rtl_csi_access_enable_2(ioaddr);
4714
4715         rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4716
4717         __rtl_hw_start_8168cp(ioaddr, pdev);
4718 }
4719
4720 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
4721 {
4722         rtl_csi_access_enable_2(ioaddr);
4723
4724         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4725
4726         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4727
4728         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4729 }
4730
4731 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
4732 {
4733         rtl_csi_access_enable_2(ioaddr);
4734
4735         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4736
4737         /* Magic. */
4738         RTL_W8(DBG_REG, 0x20);
4739
4740         RTL_W8(MaxTxPacketSize, TxPacketMax);
4741
4742         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4743
4744         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4745 }
4746
4747 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
4748 {
4749         static const struct ephy_info e_info_8168c_1[] = {
4750                 { 0x02, 0x0800, 0x1000 },
4751                 { 0x03, 0,      0x0002 },
4752                 { 0x06, 0x0080, 0x0000 }
4753         };
4754
4755         rtl_csi_access_enable_2(ioaddr);
4756
4757         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4758
4759         rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4760
4761         __rtl_hw_start_8168cp(ioaddr, pdev);
4762 }
4763
4764 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
4765 {
4766         static const struct ephy_info e_info_8168c_2[] = {
4767                 { 0x01, 0,      0x0001 },
4768                 { 0x03, 0x0400, 0x0220 }
4769         };
4770
4771         rtl_csi_access_enable_2(ioaddr);
4772
4773         rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4774
4775         __rtl_hw_start_8168cp(ioaddr, pdev);
4776 }
4777
4778 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
4779 {
4780         rtl_hw_start_8168c_2(ioaddr, pdev);
4781 }
4782
4783 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
4784 {
4785         rtl_csi_access_enable_2(ioaddr);
4786
4787         __rtl_hw_start_8168cp(ioaddr, pdev);
4788 }
4789
4790 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
4791 {
4792         rtl_csi_access_enable_2(ioaddr);
4793
4794         rtl_disable_clock_request(pdev);
4795
4796         RTL_W8(MaxTxPacketSize, TxPacketMax);
4797
4798         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4799
4800         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4801 }
4802
4803 static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
4804 {
4805         rtl_csi_access_enable_1(ioaddr);
4806
4807         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4808
4809         RTL_W8(MaxTxPacketSize, TxPacketMax);
4810
4811         rtl_disable_clock_request(pdev);
4812 }
4813
4814 static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
4815 {
4816         static const struct ephy_info e_info_8168d_4[] = {
4817                 { 0x0b, ~0,     0x48 },
4818                 { 0x19, 0x20,   0x50 },
4819                 { 0x0c, ~0,     0x20 }
4820         };
4821         int i;
4822
4823         rtl_csi_access_enable_1(ioaddr);
4824
4825         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4826
4827         RTL_W8(MaxTxPacketSize, TxPacketMax);
4828
4829         for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4830                 const struct ephy_info *e = e_info_8168d_4 + i;
4831                 u16 w;
4832
4833                 w = rtl_ephy_read(ioaddr, e->offset);
4834                 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4835         }
4836
4837         rtl_enable_clock_request(pdev);
4838 }
4839
4840 static void rtl_hw_start_8168e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4841 {
4842         static const struct ephy_info e_info_8168e_1[] = {
4843                 { 0x00, 0x0200, 0x0100 },
4844                 { 0x00, 0x0000, 0x0004 },
4845                 { 0x06, 0x0002, 0x0001 },
4846                 { 0x06, 0x0000, 0x0030 },
4847                 { 0x07, 0x0000, 0x2000 },
4848                 { 0x00, 0x0000, 0x0020 },
4849                 { 0x03, 0x5800, 0x2000 },
4850                 { 0x03, 0x0000, 0x0001 },
4851                 { 0x01, 0x0800, 0x1000 },
4852                 { 0x07, 0x0000, 0x4000 },
4853                 { 0x1e, 0x0000, 0x2000 },
4854                 { 0x19, 0xffff, 0xfe6c },
4855                 { 0x0a, 0x0000, 0x0040 }
4856         };
4857
4858         rtl_csi_access_enable_2(ioaddr);
4859
4860         rtl_ephy_init(ioaddr, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
4861
4862         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4863
4864         RTL_W8(MaxTxPacketSize, TxPacketMax);
4865
4866         rtl_disable_clock_request(pdev);
4867
4868         /* Reset tx FIFO pointer */
4869         RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4870         RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
4871
4872         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4873 }
4874
4875 static void rtl_hw_start_8168e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4876 {
4877         static const struct ephy_info e_info_8168e_2[] = {
4878                 { 0x09, 0x0000, 0x0080 },
4879                 { 0x19, 0x0000, 0x0224 }
4880         };
4881
4882         rtl_csi_access_enable_1(ioaddr);
4883
4884         rtl_ephy_init(ioaddr, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
4885
4886         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4887
4888         rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4889         rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4890         rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4891         rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4892         rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4893         rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
4894         rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4895         rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4896                      ERIAR_EXGMAC);
4897
4898         RTL_W8(MaxTxPacketSize, EarlySize);
4899
4900         rtl_disable_clock_request(pdev);
4901
4902         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4903         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4904
4905         /* Adjust EEE LED frequency */
4906         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4907
4908         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4909         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4910         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4911 }
4912
4913 static void rtl_hw_start_8168f_1(void __iomem *ioaddr, struct pci_dev *pdev)
4914 {
4915         static const struct ephy_info e_info_8168f_1[] = {
4916                 { 0x06, 0x00c0, 0x0020 },
4917                 { 0x08, 0x0001, 0x0002 },
4918                 { 0x09, 0x0000, 0x0080 },
4919                 { 0x19, 0x0000, 0x0224 }
4920         };
4921
4922         rtl_csi_access_enable_1(ioaddr);
4923
4924         rtl_ephy_init(ioaddr, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
4925
4926         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4927
4928         rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4929         rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4930         rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4931         rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4932         rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
4933         rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
4934         rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4935         rtl_w1w0_eri(ioaddr, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4936         rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4937         rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
4938         rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4939                      ERIAR_EXGMAC);
4940
4941         RTL_W8(MaxTxPacketSize, EarlySize);
4942
4943         rtl_disable_clock_request(pdev);
4944
4945         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4946         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4947
4948         /* Adjust EEE LED frequency */
4949         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4950
4951         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4952         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4953         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4954 }
4955
4956 static void rtl_hw_start_8168(struct net_device *dev)
4957 {
4958         struct rtl8169_private *tp = netdev_priv(dev);
4959         void __iomem *ioaddr = tp->mmio_addr;
4960         struct pci_dev *pdev = tp->pci_dev;
4961
4962         RTL_W8(Cfg9346, Cfg9346_Unlock);
4963
4964         RTL_W8(MaxTxPacketSize, TxPacketMax);
4965
4966         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4967
4968         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
4969
4970         RTL_W16(CPlusCmd, tp->cp_cmd);
4971
4972         RTL_W16(IntrMitigate, 0x5151);
4973
4974         /* Work around for RxFIFO overflow. */
4975         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
4976                 tp->event_slow |= RxFIFOOver | PCSTimeout;
4977                 tp->event_slow &= ~RxOverflow;
4978         }
4979
4980         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4981
4982         rtl_set_rx_mode(dev);
4983
4984         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4985                 (InterFrameGap << TxInterFrameGapShift));
4986
4987         RTL_R8(IntrMask);
4988
4989         switch (tp->mac_version) {
4990         case RTL_GIGA_MAC_VER_11:
4991                 rtl_hw_start_8168bb(ioaddr, pdev);
4992                 break;
4993
4994         case RTL_GIGA_MAC_VER_12:
4995         case RTL_GIGA_MAC_VER_17:
4996                 rtl_hw_start_8168bef(ioaddr, pdev);
4997                 break;
4998
4999         case RTL_GIGA_MAC_VER_18:
5000                 rtl_hw_start_8168cp_1(ioaddr, pdev);
5001                 break;
5002
5003         case RTL_GIGA_MAC_VER_19:
5004                 rtl_hw_start_8168c_1(ioaddr, pdev);
5005                 break;
5006
5007         case RTL_GIGA_MAC_VER_20:
5008                 rtl_hw_start_8168c_2(ioaddr, pdev);
5009                 break;
5010
5011         case RTL_GIGA_MAC_VER_21:
5012                 rtl_hw_start_8168c_3(ioaddr, pdev);
5013                 break;
5014
5015         case RTL_GIGA_MAC_VER_22:
5016                 rtl_hw_start_8168c_4(ioaddr, pdev);
5017                 break;
5018
5019         case RTL_GIGA_MAC_VER_23:
5020                 rtl_hw_start_8168cp_2(ioaddr, pdev);
5021                 break;
5022
5023         case RTL_GIGA_MAC_VER_24:
5024                 rtl_hw_start_8168cp_3(ioaddr, pdev);
5025                 break;
5026
5027         case RTL_GIGA_MAC_VER_25:
5028         case RTL_GIGA_MAC_VER_26:
5029         case RTL_GIGA_MAC_VER_27:
5030                 rtl_hw_start_8168d(ioaddr, pdev);
5031                 break;
5032
5033         case RTL_GIGA_MAC_VER_28:
5034                 rtl_hw_start_8168d_4(ioaddr, pdev);
5035                 break;
5036
5037         case RTL_GIGA_MAC_VER_31:
5038                 rtl_hw_start_8168dp(ioaddr, pdev);
5039                 break;
5040
5041         case RTL_GIGA_MAC_VER_32:
5042         case RTL_GIGA_MAC_VER_33:
5043                 rtl_hw_start_8168e_1(ioaddr, pdev);
5044                 break;
5045         case RTL_GIGA_MAC_VER_34:
5046                 rtl_hw_start_8168e_2(ioaddr, pdev);
5047                 break;
5048
5049         case RTL_GIGA_MAC_VER_35:
5050         case RTL_GIGA_MAC_VER_36:
5051                 rtl_hw_start_8168f_1(ioaddr, pdev);
5052                 break;
5053
5054         default:
5055                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
5056                         dev->name, tp->mac_version);
5057                 break;
5058         }
5059
5060         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5061
5062         RTL_W8(Cfg9346, Cfg9346_Lock);
5063
5064         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
5065 }
5066
5067 #define R810X_CPCMD_QUIRK_MASK (\
5068         EnableBist | \
5069         Mac_dbgo_oe | \
5070         Force_half_dup | \
5071         Force_rxflow_en | \
5072         Force_txflow_en | \
5073         Cxpl_dbg_sel | \
5074         ASF | \
5075         PktCntrDisable | \
5076         Mac_dbgo_sel)
5077
5078 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
5079 {
5080         static const struct ephy_info e_info_8102e_1[] = {
5081                 { 0x01, 0, 0x6e65 },
5082                 { 0x02, 0, 0x091f },
5083                 { 0x03, 0, 0xc2f9 },
5084                 { 0x06, 0, 0xafb5 },
5085                 { 0x07, 0, 0x0e00 },
5086                 { 0x19, 0, 0xec80 },
5087                 { 0x01, 0, 0x2e65 },
5088                 { 0x01, 0, 0x6e65 }
5089         };
5090         u8 cfg1;
5091
5092         rtl_csi_access_enable_2(ioaddr);
5093
5094         RTL_W8(DBG_REG, FIX_NAK_1);
5095
5096         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5097
5098         RTL_W8(Config1,
5099                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5100         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5101
5102         cfg1 = RTL_R8(Config1);
5103         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5104                 RTL_W8(Config1, cfg1 & ~LEDS0);
5105
5106         rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
5107 }
5108
5109 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
5110 {
5111         rtl_csi_access_enable_2(ioaddr);
5112
5113         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5114
5115         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
5116         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5117 }
5118
5119 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
5120 {
5121         rtl_hw_start_8102e_2(ioaddr, pdev);
5122
5123         rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
5124 }
5125
5126 static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
5127 {
5128         static const struct ephy_info e_info_8105e_1[] = {
5129                 { 0x07, 0, 0x4000 },
5130                 { 0x19, 0, 0x0200 },
5131                 { 0x19, 0, 0x0020 },
5132                 { 0x1e, 0, 0x2000 },
5133                 { 0x03, 0, 0x0001 },
5134                 { 0x19, 0, 0x0100 },
5135                 { 0x19, 0, 0x0004 },
5136                 { 0x0a, 0, 0x0020 }
5137         };
5138
5139         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5140         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5141
5142         /* Disable Early Tally Counter */
5143         RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
5144
5145         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
5146         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5147
5148         rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
5149 }
5150
5151 static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
5152 {
5153         rtl_hw_start_8105e_1(ioaddr, pdev);
5154         rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
5155 }
5156
5157 static void rtl_hw_start_8101(struct net_device *dev)
5158 {
5159         struct rtl8169_private *tp = netdev_priv(dev);
5160         void __iomem *ioaddr = tp->mmio_addr;
5161         struct pci_dev *pdev = tp->pci_dev;
5162
5163         if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5164                 tp->event_slow &= ~RxFIFOOver;
5165
5166         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5167             tp->mac_version == RTL_GIGA_MAC_VER_16) {
5168                 int cap = pci_pcie_cap(pdev);
5169
5170                 if (cap) {
5171                         pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
5172                                               PCI_EXP_DEVCTL_NOSNOOP_EN);
5173                 }
5174         }
5175
5176         RTL_W8(Cfg9346, Cfg9346_Unlock);
5177
5178         switch (tp->mac_version) {
5179         case RTL_GIGA_MAC_VER_07:
5180                 rtl_hw_start_8102e_1(ioaddr, pdev);
5181                 break;
5182
5183         case RTL_GIGA_MAC_VER_08:
5184                 rtl_hw_start_8102e_3(ioaddr, pdev);
5185                 break;
5186
5187         case RTL_GIGA_MAC_VER_09:
5188                 rtl_hw_start_8102e_2(ioaddr, pdev);
5189                 break;
5190
5191         case RTL_GIGA_MAC_VER_29:
5192                 rtl_hw_start_8105e_1(ioaddr, pdev);
5193                 break;
5194         case RTL_GIGA_MAC_VER_30:
5195                 rtl_hw_start_8105e_2(ioaddr, pdev);
5196                 break;
5197         }
5198
5199         RTL_W8(Cfg9346, Cfg9346_Lock);
5200
5201         RTL_W8(MaxTxPacketSize, TxPacketMax);
5202
5203         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
5204
5205         tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
5206         RTL_W16(CPlusCmd, tp->cp_cmd);
5207
5208         RTL_W16(IntrMitigate, 0x0000);
5209
5210         rtl_set_rx_tx_desc_registers(tp, ioaddr);
5211
5212         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5213         rtl_set_rx_tx_config_registers(tp);
5214
5215         RTL_R8(IntrMask);
5216
5217         rtl_set_rx_mode(dev);
5218
5219         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
5220 }
5221
5222 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5223 {
5224         struct rtl8169_private *tp = netdev_priv(dev);
5225
5226         if (new_mtu < ETH_ZLEN ||
5227             new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
5228                 return -EINVAL;
5229
5230         if (new_mtu > ETH_DATA_LEN)
5231                 rtl_hw_jumbo_enable(tp);
5232         else
5233                 rtl_hw_jumbo_disable(tp);
5234
5235         dev->mtu = new_mtu;
5236         netdev_update_features(dev);
5237
5238         return 0;
5239 }
5240
5241 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5242 {
5243         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5244         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5245 }
5246
5247 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5248                                      void **data_buff, struct RxDesc *desc)
5249 {
5250         dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
5251                          DMA_FROM_DEVICE);
5252
5253         kfree(*data_buff);
5254         *data_buff = NULL;
5255         rtl8169_make_unusable_by_asic(desc);
5256 }
5257
5258 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
5259 {
5260         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5261
5262         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
5263 }
5264
5265 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
5266                                        u32 rx_buf_sz)
5267 {
5268         desc->addr = cpu_to_le64(mapping);
5269         wmb();
5270         rtl8169_mark_to_asic(desc, rx_buf_sz);
5271 }
5272
5273 static inline void *rtl8169_align(void *data)
5274 {
5275         return (void *)ALIGN((long)data, 16);
5276 }
5277
5278 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5279                                              struct RxDesc *desc)
5280 {
5281         void *data;
5282         dma_addr_t mapping;
5283         struct device *d = &tp->pci_dev->dev;
5284         struct net_device *dev = tp->dev;
5285         int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
5286
5287         data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
5288         if (!data)
5289                 return NULL;
5290
5291         if (rtl8169_align(data) != data) {
5292                 kfree(data);
5293                 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
5294                 if (!data)
5295                         return NULL;
5296         }
5297
5298         mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
5299                                  DMA_FROM_DEVICE);
5300         if (unlikely(dma_mapping_error(d, mapping))) {
5301                 if (net_ratelimit())
5302                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5303                 goto err_out;
5304         }
5305
5306         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
5307         return data;
5308
5309 err_out:
5310         kfree(data);
5311         return NULL;
5312 }
5313
5314 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5315 {
5316         unsigned int i;
5317
5318         for (i = 0; i < NUM_RX_DESC; i++) {
5319                 if (tp->Rx_databuff[i]) {
5320                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
5321                                             tp->RxDescArray + i);
5322                 }
5323         }
5324 }
5325
5326 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5327 {
5328         desc->opts1 |= cpu_to_le32(RingEnd);
5329 }
5330
5331 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5332 {
5333         unsigned int i;
5334
5335         for (i = 0; i < NUM_RX_DESC; i++) {
5336                 void *data;
5337
5338                 if (tp->Rx_databuff[i])
5339                         continue;
5340
5341                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5342                 if (!data) {
5343                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5344                         goto err_out;
5345                 }
5346                 tp->Rx_databuff[i] = data;
5347         }
5348
5349         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5350         return 0;
5351
5352 err_out:
5353         rtl8169_rx_clear(tp);
5354         return -ENOMEM;
5355 }
5356
5357 static int rtl8169_init_ring(struct net_device *dev)
5358 {
5359         struct rtl8169_private *tp = netdev_priv(dev);
5360
5361         rtl8169_init_ring_indexes(tp);
5362
5363         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
5364         memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
5365
5366         return rtl8169_rx_fill(tp);
5367 }
5368
5369 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5370                                  struct TxDesc *desc)
5371 {
5372         unsigned int len = tx_skb->len;
5373
5374         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5375
5376         desc->opts1 = 0x00;
5377         desc->opts2 = 0x00;
5378         desc->addr = 0x00;
5379         tx_skb->len = 0;
5380 }
5381
5382 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5383                                    unsigned int n)
5384 {
5385         unsigned int i;
5386
5387         for (i = 0; i < n; i++) {
5388                 unsigned int entry = (start + i) % NUM_TX_DESC;
5389                 struct ring_info *tx_skb = tp->tx_skb + entry;
5390                 unsigned int len = tx_skb->len;
5391
5392                 if (len) {
5393                         struct sk_buff *skb = tx_skb->skb;
5394
5395                         rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5396                                              tp->TxDescArray + entry);
5397                         if (skb) {
5398                                 tp->dev->stats.tx_dropped++;
5399                                 dev_kfree_skb(skb);
5400                                 tx_skb->skb = NULL;
5401                         }
5402                 }
5403         }
5404 }
5405
5406 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5407 {
5408         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5409         tp->cur_tx = tp->dirty_tx = 0;
5410         netdev_reset_queue(tp->dev);
5411 }
5412
5413 static void rtl_reset_work(struct rtl8169_private *tp)
5414 {
5415         struct net_device *dev = tp->dev;
5416         int i;
5417
5418         napi_disable(&tp->napi);
5419         netif_stop_queue(dev);
5420         synchronize_sched();
5421
5422         rtl8169_hw_reset(tp);
5423
5424         for (i = 0; i < NUM_RX_DESC; i++)
5425                 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
5426
5427         rtl8169_tx_clear(tp);
5428         rtl8169_init_ring_indexes(tp);
5429
5430         napi_enable(&tp->napi);
5431         rtl_hw_start(dev);
5432         netif_wake_queue(dev);
5433         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
5434 }
5435
5436 static void rtl8169_tx_timeout(struct net_device *dev)
5437 {
5438         struct rtl8169_private *tp = netdev_priv(dev);
5439
5440         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5441 }
5442
5443 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5444                               u32 *opts)
5445 {
5446         struct skb_shared_info *info = skb_shinfo(skb);
5447         unsigned int cur_frag, entry;
5448         struct TxDesc * uninitialized_var(txd);
5449         struct device *d = &tp->pci_dev->dev;
5450
5451         entry = tp->cur_tx;
5452         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5453                 const skb_frag_t *frag = info->frags + cur_frag;
5454                 dma_addr_t mapping;
5455                 u32 status, len;
5456                 void *addr;
5457
5458                 entry = (entry + 1) % NUM_TX_DESC;
5459
5460                 txd = tp->TxDescArray + entry;
5461                 len = skb_frag_size(frag);
5462                 addr = skb_frag_address(frag);
5463                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5464                 if (unlikely(dma_mapping_error(d, mapping))) {
5465                         if (net_ratelimit())
5466                                 netif_err(tp, drv, tp->dev,
5467                                           "Failed to map TX fragments DMA!\n");
5468                         goto err_out;
5469                 }
5470
5471                 /* Anti gcc 2.95.3 bugware (sic) */
5472                 status = opts[0] | len |
5473                         (RingEnd * !((entry + 1) % NUM_TX_DESC));
5474
5475                 txd->opts1 = cpu_to_le32(status);
5476                 txd->opts2 = cpu_to_le32(opts[1]);
5477                 txd->addr = cpu_to_le64(mapping);
5478
5479                 tp->tx_skb[entry].len = len;
5480         }
5481
5482         if (cur_frag) {
5483                 tp->tx_skb[entry].skb = skb;
5484                 txd->opts1 |= cpu_to_le32(LastFrag);
5485         }
5486
5487         return cur_frag;
5488
5489 err_out:
5490         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5491         return -EIO;
5492 }
5493
5494 static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
5495                                     struct sk_buff *skb, u32 *opts)
5496 {
5497         const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
5498         u32 mss = skb_shinfo(skb)->gso_size;
5499         int offset = info->opts_offset;
5500
5501         if (mss) {
5502                 opts[0] |= TD_LSO;
5503                 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
5504         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5505                 const struct iphdr *ip = ip_hdr(skb);
5506
5507                 if (ip->protocol == IPPROTO_TCP)
5508                         opts[offset] |= info->checksum.tcp;
5509                 else if (ip->protocol == IPPROTO_UDP)
5510                         opts[offset] |= info->checksum.udp;
5511                 else
5512                         WARN_ON_ONCE(1);
5513         }
5514 }
5515
5516 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5517                                       struct net_device *dev)
5518 {
5519         struct rtl8169_private *tp = netdev_priv(dev);
5520         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
5521         struct TxDesc *txd = tp->TxDescArray + entry;
5522         void __iomem *ioaddr = tp->mmio_addr;
5523         struct device *d = &tp->pci_dev->dev;
5524         dma_addr_t mapping;
5525         u32 status, len;
5526         u32 opts[2];
5527         int frags;
5528
5529         if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
5530                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
5531                 goto err_stop_0;
5532         }
5533
5534         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
5535                 goto err_stop_0;
5536
5537         len = skb_headlen(skb);
5538         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
5539         if (unlikely(dma_mapping_error(d, mapping))) {
5540                 if (net_ratelimit())
5541                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
5542                 goto err_dma_0;
5543         }
5544
5545         tp->tx_skb[entry].len = len;
5546         txd->addr = cpu_to_le64(mapping);
5547
5548         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
5549         opts[0] = DescOwn;
5550
5551         rtl8169_tso_csum(tp, skb, opts);
5552
5553         frags = rtl8169_xmit_frags(tp, skb, opts);
5554         if (frags < 0)
5555                 goto err_dma_1;
5556         else if (frags)
5557                 opts[0] |= FirstFrag;
5558         else {
5559                 opts[0] |= FirstFrag | LastFrag;
5560                 tp->tx_skb[entry].skb = skb;
5561         }
5562
5563         txd->opts2 = cpu_to_le32(opts[1]);
5564
5565         netdev_sent_queue(dev, skb->len);
5566
5567         wmb();
5568
5569         /* Anti gcc 2.95.3 bugware (sic) */
5570         status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
5571         txd->opts1 = cpu_to_le32(status);
5572
5573         tp->cur_tx += frags + 1;
5574
5575         wmb();
5576
5577         RTL_W8(TxPoll, NPQ);
5578
5579         mmiowb();
5580
5581         if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
5582                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
5583                  * not miss a ring update when it notices a stopped queue.
5584                  */
5585                 smp_wmb();
5586                 netif_stop_queue(dev);
5587                 /* Sync with rtl_tx:
5588                  * - publish queue status and cur_tx ring index (write barrier)
5589                  * - refresh dirty_tx ring index (read barrier).
5590                  * May the current thread have a pessimistic view of the ring
5591                  * status and forget to wake up queue, a racing rtl_tx thread
5592                  * can't.
5593                  */
5594                 smp_mb();
5595                 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
5596                         netif_wake_queue(dev);
5597         }
5598
5599         return NETDEV_TX_OK;
5600
5601 err_dma_1:
5602         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
5603 err_dma_0:
5604         dev_kfree_skb(skb);
5605         dev->stats.tx_dropped++;
5606         return NETDEV_TX_OK;
5607
5608 err_stop_0:
5609         netif_stop_queue(dev);
5610         dev->stats.tx_dropped++;
5611         return NETDEV_TX_BUSY;
5612 }
5613
5614 static void rtl8169_pcierr_interrupt(struct net_device *dev)
5615 {
5616         struct rtl8169_private *tp = netdev_priv(dev);
5617         struct pci_dev *pdev = tp->pci_dev;
5618         u16 pci_status, pci_cmd;
5619
5620         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5621         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5622
5623         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5624                   pci_cmd, pci_status);
5625
5626         /*
5627          * The recovery sequence below admits a very elaborated explanation:
5628          * - it seems to work;
5629          * - I did not see what else could be done;
5630          * - it makes iop3xx happy.
5631          *
5632          * Feel free to adjust to your needs.
5633          */
5634         if (pdev->broken_parity_status)
5635                 pci_cmd &= ~PCI_COMMAND_PARITY;
5636         else
5637                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5638
5639         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
5640
5641         pci_write_config_word(pdev, PCI_STATUS,
5642                 pci_status & (PCI_STATUS_DETECTED_PARITY |
5643                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5644                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5645
5646         /* The infamous DAC f*ckup only happens at boot time */
5647         if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
5648                 void __iomem *ioaddr = tp->mmio_addr;
5649
5650                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
5651                 tp->cp_cmd &= ~PCIDAC;
5652                 RTL_W16(CPlusCmd, tp->cp_cmd);
5653                 dev->features &= ~NETIF_F_HIGHDMA;
5654         }
5655
5656         rtl8169_hw_reset(tp);
5657
5658         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5659 }
5660
5661 struct rtl_txc {
5662         int packets;
5663         int bytes;
5664 };
5665
5666 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
5667 {
5668         struct rtl8169_stats *tx_stats = &tp->tx_stats;
5669         unsigned int dirty_tx, tx_left;
5670         struct rtl_txc txc = { 0, 0 };
5671
5672         dirty_tx = tp->dirty_tx;
5673         smp_rmb();
5674         tx_left = tp->cur_tx - dirty_tx;
5675
5676         while (tx_left > 0) {
5677                 unsigned int entry = dirty_tx % NUM_TX_DESC;
5678                 struct ring_info *tx_skb = tp->tx_skb + entry;
5679                 u32 status;
5680
5681                 rmb();
5682                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5683                 if (status & DescOwn)
5684                         break;
5685
5686                 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5687                                      tp->TxDescArray + entry);
5688                 if (status & LastFrag) {
5689                         struct sk_buff *skb = tx_skb->skb;
5690
5691                         txc.packets++;
5692                         txc.bytes += skb->len;
5693                         dev_kfree_skb(skb);
5694                         tx_skb->skb = NULL;
5695                 }
5696                 dirty_tx++;
5697                 tx_left--;
5698         }
5699
5700         u64_stats_update_begin(&tx_stats->syncp);
5701         tx_stats->packets += txc.packets;
5702         tx_stats->bytes += txc.bytes;
5703         u64_stats_update_end(&tx_stats->syncp);
5704
5705         netdev_completed_queue(dev, txc.packets, txc.bytes);
5706
5707         if (tp->dirty_tx != dirty_tx) {
5708                 tp->dirty_tx = dirty_tx;
5709                 /* Sync with rtl8169_start_xmit:
5710                  * - publish dirty_tx ring index (write barrier)
5711                  * - refresh cur_tx ring index and queue status (read barrier)
5712                  * May the current thread miss the stopped queue condition,
5713                  * a racing xmit thread can only have a right view of the
5714                  * ring status.
5715                  */
5716                 smp_mb();
5717                 if (netif_queue_stopped(dev) &&
5718                     (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
5719                         netif_wake_queue(dev);
5720                 }
5721                 /*
5722                  * 8168 hack: TxPoll requests are lost when the Tx packets are
5723                  * too close. Let's kick an extra TxPoll request when a burst
5724                  * of start_xmit activity is detected (if it is not detected,
5725                  * it is slow enough). -- FR
5726                  */
5727                 if (tp->cur_tx != dirty_tx) {
5728                         void __iomem *ioaddr = tp->mmio_addr;
5729
5730                         RTL_W8(TxPoll, NPQ);
5731                 }
5732         }
5733 }
5734
5735 static inline int rtl8169_fragmented_frame(u32 status)
5736 {
5737         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5738 }
5739
5740 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
5741 {
5742         u32 status = opts1 & RxProtoMask;
5743
5744         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
5745             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
5746                 skb->ip_summed = CHECKSUM_UNNECESSARY;
5747         else
5748                 skb_checksum_none_assert(skb);
5749 }
5750
5751 static struct sk_buff *rtl8169_try_rx_copy(void *data,
5752                                            struct rtl8169_private *tp,
5753                                            int pkt_size,
5754                                            dma_addr_t addr)
5755 {
5756         struct sk_buff *skb;
5757         struct device *d = &tp->pci_dev->dev;
5758
5759         data = rtl8169_align(data);
5760         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
5761         prefetch(data);
5762         skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
5763         if (skb)
5764                 memcpy(skb->data, data, pkt_size);
5765         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
5766
5767         return skb;
5768 }
5769
5770 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
5771 {
5772         unsigned int cur_rx, rx_left;
5773         unsigned int count;
5774
5775         cur_rx = tp->cur_rx;
5776         rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
5777         rx_left = min(rx_left, budget);
5778
5779         for (; rx_left > 0; rx_left--, cur_rx++) {
5780                 unsigned int entry = cur_rx % NUM_RX_DESC;
5781                 struct RxDesc *desc = tp->RxDescArray + entry;
5782                 u32 status;
5783
5784                 rmb();
5785                 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
5786
5787                 if (status & DescOwn)
5788                         break;
5789                 if (unlikely(status & RxRES)) {
5790                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
5791                                    status);
5792                         dev->stats.rx_errors++;
5793                         if (status & (RxRWT | RxRUNT))
5794                                 dev->stats.rx_length_errors++;
5795                         if (status & RxCRC)
5796                                 dev->stats.rx_crc_errors++;
5797                         if (status & RxFOVF) {
5798                                 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5799                                 dev->stats.rx_fifo_errors++;
5800                         }
5801                         if ((status & (RxRUNT | RxCRC)) &&
5802                             !(status & (RxRWT | RxFOVF)) &&
5803                             (dev->features & NETIF_F_RXALL))
5804                                 goto process_pkt;
5805
5806                         rtl8169_mark_to_asic(desc, rx_buf_sz);
5807                 } else {
5808                         struct sk_buff *skb;
5809                         dma_addr_t addr;
5810                         int pkt_size;
5811
5812 process_pkt:
5813                         addr = le64_to_cpu(desc->addr);
5814                         if (likely(!(dev->features & NETIF_F_RXFCS)))
5815                                 pkt_size = (status & 0x00003fff) - 4;
5816                         else
5817                                 pkt_size = status & 0x00003fff;
5818
5819                         /*
5820                          * The driver does not support incoming fragmented
5821                          * frames. They are seen as a symptom of over-mtu
5822                          * sized frames.
5823                          */
5824                         if (unlikely(rtl8169_fragmented_frame(status))) {
5825                                 dev->stats.rx_dropped++;
5826                                 dev->stats.rx_length_errors++;
5827                                 rtl8169_mark_to_asic(desc, rx_buf_sz);
5828                                 continue;
5829                         }
5830
5831                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
5832                                                   tp, pkt_size, addr);
5833                         rtl8169_mark_to_asic(desc, rx_buf_sz);
5834                         if (!skb) {
5835                                 dev->stats.rx_dropped++;
5836                                 continue;
5837                         }
5838
5839                         rtl8169_rx_csum(skb, status);
5840                         skb_put(skb, pkt_size);
5841                         skb->protocol = eth_type_trans(skb, dev);
5842
5843                         rtl8169_rx_vlan_tag(desc, skb);
5844
5845                         napi_gro_receive(&tp->napi, skb);
5846
5847                         u64_stats_update_begin(&tp->rx_stats.syncp);
5848                         tp->rx_stats.packets++;
5849                         tp->rx_stats.bytes += pkt_size;
5850                         u64_stats_update_end(&tp->rx_stats.syncp);
5851                 }
5852
5853                 /* Work around for AMD plateform. */
5854                 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
5855                     (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
5856                         desc->opts2 = 0;
5857                         cur_rx++;
5858                 }
5859         }
5860
5861         count = cur_rx - tp->cur_rx;
5862         tp->cur_rx = cur_rx;
5863
5864         tp->dirty_rx += count;
5865
5866         return count;
5867 }
5868
5869 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
5870 {
5871         struct net_device *dev = dev_instance;
5872         struct rtl8169_private *tp = netdev_priv(dev);
5873         int handled = 0;
5874         u16 status;
5875
5876         status = rtl_get_events(tp);
5877         if (status && status != 0xffff) {
5878                 status &= RTL_EVENT_NAPI | tp->event_slow;
5879                 if (status) {
5880                         handled = 1;
5881
5882                         rtl_irq_disable(tp);
5883                         napi_schedule(&tp->napi);
5884                 }
5885         }
5886         return IRQ_RETVAL(handled);
5887 }
5888
5889 /*
5890  * Workqueue context.
5891  */
5892 static void rtl_slow_event_work(struct rtl8169_private *tp)
5893 {
5894         struct net_device *dev = tp->dev;
5895         u16 status;
5896
5897         status = rtl_get_events(tp) & tp->event_slow;
5898         rtl_ack_events(tp, status);
5899
5900         if (unlikely(status & RxFIFOOver)) {
5901                 switch (tp->mac_version) {
5902                 /* Work around for rx fifo overflow */
5903                 case RTL_GIGA_MAC_VER_11:
5904                         netif_stop_queue(dev);
5905                         /* XXX - Hack alert. See rtl_task(). */
5906                         set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
5907                 default:
5908                         break;
5909                 }
5910         }
5911
5912         if (unlikely(status & SYSErr))
5913                 rtl8169_pcierr_interrupt(dev);
5914
5915         if (status & LinkChg)
5916                 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
5917
5918         napi_disable(&tp->napi);
5919         rtl_irq_disable(tp);
5920
5921         napi_enable(&tp->napi);
5922         napi_schedule(&tp->napi);
5923 }
5924
5925 static void rtl_task(struct work_struct *work)
5926 {
5927         static const struct {
5928                 int bitnr;
5929                 void (*action)(struct rtl8169_private *);
5930         } rtl_work[] = {
5931                 /* XXX - keep rtl_slow_event_work() as first element. */
5932                 { RTL_FLAG_TASK_SLOW_PENDING,   rtl_slow_event_work },
5933                 { RTL_FLAG_TASK_RESET_PENDING,  rtl_reset_work },
5934                 { RTL_FLAG_TASK_PHY_PENDING,    rtl_phy_work }
5935         };
5936         struct rtl8169_private *tp =
5937                 container_of(work, struct rtl8169_private, wk.work);
5938         struct net_device *dev = tp->dev;
5939         int i;
5940
5941         rtl_lock_work(tp);
5942
5943         if (!netif_running(dev) ||
5944             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
5945                 goto out_unlock;
5946
5947         for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
5948                 bool pending;
5949
5950                 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
5951                 if (pending)
5952                         rtl_work[i].action(tp);
5953         }
5954
5955 out_unlock:
5956         rtl_unlock_work(tp);
5957 }
5958
5959 static int rtl8169_poll(struct napi_struct *napi, int budget)
5960 {
5961         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5962         struct net_device *dev = tp->dev;
5963         u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
5964         int work_done= 0;
5965         u16 status;
5966
5967         status = rtl_get_events(tp);
5968         rtl_ack_events(tp, status & ~tp->event_slow);
5969
5970         if (status & RTL_EVENT_NAPI_RX)
5971                 work_done = rtl_rx(dev, tp, (u32) budget);
5972
5973         if (status & RTL_EVENT_NAPI_TX)
5974                 rtl_tx(dev, tp);
5975
5976         if (status & tp->event_slow) {
5977                 enable_mask &= ~tp->event_slow;
5978
5979                 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
5980         }
5981
5982         if (work_done < budget) {
5983                 napi_complete(napi);
5984
5985                 rtl_irq_enable(tp, enable_mask);
5986                 mmiowb();
5987         }
5988
5989         return work_done;
5990 }
5991
5992 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5993 {
5994         struct rtl8169_private *tp = netdev_priv(dev);
5995
5996         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5997                 return;
5998
5999         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
6000         RTL_W32(RxMissed, 0);
6001 }
6002
6003 static void rtl8169_down(struct net_device *dev)
6004 {
6005         struct rtl8169_private *tp = netdev_priv(dev);
6006         void __iomem *ioaddr = tp->mmio_addr;
6007
6008         del_timer_sync(&tp->timer);
6009
6010         napi_disable(&tp->napi);
6011         netif_stop_queue(dev);
6012
6013         rtl8169_hw_reset(tp);
6014         /*
6015          * At this point device interrupts can not be enabled in any function,
6016          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6017          * and napi is disabled (rtl8169_poll).
6018          */
6019         rtl8169_rx_missed(dev, ioaddr);
6020
6021         /* Give a racing hard_start_xmit a few cycles to complete. */
6022         synchronize_sched();
6023
6024         rtl8169_tx_clear(tp);
6025
6026         rtl8169_rx_clear(tp);
6027
6028         rtl_pll_power_down(tp);
6029 }
6030
6031 static int rtl8169_close(struct net_device *dev)
6032 {
6033         struct rtl8169_private *tp = netdev_priv(dev);
6034         struct pci_dev *pdev = tp->pci_dev;
6035
6036         pm_runtime_get_sync(&pdev->dev);
6037
6038         /* Update counters before going down */
6039         rtl8169_update_counters(dev);
6040
6041         rtl_lock_work(tp);
6042         clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6043
6044         rtl8169_down(dev);
6045         rtl_unlock_work(tp);
6046
6047         free_irq(dev->irq, dev);
6048
6049         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6050                           tp->RxPhyAddr);
6051         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6052                           tp->TxPhyAddr);
6053         tp->TxDescArray = NULL;
6054         tp->RxDescArray = NULL;
6055
6056         pm_runtime_put_sync(&pdev->dev);
6057
6058         return 0;
6059 }
6060
6061 static void rtl_set_rx_mode(struct net_device *dev)
6062 {
6063         struct rtl8169_private *tp = netdev_priv(dev);
6064         void __iomem *ioaddr = tp->mmio_addr;
6065         u32 mc_filter[2];       /* Multicast hash filter */
6066         int rx_mode;
6067         u32 tmp = 0;
6068
6069         if (dev->flags & IFF_PROMISC) {
6070                 /* Unconditionally log net taps. */
6071                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
6072                 rx_mode =
6073                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
6074                     AcceptAllPhys;
6075                 mc_filter[1] = mc_filter[0] = 0xffffffff;
6076         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
6077                    (dev->flags & IFF_ALLMULTI)) {
6078                 /* Too many to filter perfectly -- accept all multicasts. */
6079                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
6080                 mc_filter[1] = mc_filter[0] = 0xffffffff;
6081         } else {
6082                 struct netdev_hw_addr *ha;
6083
6084                 rx_mode = AcceptBroadcast | AcceptMyPhys;
6085                 mc_filter[1] = mc_filter[0] = 0;
6086                 netdev_for_each_mc_addr(ha, dev) {
6087                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
6088                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
6089                         rx_mode |= AcceptMulticast;
6090                 }
6091         }
6092
6093         if (dev->features & NETIF_F_RXALL)
6094                 rx_mode |= (AcceptErr | AcceptRunt);
6095
6096         tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
6097
6098         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
6099                 u32 data = mc_filter[0];
6100
6101                 mc_filter[0] = swab32(mc_filter[1]);
6102                 mc_filter[1] = swab32(data);
6103         }
6104
6105         RTL_W32(MAR0 + 4, mc_filter[1]);
6106         RTL_W32(MAR0 + 0, mc_filter[0]);
6107
6108         RTL_W32(RxConfig, tmp);
6109 }
6110
6111 static struct rtnl_link_stats64 *
6112 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6113 {
6114         struct rtl8169_private *tp = netdev_priv(dev);
6115         void __iomem *ioaddr = tp->mmio_addr;
6116         unsigned int start;
6117
6118         if (netif_running(dev))
6119                 rtl8169_rx_missed(dev, ioaddr);
6120
6121         do {
6122                 start = u64_stats_fetch_begin_bh(&tp->rx_stats.syncp);
6123                 stats->rx_packets = tp->rx_stats.packets;
6124                 stats->rx_bytes = tp->rx_stats.bytes;
6125         } while (u64_stats_fetch_retry_bh(&tp->rx_stats.syncp, start));
6126
6127
6128         do {
6129                 start = u64_stats_fetch_begin_bh(&tp->tx_stats.syncp);
6130                 stats->tx_packets = tp->tx_stats.packets;
6131                 stats->tx_bytes = tp->tx_stats.bytes;
6132         } while (u64_stats_fetch_retry_bh(&tp->tx_stats.syncp, start));
6133
6134         stats->rx_dropped       = dev->stats.rx_dropped;
6135         stats->tx_dropped       = dev->stats.tx_dropped;
6136         stats->rx_length_errors = dev->stats.rx_length_errors;
6137         stats->rx_errors        = dev->stats.rx_errors;
6138         stats->rx_crc_errors    = dev->stats.rx_crc_errors;
6139         stats->rx_fifo_errors   = dev->stats.rx_fifo_errors;
6140         stats->rx_missed_errors = dev->stats.rx_missed_errors;
6141
6142         return stats;
6143 }
6144
6145 static void rtl8169_net_suspend(struct net_device *dev)
6146 {
6147         struct rtl8169_private *tp = netdev_priv(dev);
6148
6149         if (!netif_running(dev))
6150                 return;
6151
6152         netif_device_detach(dev);
6153         netif_stop_queue(dev);
6154
6155         rtl_lock_work(tp);
6156         napi_disable(&tp->napi);
6157         clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6158         rtl_unlock_work(tp);
6159
6160         rtl_pll_power_down(tp);
6161 }
6162
6163 #ifdef CONFIG_PM
6164
6165 static int rtl8169_suspend(struct device *device)
6166 {
6167         struct pci_dev *pdev = to_pci_dev(device);
6168         struct net_device *dev = pci_get_drvdata(pdev);
6169
6170         rtl8169_net_suspend(dev);
6171
6172         return 0;
6173 }
6174
6175 static void __rtl8169_resume(struct net_device *dev)
6176 {
6177         struct rtl8169_private *tp = netdev_priv(dev);
6178
6179         netif_device_attach(dev);
6180
6181         rtl_pll_power_up(tp);
6182
6183         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6184
6185         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6186 }
6187
6188 static int rtl8169_resume(struct device *device)
6189 {
6190         struct pci_dev *pdev = to_pci_dev(device);
6191         struct net_device *dev = pci_get_drvdata(pdev);
6192         struct rtl8169_private *tp = netdev_priv(dev);
6193
6194         rtl8169_init_phy(dev, tp);
6195
6196         if (netif_running(dev))
6197                 __rtl8169_resume(dev);
6198
6199         return 0;
6200 }
6201
6202 static int rtl8169_runtime_suspend(struct device *device)
6203 {
6204         struct pci_dev *pdev = to_pci_dev(device);
6205         struct net_device *dev = pci_get_drvdata(pdev);
6206         struct rtl8169_private *tp = netdev_priv(dev);
6207
6208         if (!tp->TxDescArray)
6209                 return 0;
6210
6211         rtl_lock_work(tp);
6212         tp->saved_wolopts = __rtl8169_get_wol(tp);
6213         __rtl8169_set_wol(tp, WAKE_ANY);
6214         rtl_unlock_work(tp);
6215
6216         rtl8169_net_suspend(dev);
6217
6218         return 0;
6219 }
6220
6221 static int rtl8169_runtime_resume(struct device *device)
6222 {
6223         struct pci_dev *pdev = to_pci_dev(device);
6224         struct net_device *dev = pci_get_drvdata(pdev);
6225         struct rtl8169_private *tp = netdev_priv(dev);
6226
6227         if (!tp->TxDescArray)
6228                 return 0;
6229
6230         rtl_lock_work(tp);
6231         __rtl8169_set_wol(tp, tp->saved_wolopts);
6232         tp->saved_wolopts = 0;
6233         rtl_unlock_work(tp);
6234
6235         rtl8169_init_phy(dev, tp);
6236
6237         __rtl8169_resume(dev);
6238
6239         return 0;
6240 }
6241
6242 static int rtl8169_runtime_idle(struct device *device)
6243 {
6244         struct pci_dev *pdev = to_pci_dev(device);
6245         struct net_device *dev = pci_get_drvdata(pdev);
6246         struct rtl8169_private *tp = netdev_priv(dev);
6247
6248         return tp->TxDescArray ? -EBUSY : 0;
6249 }
6250
6251 static const struct dev_pm_ops rtl8169_pm_ops = {
6252         .suspend                = rtl8169_suspend,
6253         .resume                 = rtl8169_resume,
6254         .freeze                 = rtl8169_suspend,
6255         .thaw                   = rtl8169_resume,
6256         .poweroff               = rtl8169_suspend,
6257         .restore                = rtl8169_resume,
6258         .runtime_suspend        = rtl8169_runtime_suspend,
6259         .runtime_resume         = rtl8169_runtime_resume,
6260         .runtime_idle           = rtl8169_runtime_idle,
6261 };
6262
6263 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
6264
6265 #else /* !CONFIG_PM */
6266
6267 #define RTL8169_PM_OPS  NULL
6268
6269 #endif /* !CONFIG_PM */
6270
6271 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6272 {
6273         void __iomem *ioaddr = tp->mmio_addr;
6274
6275         /* WoL fails with 8168b when the receiver is disabled. */
6276         switch (tp->mac_version) {
6277         case RTL_GIGA_MAC_VER_11:
6278         case RTL_GIGA_MAC_VER_12:
6279         case RTL_GIGA_MAC_VER_17:
6280                 pci_clear_master(tp->pci_dev);
6281
6282                 RTL_W8(ChipCmd, CmdRxEnb);
6283                 /* PCI commit */
6284                 RTL_R8(ChipCmd);
6285                 break;
6286         default:
6287                 break;
6288         }
6289 }
6290
6291 static void rtl_shutdown(struct pci_dev *pdev)
6292 {
6293         struct net_device *dev = pci_get_drvdata(pdev);
6294         struct rtl8169_private *tp = netdev_priv(dev);
6295         struct device *d = &pdev->dev;
6296
6297         pm_runtime_get_sync(d);
6298
6299         rtl8169_net_suspend(dev);
6300
6301         /* Restore original MAC address */
6302         rtl_rar_set(tp, dev->perm_addr);
6303
6304         rtl8169_hw_reset(tp);
6305
6306         if (system_state == SYSTEM_POWER_OFF) {
6307                 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
6308                         rtl_wol_suspend_quirk(tp);
6309                         rtl_wol_shutdown_quirk(tp);
6310                 }
6311
6312                 pci_wake_from_d3(pdev, true);
6313                 pci_set_power_state(pdev, PCI_D3hot);
6314         }
6315
6316         pm_runtime_put_noidle(d);
6317 }
6318
6319 static struct pci_driver rtl8169_pci_driver = {
6320         .name           = MODULENAME,
6321         .id_table       = rtl8169_pci_tbl,
6322         .probe          = rtl8169_init_one,
6323         .remove         = __devexit_p(rtl8169_remove_one),
6324         .shutdown       = rtl_shutdown,
6325         .driver.pm      = RTL8169_PM_OPS,
6326 };
6327
6328 static int __init rtl8169_init_module(void)
6329 {
6330         return pci_register_driver(&rtl8169_pci_driver);
6331 }
6332
6333 static void __exit rtl8169_cleanup_module(void)
6334 {
6335         pci_unregister_driver(&rtl8169_pci_driver);
6336 }
6337
6338 module_init(rtl8169_init_module);
6339 module_exit(rtl8169_cleanup_module);