drivers/net/ethernet/realtek/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/firmware.h>
  28 #include <linux/pci-aspm.h>
  29 #include <linux/prefetch.h>
  30 #include <linux/ipv6.h>
  31 #include <net/ip6_checksum.h>
  32
  33 #include <asm/io.h>
  34 #include <asm/irq.h>
  35
  36 #define RTL8169_VERSION "2.3LK-NAPI"
  37 #define MODULENAME "r8169"
  38 #define PFX MODULENAME ": "
  39
  40 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  41 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  42 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  43 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  44 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  45 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  46 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  47 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  48 #define FIRMWARE_8402_1         "rtl_nic/rtl8402-1.fw"
  49 #define FIRMWARE_8411_1         "rtl_nic/rtl8411-1.fw"
  50 #define FIRMWARE_8411_2         "rtl_nic/rtl8411-2.fw"
  51 #define FIRMWARE_8106E_1        "rtl_nic/rtl8106e-1.fw"
  52 #define FIRMWARE_8106E_2        "rtl_nic/rtl8106e-2.fw"
  53 #define FIRMWARE_8168G_2        "rtl_nic/rtl8168g-2.fw"
  54 #define FIRMWARE_8168G_3        "rtl_nic/rtl8168g-3.fw"
  55 #define FIRMWARE_8168H_1        "rtl_nic/rtl8168h-1.fw"
  56 #define FIRMWARE_8168H_2        "rtl_nic/rtl8168h-2.fw"
  57 #define FIRMWARE_8107E_1        "rtl_nic/rtl8107e-1.fw"
  58 #define FIRMWARE_8107E_2        "rtl_nic/rtl8107e-2.fw"
  59
  60 #ifdef RTL8169_DEBUG
  61 #define assert(expr) \
  62         if (!(expr)) {                                  \
  63                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  64                 #expr,__FILE__,__func__,__LINE__);              \
  65         }
  66 #define dprintk(fmt, args...) \
  67         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  68 #else
  69 #define assert(expr) do {} while (0)
  70 #define dprintk(fmt, args...)   do {} while (0)
  71 #endif /* RTL8169_DEBUG */
  72
  73 #define R8169_MSG_DEFAULT \
  74         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  75
  76 #define TX_SLOTS_AVAIL(tp) \
  77         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
  78
  79 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
  80 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
  81         (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
  82
  83 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  84    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  85 static const int multicast_filter_limit = 32;
  86
  87 #define MAX_READ_REQUEST_SHIFT  12
  88 #define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
  89 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  90
  91 #define R8169_REGS_SIZE         256
  92 #define R8169_NAPI_WEIGHT       64
  93 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  94 #define NUM_RX_DESC     256U    /* Number of Rx descriptor registers */
  95 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  96 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  97
  98 #define RTL8169_TX_TIMEOUT      (6*HZ)
  99 #define RTL8169_PHY_TIMEOUT     (10*HZ)
 100
 101 /* write/read MMIO register */
 102 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
 103 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
 104 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
 105 #define RTL_R8(reg)             readb (ioaddr + (reg))
 106 #define RTL_R16(reg)            readw (ioaddr + (reg))
 107 #define RTL_R32(reg)            readl (ioaddr + (reg))
 108
 109 enum mac_version {
 110         RTL_GIGA_MAC_VER_01 = 0,
 111         RTL_GIGA_MAC_VER_02,
 112         RTL_GIGA_MAC_VER_03,
 113         RTL_GIGA_MAC_VER_04,
 114         RTL_GIGA_MAC_VER_05,
 115         RTL_GIGA_MAC_VER_06,
 116         RTL_GIGA_MAC_VER_07,
 117         RTL_GIGA_MAC_VER_08,
 118         RTL_GIGA_MAC_VER_09,
 119         RTL_GIGA_MAC_VER_10,
 120         RTL_GIGA_MAC_VER_11,
 121         RTL_GIGA_MAC_VER_12,
 122         RTL_GIGA_MAC_VER_13,
 123         RTL_GIGA_MAC_VER_14,
 124         RTL_GIGA_MAC_VER_15,
 125         RTL_GIGA_MAC_VER_16,
 126         RTL_GIGA_MAC_VER_17,
 127         RTL_GIGA_MAC_VER_18,
 128         RTL_GIGA_MAC_VER_19,
 129         RTL_GIGA_MAC_VER_20,
 130         RTL_GIGA_MAC_VER_21,
 131         RTL_GIGA_MAC_VER_22,
 132         RTL_GIGA_MAC_VER_23,
 133         RTL_GIGA_MAC_VER_24,
 134         RTL_GIGA_MAC_VER_25,
 135         RTL_GIGA_MAC_VER_26,
 136         RTL_GIGA_MAC_VER_27,
 137         RTL_GIGA_MAC_VER_28,
 138         RTL_GIGA_MAC_VER_29,
 139         RTL_GIGA_MAC_VER_30,
 140         RTL_GIGA_MAC_VER_31,
 141         RTL_GIGA_MAC_VER_32,
 142         RTL_GIGA_MAC_VER_33,
 143         RTL_GIGA_MAC_VER_34,
 144         RTL_GIGA_MAC_VER_35,
 145         RTL_GIGA_MAC_VER_36,
 146         RTL_GIGA_MAC_VER_37,
 147         RTL_GIGA_MAC_VER_38,
 148         RTL_GIGA_MAC_VER_39,
 149         RTL_GIGA_MAC_VER_40,
 150         RTL_GIGA_MAC_VER_41,
 151         RTL_GIGA_MAC_VER_42,
 152         RTL_GIGA_MAC_VER_43,
 153         RTL_GIGA_MAC_VER_44,
 154         RTL_GIGA_MAC_VER_45,
 155         RTL_GIGA_MAC_VER_46,
 156         RTL_GIGA_MAC_VER_47,
 157         RTL_GIGA_MAC_VER_48,
 158         RTL_GIGA_MAC_NONE   = 0xff,
 159 };
 160
 161 enum rtl_tx_desc_version {
 162         RTL_TD_0        = 0,
 163         RTL_TD_1        = 1,
 164 };
 165
 166 #define JUMBO_1K        ETH_DATA_LEN
 167 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
 168 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
 169 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
 170 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
 171
 172 #define _R(NAME,TD,FW,SZ,B) {   \
 173         .name = NAME,           \
 174         .txd_version = TD,      \
 175         .fw_name = FW,          \
 176         .jumbo_max = SZ,        \
 177         .jumbo_tx_csum = B      \
 178 }
 179
 180 static const struct {
 181         const char *name;
 182         enum rtl_tx_desc_version txd_version;
 183         const char *fw_name;
 184         u16 jumbo_max;
 185         bool jumbo_tx_csum;
 186 } rtl_chip_infos[] = {
 187         /* PCI devices. */
 188         [RTL_GIGA_MAC_VER_01] =
 189                 _R("RTL8169",           RTL_TD_0, NULL, JUMBO_7K, true),
 190         [RTL_GIGA_MAC_VER_02] =
 191                 _R("RTL8169s",          RTL_TD_0, NULL, JUMBO_7K, true),
 192         [RTL_GIGA_MAC_VER_03] =
 193                 _R("RTL8110s",          RTL_TD_0, NULL, JUMBO_7K, true),
 194         [RTL_GIGA_MAC_VER_04] =
 195                 _R("RTL8169sb/8110sb",  RTL_TD_0, NULL, JUMBO_7K, true),
 196         [RTL_GIGA_MAC_VER_05] =
 197                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 198         [RTL_GIGA_MAC_VER_06] =
 199                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 200         /* PCI-E devices. */
 201         [RTL_GIGA_MAC_VER_07] =
 202                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 203         [RTL_GIGA_MAC_VER_08] =
 204                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 205         [RTL_GIGA_MAC_VER_09] =
 206                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 207         [RTL_GIGA_MAC_VER_10] =
 208                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 209         [RTL_GIGA_MAC_VER_11] =
 210                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 211         [RTL_GIGA_MAC_VER_12] =
 212                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 213         [RTL_GIGA_MAC_VER_13] =
 214                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 215         [RTL_GIGA_MAC_VER_14] =
 216                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 217         [RTL_GIGA_MAC_VER_15] =
 218                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 219         [RTL_GIGA_MAC_VER_16] =
 220                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 221         [RTL_GIGA_MAC_VER_17] =
 222                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 223         [RTL_GIGA_MAC_VER_18] =
 224                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 225         [RTL_GIGA_MAC_VER_19] =
 226                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 227         [RTL_GIGA_MAC_VER_20] =
 228                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 229         [RTL_GIGA_MAC_VER_21] =
 230                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 231         [RTL_GIGA_MAC_VER_22] =
 232                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 233         [RTL_GIGA_MAC_VER_23] =
 234                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 235         [RTL_GIGA_MAC_VER_24] =
 236                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 237         [RTL_GIGA_MAC_VER_25] =
 238                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_1,
 239                                                         JUMBO_9K, false),
 240         [RTL_GIGA_MAC_VER_26] =
 241                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_2,
 242                                                         JUMBO_9K, false),
 243         [RTL_GIGA_MAC_VER_27] =
 244                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 245         [RTL_GIGA_MAC_VER_28] =
 246                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 247         [RTL_GIGA_MAC_VER_29] =
 248                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 249                                                         JUMBO_1K, true),
 250         [RTL_GIGA_MAC_VER_30] =
 251                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 252                                                         JUMBO_1K, true),
 253         [RTL_GIGA_MAC_VER_31] =
 254                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 255         [RTL_GIGA_MAC_VER_32] =
 256                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_1,
 257                                                         JUMBO_9K, false),
 258         [RTL_GIGA_MAC_VER_33] =
 259                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_2,
 260                                                         JUMBO_9K, false),
 261         [RTL_GIGA_MAC_VER_34] =
 262                 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
 263                                                         JUMBO_9K, false),
 264         [RTL_GIGA_MAC_VER_35] =
 265                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_1,
 266                                                         JUMBO_9K, false),
 267         [RTL_GIGA_MAC_VER_36] =
 268                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_2,
 269                                                         JUMBO_9K, false),
 270         [RTL_GIGA_MAC_VER_37] =
 271                 _R("RTL8402",           RTL_TD_1, FIRMWARE_8402_1,
 272                                                         JUMBO_1K, true),
 273         [RTL_GIGA_MAC_VER_38] =
 274                 _R("RTL8411",           RTL_TD_1, FIRMWARE_8411_1,
 275                                                         JUMBO_9K, false),
 276         [RTL_GIGA_MAC_VER_39] =
 277                 _R("RTL8106e",          RTL_TD_1, FIRMWARE_8106E_1,
 278                                                         JUMBO_1K, true),
 279         [RTL_GIGA_MAC_VER_40] =
 280                 _R("RTL8168g/8111g",    RTL_TD_1, FIRMWARE_8168G_2,
 281                                                         JUMBO_9K, false),
 282         [RTL_GIGA_MAC_VER_41] =
 283                 _R("RTL8168g/8111g",    RTL_TD_1, NULL, JUMBO_9K, false),
 284         [RTL_GIGA_MAC_VER_42] =
 285                 _R("RTL8168g/8111g",    RTL_TD_1, FIRMWARE_8168G_3,
 286                                                         JUMBO_9K, false),
 287         [RTL_GIGA_MAC_VER_43] =
 288                 _R("RTL8106e",          RTL_TD_1, FIRMWARE_8106E_2,
 289                                                         JUMBO_1K, true),
 290         [RTL_GIGA_MAC_VER_44] =
 291                 _R("RTL8411",           RTL_TD_1, FIRMWARE_8411_2,
 292                                                         JUMBO_9K, false),
 293         [RTL_GIGA_MAC_VER_45] =
 294                 _R("RTL8168h/8111h",    RTL_TD_1, FIRMWARE_8168H_1,
 295                                                         JUMBO_9K, false),
 296         [RTL_GIGA_MAC_VER_46] =
 297                 _R("RTL8168h/8111h",    RTL_TD_1, FIRMWARE_8168H_2,
 298                                                         JUMBO_9K, false),
 299         [RTL_GIGA_MAC_VER_47] =
 300                 _R("RTL8107e",          RTL_TD_1, FIRMWARE_8107E_1,
 301                                                         JUMBO_1K, false),
 302         [RTL_GIGA_MAC_VER_48] =
 303                 _R("RTL8107e",          RTL_TD_1, FIRMWARE_8107E_2,
 304                                                         JUMBO_1K, false),
 305 };
 306 #undef _R
 307
 308 enum cfg_version {
 309         RTL_CFG_0 = 0x00,
 310         RTL_CFG_1,
 311         RTL_CFG_2
 312 };
 313
 314 static const struct pci_device_id rtl8169_pci_tbl[] = {
 315         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 316         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 317         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 318         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 319         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 320         { PCI_VENDOR_ID_DLINK,                  0x4300,
 321                 PCI_VENDOR_ID_DLINK, 0x4b10,             0, 0, RTL_CFG_1 },
 322         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 323         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4302), 0, 0, RTL_CFG_0 },
 324         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 325         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 326         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 327                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 328         { 0x0001,                               0x8168,
 329                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 330         {0,},
 331 };
 332
 333 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 334
 335 static int rx_buf_sz = 16383;
 336 static int use_dac;
 337 static struct {
 338         u32 msg_enable;
 339 } debug = { -1 };
 340
 341 enum rtl_registers {
 342         MAC0            = 0,    /* Ethernet hardware address. */
 343         MAC4            = 4,
 344         MAR0            = 8,    /* Multicast filter. */
 345         CounterAddrLow          = 0x10,
 346         CounterAddrHigh         = 0x14,
 347         TxDescStartAddrLow      = 0x20,
 348         TxDescStartAddrHigh     = 0x24,
 349         TxHDescStartAddrLow     = 0x28,
 350         TxHDescStartAddrHigh    = 0x2c,
 351         FLASH           = 0x30,
 352         ERSR            = 0x36,
 353         ChipCmd         = 0x37,
 354         TxPoll          = 0x38,
 355         IntrMask        = 0x3c,
 356         IntrStatus      = 0x3e,
 357
 358         TxConfig        = 0x40,
 359 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 360 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 361
 362         RxConfig        = 0x44,
 363 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 364 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 365 #define RXCFG_FIFO_SHIFT                13
 366                                         /* No threshold before first PCI xfer */
 367 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 368 #define RX_EARLY_OFF                    (1 << 11)
 369 #define RXCFG_DMA_SHIFT                 8
 370                                         /* Unlimited maximum PCI burst. */
 371 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 372
 373         RxMissed        = 0x4c,
 374         Cfg9346         = 0x50,
 375         Config0         = 0x51,
 376         Config1         = 0x52,
 377         Config2         = 0x53,
 378 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 379
 380         Config3         = 0x54,
 381         Config4         = 0x55,
 382         Config5         = 0x56,
 383         MultiIntr       = 0x5c,
 384         PHYAR           = 0x60,
 385         PHYstatus       = 0x6c,
 386         RxMaxSize       = 0xda,
 387         CPlusCmd        = 0xe0,
 388         IntrMitigate    = 0xe2,
 389         RxDescAddrLow   = 0xe4,
 390         RxDescAddrHigh  = 0xe8,
 391         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 392
 393 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 394
 395         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 396
 397 #define TxPacketMax     (8064 >> 7)
 398 #define EarlySize       0x27
 399
 400         FuncEvent       = 0xf0,
 401         FuncEventMask   = 0xf4,
 402         FuncPresetState = 0xf8,
 403         FuncForceEvent  = 0xfc,
 404 };
 405
 406 enum rtl8110_registers {
 407         TBICSR                  = 0x64,
 408         TBI_ANAR                = 0x68,
 409         TBI_LPAR                = 0x6a,
 410 };
 411
 412 enum rtl8168_8101_registers {
 413         CSIDR                   = 0x64,
 414         CSIAR                   = 0x68,
 415 #define CSIAR_FLAG                      0x80000000
 416 #define CSIAR_WRITE_CMD                 0x80000000
 417 #define CSIAR_BYTE_ENABLE               0x0f
 418 #define CSIAR_BYTE_ENABLE_SHIFT         12
 419 #define CSIAR_ADDR_MASK                 0x0fff
 420 #define CSIAR_FUNC_CARD                 0x00000000
 421 #define CSIAR_FUNC_SDIO                 0x00010000
 422 #define CSIAR_FUNC_NIC                  0x00020000
 423 #define CSIAR_FUNC_NIC2                 0x00010000
 424         PMCH                    = 0x6f,
 425         EPHYAR                  = 0x80,
 426 #define EPHYAR_FLAG                     0x80000000
 427 #define EPHYAR_WRITE_CMD                0x80000000
 428 #define EPHYAR_REG_MASK                 0x1f
 429 #define EPHYAR_REG_SHIFT                16
 430 #define EPHYAR_DATA_MASK                0xffff
 431         DLLPR                   = 0xd0,
 432 #define PFM_EN                          (1 << 6)
 433 #define TX_10M_PS_EN                    (1 << 7)
 434         DBG_REG                 = 0xd1,
 435 #define FIX_NAK_1                       (1 << 4)
 436 #define FIX_NAK_2                       (1 << 3)
 437         TWSI                    = 0xd2,
 438         MCU                     = 0xd3,
 439 #define NOW_IS_OOB                      (1 << 7)
 440 #define TX_EMPTY                        (1 << 5)
 441 #define RX_EMPTY                        (1 << 4)
 442 #define RXTX_EMPTY                      (TX_EMPTY | RX_EMPTY)
 443 #define EN_NDP                          (1 << 3)
 444 #define EN_OOB_RESET                    (1 << 2)
 445 #define LINK_LIST_RDY                   (1 << 1)
 446         EFUSEAR                 = 0xdc,
 447 #define EFUSEAR_FLAG                    0x80000000
 448 #define EFUSEAR_WRITE_CMD               0x80000000
 449 #define EFUSEAR_READ_CMD                0x00000000
 450 #define EFUSEAR_REG_MASK                0x03ff
 451 #define EFUSEAR_REG_SHIFT               8
 452 #define EFUSEAR_DATA_MASK               0xff
 453         MISC_1                  = 0xf2,
 454 #define PFM_D3COLD_EN                   (1 << 6)
 455 };
 456
 457 enum rtl8168_registers {
 458         LED_FREQ                = 0x1a,
 459         EEE_LED                 = 0x1b,
 460         ERIDR                   = 0x70,
 461         ERIAR                   = 0x74,
 462 #define ERIAR_FLAG                      0x80000000
 463 #define ERIAR_WRITE_CMD                 0x80000000
 464 #define ERIAR_READ_CMD                  0x00000000
 465 #define ERIAR_ADDR_BYTE_ALIGN           4
 466 #define ERIAR_TYPE_SHIFT                16
 467 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 468 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 469 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 470 #define ERIAR_MASK_SHIFT                12
 471 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 472 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 473 #define ERIAR_MASK_0100                 (0x4 << ERIAR_MASK_SHIFT)
 474 #define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
 475 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 476         EPHY_RXER_NUM           = 0x7c,
 477         OCPDR                   = 0xb0, /* OCP GPHY access */
 478 #define OCPDR_WRITE_CMD                 0x80000000
 479 #define OCPDR_READ_CMD                  0x00000000
 480 #define OCPDR_REG_MASK                  0x7f
 481 #define OCPDR_GPHY_REG_SHIFT            16
 482 #define OCPDR_DATA_MASK                 0xffff
 483         OCPAR                   = 0xb4,
 484 #define OCPAR_FLAG                      0x80000000
 485 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 486 #define OCPAR_GPHY_READ_CMD             0x0000f060
 487         GPHY_OCP                = 0xb8,
 488         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 489         MISC                    = 0xf0, /* 8168e only. */
 490 #define TXPLA_RST                       (1 << 29)
 491 #define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
 492 #define PWM_EN                          (1 << 22)
 493 #define RXDV_GATED_EN                   (1 << 19)
 494 #define EARLY_TALLY_EN                  (1 << 16)
 495 };
 496
 497 enum rtl_register_content {
 498         /* InterruptStatusBits */
 499         SYSErr          = 0x8000,
 500         PCSTimeout      = 0x4000,
 501         SWInt           = 0x0100,
 502         TxDescUnavail   = 0x0080,
 503         RxFIFOOver      = 0x0040,
 504         LinkChg         = 0x0020,
 505         RxOverflow      = 0x0010,
 506         TxErr           = 0x0008,
 507         TxOK            = 0x0004,
 508         RxErr           = 0x0002,
 509         RxOK            = 0x0001,
 510
 511         /* RxStatusDesc */
 512         RxBOVF  = (1 << 24),
 513         RxFOVF  = (1 << 23),
 514         RxRWT   = (1 << 22),
 515         RxRES   = (1 << 21),
 516         RxRUNT  = (1 << 20),
 517         RxCRC   = (1 << 19),
 518
 519         /* ChipCmdBits */
 520         StopReq         = 0x80,
 521         CmdReset        = 0x10,
 522         CmdRxEnb        = 0x08,
 523         CmdTxEnb        = 0x04,
 524         RxBufEmpty      = 0x01,
 525
 526         /* TXPoll register p.5 */
 527         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 528         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 529         FSWInt          = 0x01,         /* Forced software interrupt */
 530
 531         /* Cfg9346Bits */
 532         Cfg9346_Lock    = 0x00,
 533         Cfg9346_Unlock  = 0xc0,
 534
 535         /* rx_mode_bits */
 536         AcceptErr       = 0x20,
 537         AcceptRunt      = 0x10,
 538         AcceptBroadcast = 0x08,
 539         AcceptMulticast = 0x04,
 540         AcceptMyPhys    = 0x02,
 541         AcceptAllPhys   = 0x01,
 542 #define RX_CONFIG_ACCEPT_MASK           0x3f
 543
 544         /* TxConfigBits */
 545         TxInterFrameGapShift = 24,
 546         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 547
 548         /* Config1 register p.24 */
 549         LEDS1           = (1 << 7),
 550         LEDS0           = (1 << 6),
 551         Speed_down      = (1 << 4),
 552         MEMMAP          = (1 << 3),
 553         IOMAP           = (1 << 2),
 554         VPD             = (1 << 1),
 555         PMEnable        = (1 << 0),     /* Power Management Enable */
 556
 557         /* Config2 register p. 25 */
 558         ClkReqEn        = (1 << 7),     /* Clock Request Enable */
 559         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 560         PCI_Clock_66MHz = 0x01,
 561         PCI_Clock_33MHz = 0x00,
 562
 563         /* Config3 register p.25 */
 564         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 565         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 566         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 567         Rdy_to_L23      = (1 << 1),     /* L23 Enable */
 568         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 569
 570         /* Config4 register */
 571         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 572
 573         /* Config5 register p.27 */
 574         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 575         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 576         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 577         Spi_en          = (1 << 3),
 578         LanWake         = (1 << 1),     /* LanWake enable/disable */
 579         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 580         ASPM_en         = (1 << 0),     /* ASPM enable */
 581
 582         /* TBICSR p.28 */
 583         TBIReset        = 0x80000000,
 584         TBILoopback     = 0x40000000,
 585         TBINwEnable     = 0x20000000,
 586         TBINwRestart    = 0x10000000,
 587         TBILinkOk       = 0x02000000,
 588         TBINwComplete   = 0x01000000,
 589
 590         /* CPlusCmd p.31 */
 591         EnableBist      = (1 << 15),    // 8168 8101
 592         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 593         Normal_mode     = (1 << 13),    // unused
 594         Force_half_dup  = (1 << 12),    // 8168 8101
 595         Force_rxflow_en = (1 << 11),    // 8168 8101
 596         Force_txflow_en = (1 << 10),    // 8168 8101
 597         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 598         ASF             = (1 << 8),     // 8168 8101
 599         PktCntrDisable  = (1 << 7),     // 8168 8101
 600         Mac_dbgo_sel    = 0x001c,       // 8168
 601         RxVlan          = (1 << 6),
 602         RxChkSum        = (1 << 5),
 603         PCIDAC          = (1 << 4),
 604         PCIMulRW        = (1 << 3),
 605         INTT_0          = 0x0000,       // 8168
 606         INTT_1          = 0x0001,       // 8168
 607         INTT_2          = 0x0002,       // 8168
 608         INTT_3          = 0x0003,       // 8168
 609
 610         /* rtl8169_PHYstatus */
 611         TBI_Enable      = 0x80,
 612         TxFlowCtrl      = 0x40,
 613         RxFlowCtrl      = 0x20,
 614         _1000bpsF       = 0x10,
 615         _100bps         = 0x08,
 616         _10bps          = 0x04,
 617         LinkStatus      = 0x02,
 618         FullDup         = 0x01,
 619
 620         /* _TBICSRBit */
 621         TBILinkOK       = 0x02000000,
 622
 623         /* DumpCounterCommand */
 624         CounterDump     = 0x8,
 625
 626         /* magic enable v2 */
 627         MagicPacket_v2  = (1 << 16),    /* Wake up when receives a Magic Packet */
 628 };
 629
 630 enum rtl_desc_bit {
 631         /* First doubleword. */
 632         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 633         RingEnd         = (1 << 30), /* End of descriptor ring */
 634         FirstFrag       = (1 << 29), /* First segment of a packet */
 635         LastFrag        = (1 << 28), /* Final segment of a packet */
 636 };
 637
 638 /* Generic case. */
 639 enum rtl_tx_desc_bit {
 640         /* First doubleword. */
 641         TD_LSO          = (1 << 27),            /* Large Send Offload */
 642 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 643
 644         /* Second doubleword. */
 645         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 646 };
 647
 648 /* 8169, 8168b and 810x except 8102e. */
 649 enum rtl_tx_desc_bit_0 {
 650         /* First doubleword. */
 651 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 652         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 653         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 654         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 655 };
 656
 657 /* 8102e, 8168c and beyond. */
 658 enum rtl_tx_desc_bit_1 {
 659         /* First doubleword. */
 660         TD1_GTSENV4     = (1 << 26),            /* Giant Send for IPv4 */
 661         TD1_GTSENV6     = (1 << 25),            /* Giant Send for IPv6 */
 662 #define GTTCPHO_SHIFT                   18
 663 #define GTTCPHO_MAX                     0x7fU
 664
 665         /* Second doubleword. */
 666 #define TCPHO_SHIFT                     18
 667 #define TCPHO_MAX                       0x3ffU
 668 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 669         TD1_IPv6_CS     = (1 << 28),            /* Calculate IPv6 checksum */
 670         TD1_IPv4_CS     = (1 << 29),            /* Calculate IPv4 checksum */
 671         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 672         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 673 };
 674
 675 enum rtl_rx_desc_bit {
 676         /* Rx private */
 677         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 678         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
 679
 680 #define RxProtoUDP      (PID1)
 681 #define RxProtoTCP      (PID0)
 682 #define RxProtoIP       (PID1 | PID0)
 683 #define RxProtoMask     RxProtoIP
 684
 685         IPFail          = (1 << 16), /* IP checksum failed */
 686         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 687         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 688         RxVlanTag       = (1 << 16), /* VLAN tag available */
 689 };
 690
 691 #define RsvdMask        0x3fffc000
 692
 693 struct TxDesc {
 694         __le32 opts1;
 695         __le32 opts2;
 696         __le64 addr;
 697 };
 698
 699 struct RxDesc {
 700         __le32 opts1;
 701         __le32 opts2;
 702         __le64 addr;
 703 };
 704
 705 struct ring_info {
 706         struct sk_buff  *skb;
 707         u32             len;
 708         u8              __pad[sizeof(void *) - sizeof(u32)];
 709 };
 710
 711 enum features {
 712         RTL_FEATURE_WOL         = (1 << 0),
 713         RTL_FEATURE_MSI         = (1 << 1),
 714         RTL_FEATURE_GMII        = (1 << 2),
 715 };
 716
 717 struct rtl8169_counters {
 718         __le64  tx_packets;
 719         __le64  rx_packets;
 720         __le64  tx_errors;
 721         __le32  rx_errors;
 722         __le16  rx_missed;
 723         __le16  align_errors;
 724         __le32  tx_one_collision;
 725         __le32  tx_multi_collision;
 726         __le64  rx_unicast;
 727         __le64  rx_broadcast;
 728         __le32  rx_multicast;
 729         __le16  tx_aborted;
 730         __le16  tx_underun;
 731 };
 732
 733 enum rtl_flag {
 734         RTL_FLAG_TASK_ENABLED,
 735         RTL_FLAG_TASK_SLOW_PENDING,
 736         RTL_FLAG_TASK_RESET_PENDING,
 737         RTL_FLAG_TASK_PHY_PENDING,
 738         RTL_FLAG_MAX
 739 };
 740
 741 struct rtl8169_stats {
 742         u64                     packets;
 743         u64                     bytes;
 744         struct u64_stats_sync   syncp;
 745 };
 746
 747 struct rtl8169_private {
 748         void __iomem *mmio_addr;        /* memory map physical address */
 749         struct pci_dev *pci_dev;
 750         struct net_device *dev;
 751         struct napi_struct napi;
 752         u32 msg_enable;
 753         u16 txd_version;
 754         u16 mac_version;
 755         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 756         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 757         u32 dirty_tx;
 758         struct rtl8169_stats rx_stats;
 759         struct rtl8169_stats tx_stats;
 760         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 761         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 762         dma_addr_t TxPhyAddr;
 763         dma_addr_t RxPhyAddr;
 764         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 765         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 766         struct timer_list timer;
 767         u16 cp_cmd;
 768
 769         u16 event_slow;
 770
 771         struct mdio_ops {
 772                 void (*write)(struct rtl8169_private *, int, int);
 773                 int (*read)(struct rtl8169_private *, int);
 774         } mdio_ops;
 775
 776         struct pll_power_ops {
 777                 void (*down)(struct rtl8169_private *);
 778                 void (*up)(struct rtl8169_private *);
 779         } pll_power_ops;
 780
 781         struct jumbo_ops {
 782                 void (*enable)(struct rtl8169_private *);
 783                 void (*disable)(struct rtl8169_private *);
 784         } jumbo_ops;
 785
 786         struct csi_ops {
 787                 void (*write)(struct rtl8169_private *, int, int);
 788                 u32 (*read)(struct rtl8169_private *, int);
 789         } csi_ops;
 790
 791         int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
 792         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
 793         void (*phy_reset_enable)(struct rtl8169_private *tp);
 794         void (*hw_start)(struct net_device *);
 795         unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
 796         unsigned int (*link_ok)(void __iomem *);
 797         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
 798         bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
 799
 800         struct {
 801                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 802                 struct mutex mutex;
 803                 struct work_struct work;
 804         } wk;
 805
 806         unsigned features;
 807
 808         struct mii_if_info mii;
 809         struct rtl8169_counters counters;
 810         u32 saved_wolopts;
 811         u32 opts1_mask;
 812
 813         struct rtl_fw {
 814                 const struct firmware *fw;
 815
 816 #define RTL_VER_SIZE            32
 817
 818                 char version[RTL_VER_SIZE];
 819
 820                 struct rtl_fw_phy_action {
 821                         __le32 *code;
 822                         size_t size;
 823                 } phy_action;
 824         } *rtl_fw;
 825 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN)
 826
 827         u32 ocp_base;
 828 };
 829
 830 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 831 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 832 module_param(use_dac, int, 0);
 833 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 834 module_param_named(debug, debug.msg_enable, int, 0);
 835 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 836 MODULE_LICENSE("GPL");
 837 MODULE_VERSION(RTL8169_VERSION);
 838 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 839 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 840 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 841 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 842 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 843 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 844 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 845 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 846 MODULE_FIRMWARE(FIRMWARE_8402_1);
 847 MODULE_FIRMWARE(FIRMWARE_8411_1);
 848 MODULE_FIRMWARE(FIRMWARE_8411_2);
 849 MODULE_FIRMWARE(FIRMWARE_8106E_1);
 850 MODULE_FIRMWARE(FIRMWARE_8106E_2);
 851 MODULE_FIRMWARE(FIRMWARE_8168G_2);
 852 MODULE_FIRMWARE(FIRMWARE_8168G_3);
 853 MODULE_FIRMWARE(FIRMWARE_8168H_1);
 854 MODULE_FIRMWARE(FIRMWARE_8168H_2);
 855 MODULE_FIRMWARE(FIRMWARE_8107E_1);
 856 MODULE_FIRMWARE(FIRMWARE_8107E_2);
 857
 858 static void rtl_lock_work(struct rtl8169_private *tp)
 859 {
 860         mutex_lock(&tp->wk.mutex);
 861 }
 862
 863 static void rtl_unlock_work(struct rtl8169_private *tp)
 864 {
 865         mutex_unlock(&tp->wk.mutex);
 866 }
 867
 868 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
 869 {
 870         pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
 871                                            PCI_EXP_DEVCTL_READRQ, force);
 872 }
 873
 874 struct rtl_cond {
 875         bool (*check)(struct rtl8169_private *);
 876         const char *msg;
 877 };
 878
 879 static void rtl_udelay(unsigned int d)
 880 {
 881         udelay(d);
 882 }
 883
 884 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
 885                           void (*delay)(unsigned int), unsigned int d, int n,
 886                           bool high)
 887 {
 888         int i;
 889
 890         for (i = 0; i < n; i++) {
 891                 delay(d);
 892                 if (c->check(tp) == high)
 893                         return true;
 894         }
 895         netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
 896                   c->msg, !high, n, d);
 897         return false;
 898 }
 899
 900 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
 901                                       const struct rtl_cond *c,
 902                                       unsigned int d, int n)
 903 {
 904         return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
 905 }
 906
 907 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
 908                                      const struct rtl_cond *c,
 909                                      unsigned int d, int n)
 910 {
 911         return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
 912 }
 913
 914 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
 915                                       const struct rtl_cond *c,
 916                                       unsigned int d, int n)
 917 {
 918         return rtl_loop_wait(tp, c, msleep, d, n, true);
 919 }
 920
 921 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
 922                                      const struct rtl_cond *c,
 923                                      unsigned int d, int n)
 924 {
 925         return rtl_loop_wait(tp, c, msleep, d, n, false);
 926 }
 927
 928 #define DECLARE_RTL_COND(name)                          \
 929 static bool name ## _check(struct rtl8169_private *);   \
 930                                                         \
 931 static const struct rtl_cond name = {                   \
 932         .check  = name ## _check,                       \
 933         .msg    = #name                                 \
 934 };                                                      \
 935                                                         \
 936 static bool name ## _check(struct rtl8169_private *tp)
 937
 938 DECLARE_RTL_COND(rtl_ocpar_cond)
 939 {
 940         void __iomem *ioaddr = tp->mmio_addr;
 941
 942         return RTL_R32(OCPAR) & OCPAR_FLAG;
 943 }
 944
 945 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
 946 {
 947         void __iomem *ioaddr = tp->mmio_addr;
 948
 949         RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 950
 951         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
 952                 RTL_R32(OCPDR) : ~0;
 953 }
 954
 955 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
 956 {
 957         void __iomem *ioaddr = tp->mmio_addr;
 958
 959         RTL_W32(OCPDR, data);
 960         RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 961
 962         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
 963 }
 964
 965 DECLARE_RTL_COND(rtl_eriar_cond)
 966 {
 967         void __iomem *ioaddr = tp->mmio_addr;
 968
 969         return RTL_R32(ERIAR) & ERIAR_FLAG;
 970 }
 971
 972 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
 973 {
 974         void __iomem *ioaddr = tp->mmio_addr;
 975
 976         RTL_W8(ERIDR, cmd);
 977         RTL_W32(ERIAR, 0x800010e8);
 978         msleep(2);
 979
 980         if (!rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 5))
 981                 return;
 982
 983         ocp_write(tp, 0x1, 0x30, 0x00000001);
 984 }
 985
 986 #define OOB_CMD_RESET           0x00
 987 #define OOB_CMD_DRIVER_START    0x05
 988 #define OOB_CMD_DRIVER_STOP     0x06
 989
 990 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
 991 {
 992         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
 993 }
 994
 995 DECLARE_RTL_COND(rtl_ocp_read_cond)
 996 {
 997         u16 reg;
 998
 999         reg = rtl8168_get_ocp_reg(tp);
1000
1001         return ocp_read(tp, 0x0f, reg) & 0x00000800;
1002 }
1003
1004 static void rtl8168_driver_start(struct rtl8169_private *tp)
1005 {
1006         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
1007
1008         rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
1009 }
1010
1011 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1012 {
1013         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1014
1015         rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
1016 }
1017
1018 static int r8168dp_check_dash(struct rtl8169_private *tp)
1019 {
1020         u16 reg = rtl8168_get_ocp_reg(tp);
1021
1022         return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
1023 }
1024
1025 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
1026 {
1027         if (reg & 0xffff0001) {
1028                 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
1029                 return true;
1030         }
1031         return false;
1032 }
1033
1034 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
1035 {
1036         void __iomem *ioaddr = tp->mmio_addr;
1037
1038         return RTL_R32(GPHY_OCP) & OCPAR_FLAG;
1039 }
1040
1041 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1042 {
1043         void __iomem *ioaddr = tp->mmio_addr;
1044
1045         if (rtl_ocp_reg_failure(tp, reg))
1046                 return;
1047
1048         RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
1049
1050         rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
1051 }
1052
1053 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
1054 {
1055         void __iomem *ioaddr = tp->mmio_addr;
1056
1057         if (rtl_ocp_reg_failure(tp, reg))
1058                 return 0;
1059
1060         RTL_W32(GPHY_OCP, reg << 15);
1061
1062         return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
1063                 (RTL_R32(GPHY_OCP) & 0xffff) : ~0;
1064 }
1065
1066 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1067 {
1068         void __iomem *ioaddr = tp->mmio_addr;
1069
1070         if (rtl_ocp_reg_failure(tp, reg))
1071                 return;
1072
1073         RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data);
1074 }
1075
1076 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1077 {
1078         void __iomem *ioaddr = tp->mmio_addr;
1079
1080         if (rtl_ocp_reg_failure(tp, reg))
1081                 return 0;
1082
1083         RTL_W32(OCPDR, reg << 15);
1084
1085         return RTL_R32(OCPDR);
1086 }
1087
1088 #define OCP_STD_PHY_BASE        0xa400
1089
1090 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1091 {
1092         if (reg == 0x1f) {
1093                 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1094                 return;
1095         }
1096
1097         if (tp->ocp_base != OCP_STD_PHY_BASE)
1098                 reg -= 0x10;
1099
1100         r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1101 }
1102
1103 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1104 {
1105         if (tp->ocp_base != OCP_STD_PHY_BASE)
1106                 reg -= 0x10;
1107
1108         return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1109 }
1110
1111 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
1112 {
1113         if (reg == 0x1f) {
1114                 tp->ocp_base = value << 4;
1115                 return;
1116         }
1117
1118         r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
1119 }
1120
1121 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
1122 {
1123         return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
1124 }
1125
1126 DECLARE_RTL_COND(rtl_phyar_cond)
1127 {
1128         void __iomem *ioaddr = tp->mmio_addr;
1129
1130         return RTL_R32(PHYAR) & 0x80000000;
1131 }
1132
1133 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1134 {
1135         void __iomem *ioaddr = tp->mmio_addr;
1136
1137         RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1138
1139         rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
1140         /*
1141          * According to hardware specs a 20us delay is required after write
1142          * complete indication, but before sending next command.
1143          */
1144         udelay(20);
1145 }
1146
1147 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1148 {
1149         void __iomem *ioaddr = tp->mmio_addr;
1150         int value;
1151
1152         RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16);
1153
1154         value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1155                 RTL_R32(PHYAR) & 0xffff : ~0;
1156
1157         /*
1158          * According to hardware specs a 20us delay is required after read
1159          * complete indication, but before sending next command.
1160          */
1161         udelay(20);
1162
1163         return value;
1164 }
1165
1166 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
1167 {
1168         void __iomem *ioaddr = tp->mmio_addr;
1169
1170         RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
1171         RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
1172         RTL_W32(EPHY_RXER_NUM, 0);
1173
1174         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
1175 }
1176
1177 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
1178 {
1179         r8168dp_1_mdio_access(tp, reg,
1180                               OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
1181 }
1182
1183 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
1184 {
1185         void __iomem *ioaddr = tp->mmio_addr;
1186
1187         r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
1188
1189         mdelay(1);
1190         RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
1191         RTL_W32(EPHY_RXER_NUM, 0);
1192
1193         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1194                 RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0;
1195 }
1196
1197 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
1198
1199 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
1200 {
1201         RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1202 }
1203
1204 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
1205 {
1206         RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1207 }
1208
1209 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1210 {
1211         void __iomem *ioaddr = tp->mmio_addr;
1212
1213         r8168dp_2_mdio_start(ioaddr);
1214
1215         r8169_mdio_write(tp, reg, value);
1216
1217         r8168dp_2_mdio_stop(ioaddr);
1218 }
1219
1220 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1221 {
1222         void __iomem *ioaddr = tp->mmio_addr;
1223         int value;
1224
1225         r8168dp_2_mdio_start(ioaddr);
1226
1227         value = r8169_mdio_read(tp, reg);
1228
1229         r8168dp_2_mdio_stop(ioaddr);
1230
1231         return value;
1232 }
1233
1234 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1235 {
1236         tp->mdio_ops.write(tp, location, val);
1237 }
1238
1239 static int rtl_readphy(struct rtl8169_private *tp, int location)
1240 {
1241         return tp->mdio_ops.read(tp, location);
1242 }
1243
1244 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1245 {
1246         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1247 }
1248
1249 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1250 {
1251         int val;
1252
1253         val = rtl_readphy(tp, reg_addr);
1254         rtl_writephy(tp, reg_addr, (val | p) & ~m);
1255 }
1256
1257 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1258                            int val)
1259 {
1260         struct rtl8169_private *tp = netdev_priv(dev);
1261
1262         rtl_writephy(tp, location, val);
1263 }
1264
1265 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1266 {
1267         struct rtl8169_private *tp = netdev_priv(dev);
1268
1269         return rtl_readphy(tp, location);
1270 }
1271
1272 DECLARE_RTL_COND(rtl_ephyar_cond)
1273 {
1274         void __iomem *ioaddr = tp->mmio_addr;
1275
1276         return RTL_R32(EPHYAR) & EPHYAR_FLAG;
1277 }
1278
1279 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1280 {
1281         void __iomem *ioaddr = tp->mmio_addr;
1282
1283         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1284                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1285
1286         rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1287
1288         udelay(10);
1289 }
1290
1291 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1292 {
1293         void __iomem *ioaddr = tp->mmio_addr;
1294
1295         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1296
1297         return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1298                 RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0;
1299 }
1300
1301 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1302                           u32 val, int type)
1303 {
1304         void __iomem *ioaddr = tp->mmio_addr;
1305
1306         BUG_ON((addr & 3) || (mask == 0));
1307         RTL_W32(ERIDR, val);
1308         RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1309
1310         rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1311 }
1312
1313 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1314 {
1315         void __iomem *ioaddr = tp->mmio_addr;
1316
1317         RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1318
1319         return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1320                 RTL_R32(ERIDR) : ~0;
1321 }
1322
1323 static void rtl_w1w0_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1324                          u32 m, int type)
1325 {
1326         u32 val;
1327
1328         val = rtl_eri_read(tp, addr, type);
1329         rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
1330 }
1331
1332 struct exgmac_reg {
1333         u16 addr;
1334         u16 mask;
1335         u32 val;
1336 };
1337
1338 static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
1339                                    const struct exgmac_reg *r, int len)
1340 {
1341         while (len-- > 0) {
1342                 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1343                 r++;
1344         }
1345 }
1346
1347 DECLARE_RTL_COND(rtl_efusear_cond)
1348 {
1349         void __iomem *ioaddr = tp->mmio_addr;
1350
1351         return RTL_R32(EFUSEAR) & EFUSEAR_FLAG;
1352 }
1353
1354 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1355 {
1356         void __iomem *ioaddr = tp->mmio_addr;
1357
1358         RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1359
1360         return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1361                 RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1362 }
1363
1364 static u16 rtl_get_events(struct rtl8169_private *tp)
1365 {
1366         void __iomem *ioaddr = tp->mmio_addr;
1367
1368         return RTL_R16(IntrStatus);
1369 }
1370
1371 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1372 {
1373         void __iomem *ioaddr = tp->mmio_addr;
1374
1375         RTL_W16(IntrStatus, bits);
1376         mmiowb();
1377 }
1378
1379 static void rtl_irq_disable(struct rtl8169_private *tp)
1380 {
1381         void __iomem *ioaddr = tp->mmio_addr;
1382
1383         RTL_W16(IntrMask, 0);
1384         mmiowb();
1385 }
1386
1387 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1388 {
1389         void __iomem *ioaddr = tp->mmio_addr;
1390
1391         RTL_W16(IntrMask, bits);
1392 }
1393
1394 #define RTL_EVENT_NAPI_RX       (RxOK | RxErr)
1395 #define RTL_EVENT_NAPI_TX       (TxOK | TxErr)
1396 #define RTL_EVENT_NAPI          (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1397
1398 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1399 {
1400         rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1401 }
1402
1403 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1404 {
1405         void __iomem *ioaddr = tp->mmio_addr;
1406
1407         rtl_irq_disable(tp);
1408         rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1409         RTL_R8(ChipCmd);
1410 }
1411
1412 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1413 {
1414         void __iomem *ioaddr = tp->mmio_addr;
1415
1416         return RTL_R32(TBICSR) & TBIReset;
1417 }
1418
1419 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1420 {
1421         return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1422 }
1423
1424 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1425 {
1426         return RTL_R32(TBICSR) & TBILinkOk;
1427 }
1428
1429 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1430 {
1431         return RTL_R8(PHYstatus) & LinkStatus;
1432 }
1433
1434 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1435 {
1436         void __iomem *ioaddr = tp->mmio_addr;
1437
1438         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1439 }
1440
1441 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1442 {
1443         unsigned int val;
1444
1445         val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1446         rtl_writephy(tp, MII_BMCR, val & 0xffff);
1447 }
1448
1449 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1450 {
1451         void __iomem *ioaddr = tp->mmio_addr;
1452         struct net_device *dev = tp->dev;
1453
1454         if (!netif_running(dev))
1455                 return;
1456
1457         if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1458             tp->mac_version == RTL_GIGA_MAC_VER_38) {
1459                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1460                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1461                                       ERIAR_EXGMAC);
1462                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1463                                       ERIAR_EXGMAC);
1464                 } else if (RTL_R8(PHYstatus) & _100bps) {
1465                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1466                                       ERIAR_EXGMAC);
1467                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1468                                       ERIAR_EXGMAC);
1469                 } else {
1470                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1471                                       ERIAR_EXGMAC);
1472                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1473                                       ERIAR_EXGMAC);
1474                 }
1475                 /* Reset packet filter */
1476                 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1477                              ERIAR_EXGMAC);
1478                 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1479                              ERIAR_EXGMAC);
1480         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1481                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1482                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1483                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1484                                       ERIAR_EXGMAC);
1485                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1486                                       ERIAR_EXGMAC);
1487                 } else {
1488                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1489                                       ERIAR_EXGMAC);
1490                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1491                                       ERIAR_EXGMAC);
1492                 }
1493         } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1494                 if (RTL_R8(PHYstatus) & _10bps) {
1495                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1496                                       ERIAR_EXGMAC);
1497                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1498                                       ERIAR_EXGMAC);
1499                 } else {
1500                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1501                                       ERIAR_EXGMAC);
1502                 }
1503         }
1504 }
1505
1506 static void __rtl8169_check_link_status(struct net_device *dev,
1507                                         struct rtl8169_private *tp,
1508                                         void __iomem *ioaddr, bool pm)
1509 {
1510         if (tp->link_ok(ioaddr)) {
1511                 rtl_link_chg_patch(tp);
1512                 /* This is to cancel a scheduled suspend if there's one. */
1513                 if (pm)
1514                         pm_request_resume(&tp->pci_dev->dev);
1515                 netif_carrier_on(dev);
1516                 if (net_ratelimit())
1517                         netif_info(tp, ifup, dev, "link up\n");
1518         } else {
1519                 netif_carrier_off(dev);
1520                 netif_info(tp, ifdown, dev, "link down\n");
1521                 if (pm)
1522                         pm_schedule_suspend(&tp->pci_dev->dev, 5000);
1523         }
1524 }
1525
1526 static void rtl8169_check_link_status(struct net_device *dev,
1527                                       struct rtl8169_private *tp,
1528                                       void __iomem *ioaddr)
1529 {
1530         __rtl8169_check_link_status(dev, tp, ioaddr, false);
1531 }
1532
1533 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1534
1535 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1536 {
1537         void __iomem *ioaddr = tp->mmio_addr;
1538         u8 options;
1539         u32 wolopts = 0;
1540
1541         options = RTL_R8(Config1);
1542         if (!(options & PMEnable))
1543                 return 0;
1544
1545         options = RTL_R8(Config3);
1546         if (options & LinkUp)
1547                 wolopts |= WAKE_PHY;
1548         switch (tp->mac_version) {
1549         case RTL_GIGA_MAC_VER_45:
1550         case RTL_GIGA_MAC_VER_46:
1551                 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
1552                         wolopts |= WAKE_MAGIC;
1553                 break;
1554         default:
1555                 if (options & MagicPacket)
1556                         wolopts |= WAKE_MAGIC;
1557                 break;
1558         }
1559
1560         options = RTL_R8(Config5);
1561         if (options & UWF)
1562                 wolopts |= WAKE_UCAST;
1563         if (options & BWF)
1564                 wolopts |= WAKE_BCAST;
1565         if (options & MWF)
1566                 wolopts |= WAKE_MCAST;
1567
1568         return wolopts;
1569 }
1570
1571 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1572 {
1573         struct rtl8169_private *tp = netdev_priv(dev);
1574
1575         rtl_lock_work(tp);
1576
1577         wol->supported = WAKE_ANY;
1578         wol->wolopts = __rtl8169_get_wol(tp);
1579
1580         rtl_unlock_work(tp);
1581 }
1582
1583 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1584 {
1585         void __iomem *ioaddr = tp->mmio_addr;
1586         unsigned int i, tmp;
1587         static const struct {
1588                 u32 opt;
1589                 u16 reg;
1590                 u8  mask;
1591         } cfg[] = {
1592                 { WAKE_PHY,   Config3, LinkUp },
1593                 { WAKE_UCAST, Config5, UWF },
1594                 { WAKE_BCAST, Config5, BWF },
1595                 { WAKE_MCAST, Config5, MWF },
1596                 { WAKE_ANY,   Config5, LanWake },
1597                 { WAKE_MAGIC, Config3, MagicPacket }
1598         };
1599         u8 options;
1600
1601         RTL_W8(Cfg9346, Cfg9346_Unlock);
1602
1603         switch (tp->mac_version) {
1604         case RTL_GIGA_MAC_VER_45:
1605         case RTL_GIGA_MAC_VER_46:
1606                 tmp = ARRAY_SIZE(cfg) - 1;
1607                 if (wolopts & WAKE_MAGIC)
1608                         rtl_w1w0_eri(tp,
1609                                      0x0dc,
1610                                      ERIAR_MASK_0100,
1611                                      MagicPacket_v2,
1612                                      0x0000,
1613                                      ERIAR_EXGMAC);
1614                 else
1615                         rtl_w1w0_eri(tp,
1616                                      0x0dc,
1617                                      ERIAR_MASK_0100,
1618                                      0x0000,
1619                                      MagicPacket_v2,
1620                                      ERIAR_EXGMAC);
1621                 break;
1622         default:
1623                 tmp = ARRAY_SIZE(cfg);
1624                 break;
1625         }
1626
1627         for (i = 0; i < tmp; i++) {
1628                 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1629                 if (wolopts & cfg[i].opt)
1630                         options |= cfg[i].mask;
1631                 RTL_W8(cfg[i].reg, options);
1632         }
1633
1634         switch (tp->mac_version) {
1635         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1636                 options = RTL_R8(Config1) & ~PMEnable;
1637                 if (wolopts)
1638                         options |= PMEnable;
1639                 RTL_W8(Config1, options);
1640                 break;
1641         default:
1642                 options = RTL_R8(Config2) & ~PME_SIGNAL;
1643                 if (wolopts)
1644                         options |= PME_SIGNAL;
1645                 RTL_W8(Config2, options);
1646                 break;
1647         }
1648
1649         RTL_W8(Cfg9346, Cfg9346_Lock);
1650 }
1651
1652 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1653 {
1654         struct rtl8169_private *tp = netdev_priv(dev);
1655
1656         rtl_lock_work(tp);
1657
1658         if (wol->wolopts)
1659                 tp->features |= RTL_FEATURE_WOL;
1660         else
1661                 tp->features &= ~RTL_FEATURE_WOL;
1662         __rtl8169_set_wol(tp, wol->wolopts);
1663
1664         rtl_unlock_work(tp);
1665
1666         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1667
1668         return 0;
1669 }
1670
1671 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1672 {
1673         return rtl_chip_infos[tp->mac_version].fw_name;
1674 }
1675
1676 static void rtl8169_get_drvinfo(struct net_device *dev,
1677                                 struct ethtool_drvinfo *info)
1678 {
1679         struct rtl8169_private *tp = netdev_priv(dev);
1680         struct rtl_fw *rtl_fw = tp->rtl_fw;
1681
1682         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1683         strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1684         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1685         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1686         if (!IS_ERR_OR_NULL(rtl_fw))
1687                 strlcpy(info->fw_version, rtl_fw->version,
1688                         sizeof(info->fw_version));
1689 }
1690
1691 static int rtl8169_get_regs_len(struct net_device *dev)
1692 {
1693         return R8169_REGS_SIZE;
1694 }
1695
1696 static int rtl8169_set_speed_tbi(struct net_device *dev,
1697                                  u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1698 {
1699         struct rtl8169_private *tp = netdev_priv(dev);
1700         void __iomem *ioaddr = tp->mmio_addr;
1701         int ret = 0;
1702         u32 reg;
1703
1704         reg = RTL_R32(TBICSR);
1705         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1706             (duplex == DUPLEX_FULL)) {
1707                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1708         } else if (autoneg == AUTONEG_ENABLE)
1709                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1710         else {
1711                 netif_warn(tp, link, dev,
1712                            "incorrect speed setting refused in TBI mode\n");
1713                 ret = -EOPNOTSUPP;
1714         }
1715
1716         return ret;
1717 }
1718
1719 static int rtl8169_set_speed_xmii(struct net_device *dev,
1720                                   u8 autoneg, u16 speed, u8 duplex, u32 adv)
1721 {
1722         struct rtl8169_private *tp = netdev_priv(dev);
1723         int giga_ctrl, bmcr;
1724         int rc = -EINVAL;
1725
1726         rtl_writephy(tp, 0x1f, 0x0000);
1727
1728         if (autoneg == AUTONEG_ENABLE) {
1729                 int auto_nego;
1730
1731                 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1732                 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1733                                 ADVERTISE_100HALF | ADVERTISE_100FULL);
1734
1735                 if (adv & ADVERTISED_10baseT_Half)
1736                         auto_nego |= ADVERTISE_10HALF;
1737                 if (adv & ADVERTISED_10baseT_Full)
1738                         auto_nego |= ADVERTISE_10FULL;
1739                 if (adv & ADVERTISED_100baseT_Half)
1740                         auto_nego |= ADVERTISE_100HALF;
1741                 if (adv & ADVERTISED_100baseT_Full)
1742                         auto_nego |= ADVERTISE_100FULL;
1743
1744                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1745
1746                 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1747                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1748
1749                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1750                 if (tp->mii.supports_gmii) {
1751                         if (adv & ADVERTISED_1000baseT_Half)
1752                                 giga_ctrl |= ADVERTISE_1000HALF;
1753                         if (adv & ADVERTISED_1000baseT_Full)
1754                                 giga_ctrl |= ADVERTISE_1000FULL;
1755                 } else if (adv & (ADVERTISED_1000baseT_Half |
1756                                   ADVERTISED_1000baseT_Full)) {
1757                         netif_info(tp, link, dev,
1758                                    "PHY does not support 1000Mbps\n");
1759                         goto out;
1760                 }
1761
1762                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1763
1764                 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1765                 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1766         } else {
1767                 giga_ctrl = 0;
1768
1769                 if (speed == SPEED_10)
1770                         bmcr = 0;
1771                 else if (speed == SPEED_100)
1772                         bmcr = BMCR_SPEED100;
1773                 else
1774                         goto out;
1775
1776                 if (duplex == DUPLEX_FULL)
1777                         bmcr |= BMCR_FULLDPLX;
1778         }
1779
1780         rtl_writephy(tp, MII_BMCR, bmcr);
1781
1782         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1783             tp->mac_version == RTL_GIGA_MAC_VER_03) {
1784                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1785                         rtl_writephy(tp, 0x17, 0x2138);
1786                         rtl_writephy(tp, 0x0e, 0x0260);
1787                 } else {
1788                         rtl_writephy(tp, 0x17, 0x2108);
1789                         rtl_writephy(tp, 0x0e, 0x0000);
1790                 }
1791         }
1792
1793         rc = 0;
1794 out:
1795         return rc;
1796 }
1797
1798 static int rtl8169_set_speed(struct net_device *dev,
1799                              u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1800 {
1801         struct rtl8169_private *tp = netdev_priv(dev);
1802         int ret;
1803
1804         ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1805         if (ret < 0)
1806                 goto out;
1807
1808         if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1809             (advertising & ADVERTISED_1000baseT_Full)) {
1810                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1811         }
1812 out:
1813         return ret;
1814 }
1815
1816 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1817 {
1818         struct rtl8169_private *tp = netdev_priv(dev);
1819         int ret;
1820
1821         del_timer_sync(&tp->timer);
1822
1823         rtl_lock_work(tp);
1824         ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1825                                 cmd->duplex, cmd->advertising);
1826         rtl_unlock_work(tp);
1827
1828         return ret;
1829 }
1830
1831 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1832         netdev_features_t features)
1833 {
1834         struct rtl8169_private *tp = netdev_priv(dev);
1835
1836         if (dev->mtu > TD_MSS_MAX)
1837                 features &= ~NETIF_F_ALL_TSO;
1838
1839         if (dev->mtu > JUMBO_1K &&
1840             !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1841                 features &= ~NETIF_F_IP_CSUM;
1842
1843         return features;
1844 }
1845
1846 static void __rtl8169_set_features(struct net_device *dev,
1847                                    netdev_features_t features)
1848 {
1849         struct rtl8169_private *tp = netdev_priv(dev);
1850         void __iomem *ioaddr = tp->mmio_addr;
1851         u32 rx_config;
1852
1853         rx_config = RTL_R32(RxConfig);
1854         if (features & NETIF_F_RXALL)
1855                 rx_config |= (AcceptErr | AcceptRunt);
1856         else
1857                 rx_config &= ~(AcceptErr | AcceptRunt);
1858
1859         RTL_W32(RxConfig, rx_config);
1860
1861         if (features & NETIF_F_RXCSUM)
1862                 tp->cp_cmd |= RxChkSum;
1863         else
1864                 tp->cp_cmd &= ~RxChkSum;
1865
1866         if (features & NETIF_F_HW_VLAN_CTAG_RX)
1867                 tp->cp_cmd |= RxVlan;
1868         else
1869                 tp->cp_cmd &= ~RxVlan;
1870
1871         tp->cp_cmd |= RTL_R16(CPlusCmd) & ~(RxVlan | RxChkSum);
1872
1873         RTL_W16(CPlusCmd, tp->cp_cmd);
1874         RTL_R16(CPlusCmd);
1875 }
1876
1877 static int rtl8169_set_features(struct net_device *dev,
1878                                 netdev_features_t features)
1879 {
1880         struct rtl8169_private *tp = netdev_priv(dev);
1881
1882         features &= NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX;
1883
1884         rtl_lock_work(tp);
1885         if (features ^ dev->features)
1886                 __rtl8169_set_features(dev, features);
1887         rtl_unlock_work(tp);
1888
1889         return 0;
1890 }
1891
1892
1893 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1894 {
1895         return (vlan_tx_tag_present(skb)) ?
1896                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1897 }
1898
1899 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1900 {
1901         u32 opts2 = le32_to_cpu(desc->opts2);
1902
1903         if (opts2 & RxVlanTag)
1904                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1905 }
1906
1907 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1908 {
1909         struct rtl8169_private *tp = netdev_priv(dev);
1910         void __iomem *ioaddr = tp->mmio_addr;
1911         u32 status;
1912
1913         cmd->supported =
1914                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1915         cmd->port = PORT_FIBRE;
1916         cmd->transceiver = XCVR_INTERNAL;
1917
1918         status = RTL_R32(TBICSR);
1919         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
1920         cmd->autoneg = !!(status & TBINwEnable);
1921
1922         ethtool_cmd_speed_set(cmd, SPEED_1000);
1923         cmd->duplex = DUPLEX_FULL; /* Always set */
1924
1925         return 0;
1926 }
1927
1928 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1929 {
1930         struct rtl8169_private *tp = netdev_priv(dev);
1931
1932         return mii_ethtool_gset(&tp->mii, cmd);
1933 }
1934
1935 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1936 {
1937         struct rtl8169_private *tp = netdev_priv(dev);
1938         int rc;
1939
1940         rtl_lock_work(tp);
1941         rc = tp->get_settings(dev, cmd);
1942         rtl_unlock_work(tp);
1943
1944         return rc;
1945 }
1946
1947 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1948                              void *p)
1949 {
1950         struct rtl8169_private *tp = netdev_priv(dev);
1951         u32 __iomem *data = tp->mmio_addr;
1952         u32 *dw = p;
1953         int i;
1954
1955         rtl_lock_work(tp);
1956         for (i = 0; i < R8169_REGS_SIZE; i += 4)
1957                 memcpy_fromio(dw++, data++, 4);
1958         rtl_unlock_work(tp);
1959 }
1960
1961 static u32 rtl8169_get_msglevel(struct net_device *dev)
1962 {
1963         struct rtl8169_private *tp = netdev_priv(dev);
1964
1965         return tp->msg_enable;
1966 }
1967
1968 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1969 {
1970         struct rtl8169_private *tp = netdev_priv(dev);
1971
1972         tp->msg_enable = value;
1973 }
1974
1975 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1976         "tx_packets",
1977         "rx_packets",
1978         "tx_errors",
1979         "rx_errors",
1980         "rx_missed",
1981         "align_errors",
1982         "tx_single_collisions",
1983         "tx_multi_collisions",
1984         "unicast",
1985         "broadcast",
1986         "multicast",
1987         "tx_aborted",
1988         "tx_underrun",
1989 };
1990
1991 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1992 {
1993         switch (sset) {
1994         case ETH_SS_STATS:
1995                 return ARRAY_SIZE(rtl8169_gstrings);
1996         default:
1997                 return -EOPNOTSUPP;
1998         }
1999 }
2000
2001 DECLARE_RTL_COND(rtl_counters_cond)
2002 {
2003         void __iomem *ioaddr = tp->mmio_addr;
2004
2005         return RTL_R32(CounterAddrLow) & CounterDump;
2006 }
2007
2008 static void rtl8169_update_counters(struct net_device *dev)
2009 {
2010         struct rtl8169_private *tp = netdev_priv(dev);
2011         void __iomem *ioaddr = tp->mmio_addr;
2012         struct device *d = &tp->pci_dev->dev;
2013         struct rtl8169_counters *counters;
2014         dma_addr_t paddr;
2015         u32 cmd;
2016
2017         /*
2018          * Some chips are unable to dump tally counters when the receiver
2019          * is disabled.
2020          */
2021         if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
2022                 return;
2023
2024         counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
2025         if (!counters)
2026                 return;
2027
2028         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
2029         cmd = (u64)paddr & DMA_BIT_MASK(32);
2030         RTL_W32(CounterAddrLow, cmd);
2031         RTL_W32(CounterAddrLow, cmd | CounterDump);
2032
2033         if (rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000))
2034                 memcpy(&tp->counters, counters, sizeof(*counters));
2035
2036         RTL_W32(CounterAddrLow, 0);
2037         RTL_W32(CounterAddrHigh, 0);
2038
2039         dma_free_coherent(d, sizeof(*counters), counters, paddr);
2040 }
2041
2042 static void rtl8169_get_ethtool_stats(struct net_device *dev,
2043                                       struct ethtool_stats *stats, u64 *data)
2044 {
2045         struct rtl8169_private *tp = netdev_priv(dev);
2046
2047         ASSERT_RTNL();
2048
2049         rtl8169_update_counters(dev);
2050
2051         data[0] = le64_to_cpu(tp->counters.tx_packets);
2052         data[1] = le64_to_cpu(tp->counters.rx_packets);
2053         data[2] = le64_to_cpu(tp->counters.tx_errors);
2054         data[3] = le32_to_cpu(tp->counters.rx_errors);
2055         data[4] = le16_to_cpu(tp->counters.rx_missed);
2056         data[5] = le16_to_cpu(tp->counters.align_errors);
2057         data[6] = le32_to_cpu(tp->counters.tx_one_collision);
2058         data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
2059         data[8] = le64_to_cpu(tp->counters.rx_unicast);
2060         data[9] = le64_to_cpu(tp->counters.rx_broadcast);
2061         data[10] = le32_to_cpu(tp->counters.rx_multicast);
2062         data[11] = le16_to_cpu(tp->counters.tx_aborted);
2063         data[12] = le16_to_cpu(tp->counters.tx_underun);
2064 }
2065
2066 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2067 {
2068         switch(stringset) {
2069         case ETH_SS_STATS:
2070                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
2071                 break;
2072         }
2073 }
2074
2075 static const struct ethtool_ops rtl8169_ethtool_ops = {
2076         .get_drvinfo            = rtl8169_get_drvinfo,
2077         .get_regs_len           = rtl8169_get_regs_len,
2078         .get_link               = ethtool_op_get_link,
2079         .get_settings           = rtl8169_get_settings,
2080         .set_settings           = rtl8169_set_settings,
2081         .get_msglevel           = rtl8169_get_msglevel,
2082         .set_msglevel           = rtl8169_set_msglevel,
2083         .get_regs               = rtl8169_get_regs,
2084         .get_wol                = rtl8169_get_wol,
2085         .set_wol                = rtl8169_set_wol,
2086         .get_strings            = rtl8169_get_strings,
2087         .get_sset_count         = rtl8169_get_sset_count,
2088         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
2089         .get_ts_info            = ethtool_op_get_ts_info,
2090 };
2091
2092 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
2093                                     struct net_device *dev, u8 default_version)
2094 {
2095         void __iomem *ioaddr = tp->mmio_addr;
2096         /*
2097          * The driver currently handles the 8168Bf and the 8168Be identically
2098          * but they can be identified more specifically through the test below
2099          * if needed:
2100          *
2101          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2102          *
2103          * Same thing for the 8101Eb and the 8101Ec:
2104          *
2105          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2106          */
2107         static const struct rtl_mac_info {
2108                 u32 mask;
2109                 u32 val;
2110                 int mac_version;
2111         } mac_info[] = {
2112                 /* 8168H family. */
2113                 { 0x7cf00000, 0x54100000,       RTL_GIGA_MAC_VER_46 },
2114                 { 0x7cf00000, 0x54000000,       RTL_GIGA_MAC_VER_45 },
2115
2116                 /* 8168G family. */
2117                 { 0x7cf00000, 0x5c800000,       RTL_GIGA_MAC_VER_44 },
2118                 { 0x7cf00000, 0x50900000,       RTL_GIGA_MAC_VER_42 },
2119                 { 0x7cf00000, 0x4c100000,       RTL_GIGA_MAC_VER_41 },
2120                 { 0x7cf00000, 0x4c000000,       RTL_GIGA_MAC_VER_40 },
2121
2122                 /* 8168F family. */
2123                 { 0x7c800000, 0x48800000,       RTL_GIGA_MAC_VER_38 },
2124                 { 0x7cf00000, 0x48100000,       RTL_GIGA_MAC_VER_36 },
2125                 { 0x7cf00000, 0x48000000,       RTL_GIGA_MAC_VER_35 },
2126
2127                 /* 8168E family. */
2128                 { 0x7c800000, 0x2c800000,       RTL_GIGA_MAC_VER_34 },
2129                 { 0x7cf00000, 0x2c200000,       RTL_GIGA_MAC_VER_33 },
2130                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
2131                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
2132
2133                 /* 8168D family. */
2134                 { 0x7cf00000, 0x28300000,       RTL_GIGA_MAC_VER_26 },
2135                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
2136                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
2137
2138                 /* 8168DP family. */
2139                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
2140                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
2141                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
2142
2143                 /* 8168C family. */
2144                 { 0x7cf00000, 0x3cb00000,       RTL_GIGA_MAC_VER_24 },
2145                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
2146                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
2147                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
2148                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
2149                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
2150                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
2151                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
2152                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
2153
2154                 /* 8168B family. */
2155                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
2156                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
2157                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
2158                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
2159
2160                 /* 8101 family. */
2161                 { 0x7cf00000, 0x44900000,       RTL_GIGA_MAC_VER_39 },
2162                 { 0x7c800000, 0x44800000,       RTL_GIGA_MAC_VER_39 },
2163                 { 0x7c800000, 0x44000000,       RTL_GIGA_MAC_VER_37 },
2164                 { 0x7cf00000, 0x40b00000,       RTL_GIGA_MAC_VER_30 },
2165                 { 0x7cf00000, 0x40a00000,       RTL_GIGA_MAC_VER_30 },
2166                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
2167                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
2168                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
2169                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
2170                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
2171                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
2172                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
2173                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
2174                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
2175                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
2176                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
2177                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
2178                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
2179                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
2180                 /* FIXME: where did these entries come from ? -- FR */
2181                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
2182                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
2183
2184                 /* 8110 family. */
2185                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
2186                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
2187                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
2188                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
2189                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
2190                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
2191
2192                 /* Catch-all */
2193                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
2194         };
2195         const struct rtl_mac_info *p = mac_info;
2196         u32 reg;
2197
2198         reg = RTL_R32(TxConfig);
2199         while ((reg & p->mask) != p->val)
2200                 p++;
2201         tp->mac_version = p->mac_version;
2202
2203         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2204                 netif_notice(tp, probe, dev,
2205                              "unknown MAC, using family default\n");
2206                 tp->mac_version = default_version;
2207         } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2208                 tp->mac_version = tp->mii.supports_gmii ?
2209                                   RTL_GIGA_MAC_VER_42 :
2210                                   RTL_GIGA_MAC_VER_43;
2211         } else if (tp->mac_version == RTL_GIGA_MAC_VER_45) {
2212                 tp->mac_version = tp->mii.supports_gmii ?
2213                                   RTL_GIGA_MAC_VER_45 :
2214                                   RTL_GIGA_MAC_VER_47;
2215         } else if (tp->mac_version == RTL_GIGA_MAC_VER_46) {
2216                 tp->mac_version = tp->mii.supports_gmii ?
2217                                   RTL_GIGA_MAC_VER_46 :
2218                                   RTL_GIGA_MAC_VER_48;
2219         }
2220 }
2221
2222 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2223 {
2224         dprintk("mac_version = 0x%02x\n", tp->mac_version);
2225 }
2226
2227 struct phy_reg {
2228         u16 reg;
2229         u16 val;
2230 };
2231
2232 static void rtl_writephy_batch(struct rtl8169_private *tp,
2233                                const struct phy_reg *regs, int len)
2234 {
2235         while (len-- > 0) {
2236                 rtl_writephy(tp, regs->reg, regs->val);
2237                 regs++;
2238         }
2239 }
2240
2241 #define PHY_READ                0x00000000
2242 #define PHY_DATA_OR             0x10000000
2243 #define PHY_DATA_AND            0x20000000
2244 #define PHY_BJMPN               0x30000000
2245 #define PHY_MDIO_CHG            0x40000000
2246 #define PHY_CLEAR_READCOUNT     0x70000000
2247 #define PHY_WRITE               0x80000000
2248 #define PHY_READCOUNT_EQ_SKIP   0x90000000
2249 #define PHY_COMP_EQ_SKIPN       0xa0000000
2250 #define PHY_COMP_NEQ_SKIPN      0xb0000000
2251 #define PHY_WRITE_PREVIOUS      0xc0000000
2252 #define PHY_SKIPN               0xd0000000
2253 #define PHY_DELAY_MS            0xe0000000
2254
2255 struct fw_info {
2256         u32     magic;
2257         char    version[RTL_VER_SIZE];
2258         __le32  fw_start;
2259         __le32  fw_len;
2260         u8      chksum;
2261 } __packed;
2262
2263 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2264
2265 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2266 {
2267         const struct firmware *fw = rtl_fw->fw;
2268         struct fw_info *fw_info = (struct fw_info *)fw->data;
2269         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2270         char *version = rtl_fw->version;
2271         bool rc = false;
2272
2273         if (fw->size < FW_OPCODE_SIZE)
2274                 goto out;
2275
2276         if (!fw_info->magic) {
2277                 size_t i, size, start;
2278                 u8 checksum = 0;
2279
2280                 if (fw->size < sizeof(*fw_info))
2281                         goto out;
2282
2283                 for (i = 0; i < fw->size; i++)
2284                         checksum += fw->data[i];
2285                 if (checksum != 0)
2286                         goto out;
2287
2288                 start = le32_to_cpu(fw_info->fw_start);
2289                 if (start > fw->size)
2290                         goto out;
2291
2292                 size = le32_to_cpu(fw_info->fw_len);
2293                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2294                         goto out;
2295
2296                 memcpy(version, fw_info->version, RTL_VER_SIZE);
2297
2298                 pa->code = (__le32 *)(fw->data + start);
2299                 pa->size = size;
2300         } else {
2301                 if (fw->size % FW_OPCODE_SIZE)
2302                         goto out;
2303
2304                 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2305
2306                 pa->code = (__le32 *)fw->data;
2307                 pa->size = fw->size / FW_OPCODE_SIZE;
2308         }
2309         version[RTL_VER_SIZE - 1] = 0;
2310
2311         rc = true;
2312 out:
2313         return rc;
2314 }
2315
2316 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2317                            struct rtl_fw_phy_action *pa)
2318 {
2319         bool rc = false;
2320         size_t index;
2321
2322         for (index = 0; index < pa->size; index++) {
2323                 u32 action = le32_to_cpu(pa->code[index]);
2324                 u32 regno = (action & 0x0fff0000) >> 16;
2325
2326                 switch(action & 0xf0000000) {
2327                 case PHY_READ:
2328                 case PHY_DATA_OR:
2329                 case PHY_DATA_AND:
2330                 case PHY_MDIO_CHG:
2331                 case PHY_CLEAR_READCOUNT:
2332                 case PHY_WRITE:
2333                 case PHY_WRITE_PREVIOUS:
2334                 case PHY_DELAY_MS:
2335                         break;
2336
2337                 case PHY_BJMPN:
2338                         if (regno > index) {
2339                                 netif_err(tp, ifup, tp->dev,
2340                                           "Out of range of firmware\n");
2341                                 goto out;
2342                         }
2343                         break;
2344                 case PHY_READCOUNT_EQ_SKIP:
2345                         if (index + 2 >= pa->size) {
2346                                 netif_err(tp, ifup, tp->dev,
2347                                           "Out of range of firmware\n");
2348                                 goto out;
2349                         }
2350                         break;
2351                 case PHY_COMP_EQ_SKIPN:
2352                 case PHY_COMP_NEQ_SKIPN:
2353                 case PHY_SKIPN:
2354                         if (index + 1 + regno >= pa->size) {
2355                                 netif_err(tp, ifup, tp->dev,
2356                                           "Out of range of firmware\n");
2357                                 goto out;
2358                         }
2359                         break;
2360
2361                 default:
2362                         netif_err(tp, ifup, tp->dev,
2363                                   "Invalid action 0x%08x\n", action);
2364                         goto out;
2365                 }
2366         }
2367         rc = true;
2368 out:
2369         return rc;
2370 }
2371
2372 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2373 {
2374         struct net_device *dev = tp->dev;
2375         int rc = -EINVAL;
2376
2377         if (!rtl_fw_format_ok(tp, rtl_fw)) {
2378                 netif_err(tp, ifup, dev, "invalid firwmare\n");
2379                 goto out;
2380         }
2381
2382         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2383                 rc = 0;
2384 out:
2385         return rc;
2386 }
2387
2388 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2389 {
2390         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2391         struct mdio_ops org, *ops = &tp->mdio_ops;
2392         u32 predata, count;
2393         size_t index;
2394
2395         predata = count = 0;
2396         org.write = ops->write;
2397         org.read = ops->read;
2398
2399         for (index = 0; index < pa->size; ) {
2400                 u32 action = le32_to_cpu(pa->code[index]);
2401                 u32 data = action & 0x0000ffff;
2402                 u32 regno = (action & 0x0fff0000) >> 16;
2403
2404                 if (!action)
2405                         break;
2406
2407                 switch(action & 0xf0000000) {
2408                 case PHY_READ:
2409                         predata = rtl_readphy(tp, regno);
2410                         count++;
2411                         index++;
2412                         break;
2413                 case PHY_DATA_OR:
2414                         predata |= data;
2415                         index++;
2416                         break;
2417                 case PHY_DATA_AND:
2418                         predata &= data;
2419                         index++;
2420                         break;
2421                 case PHY_BJMPN:
2422                         index -= regno;
2423                         break;
2424                 case PHY_MDIO_CHG:
2425                         if (data == 0) {
2426                                 ops->write = org.write;
2427                                 ops->read = org.read;
2428                         } else if (data == 1) {
2429                                 ops->write = mac_mcu_write;
2430                                 ops->read = mac_mcu_read;
2431                         }
2432
2433                         index++;
2434                         break;
2435                 case PHY_CLEAR_READCOUNT:
2436                         count = 0;
2437                         index++;
2438                         break;
2439                 case PHY_WRITE:
2440                         rtl_writephy(tp, regno, data);
2441                         index++;
2442                         break;
2443                 case PHY_READCOUNT_EQ_SKIP:
2444                         index += (count == data) ? 2 : 1;
2445                         break;
2446                 case PHY_COMP_EQ_SKIPN:
2447                         if (predata == data)
2448                                 index += regno;
2449                         index++;
2450                         break;
2451                 case PHY_COMP_NEQ_SKIPN:
2452                         if (predata != data)
2453                                 index += regno;
2454                         index++;
2455                         break;
2456                 case PHY_WRITE_PREVIOUS:
2457                         rtl_writephy(tp, regno, predata);
2458                         index++;
2459                         break;
2460                 case PHY_SKIPN:
2461                         index += regno + 1;
2462                         break;
2463                 case PHY_DELAY_MS:
2464                         mdelay(data);
2465                         index++;
2466                         break;
2467
2468                 default:
2469                         BUG();
2470                 }
2471         }
2472
2473         ops->write = org.write;
2474         ops->read = org.read;
2475 }
2476
2477 static void rtl_release_firmware(struct rtl8169_private *tp)
2478 {
2479         if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2480                 release_firmware(tp->rtl_fw->fw);
2481                 kfree(tp->rtl_fw);
2482         }
2483         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2484 }
2485
2486 static void rtl_apply_firmware(struct rtl8169_private *tp)
2487 {
2488         struct rtl_fw *rtl_fw = tp->rtl_fw;
2489
2490         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2491         if (!IS_ERR_OR_NULL(rtl_fw))
2492                 rtl_phy_write_fw(tp, rtl_fw);
2493 }
2494
2495 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2496 {
2497         if (rtl_readphy(tp, reg) != val)
2498                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2499         else
2500                 rtl_apply_firmware(tp);
2501 }
2502
2503 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2504 {
2505         static const struct phy_reg phy_reg_init[] = {
2506                 { 0x1f, 0x0001 },
2507                 { 0x06, 0x006e },
2508                 { 0x08, 0x0708 },
2509                 { 0x15, 0x4000 },
2510                 { 0x18, 0x65c7 },
2511
2512                 { 0x1f, 0x0001 },
2513                 { 0x03, 0x00a1 },
2514                 { 0x02, 0x0008 },
2515                 { 0x01, 0x0120 },
2516                 { 0x00, 0x1000 },
2517                 { 0x04, 0x0800 },
2518                 { 0x04, 0x0000 },
2519
2520                 { 0x03, 0xff41 },
2521                 { 0x02, 0xdf60 },
2522                 { 0x01, 0x0140 },
2523                 { 0x00, 0x0077 },
2524                 { 0x04, 0x7800 },
2525                 { 0x04, 0x7000 },
2526
2527                 { 0x03, 0x802f },
2528                 { 0x02, 0x4f02 },
2529                 { 0x01, 0x0409 },
2530                 { 0x00, 0xf0f9 },
2531                 { 0x04, 0x9800 },
2532                 { 0x04, 0x9000 },
2533
2534                 { 0x03, 0xdf01 },
2535                 { 0x02, 0xdf20 },
2536                 { 0x01, 0xff95 },
2537                 { 0x00, 0xba00 },
2538                 { 0x04, 0xa800 },
2539                 { 0x04, 0xa000 },
2540
2541                 { 0x03, 0xff41 },
2542                 { 0x02, 0xdf20 },
2543                 { 0x01, 0x0140 },
2544                 { 0x00, 0x00bb },
2545                 { 0x04, 0xb800 },
2546                 { 0x04, 0xb000 },
2547
2548                 { 0x03, 0xdf41 },
2549                 { 0x02, 0xdc60 },
2550                 { 0x01, 0x6340 },
2551                 { 0x00, 0x007d },
2552                 { 0x04, 0xd800 },
2553                 { 0x04, 0xd000 },
2554
2555                 { 0x03, 0xdf01 },
2556                 { 0x02, 0xdf20 },
2557                 { 0x01, 0x100a },
2558                 { 0x00, 0xa0ff },
2559                 { 0x04, 0xf800 },
2560                 { 0x04, 0xf000 },
2561
2562                 { 0x1f, 0x0000 },
2563                 { 0x0b, 0x0000 },
2564                 { 0x00, 0x9200 }
2565         };
2566
2567         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2568 }
2569
2570 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2571 {
2572         static const struct phy_reg phy_reg_init[] = {
2573                 { 0x1f, 0x0002 },
2574                 { 0x01, 0x90d0 },
2575                 { 0x1f, 0x0000 }
2576         };
2577
2578         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2579 }
2580
2581 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2582 {
2583         struct pci_dev *pdev = tp->pci_dev;
2584
2585         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2586             (pdev->subsystem_device != 0xe000))
2587                 return;
2588
2589         rtl_writephy(tp, 0x1f, 0x0001);
2590         rtl_writephy(tp, 0x10, 0xf01b);
2591         rtl_writephy(tp, 0x1f, 0x0000);
2592 }
2593
2594 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2595 {
2596         static const struct phy_reg phy_reg_init[] = {
2597                 { 0x1f, 0x0001 },
2598                 { 0x04, 0x0000 },
2599                 { 0x03, 0x00a1 },
2600                 { 0x02, 0x0008 },
2601                 { 0x01, 0x0120 },
2602                 { 0x00, 0x1000 },
2603                 { 0x04, 0x0800 },
2604                 { 0x04, 0x9000 },
2605                 { 0x03, 0x802f },
2606                 { 0x02, 0x4f02 },
2607                 { 0x01, 0x0409 },
2608                 { 0x00, 0xf099 },
2609                 { 0x04, 0x9800 },
2610                 { 0x04, 0xa000 },
2611                 { 0x03, 0xdf01 },
2612                 { 0x02, 0xdf20 },
2613                 { 0x01, 0xff95 },
2614                 { 0x00, 0xba00 },
2615                 { 0x04, 0xa800 },
2616                 { 0x04, 0xf000 },
2617                 { 0x03, 0xdf01 },
2618                 { 0x02, 0xdf20 },
2619                 { 0x01, 0x101a },
2620                 { 0x00, 0xa0ff },
2621                 { 0x04, 0xf800 },
2622                 { 0x04, 0x0000 },
2623                 { 0x1f, 0x0000 },
2624
2625                 { 0x1f, 0x0001 },
2626                 { 0x10, 0xf41b },
2627                 { 0x14, 0xfb54 },
2628                 { 0x18, 0xf5c7 },
2629                 { 0x1f, 0x0000 },
2630
2631                 { 0x1f, 0x0001 },
2632                 { 0x17, 0x0cc0 },
2633                 { 0x1f, 0x0000 }
2634         };
2635
2636         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2637
2638         rtl8169scd_hw_phy_config_quirk(tp);
2639 }
2640
2641 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2642 {
2643         static const struct phy_reg phy_reg_init[] = {
2644                 { 0x1f, 0x0001 },
2645                 { 0x04, 0x0000 },
2646                 { 0x03, 0x00a1 },
2647                 { 0x02, 0x0008 },
2648                 { 0x01, 0x0120 },
2649                 { 0x00, 0x1000 },
2650                 { 0x04, 0x0800 },
2651                 { 0x04, 0x9000 },
2652                 { 0x03, 0x802f },
2653                 { 0x02, 0x4f02 },
2654                 { 0x01, 0x0409 },
2655                 { 0x00, 0xf099 },
2656                 { 0x04, 0x9800 },
2657                 { 0x04, 0xa000 },
2658                 { 0x03, 0xdf01 },
2659                 { 0x02, 0xdf20 },
2660                 { 0x01, 0xff95 },
2661                 { 0x00, 0xba00 },
2662                 { 0x04, 0xa800 },
2663                 { 0x04, 0xf000 },
2664                 { 0x03, 0xdf01 },
2665                 { 0x02, 0xdf20 },
2666                 { 0x01, 0x101a },
2667                 { 0x00, 0xa0ff },
2668                 { 0x04, 0xf800 },
2669                 { 0x04, 0x0000 },
2670                 { 0x1f, 0x0000 },
2671
2672                 { 0x1f, 0x0001 },
2673                 { 0x0b, 0x8480 },
2674                 { 0x1f, 0x0000 },
2675
2676                 { 0x1f, 0x0001 },
2677                 { 0x18, 0x67c7 },
2678                 { 0x04, 0x2000 },
2679                 { 0x03, 0x002f },
2680                 { 0x02, 0x4360 },
2681                 { 0x01, 0x0109 },
2682                 { 0x00, 0x3022 },
2683                 { 0x04, 0x2800 },
2684                 { 0x1f, 0x0000 },
2685
2686                 { 0x1f, 0x0001 },
2687                 { 0x17, 0x0cc0 },
2688                 { 0x1f, 0x0000 }
2689         };
2690
2691         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2692 }
2693
2694 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2695 {
2696         static const struct phy_reg phy_reg_init[] = {
2697                 { 0x10, 0xf41b },
2698                 { 0x1f, 0x0000 }
2699         };
2700
2701         rtl_writephy(tp, 0x1f, 0x0001);
2702         rtl_patchphy(tp, 0x16, 1 << 0);
2703
2704         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2705 }
2706
2707 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2708 {
2709         static const struct phy_reg phy_reg_init[] = {
2710                 { 0x1f, 0x0001 },
2711                 { 0x10, 0xf41b },
2712                 { 0x1f, 0x0000 }
2713         };
2714
2715         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2716 }
2717
2718 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2719 {
2720         static const struct phy_reg phy_reg_init[] = {
2721                 { 0x1f, 0x0000 },
2722                 { 0x1d, 0x0f00 },
2723                 { 0x1f, 0x0002 },
2724                 { 0x0c, 0x1ec8 },
2725                 { 0x1f, 0x0000 }
2726         };
2727
2728         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2729 }
2730
2731 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2732 {
2733         static const struct phy_reg phy_reg_init[] = {
2734                 { 0x1f, 0x0001 },
2735                 { 0x1d, 0x3d98 },
2736                 { 0x1f, 0x0000 }
2737         };
2738
2739         rtl_writephy(tp, 0x1f, 0x0000);
2740         rtl_patchphy(tp, 0x14, 1 << 5);
2741         rtl_patchphy(tp, 0x0d, 1 << 5);
2742
2743         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2744 }
2745
2746 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2747 {
2748         static const struct phy_reg phy_reg_init[] = {
2749                 { 0x1f, 0x0001 },
2750                 { 0x12, 0x2300 },
2751                 { 0x1f, 0x0002 },
2752                 { 0x00, 0x88d4 },
2753                 { 0x01, 0x82b1 },
2754                 { 0x03, 0x7002 },
2755                 { 0x08, 0x9e30 },
2756                 { 0x09, 0x01f0 },
2757                 { 0x0a, 0x5500 },
2758                 { 0x0c, 0x00c8 },
2759                 { 0x1f, 0x0003 },
2760                 { 0x12, 0xc096 },
2761                 { 0x16, 0x000a },
2762                 { 0x1f, 0x0000 },
2763                 { 0x1f, 0x0000 },
2764                 { 0x09, 0x2000 },
2765                 { 0x09, 0x0000 }
2766         };
2767
2768         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2769
2770         rtl_patchphy(tp, 0x14, 1 << 5);
2771         rtl_patchphy(tp, 0x0d, 1 << 5);
2772         rtl_writephy(tp, 0x1f, 0x0000);
2773 }
2774
2775 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2776 {
2777         static const struct phy_reg phy_reg_init[] = {
2778                 { 0x1f, 0x0001 },
2779                 { 0x12, 0x2300 },
2780                 { 0x03, 0x802f },
2781                 { 0x02, 0x4f02 },
2782                 { 0x01, 0x0409 },
2783                 { 0x00, 0xf099 },
2784                 { 0x04, 0x9800 },
2785                 { 0x04, 0x9000 },
2786                 { 0x1d, 0x3d98 },
2787                 { 0x1f, 0x0002 },
2788                 { 0x0c, 0x7eb8 },
2789                 { 0x06, 0x0761 },
2790                 { 0x1f, 0x0003 },
2791                 { 0x16, 0x0f0a },
2792                 { 0x1f, 0x0000 }
2793         };
2794
2795         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2796
2797         rtl_patchphy(tp, 0x16, 1 << 0);
2798         rtl_patchphy(tp, 0x14, 1 << 5);
2799         rtl_patchphy(tp, 0x0d, 1 << 5);
2800         rtl_writephy(tp, 0x1f, 0x0000);
2801 }
2802
2803 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2804 {
2805         static const struct phy_reg phy_reg_init[] = {
2806                 { 0x1f, 0x0001 },
2807                 { 0x12, 0x2300 },
2808                 { 0x1d, 0x3d98 },
2809                 { 0x1f, 0x0002 },
2810                 { 0x0c, 0x7eb8 },
2811                 { 0x06, 0x5461 },
2812                 { 0x1f, 0x0003 },
2813                 { 0x16, 0x0f0a },
2814                 { 0x1f, 0x0000 }
2815         };
2816
2817         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2818
2819         rtl_patchphy(tp, 0x16, 1 << 0);
2820         rtl_patchphy(tp, 0x14, 1 << 5);
2821         rtl_patchphy(tp, 0x0d, 1 << 5);
2822         rtl_writephy(tp, 0x1f, 0x0000);
2823 }
2824
2825 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2826 {
2827         rtl8168c_3_hw_phy_config(tp);
2828 }
2829
2830 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2831 {
2832         static const struct phy_reg phy_reg_init_0[] = {
2833                 /* Channel Estimation */
2834                 { 0x1f, 0x0001 },
2835                 { 0x06, 0x4064 },
2836                 { 0x07, 0x2863 },
2837                 { 0x08, 0x059c },
2838                 { 0x09, 0x26b4 },
2839                 { 0x0a, 0x6a19 },
2840                 { 0x0b, 0xdcc8 },
2841                 { 0x10, 0xf06d },
2842                 { 0x14, 0x7f68 },
2843                 { 0x18, 0x7fd9 },
2844                 { 0x1c, 0xf0ff },
2845                 { 0x1d, 0x3d9c },
2846                 { 0x1f, 0x0003 },
2847                 { 0x12, 0xf49f },
2848                 { 0x13, 0x070b },
2849                 { 0x1a, 0x05ad },
2850                 { 0x14, 0x94c0 },
2851
2852                 /*
2853                  * Tx Error Issue
2854                  * Enhance line driver power
2855                  */
2856                 { 0x1f, 0x0002 },
2857                 { 0x06, 0x5561 },
2858                 { 0x1f, 0x0005 },
2859                 { 0x05, 0x8332 },
2860                 { 0x06, 0x5561 },
2861
2862                 /*
2863                  * Can not link to 1Gbps with bad cable
2864                  * Decrease SNR threshold form 21.07dB to 19.04dB
2865                  */
2866                 { 0x1f, 0x0001 },
2867                 { 0x17, 0x0cc0 },
2868
2869                 { 0x1f, 0x0000 },
2870                 { 0x0d, 0xf880 }
2871         };
2872
2873         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2874
2875         /*
2876          * Rx Error Issue
2877          * Fine Tune Switching regulator parameter
2878          */
2879         rtl_writephy(tp, 0x1f, 0x0002);
2880         rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2881         rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2882
2883         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2884                 static const struct phy_reg phy_reg_init[] = {
2885                         { 0x1f, 0x0002 },
2886                         { 0x05, 0x669a },
2887                         { 0x1f, 0x0005 },
2888                         { 0x05, 0x8330 },
2889                         { 0x06, 0x669a },
2890                         { 0x1f, 0x0002 }
2891                 };
2892                 int val;
2893
2894                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2895
2896                 val = rtl_readphy(tp, 0x0d);
2897
2898                 if ((val & 0x00ff) != 0x006c) {
2899                         static const u32 set[] = {
2900                                 0x0065, 0x0066, 0x0067, 0x0068,
2901                                 0x0069, 0x006a, 0x006b, 0x006c
2902                         };
2903                         int i;
2904
2905                         rtl_writephy(tp, 0x1f, 0x0002);
2906
2907                         val &= 0xff00;
2908                         for (i = 0; i < ARRAY_SIZE(set); i++)
2909                                 rtl_writephy(tp, 0x0d, val | set[i]);
2910                 }
2911         } else {
2912                 static const struct phy_reg phy_reg_init[] = {
2913                         { 0x1f, 0x0002 },
2914                         { 0x05, 0x6662 },
2915                         { 0x1f, 0x0005 },
2916                         { 0x05, 0x8330 },
2917                         { 0x06, 0x6662 }
2918                 };
2919
2920                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2921         }
2922
2923         /* RSET couple improve */
2924         rtl_writephy(tp, 0x1f, 0x0002);
2925         rtl_patchphy(tp, 0x0d, 0x0300);
2926         rtl_patchphy(tp, 0x0f, 0x0010);
2927
2928         /* Fine tune PLL performance */
2929         rtl_writephy(tp, 0x1f, 0x0002);
2930         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2931         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2932
2933         rtl_writephy(tp, 0x1f, 0x0005);
2934         rtl_writephy(tp, 0x05, 0x001b);
2935
2936         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2937
2938         rtl_writephy(tp, 0x1f, 0x0000);
2939 }
2940
2941 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2942 {
2943         static const struct phy_reg phy_reg_init_0[] = {
2944                 /* Channel Estimation */
2945                 { 0x1f, 0x0001 },
2946                 { 0x06, 0x4064 },
2947                 { 0x07, 0x2863 },
2948                 { 0x08, 0x059c },
2949                 { 0x09, 0x26b4 },
2950                 { 0x0a, 0x6a19 },
2951                 { 0x0b, 0xdcc8 },
2952                 { 0x10, 0xf06d },
2953                 { 0x14, 0x7f68 },
2954                 { 0x18, 0x7fd9 },
2955                 { 0x1c, 0xf0ff },
2956                 { 0x1d, 0x3d9c },
2957                 { 0x1f, 0x0003 },
2958                 { 0x12, 0xf49f },
2959                 { 0x13, 0x070b },
2960                 { 0x1a, 0x05ad },
2961                 { 0x14, 0x94c0 },
2962
2963                 /*
2964                  * Tx Error Issue
2965                  * Enhance line driver power
2966                  */
2967                 { 0x1f, 0x0002 },
2968                 { 0x06, 0x5561 },
2969                 { 0x1f, 0x0005 },
2970                 { 0x05, 0x8332 },
2971                 { 0x06, 0x5561 },
2972
2973                 /*
2974                  * Can not link to 1Gbps with bad cable
2975                  * Decrease SNR threshold form 21.07dB to 19.04dB
2976                  */
2977                 { 0x1f, 0x0001 },
2978                 { 0x17, 0x0cc0 },
2979
2980                 { 0x1f, 0x0000 },
2981                 { 0x0d, 0xf880 }
2982         };
2983
2984         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2985
2986         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2987                 static const struct phy_reg phy_reg_init[] = {
2988                         { 0x1f, 0x0002 },
2989                         { 0x05, 0x669a },
2990                         { 0x1f, 0x0005 },
2991                         { 0x05, 0x8330 },
2992                         { 0x06, 0x669a },
2993
2994                         { 0x1f, 0x0002 }
2995                 };
2996                 int val;
2997
2998                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2999
3000                 val = rtl_readphy(tp, 0x0d);
3001                 if ((val & 0x00ff) != 0x006c) {
3002                         static const u32 set[] = {
3003                                 0x0065, 0x0066, 0x0067, 0x0068,
3004                                 0x0069, 0x006a, 0x006b, 0x006c
3005                         };
3006                         int i;
3007
3008                         rtl_writephy(tp, 0x1f, 0x0002);
3009
3010                         val &= 0xff00;
3011                         for (i = 0; i < ARRAY_SIZE(set); i++)
3012                                 rtl_writephy(tp, 0x0d, val | set[i]);
3013                 }
3014         } else {
3015                 static const struct phy_reg phy_reg_init[] = {
3016                         { 0x1f, 0x0002 },
3017                         { 0x05, 0x2642 },
3018                         { 0x1f, 0x0005 },
3019                         { 0x05, 0x8330 },
3020                         { 0x06, 0x2642 }
3021                 };
3022
3023                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3024         }
3025
3026         /* Fine tune PLL performance */
3027         rtl_writephy(tp, 0x1f, 0x0002);
3028         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
3029         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
3030
3031         /* Switching regulator Slew rate */
3032         rtl_writephy(tp, 0x1f, 0x0002);
3033         rtl_patchphy(tp, 0x0f, 0x0017);
3034
3035         rtl_writephy(tp, 0x1f, 0x0005);
3036         rtl_writephy(tp, 0x05, 0x001b);
3037
3038         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
3039
3040         rtl_writephy(tp, 0x1f, 0x0000);
3041 }
3042
3043 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
3044 {
3045         static const struct phy_reg phy_reg_init[] = {
3046                 { 0x1f, 0x0002 },
3047                 { 0x10, 0x0008 },
3048                 { 0x0d, 0x006c },
3049
3050                 { 0x1f, 0x0000 },
3051                 { 0x0d, 0xf880 },
3052
3053                 { 0x1f, 0x0001 },
3054                 { 0x17, 0x0cc0 },
3055
3056                 { 0x1f, 0x0001 },
3057                 { 0x0b, 0xa4d8 },
3058                 { 0x09, 0x281c },
3059                 { 0x07, 0x2883 },
3060                 { 0x0a, 0x6b35 },
3061                 { 0x1d, 0x3da4 },
3062                 { 0x1c, 0xeffd },
3063                 { 0x14, 0x7f52 },
3064                 { 0x18, 0x7fc6 },
3065                 { 0x08, 0x0601 },
3066                 { 0x06, 0x4063 },
3067                 { 0x10, 0xf074 },
3068                 { 0x1f, 0x0003 },
3069                 { 0x13, 0x0789 },
3070                 { 0x12, 0xf4bd },
3071                 { 0x1a, 0x04fd },
3072                 { 0x14, 0x84b0 },
3073                 { 0x1f, 0x0000 },
3074                 { 0x00, 0x9200 },
3075
3076                 { 0x1f, 0x0005 },
3077                 { 0x01, 0x0340 },
3078                 { 0x1f, 0x0001 },
3079                 { 0x04, 0x4000 },
3080                 { 0x03, 0x1d21 },
3081                 { 0x02, 0x0c32 },
3082                 { 0x01, 0x0200 },
3083                 { 0x00, 0x5554 },
3084                 { 0x04, 0x4800 },
3085                 { 0x04, 0x4000 },
3086                 { 0x04, 0xf000 },
3087                 { 0x03, 0xdf01 },
3088                 { 0x02, 0xdf20 },
3089                 { 0x01, 0x101a },
3090                 { 0x00, 0xa0ff },
3091                 { 0x04, 0xf800 },
3092                 { 0x04, 0xf000 },
3093                 { 0x1f, 0x0000 },
3094
3095                 { 0x1f, 0x0007 },
3096                 { 0x1e, 0x0023 },
3097                 { 0x16, 0x0000 },
3098                 { 0x1f, 0x0000 }
3099         };
3100
3101         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3102 }
3103
3104 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3105 {
3106         static const struct phy_reg phy_reg_init[] = {
3107                 { 0x1f, 0x0001 },
3108                 { 0x17, 0x0cc0 },
3109
3110                 { 0x1f, 0x0007 },
3111                 { 0x1e, 0x002d },
3112                 { 0x18, 0x0040 },
3113                 { 0x1f, 0x0000 }
3114         };
3115
3116         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3117         rtl_patchphy(tp, 0x0d, 1 << 5);
3118 }
3119
3120 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3121 {
3122         static const struct phy_reg phy_reg_init[] = {
3123                 /* Enable Delay cap */
3124                 { 0x1f, 0x0005 },
3125                 { 0x05, 0x8b80 },
3126                 { 0x06, 0xc896 },
3127                 { 0x1f, 0x0000 },
3128
3129                 /* Channel estimation fine tune */
3130                 { 0x1f, 0x0001 },
3131                 { 0x0b, 0x6c20 },
3132                 { 0x07, 0x2872 },
3133                 { 0x1c, 0xefff },
3134                 { 0x1f, 0x0003 },
3135                 { 0x14, 0x6420 },
3136                 { 0x1f, 0x0000 },
3137
3138                 /* Update PFM & 10M TX idle timer */
3139                 { 0x1f, 0x0007 },
3140                 { 0x1e, 0x002f },
3141                 { 0x15, 0x1919 },
3142                 { 0x1f, 0x0000 },
3143
3144                 { 0x1f, 0x0007 },
3145                 { 0x1e, 0x00ac },
3146                 { 0x18, 0x0006 },
3147                 { 0x1f, 0x0000 }
3148         };
3149
3150         rtl_apply_firmware(tp);
3151
3152         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3153
3154         /* DCO enable for 10M IDLE Power */
3155         rtl_writephy(tp, 0x1f, 0x0007);
3156         rtl_writephy(tp, 0x1e, 0x0023);
3157         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
3158         rtl_writephy(tp, 0x1f, 0x0000);
3159
3160         /* For impedance matching */
3161         rtl_writephy(tp, 0x1f, 0x0002);
3162         rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
3163         rtl_writephy(tp, 0x1f, 0x0000);
3164
3165         /* PHY auto speed down */
3166         rtl_writephy(tp, 0x1f, 0x0007);
3167         rtl_writephy(tp, 0x1e, 0x002d);
3168         rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
3169         rtl_writephy(tp, 0x1f, 0x0000);
3170         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3171
3172         rtl_writephy(tp, 0x1f, 0x0005);
3173         rtl_writephy(tp, 0x05, 0x8b86);
3174         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3175         rtl_writephy(tp, 0x1f, 0x0000);
3176
3177         rtl_writephy(tp, 0x1f, 0x0005);
3178         rtl_writephy(tp, 0x05, 0x8b85);
3179         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3180         rtl_writephy(tp, 0x1f, 0x0007);
3181         rtl_writephy(tp, 0x1e, 0x0020);
3182         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
3183         rtl_writephy(tp, 0x1f, 0x0006);
3184         rtl_writephy(tp, 0x00, 0x5a00);
3185         rtl_writephy(tp, 0x1f, 0x0000);
3186         rtl_writephy(tp, 0x0d, 0x0007);
3187         rtl_writephy(tp, 0x0e, 0x003c);
3188         rtl_writephy(tp, 0x0d, 0x4007);
3189         rtl_writephy(tp, 0x0e, 0x0000);
3190         rtl_writephy(tp, 0x0d, 0x0000);
3191 }
3192
3193 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3194 {
3195         const u16 w[] = {
3196                 addr[0] | (addr[1] << 8),
3197                 addr[2] | (addr[3] << 8),
3198                 addr[4] | (addr[5] << 8)
3199         };
3200         const struct exgmac_reg e[] = {
3201                 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3202                 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3203                 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3204                 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3205         };
3206
3207         rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3208 }
3209
3210 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3211 {
3212         static const struct phy_reg phy_reg_init[] = {
3213                 /* Enable Delay cap */
3214                 { 0x1f, 0x0004 },
3215                 { 0x1f, 0x0007 },
3216                 { 0x1e, 0x00ac },
3217                 { 0x18, 0x0006 },
3218                 { 0x1f, 0x0002 },
3219                 { 0x1f, 0x0000 },
3220                 { 0x1f, 0x0000 },
3221
3222                 /* Channel estimation fine tune */
3223                 { 0x1f, 0x0003 },
3224                 { 0x09, 0xa20f },
3225                 { 0x1f, 0x0000 },
3226                 { 0x1f, 0x0000 },
3227
3228                 /* Green Setting */
3229                 { 0x1f, 0x0005 },
3230                 { 0x05, 0x8b5b },
3231                 { 0x06, 0x9222 },
3232                 { 0x05, 0x8b6d },
3233                 { 0x06, 0x8000 },
3234                 { 0x05, 0x8b76 },
3235                 { 0x06, 0x8000 },
3236                 { 0x1f, 0x0000 }
3237         };
3238
3239         rtl_apply_firmware(tp);
3240
3241         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3242
3243         /* For 4-corner performance improve */
3244         rtl_writephy(tp, 0x1f, 0x0005);
3245         rtl_writephy(tp, 0x05, 0x8b80);
3246         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
3247         rtl_writephy(tp, 0x1f, 0x0000);
3248
3249         /* PHY auto speed down */
3250         rtl_writephy(tp, 0x1f, 0x0004);
3251         rtl_writephy(tp, 0x1f, 0x0007);
3252         rtl_writephy(tp, 0x1e, 0x002d);
3253         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3254         rtl_writephy(tp, 0x1f, 0x0002);
3255         rtl_writephy(tp, 0x1f, 0x0000);
3256         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3257
3258         /* improve 10M EEE waveform */
3259         rtl_writephy(tp, 0x1f, 0x0005);
3260         rtl_writephy(tp, 0x05, 0x8b86);
3261         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3262         rtl_writephy(tp, 0x1f, 0x0000);
3263
3264         /* Improve 2-pair detection performance */
3265         rtl_writephy(tp, 0x1f, 0x0005);
3266         rtl_writephy(tp, 0x05, 0x8b85);
3267         rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3268         rtl_writephy(tp, 0x1f, 0x0000);
3269
3270         /* EEE setting */
3271         rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, ERIAR_EXGMAC);
3272         rtl_writephy(tp, 0x1f, 0x0005);
3273         rtl_writephy(tp, 0x05, 0x8b85);
3274         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3275         rtl_writephy(tp, 0x1f, 0x0004);
3276         rtl_writephy(tp, 0x1f, 0x0007);
3277         rtl_writephy(tp, 0x1e, 0x0020);
3278         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
3279         rtl_writephy(tp, 0x1f, 0x0002);
3280         rtl_writephy(tp, 0x1f, 0x0000);
3281         rtl_writephy(tp, 0x0d, 0x0007);
3282         rtl_writephy(tp, 0x0e, 0x003c);
3283         rtl_writephy(tp, 0x0d, 0x4007);
3284         rtl_writephy(tp, 0x0e, 0x0000);
3285         rtl_writephy(tp, 0x0d, 0x0000);
3286
3287         /* Green feature */
3288         rtl_writephy(tp, 0x1f, 0x0003);
3289         rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3290         rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3291         rtl_writephy(tp, 0x1f, 0x0000);
3292
3293         /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3294         rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3295 }
3296
3297 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3298 {
3299         /* For 4-corner performance improve */
3300         rtl_writephy(tp, 0x1f, 0x0005);
3301         rtl_writephy(tp, 0x05, 0x8b80);
3302         rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3303         rtl_writephy(tp, 0x1f, 0x0000);
3304
3305         /* PHY auto speed down */
3306         rtl_writephy(tp, 0x1f, 0x0007);
3307         rtl_writephy(tp, 0x1e, 0x002d);
3308         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3309         rtl_writephy(tp, 0x1f, 0x0000);
3310         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3311
3312         /* Improve 10M EEE waveform */
3313         rtl_writephy(tp, 0x1f, 0x0005);
3314         rtl_writephy(tp, 0x05, 0x8b86);
3315         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3316         rtl_writephy(tp, 0x1f, 0x0000);
3317 }
3318
3319 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3320 {
3321         static const struct phy_reg phy_reg_init[] = {
3322                 /* Channel estimation fine tune */
3323                 { 0x1f, 0x0003 },
3324                 { 0x09, 0xa20f },
3325                 { 0x1f, 0x0000 },
3326
3327                 /* Modify green table for giga & fnet */
3328                 { 0x1f, 0x0005 },
3329                 { 0x05, 0x8b55 },
3330                 { 0x06, 0x0000 },
3331                 { 0x05, 0x8b5e },
3332                 { 0x06, 0x0000 },
3333                 { 0x05, 0x8b67 },
3334                 { 0x06, 0x0000 },
3335                 { 0x05, 0x8b70 },
3336                 { 0x06, 0x0000 },
3337                 { 0x1f, 0x0000 },
3338                 { 0x1f, 0x0007 },
3339                 { 0x1e, 0x0078 },
3340                 { 0x17, 0x0000 },
3341                 { 0x19, 0x00fb },
3342                 { 0x1f, 0x0000 },
3343
3344                 /* Modify green table for 10M */
3345                 { 0x1f, 0x0005 },
3346                 { 0x05, 0x8b79 },
3347                 { 0x06, 0xaa00 },
3348                 { 0x1f, 0x0000 },
3349
3350                 /* Disable hiimpedance detection (RTCT) */
3351                 { 0x1f, 0x0003 },
3352                 { 0x01, 0x328a },
3353                 { 0x1f, 0x0000 }
3354         };
3355
3356         rtl_apply_firmware(tp);
3357
3358         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3359
3360         rtl8168f_hw_phy_config(tp);
3361
3362         /* Improve 2-pair detection performance */
3363         rtl_writephy(tp, 0x1f, 0x0005);
3364         rtl_writephy(tp, 0x05, 0x8b85);
3365         rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3366         rtl_writephy(tp, 0x1f, 0x0000);
3367 }
3368
3369 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3370 {
3371         rtl_apply_firmware(tp);
3372
3373         rtl8168f_hw_phy_config(tp);
3374 }
3375
3376 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3377 {
3378         static const struct phy_reg phy_reg_init[] = {
3379                 /* Channel estimation fine tune */
3380                 { 0x1f, 0x0003 },
3381                 { 0x09, 0xa20f },
3382                 { 0x1f, 0x0000 },
3383
3384                 /* Modify green table for giga & fnet */
3385                 { 0x1f, 0x0005 },
3386                 { 0x05, 0x8b55 },
3387                 { 0x06, 0x0000 },
3388                 { 0x05, 0x8b5e },
3389                 { 0x06, 0x0000 },
3390                 { 0x05, 0x8b67 },
3391                 { 0x06, 0x0000 },
3392                 { 0x05, 0x8b70 },
3393                 { 0x06, 0x0000 },
3394                 { 0x1f, 0x0000 },
3395                 { 0x1f, 0x0007 },
3396                 { 0x1e, 0x0078 },
3397                 { 0x17, 0x0000 },
3398                 { 0x19, 0x00aa },
3399                 { 0x1f, 0x0000 },
3400
3401                 /* Modify green table for 10M */
3402                 { 0x1f, 0x0005 },
3403                 { 0x05, 0x8b79 },
3404                 { 0x06, 0xaa00 },
3405                 { 0x1f, 0x0000 },
3406
3407                 /* Disable hiimpedance detection (RTCT) */
3408                 { 0x1f, 0x0003 },
3409                 { 0x01, 0x328a },
3410                 { 0x1f, 0x0000 }
3411         };
3412
3413
3414         rtl_apply_firmware(tp);
3415
3416         rtl8168f_hw_phy_config(tp);
3417
3418         /* Improve 2-pair detection performance */
3419         rtl_writephy(tp, 0x1f, 0x0005);
3420         rtl_writephy(tp, 0x05, 0x8b85);
3421         rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3422         rtl_writephy(tp, 0x1f, 0x0000);
3423
3424         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3425
3426         /* Modify green table for giga */
3427         rtl_writephy(tp, 0x1f, 0x0005);
3428         rtl_writephy(tp, 0x05, 0x8b54);
3429         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
3430         rtl_writephy(tp, 0x05, 0x8b5d);
3431         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
3432         rtl_writephy(tp, 0x05, 0x8a7c);
3433         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3434         rtl_writephy(tp, 0x05, 0x8a7f);
3435         rtl_w1w0_phy(tp, 0x06, 0x0100, 0x0000);
3436         rtl_writephy(tp, 0x05, 0x8a82);
3437         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3438         rtl_writephy(tp, 0x05, 0x8a85);
3439         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3440         rtl_writephy(tp, 0x05, 0x8a88);
3441         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3442         rtl_writephy(tp, 0x1f, 0x0000);
3443
3444         /* uc same-seed solution */
3445         rtl_writephy(tp, 0x1f, 0x0005);
3446         rtl_writephy(tp, 0x05, 0x8b85);
3447         rtl_w1w0_phy(tp, 0x06, 0x8000, 0x0000);
3448         rtl_writephy(tp, 0x1f, 0x0000);
3449
3450         /* eee setting */
3451         rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
3452         rtl_writephy(tp, 0x1f, 0x0005);
3453         rtl_writephy(tp, 0x05, 0x8b85);
3454         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3455         rtl_writephy(tp, 0x1f, 0x0004);
3456         rtl_writephy(tp, 0x1f, 0x0007);
3457         rtl_writephy(tp, 0x1e, 0x0020);
3458         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
3459         rtl_writephy(tp, 0x1f, 0x0000);
3460         rtl_writephy(tp, 0x0d, 0x0007);
3461         rtl_writephy(tp, 0x0e, 0x003c);
3462         rtl_writephy(tp, 0x0d, 0x4007);
3463         rtl_writephy(tp, 0x0e, 0x0000);
3464         rtl_writephy(tp, 0x0d, 0x0000);
3465
3466         /* Green feature */
3467         rtl_writephy(tp, 0x1f, 0x0003);
3468         rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3469         rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3470         rtl_writephy(tp, 0x1f, 0x0000);
3471 }
3472
3473 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3474 {
3475         rtl_apply_firmware(tp);
3476
3477         rtl_writephy(tp, 0x1f, 0x0a46);
3478         if (rtl_readphy(tp, 0x10) & 0x0100) {
3479                 rtl_writephy(tp, 0x1f, 0x0bcc);
3480                 rtl_w1w0_phy(tp, 0x12, 0x0000, 0x8000);
3481         } else {
3482                 rtl_writephy(tp, 0x1f, 0x0bcc);
3483                 rtl_w1w0_phy(tp, 0x12, 0x8000, 0x0000);
3484         }
3485
3486         rtl_writephy(tp, 0x1f, 0x0a46);
3487         if (rtl_readphy(tp, 0x13) & 0x0100) {
3488                 rtl_writephy(tp, 0x1f, 0x0c41);
3489                 rtl_w1w0_phy(tp, 0x15, 0x0002, 0x0000);
3490         } else {
3491                 rtl_writephy(tp, 0x1f, 0x0c41);
3492                 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0002);
3493         }
3494
3495         /* Enable PHY auto speed down */
3496         rtl_writephy(tp, 0x1f, 0x0a44);
3497         rtl_w1w0_phy(tp, 0x11, 0x000c, 0x0000);
3498
3499         rtl_writephy(tp, 0x1f, 0x0bcc);
3500         rtl_w1w0_phy(tp, 0x14, 0x0100, 0x0000);
3501         rtl_writephy(tp, 0x1f, 0x0a44);
3502         rtl_w1w0_phy(tp, 0x11, 0x00c0, 0x0000);
3503         rtl_writephy(tp, 0x1f, 0x0a43);
3504         rtl_writephy(tp, 0x13, 0x8084);
3505         rtl_w1w0_phy(tp, 0x14, 0x0000, 0x6000);
3506         rtl_w1w0_phy(tp, 0x10, 0x1003, 0x0000);
3507
3508         /* EEE auto-fallback function */
3509         rtl_writephy(tp, 0x1f, 0x0a4b);
3510         rtl_w1w0_phy(tp, 0x11, 0x0004, 0x0000);
3511
3512         /* Enable UC LPF tune function */
3513         rtl_writephy(tp, 0x1f, 0x0a43);
3514         rtl_writephy(tp, 0x13, 0x8012);
3515         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3516
3517         rtl_writephy(tp, 0x1f, 0x0c42);
3518         rtl_w1w0_phy(tp, 0x11, 0x4000, 0x2000);
3519
3520         /* Improve SWR Efficiency */
3521         rtl_writephy(tp, 0x1f, 0x0bcd);
3522         rtl_writephy(tp, 0x14, 0x5065);
3523         rtl_writephy(tp, 0x14, 0xd065);
3524         rtl_writephy(tp, 0x1f, 0x0bc8);
3525         rtl_writephy(tp, 0x11, 0x5655);
3526         rtl_writephy(tp, 0x1f, 0x0bcd);
3527         rtl_writephy(tp, 0x14, 0x1065);
3528         rtl_writephy(tp, 0x14, 0x9065);
3529         rtl_writephy(tp, 0x14, 0x1065);
3530
3531         /* Check ALDPS bit, disable it if enabled */
3532         rtl_writephy(tp, 0x1f, 0x0a43);
3533         if (rtl_readphy(tp, 0x10) & 0x0004)
3534                 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0004);
3535
3536         rtl_writephy(tp, 0x1f, 0x0000);
3537 }
3538
3539 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3540 {
3541         rtl_apply_firmware(tp);
3542 }
3543
3544 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3545 {
3546         u16 dout_tapbin;
3547         u32 data;
3548
3549         rtl_apply_firmware(tp);
3550
3551         /* CHN EST parameters adjust - giga master */
3552         rtl_writephy(tp, 0x1f, 0x0a43);
3553         rtl_writephy(tp, 0x13, 0x809b);
3554         rtl_w1w0_phy(tp, 0x14, 0x8000, 0xf800);
3555         rtl_writephy(tp, 0x13, 0x80a2);
3556         rtl_w1w0_phy(tp, 0x14, 0x8000, 0xff00);
3557         rtl_writephy(tp, 0x13, 0x80a4);
3558         rtl_w1w0_phy(tp, 0x14, 0x8500, 0xff00);
3559         rtl_writephy(tp, 0x13, 0x809c);
3560         rtl_w1w0_phy(tp, 0x14, 0xbd00, 0xff00);
3561         rtl_writephy(tp, 0x1f, 0x0000);
3562
3563         /* CHN EST parameters adjust - giga slave */
3564         rtl_writephy(tp, 0x1f, 0x0a43);
3565         rtl_writephy(tp, 0x13, 0x80ad);
3566         rtl_w1w0_phy(tp, 0x14, 0x7000, 0xf800);
3567         rtl_writephy(tp, 0x13, 0x80b4);
3568         rtl_w1w0_phy(tp, 0x14, 0x5000, 0xff00);
3569         rtl_writephy(tp, 0x13, 0x80ac);
3570         rtl_w1w0_phy(tp, 0x14, 0x4000, 0xff00);
3571         rtl_writephy(tp, 0x1f, 0x0000);
3572
3573         /* CHN EST parameters adjust - fnet */
3574         rtl_writephy(tp, 0x1f, 0x0a43);
3575         rtl_writephy(tp, 0x13, 0x808e);
3576         rtl_w1w0_phy(tp, 0x14, 0x1200, 0xff00);
3577         rtl_writephy(tp, 0x13, 0x8090);
3578         rtl_w1w0_phy(tp, 0x14, 0xe500, 0xff00);
3579         rtl_writephy(tp, 0x13, 0x8092);
3580         rtl_w1w0_phy(tp, 0x14, 0x9f00, 0xff00);
3581         rtl_writephy(tp, 0x1f, 0x0000);
3582
3583         /* enable R-tune & PGA-retune function */
3584         dout_tapbin = 0;
3585         rtl_writephy(tp, 0x1f, 0x0a46);
3586         data = rtl_readphy(tp, 0x13);
3587         data &= 3;
3588         data <<= 2;
3589         dout_tapbin |= data;
3590         data = rtl_readphy(tp, 0x12);
3591         data &= 0xc000;
3592         data >>= 14;
3593         dout_tapbin |= data;
3594         dout_tapbin = ~(dout_tapbin^0x08);
3595         dout_tapbin <<= 12;
3596         dout_tapbin &= 0xf000;
3597         rtl_writephy(tp, 0x1f, 0x0a43);
3598         rtl_writephy(tp, 0x13, 0x827a);
3599         rtl_w1w0_phy(tp, 0x14, dout_tapbin, 0xf000);
3600         rtl_writephy(tp, 0x13, 0x827b);
3601         rtl_w1w0_phy(tp, 0x14, dout_tapbin, 0xf000);
3602         rtl_writephy(tp, 0x13, 0x827c);
3603         rtl_w1w0_phy(tp, 0x14, dout_tapbin, 0xf000);
3604         rtl_writephy(tp, 0x13, 0x827d);
3605         rtl_w1w0_phy(tp, 0x14, dout_tapbin, 0xf000);
3606
3607         rtl_writephy(tp, 0x1f, 0x0a43);
3608         rtl_writephy(tp, 0x13, 0x0811);
3609         rtl_w1w0_phy(tp, 0x14, 0x0800, 0x0000);
3610         rtl_writephy(tp, 0x1f, 0x0a42);
3611         rtl_w1w0_phy(tp, 0x16, 0x0002, 0x0000);
3612         rtl_writephy(tp, 0x1f, 0x0000);
3613
3614         /* enable GPHY 10M */
3615         rtl_writephy(tp, 0x1f, 0x0a44);
3616         rtl_w1w0_phy(tp, 0x11, 0x0800, 0x0000);
3617         rtl_writephy(tp, 0x1f, 0x0000);
3618
3619         /* SAR ADC performance */
3620         rtl_writephy(tp, 0x1f, 0x0bca);
3621         rtl_w1w0_phy(tp, 0x17, 0x4000, 0x3000);
3622         rtl_writephy(tp, 0x1f, 0x0000);
3623
3624         rtl_writephy(tp, 0x1f, 0x0a43);
3625         rtl_writephy(tp, 0x13, 0x803f);
3626         rtl_w1w0_phy(tp, 0x14, 0x0000, 0x3000);
3627         rtl_writephy(tp, 0x13, 0x8047);
3628         rtl_w1w0_phy(tp, 0x14, 0x0000, 0x3000);
3629         rtl_writephy(tp, 0x13, 0x804f);
3630         rtl_w1w0_phy(tp, 0x14, 0x0000, 0x3000);
3631         rtl_writephy(tp, 0x13, 0x8057);
3632         rtl_w1w0_phy(tp, 0x14, 0x0000, 0x3000);
3633         rtl_writephy(tp, 0x13, 0x805f);
3634         rtl_w1w0_phy(tp, 0x14, 0x0000, 0x3000);
3635         rtl_writephy(tp, 0x13, 0x8067);
3636         rtl_w1w0_phy(tp, 0x14, 0x0000, 0x3000);
3637         rtl_writephy(tp, 0x13, 0x806f);
3638         rtl_w1w0_phy(tp, 0x14, 0x0000, 0x3000);
3639         rtl_writephy(tp, 0x1f, 0x0000);
3640
3641         /* disable phy pfm mode */
3642         rtl_writephy(tp, 0x1f, 0x0a44);
3643         rtl_w1w0_phy(tp, 0x14, 0x0000, 0x0080);
3644         rtl_writephy(tp, 0x1f, 0x0000);
3645
3646         /* Check ALDPS bit, disable it if enabled */
3647         rtl_writephy(tp, 0x1f, 0x0a43);
3648         if (rtl_readphy(tp, 0x10) & 0x0004)
3649                 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0004);
3650
3651         rtl_writephy(tp, 0x1f, 0x0000);
3652 }
3653
3654 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3655 {
3656         u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3657         u16 rlen;
3658         u32 data;
3659
3660         rtl_apply_firmware(tp);
3661
3662         /* CHIN EST parameter update */
3663         rtl_writephy(tp, 0x1f, 0x0a43);
3664         rtl_writephy(tp, 0x13, 0x808a);
3665         rtl_w1w0_phy(tp, 0x14, 0x000a, 0x003f);
3666         rtl_writephy(tp, 0x1f, 0x0000);
3667
3668         /* enable R-tune & PGA-retune function */
3669         rtl_writephy(tp, 0x1f, 0x0a43);
3670         rtl_writephy(tp, 0x13, 0x0811);
3671         rtl_w1w0_phy(tp, 0x14, 0x0800, 0x0000);
3672         rtl_writephy(tp, 0x1f, 0x0a42);
3673         rtl_w1w0_phy(tp, 0x16, 0x0002, 0x0000);
3674         rtl_writephy(tp, 0x1f, 0x0000);
3675
3676         /* enable GPHY 10M */
3677         rtl_writephy(tp, 0x1f, 0x0a44);
3678         rtl_w1w0_phy(tp, 0x11, 0x0800, 0x0000);
3679         rtl_writephy(tp, 0x1f, 0x0000);
3680
3681         r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3682         data = r8168_mac_ocp_read(tp, 0xdd02);
3683         ioffset_p3 = ((data & 0x80)>>7);
3684         ioffset_p3 <<= 3;
3685
3686         data = r8168_mac_ocp_read(tp, 0xdd00);
3687         ioffset_p3 |= ((data & (0xe000))>>13);
3688         ioffset_p2 = ((data & (0x1e00))>>9);
3689         ioffset_p1 = ((data & (0x01e0))>>5);
3690         ioffset_p0 = ((data & 0x0010)>>4);
3691         ioffset_p0 <<= 3;
3692         ioffset_p0 |= (data & (0x07));
3693         data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3694
3695         if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
3696             (ioffset_p1 != 0x0f) || (ioffset_p0 == 0x0f)) {
3697                 rtl_writephy(tp, 0x1f, 0x0bcf);
3698                 rtl_writephy(tp, 0x16, data);
3699                 rtl_writephy(tp, 0x1f, 0x0000);
3700         }
3701
3702         /* Modify rlen (TX LPF corner frequency) level */
3703         rtl_writephy(tp, 0x1f, 0x0bcd);
3704         data = rtl_readphy(tp, 0x16);
3705         data &= 0x000f;
3706         rlen = 0;
3707         if (data > 3)
3708                 rlen = data - 3;
3709         data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3710         rtl_writephy(tp, 0x17, data);
3711         rtl_writephy(tp, 0x1f, 0x0bcd);
3712         rtl_writephy(tp, 0x1f, 0x0000);
3713
3714         /* disable phy pfm mode */
3715         rtl_writephy(tp, 0x1f, 0x0a44);
3716         rtl_w1w0_phy(tp, 0x14, 0x0000, 0x0080);
3717         rtl_writephy(tp, 0x1f, 0x0000);
3718
3719         /* Check ALDPS bit, disable it if enabled */
3720         rtl_writephy(tp, 0x1f, 0x0a43);
3721         if (rtl_readphy(tp, 0x10) & 0x0004)
3722                 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0004);
3723
3724         rtl_writephy(tp, 0x1f, 0x0000);
3725 }
3726
3727 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3728 {
3729         static const struct phy_reg phy_reg_init[] = {
3730                 { 0x1f, 0x0003 },
3731                 { 0x08, 0x441d },
3732                 { 0x01, 0x9100 },
3733                 { 0x1f, 0x0000 }
3734         };
3735
3736         rtl_writephy(tp, 0x1f, 0x0000);
3737         rtl_patchphy(tp, 0x11, 1 << 12);
3738         rtl_patchphy(tp, 0x19, 1 << 13);
3739         rtl_patchphy(tp, 0x10, 1 << 15);
3740
3741         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3742 }
3743
3744 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3745 {
3746         static const struct phy_reg phy_reg_init[] = {
3747                 { 0x1f, 0x0005 },
3748                 { 0x1a, 0x0000 },
3749                 { 0x1f, 0x0000 },
3750
3751                 { 0x1f, 0x0004 },
3752                 { 0x1c, 0x0000 },
3753                 { 0x1f, 0x0000 },
3754
3755                 { 0x1f, 0x0001 },
3756                 { 0x15, 0x7701 },
3757                 { 0x1f, 0x0000 }
3758         };
3759
3760         /* Disable ALDPS before ram code */
3761         rtl_writephy(tp, 0x1f, 0x0000);
3762         rtl_writephy(tp, 0x18, 0x0310);
3763         msleep(100);
3764
3765         rtl_apply_firmware(tp);
3766
3767         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3768 }
3769
3770 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3771 {
3772         /* Disable ALDPS before setting firmware */
3773         rtl_writephy(tp, 0x1f, 0x0000);
3774         rtl_writephy(tp, 0x18, 0x0310);
3775         msleep(20);
3776
3777         rtl_apply_firmware(tp);
3778
3779         /* EEE setting */
3780         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3781         rtl_writephy(tp, 0x1f, 0x0004);
3782         rtl_writephy(tp, 0x10, 0x401f);
3783         rtl_writephy(tp, 0x19, 0x7030);
3784         rtl_writephy(tp, 0x1f, 0x0000);
3785 }
3786
3787 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3788 {
3789         static const struct phy_reg phy_reg_init[] = {
3790                 { 0x1f, 0x0004 },
3791                 { 0x10, 0xc07f },
3792                 { 0x19, 0x7030 },
3793                 { 0x1f, 0x0000 }
3794         };
3795
3796         /* Disable ALDPS before ram code */
3797         rtl_writephy(tp, 0x1f, 0x0000);
3798         rtl_writephy(tp, 0x18, 0x0310);
3799         msleep(100);
3800
3801         rtl_apply_firmware(tp);
3802
3803         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3804         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3805
3806         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3807 }
3808
3809 static void rtl_hw_phy_config(struct net_device *dev)
3810 {
3811         struct rtl8169_private *tp = netdev_priv(dev);
3812
3813         rtl8169_print_mac_version(tp);
3814
3815         switch (tp->mac_version) {
3816         case RTL_GIGA_MAC_VER_01:
3817                 break;
3818         case RTL_GIGA_MAC_VER_02:
3819         case RTL_GIGA_MAC_VER_03:
3820                 rtl8169s_hw_phy_config(tp);
3821                 break;
3822         case RTL_GIGA_MAC_VER_04:
3823                 rtl8169sb_hw_phy_config(tp);
3824                 break;
3825         case RTL_GIGA_MAC_VER_05:
3826                 rtl8169scd_hw_phy_config(tp);
3827                 break;
3828         case RTL_GIGA_MAC_VER_06:
3829                 rtl8169sce_hw_phy_config(tp);
3830                 break;
3831         case RTL_GIGA_MAC_VER_07:
3832         case RTL_GIGA_MAC_VER_08:
3833         case RTL_GIGA_MAC_VER_09:
3834                 rtl8102e_hw_phy_config(tp);
3835                 break;
3836         case RTL_GIGA_MAC_VER_11:
3837                 rtl8168bb_hw_phy_config(tp);
3838                 break;
3839         case RTL_GIGA_MAC_VER_12:
3840                 rtl8168bef_hw_phy_config(tp);
3841                 break;
3842         case RTL_GIGA_MAC_VER_17:
3843                 rtl8168bef_hw_phy_config(tp);
3844                 break;
3845         case RTL_GIGA_MAC_VER_18:
3846                 rtl8168cp_1_hw_phy_config(tp);
3847                 break;
3848         case RTL_GIGA_MAC_VER_19:
3849                 rtl8168c_1_hw_phy_config(tp);
3850                 break;
3851         case RTL_GIGA_MAC_VER_20:
3852                 rtl8168c_2_hw_phy_config(tp);
3853                 break;
3854         case RTL_GIGA_MAC_VER_21:
3855                 rtl8168c_3_hw_phy_config(tp);
3856                 break;
3857         case RTL_GIGA_MAC_VER_22:
3858                 rtl8168c_4_hw_phy_config(tp);
3859                 break;
3860         case RTL_GIGA_MAC_VER_23:
3861         case RTL_GIGA_MAC_VER_24:
3862                 rtl8168cp_2_hw_phy_config(tp);
3863                 break;
3864         case RTL_GIGA_MAC_VER_25:
3865                 rtl8168d_1_hw_phy_config(tp);
3866                 break;
3867         case RTL_GIGA_MAC_VER_26:
3868                 rtl8168d_2_hw_phy_config(tp);
3869                 break;
3870         case RTL_GIGA_MAC_VER_27:
3871                 rtl8168d_3_hw_phy_config(tp);
3872                 break;
3873         case RTL_GIGA_MAC_VER_28:
3874                 rtl8168d_4_hw_phy_config(tp);
3875                 break;
3876         case RTL_GIGA_MAC_VER_29:
3877         case RTL_GIGA_MAC_VER_30:
3878                 rtl8105e_hw_phy_config(tp);
3879                 break;
3880         case RTL_GIGA_MAC_VER_31:
3881                 /* None. */
3882                 break;
3883         case RTL_GIGA_MAC_VER_32:
3884         case RTL_GIGA_MAC_VER_33:
3885                 rtl8168e_1_hw_phy_config(tp);
3886                 break;
3887         case RTL_GIGA_MAC_VER_34:
3888                 rtl8168e_2_hw_phy_config(tp);
3889                 break;
3890         case RTL_GIGA_MAC_VER_35:
3891                 rtl8168f_1_hw_phy_config(tp);
3892                 break;
3893         case RTL_GIGA_MAC_VER_36:
3894                 rtl8168f_2_hw_phy_config(tp);
3895                 break;
3896
3897         case RTL_GIGA_MAC_VER_37:
3898                 rtl8402_hw_phy_config(tp);
3899                 break;
3900
3901         case RTL_GIGA_MAC_VER_38:
3902                 rtl8411_hw_phy_config(tp);
3903                 break;
3904
3905         case RTL_GIGA_MAC_VER_39:
3906                 rtl8106e_hw_phy_config(tp);
3907                 break;
3908
3909         case RTL_GIGA_MAC_VER_40:
3910                 rtl8168g_1_hw_phy_config(tp);
3911                 break;
3912         case RTL_GIGA_MAC_VER_42:
3913         case RTL_GIGA_MAC_VER_43:
3914         case RTL_GIGA_MAC_VER_44:
3915                 rtl8168g_2_hw_phy_config(tp);
3916                 break;
3917         case RTL_GIGA_MAC_VER_45:
3918         case RTL_GIGA_MAC_VER_47:
3919                 rtl8168h_1_hw_phy_config(tp);
3920                 break;
3921         case RTL_GIGA_MAC_VER_46:
3922         case RTL_GIGA_MAC_VER_48:
3923                 rtl8168h_2_hw_phy_config(tp);
3924                 break;
3925
3926         case RTL_GIGA_MAC_VER_41:
3927         default:
3928                 break;
3929         }
3930 }
3931
3932 static void rtl_phy_work(struct rtl8169_private *tp)
3933 {
3934         struct timer_list *timer = &tp->timer;
3935         void __iomem *ioaddr = tp->mmio_addr;
3936         unsigned long timeout = RTL8169_PHY_TIMEOUT;
3937
3938         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
3939
3940         if (tp->phy_reset_pending(tp)) {
3941                 /*
3942                  * A busy loop could burn quite a few cycles on nowadays CPU.
3943                  * Let's delay the execution of the timer for a few ticks.
3944                  */
3945                 timeout = HZ/10;
3946                 goto out_mod_timer;
3947         }
3948
3949         if (tp->link_ok(ioaddr))
3950                 return;
3951
3952         netif_dbg(tp, link, tp->dev, "PHY reset until link up\n");
3953
3954         tp->phy_reset_enable(tp);
3955
3956 out_mod_timer:
3957         mod_timer(timer, jiffies + timeout);
3958 }
3959
3960 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3961 {
3962         if (!test_and_set_bit(flag, tp->wk.flags))
3963                 schedule_work(&tp->wk.work);
3964 }
3965
3966 static void rtl8169_phy_timer(unsigned long __opaque)
3967 {
3968         struct net_device *dev = (struct net_device *)__opaque;
3969         struct rtl8169_private *tp = netdev_priv(dev);
3970
3971         rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
3972 }
3973
3974 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3975                                   void __iomem *ioaddr)
3976 {
3977         iounmap(ioaddr);
3978         pci_release_regions(pdev);
3979         pci_clear_mwi(pdev);
3980         pci_disable_device(pdev);
3981         free_netdev(dev);
3982 }
3983
3984 DECLARE_RTL_COND(rtl_phy_reset_cond)
3985 {
3986         return tp->phy_reset_pending(tp);
3987 }
3988
3989 static void rtl8169_phy_reset(struct net_device *dev,
3990                               struct rtl8169_private *tp)
3991 {
3992         tp->phy_reset_enable(tp);
3993         rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
3994 }
3995
3996 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
3997 {
3998         void __iomem *ioaddr = tp->mmio_addr;
3999
4000         return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
4001             (RTL_R8(PHYstatus) & TBI_Enable);
4002 }
4003
4004 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
4005 {
4006         void __iomem *ioaddr = tp->mmio_addr;
4007
4008         rtl_hw_phy_config(dev);
4009
4010         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
4011                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4012                 RTL_W8(0x82, 0x01);
4013         }
4014
4015         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4016
4017         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
4018                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4019
4020         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4021                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4022                 RTL_W8(0x82, 0x01);
4023                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4024                 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4025         }
4026
4027         rtl8169_phy_reset(dev, tp);
4028
4029         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
4030                           ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4031                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4032                           (tp->mii.supports_gmii ?
4033                            ADVERTISED_1000baseT_Half |
4034                            ADVERTISED_1000baseT_Full : 0));
4035
4036         if (rtl_tbi_enabled(tp))
4037                 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4038 }
4039
4040 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4041 {
4042         void __iomem *ioaddr = tp->mmio_addr;
4043
4044         rtl_lock_work(tp);
4045
4046         RTL_W8(Cfg9346, Cfg9346_Unlock);
4047
4048         RTL_W32(MAC4, addr[4] | addr[5] << 8);
4049         RTL_R32(MAC4);
4050
4051         RTL_W32(MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
4052         RTL_R32(MAC0);
4053
4054         if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4055                 rtl_rar_exgmac_set(tp, addr);
4056
4057         RTL_W8(Cfg9346, Cfg9346_Lock);
4058
4059         rtl_unlock_work(tp);
4060 }
4061
4062 static int rtl_set_mac_address(struct net_device *dev, void *p)
4063 {
4064         struct rtl8169_private *tp = netdev_priv(dev);
4065         struct sockaddr *addr = p;
4066
4067         if (!is_valid_ether_addr(addr->sa_data))
4068                 return -EADDRNOTAVAIL;
4069
4070         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
4071
4072         rtl_rar_set(tp, dev->dev_addr);
4073
4074         return 0;
4075 }
4076
4077 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4078 {
4079         struct rtl8169_private *tp = netdev_priv(dev);
4080         struct mii_ioctl_data *data = if_mii(ifr);
4081
4082         return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
4083 }
4084
4085 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
4086                           struct mii_ioctl_data *data, int cmd)
4087 {
4088         switch (cmd) {
4089         case SIOCGMIIPHY:
4090                 data->phy_id = 32; /* Internal PHY */
4091                 return 0;
4092
4093         case SIOCGMIIREG:
4094                 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
4095                 return 0;
4096
4097         case SIOCSMIIREG:
4098                 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
4099                 return 0;
4100         }
4101         return -EOPNOTSUPP;
4102 }
4103
4104 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
4105 {
4106         return -EOPNOTSUPP;
4107 }
4108
4109 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
4110 {
4111         if (tp->features & RTL_FEATURE_MSI) {
4112                 pci_disable_msi(pdev);
4113                 tp->features &= ~RTL_FEATURE_MSI;
4114         }
4115 }
4116
4117 static void rtl_init_mdio_ops(struct rtl8169_private *tp)
4118 {
4119         struct mdio_ops *ops = &tp->mdio_ops;
4120
4121         switch (tp->mac_version) {
4122         case RTL_GIGA_MAC_VER_27:
4123                 ops->write      = r8168dp_1_mdio_write;
4124                 ops->read       = r8168dp_1_mdio_read;
4125                 break;
4126         case RTL_GIGA_MAC_VER_28:
4127         case RTL_GIGA_MAC_VER_31:
4128                 ops->write      = r8168dp_2_mdio_write;
4129                 ops->read       = r8168dp_2_mdio_read;
4130                 break;
4131         case RTL_GIGA_MAC_VER_40:
4132         case RTL_GIGA_MAC_VER_41:
4133         case RTL_GIGA_MAC_VER_42:
4134         case RTL_GIGA_MAC_VER_43:
4135         case RTL_GIGA_MAC_VER_44:
4136         case RTL_GIGA_MAC_VER_45:
4137         case RTL_GIGA_MAC_VER_46:
4138         case RTL_GIGA_MAC_VER_47:
4139         case RTL_GIGA_MAC_VER_48:
4140                 ops->write      = r8168g_mdio_write;
4141                 ops->read       = r8168g_mdio_read;
4142                 break;
4143         default:
4144                 ops->write      = r8169_mdio_write;
4145                 ops->read       = r8169_mdio_read;
4146                 break;
4147         }
4148 }
4149
4150 static void rtl_speed_down(struct rtl8169_private *tp)
4151 {
4152         u32 adv;
4153         int lpa;
4154
4155         rtl_writephy(tp, 0x1f, 0x0000);
4156         lpa = rtl_readphy(tp, MII_LPA);
4157
4158         if (lpa & (LPA_10HALF | LPA_10FULL))
4159                 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
4160         else if (lpa & (LPA_100HALF | LPA_100FULL))
4161                 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4162                       ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4163         else
4164                 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4165                       ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4166                       (tp->mii.supports_gmii ?
4167                        ADVERTISED_1000baseT_Half |
4168                        ADVERTISED_1000baseT_Full : 0);
4169
4170         rtl8169_set_speed(tp->dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
4171                           adv);
4172 }
4173
4174 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4175 {
4176         void __iomem *ioaddr = tp->mmio_addr;
4177
4178         switch (tp->mac_version) {
4179         case RTL_GIGA_MAC_VER_25:
4180         case RTL_GIGA_MAC_VER_26:
4181         case RTL_GIGA_MAC_VER_29:
4182         case RTL_GIGA_MAC_VER_30:
4183         case RTL_GIGA_MAC_VER_32:
4184         case RTL_GIGA_MAC_VER_33:
4185         case RTL_GIGA_MAC_VER_34:
4186         case RTL_GIGA_MAC_VER_37:
4187         case RTL_GIGA_MAC_VER_38:
4188         case RTL_GIGA_MAC_VER_39:
4189         case RTL_GIGA_MAC_VER_40:
4190         case RTL_GIGA_MAC_VER_41:
4191         case RTL_GIGA_MAC_VER_42:
4192         case RTL_GIGA_MAC_VER_43:
4193         case RTL_GIGA_MAC_VER_44:
4194         case RTL_GIGA_MAC_VER_45:
4195         case RTL_GIGA_MAC_VER_46:
4196         case RTL_GIGA_MAC_VER_47:
4197         case RTL_GIGA_MAC_VER_48:
4198                 RTL_W32(RxConfig, RTL_R32(RxConfig) |
4199                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4200                 break;
4201         default:
4202                 break;
4203         }
4204 }
4205
4206 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
4207 {
4208         if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
4209                 return false;
4210
4211         rtl_speed_down(tp);
4212         rtl_wol_suspend_quirk(tp);
4213
4214         return true;
4215 }
4216
4217 static void r810x_phy_power_down(struct rtl8169_private *tp)
4218 {
4219         rtl_writephy(tp, 0x1f, 0x0000);
4220         rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4221 }
4222
4223 static void r810x_phy_power_up(struct rtl8169_private *tp)
4224 {
4225         rtl_writephy(tp, 0x1f, 0x0000);
4226         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4227 }
4228
4229 static void r810x_pll_power_down(struct rtl8169_private *tp)
4230 {
4231         void __iomem *ioaddr = tp->mmio_addr;
4232
4233         if (rtl_wol_pll_power_down(tp))
4234                 return;
4235
4236         r810x_phy_power_down(tp);
4237
4238         switch (tp->mac_version) {
4239         case RTL_GIGA_MAC_VER_07:
4240         case RTL_GIGA_MAC_VER_08:
4241         case RTL_GIGA_MAC_VER_09:
4242         case RTL_GIGA_MAC_VER_10:
4243         case RTL_GIGA_MAC_VER_13:
4244         case RTL_GIGA_MAC_VER_16:
4245                 break;
4246         default:
4247                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4248                 break;
4249         }
4250 }
4251
4252 static void r810x_pll_power_up(struct rtl8169_private *tp)
4253 {
4254         void __iomem *ioaddr = tp->mmio_addr;
4255
4256         r810x_phy_power_up(tp);
4257
4258         switch (tp->mac_version) {
4259         case RTL_GIGA_MAC_VER_07:
4260         case RTL_GIGA_MAC_VER_08:
4261         case RTL_GIGA_MAC_VER_09:
4262         case RTL_GIGA_MAC_VER_10:
4263         case RTL_GIGA_MAC_VER_13:
4264         case RTL_GIGA_MAC_VER_16:
4265                 break;
4266         case RTL_GIGA_MAC_VER_47:
4267         case RTL_GIGA_MAC_VER_48:
4268                 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
4269                 break;
4270         default:
4271                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4272                 break;
4273         }
4274 }
4275
4276 static void r8168_phy_power_up(struct rtl8169_private *tp)
4277 {
4278         rtl_writephy(tp, 0x1f, 0x0000);
4279         switch (tp->mac_version) {
4280         case RTL_GIGA_MAC_VER_11:
4281         case RTL_GIGA_MAC_VER_12:
4282         case RTL_GIGA_MAC_VER_17:
4283         case RTL_GIGA_MAC_VER_18:
4284         case RTL_GIGA_MAC_VER_19:
4285         case RTL_GIGA_MAC_VER_20:
4286         case RTL_GIGA_MAC_VER_21:
4287         case RTL_GIGA_MAC_VER_22:
4288         case RTL_GIGA_MAC_VER_23:
4289         case RTL_GIGA_MAC_VER_24:
4290         case RTL_GIGA_MAC_VER_25:
4291         case RTL_GIGA_MAC_VER_26:
4292         case RTL_GIGA_MAC_VER_27:
4293         case RTL_GIGA_MAC_VER_28:
4294         case RTL_GIGA_MAC_VER_31:
4295                 rtl_writephy(tp, 0x0e, 0x0000);
4296                 break;
4297         default:
4298                 break;
4299         }
4300         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4301 }
4302
4303 static void r8168_phy_power_down(struct rtl8169_private *tp)
4304 {
4305         rtl_writephy(tp, 0x1f, 0x0000);
4306         switch (tp->mac_version) {
4307         case RTL_GIGA_MAC_VER_32:
4308         case RTL_GIGA_MAC_VER_33:
4309         case RTL_GIGA_MAC_VER_40:
4310         case RTL_GIGA_MAC_VER_41:
4311                 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
4312                 break;
4313
4314         case RTL_GIGA_MAC_VER_11:
4315         case RTL_GIGA_MAC_VER_12:
4316         case RTL_GIGA_MAC_VER_17:
4317         case RTL_GIGA_MAC_VER_18:
4318         case RTL_GIGA_MAC_VER_19:
4319         case RTL_GIGA_MAC_VER_20:
4320         case RTL_GIGA_MAC_VER_21:
4321         case RTL_GIGA_MAC_VER_22:
4322         case RTL_GIGA_MAC_VER_23:
4323         case RTL_GIGA_MAC_VER_24:
4324         case RTL_GIGA_MAC_VER_25:
4325         case RTL_GIGA_MAC_VER_26:
4326         case RTL_GIGA_MAC_VER_27:
4327         case RTL_GIGA_MAC_VER_28:
4328         case RTL_GIGA_MAC_VER_31:
4329                 rtl_writephy(tp, 0x0e, 0x0200);
4330         default:
4331                 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4332                 break;
4333         }
4334 }
4335
4336 static void r8168_pll_power_down(struct rtl8169_private *tp)
4337 {
4338         void __iomem *ioaddr = tp->mmio_addr;
4339
4340         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4341              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4342              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
4343             r8168dp_check_dash(tp)) {
4344                 return;
4345         }
4346
4347         if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
4348              tp->mac_version == RTL_GIGA_MAC_VER_24) &&
4349             (RTL_R16(CPlusCmd) & ASF)) {
4350                 return;
4351         }
4352
4353         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4354             tp->mac_version == RTL_GIGA_MAC_VER_33)
4355                 rtl_ephy_write(tp, 0x19, 0xff64);
4356
4357         if (rtl_wol_pll_power_down(tp))
4358                 return;
4359
4360         r8168_phy_power_down(tp);
4361
4362         switch (tp->mac_version) {
4363         case RTL_GIGA_MAC_VER_25:
4364         case RTL_GIGA_MAC_VER_26:
4365         case RTL_GIGA_MAC_VER_27:
4366         case RTL_GIGA_MAC_VER_28:
4367         case RTL_GIGA_MAC_VER_31:
4368         case RTL_GIGA_MAC_VER_32:
4369         case RTL_GIGA_MAC_VER_33:
4370         case RTL_GIGA_MAC_VER_45:
4371         case RTL_GIGA_MAC_VER_46:
4372                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4373                 break;
4374         case RTL_GIGA_MAC_VER_40:
4375         case RTL_GIGA_MAC_VER_41:
4376                 rtl_w1w0_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
4377                              0xfc000000, ERIAR_EXGMAC);
4378                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4379                 break;
4380         }
4381 }
4382
4383 static void r8168_pll_power_up(struct rtl8169_private *tp)
4384 {
4385         void __iomem *ioaddr = tp->mmio_addr;
4386
4387         switch (tp->mac_version) {
4388         case RTL_GIGA_MAC_VER_25:
4389         case RTL_GIGA_MAC_VER_26:
4390         case RTL_GIGA_MAC_VER_27:
4391         case RTL_GIGA_MAC_VER_28:
4392         case RTL_GIGA_MAC_VER_31:
4393         case RTL_GIGA_MAC_VER_32:
4394         case RTL_GIGA_MAC_VER_33:
4395                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4396                 break;
4397         case RTL_GIGA_MAC_VER_45:
4398         case RTL_GIGA_MAC_VER_46:
4399                 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
4400                 break;
4401         case RTL_GIGA_MAC_VER_40:
4402         case RTL_GIGA_MAC_VER_41:
4403                 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
4404                 rtl_w1w0_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
4405                              0x00000000, ERIAR_EXGMAC);
4406                 break;
4407         }
4408
4409         r8168_phy_power_up(tp);
4410 }
4411
4412 static void rtl_generic_op(struct rtl8169_private *tp,
4413                            void (*op)(struct rtl8169_private *))
4414 {
4415         if (op)
4416                 op(tp);
4417 }
4418
4419 static void rtl_pll_power_down(struct rtl8169_private *tp)
4420 {
4421         rtl_generic_op(tp, tp->pll_power_ops.down);
4422 }
4423
4424 static void rtl_pll_power_up(struct rtl8169_private *tp)
4425 {
4426         rtl_generic_op(tp, tp->pll_power_ops.up);
4427 }
4428
4429 static void rtl_init_pll_power_ops(struct rtl8169_private *tp)
4430 {
4431         struct pll_power_ops *ops = &tp->pll_power_ops;
4432
4433         switch (tp->mac_version) {
4434         case RTL_GIGA_MAC_VER_07:
4435         case RTL_GIGA_MAC_VER_08:
4436         case RTL_GIGA_MAC_VER_09:
4437         case RTL_GIGA_MAC_VER_10:
4438         case RTL_GIGA_MAC_VER_16:
4439         case RTL_GIGA_MAC_VER_29:
4440         case RTL_GIGA_MAC_VER_30:
4441         case RTL_GIGA_MAC_VER_37:
4442         case RTL_GIGA_MAC_VER_39:
4443         case RTL_GIGA_MAC_VER_43:
4444         case RTL_GIGA_MAC_VER_47:
4445         case RTL_GIGA_MAC_VER_48:
4446                 ops->down       = r810x_pll_power_down;
4447                 ops->up         = r810x_pll_power_up;
4448                 break;
4449
4450         case RTL_GIGA_MAC_VER_11:
4451         case RTL_GIGA_MAC_VER_12:
4452         case RTL_GIGA_MAC_VER_17:
4453         case RTL_GIGA_MAC_VER_18:
4454         case RTL_GIGA_MAC_VER_19:
4455         case RTL_GIGA_MAC_VER_20:
4456         case RTL_GIGA_MAC_VER_21:
4457         case RTL_GIGA_MAC_VER_22:
4458         case RTL_GIGA_MAC_VER_23:
4459         case RTL_GIGA_MAC_VER_24:
4460         case RTL_GIGA_MAC_VER_25:
4461         case RTL_GIGA_MAC_VER_26:
4462         case RTL_GIGA_MAC_VER_27:
4463         case RTL_GIGA_MAC_VER_28:
4464         case RTL_GIGA_MAC_VER_31:
4465         case RTL_GIGA_MAC_VER_32:
4466         case RTL_GIGA_MAC_VER_33:
4467         case RTL_GIGA_MAC_VER_34:
4468         case RTL_GIGA_MAC_VER_35:
4469         case RTL_GIGA_MAC_VER_36:
4470         case RTL_GIGA_MAC_VER_38:
4471         case RTL_GIGA_MAC_VER_40:
4472         case RTL_GIGA_MAC_VER_41:
4473         case RTL_GIGA_MAC_VER_42:
4474         case RTL_GIGA_MAC_VER_44:
4475         case RTL_GIGA_MAC_VER_45:
4476         case RTL_GIGA_MAC_VER_46:
4477                 ops->down       = r8168_pll_power_down;
4478                 ops->up         = r8168_pll_power_up;
4479                 break;
4480
4481         default:
4482                 ops->down       = NULL;
4483                 ops->up         = NULL;
4484                 break;
4485         }
4486 }
4487
4488 static void rtl_init_rxcfg(struct rtl8169_private *tp)
4489 {
4490         void __iomem *ioaddr = tp->mmio_addr;
4491
4492         switch (tp->mac_version) {
4493         case RTL_GIGA_MAC_VER_01:
4494         case RTL_GIGA_MAC_VER_02:
4495         case RTL_GIGA_MAC_VER_03:
4496         case RTL_GIGA_MAC_VER_04:
4497         case RTL_GIGA_MAC_VER_05:
4498         case RTL_GIGA_MAC_VER_06:
4499         case RTL_GIGA_MAC_VER_10:
4500         case RTL_GIGA_MAC_VER_11:
4501         case RTL_GIGA_MAC_VER_12:
4502         case RTL_GIGA_MAC_VER_13:
4503         case RTL_GIGA_MAC_VER_14:
4504         case RTL_GIGA_MAC_VER_15:
4505         case RTL_GIGA_MAC_VER_16:
4506         case RTL_GIGA_MAC_VER_17:
4507                 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4508                 break;
4509         case RTL_GIGA_MAC_VER_18:
4510         case RTL_GIGA_MAC_VER_19:
4511         case RTL_GIGA_MAC_VER_20:
4512         case RTL_GIGA_MAC_VER_21:
4513         case RTL_GIGA_MAC_VER_22:
4514         case RTL_GIGA_MAC_VER_23:
4515         case RTL_GIGA_MAC_VER_24:
4516         case RTL_GIGA_MAC_VER_34:
4517         case RTL_GIGA_MAC_VER_35:
4518                 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4519                 break;
4520         case RTL_GIGA_MAC_VER_40:
4521                 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
4522                 break;
4523         case RTL_GIGA_MAC_VER_41:
4524         case RTL_GIGA_MAC_VER_42:
4525         case RTL_GIGA_MAC_VER_43:
4526         case RTL_GIGA_MAC_VER_44:
4527         case RTL_GIGA_MAC_VER_45:
4528         case RTL_GIGA_MAC_VER_46:
4529         case RTL_GIGA_MAC_VER_47:
4530         case RTL_GIGA_MAC_VER_48:
4531                 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST | RX_EARLY_OFF);
4532                 break;
4533         default:
4534                 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
4535                 break;
4536         }
4537 }
4538
4539 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4540 {
4541         tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
4542 }
4543
4544 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4545 {
4546         void __iomem *ioaddr = tp->mmio_addr;
4547
4548         RTL_W8(Cfg9346, Cfg9346_Unlock);
4549         rtl_generic_op(tp, tp->jumbo_ops.enable);
4550         RTL_W8(Cfg9346, Cfg9346_Lock);
4551 }
4552
4553 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4554 {
4555         void __iomem *ioaddr = tp->mmio_addr;
4556
4557         RTL_W8(Cfg9346, Cfg9346_Unlock);
4558         rtl_generic_op(tp, tp->jumbo_ops.disable);
4559         RTL_W8(Cfg9346, Cfg9346_Lock);
4560 }
4561
4562 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4563 {
4564         void __iomem *ioaddr = tp->mmio_addr;
4565
4566         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4567         RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
4568         rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
4569 }
4570
4571 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4572 {
4573         void __iomem *ioaddr = tp->mmio_addr;
4574
4575         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4576         RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
4577         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
4578 }
4579
4580 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4581 {
4582         void __iomem *ioaddr = tp->mmio_addr;
4583
4584         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4585 }
4586
4587 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4588 {
4589         void __iomem *ioaddr = tp->mmio_addr;
4590
4591         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4592 }
4593
4594 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4595 {
4596         void __iomem *ioaddr = tp->mmio_addr;
4597
4598         RTL_W8(MaxTxPacketSize, 0x3f);
4599         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4600         RTL_W8(Config4, RTL_R8(Config4) | 0x01);
4601         rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
4602 }
4603
4604 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4605 {
4606         void __iomem *ioaddr = tp->mmio_addr;
4607
4608         RTL_W8(MaxTxPacketSize, 0x0c);
4609         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4610         RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
4611         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
4612 }
4613
4614 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4615 {
4616         rtl_tx_performance_tweak(tp->pci_dev,
4617                 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4618 }
4619
4620 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4621 {
4622         rtl_tx_performance_tweak(tp->pci_dev,
4623                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4624 }
4625
4626 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4627 {
4628         void __iomem *ioaddr = tp->mmio_addr;
4629
4630         r8168b_0_hw_jumbo_enable(tp);
4631
4632         RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
4633 }
4634
4635 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4636 {
4637         void __iomem *ioaddr = tp->mmio_addr;
4638
4639         r8168b_0_hw_jumbo_disable(tp);
4640
4641         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4642 }
4643
4644 static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
4645 {
4646         struct jumbo_ops *ops = &tp->jumbo_ops;
4647
4648         switch (tp->mac_version) {
4649         case RTL_GIGA_MAC_VER_11:
4650                 ops->disable    = r8168b_0_hw_jumbo_disable;
4651                 ops->enable     = r8168b_0_hw_jumbo_enable;
4652                 break;
4653         case RTL_GIGA_MAC_VER_12:
4654         case RTL_GIGA_MAC_VER_17:
4655                 ops->disable    = r8168b_1_hw_jumbo_disable;
4656                 ops->enable     = r8168b_1_hw_jumbo_enable;
4657                 break;
4658         case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4659         case RTL_GIGA_MAC_VER_19:
4660         case RTL_GIGA_MAC_VER_20:
4661         case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4662         case RTL_GIGA_MAC_VER_22:
4663         case RTL_GIGA_MAC_VER_23:
4664         case RTL_GIGA_MAC_VER_24:
4665         case RTL_GIGA_MAC_VER_25:
4666         case RTL_GIGA_MAC_VER_26:
4667                 ops->disable    = r8168c_hw_jumbo_disable;
4668                 ops->enable     = r8168c_hw_jumbo_enable;
4669                 break;
4670         case RTL_GIGA_MAC_VER_27:
4671         case RTL_GIGA_MAC_VER_28:
4672                 ops->disable    = r8168dp_hw_jumbo_disable;
4673                 ops->enable     = r8168dp_hw_jumbo_enable;
4674                 break;
4675         case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4676         case RTL_GIGA_MAC_VER_32:
4677         case RTL_GIGA_MAC_VER_33:
4678         case RTL_GIGA_MAC_VER_34:
4679                 ops->disable    = r8168e_hw_jumbo_disable;
4680                 ops->enable     = r8168e_hw_jumbo_enable;
4681                 break;
4682
4683         /*
4684          * No action needed for jumbo frames with 8169.
4685          * No jumbo for 810x at all.
4686          */
4687         case RTL_GIGA_MAC_VER_40:
4688         case RTL_GIGA_MAC_VER_41:
4689         case RTL_GIGA_MAC_VER_42:
4690         case RTL_GIGA_MAC_VER_43:
4691         case RTL_GIGA_MAC_VER_44:
4692         case RTL_GIGA_MAC_VER_45:
4693         case RTL_GIGA_MAC_VER_46:
4694         case RTL_GIGA_MAC_VER_47:
4695         case RTL_GIGA_MAC_VER_48:
4696         default:
4697                 ops->disable    = NULL;
4698                 ops->enable     = NULL;
4699                 break;
4700         }
4701 }
4702
4703 DECLARE_RTL_COND(rtl_chipcmd_cond)
4704 {
4705         void __iomem *ioaddr = tp->mmio_addr;
4706
4707         return RTL_R8(ChipCmd) & CmdReset;
4708 }
4709
4710 static void rtl_hw_reset(struct rtl8169_private *tp)
4711 {
4712         void __iomem *ioaddr = tp->mmio_addr;
4713
4714         RTL_W8(ChipCmd, CmdReset);
4715
4716         rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
4717 }
4718
4719 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
4720 {
4721         struct rtl_fw *rtl_fw;
4722         const char *name;
4723         int rc = -ENOMEM;
4724
4725         name = rtl_lookup_firmware_name(tp);
4726         if (!name)
4727                 goto out_no_firmware;
4728
4729         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4730         if (!rtl_fw)
4731                 goto err_warn;
4732
4733         rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
4734         if (rc < 0)
4735                 goto err_free;
4736
4737         rc = rtl_check_firmware(tp, rtl_fw);
4738         if (rc < 0)
4739                 goto err_release_firmware;
4740
4741         tp->rtl_fw = rtl_fw;
4742 out:
4743         return;
4744
4745 err_release_firmware:
4746         release_firmware(rtl_fw->fw);
4747 err_free:
4748         kfree(rtl_fw);
4749 err_warn:
4750         netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4751                    name, rc);
4752 out_no_firmware:
4753         tp->rtl_fw = NULL;
4754         goto out;
4755 }
4756
4757 static void rtl_request_firmware(struct rtl8169_private *tp)
4758 {
4759         if (IS_ERR(tp->rtl_fw))
4760                 rtl_request_uncached_firmware(tp);
4761 }
4762
4763 static void rtl_rx_close(struct rtl8169_private *tp)
4764 {
4765         void __iomem *ioaddr = tp->mmio_addr;
4766
4767         RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4768 }
4769
4770 DECLARE_RTL_COND(rtl_npq_cond)
4771 {
4772         void __iomem *ioaddr = tp->mmio_addr;
4773
4774         return RTL_R8(TxPoll) & NPQ;
4775 }
4776
4777 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4778 {
4779         void __iomem *ioaddr = tp->mmio_addr;
4780
4781         return RTL_R32(TxConfig) & TXCFG_EMPTY;
4782 }
4783
4784 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4785 {
4786         void __iomem *ioaddr = tp->mmio_addr;
4787
4788         /* Disable interrupts */
4789         rtl8169_irq_mask_and_ack(tp);
4790
4791         rtl_rx_close(tp);
4792
4793         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4794             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4795             tp->mac_version == RTL_GIGA_MAC_VER_31) {
4796                 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
4797         } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
4798                    tp->mac_version == RTL_GIGA_MAC_VER_35 ||
4799                    tp->mac_version == RTL_GIGA_MAC_VER_36 ||
4800                    tp->mac_version == RTL_GIGA_MAC_VER_37 ||
4801                    tp->mac_version == RTL_GIGA_MAC_VER_38 ||
4802                    tp->mac_version == RTL_GIGA_MAC_VER_40 ||
4803                    tp->mac_version == RTL_GIGA_MAC_VER_41 ||
4804                    tp->mac_version == RTL_GIGA_MAC_VER_42 ||
4805                    tp->mac_version == RTL_GIGA_MAC_VER_43 ||
4806                    tp->mac_version == RTL_GIGA_MAC_VER_44 ||
4807                    tp->mac_version == RTL_GIGA_MAC_VER_45 ||
4808                    tp->mac_version == RTL_GIGA_MAC_VER_46 ||
4809                    tp->mac_version == RTL_GIGA_MAC_VER_47 ||
4810                    tp->mac_version == RTL_GIGA_MAC_VER_48) {
4811                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4812                 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4813         } else {
4814                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4815                 udelay(100);
4816         }
4817
4818         rtl_hw_reset(tp);
4819 }
4820
4821 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
4822 {
4823         void __iomem *ioaddr = tp->mmio_addr;
4824
4825         /* Set DMA burst size and Interframe Gap Time */
4826         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4827                 (InterFrameGap << TxInterFrameGapShift));
4828 }
4829
4830 static void rtl_hw_start(struct net_device *dev)
4831 {
4832         struct rtl8169_private *tp = netdev_priv(dev);
4833
4834         tp->hw_start(dev);
4835
4836         rtl_irq_enable_all(tp);
4837 }
4838
4839 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4840                                          void __iomem *ioaddr)
4841 {
4842         /*
4843          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4844          * register to be written before TxDescAddrLow to work.
4845          * Switching from MMIO to I/O access fixes the issue as well.
4846          */
4847         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4848         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4849         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4850         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4851 }
4852
4853 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4854 {
4855         u16 cmd;
4856
4857         cmd = RTL_R16(CPlusCmd);
4858         RTL_W16(CPlusCmd, cmd);
4859         return cmd;
4860 }
4861
4862 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
4863 {
4864         /* Low hurts. Let's disable the filtering. */
4865         RTL_W16(RxMaxSize, rx_buf_sz + 1);
4866 }
4867
4868 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4869 {
4870         static const struct rtl_cfg2_info {
4871                 u32 mac_version;
4872                 u32 clk;
4873                 u32 val;
4874         } cfg2_info [] = {
4875                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4876                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4877                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4878                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
4879         };
4880         const struct rtl_cfg2_info *p = cfg2_info;
4881         unsigned int i;
4882         u32 clk;
4883
4884         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
4885         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
4886                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4887                         RTL_W32(0x7c, p->val);
4888                         break;
4889                 }
4890         }
4891 }
4892
4893 static void rtl_set_rx_mode(struct net_device *dev)
4894 {
4895         struct rtl8169_private *tp = netdev_priv(dev);
4896         void __iomem *ioaddr = tp->mmio_addr;
4897         u32 mc_filter[2];       /* Multicast hash filter */
4898         int rx_mode;
4899         u32 tmp = 0;
4900
4901         if (dev->flags & IFF_PROMISC) {
4902                 /* Unconditionally log net taps. */
4903                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4904                 rx_mode =
4905                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4906                     AcceptAllPhys;
4907                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4908         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4909                    (dev->flags & IFF_ALLMULTI)) {
4910                 /* Too many to filter perfectly -- accept all multicasts. */
4911                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4912                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4913         } else {
4914                 struct netdev_hw_addr *ha;
4915
4916                 rx_mode = AcceptBroadcast | AcceptMyPhys;
4917                 mc_filter[1] = mc_filter[0] = 0;
4918                 netdev_for_each_mc_addr(ha, dev) {
4919                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4920                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4921                         rx_mode |= AcceptMulticast;
4922                 }
4923         }
4924
4925         if (dev->features & NETIF_F_RXALL)
4926                 rx_mode |= (AcceptErr | AcceptRunt);
4927
4928         tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4929
4930         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4931                 u32 data = mc_filter[0];
4932
4933                 mc_filter[0] = swab32(mc_filter[1]);
4934                 mc_filter[1] = swab32(data);
4935         }
4936
4937         if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4938                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4939
4940         RTL_W32(MAR0 + 4, mc_filter[1]);
4941         RTL_W32(MAR0 + 0, mc_filter[0]);
4942
4943         RTL_W32(RxConfig, tmp);
4944 }
4945
4946 static void rtl_hw_start_8169(struct net_device *dev)
4947 {
4948         struct rtl8169_private *tp = netdev_priv(dev);
4949         void __iomem *ioaddr = tp->mmio_addr;
4950         struct pci_dev *pdev = tp->pci_dev;
4951
4952         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4953                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4954                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4955         }
4956
4957         RTL_W8(Cfg9346, Cfg9346_Unlock);
4958         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4959             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4960             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4961             tp->mac_version == RTL_GIGA_MAC_VER_04)
4962                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4963
4964         rtl_init_rxcfg(tp);
4965
4966         RTL_W8(EarlyTxThres, NoEarlyTx);
4967
4968         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4969
4970         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4971             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4972             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4973             tp->mac_version == RTL_GIGA_MAC_VER_04)
4974                 rtl_set_rx_tx_config_registers(tp);
4975
4976         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
4977
4978         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4979             tp->mac_version == RTL_GIGA_MAC_VER_03) {
4980                 dprintk("Set MAC Reg C+CR Offset 0xe0. "
4981                         "Bit-3 and bit-14 MUST be 1\n");
4982                 tp->cp_cmd |= (1 << 14);
4983         }
4984
4985         RTL_W16(CPlusCmd, tp->cp_cmd);
4986
4987         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4988
4989         /*
4990          * Undocumented corner. Supposedly:
4991          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4992          */
4993         RTL_W16(IntrMitigate, 0x0000);
4994
4995         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4996
4997         if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4998             tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4999             tp->mac_version != RTL_GIGA_MAC_VER_03 &&
5000             tp->mac_version != RTL_GIGA_MAC_VER_04) {
5001                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5002                 rtl_set_rx_tx_config_registers(tp);
5003         }
5004
5005         RTL_W8(Cfg9346, Cfg9346_Lock);
5006
5007         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
5008         RTL_R8(IntrMask);
5009
5010         RTL_W32(RxMissed, 0);
5011
5012         rtl_set_rx_mode(dev);
5013
5014         /* no early-rx interrupts */
5015         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
5016 }
5017
5018 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
5019 {
5020         if (tp->csi_ops.write)
5021                 tp->csi_ops.write(tp, addr, value);
5022 }
5023
5024 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
5025 {
5026         return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0;
5027 }
5028
5029 static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
5030 {
5031         u32 csi;
5032
5033         csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
5034         rtl_csi_write(tp, 0x070c, csi | bits);
5035 }
5036
5037 static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
5038 {
5039         rtl_csi_access_enable(tp, 0x17000000);
5040 }
5041
5042 static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
5043 {
5044         rtl_csi_access_enable(tp, 0x27000000);
5045 }
5046
5047 DECLARE_RTL_COND(rtl_csiar_cond)
5048 {
5049         void __iomem *ioaddr = tp->mmio_addr;
5050
5051         return RTL_R32(CSIAR) & CSIAR_FLAG;
5052 }
5053
5054 static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value)
5055 {
5056         void __iomem *ioaddr = tp->mmio_addr;
5057
5058         RTL_W32(CSIDR, value);
5059         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5060                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5061
5062         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5063 }
5064
5065 static u32 r8169_csi_read(struct rtl8169_private *tp, int addr)
5066 {
5067         void __iomem *ioaddr = tp->mmio_addr;
5068
5069         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
5070                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5071
5072         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5073                 RTL_R32(CSIDR) : ~0;
5074 }
5075
5076 static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value)
5077 {
5078         void __iomem *ioaddr = tp->mmio_addr;
5079
5080         RTL_W32(CSIDR, value);
5081         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5082                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5083                 CSIAR_FUNC_NIC);
5084
5085         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5086 }
5087
5088 static u32 r8402_csi_read(struct rtl8169_private *tp, int addr)
5089 {
5090         void __iomem *ioaddr = tp->mmio_addr;
5091
5092         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
5093                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5094
5095         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5096                 RTL_R32(CSIDR) : ~0;
5097 }
5098
5099 static void r8411_csi_write(struct rtl8169_private *tp, int addr, int value)
5100 {
5101         void __iomem *ioaddr = tp->mmio_addr;
5102
5103         RTL_W32(CSIDR, value);
5104         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5105                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5106                 CSIAR_FUNC_NIC2);
5107
5108         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5109 }
5110
5111 static u32 r8411_csi_read(struct rtl8169_private *tp, int addr)
5112 {
5113         void __iomem *ioaddr = tp->mmio_addr;
5114
5115         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC2 |
5116                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5117
5118         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5119                 RTL_R32(CSIDR) : ~0;
5120 }
5121
5122 static void rtl_init_csi_ops(struct rtl8169_private *tp)
5123 {
5124         struct csi_ops *ops = &tp->csi_ops;
5125
5126         switch (tp->mac_version) {
5127         case RTL_GIGA_MAC_VER_01:
5128         case RTL_GIGA_MAC_VER_02:
5129         case RTL_GIGA_MAC_VER_03:
5130         case RTL_GIGA_MAC_VER_04:
5131         case RTL_GIGA_MAC_VER_05:
5132         case RTL_GIGA_MAC_VER_06:
5133         case RTL_GIGA_MAC_VER_10:
5134         case RTL_GIGA_MAC_VER_11:
5135         case RTL_GIGA_MAC_VER_12:
5136         case RTL_GIGA_MAC_VER_13:
5137         case RTL_GIGA_MAC_VER_14:
5138         case RTL_GIGA_MAC_VER_15:
5139         case RTL_GIGA_MAC_VER_16:
5140         case RTL_GIGA_MAC_VER_17:
5141                 ops->write      = NULL;
5142                 ops->read       = NULL;
5143                 break;
5144
5145         case RTL_GIGA_MAC_VER_37:
5146         case RTL_GIGA_MAC_VER_38:
5147                 ops->write      = r8402_csi_write;
5148                 ops->read       = r8402_csi_read;
5149                 break;
5150
5151         case RTL_GIGA_MAC_VER_44:
5152                 ops->write      = r8411_csi_write;
5153                 ops->read       = r8411_csi_read;
5154                 break;
5155
5156         default:
5157                 ops->write      = r8169_csi_write;
5158                 ops->read       = r8169_csi_read;
5159                 break;
5160         }
5161 }
5162
5163 struct ephy_info {
5164         unsigned int offset;
5165         u16 mask;
5166         u16 bits;
5167 };
5168
5169 static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
5170                           int len)
5171 {
5172         u16 w;
5173
5174         while (len-- > 0) {
5175                 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
5176                 rtl_ephy_write(tp, e->offset, w);
5177                 e++;
5178         }
5179 }
5180
5181 static void rtl_disable_clock_request(struct pci_dev *pdev)
5182 {
5183         pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
5184                                    PCI_EXP_LNKCTL_CLKREQ_EN);
5185 }
5186
5187 static void rtl_enable_clock_request(struct pci_dev *pdev)
5188 {
5189         pcie_capability_set_word(pdev, PCI_EXP_LNKCTL,
5190                                  PCI_EXP_LNKCTL_CLKREQ_EN);
5191 }
5192
5193 static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
5194 {
5195         void __iomem *ioaddr = tp->mmio_addr;
5196         u8 data;
5197
5198         data = RTL_R8(Config3);
5199
5200         if (enable)
5201                 data |= Rdy_to_L23;
5202         else
5203                 data &= ~Rdy_to_L23;
5204
5205         RTL_W8(Config3, data);
5206 }
5207
5208 #define R8168_CPCMD_QUIRK_MASK (\
5209         EnableBist | \
5210         Mac_dbgo_oe | \
5211         Force_half_dup | \
5212         Force_rxflow_en | \
5213         Force_txflow_en | \
5214         Cxpl_dbg_sel | \
5215         ASF | \
5216         PktCntrDisable | \
5217         Mac_dbgo_sel)
5218
5219 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
5220 {
5221         void __iomem *ioaddr = tp->mmio_addr;
5222         struct pci_dev *pdev = tp->pci_dev;
5223
5224         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5225
5226         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5227
5228         if (tp->dev->mtu <= ETH_DATA_LEN) {
5229                 rtl_tx_performance_tweak(pdev, (0x5 << MAX_READ_REQUEST_SHIFT) |
5230                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
5231         }
5232 }
5233
5234 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
5235 {
5236         void __iomem *ioaddr = tp->mmio_addr;
5237
5238         rtl_hw_start_8168bb(tp);
5239
5240         RTL_W8(MaxTxPacketSize, TxPacketMax);
5241
5242         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
5243 }
5244
5245 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
5246 {
5247         void __iomem *ioaddr = tp->mmio_addr;
5248         struct pci_dev *pdev = tp->pci_dev;
5249
5250         RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
5251
5252         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5253
5254         if (tp->dev->mtu <= ETH_DATA_LEN)
5255                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5256
5257         rtl_disable_clock_request(pdev);
5258
5259         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5260 }
5261
5262 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
5263 {
5264         static const struct ephy_info e_info_8168cp[] = {
5265                 { 0x01, 0,      0x0001 },
5266                 { 0x02, 0x0800, 0x1000 },
5267                 { 0x03, 0,      0x0042 },
5268                 { 0x06, 0x0080, 0x0000 },
5269                 { 0x07, 0,      0x2000 }
5270         };
5271
5272         rtl_csi_access_enable_2(tp);
5273
5274         rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
5275
5276         __rtl_hw_start_8168cp(tp);
5277 }
5278
5279 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
5280 {
5281         void __iomem *ioaddr = tp->mmio_addr;
5282         struct pci_dev *pdev = tp->pci_dev;
5283
5284         rtl_csi_access_enable_2(tp);
5285
5286         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5287
5288         if (tp->dev->mtu <= ETH_DATA_LEN)
5289                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5290
5291         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5292 }
5293
5294 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
5295 {
5296         void __iomem *ioaddr = tp->mmio_addr;
5297         struct pci_dev *pdev = tp->pci_dev;
5298
5299         rtl_csi_access_enable_2(tp);
5300
5301         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5302
5303         /* Magic. */
5304         RTL_W8(DBG_REG, 0x20);
5305
5306         RTL_W8(MaxTxPacketSize, TxPacketMax);
5307
5308         if (tp->dev->mtu <= ETH_DATA_LEN)
5309                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5310
5311         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5312 }
5313
5314 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
5315 {
5316         void __iomem *ioaddr = tp->mmio_addr;
5317         static const struct ephy_info e_info_8168c_1[] = {
5318                 { 0x02, 0x0800, 0x1000 },
5319                 { 0x03, 0,      0x0002 },
5320                 { 0x06, 0x0080, 0x0000 }
5321         };
5322
5323         rtl_csi_access_enable_2(tp);
5324
5325         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
5326
5327         rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
5328
5329         __rtl_hw_start_8168cp(tp);
5330 }
5331
5332 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
5333 {
5334         static const struct ephy_info e_info_8168c_2[] = {
5335                 { 0x01, 0,      0x0001 },
5336                 { 0x03, 0x0400, 0x0220 }
5337         };
5338
5339         rtl_csi_access_enable_2(tp);
5340
5341         rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
5342
5343         __rtl_hw_start_8168cp(tp);
5344 }
5345
5346 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
5347 {
5348         rtl_hw_start_8168c_2(tp);
5349 }
5350
5351 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
5352 {
5353         rtl_csi_access_enable_2(tp);
5354
5355         __rtl_hw_start_8168cp(tp);
5356 }
5357
5358 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5359 {
5360         void __iomem *ioaddr = tp->mmio_addr;
5361         struct pci_dev *pdev = tp->pci_dev;
5362
5363         rtl_csi_access_enable_2(tp);
5364
5365         rtl_disable_clock_request(pdev);
5366
5367         RTL_W8(MaxTxPacketSize, TxPacketMax);
5368
5369         if (tp->dev->mtu <= ETH_DATA_LEN)
5370                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5371
5372         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5373 }
5374
5375 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
5376 {
5377         void __iomem *ioaddr = tp->mmio_addr;
5378         struct pci_dev *pdev = tp->pci_dev;
5379
5380         rtl_csi_access_enable_1(tp);
5381
5382         if (tp->dev->mtu <= ETH_DATA_LEN)
5383                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5384
5385         RTL_W8(MaxTxPacketSize, TxPacketMax);
5386
5387         rtl_disable_clock_request(pdev);
5388 }
5389
5390 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
5391 {
5392         void __iomem *ioaddr = tp->mmio_addr;
5393         struct pci_dev *pdev = tp->pci_dev;
5394         static const struct ephy_info e_info_8168d_4[] = {
5395                 { 0x0b, ~0,     0x48 },
5396                 { 0x19, 0x20,   0x50 },
5397                 { 0x0c, ~0,     0x20 }
5398         };
5399         int i;
5400
5401         rtl_csi_access_enable_1(tp);
5402
5403         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5404
5405         RTL_W8(MaxTxPacketSize, TxPacketMax);
5406
5407         for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
5408                 const struct ephy_info *e = e_info_8168d_4 + i;
5409                 u16 w;
5410
5411                 w = rtl_ephy_read(tp, e->offset);
5412                 rtl_ephy_write(tp, 0x03, (w & e->mask) | e->bits);
5413         }
5414
5415         rtl_enable_clock_request(pdev);
5416 }
5417
5418 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
5419 {
5420         void __iomem *ioaddr = tp->mmio_addr;
5421         struct pci_dev *pdev = tp->pci_dev;
5422         static const struct ephy_info e_info_8168e_1[] = {
5423                 { 0x00, 0x0200, 0x0100 },
5424                 { 0x00, 0x0000, 0x0004 },
5425                 { 0x06, 0x0002, 0x0001 },
5426                 { 0x06, 0x0000, 0x0030 },
5427                 { 0x07, 0x0000, 0x2000 },
5428                 { 0x00, 0x0000, 0x0020 },
5429                 { 0x03, 0x5800, 0x2000 },
5430                 { 0x03, 0x0000, 0x0001 },
5431                 { 0x01, 0x0800, 0x1000 },
5432                 { 0x07, 0x0000, 0x4000 },
5433                 { 0x1e, 0x0000, 0x2000 },
5434                 { 0x19, 0xffff, 0xfe6c },
5435                 { 0x0a, 0x0000, 0x0040 }
5436         };
5437
5438         rtl_csi_access_enable_2(tp);
5439
5440         rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
5441
5442         if (tp->dev->mtu <= ETH_DATA_LEN)
5443                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5444
5445         RTL_W8(MaxTxPacketSize, TxPacketMax);
5446
5447         rtl_disable_clock_request(pdev);
5448
5449         /* Reset tx FIFO pointer */
5450         RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
5451         RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
5452
5453         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5454 }
5455
5456 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
5457 {
5458         void __iomem *ioaddr = tp->mmio_addr;
5459         struct pci_dev *pdev = tp->pci_dev;
5460         static const struct ephy_info e_info_8168e_2[] = {
5461                 { 0x09, 0x0000, 0x0080 },
5462                 { 0x19, 0x0000, 0x0224 }
5463         };
5464
5465         rtl_csi_access_enable_1(tp);
5466
5467         rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
5468
5469         if (tp->dev->mtu <= ETH_DATA_LEN)
5470                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5471
5472         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5473         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5474         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5475         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5476         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5477         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
5478         rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5479         rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5480
5481         RTL_W8(MaxTxPacketSize, EarlySize);
5482
5483         rtl_disable_clock_request(pdev);
5484
5485         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5486         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5487
5488         /* Adjust EEE LED frequency */
5489         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5490
5491         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5492         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5493         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5494 }
5495
5496 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
5497 {
5498         void __iomem *ioaddr = tp->mmio_addr;
5499         struct pci_dev *pdev = tp->pci_dev;
5500
5501         rtl_csi_access_enable_2(tp);
5502
5503         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5504
5505         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5506         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5507         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5508         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5509         rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5510         rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5511         rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5512         rtl_w1w0_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5513         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5514         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
5515
5516         RTL_W8(MaxTxPacketSize, EarlySize);
5517
5518         rtl_disable_clock_request(pdev);
5519
5520         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5521         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5522         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5523         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5524         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5525 }
5526
5527 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5528 {
5529         void __iomem *ioaddr = tp->mmio_addr;
5530         static const struct ephy_info e_info_8168f_1[] = {
5531                 { 0x06, 0x00c0, 0x0020 },
5532                 { 0x08, 0x0001, 0x0002 },
5533                 { 0x09, 0x0000, 0x0080 },
5534                 { 0x19, 0x0000, 0x0224 }
5535         };
5536
5537         rtl_hw_start_8168f(tp);
5538
5539         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5540
5541         rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5542
5543         /* Adjust EEE LED frequency */
5544         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5545 }
5546
5547 static void rtl_hw_start_8411(struct rtl8169_private *tp)
5548 {
5549         static const struct ephy_info e_info_8168f_1[] = {
5550                 { 0x06, 0x00c0, 0x0020 },
5551                 { 0x0f, 0xffff, 0x5200 },
5552                 { 0x1e, 0x0000, 0x4000 },
5553                 { 0x19, 0x0000, 0x0224 }
5554         };
5555
5556         rtl_hw_start_8168f(tp);
5557         rtl_pcie_state_l2l3_enable(tp, false);
5558
5559         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5560
5561         rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
5562 }
5563
5564 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5565 {
5566         void __iomem *ioaddr = tp->mmio_addr;
5567         struct pci_dev *pdev = tp->pci_dev;
5568
5569         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5570
5571         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5572         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5573         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5574         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5575
5576         rtl_csi_access_enable_1(tp);
5577
5578         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5579
5580         rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5581         rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5582         rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
5583
5584         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5585         RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
5586         RTL_W8(MaxTxPacketSize, EarlySize);
5587
5588         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5589         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5590
5591         /* Adjust EEE LED frequency */
5592         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5593
5594         rtl_w1w0_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5595         rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
5596
5597         rtl_pcie_state_l2l3_enable(tp, false);
5598 }
5599
5600 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
5601 {
5602         void __iomem *ioaddr = tp->mmio_addr;
5603         static const struct ephy_info e_info_8168g_2[] = {
5604                 { 0x00, 0x0000, 0x0008 },
5605                 { 0x0c, 0x3df0, 0x0200 },
5606                 { 0x19, 0xffff, 0xfc00 },
5607                 { 0x1e, 0xffff, 0x20eb }
5608         };
5609
5610         rtl_hw_start_8168g_1(tp);
5611
5612         /* disable aspm and clock request before access ephy */
5613         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
5614         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
5615         rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
5616 }
5617
5618 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
5619 {
5620         void __iomem *ioaddr = tp->mmio_addr;
5621         static const struct ephy_info e_info_8411_2[] = {
5622                 { 0x00, 0x0000, 0x0008 },
5623                 { 0x0c, 0x3df0, 0x0200 },
5624                 { 0x0f, 0xffff, 0x5200 },
5625                 { 0x19, 0x0020, 0x0000 },
5626                 { 0x1e, 0x0000, 0x2000 }
5627         };
5628
5629         rtl_hw_start_8168g_1(tp);
5630
5631         /* disable aspm and clock request before access ephy */
5632         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
5633         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
5634         rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
5635 }
5636
5637 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
5638 {
5639         void __iomem *ioaddr = tp->mmio_addr;
5640         struct pci_dev *pdev = tp->pci_dev;
5641         u16 rg_saw_cnt;
5642         u32 data;
5643         static const struct ephy_info e_info_8168h_1[] = {
5644                 { 0x1e, 0x0800, 0x0001 },
5645                 { 0x1d, 0x0000, 0x0800 },
5646                 { 0x05, 0xffff, 0x2089 },
5647                 { 0x06, 0xffff, 0x5881 },
5648                 { 0x04, 0xffff, 0x154a },
5649                 { 0x01, 0xffff, 0x068b }
5650         };
5651
5652         /* disable aspm and clock request before access ephy */
5653         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
5654         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
5655         rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
5656
5657         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5658
5659         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
5660         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5661         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5662         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5663
5664         rtl_csi_access_enable_1(tp);
5665
5666         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5667
5668         rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5669         rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5670
5671         rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
5672
5673         rtl_w1w0_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
5674
5675         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
5676
5677         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5678         RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
5679         RTL_W8(MaxTxPacketSize, EarlySize);
5680
5681         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5682         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5683
5684         /* Adjust EEE LED frequency */
5685         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5686
5687         RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
5688         RTL_W8(DLLPR, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
5689
5690         RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN);
5691
5692         rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
5693
5694         rtl_pcie_state_l2l3_enable(tp, false);
5695
5696         rtl_writephy(tp, 0x1f, 0x0c42);
5697         rg_saw_cnt = rtl_readphy(tp, 0x13);
5698         rtl_writephy(tp, 0x1f, 0x0000);
5699         if (rg_saw_cnt > 0) {
5700                 u16 sw_cnt_1ms_ini;
5701
5702                 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
5703                 sw_cnt_1ms_ini &= 0x0fff;
5704                 data = r8168_mac_ocp_read(tp, 0xd412);
5705                 data &= 0x0fff;
5706                 data |= sw_cnt_1ms_ini;
5707                 r8168_mac_ocp_write(tp, 0xd412, data);
5708         }
5709
5710         data = r8168_mac_ocp_read(tp, 0xe056);
5711         data &= 0xf0;
5712         data |= 0x07;
5713         r8168_mac_ocp_write(tp, 0xe056, data);
5714
5715         data = r8168_mac_ocp_read(tp, 0xe052);
5716         data &= 0x8008;
5717         data |= 0x6000;
5718         r8168_mac_ocp_write(tp, 0xe052, data);
5719
5720         data = r8168_mac_ocp_read(tp, 0xe0d6);
5721         data &= 0x01ff;
5722         data |= 0x017f;
5723         r8168_mac_ocp_write(tp, 0xe0d6, data);
5724
5725         data = r8168_mac_ocp_read(tp, 0xd420);
5726         data &= 0x0fff;
5727         data |= 0x047f;
5728         r8168_mac_ocp_write(tp, 0xd420, data);
5729
5730         r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
5731         r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
5732         r8168_mac_ocp_write(tp, 0xc094, 0x0000);
5733         r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
5734 }
5735
5736 static void rtl_hw_start_8168(struct net_device *dev)
5737 {
5738         struct rtl8169_private *tp = netdev_priv(dev);
5739         void __iomem *ioaddr = tp->mmio_addr;
5740
5741         RTL_W8(Cfg9346, Cfg9346_Unlock);
5742
5743         RTL_W8(MaxTxPacketSize, TxPacketMax);
5744
5745         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
5746
5747         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
5748
5749         RTL_W16(CPlusCmd, tp->cp_cmd);
5750
5751         RTL_W16(IntrMitigate, 0x5151);
5752
5753         /* Work around for RxFIFO overflow. */
5754         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
5755                 tp->event_slow |= RxFIFOOver | PCSTimeout;
5756                 tp->event_slow &= ~RxOverflow;
5757         }
5758
5759         rtl_set_rx_tx_desc_registers(tp, ioaddr);
5760
5761         rtl_set_rx_tx_config_registers(tp);
5762
5763         RTL_R8(IntrMask);
5764
5765         switch (tp->mac_version) {
5766         case RTL_GIGA_MAC_VER_11:
5767                 rtl_hw_start_8168bb(tp);
5768                 break;
5769
5770         case RTL_GIGA_MAC_VER_12:
5771         case RTL_GIGA_MAC_VER_17:
5772                 rtl_hw_start_8168bef(tp);
5773                 break;
5774
5775         case RTL_GIGA_MAC_VER_18:
5776                 rtl_hw_start_8168cp_1(tp);
5777                 break;
5778
5779         case RTL_GIGA_MAC_VER_19:
5780                 rtl_hw_start_8168c_1(tp);
5781                 break;
5782
5783         case RTL_GIGA_MAC_VER_20:
5784                 rtl_hw_start_8168c_2(tp);
5785                 break;
5786
5787         case RTL_GIGA_MAC_VER_21:
5788                 rtl_hw_start_8168c_3(tp);
5789                 break;
5790
5791         case RTL_GIGA_MAC_VER_22:
5792                 rtl_hw_start_8168c_4(tp);
5793                 break;
5794
5795         case RTL_GIGA_MAC_VER_23:
5796                 rtl_hw_start_8168cp_2(tp);
5797                 break;
5798
5799         case RTL_GIGA_MAC_VER_24:
5800                 rtl_hw_start_8168cp_3(tp);
5801                 break;
5802
5803         case RTL_GIGA_MAC_VER_25:
5804         case RTL_GIGA_MAC_VER_26:
5805         case RTL_GIGA_MAC_VER_27:
5806                 rtl_hw_start_8168d(tp);
5807                 break;
5808
5809         case RTL_GIGA_MAC_VER_28:
5810                 rtl_hw_start_8168d_4(tp);
5811                 break;
5812
5813         case RTL_GIGA_MAC_VER_31:
5814                 rtl_hw_start_8168dp(tp);
5815                 break;
5816
5817         case RTL_GIGA_MAC_VER_32:
5818         case RTL_GIGA_MAC_VER_33:
5819                 rtl_hw_start_8168e_1(tp);
5820                 break;
5821         case RTL_GIGA_MAC_VER_34:
5822                 rtl_hw_start_8168e_2(tp);
5823                 break;
5824
5825         case RTL_GIGA_MAC_VER_35:
5826         case RTL_GIGA_MAC_VER_36:
5827                 rtl_hw_start_8168f_1(tp);
5828                 break;
5829
5830         case RTL_GIGA_MAC_VER_38:
5831                 rtl_hw_start_8411(tp);
5832                 break;
5833
5834         case RTL_GIGA_MAC_VER_40:
5835         case RTL_GIGA_MAC_VER_41:
5836                 rtl_hw_start_8168g_1(tp);
5837                 break;
5838         case RTL_GIGA_MAC_VER_42:
5839                 rtl_hw_start_8168g_2(tp);
5840                 break;
5841
5842         case RTL_GIGA_MAC_VER_44:
5843                 rtl_hw_start_8411_2(tp);
5844                 break;
5845
5846         case RTL_GIGA_MAC_VER_45:
5847         case RTL_GIGA_MAC_VER_46:
5848                 rtl_hw_start_8168h_1(tp);
5849                 break;
5850
5851         default:
5852                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
5853                         dev->name, tp->mac_version);
5854                 break;
5855         }
5856
5857         RTL_W8(Cfg9346, Cfg9346_Lock);
5858
5859         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5860
5861         rtl_set_rx_mode(dev);
5862
5863         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
5864 }
5865
5866 #define R810X_CPCMD_QUIRK_MASK (\
5867         EnableBist | \
5868         Mac_dbgo_oe | \
5869         Force_half_dup | \
5870         Force_rxflow_en | \
5871         Force_txflow_en | \
5872         Cxpl_dbg_sel | \
5873         ASF | \
5874         PktCntrDisable | \
5875         Mac_dbgo_sel)
5876
5877 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
5878 {
5879         void __iomem *ioaddr = tp->mmio_addr;
5880         struct pci_dev *pdev = tp->pci_dev;
5881         static const struct ephy_info e_info_8102e_1[] = {
5882                 { 0x01, 0, 0x6e65 },
5883                 { 0x02, 0, 0x091f },
5884                 { 0x03, 0, 0xc2f9 },
5885                 { 0x06, 0, 0xafb5 },
5886                 { 0x07, 0, 0x0e00 },
5887                 { 0x19, 0, 0xec80 },
5888                 { 0x01, 0, 0x2e65 },
5889                 { 0x01, 0, 0x6e65 }
5890         };
5891         u8 cfg1;
5892
5893         rtl_csi_access_enable_2(tp);
5894
5895         RTL_W8(DBG_REG, FIX_NAK_1);
5896
5897         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5898
5899         RTL_W8(Config1,
5900                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5901         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5902
5903         cfg1 = RTL_R8(Config1);
5904         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5905                 RTL_W8(Config1, cfg1 & ~LEDS0);
5906
5907         rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
5908 }
5909
5910 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
5911 {
5912         void __iomem *ioaddr = tp->mmio_addr;
5913         struct pci_dev *pdev = tp->pci_dev;
5914
5915         rtl_csi_access_enable_2(tp);
5916
5917         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5918
5919         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
5920         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5921 }
5922
5923 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
5924 {
5925         rtl_hw_start_8102e_2(tp);
5926
5927         rtl_ephy_write(tp, 0x03, 0xc2f9);
5928 }
5929
5930 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5931 {
5932         void __iomem *ioaddr = tp->mmio_addr;
5933         static const struct ephy_info e_info_8105e_1[] = {
5934                 { 0x07, 0, 0x4000 },
5935                 { 0x19, 0, 0x0200 },
5936                 { 0x19, 0, 0x0020 },
5937                 { 0x1e, 0, 0x2000 },
5938                 { 0x03, 0, 0x0001 },
5939                 { 0x19, 0, 0x0100 },
5940                 { 0x19, 0, 0x0004 },
5941                 { 0x0a, 0, 0x0020 }
5942         };
5943
5944         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5945         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5946
5947         /* Disable Early Tally Counter */
5948         RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
5949
5950         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
5951         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5952
5953         rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
5954
5955         rtl_pcie_state_l2l3_enable(tp, false);
5956 }
5957
5958 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5959 {
5960         rtl_hw_start_8105e_1(tp);
5961         rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5962 }
5963
5964 static void rtl_hw_start_8402(struct rtl8169_private *tp)
5965 {
5966         void __iomem *ioaddr = tp->mmio_addr;
5967         static const struct ephy_info e_info_8402[] = {
5968                 { 0x19, 0xffff, 0xff64 },
5969                 { 0x1e, 0, 0x4000 }
5970         };
5971
5972         rtl_csi_access_enable_2(tp);
5973
5974         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5975         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5976
5977         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5978         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5979
5980         rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
5981
5982         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
5983
5984         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
5985         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
5986         rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5987         rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5988         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5989         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5990         rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
5991
5992         rtl_pcie_state_l2l3_enable(tp, false);
5993 }
5994
5995 static void rtl_hw_start_8106(struct rtl8169_private *tp)
5996 {
5997         void __iomem *ioaddr = tp->mmio_addr;
5998
5999         /* Force LAN exit from ASPM if Rx/Tx are not idle */
6000         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6001
6002         RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
6003         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
6004         RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6005
6006         rtl_pcie_state_l2l3_enable(tp, false);
6007 }
6008
6009 static void rtl_hw_start_8101(struct net_device *dev)
6010 {
6011         struct rtl8169_private *tp = netdev_priv(dev);
6012         void __iomem *ioaddr = tp->mmio_addr;
6013         struct pci_dev *pdev = tp->pci_dev;
6014
6015         if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
6016                 tp->event_slow &= ~RxFIFOOver;
6017
6018         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
6019             tp->mac_version == RTL_GIGA_MAC_VER_16)
6020                 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL,
6021                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
6022
6023         RTL_W8(Cfg9346, Cfg9346_Unlock);
6024
6025         RTL_W8(MaxTxPacketSize, TxPacketMax);
6026
6027         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
6028
6029         tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
6030         RTL_W16(CPlusCmd, tp->cp_cmd);
6031
6032         rtl_set_rx_tx_desc_registers(tp, ioaddr);
6033
6034         rtl_set_rx_tx_config_registers(tp);
6035
6036         switch (tp->mac_version) {
6037         case RTL_GIGA_MAC_VER_07:
6038                 rtl_hw_start_8102e_1(tp);
6039                 break;
6040
6041         case RTL_GIGA_MAC_VER_08:
6042                 rtl_hw_start_8102e_3(tp);
6043                 break;
6044
6045         case RTL_GIGA_MAC_VER_09:
6046                 rtl_hw_start_8102e_2(tp);
6047                 break;
6048
6049         case RTL_GIGA_MAC_VER_29:
6050                 rtl_hw_start_8105e_1(tp);
6051                 break;
6052         case RTL_GIGA_MAC_VER_30:
6053                 rtl_hw_start_8105e_2(tp);
6054                 break;
6055
6056         case RTL_GIGA_MAC_VER_37:
6057                 rtl_hw_start_8402(tp);
6058                 break;
6059
6060         case RTL_GIGA_MAC_VER_39:
6061                 rtl_hw_start_8106(tp);
6062                 break;
6063         case RTL_GIGA_MAC_VER_43:
6064                 rtl_hw_start_8168g_2(tp);
6065                 break;
6066         case RTL_GIGA_MAC_VER_47:
6067         case RTL_GIGA_MAC_VER_48:
6068                 rtl_hw_start_8168h_1(tp);
6069                 break;
6070         }
6071
6072         RTL_W8(Cfg9346, Cfg9346_Lock);
6073
6074         RTL_W16(IntrMitigate, 0x0000);
6075
6076         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
6077
6078         rtl_set_rx_mode(dev);
6079
6080         RTL_R8(IntrMask);
6081
6082         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6083 }
6084
6085 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
6086 {
6087         struct rtl8169_private *tp = netdev_priv(dev);
6088
6089         if (new_mtu < ETH_ZLEN ||
6090             new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
6091                 return -EINVAL;
6092
6093         if (new_mtu > ETH_DATA_LEN)
6094                 rtl_hw_jumbo_enable(tp);
6095         else
6096                 rtl_hw_jumbo_disable(tp);
6097
6098         dev->mtu = new_mtu;
6099         netdev_update_features(dev);
6100
6101         return 0;
6102 }
6103
6104 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
6105 {
6106         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
6107         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
6108 }
6109
6110 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
6111                                      void **data_buff, struct RxDesc *desc)
6112 {
6113         dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
6114                          DMA_FROM_DEVICE);
6115
6116         kfree(*data_buff);
6117         *data_buff = NULL;
6118         rtl8169_make_unusable_by_asic(desc);
6119 }
6120
6121 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
6122 {
6123         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
6124
6125         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
6126 }
6127
6128 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
6129                                        u32 rx_buf_sz)
6130 {
6131         desc->addr = cpu_to_le64(mapping);
6132         wmb();
6133         rtl8169_mark_to_asic(desc, rx_buf_sz);
6134 }
6135
6136 static inline void *rtl8169_align(void *data)
6137 {
6138         return (void *)ALIGN((long)data, 16);
6139 }
6140
6141 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
6142                                              struct RxDesc *desc)
6143 {
6144         void *data;
6145         dma_addr_t mapping;
6146         struct device *d = &tp->pci_dev->dev;
6147         struct net_device *dev = tp->dev;
6148         int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
6149
6150         data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
6151         if (!data)
6152                 return NULL;
6153
6154         if (rtl8169_align(data) != data) {
6155                 kfree(data);
6156                 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
6157                 if (!data)
6158                         return NULL;
6159         }
6160
6161         mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
6162                                  DMA_FROM_DEVICE);
6163         if (unlikely(dma_mapping_error(d, mapping))) {
6164                 if (net_ratelimit())
6165                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
6166                 goto err_out;
6167         }
6168
6169         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6170         return data;
6171
6172 err_out:
6173         kfree(data);
6174         return NULL;
6175 }
6176
6177 static void rtl8169_rx_clear(struct rtl8169_private *tp)
6178 {
6179         unsigned int i;
6180
6181         for (i = 0; i < NUM_RX_DESC; i++) {
6182                 if (tp->Rx_databuff[i]) {
6183                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
6184                                             tp->RxDescArray + i);
6185                 }
6186         }
6187 }
6188
6189 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
6190 {
6191         desc->opts1 |= cpu_to_le32(RingEnd);
6192 }
6193
6194 static int rtl8169_rx_fill(struct rtl8169_private *tp)
6195 {
6196         unsigned int i;
6197
6198         for (i = 0; i < NUM_RX_DESC; i++) {
6199                 void *data;
6200
6201                 if (tp->Rx_databuff[i])
6202                         continue;
6203
6204                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6205                 if (!data) {
6206                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
6207                         goto err_out;
6208                 }
6209                 tp->Rx_databuff[i] = data;
6210         }
6211
6212         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
6213         return 0;
6214
6215 err_out:
6216         rtl8169_rx_clear(tp);
6217         return -ENOMEM;
6218 }
6219
6220 static int rtl8169_init_ring(struct net_device *dev)
6221 {
6222         struct rtl8169_private *tp = netdev_priv(dev);
6223
6224         rtl8169_init_ring_indexes(tp);
6225
6226         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6227         memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
6228
6229         return rtl8169_rx_fill(tp);
6230 }
6231
6232 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
6233                                  struct TxDesc *desc)
6234 {
6235         unsigned int len = tx_skb->len;
6236
6237         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
6238
6239         desc->opts1 = 0x00;
6240         desc->opts2 = 0x00;
6241         desc->addr = 0x00;
6242         tx_skb->len = 0;
6243 }
6244
6245 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
6246                                    unsigned int n)
6247 {
6248         unsigned int i;
6249
6250         for (i = 0; i < n; i++) {
6251                 unsigned int entry = (start + i) % NUM_TX_DESC;
6252                 struct ring_info *tx_skb = tp->tx_skb + entry;
6253                 unsigned int len = tx_skb->len;
6254
6255                 if (len) {
6256                         struct sk_buff *skb = tx_skb->skb;
6257
6258                         rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
6259                                              tp->TxDescArray + entry);
6260                         if (skb) {
6261                                 tp->dev->stats.tx_dropped++;
6262                                 dev_kfree_skb_any(skb);
6263                                 tx_skb->skb = NULL;
6264                         }
6265                 }
6266         }
6267 }
6268
6269 static void rtl8169_tx_clear(struct rtl8169_private *tp)
6270 {
6271         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
6272         tp->cur_tx = tp->dirty_tx = 0;
6273 }
6274
6275 static void rtl_reset_work(struct rtl8169_private *tp)
6276 {
6277         struct net_device *dev = tp->dev;
6278         int i;
6279
6280         napi_disable(&tp->napi);
6281         netif_stop_queue(dev);
6282         synchronize_sched();
6283
6284         rtl8169_hw_reset(tp);
6285
6286         for (i = 0; i < NUM_RX_DESC; i++)
6287                 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
6288
6289         rtl8169_tx_clear(tp);
6290         rtl8169_init_ring_indexes(tp);
6291
6292         napi_enable(&tp->napi);
6293         rtl_hw_start(dev);
6294         netif_wake_queue(dev);
6295         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
6296 }
6297
6298 static void rtl8169_tx_timeout(struct net_device *dev)
6299 {
6300         struct rtl8169_private *tp = netdev_priv(dev);
6301
6302         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6303 }
6304
6305 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
6306                               u32 *opts)
6307 {
6308         struct skb_shared_info *info = skb_shinfo(skb);
6309         unsigned int cur_frag, entry;
6310         struct TxDesc *uninitialized_var(txd);
6311         struct device *d = &tp->pci_dev->dev;
6312
6313         entry = tp->cur_tx;
6314         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
6315                 const skb_frag_t *frag = info->frags + cur_frag;
6316                 dma_addr_t mapping;
6317                 u32 status, len;
6318                 void *addr;
6319
6320                 entry = (entry + 1) % NUM_TX_DESC;
6321
6322                 txd = tp->TxDescArray + entry;
6323                 len = skb_frag_size(frag);
6324                 addr = skb_frag_address(frag);
6325                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
6326                 if (unlikely(dma_mapping_error(d, mapping))) {
6327                         if (net_ratelimit())
6328                                 netif_err(tp, drv, tp->dev,
6329                                           "Failed to map TX fragments DMA!\n");
6330                         goto err_out;
6331                 }
6332
6333                 /* Anti gcc 2.95.3 bugware (sic) */
6334                 status = opts[0] | len |
6335                         (RingEnd * !((entry + 1) % NUM_TX_DESC));
6336
6337                 txd->opts1 = cpu_to_le32(status);
6338                 txd->opts2 = cpu_to_le32(opts[1]);
6339                 txd->addr = cpu_to_le64(mapping);
6340
6341                 tp->tx_skb[entry].len = len;
6342         }
6343
6344         if (cur_frag) {
6345                 tp->tx_skb[entry].skb = skb;
6346                 txd->opts1 |= cpu_to_le32(LastFrag);
6347         }
6348
6349         return cur_frag;
6350
6351 err_out:
6352         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
6353         return -EIO;
6354 }
6355
6356 static bool rtl_skb_pad(struct sk_buff *skb)
6357 {
6358         if (skb_padto(skb, ETH_ZLEN))
6359                 return false;
6360         skb_put(skb, ETH_ZLEN - skb->len);
6361         return true;
6362 }
6363
6364 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
6365 {
6366         return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
6367 }
6368
6369 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6370                                       struct net_device *dev);
6371 /* r8169_csum_workaround()
6372  * The hw limites the value the transport offset. When the offset is out of the
6373  * range, calculate the checksum by sw.
6374  */
6375 static void r8169_csum_workaround(struct rtl8169_private *tp,
6376                                   struct sk_buff *skb)
6377 {
6378         if (skb_shinfo(skb)->gso_size) {
6379                 netdev_features_t features = tp->dev->features;
6380                 struct sk_buff *segs, *nskb;
6381
6382                 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
6383                 segs = skb_gso_segment(skb, features);
6384                 if (IS_ERR(segs) || !segs)
6385                         goto drop;
6386
6387                 do {
6388                         nskb = segs;
6389                         segs = segs->next;
6390                         nskb->next = NULL;
6391                         rtl8169_start_xmit(nskb, tp->dev);
6392                 } while (segs);
6393
6394                 dev_kfree_skb(skb);
6395         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6396                 if (skb_checksum_help(skb) < 0)
6397                         goto drop;
6398
6399                 rtl8169_start_xmit(skb, tp->dev);
6400         } else {
6401                 struct net_device_stats *stats;
6402
6403 drop:
6404                 stats = &tp->dev->stats;
6405                 stats->tx_dropped++;
6406                 dev_kfree_skb(skb);
6407         }
6408 }
6409
6410 /* msdn_giant_send_check()
6411  * According to the document of microsoft, the TCP Pseudo Header excludes the
6412  * packet length for IPv6 TCP large packets.
6413  */
6414 static int msdn_giant_send_check(struct sk_buff *skb)
6415 {
6416         const struct ipv6hdr *ipv6h;
6417         struct tcphdr *th;
6418         int ret;
6419
6420         ret = skb_cow_head(skb, 0);
6421         if (ret)
6422                 return ret;
6423
6424         ipv6h = ipv6_hdr(skb);
6425         th = tcp_hdr(skb);
6426
6427         th->check = 0;
6428         th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
6429
6430         return ret;
6431 }
6432
6433 static inline __be16 get_protocol(struct sk_buff *skb)
6434 {
6435         __be16 protocol;
6436
6437         if (skb->protocol == htons(ETH_P_8021Q))
6438                 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
6439         else
6440                 protocol = skb->protocol;
6441
6442         return protocol;
6443 }
6444
6445 static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
6446                                 struct sk_buff *skb, u32 *opts)
6447 {
6448         u32 mss = skb_shinfo(skb)->gso_size;
6449
6450         if (mss) {
6451                 opts[0] |= TD_LSO;
6452                 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
6453         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6454                 const struct iphdr *ip = ip_hdr(skb);
6455
6456                 if (ip->protocol == IPPROTO_TCP)
6457                         opts[0] |= TD0_IP_CS | TD0_TCP_CS;
6458                 else if (ip->protocol == IPPROTO_UDP)
6459                         opts[0] |= TD0_IP_CS | TD0_UDP_CS;
6460                 else
6461                         WARN_ON_ONCE(1);
6462         }
6463
6464         return true;
6465 }
6466
6467 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
6468                                 struct sk_buff *skb, u32 *opts)
6469 {
6470         u32 transport_offset = (u32)skb_transport_offset(skb);
6471         u32 mss = skb_shinfo(skb)->gso_size;
6472
6473         if (mss) {
6474                 if (transport_offset > GTTCPHO_MAX) {
6475                         netif_warn(tp, tx_err, tp->dev,
6476                                    "Invalid transport offset 0x%x for TSO\n",
6477                                    transport_offset);
6478                         return false;
6479                 }
6480
6481                 switch (get_protocol(skb)) {
6482                 case htons(ETH_P_IP):
6483                         opts[0] |= TD1_GTSENV4;
6484                         break;
6485
6486                 case htons(ETH_P_IPV6):
6487                         if (msdn_giant_send_check(skb))
6488                                 return false;
6489
6490                         opts[0] |= TD1_GTSENV6;
6491                         break;
6492
6493                 default:
6494                         WARN_ON_ONCE(1);
6495                         break;
6496                 }
6497
6498                 opts[0] |= transport_offset << GTTCPHO_SHIFT;
6499                 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
6500         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6501                 u8 ip_protocol;
6502
6503                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
6504                         return skb_checksum_help(skb) == 0 && rtl_skb_pad(skb);
6505
6506                 if (transport_offset > TCPHO_MAX) {
6507                         netif_warn(tp, tx_err, tp->dev,
6508                                    "Invalid transport offset 0x%x\n",
6509                                    transport_offset);
6510                         return false;
6511                 }
6512
6513                 switch (get_protocol(skb)) {
6514                 case htons(ETH_P_IP):
6515                         opts[1] |= TD1_IPv4_CS;
6516                         ip_protocol = ip_hdr(skb)->protocol;
6517                         break;
6518
6519                 case htons(ETH_P_IPV6):
6520                         opts[1] |= TD1_IPv6_CS;
6521                         ip_protocol = ipv6_hdr(skb)->nexthdr;
6522                         break;
6523
6524                 default:
6525                         ip_protocol = IPPROTO_RAW;
6526                         break;
6527                 }
6528
6529                 if (ip_protocol == IPPROTO_TCP)
6530                         opts[1] |= TD1_TCP_CS;
6531                 else if (ip_protocol == IPPROTO_UDP)
6532                         opts[1] |= TD1_UDP_CS;
6533                 else
6534                         WARN_ON_ONCE(1);
6535
6536                 opts[1] |= transport_offset << TCPHO_SHIFT;
6537         } else {
6538                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
6539                         return rtl_skb_pad(skb);
6540         }
6541
6542         return true;
6543 }
6544
6545 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6546                                       struct net_device *dev)
6547 {
6548         struct rtl8169_private *tp = netdev_priv(dev);
6549         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
6550         struct TxDesc *txd = tp->TxDescArray + entry;
6551         void __iomem *ioaddr = tp->mmio_addr;
6552         struct device *d = &tp->pci_dev->dev;
6553         dma_addr_t mapping;
6554         u32 status, len;
6555         u32 opts[2];
6556         int frags;
6557
6558         if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
6559                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
6560                 goto err_stop_0;
6561         }
6562
6563         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
6564                 goto err_stop_0;
6565
6566         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
6567         opts[0] = DescOwn;
6568
6569         if (!tp->tso_csum(tp, skb, opts)) {
6570                 r8169_csum_workaround(tp, skb);
6571                 return NETDEV_TX_OK;
6572         }
6573
6574         len = skb_headlen(skb);
6575         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
6576         if (unlikely(dma_mapping_error(d, mapping))) {
6577                 if (net_ratelimit())
6578                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
6579                 goto err_dma_0;
6580         }
6581
6582         tp->tx_skb[entry].len = len;
6583         txd->addr = cpu_to_le64(mapping);
6584
6585         frags = rtl8169_xmit_frags(tp, skb, opts);
6586         if (frags < 0)
6587                 goto err_dma_1;
6588         else if (frags)
6589                 opts[0] |= FirstFrag;
6590         else {
6591                 opts[0] |= FirstFrag | LastFrag;
6592                 tp->tx_skb[entry].skb = skb;
6593         }
6594
6595         txd->opts2 = cpu_to_le32(opts[1]);
6596
6597         skb_tx_timestamp(skb);
6598
6599         wmb();
6600
6601         /* Anti gcc 2.95.3 bugware (sic) */
6602         status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
6603         txd->opts1 = cpu_to_le32(status);
6604
6605         tp->cur_tx += frags + 1;
6606
6607         wmb();
6608
6609         RTL_W8(TxPoll, NPQ);
6610
6611         mmiowb();
6612
6613         if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
6614                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
6615                  * not miss a ring update when it notices a stopped queue.
6616                  */
6617                 smp_wmb();
6618                 netif_stop_queue(dev);
6619                 /* Sync with rtl_tx:
6620                  * - publish queue status and cur_tx ring index (write barrier)
6621                  * - refresh dirty_tx ring index (read barrier).
6622                  * May the current thread have a pessimistic view of the ring
6623                  * status and forget to wake up queue, a racing rtl_tx thread
6624                  * can't.
6625                  */
6626                 smp_mb();
6627                 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
6628                         netif_wake_queue(dev);
6629         }
6630
6631         return NETDEV_TX_OK;
6632
6633 err_dma_1:
6634         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
6635 err_dma_0:
6636         dev_kfree_skb_any(skb);
6637         dev->stats.tx_dropped++;
6638         return NETDEV_TX_OK;
6639
6640 err_stop_0:
6641         netif_stop_queue(dev);
6642         dev->stats.tx_dropped++;
6643         return NETDEV_TX_BUSY;
6644 }
6645
6646 static void rtl8169_pcierr_interrupt(struct net_device *dev)
6647 {
6648         struct rtl8169_private *tp = netdev_priv(dev);
6649         struct pci_dev *pdev = tp->pci_dev;
6650         u16 pci_status, pci_cmd;
6651
6652         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
6653         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
6654
6655         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
6656                   pci_cmd, pci_status);
6657
6658         /*
6659          * The recovery sequence below admits a very elaborated explanation:
6660          * - it seems to work;
6661          * - I did not see what else could be done;
6662          * - it makes iop3xx happy.
6663          *
6664          * Feel free to adjust to your needs.
6665          */
6666         if (pdev->broken_parity_status)
6667                 pci_cmd &= ~PCI_COMMAND_PARITY;
6668         else
6669                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
6670
6671         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
6672
6673         pci_write_config_word(pdev, PCI_STATUS,
6674                 pci_status & (PCI_STATUS_DETECTED_PARITY |
6675                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
6676                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
6677
6678         /* The infamous DAC f*ckup only happens at boot time */
6679         if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
6680                 void __iomem *ioaddr = tp->mmio_addr;
6681
6682                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
6683                 tp->cp_cmd &= ~PCIDAC;
6684                 RTL_W16(CPlusCmd, tp->cp_cmd);
6685                 dev->features &= ~NETIF_F_HIGHDMA;
6686         }
6687
6688         rtl8169_hw_reset(tp);
6689
6690         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6691 }
6692
6693 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
6694 {
6695         unsigned int dirty_tx, tx_left;
6696
6697         dirty_tx = tp->dirty_tx;
6698         smp_rmb();
6699         tx_left = tp->cur_tx - dirty_tx;
6700
6701         while (tx_left > 0) {
6702                 unsigned int entry = dirty_tx % NUM_TX_DESC;
6703                 struct ring_info *tx_skb = tp->tx_skb + entry;
6704                 u32 status;
6705
6706                 rmb();
6707                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
6708                 if (status & DescOwn)
6709                         break;
6710
6711                 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
6712                                      tp->TxDescArray + entry);
6713                 if (status & LastFrag) {
6714                         u64_stats_update_begin(&tp->tx_stats.syncp);
6715                         tp->tx_stats.packets++;
6716                         tp->tx_stats.bytes += tx_skb->skb->len;
6717                         u64_stats_update_end(&tp->tx_stats.syncp);
6718                         dev_kfree_skb_any(tx_skb->skb);
6719                         tx_skb->skb = NULL;
6720                 }
6721                 dirty_tx++;
6722                 tx_left--;
6723         }
6724
6725         if (tp->dirty_tx != dirty_tx) {
6726                 tp->dirty_tx = dirty_tx;
6727                 /* Sync with rtl8169_start_xmit:
6728                  * - publish dirty_tx ring index (write barrier)
6729                  * - refresh cur_tx ring index and queue status (read barrier)
6730                  * May the current thread miss the stopped queue condition,
6731                  * a racing xmit thread can only have a right view of the
6732                  * ring status.
6733                  */
6734                 smp_mb();
6735                 if (netif_queue_stopped(dev) &&
6736                     TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
6737                         netif_wake_queue(dev);
6738                 }
6739                 /*
6740                  * 8168 hack: TxPoll requests are lost when the Tx packets are
6741                  * too close. Let's kick an extra TxPoll request when a burst
6742                  * of start_xmit activity is detected (if it is not detected,
6743                  * it is slow enough). -- FR
6744                  */
6745                 if (tp->cur_tx != dirty_tx) {
6746                         void __iomem *ioaddr = tp->mmio_addr;
6747
6748                         RTL_W8(TxPoll, NPQ);
6749                 }
6750         }
6751 }
6752
6753 static inline int rtl8169_fragmented_frame(u32 status)
6754 {
6755         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
6756 }
6757
6758 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
6759 {
6760         u32 status = opts1 & RxProtoMask;
6761
6762         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
6763             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
6764                 skb->ip_summed = CHECKSUM_UNNECESSARY;
6765         else
6766                 skb_checksum_none_assert(skb);
6767 }
6768
6769 static struct sk_buff *rtl8169_try_rx_copy(void *data,
6770                                            struct rtl8169_private *tp,
6771                                            int pkt_size,
6772                                            dma_addr_t addr)
6773 {
6774         struct sk_buff *skb;
6775         struct device *d = &tp->pci_dev->dev;
6776
6777         data = rtl8169_align(data);
6778         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6779         prefetch(data);
6780         skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
6781         if (skb)
6782                 memcpy(skb->data, data, pkt_size);
6783         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6784
6785         return skb;
6786 }
6787
6788 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
6789 {
6790         unsigned int cur_rx, rx_left;
6791         unsigned int count;
6792
6793         cur_rx = tp->cur_rx;
6794
6795         for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
6796                 unsigned int entry = cur_rx % NUM_RX_DESC;
6797                 struct RxDesc *desc = tp->RxDescArray + entry;
6798                 u32 status;
6799
6800                 rmb();
6801                 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
6802
6803                 if (status & DescOwn)
6804                         break;
6805                 if (unlikely(status & RxRES)) {
6806                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6807                                    status);
6808                         dev->stats.rx_errors++;
6809                         if (status & (RxRWT | RxRUNT))
6810                                 dev->stats.rx_length_errors++;
6811                         if (status & RxCRC)
6812                                 dev->stats.rx_crc_errors++;
6813                         if (status & RxFOVF) {
6814                                 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6815                                 dev->stats.rx_fifo_errors++;
6816                         }
6817                         if ((status & (RxRUNT | RxCRC)) &&
6818                             !(status & (RxRWT | RxFOVF)) &&
6819                             (dev->features & NETIF_F_RXALL))
6820                                 goto process_pkt;
6821                 } else {
6822                         struct sk_buff *skb;
6823                         dma_addr_t addr;
6824                         int pkt_size;
6825
6826 process_pkt:
6827                         addr = le64_to_cpu(desc->addr);
6828                         if (likely(!(dev->features & NETIF_F_RXFCS)))
6829                                 pkt_size = (status & 0x00003fff) - 4;
6830                         else
6831                                 pkt_size = status & 0x00003fff;
6832
6833                         /*
6834                          * The driver does not support incoming fragmented
6835                          * frames. They are seen as a symptom of over-mtu
6836                          * sized frames.
6837                          */
6838                         if (unlikely(rtl8169_fragmented_frame(status))) {
6839                                 dev->stats.rx_dropped++;
6840                                 dev->stats.rx_length_errors++;
6841                                 goto release_descriptor;
6842                         }
6843
6844                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6845                                                   tp, pkt_size, addr);
6846                         if (!skb) {
6847                                 dev->stats.rx_dropped++;
6848                                 goto release_descriptor;
6849                         }
6850
6851                         rtl8169_rx_csum(skb, status);
6852                         skb_put(skb, pkt_size);
6853                         skb->protocol = eth_type_trans(skb, dev);
6854
6855                         rtl8169_rx_vlan_tag(desc, skb);
6856
6857                         napi_gro_receive(&tp->napi, skb);
6858
6859                         u64_stats_update_begin(&tp->rx_stats.syncp);
6860                         tp->rx_stats.packets++;
6861                         tp->rx_stats.bytes += pkt_size;
6862                         u64_stats_update_end(&tp->rx_stats.syncp);
6863                 }
6864 release_descriptor:
6865                 desc->opts2 = 0;
6866                 wmb();
6867                 rtl8169_mark_to_asic(desc, rx_buf_sz);
6868         }
6869
6870         count = cur_rx - tp->cur_rx;
6871         tp->cur_rx = cur_rx;
6872
6873         return count;
6874 }
6875
6876 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
6877 {
6878         struct net_device *dev = dev_instance;
6879         struct rtl8169_private *tp = netdev_priv(dev);
6880         int handled = 0;
6881         u16 status;
6882
6883         status = rtl_get_events(tp);
6884         if (status && status != 0xffff) {
6885                 status &= RTL_EVENT_NAPI | tp->event_slow;
6886                 if (status) {
6887                         handled = 1;
6888
6889                         rtl_irq_disable(tp);
6890                         napi_schedule(&tp->napi);
6891                 }
6892         }
6893         return IRQ_RETVAL(handled);
6894 }
6895
6896 /*
6897  * Workqueue context.
6898  */
6899 static void rtl_slow_event_work(struct rtl8169_private *tp)
6900 {
6901         struct net_device *dev = tp->dev;
6902         u16 status;
6903
6904         status = rtl_get_events(tp) & tp->event_slow;
6905         rtl_ack_events(tp, status);
6906
6907         if (unlikely(status & RxFIFOOver)) {
6908                 switch (tp->mac_version) {
6909                 /* Work around for rx fifo overflow */
6910                 case RTL_GIGA_MAC_VER_11:
6911                         netif_stop_queue(dev);
6912                         /* XXX - Hack alert. See rtl_task(). */
6913                         set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
6914                 default:
6915                         break;
6916                 }
6917         }
6918
6919         if (unlikely(status & SYSErr))
6920                 rtl8169_pcierr_interrupt(dev);
6921
6922         if (status & LinkChg)
6923                 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
6924
6925         rtl_irq_enable_all(tp);
6926 }
6927
6928 static void rtl_task(struct work_struct *work)
6929 {
6930         static const struct {
6931                 int bitnr;
6932                 void (*action)(struct rtl8169_private *);
6933         } rtl_work[] = {
6934                 /* XXX - keep rtl_slow_event_work() as first element. */
6935                 { RTL_FLAG_TASK_SLOW_PENDING,   rtl_slow_event_work },
6936                 { RTL_FLAG_TASK_RESET_PENDING,  rtl_reset_work },
6937                 { RTL_FLAG_TASK_PHY_PENDING,    rtl_phy_work }
6938         };
6939         struct rtl8169_private *tp =
6940                 container_of(work, struct rtl8169_private, wk.work);
6941         struct net_device *dev = tp->dev;
6942         int i;
6943
6944         rtl_lock_work(tp);
6945
6946         if (!netif_running(dev) ||
6947             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
6948                 goto out_unlock;
6949
6950         for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6951                 bool pending;
6952
6953                 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
6954                 if (pending)
6955                         rtl_work[i].action(tp);
6956         }
6957
6958 out_unlock:
6959         rtl_unlock_work(tp);
6960 }
6961
6962 static int rtl8169_poll(struct napi_struct *napi, int budget)
6963 {
6964         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6965         struct net_device *dev = tp->dev;
6966         u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
6967         int work_done= 0;
6968         u16 status;
6969
6970         status = rtl_get_events(tp);
6971         rtl_ack_events(tp, status & ~tp->event_slow);
6972
6973         if (status & RTL_EVENT_NAPI_RX)
6974                 work_done = rtl_rx(dev, tp, (u32) budget);
6975
6976         if (status & RTL_EVENT_NAPI_TX)
6977                 rtl_tx(dev, tp);
6978
6979         if (status & tp->event_slow) {
6980                 enable_mask &= ~tp->event_slow;
6981
6982                 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
6983         }
6984
6985         if (work_done < budget) {
6986                 napi_complete(napi);
6987
6988                 rtl_irq_enable(tp, enable_mask);
6989                 mmiowb();
6990         }
6991
6992         return work_done;
6993 }
6994
6995 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
6996 {
6997         struct rtl8169_private *tp = netdev_priv(dev);
6998
6999         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
7000                 return;
7001
7002         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
7003         RTL_W32(RxMissed, 0);
7004 }
7005
7006 static void rtl8169_down(struct net_device *dev)
7007 {
7008         struct rtl8169_private *tp = netdev_priv(dev);
7009         void __iomem *ioaddr = tp->mmio_addr;
7010
7011         del_timer_sync(&tp->timer);
7012
7013         napi_disable(&tp->napi);
7014         netif_stop_queue(dev);
7015
7016         rtl8169_hw_reset(tp);
7017         /*
7018          * At this point device interrupts can not be enabled in any function,
7019          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
7020          * and napi is disabled (rtl8169_poll).
7021          */
7022         rtl8169_rx_missed(dev, ioaddr);
7023
7024         /* Give a racing hard_start_xmit a few cycles to complete. */
7025         synchronize_sched();
7026
7027         rtl8169_tx_clear(tp);
7028
7029         rtl8169_rx_clear(tp);
7030
7031         rtl_pll_power_down(tp);
7032 }
7033
7034 static int rtl8169_close(struct net_device *dev)
7035 {
7036         struct rtl8169_private *tp = netdev_priv(dev);
7037         struct pci_dev *pdev = tp->pci_dev;
7038
7039         pm_runtime_get_sync(&pdev->dev);
7040
7041         /* Update counters before going down */
7042         rtl8169_update_counters(dev);
7043
7044         rtl_lock_work(tp);
7045         clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7046
7047         rtl8169_down(dev);
7048         rtl_unlock_work(tp);
7049
7050         cancel_work_sync(&tp->wk.work);
7051
7052         free_irq(pdev->irq, dev);
7053
7054         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7055                           tp->RxPhyAddr);
7056         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7057                           tp->TxPhyAddr);
7058         tp->TxDescArray = NULL;
7059         tp->RxDescArray = NULL;
7060
7061         pm_runtime_put_sync(&pdev->dev);
7062
7063         return 0;
7064 }
7065
7066 #ifdef CONFIG_NET_POLL_CONTROLLER
7067 static void rtl8169_netpoll(struct net_device *dev)
7068 {
7069         struct rtl8169_private *tp = netdev_priv(dev);
7070
7071         rtl8169_interrupt(tp->pci_dev->irq, dev);
7072 }
7073 #endif
7074
7075 static int rtl_open(struct net_device *dev)
7076 {
7077         struct rtl8169_private *tp = netdev_priv(dev);
7078         void __iomem *ioaddr = tp->mmio_addr;
7079         struct pci_dev *pdev = tp->pci_dev;
7080         int retval = -ENOMEM;
7081
7082         pm_runtime_get_sync(&pdev->dev);
7083
7084         /*
7085          * Rx and Tx descriptors needs 256 bytes alignment.
7086          * dma_alloc_coherent provides more.
7087          */
7088         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
7089                                              &tp->TxPhyAddr, GFP_KERNEL);
7090         if (!tp->TxDescArray)
7091                 goto err_pm_runtime_put;
7092
7093         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
7094                                              &tp->RxPhyAddr, GFP_KERNEL);
7095         if (!tp->RxDescArray)
7096                 goto err_free_tx_0;
7097
7098         retval = rtl8169_init_ring(dev);
7099         if (retval < 0)
7100                 goto err_free_rx_1;
7101
7102         INIT_WORK(&tp->wk.work, rtl_task);
7103
7104         smp_mb();
7105
7106         rtl_request_firmware(tp);
7107
7108         retval = request_irq(pdev->irq, rtl8169_interrupt,
7109                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
7110                              dev->name, dev);
7111         if (retval < 0)
7112                 goto err_release_fw_2;
7113
7114         rtl_lock_work(tp);
7115
7116         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7117
7118         napi_enable(&tp->napi);
7119
7120         rtl8169_init_phy(dev, tp);
7121
7122         __rtl8169_set_features(dev, dev->features);
7123
7124         rtl_pll_power_up(tp);
7125
7126         rtl_hw_start(dev);
7127
7128         netif_start_queue(dev);
7129
7130         rtl_unlock_work(tp);
7131
7132         tp->saved_wolopts = 0;
7133         pm_runtime_put_noidle(&pdev->dev);
7134
7135         rtl8169_check_link_status(dev, tp, ioaddr);
7136 out:
7137         return retval;
7138
7139 err_release_fw_2:
7140         rtl_release_firmware(tp);
7141         rtl8169_rx_clear(tp);
7142 err_free_rx_1:
7143         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7144                           tp->RxPhyAddr);
7145         tp->RxDescArray = NULL;
7146 err_free_tx_0:
7147         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7148                           tp->TxPhyAddr);
7149         tp->TxDescArray = NULL;
7150 err_pm_runtime_put:
7151         pm_runtime_put_noidle(&pdev->dev);
7152         goto out;
7153 }
7154
7155 static struct rtnl_link_stats64 *
7156 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
7157 {
7158         struct rtl8169_private *tp = netdev_priv(dev);
7159         void __iomem *ioaddr = tp->mmio_addr;
7160         unsigned int start;
7161
7162         if (netif_running(dev))
7163                 rtl8169_rx_missed(dev, ioaddr);
7164
7165         do {
7166                 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
7167                 stats->rx_packets = tp->rx_stats.packets;
7168                 stats->rx_bytes = tp->rx_stats.bytes;
7169         } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
7170
7171
7172         do {
7173                 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
7174                 stats->tx_packets = tp->tx_stats.packets;
7175                 stats->tx_bytes = tp->tx_stats.bytes;
7176         } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
7177
7178         stats->rx_dropped       = dev->stats.rx_dropped;
7179         stats->tx_dropped       = dev->stats.tx_dropped;
7180         stats->rx_length_errors = dev->stats.rx_length_errors;
7181         stats->rx_errors        = dev->stats.rx_errors;
7182         stats->rx_crc_errors    = dev->stats.rx_crc_errors;
7183         stats->rx_fifo_errors   = dev->stats.rx_fifo_errors;
7184         stats->rx_missed_errors = dev->stats.rx_missed_errors;
7185
7186         return stats;
7187 }
7188
7189 static void rtl8169_net_suspend(struct net_device *dev)
7190 {
7191         struct rtl8169_private *tp = netdev_priv(dev);
7192
7193         if (!netif_running(dev))
7194                 return;
7195
7196         netif_device_detach(dev);
7197         netif_stop_queue(dev);
7198
7199         rtl_lock_work(tp);
7200         napi_disable(&tp->napi);
7201         clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7202         rtl_unlock_work(tp);
7203
7204         rtl_pll_power_down(tp);
7205 }
7206
7207 #ifdef CONFIG_PM
7208
7209 static int rtl8169_suspend(struct device *device)
7210 {
7211         struct pci_dev *pdev = to_pci_dev(device);
7212         struct net_device *dev = pci_get_drvdata(pdev);
7213
7214         rtl8169_net_suspend(dev);
7215
7216         return 0;
7217 }
7218
7219 static void __rtl8169_resume(struct net_device *dev)
7220 {
7221         struct rtl8169_private *tp = netdev_priv(dev);
7222
7223         netif_device_attach(dev);
7224
7225         rtl_pll_power_up(tp);
7226
7227         rtl_lock_work(tp);
7228         napi_enable(&tp->napi);
7229         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7230         rtl_unlock_work(tp);
7231
7232         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7233 }
7234
7235 static int rtl8169_resume(struct device *device)
7236 {
7237         struct pci_dev *pdev = to_pci_dev(device);
7238         struct net_device *dev = pci_get_drvdata(pdev);
7239         struct rtl8169_private *tp = netdev_priv(dev);
7240
7241         rtl8169_init_phy(dev, tp);
7242
7243         if (netif_running(dev))
7244                 __rtl8169_resume(dev);
7245
7246         return 0;
7247 }
7248
7249 static int rtl8169_runtime_suspend(struct device *device)
7250 {
7251         struct pci_dev *pdev = to_pci_dev(device);
7252         struct net_device *dev = pci_get_drvdata(pdev);
7253         struct rtl8169_private *tp = netdev_priv(dev);
7254
7255         if (!tp->TxDescArray)
7256                 return 0;
7257
7258         rtl_lock_work(tp);
7259         tp->saved_wolopts = __rtl8169_get_wol(tp);
7260         __rtl8169_set_wol(tp, WAKE_ANY);
7261         rtl_unlock_work(tp);
7262
7263         rtl8169_net_suspend(dev);
7264
7265         return 0;
7266 }
7267
7268 static int rtl8169_runtime_resume(struct device *device)
7269 {
7270         struct pci_dev *pdev = to_pci_dev(device);
7271         struct net_device *dev = pci_get_drvdata(pdev);
7272         struct rtl8169_private *tp = netdev_priv(dev);
7273
7274         if (!tp->TxDescArray)
7275                 return 0;
7276
7277         rtl_lock_work(tp);
7278         __rtl8169_set_wol(tp, tp->saved_wolopts);
7279         tp->saved_wolopts = 0;
7280         rtl_unlock_work(tp);
7281
7282         rtl8169_init_phy(dev, tp);
7283
7284         __rtl8169_resume(dev);
7285
7286         return 0;
7287 }
7288
7289 static int rtl8169_runtime_idle(struct device *device)
7290 {
7291         struct pci_dev *pdev = to_pci_dev(device);
7292         struct net_device *dev = pci_get_drvdata(pdev);
7293         struct rtl8169_private *tp = netdev_priv(dev);
7294
7295         return tp->TxDescArray ? -EBUSY : 0;
7296 }
7297
7298 static const struct dev_pm_ops rtl8169_pm_ops = {
7299         .suspend                = rtl8169_suspend,
7300         .resume                 = rtl8169_resume,
7301         .freeze                 = rtl8169_suspend,
7302         .thaw                   = rtl8169_resume,
7303         .poweroff               = rtl8169_suspend,
7304         .restore                = rtl8169_resume,
7305         .runtime_suspend        = rtl8169_runtime_suspend,
7306         .runtime_resume         = rtl8169_runtime_resume,
7307         .runtime_idle           = rtl8169_runtime_idle,
7308 };
7309
7310 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
7311
7312 #else /* !CONFIG_PM */
7313
7314 #define RTL8169_PM_OPS  NULL
7315
7316 #endif /* !CONFIG_PM */
7317
7318 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
7319 {
7320         void __iomem *ioaddr = tp->mmio_addr;
7321
7322         /* WoL fails with 8168b when the receiver is disabled. */
7323         switch (tp->mac_version) {
7324         case RTL_GIGA_MAC_VER_11:
7325         case RTL_GIGA_MAC_VER_12:
7326         case RTL_GIGA_MAC_VER_17:
7327                 pci_clear_master(tp->pci_dev);
7328
7329                 RTL_W8(ChipCmd, CmdRxEnb);
7330                 /* PCI commit */
7331                 RTL_R8(ChipCmd);
7332                 break;
7333         default:
7334                 break;
7335         }
7336 }
7337
7338 static void rtl_shutdown(struct pci_dev *pdev)
7339 {
7340         struct net_device *dev = pci_get_drvdata(pdev);
7341         struct rtl8169_private *tp = netdev_priv(dev);
7342         struct device *d = &pdev->dev;
7343
7344         pm_runtime_get_sync(d);
7345
7346         rtl8169_net_suspend(dev);
7347
7348         /* Restore original MAC address */
7349         rtl_rar_set(tp, dev->perm_addr);
7350
7351         rtl8169_hw_reset(tp);
7352
7353         if (system_state == SYSTEM_POWER_OFF) {
7354                 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
7355                         rtl_wol_suspend_quirk(tp);
7356                         rtl_wol_shutdown_quirk(tp);
7357                 }
7358
7359                 pci_wake_from_d3(pdev, true);
7360                 pci_set_power_state(pdev, PCI_D3hot);
7361         }
7362
7363         pm_runtime_put_noidle(d);
7364 }
7365
7366 static void rtl_remove_one(struct pci_dev *pdev)
7367 {
7368         struct net_device *dev = pci_get_drvdata(pdev);
7369         struct rtl8169_private *tp = netdev_priv(dev);
7370
7371         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
7372             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
7373             tp->mac_version == RTL_GIGA_MAC_VER_31) {
7374                 rtl8168_driver_stop(tp);
7375         }
7376
7377         netif_napi_del(&tp->napi);
7378
7379         unregister_netdev(dev);
7380
7381         rtl_release_firmware(tp);
7382
7383         if (pci_dev_run_wake(pdev))
7384                 pm_runtime_get_noresume(&pdev->dev);
7385
7386         /* restore original MAC address */
7387         rtl_rar_set(tp, dev->perm_addr);
7388
7389         rtl_disable_msi(pdev, tp);
7390         rtl8169_release_board(pdev, dev, tp->mmio_addr);
7391 }
7392
7393 static const struct net_device_ops rtl_netdev_ops = {
7394         .ndo_open               = rtl_open,
7395         .ndo_stop               = rtl8169_close,
7396         .ndo_get_stats64        = rtl8169_get_stats64,
7397         .ndo_start_xmit         = rtl8169_start_xmit,
7398         .ndo_tx_timeout         = rtl8169_tx_timeout,
7399         .ndo_validate_addr      = eth_validate_addr,
7400         .ndo_change_mtu         = rtl8169_change_mtu,
7401         .ndo_fix_features       = rtl8169_fix_features,
7402         .ndo_set_features       = rtl8169_set_features,
7403         .ndo_set_mac_address    = rtl_set_mac_address,
7404         .ndo_do_ioctl           = rtl8169_ioctl,
7405         .ndo_set_rx_mode        = rtl_set_rx_mode,
7406 #ifdef CONFIG_NET_POLL_CONTROLLER
7407         .ndo_poll_controller    = rtl8169_netpoll,
7408 #endif
7409
7410 };
7411
7412 static const struct rtl_cfg_info {
7413         void (*hw_start)(struct net_device *);
7414         unsigned int region;
7415         unsigned int align;
7416         u16 event_slow;
7417         unsigned features;
7418         u8 default_ver;
7419 } rtl_cfg_infos [] = {
7420         [RTL_CFG_0] = {
7421                 .hw_start       = rtl_hw_start_8169,
7422                 .region         = 1,
7423                 .align          = 0,
7424                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
7425                 .features       = RTL_FEATURE_GMII,
7426                 .default_ver    = RTL_GIGA_MAC_VER_01,
7427         },
7428         [RTL_CFG_1] = {
7429                 .hw_start       = rtl_hw_start_8168,
7430                 .region         = 2,
7431                 .align          = 8,
7432                 .event_slow     = SYSErr | LinkChg | RxOverflow,
7433                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
7434                 .default_ver    = RTL_GIGA_MAC_VER_11,
7435         },
7436         [RTL_CFG_2] = {
7437                 .hw_start       = rtl_hw_start_8101,
7438                 .region         = 2,
7439                 .align          = 8,
7440                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
7441                                   PCSTimeout,
7442                 .features       = RTL_FEATURE_MSI,
7443                 .default_ver    = RTL_GIGA_MAC_VER_13,
7444         }
7445 };
7446
7447 /* Cfg9346_Unlock assumed. */
7448 static unsigned rtl_try_msi(struct rtl8169_private *tp,
7449                             const struct rtl_cfg_info *cfg)
7450 {
7451         void __iomem *ioaddr = tp->mmio_addr;
7452         unsigned msi = 0;
7453         u8 cfg2;
7454
7455         cfg2 = RTL_R8(Config2) & ~MSIEnable;
7456         if (cfg->features & RTL_FEATURE_MSI) {
7457                 if (pci_enable_msi(tp->pci_dev)) {
7458                         netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
7459                 } else {
7460                         cfg2 |= MSIEnable;
7461                         msi = RTL_FEATURE_MSI;
7462                 }
7463         }
7464         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
7465                 RTL_W8(Config2, cfg2);
7466         return msi;
7467 }
7468
7469 DECLARE_RTL_COND(rtl_link_list_ready_cond)
7470 {
7471         void __iomem *ioaddr = tp->mmio_addr;
7472
7473         return RTL_R8(MCU) & LINK_LIST_RDY;
7474 }
7475
7476 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
7477 {
7478         void __iomem *ioaddr = tp->mmio_addr;
7479
7480         return (RTL_R8(MCU) & RXTX_EMPTY) == RXTX_EMPTY;
7481 }
7482
7483 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
7484 {
7485         void __iomem *ioaddr = tp->mmio_addr;
7486         u32 data;
7487
7488         tp->ocp_base = OCP_STD_PHY_BASE;
7489
7490         RTL_W32(MISC, RTL_R32(MISC) | RXDV_GATED_EN);
7491
7492         if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
7493                 return;
7494
7495         if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
7496                 return;
7497
7498         RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
7499         msleep(1);
7500         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
7501
7502         data = r8168_mac_ocp_read(tp, 0xe8de);
7503         data &= ~(1 << 14);
7504         r8168_mac_ocp_write(tp, 0xe8de, data);
7505
7506         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7507                 return;
7508
7509         data = r8168_mac_ocp_read(tp, 0xe8de);
7510         data |= (1 << 15);
7511         r8168_mac_ocp_write(tp, 0xe8de, data);
7512
7513         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7514                 return;
7515 }
7516
7517 static void rtl_hw_initialize(struct rtl8169_private *tp)
7518 {
7519         switch (tp->mac_version) {
7520         case RTL_GIGA_MAC_VER_40:
7521         case RTL_GIGA_MAC_VER_41:
7522         case RTL_GIGA_MAC_VER_42:
7523         case RTL_GIGA_MAC_VER_43:
7524         case RTL_GIGA_MAC_VER_44:
7525         case RTL_GIGA_MAC_VER_45:
7526         case RTL_GIGA_MAC_VER_46:
7527         case RTL_GIGA_MAC_VER_47:
7528         case RTL_GIGA_MAC_VER_48:
7529                 rtl_hw_init_8168g(tp);
7530                 break;
7531
7532         default:
7533                 break;
7534         }
7535 }
7536
7537 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7538 {
7539         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
7540         const unsigned int region = cfg->region;
7541         struct rtl8169_private *tp;
7542         struct mii_if_info *mii;
7543         struct net_device *dev;
7544         void __iomem *ioaddr;
7545         int chipset, i;
7546         int rc;
7547
7548         if (netif_msg_drv(&debug)) {
7549                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
7550                        MODULENAME, RTL8169_VERSION);
7551         }
7552
7553         dev = alloc_etherdev(sizeof (*tp));
7554         if (!dev) {
7555                 rc = -ENOMEM;
7556                 goto out;
7557         }
7558
7559         SET_NETDEV_DEV(dev, &pdev->dev);
7560         dev->netdev_ops = &rtl_netdev_ops;
7561         tp = netdev_priv(dev);
7562         tp->dev = dev;
7563         tp->pci_dev = pdev;
7564         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
7565
7566         mii = &tp->mii;
7567         mii->dev = dev;
7568         mii->mdio_read = rtl_mdio_read;
7569         mii->mdio_write = rtl_mdio_write;
7570         mii->phy_id_mask = 0x1f;
7571         mii->reg_num_mask = 0x1f;
7572         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
7573
7574         /* disable ASPM completely as that cause random device stop working
7575          * problems as well as full system hangs for some PCIe devices users */
7576         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
7577                                      PCIE_LINK_STATE_CLKPM);
7578
7579         /* enable device (incl. PCI PM wakeup and hotplug setup) */
7580         rc = pci_enable_device(pdev);
7581         if (rc < 0) {
7582                 netif_err(tp, probe, dev, "enable failure\n");
7583                 goto err_out_free_dev_1;
7584         }
7585
7586         if (pci_set_mwi(pdev) < 0)
7587                 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
7588
7589         /* make sure PCI base addr 1 is MMIO */
7590         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
7591                 netif_err(tp, probe, dev,
7592                           "region #%d not an MMIO resource, aborting\n",
7593                           region);
7594                 rc = -ENODEV;
7595                 goto err_out_mwi_2;
7596         }
7597
7598         /* check for weird/broken PCI region reporting */
7599         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
7600                 netif_err(tp, probe, dev,
7601                           "Invalid PCI region size(s), aborting\n");
7602                 rc = -ENODEV;
7603                 goto err_out_mwi_2;
7604         }
7605
7606         rc = pci_request_regions(pdev, MODULENAME);
7607         if (rc < 0) {
7608                 netif_err(tp, probe, dev, "could not request regions\n");
7609                 goto err_out_mwi_2;
7610         }
7611
7612         tp->cp_cmd = 0;
7613
7614         if ((sizeof(dma_addr_t) > 4) &&
7615             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
7616                 tp->cp_cmd |= PCIDAC;
7617                 dev->features |= NETIF_F_HIGHDMA;
7618         } else {
7619                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7620                 if (rc < 0) {
7621                         netif_err(tp, probe, dev, "DMA configuration failed\n");
7622                         goto err_out_free_res_3;
7623                 }
7624         }
7625
7626         /* ioremap MMIO region */
7627         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
7628         if (!ioaddr) {
7629                 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
7630                 rc = -EIO;
7631                 goto err_out_free_res_3;
7632         }
7633         tp->mmio_addr = ioaddr;
7634
7635         if (!pci_is_pcie(pdev))
7636                 netif_info(tp, probe, dev, "not PCI Express\n");
7637
7638         /* Identify chip attached to board */
7639         rtl8169_get_mac_version(tp, dev, cfg->default_ver);
7640
7641         rtl_init_rxcfg(tp);
7642
7643         rtl_irq_disable(tp);
7644
7645         rtl_hw_initialize(tp);
7646
7647         rtl_hw_reset(tp);
7648
7649         rtl_ack_events(tp, 0xffff);
7650
7651         pci_set_master(pdev);
7652
7653         rtl_init_mdio_ops(tp);
7654         rtl_init_pll_power_ops(tp);
7655         rtl_init_jumbo_ops(tp);
7656         rtl_init_csi_ops(tp);
7657
7658         rtl8169_print_mac_version(tp);
7659
7660         chipset = tp->mac_version;
7661         tp->txd_version = rtl_chip_infos[chipset].txd_version;
7662
7663         RTL_W8(Cfg9346, Cfg9346_Unlock);
7664         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
7665         RTL_W8(Config5, RTL_R8(Config5) & (BWF | MWF | UWF | LanWake | PMEStatus));
7666         switch (tp->mac_version) {
7667         case RTL_GIGA_MAC_VER_45:
7668         case RTL_GIGA_MAC_VER_46:
7669                 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
7670                         tp->features |= RTL_FEATURE_WOL;
7671                 if ((RTL_R8(Config3) & LinkUp) != 0)
7672                         tp->features |= RTL_FEATURE_WOL;
7673                 break;
7674         default:
7675                 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
7676                         tp->features |= RTL_FEATURE_WOL;
7677                 break;
7678         }
7679         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
7680                 tp->features |= RTL_FEATURE_WOL;
7681         tp->features |= rtl_try_msi(tp, cfg);
7682         RTL_W8(Cfg9346, Cfg9346_Lock);
7683
7684         if (rtl_tbi_enabled(tp)) {
7685                 tp->set_speed = rtl8169_set_speed_tbi;
7686                 tp->get_settings = rtl8169_gset_tbi;
7687                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
7688                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
7689                 tp->link_ok = rtl8169_tbi_link_ok;
7690                 tp->do_ioctl = rtl_tbi_ioctl;
7691         } else {
7692                 tp->set_speed = rtl8169_set_speed_xmii;
7693                 tp->get_settings = rtl8169_gset_xmii;
7694                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
7695                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
7696                 tp->link_ok = rtl8169_xmii_link_ok;
7697                 tp->do_ioctl = rtl_xmii_ioctl;
7698         }
7699
7700         mutex_init(&tp->wk.mutex);
7701         u64_stats_init(&tp->rx_stats.syncp);
7702         u64_stats_init(&tp->tx_stats.syncp);
7703
7704         /* Get MAC address */
7705         if (tp->mac_version == RTL_GIGA_MAC_VER_45 ||
7706             tp->mac_version == RTL_GIGA_MAC_VER_46 ||
7707             tp->mac_version == RTL_GIGA_MAC_VER_47 ||
7708             tp->mac_version == RTL_GIGA_MAC_VER_48) {
7709                 u16 mac_addr[3];
7710
7711                 *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);
7712                 *(u16 *)&mac_addr[2] = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC);
7713
7714                 if (is_valid_ether_addr((u8 *)mac_addr))
7715                         rtl_rar_set(tp, (u8 *)mac_addr);
7716         }
7717         for (i = 0; i < ETH_ALEN; i++)
7718                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
7719
7720         dev->ethtool_ops = &rtl8169_ethtool_ops;
7721         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
7722
7723         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
7724
7725         /* don't enable SG, IP_CSUM and TSO by default - it might not work
7726          * properly for all devices */
7727         dev->features |= NETIF_F_RXCSUM |
7728                 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
7729
7730         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7731                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
7732                 NETIF_F_HW_VLAN_CTAG_RX;
7733         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7734                 NETIF_F_HIGHDMA;
7735
7736         tp->cp_cmd |= RxChkSum | RxVlan;
7737
7738         /*
7739          * Pretend we are using VLANs; This bypasses a nasty bug where
7740          * Interrupts stop flowing on high load on 8110SCd controllers.
7741          */
7742         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
7743                 /* Disallow toggling */
7744                 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
7745
7746         if (tp->txd_version == RTL_TD_0)
7747                 tp->tso_csum = rtl8169_tso_csum_v1;
7748         else if (tp->txd_version == RTL_TD_1) {
7749                 tp->tso_csum = rtl8169_tso_csum_v2;
7750                 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
7751         } else
7752                 WARN_ON_ONCE(1);
7753
7754         dev->hw_features |= NETIF_F_RXALL;
7755         dev->hw_features |= NETIF_F_RXFCS;
7756
7757         tp->hw_start = cfg->hw_start;
7758         tp->event_slow = cfg->event_slow;
7759
7760         tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
7761                 ~(RxBOVF | RxFOVF) : ~0;
7762
7763         init_timer(&tp->timer);
7764         tp->timer.data = (unsigned long) dev;
7765         tp->timer.function = rtl8169_phy_timer;
7766
7767         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
7768
7769         rc = register_netdev(dev);
7770         if (rc < 0)
7771                 goto err_out_msi_4;
7772
7773         pci_set_drvdata(pdev, dev);
7774
7775         netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
7776                    rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
7777                    (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
7778         if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
7779                 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
7780                            "tx checksumming: %s]\n",
7781                            rtl_chip_infos[chipset].jumbo_max,
7782                            rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
7783         }
7784
7785         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
7786             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
7787             tp->mac_version == RTL_GIGA_MAC_VER_31) {
7788                 rtl8168_driver_start(tp);
7789         }
7790
7791         device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
7792
7793         if (pci_dev_run_wake(pdev))
7794                 pm_runtime_put_noidle(&pdev->dev);
7795
7796         netif_carrier_off(dev);
7797
7798 out:
7799         return rc;
7800
7801 err_out_msi_4:
7802         netif_napi_del(&tp->napi);
7803         rtl_disable_msi(pdev, tp);
7804         iounmap(ioaddr);
7805 err_out_free_res_3:
7806         pci_release_regions(pdev);
7807 err_out_mwi_2:
7808         pci_clear_mwi(pdev);
7809         pci_disable_device(pdev);
7810 err_out_free_dev_1:
7811         free_netdev(dev);
7812         goto out;
7813 }
7814
7815 static struct pci_driver rtl8169_pci_driver = {
7816         .name           = MODULENAME,
7817         .id_table       = rtl8169_pci_tbl,
7818         .probe          = rtl_init_one,
7819         .remove         = rtl_remove_one,
7820         .shutdown       = rtl_shutdown,
7821         .driver.pm      = RTL8169_PM_OPS,
7822 };
7823
7824 module_pci_driver(rtl8169_pci_driver);